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Arria V GT FPGA Development Kit User Guide

1. 1 1 SO DWAfe slve E __ eee bes 1 1 Quartus Il Software bees E a bees IER 1 1 Arria V GT FPGA Development Kit Installer 1 2 Chapter 2 Getting Started VOU Begin iss petet o 2 1 Inspect the Boards dare twas eis epe e eie e epe oe d ERE pede lectos 2 1 Reterences esos b Rhe RUP EUR RE eher ebrgug been errare E adhe need ween bah 2 2 Chapter 3 Software Installation Installing the Quartus II Subscription Edition Software 3 1 Licensing Considerations 3 1 Installing the Development 3 3 Installing the USB Blaster Driver 3 4 Chapter 4 Development Board Setup Setting Up the Board eei zer Re ee der bes peer page pork eed eee aces 4 1 Factory Default Switch and Jumper Settings 4 2 Chapter 5 Board Update Portal Connecting to the Board Update Portal Web Page 5 1 Using the Board Update Portal to Update User Designs 5 2 Chapter 6 Board Test System Preparing the Boardi d rue Ded UE 6 2 Running the Board Test System
2. 101 Innovation Drive San Jose CA 95134 www altera com UG 01124 1 0 Arria V GT FPGA Development Kit User Guide gt lt Feedback Subscribe 2012 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks zi Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide N DTE SYN Contents Chapter 1 About This Kit Kit Features ea bed tc deed Paes Phe ee ae ey 1 1 Hardwabe ic
3. Detected errors 0 15 Inserted errors 0 Insert Error Clear Word error rate 3 527290e 10 Tx MBps 3199 1948 Rx MBps 3199 5588 gt You must have the loopback HSMB installed on the HSMC Port B connector that you are testing for this test to work correctly The following sections describe the controls on the HSMB FMC tab Status The Status control displays the following status information during the loopback test m PLL lock Shows the PLL locked or unlocked state Channel lock Shows the channel locked or unlocked state When locked all lanes are word aligned and channel bonded Pattern sync Shows the pattern synced or not synced state The pattern is considered synced when the start of the data sequence is detected November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 16 Chapter 6 Board Test System Using the Board Test System Port FPGA2 The Port FPGA2 control allows you to specify which interface to test The following port tests are available XCVR x4 HSMB design run at 6 4 Gbps m CMOS x3 HSMB design run at 25 Mbps m FMC XCVR x4 FMC design run at 6 4 Gbps m CMOS x80 FMC design run at 25 Mbps PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface The following settings are available for analysis m Serial Loopback Routes
4. Directory Name board_design_files Description of Contents Contains schematic layout assembly and bill of material board design files Use these files as a starting point for a new prototype board design demos Contains demonstration applications if present documents Contains the kit documentation examples Contains the sample design files for the Arria V GT FPGA Development Kit factory_recovery Contains the original data programmed onto the board before shipment Use this data to restore the board with its original factory contents November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 3 4 Chapter 3 Software Installation Installing the USB Blaster II Driver Installing the USB Blaster Driver The Arria V GT FPGA development board includes integrated On Board USB Blaster II circuitry for FPGA programming However for the host computer and board to communicate you must install the USB Blaster II driver on the host computer T Installation instructions for the USB Blaster II driver for your operating system are available on the Altera website On the Altera Programming Cable Driver Information page of the Altera website locate the table entry for your configuration and click the link to access the instructions St For USB Blaster II configuration details refer to the On Board USB Blaster II page Arria V GT FPGA Development Kit November 2012 Altera Corporation Use
5. 6 22 Chapter 6 Board Test System Using the Board Test System Port FPGA2 The Port 2 control allows you to specify which interface to test The following port test is available m SMA GXB R9 design run at 10 Gbps m Bull s Eye GXB 115 design run at 10 Gbps PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface The following settings are available for analysis m Serial Loopback Routes signals between the receiver and the transmitter Enter the following values to enable the serial loopbacks 0 high speed serial transceiver signals to loopback on the board 1 serial loopback 2 reverse serial loopback pre CDR 4 reverse serial loopback post CDR VOD Specifies the voltage output differential of the transmitter buffer Pre emphasis tap m Pre Specifies the amount of pre emphasis on the pre tap of the transmitter buffer m First post 5pecifies the amount of pre emphasis on the first post tap of the transmitter buffer m Second post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer m Equalizer Specifies the setting for the receiver equalizer m DC gain Specifies the DC portion of the receiver equalizer Data Type The Data type control specifies the type of data contained in the transactions The following data types are available for analysis m PRBS7 Selects pseudo random 7 bit sequences PRB
6. a parallel flash loader PFL megafunction When the board powers up the PFL reads a design from flash memory and configures the FPGA The Load Selector SW5 3 controls which design to load When the switch is in the on factory position the PFL loads the design from the factory portion of flash memory 57 The kit includes a MAX design which contains the MAX II PFL megafunction The design resides in the install dir gt kits arriaVGT_5agtfd7kf40_fpga examples max2 directory When configuration is complete the Config Done LED D16 illuminates signaling that the Arria V GT device configured successfully St For more information about the PFL megafunction refer to Parallel Flash Loader Megafunction User Guide November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 4 2 Chapter 4 Development Board Setup Factory Default Switch and Jumper Settings Factory Default Switch and Jumper Settings This section shows the factory switch and jumper settings for the Arria V GT FPGA development board Figure 4 1 shows the switch and jumper locations and the default position of each switch and jumper on the top side of the board Figure 4 1 Switch Locations and Default Settings on the Board Top of Lg USER_DIP1 USER_DIP2 sw2 SW3 NOM 5 55 a ns ii FAN installed i
7. not in JTAG chain ON OFF logical 1 Include HCMC Port B in the JTAG chain Switch 4 has the following options ON logical 0 FMC connector not in JTAG 4 FMC_JTAG_EN chain ON m OFF logical 1 Include FMC connector in the JTAG chain 4 Set DIP switch bank SW7 to match Table 4 4 and Figure 4 2 Table 4 4 SW7 PCle DIP Switch Settings Switch ee Function plat Switch 1 has the following options 1 PCIE PRSNT2n x1 ON 0 x1 presence detect is enabled ON m OFF 1 1 presence detect is disabled Switch 2 has the following options 2 PCIE PRSNT2n 4 ON 0 x4 presence detect is enabled ON m OFF 1 x4 presence detect is disabled Switch 3 has the following options 3 PCIE PRSNT2n x8 ON 0 x8 presence detect is enabled ON m OFF 1 x8 presence detect is disabled 4 OFF Arria V GT FPGA Development Kit User Guide November 2012 Altera Corporation Chapter 4 Development Board Setup 4 5 Factory Default Switch and Jumper Settings 5 Set DIP switch bank SW8 to match Table 4 5 and Figure 4 2 Table 4 5 SW8 FPGA1 MSEL Dip Switch Settings 7 Switch en Function uie Switch 1 has the following options 1 FPGA1 MSEL 1 When ON a logic 0 is selected ON m When OFF a logic 1 is selected Switch 2 has the following options 2 FPGA1 MSEL 2 When a logic 0 is selected OFF m When OFF a logic 1 is selected 3 ON Switch 4 has the following opt
8. 14 npa a Pee a ae ae ee ETT 6 14 The HSMB FMC 1 7 7 6 15 Status sepeser Scars p AUR 6 15 Port EPGA2 i e RE EE Rubr Rt a dees ea NR 4 6 16 PMA Seting erer e rer rv E Reo a e e ees va aer Y RE Re 6 16 Data 6 16 Error Control Re rere ea pA ea p APA Ade 6 17 Loopback i 6 17 Start eas eee tee aea 6 17 OP tices eis ate 6 17 The SDI Bull s Eye ne betes bee abode ERE d rper 6 18 Status 6 18 POrt EPCQIA2 Grousses ate ba aes Vand 6 19 Setting 6 19 Data C 6 19 Error 6 20 Loopback s euu texe Oe ea edel eee eere PER 6 20 Start bead eh bad EDU Rd 6 20 EE 6 20 The SMA aw Ca CREE 6 21 Status 0g yx eae du ie ter Ee REA 6 21 Port EPGA2 poset osti Eiei bU R
9. 5 Restoring the MAX II CPLD to the Factory Settings Because two FPGA devices are hard wired in the JTAG chain and it is possible to configure Nios II CPU devices on both FPGAs simultaneously nios2 flash programmer commands may require the device lt device index gt and instance lt instance gt arguments For more information about the nios2 flash programmer utility refer to the Nios II Flash Programmer User Guide To ensure that you have the most up to date factory restore files and information about this product refer to the Arria GT FPGA Development Kit page of the Altera website Restoring the MAX CPLD to the Factory Settings This section describes how to restore the original factory contents to the MAX II CPLD on the FPGA development board Make sure you have the Nios II EDS installed and perform the following instructions 1 Setthe board switches to the factory default settings described in Factory Default Switch and Jumper Settings on page 4 2 2 Launch the Quartus II Programmer 3 Click Auto Detect 4 Click Add File and select lt install dir NkitsNarriaV GT 5agtfd7kf40 fpgaNfactory recoveryNmax2 pof 5 Turn on the Program Configure option for the added file 6 Click Start to download the selected configuration file to the MAX II CPLD Configuration is complete when the progress bar reaches 100 To ensure that you have the most up to date factory restore files and information about this product r
10. CMOS ports Figure 6 5 HSMA Tab Board Test System E lal xl Configure Help About c 2 7 JR 1 DDRSEPGAZ 7 5 2 5 5 PLL lock locked Channel lock locked Pattern sync synced Control Port FPGA1 XCVR x4 PMA Setting LVDS x17 CMOS type 34 control Detected errors 0 515 Inserted errors 0 Insert Error Clear Word error rate 1 401251e 09 Start Stop MBps 5000 0528 MBps 5000 0536 57 You must have the loopback HSMA installed on the HSMC Port A connector that you are testing for this test to work correctly The following sections describe the controls on the HSMA tab Status The Status control displays the following status information during the loopback test m PLL lock Shows the PLL locked or unlocked state Channel lock Shows the channel locked or unlocked state When locked all lanes are word aligned and channel bonded m Pattern sync Shows the pattern synced or not synced state The pattern is considered synced when the start of the data sequence is detected November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 10 Chapter 6 Board Test System Using the Board Test System Port FPGA1 The Port 1 control all
11. D16 does not illuminate continue to step 4 to load the FPGA with a flash writing design 4 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 27 for more information 5 Click Add File and select install dir kits arriaVGT_5agtfd7kf40_fpga factory_recovery a5gtd7k3_fpga_bup sof 6 Turn on the Program Configure option for the added file 7 Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The flash device is ready for programming 8 On the Windows Start menu click All Programs gt Altera gt Nios EDS gt Nios II Command Shell 9 In the Nios command shell navigate to the lt install dir gt kits arriaVGT_5agtfd7kf40_fpga factory_recovery directory or to the directory of the flash files you created in Creating Flash Files Using the Nios II EDS on page 2 and type the following Nios II EDS command gt Because two FPGA devices are hardwired in the JTAG chain and it is possible to configure Nios II CPU devices on both FPGAs simultaneously nios2 flash programmer commands may require the device lt device index gt and instance lt instance gt arguments nios2 flash programmer d 1 i 0 base 0x0 lt yourfile gt hw flash 10 After programming completes if you have a software file to program type t
12. down set the Load Selector SW5 3 to the on factory position 2 Attach the Ethernet cable from the board to your LAN 3 Power up the board The board connects to the LAN s gateway router and obtains an IP address The LCD on the board displays the IP address November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 5 2 Chapter 5 Board Update Portal Using the Board Update Portal to Update User Designs 4 Launch a web browser on a PC that is connected to the same network and enter the IP address from the LCD into the browser address bar The Board Update Portal web page appears in the browser gt You can click Arria V GT FPGA Development Kit on the Board Update Portal web page to access the kit s home page for documentation updates and additional new designs Te You can also navigate directly to the Arria V GT FPGA Development Kit page to determine if you have the latest kit software Using the Board Update Portal to Update User Designs The Board Update Portal allows you to write new designs to the user hardware 1 and user hardware 2 portion of flash memory Designs must be in the Nios II Flash Programmer File flash format gt Design files available from the Arria V GT FPGA Development Kit page include lash files You can also create flash files from your own custom design Refer to Preparing Design Files for Flash Programming on page 2 for information about preparing your own design
13. for upload To upload a design over the network into the user portion of flash memory on your board perform the following steps 1 Perform the steps in Connecting to the Board Update Portal Web Page to access the Board Update Portal web page 2 In the Hardware File Name field specify the flash file that you either downloaded from the Altera website or created on your own If there is a software component to the design specify it in the same manner using the Software File Name field otherwise leave the Software File Name field blank 3 Click Upload The progress bar indicates the percent complete The file takes about 20 seconds to upload 4 Toconfigure the FPGA with the new design after the flash memory upload process is complete set the Load Selector SW5 3 to the off user position and power cycle the board SW1 7 As long as you don t overwrite the factory image in the flash memory device you can continue to use the Board Update Portal to write new designs to the user hardware 1 and or user hardware 2 portion of flash memory If you do overwrite the factory image you can restore it by following the instructions in Restoring the Flash Device to the Factory Settings on page A 4 Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide N 6 Board Test System The kit includes a design example and an application called the Board Test System BTS to test the functionality of the
14. program the flash memory device so that your own design loads from flash memory into the FPGA on power up This appendix describes the preprogrammed contents of the common flash interface CFI flash memory device on the Arria V GT FPGA development board and the Nios II EDS tools involved with reprogramming the user portions of the flash memory device The Arria V GT FPGA development board ships with the CFI flash device preprogrammed with a default factory FPGA configuration for running the Board Update Portal design example and a default user configuration for running the Board Test System demonstration There are several other factory software files written to the CFI flash device to support the Board Update Portal These software files were created using the Nios II EDS just as the hardware design was created using the Quartus II software For more information about Altera development tools refer to the Design Software page of the Altera website CFI Flash Memory Map Table 1 shows the default memory contents of the 1 Gb CFI flash device For the Board Update Portal to run correctly and update designs in the user memory this memory map must not be altered CAUTION Table A 1 Byte Address Flash Memory Map Block Description Size KB Address Range Unused 128 0 07 0000 0x07FF FFFF User software 46 080 0x052E 0000 0x07FD FFFF Factory software 8 192 Ox04AE 0000 0x052D FFFF Zipfs html
15. the 51570 51571 515338 and the Arria V GT FPGA development board s clocking circuitry and clock input pins refer to the Arria V GT FPGA Development Board Reference Manual The Clock Control communicates with the MAX II device on the board through the JTAG bus The Si570 and Si571 X7 X2 programmable oscillators are connected to the MAX II device through a 2 wire serial bus Figure 6 11 shows the Clock Control Figure 6 11 The Clock Control Disable CLKO 100 00 Disable CLKO CLK1 CLK1 100 00 Disable CLK1 CLk2 CLK2 100 00 Disable CLK2 CLK3 100 00 Disable CLK3 Default Set New Frequency The following sections describe the Clock Control controls Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 27 Configuring the FPGA Using the Quartus Programmer Registers The Registers control shows the current values from the 51570 51571 and Si5338A registers Frequency MHz This control allows you to change the frequency of the 51570 Si571 but you cannot read the value of this clock via the GUI However the Si5338A allows you to read the output frequencies by clicking read which may take time to read You may also change the output frequency to any of the clocks from 0 16 to 710 MHz Once you power cycle the board your settings will be reset to the default valu
16. web content 8 192 0x042E 0000 0x04AD FFFF User hardware 2 22 784 0x02CA 0000 0x042D FFFF User hardware 1 22 784 0x0166 0000 0x02C9 FFFF Factory hardware 22 784 0x0002 0000 0x0165 FFFF PFL option bits 32 0x0001 8000 0x0001 FFFF Board information 32 0x0001 0000 0x0001 7FFF Ethernet option bits 32 0x0000 8000 0x0000 FFFF User design reset vector 32 0x0000 0000 0x0000 7FFF Altera recommends that you do not overwrite the factory hardware and factory software images unless you are an expert with the Altera tools If you unintentionally overwrite the factory hardware or factory software image refer to Restoring the Flash Device to the Factory Settings on page 4 November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide A 2 Appendix A Programming the Flash Memory Device Preparing Design Files for Flash Programming Preparing Design Files for Flash Programming You can obtain designs containing prepared flash files from the Arria V GT FPGA Development Kit page of the Altera website or create flash files from your own custom design The Nios II EDS sof2flash command line utility converts your Quartus II compiled into the flash format necessary for the flash device Similarly the Nios II EDS elf2flash command line utility converts your compiled and linked Executable and Linking Format File elf software design to flash After your design files are in the flash format use the Board U
17. 012 Altera Corporation User Guide Chapter 6 Board Test System 6 17 Using the Board Test System m LF HSMB lowest frequency divide by 32 data pattern Le Settings HF1 HF2 HF3 LF are for transmit observation only The following data types are available for CMOS analysis PRBS3 Selects pseudo random 3 bit sequences for HSMB x3 CMOS PRBS80 Selects pseudo random 80 bit sequences for FMC x80 CMOS Error Control This control displays data errors detected during analysis and allows you to insert errors m Detected errors Displays the number of data errors detected in the hardware m Inserted errors Displays the number of errors inserted into the transmit data stream Insert Error Inserts a one word error into the transmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros m Word error rate Detected word errors total received words Loopback These controls display current transaction performance analysis information collected since you last clicked Start m TXand RX performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve m Tx MBps and Rx MBps Show the number of bytes of data analyzed per second Start The Start control initiates transaction performance analysis Stop The Stop contr
18. Arria VGT FPGA development board and supported daughtercards The application provides an easy to use interface to alter functional settings and observe the results You can use the BTS to test board components modify functional parameters observe performance and measure power usage While using the application you reconfigure the FPGA several times with test designs specific to the functionality you are testing The BTS is also useful as a reference for designing systems To install the application follow the steps in Installing the Development Kit on page 3 3 The Board Test System GUI communicates over the JTAG bus to a test design running in the Arria V GT device Figure 6 1 shows the initial GUI for a board that is in the factory configuration Figure 6 1 Board Test System Graphical User Interface Board Test System H lol x Configure Help About CIA nn gd EBEN JDR3 FPGA GPIO FPGA1 Flash Hsm Board information Board Name Arria V GT FPGA Development Kit Board Board P N PN 6XX 44164R Serial number SATPCIE000000 Factory test version Test Software Version 12 0 2 0 MAX II ver a 00 07 ed 23 00 01 II registers Detected the Flash GPIO Project November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 2 Ls Chapter 6 Board Test System Preparing the Board Several designs are provided to test the major board feat
19. As dialog box For GUI elements capitalization matches Letters the GUI Indicates directory names project names disk drive names file names file name bold type extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines Indicates variables For example n 1 italic type Variable names are enclosed in angle brackets For example file name and project name pof file Indicate keyboard keys and menu names For example the Delete key and the Options menu Initial Capital Letters November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide Info 2 Additional Information Typographic Conventions Visual Cue Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SU
20. BDESIGN and logic function names for example TRI An angled arrow instructs you to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b c and so on such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important e The hand points to information that requires special attention The question mark directs you to a software help system with related information Se The feet direct you to another document or website with related information Eb H The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents WARNING gt The feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document Arria V GT FPGA Development Kit User Guide November 2012 Altera Corporation
21. Corporation Arria V GT FPGA Development Kit User Guide Chapter 6 Board Test System Using the Board Test System 2 On the Configure menu click the configure command that corresponds to the functionality you wish to test The design begins running in the FPGA and the corresponding GUI application tabs that interface with the design are now enabled 57 If you use the Quartus II Programmer for configuration rather than the Board Test System GUI you may need to restart the GUI The System Info Tab The System Info tab shows the board s current configuration Figure 6 1 on page 6 1 shows the System Info tab The tab displays the contents of the MAX II registers the JTAG chain the board s MAC address and other details stored on the board The following sections describe the controls on the System Info tab Board Information The Board information controls display static information about your board m Board Name lIndicates the official name of the board given by the Board Test System m Board P N Indicates the part number of the board m Serial number Indicates the serial number of the board m Factory test version Indicates the version of the Board Test System currently running on the board m MAX ver Indicates the version of MAX II code currently running on the board The MAX II code resides in the lt install dir NkitsNarriaV GT 5agtfd7kf40 fpgaNexamples directory Newer revisions of this code might be av
22. EN E Rr Pad ee RE EAS 6 22 Setting eer 6 22 Data Type M 6 22 Error Control 5 42 sedan os a eh eis ee ee bee eee 6 23 P PI 6 23 DIOP nmm 6 23 PEE 6 23 The Power Montor Ba DE EA eX Ceu Vw A dte 6 23 General Information 6 24 Power 1 2 6 25 Power 6 25 Graph Settings ____________________ 6 25 Reset casera RR ee eS 6 25 Calculating Power tics cr bebe ee eoe vex Ao ang del e dae 6 25 The Clock Control EECOGUPENGO REG Ra RR Re 6 26 Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Contents rrj pase Cnm 6 27 Frequency MHZ 2 owsiane DG PET GU ECKE EE 6 27 Disabler 1 293 wea ee Pa 6 27 Detail bae hack Hea Hi HESS RR Ri ES 6 27 set New Frequency seed estida re KART e 6 27 Configuring the FPGA Using the Quartus Programmer 6 27 Samtec High speed Bull s E
23. FF FFFF Power Monitor 9000 0000 ve x 0000 0000 89630089 FFFF0001 94 0089 0004 0000 0010 08890889 00890089 80898089 00890089 0000 0020 00520051 00010059 000A0000 00000001 0000 0030 00000000 00170000 00850020 00090095 0000 0040 000A000A 00010000 00020002 00180000 0000 0050 00000001 0000000A 00030002 00800000 0000 0060 00 0000 00000003 00000002 00000000 0000 0070 FFFFO0000 FFFFFFFF FFFFFFFF FFFFFFFF 0x04AE 0000 052D FFFF 0x042E 0000 04AD FFFF 0x0001 0000 0001 7FFF 0x0000 8000 0000 FFFF November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 8 Chapter 6 Board Test System Using the Board Test System The following sections describe the controls on the Flash tab The Read control reads the flash memory on your board To see the flash memory contents type a starting address in the text box and click Read Values starting at the specified address appear in the table The flash memory addresses display in the format the Nios II processor within the FPGA uses that is each flash memory address is offset by 0x0800 0000 Valid are entries 0x0000 0000 through 0 07 I Ifyou enter an address outside of the flash memory address space a warning message identifies the valid flash memory address range Write The Write control wri
24. G chain 3 Click Add File and select the path to the desired sof 4 Turn on the Program Configure option for the added file November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 28 Ls Chapter 6 Board Test System Samtec High speed Bull s Eye Connector 5 Click Start to download the selected file to the FPGA Configuration is complete when the progress bar reaches 10076 Using the Quartus programmer to configure a device on the board causes other JTAG based applications such as the Board Test System and the Power Monitor to lose their connection to the board Restart those applications after configuration is complete Samtec High speed Bull s Eye Connector This kit has a Samtec Bull s Eye connector with transceivers and a clock output from the clock buffer U25 Te For details on the pinout refer to the Arria V GT FPGA Development Board Reference Manual S For details on how to use the Bull s Eye interface refer to the Altera Arria V GX FPGA Development Kits page on the Samtec website For information on how to install the cable using the cable tool refer to the bullyseye instructions pdf file that resides in the install dir gt kits arriaVGT_5agtfd7kf40_fpga documents directory Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide JA DTE RA A Programming the Flash Memory Device As you develop your own project using the Altera tools you can
25. Portal standard flash format conventionally uses either filename hw flash for hardware design files or filename sw flash for software design files Programming Flash Memory Using the Board Update Portal Once you have the necessary flash files you can use the Board Update Portal to reprogram the flash memory Refer to Using the Board Update Portal to Update User Designs on page 5 2 for more information Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Appendix A Programming the Flash Memory Device A 3 Programming Flash Memory Using the Nios EDS If you have generated a sof that operates without a software design file you can still use the Board Update Portal to upload your design In this case leave the Software File Name field blank Programming Flash Memory Using the Nios EDS The Nios IT EDS offers a nios2 flash programmer utility to program the flash memory directly To program the flash files or any compatible S Record File srec to the board using nios2 flash programmer perform these steps 1 Set the Load Selector SW5 3 to the on factory factory design to load the Board Update Portal design from flash memory on power up 2 Attach the USB Blaster cable and power up the board 3 Ifthe board has powered up and the LCD displays either Connecting or a valid IP address such as 152 198 231 75 proceed to step 8 If no output appears on the LCD or if the Config Done LED
26. S15 Selects pseudo random 15 bit sequences PRBS23 Selects pseudo random 23 bit sequences PRBS31 Selects pseudo random 31 bit sequences m HF1 highest frequency divide by 2 data pattern 10101010 m HF2 next highest frequency divide by 4 data pattern 1100110011001100 m HF3 second lowest frequency divide by 8 data pattern 1111000011110000 m LF lowest frequency divide by 32 data pattern gt Settings HF1 HF2 HF3 LF for transmit observation only Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 23 The Power Monitor Error Control This control displays data errors detected during analysis and allows you to insert errors m Detected errors Displays the number of data errors detected in the hardware Inserted errors Displays the number of errors inserted into the transmit data stream Insert Error Inserts a one word error into the transmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros m Word error rate Detected word errors total received words Start The Start control initiates transaction performance analysis Stop The Stop control terminates transaction performance analysis Loophack These controls display current transaction performance analysis information collected since yo
27. ady for programming On the Windows Start menu click All Programs gt Altera gt Nios EDS gt Nios Command Shell In the Nios II command shell navigate to the lt install dir gt kits arriaVGT_5agtfd7kf40_fpga factory_recovery directory and type the following command to run the restore script restore sh Restoring the flash memory might take several minutes Follow any instructions that appear in the Nios II command shell After all flash programming completes cycle the POWER switch SW1 off then on Using the Quartus II Programmer click Add File and select install dir kits arriaVGT_5agtfd7kf40_fpga factory_recovery a5gtd7k3_fpga_bup sof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The Config Done LED D16 illuminates indicating the flash memory device is now restored with the factory contents Cycle the POWER switch SW1 off then on to load and run the restored factory design The restore script cannot restore the board s MAC address automatically In the Nios command shell type the following Nios EDS command nios2 terminal d 1 i 0 and follow the instructions in the terminal window to generate a unique MAC address Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Appendix A Programming the Flash Memory Device A
28. ailable on the Arria V GT FPGA Development Kit page of the Altera website m MAC Indicates the MAC address of the board MAX II Registers The MAX II registers control allows you to view and change the current MAX II register values as described in Table 6 1 Changes to the register values with the GUI take effect immediately For example writing a 0 to SRST resets the board Table 6 1 II Registers Part 1 of 2 Read Write Capability Register Name Description System Reset SRST Write only Set to 0 to initiate an FPGA reconfiguration Determines which of the up to eight 0 7 pages of flash Read Write memory to use for FPGA reconfiguration The flash memory ships with pages 0 and 1 preconfigured Page Select Register PSR Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 5 Using the Board Test System Table 6 1 II Registers Part 2 of 2 Read Write ae Register Name Capability Description When set to 0 the value in PSR determines the page of Page Select Override Read Write flash memory to use for FPGA reconfiguration When set to PSO 1 the value in PSS determines the page of flash memory to use for FPGA reconfiguration Holds the current value of the illuminated PGM LED D12 D14 based on the following encoding m 0 PGMLED 014 and corresponds to the flash Page Select Switch memory page for the facto
29. alyzed per second Start The Start control initiates transaction performance analysis Stop The Stop control terminates transaction performance analysis Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 21 Using the Board Test System The SMA Tab The SMA tab Figure 6 9 allows you perform loopback tests on the SMA port Figure 6 9 The SMA Tab Test system Tb Configure Help About System Info DIfBulls E Status PLL lock locked Pattern sync synced Control r Port FPGA2 SMA R9 PMA Setting Bull s eye GXB 115 Data type or control Detected errors 0 15 Inserted errors 0 Insert Error Clear Word error rate 7 436086e 10 Start Stop Tx MBps 1250 0083 Rx MBps 1250 0085 The following sections describe the controls on the SMA tab Status The Status control displays the following status information during the loopback test m PLLlock Shows the PLL locked or unlocked state Channellock Shows the channel locked or unlocked state When locked all lanes are word aligned and channel bonded m Pattern sync Shows the pattern synced or not synced state The pattern is considered synced when the start of the data sequence is detected November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide
30. ays the following status information during the loopback test m PLLlock Shows the PLL locked or unlocked state Channellock Shows the channel locked or unlocked state When locked all lanes are word aligned and channel bonded Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 13 Using the Board Test System Pattern sync Shows the pattern synced or not synced state The pattern is considered synced when the start of the data sequence is detected Port FPGA1 The Port 1 control allows you to specify which interface to test The following port tests are available Chip to Chip XCVR x8 HSMA design run at 6 4 Gbps Designs run at 10 Gbps SMA GXB_L11 m 5 A GXB L9 m SFB B GXB L14 m Bull s Eye GXB L15 Bull s Eye GXB R16 m Bull s Eye GXB R17 PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface The following settings are available for analysis m Serial Loopback Routes signals between the receiver and the transmitter Enter the following values to enable the serial loopbacks 0 high speed serial transceiver signals to loopback on the board 1 serial loopback 2 reverse serial loopback pre CDR 4 reverse serial loopback post CDR VODc Specifies the voltage output differential of the transmitter buffer m Pre emphasis tap m Pre S
31. ber 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide iv Contents Flash Memory Map sies cis RE Ed EE PEE Y ERN 6 8 The HSMA eire Rx EE REG E iow veda ei ua A ed exa 6 9 Status ivi pu Main edu Ds 6 9 Port EPGAT 4e ete Rx EU RP CES UU RU RP RU C RP MAU RP EDU E E eS 6 10 PMA Setting iseeeeem eme e DEF ex er e ag 6 10 Data tenda 6 10 Emor Control PE ed 6 11 dure 6 11 eb uta efe est is es e pea imesh 6 11 Wooo e eta E 6 11 The SEP SMA C2C Tab Choe as 6 12 Status i e E we aS 6 12 Port EPGA T As 6 13 Setting c ak aei ba au 6 13 Data e 6 13 Error Control 6 14 Loopback ce 6 14 Start ie rud E 6
32. cheme as shown in Volume 2 Device Interfaces and Integration of the Arria V Device Handbook 2 Set DIP switch bank SW5 to match Table 4 2 and Figure 4 2 Table 4 2 SW5 Board Settings Dip Switch Board Lahel Default Switch Position Function Switch 1 has the following options 1 CLK SEL m ON logical 0 SMA input clock select OFF m OFF logical 1 programmable oscillator clock select Switch 2 has the following options 2 CLK_EN ON logical 0 on board oscillator disable ON OFF logical 1 on board oscillator enable Switch 3 has the following options m ON logical 0 load the factory design for Arria V 3 Factory1 FPGA 1 from flash at power up ON OFF logical 1 load the user design for Arria V FPGA 1 from flash at power up 4 Factory2 Switch 4 is for factory test only OFF November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide Chapter 4 Development Board Setup Factory Default Switch and Jumper Settings 3 Set DIP switch bank SW6 to match Table 4 3 and Figure 4 2 Table 4 3 SW6 JTAG Dip Switch Settings Switch ed Function oa 1 OFF Switch 2 has the following options 2 HSMA_JTAG_EN ON logical 0 HCMC Port A not in JTAG chain ON OFF logical 1 Include HCMC Port A in the JTAG chain Switch 3 has the following options 3 HSMB_JTAG_EN m ON logical 0 HCMC Port
33. d e em need e m n a n Ry ordo 6 3 Using the Board Test System a e he am be EE eee dhe 6 3 Th Configure Men cesar up oki RE ay Y baa bees Ex Fe eerte ra RE EY 6 3 The System Tab Lc ay aleve on ae es eH ce ets 6 4 board Information Leod 5 rmv TR neat bh ee ES Ade Kd ERES 6 4 MAX II 52 95 Ret _____________________ 6 4 JTAG Chair eps eiu uuu heuer Vie Eve E 6 5 The FPGA zer n EY dra ob GC Ea a Gd bd eis 6 6 Character LED ae issue ete un oe Que e hA e p bro eek dA o 6 6 User Soak 6 7 User LBS Rx a Se oe ee be bad Bk PRESS 6 7 Push Button Switches 1 0 4 6 7 The Flash Tab 4 ure Ap sedges eine ead 6 7 Read WE ER AAR d HERE Rad REGES 6 8 WEG a eat dp od koa ed ind eed uc o d n Mallets e 6 8 Random sana ed hacia 6 8 CE E 6 8 Increment TeSt Eg RAE E eed 6 8 RENE PE RE REIR eee Heke eee ee e 6 8 Erase MR REY ERR 6 8 Novem
34. dom 15 bit sequences PRBS23 Selects pseudo random 23 bit sequences m PRBS31 Selects pseudo random 31 bit sequences HF1 highest frequency divide by 2 data pattern 10101010 m HF2 next highest frequency divide by 4 data pattern 1100110011001100 m HF3 second lowest frequency divide by 8 data pattern 1111000011110000 Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 11 Using the Board Test System m LF lowest frequency divide by 40 data pattern Le Settings HF1 HF2 HF3 LF are for transmit observation only Error Control This control displays data errors detected during analysis and allows you to insert errors m Detected errors Displays the number of data errors detected in the hardware Inserted errors Displays the number of errors inserted into the transmit data stream Insert Error Inserts a one word error into the transmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros m Word error rate Detected word errors total received words Start The Start control initiates transaction performance analysis Stop The Stop control terminates transaction performance analysis Loopback These controls display current transaction performance analysis information collected since you last clicked S
35. e following sections describe the Power Monitor controls General Information The General information controls display the following information about the MAX II device m II Version Indicates the version of MAX II code currently running on the board The MAX II code resides in the install dir NkitsNarriaV GT 5agtfd7kf40 fpgaNfactory recovery and install dir gt kits arriaVGT_5agtfd7kf40_fpga examples max2 directories Newer revisions of this code might be available on the Arria V GT FPGA Development Kit page of the Altera website m Power Rail Selects the power rail to measure After selecting the desired rail click Reset to refresh the screen with new board readings Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 25 The Power Monitor T A table with the power rail information is available in the Arria V GT FPGA Development Board Reference Manual Power Information The Power information control displays current maximum and minimum power readings for the following units mAmp Power Graph The power graph displays the mA power consumption of your board over time The green line indicates the current value The red line indicates the maximum value read since the last reset The yellow line indicates the minimum value read since the last reset Graph Settings The following Graph settings controls allow you to define the look and feel of the p
36. efer to the Arria V GT FPGA Development Kit page of the Altera website November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide A 6 Appendix A Programming the Flash Memory Device Restoring the MAX II CPLD to the Factory Settings Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide ND S BAAN Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document Date Version Changes November 2012 1 0 Initial release How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact 7 Contact Method Address Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Meaning Indicate command names dialog box titles dialog box options and other GUI Bold Type labels For example Save
37. emory and provides useful kit specific links and design resources 7 After successfully updating the user hardware 1 and or hardware 2 flash memory you can load the user design from flash memory into the FPGA To do so set the Load Selector SW5 3 to the off user position and power cycle the board The design stored in user hardware 1 is used to configure FPGA 1 when the board is power cycled To configure FPGA 1 with the design stored in user hardware 2 push and release the PGM1 52 push button the required number of times until PGM2 LED lights and then push PGM_CONF 53 to configure the FPGA The source code for the Board Update Portal design resides in the lt install dir gt kits arriaVGT_5agtfd7kf40_fpga examples directory If the Board Update Portal is corrupted or deleted from the flash memory refer to Restoring the Flash Device to the Factory Settings on page 4 to restore the board with its original factory contents Connecting to the Board Update Portal Web Page This section provides instructions to connect to the Board Update Portal web page 7 Before you proceed ensure that you have the following m APC with a connection to a working Ethernet port on a DHCP enabled network separate working Ethernet port connected to the same network for the board m The Ethernet and power cables that are included in the kit To connect to the Board Update Portal web page perform these steps 1 With the board powered
38. er of data errors detected in the hardware Inserted errors Displays the number of errors inserted into the transmit data stream Insert Error Inserts a one word error into the transmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros m Word error rate Detected word errors total received words Loopback These controls display current transaction performance analysis information collected since you last clicked Start m TX and RX performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve m Tx MBps and Rx MBps Show the number of bytes of data analyzed per second Start The Start control initiates transaction performance analysis Stop The Stop control terminates transaction performance analysis Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 15 Using the Board Test System The HSMB FMC Tab The HSMB FMC tab Figure 6 7 allows you to perform loopback tests on the XCVR and CMOS ports Figure 6 7 The HSMB FMC Tah Board Test System 6 xl Configure Help About XCVR x4 PMA Setting LVDS x17 C CMOS x3 C FMCXCVR x4 C FMC CMOS x80 Data type or control
39. es except for the 51570 and Si571 devices For more information about the 51570 and 51571 registers refer to the Si570 Si571 data sheet available on the Silicon Labs website www silabs com Disable The Si5338A GUI allows you to disable clock outputs if desired This control reads the current frequency setting for the Si5338A associated with the active tab Default This control sets the frequency for the oscillator associated with the active tab back to its default value This can also be accomplished by power cycling the board Set New Frequency The Set New Frequency control sets the programmable oscillator frequency for the selected clock to the value in the Target frequency control Frequency changes might take several milliseconds to take effect You might see glitches on the clock during this time Altera recommends resetting the FPGA logic after changing frequencies Configuring the FPGA Using the Quartus Il Programmer You can use the Quartus II Programmer to configure the FPGA with a specific sof Before configuring the FPGA ensure that the Quartus II Programmer and the USB Blaster driver are installed on the host computer the USB cable is connected to the FPGA development board power to the board is on and no other applications that use the JTAG chain are running To configure the Arria V GT FPGA perform the following steps 1 Start the Quartus II Programmer 2 Click Auto Detect to display the devices in the JTA
40. ests are available m Bull s Eye GXB_R7 design run at 6 4 Gbps SDI design run at 2 9 Gbps PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface The following settings are available for analysis m Serial Loopback Routes signals between the receiver and the transmitter Enter the following values to enable the serial loopbacks 0 high speed serial transceiver signals to loopback on the board 1 serial loopback 2 reverse serial loopback pre CDR 4 reverse serial loopback post CDR VOD Specifies the voltage output differential of the transmitter buffer Pre emphasis tap m Pre Specifies the amount of pre emphasis on the pre tap of the transmitter buffer m First post 5pecifies the amount of pre emphasis on the first post tap of the transmitter buffer m Second post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer m Equalizer Specifies the setting for the receiver equalizer m DC gain Specifies the DC portion of the receiver equalizer Data Type The Data type control specifies the type of data contained in the transactions The following data types are available for analysis m PRBS7 Selects pseudo random 7 bit sequences PRBS15 Selects pseudo random 15 bit sequences PRBS23 Selects pseudo random 23 bit sequences PRBS31 Selects pseudo random 31 bit sequences HF1 h
41. f tools that allows you to develop embedded software for the Nios II processor which you can include in your Altera FPGA designs Arria V GT FPGA Development Kit Installer The license free Arria V GT FPGA Development Kit installer includes all the documentation and design examples for the kit For information on installing the Development Kit Installer refer to Software Installation on page 3 1 Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide DTE 2 Getting Started The remaining chapters in this user guide lead you through the following Arria V GT FPGA development board setup steps m Inspecting the contents of the kit m Installing the design and kit software m Setting up powering up and verifying correct operation of the FPGA development board m Configuring the Arria V GT FPGAs m Running the Board Test System designs Ta For complete information about the FPGA development board refer to the Arria V GT FPGA Development Board Reference Manual Before You Begin Before using the kit or installing the software check the kit contents and inspect the boards to verify that you received all of the items listed in Kit Features on page 1 1 If any of the items are missing contact Altera before you proceed Inspect the Boards To inspect each board perform the following steps 1 Place the board on an anti static surface and inspect it to ensure that it has not been damaged du
42. g in the FPGA The Arria V GT FPGA development board s flash memory ships preconfigured with the design that corresponds to the GPIO tab 7 If you power up your board with your own design programmed into the FPGA with the Quartus Programmer you receive a message prompting you to configure your board with a valid Board Test System design Refer to The Configure Menu for information about configuring your board Using the Board Test System This section describes each control in the Board Test System application The Configure Menu Use the Configure menu Figure 6 2 to select the design you want to use Each design example tests different functionality that corresponds to one or more application tabs Figure 6 2 The Configure Menu Board Test System Configure Help About Configure Device 1 with Flash GPIO Design Gonfigure Device 1 with DDR3x72 Design Configure Device 1 with Design Configure Device 1 with HSMA Design Configure Device 1 with SFP 5MA C2C Design Gonfigure Device 2 with DDR3x32 Design Configure Device 2 with DDR3x6 Configure Device 2 with HSMB FMC Design Configure Device 2 with SDI Bullseye Design Configure Device 2 with 5 Design Exit Ctrl Q To configure the FPGA with a test system design perform the following steps 1 Make sure there are no conflicts between the Quartus software version and the Board Test System GUI version November 2012 Altera
43. he following Nios II EDS command nios2 flash programmer d 1 i 0 base 0x0 lt yourfile gt sw flash Programming the board is now complete St For more information about the nios2 flash programmer utility refer to the Nios II Flash Programmer User Guide November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide A 4 Appendix A Programming the Flash Memory Device Restoring the Flash Device to the Factory Settings Restoring the Flash Device to the Factory Settings This section describes how to restore the original factory contents to the flash memory device on the FPGA development board Make sure you have the Nios IT EDS installed and perform the following instructions 1 10 11 12 13 Set the board switches to the factory default settings described in Factory Default Switch and Jumper Settings on page 4 2 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 27 for more information Click Add File and select lt install dir gt kits arriaVGT_5agtfd7kf40_fpga factory_recovery a5gtd7k3_fpga_bup sof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The Config Done LED D16 illuminates indicating that the flash device is re
44. ighest frequency divide by 2 data pattern 10101010 HF2 next highest frequency divide by 4 data pattern 1100110011001100 HF3 second lowest frequency divide by 8 data pattern 1111000011110000 m LF Bull s Eye lowest frequency divide by 32 data pattern m LF SDI lowest frequency divide by 10 data pattern s Settings HF1 HF2 LF are for transmit observation only November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 20 Chapter 6 Board Test System Using the Board Test System Error Control This control displays data errors detected during analysis and allows you to insert errors m Detected errors Displays the number of data errors detected in the hardware Inserted errors Displays the number of errors inserted into the transmit data stream Insert Error Inserts a one word error into the transmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros m Word error rate Detected word errors total received words Loopback These controls display current transaction performance analysis information collected since you last clicked Start m TX and RX performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve m Tx MBps and Rx MBps Show the number of bytes of data an
45. ils refer to Altera Software Installation and Licensing Manual Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 3 Software Installation 3 3 Installing the Development Kit Installing the Development Kit To install the Arria V GT FPGA Development Kit perform the following steps 1 Download the Arria V GT FPGA Development Kit installer from the Arria V GT FPGA Development Kit page of the Altera website Alternatively you can request a development kit DVD from the Altera Kit Installations DVD Request Form page of the Altera website 2 Run the Arria V GT FPGA Development Kit installer 3 Follow the on screen instructions to complete the installation process Be sure that the installation directory you choose is in the same relative location to the Quartus II software installation The installation program creates the Arria V GT FPGA Development Kit directory structure shown in Figure 3 2 Figure 3 2 Arria V GT FPGA Development Kit Installed Directory Structure 1 install dir The default Windows installation directory is C altera lt version gt kits arriaVGT 5agtfd7kf40 fpga board_design_files C demos documents a examples C factory_recovery Note to Figure 3 2 1 Early release versions might have slightly different directory names Table 3 1 lists the file directory names and a description of their contents Table 3 1 Installed Directory Contents
46. include the interface in the JTAG chain Refer to Table 4 3 for detailed settings 5 If you plug an external USB Blaster cable to the JTAG header J1 the On Board USB Blaster II is disabled T For details on the JTAG chain refer to the Arria V GT FPGA Development Board Reference Manual For USB Blaster II configuration details refer to the On Board USB Blaster II page November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 6 Chapter 6 Board Test System Using the Board Test System The GPIO FPGA 1 Tab The GPIO FPGA 1 tab allows you to interact with all the general purpose user I O components on your board You can write to the character LCD read DIP switch settings turn LEDs on or off and detect push button presses Figure 6 3 shows the GPIO FPGA 1 tab Figure 6 3 The GPIO FPGA 1 Tab ARET Test System _ EE x Configure Help About Sonens pa System Info GPIO FPGA1 Flash SFPISMAIC2C 24 Character LCD Enter text eria Development Kit Read Power Monitor User DIP switch 6 4 3 e 1 0 1 LEE 08 0 ON B B B B B User LEDs Messages Detected the Flash GPIO Project Push button switches PB2 The following sections describe the controls o
47. ions 4 FPGA1 MSEL 4 When a logic 0 is selected OFF m When OFF a logic 1 is selected Note to Table 4 5 1 Ensure that all MSEL setting are in a defined configuration scheme as shown in Volume 2 Device Interfaces and Integration of the Arria V Device Handbook 6 Set the board jumpers to match Table 4 6 Figure 4 1 and Figure 4 2 Table 4 6 Jumper Settings Part 1 of 2 Board Board Default Reference Label Function Position This jumper has the following options Installing the shunt on pins 1 2 provides 2 5 V on FMC_VCCPD Installing the shunt on pins 2 3 provides 3 3 V on J5 FMC_VCCPD FMC VCCPD Pins 1 2 5 VCCPD setting must be set according the to voltage supplied by the FMC card to avoid damaging your development board This jumper has the following options m No shunt 1 5V m Shunt on pins 1 2 1 8V J11 FMC_VCCIO_SEL Shunt pins 3 4 2 5 Pins 3 4 Shunt on pins 5 6 3 3V Note When setting this jumper to 3 3 V make sure the FMC_VCCPD is on the correct setting J5 shunt on pins 2 3 J14 FAN2 Powers the fan for FPGA 2 Installed November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 4 6 Chapter 4 Development Board Setup Factory Default Switch and Jumper Settings Table 4 6 Jumper Settings Part 2 of 2 Board Board Reference Label Default Function Position This jumper has the following options In
48. n the FPGA 1 tab Character LCD The Character LCD controls allow you to display text strings on the character LCD on your board Type text in the text boxes and then click Display Click Read to read the currently shown on the LCD display gt Ifyou exceed the 16 character display limit on either line a warning message appears Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 7 Using the Board Test System User DIP Switch The read only User DIP switches control displays the current positions of the switches in the user DIP switch bank SW2 Change the switches on the board to see the graphical display change accordingly User LEDs The User LEDs control displays the current state of the user LEDs for FPGA 1 To toggle the board LEDs click the 0 to 7 buttons to toggle red or green LEDs or click the All button Push Button Switches The read only Push button switches control displays the current state of the board user push buttons Press a push button on the board to see the graphical display change accordingly The Flash Tab The Flash tab Figure 6 4 allows you to read and write flash memory on your board Figure 6 4 The Flash Tab soara test system TE Configure Help About ATERA Detected the Flash GPIO Project Bullse DDRSFPGAT 093 Te RYAN 7 sense seo erem 0x0000 0000 OxO07
49. ntain hyphens Figure 3 1 shows 35150SPXXXX as an example serial number Figure 3 1 Locating Your Serial Number DK DSP 3SL150 YY LOT XXXXX 3S150SPXXXX 2 Consult the Activate Products table to determine how to proceed a Ifthe administrator listed for your product is someone other than you skip the remaining steps and contact your administrator to become a licensed user b Ifthe administrator listed for your product is you proceed to step 3 c Ifthe administrator listed for your product is Stocking activate the product making you the administrator and proceed to step 3 3 Use the Create New License page to license your product for a specific user you on specific computers The Manage Computers and Manage Users pages allow you to add users and computers not already present in the licensing system gt To license the Quartus II software you need your computer s network interface card NIC ID a number that uniquely identifies your computer On the computer you use to run the Quartus II software type ipconfig all ata command prompt to determine the NIC ID Your NIC ID is the 12 digit hexadecimal number on the Physical Address line 4 When licensing is complete Altera emails a license dat file to you Store the file on your computer and use the License Setup page of the Options dialog box in the Quartus software to enable the software Ta For complete licensing deta
50. ol terminates transaction performance analysis November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 18 Chapter 6 Board Test System Using the Board Test System The SDI Bull s Eye Tab The SDI Bull s Eye tab Figure 6 8 allows you perform loopback tests on the Bull s Eye and SDI ports Figure 6 8 The SDI Bull s Eye Tab Board Test System xl Configure Help About Bull s Eye GXB_R7 PMA Setting 501 Data or control Detected errors 0 presis v Inserted errors 0 Insert Error Clear Word error rate 7 460877e 10 Tx MBps 800 0124 Rx MBps 800 0122 The following sections describe the controls on the SDI Bull s Eye tab Status The Status control displays the following status information during the loopback test m PLLlock Shows the PLL locked or unlocked state m Channel lock Shows the channel locked or unlocked state When locked all lanes are word aligned and channel bonded m Pattern sync Shows the pattern synced or not synced state The pattern is considered synced when the start of the data sequence is detected Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 19 Using the Board Test System Port FPGA2 The Port FPGA2 control allows you to specify which interface to test The following port t
51. ower graph m Scale Select Specifies the amount to scale the power graph Select a smaller number to zoom in to see finer detail Select a larger number to zoom out to see the entire range of recorded values m Update Speed Specifies how often to refresh the graph Reset This Reset control clears the graph resets the minimum and maximum values and restarts the Power Monitor Calculating Power The Power Monitor calculates power by measuring two different voltages with the LT2418 A D and applying the equation P V x I to determine the power consumption The LT2418 measures the voltage after the appropriate sense resistor Vsense and the voltage drop across that sense resistor The current is calculated by dividing the measured voltage drop across the resistor by the value of the sense resistor I Vdif R Through substitution the equation for calculating power becomes P V x I Vsense x Vdif R Vsense x x 1 003 except for the ASA VCCINT and A5B_VCCINT rails which uses 0 001 Ohms for R and A5A VCCD 1 5V and 5 VCCD PLL 1 5V which use 0 009 Ohms You can verify the power numbers shown in the Power Monitor with a digital multimeter that is capable of measuring microvolts to ensure you have enough significant digits for an accurate calculation Measure the voltage on one side of the resistor the side opposite the power source and then measure the voltage on the other side The first mea
52. ows you to specify which interface to test The following port tests are available Design run at 10 Gbps m XCVR x4 Design run at 50 Mbps m CMOS x3 PMA Setting The PMA Setting button allows you to make changes to the PMA parameters at 50MHz that affect the active transceiver interface The following settings are available for analysis m Serial Loopback Routes signals between the receiver and the transmitter Enter the following values to enable the serial loopbacks 0 high speed serial transceiver signals to loopback on the board 1 serial loopback 2 reverse serial loopback pre CDR 4 reverse serial loopback post CDR m VODc Specifies the voltage output differential of the transmitter buffer m Pre emphasis tap m Pre Specifies the amount of pre emphasis on the pre tap of the transmitter buffer m First post 5pecifies the amount of pre emphasis on the first post tap of the transmitter buffer m Second post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer m Equalizer Specifies the setting for the receiver equalizer m DC gain Specifies the DC portion of the receiver equalizer Data Type The Data type control specifies the type of data contained in the transactions for transceivers The LVDS design uses 58 and the CMOS design uses PRBS3 The following data types are available for transceiver analysis m PRBS7 Selects pseudo random 7 bit sequences PRBS15 Selects pseudo ran
53. pdate Portal or the Nios II EDS nios2 flash programmer utility to write the flash files to the user hardware 1 and user software locations of the flash memory For more information about Nios EDS software tools and practices refer to the Embedded Software Development page of the Altera website Creating Flash Files Using the Nios EDS If you have an FPGA design developed using the Quartus IT software and software developed using the Nios II EDS follow these instructions 1 On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios Command Shell 2 In the Nios command shell navigate to the directory where your design files reside and type the following Nios EDS commands m For Quartus II sof files sof2flash input lt yourfile gt hw sof output lt yourfile gt hw flash offset 0x01660000 pfl optionbit 0x00018000 programmingmode PS m For Nios II elf files elf2flash base 0x0 end 0x07FFFFFF reset 0x052E0000 input yourfile sw elf output yourfile sw flash boot SOPC KIT NIOS2 components altera nios2 boot loader cfi srece The resulting flash files are ready for flash device programming If your design uses additional files such as image data or files used by the runtime program you must first convert the files to flash format and concatenate them into one flash file before using the Board Update Portal to upload them The Board Update
54. pecifies the amount of pre emphasis on the pre tap of the transmitter buffer m First post Specifies the amount of pre emphasis on the first post tap of the transmitter buffer m Second post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer m Equalizer Specifies the setting for the receiver equalizer m DC gain Specifies the DC portion of the receiver equalizer Data Type The Data type control specifies the type of data contained in the transactions The following data types are available for analysis m PRBS7 Selects pseudo random 7 bit sequences m PRBS15 Selects pseudo random 15 bit sequences November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 14 Chapter 6 Board Test System Using the Board Test System PRBS23 Selects pseudo random 23 bit sequences PRBS31 Selects pseudo random 31 bit sequences HF1 highest frequency divide by 2 data pattern 10101010 HF2 next highest frequency divide by 4 data pattern 1100110011001100 HF3 second lowest frequency divide by 8 data pattern 1111000011110000 LF SMA SFP Bull s Eye lowest frequency divide by 40 data pattern LF Chip to chip divide by 32 data pattern gt Settings HF1 HF2 HF3 LF for transmit observation only Error Control The Error control control displays data errors detected during analysis and allows you to insert errors m Detected errors Displays the numb
55. r Guide N DTE 4 Development Board Setup The instructions in this chapter explain how to set up the Arria V GT FPGA development board Setting Up the Board To prepare and apply power to the board perform the following steps 1 The Arria V GT FPGA development board ships with its board switches preconfigured to support the design examples in the kit If you suspect your board might not be currently configured with the default settings follow the instructions in Factory Default Switch and Jumper Settings on page 4 2 to return the board to its factory settings before proceeding 2 The development board ships with design examples stored in the flash memory device Verify the Load Selector SW5 3 is in the on factory position to load the design stored in the factory portion of flash memory Figure 4 1 Figure 4 2 shows the switch locations on the Arria V GT FPGA development board 3 Connect the 19 V 6 32 A to the DC Power Jack J6 on the FPGA board and plug the cord into a power outlet A Use only the supplied power supply Power regulation circuitry on the board can be damaged by power supplies with greater voltage and a lower rated power supply may not be able to provide enough power for the board 4 Set the POWER switch SW1 to the on position When power is supplied to the board blue LED D1 illuminates indicating that the board has power The MAX II device on the board contains among other things
56. refer to the Devices page For Arria V GT OrCAD symbols refer to the Capture CIS Symbols page For Nios II 32 bit embedded processor solutions refer to the Embedded Processing page Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide N D TE 2Ya 3 Software Installation This chapter explains how to install the following software m Quartus II Subscription Edition Software m Arria V GT FPGA Development Kit m USB Blaster II driver Installing the Quartus Il Subscription Edition Software The Quartus II Subscription Edition Software provides the necessary tools used for developing hardware and software for Altera devices Included in the Quartus II Subscription Edition Software are the Quartus II software the Nios II EDS and the MegaCore IP Library The Quartus II software including SOPC Builder and the Nios II EDS are the primary FPGA development tools used to create the reference designs in this kit To install the Altera development tools perform the following steps 1 Download the Quartus II Subscription Edition Software from the Quartus II Subscription Edition Software page of the Altera website Alternatively you can request a DVD from the Altera IP and Software DVD Request Form page of the Altera website 2 Choosing an installation directory that is relative to the Quartus II software installation directory follow the on screen instructions to complete the installation process If yo
57. ring shipment A Without proper anti static handling you can damage the board CAUTION 2 Verify that all components on the board appear in place and intact I gt In typical applications with the Arria GT FPGA development board a heat sink is not necessary However under extreme conditions or for engineering sample silicon the board might require additional cooling to stay within operating temperature guidelines The board has two holes near the FPGAs that accommodate many different heat sinks including the Dynatron CHR 152 You can perform power consumption and thermal modeling to determine whether your application requires additional cooling For information about measuring board and FPGA power in real time refer to The Power Monitor on page 6 23 St For more information about power consumption and thermal modeling refer to AN 358 Thermal Management for FPGAs November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 2 2 References Chapter 2 Getting Started References Use the following links to check the Altera website for other related information For the latest board design files and reference designs refer to the Arria V GT FPGA Development Kit page For additional daughter cards available for purchase refer to the Development Board Daughtercards page For the Arria V GT device documentation refer to the Documentation Arria V Devices page To purchase devices from the eStore
58. ry Default Switch and Jumper Settings section starting on page 4 2 4 Set the Load Selector SW5 3 to the off user position For more information about the board s DIP switch and jumper settings refer to the Arria V GT FPGA Development Board Reference Manual 5 Turn on the power to the board The board loads the design stored in the user hardware 1 portion of flash memory into the FPGA If your board is still in the factory configuration or if you have downloaded a newer version of the Board Test System to flash memory through the Board Update Portal the design loads the GPIO Ethernet and flash memory tests To ensure operating stability keep the USB cable connected and the board powered on when running the demonstration application The application cannot run correctly unless the USB cable is attached and the board is on CAUTION Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 3 Running the Board Test System Running the Board Test System To run the application navigate to the lt install dir gt kits arriaVGT_5agtfd7kf40_fpga examples board_test_system directory and run the BoardTestSystem exe application La On Windows click Start gt All Programs gt Altera gt Arria V GT FPGA Development Kit lt version gt gt Board Test System to run the application A GUI appears displaying the application tab that corresponds to the design runnin
59. ry hardware design Read only PSS m 1 PGM LED D13 and corresponds to the flash memory page for the user hardware 1 design m 2 PGM LED 012 and corresponds to the flash memory page for the user hardware 2 design m PSO Sets the MAX II PSO register The following options are available m UsePSR Allows the PSR to determine the page of flash memory to use for FPGA reconfiguration m Use PSS Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration m PSR Sets the MAX II PSR register The numerical values in the list corresponds to the page of flash memory to load during FPGA reconfiguration Refer to Table 6 1 for more information m PSS Displays the MAX II PSS register value Refer to Table 6 1 for the list of available options m SRST Resets the system and reloads the FPGA with a design from flash memory based on the other MAX II register values Refer to Table 6 1 for more information gt Because the System Info tab requires that a specific design is running in the FPGA at a specific clock speed writing a 0 to SRST or changing the PSO value can cause the Board Test System to stop running JTAG Chain The JTAG chain control shows all the devices currently in the JTAG chain The Arria V GT Device 1 Arria V GX Device 2 and MAX II are always in the JTAG chain SW6 selects whether HSMB and FMC are in the chain Set the SW6 switch in the off position to
60. se this version of the Quartus IT software To continue using the Quartus II software you should download the free Quartus II Web edition or purchase a subscription to Quartus II software For more information refer to the Design Software page of the Altera website The Quartus Development Kit Edition DKE software includes the following items m Quartus Software The Quartus II software including the Qsys system integration tool provides a comprehensive environment for network on a chip NoC design The Quartus II software integrates into nearly any design environment and provides interfaces to industry standard EDA tools MegaCore IP Library A library that contains Altera IP MegaCore functions You can evaluate MegaCore functions by using the OpenCore Plus feature to do the following m Simulate behavior of a MegaCore function within your system m Verify functionality of your design and quickly and easily evaluate its size and speed m Generate time limited device programming files for designs that include MegaCore functions m Program a device and verify your design in hardware gt The OpenCore Plus hardware evaluation feature is an evaluation tool for prototyping only You must purchase a license to use a MegaCore function in production St For more information about OpenCore Plus refer to AN 320 OpenCore Plus Evaluation of Megafunctions Nios II Embedded Design Suite EDS A full featured set o
61. signals between the receiver and the transmitter Enter the following values to enable the serial loopbacks 0 high speed serial transceiver signals to loopback on the board 1 serial loopback 2 reverse serial loopback pre CDR 4 reverse serial loopback post CDR m VOD Specifies the voltage output differential of the transmitter buffer tap Pre Specifies the amount of pre emphasis on the pre tap of the transmitter buffer First post Specifies the amount of pre emphasis on the first post tap of the transmitter buffer Second post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer m Equalizer Specifies the setting for the receiver equalizer m DC gain Specifies the DC portion of the receiver equalizer Data Type The Data type control specifies the type of data contained in transceiver transactions The following data types are available for transceiver analysis PRBS7 Selects pseudo random 7 bit sequences PRBS15 Selects pseudo random 15 bit sequences PRBS23 Selects pseudo random 23 bit sequences PRBS31 Selects pseudo random 31 bit sequences m HF1 highest frequency divide by 2 data pattern 10101010 m HF2 next highest frequency divide by 4 data pattern 1100110011001100 m HF3 second lowest frequency divide by 8 data pattern 1111000011110000 m LF FMC lowest frequency divide by 40 data pattern Arria V GT FPGA Development Kit November 2
62. stalling the shunt on pins 1 2 powers bank 4B when there is no FMC card installed or the FMC card does not provide a voltage for this rail The voltage on this depends on the voltage selected on J11 J28 FMC VCCIO SRC Pins 1 2 m Installing the shunt on pins 2 3 powers bank 4B when an FMC card is installed and provides the power needed for this bank The max voltage on this is 3 3 V Do not install an FMC with a higher rated card Note FMC is not available for rev A boards J23 FAN1 Powers the fan for FPGA 1 Installed Te For more information about the FPGA board settings refer to the Arria V GT FPGA Development Board Reference Manual Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide 5 Board Update Portal The Arria V GT FPGA Development Kit ships with the Board Update Portal design example stored in the factory portion of the flash memory on the board The design consists of a Nios embedded processor an Ethernet MAC and an HTML web server When you power up the board with the Load Selector SW5 3 in the on factory position the Arria V GT FPGA configures with the Board Update Portal design example The design can obtain an IP address from any DHCP server and serve a web page from the flash on your board to any host computer on the same network The web page allows you to upload new FPGA designs to the user hardware 1 and hardware 2 portion of flash m
63. surement is Vsense and the difference between the two measurements is Vdif Plug the values into the equation to determine the power consumption November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 26 Chapter 6 Board Test System The Clock Control The Clock Control The Clock Control application sets the Si570 and Si571 programmable oscillators to any frequency between 10 MHz and 810 MHz with eight digits of precision to the right of the decimal point The 51570 oscillator drives 1 to 6 buffer that drives a copy of the clock to the top and bottom edges of each FPGA in addition to REFCLK1 on the left side of each FPGA There are also four 515338 custom devices which output 4 programmable clocks to each FPGA There are two of these devices dedicated to each FPGA Each Si5338A device provides three transceiver reference clocks to the FPGA as well as an additional clock to one of the edges of the FPGA In addition Clk1 on 053 drives a 1 to 2 clock buffer to output clocks to REFCLKS on the left side of FPGA 1 and to a Samtec Bullseye SMA connector J16 The Clock Control application runs as a stand alone application ClockControl exe resides in the install dir NkitsNarriaV GT 5agtfd7kf40 fpgaNexamplesVboard test system directory On Windows click Start gt All Programs gt Altera gt Arria V GT FPGA Development Kit lt version gt gt Clock Control to start the application For more information about
64. tart m TX and RX performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve m Tx MBps and Rx MBps Show the number of bytes of data analyzed per second November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 12 Chapter 6 Board Test System Using the Board Test System The SFP SMA C2C Tab The SFP SMA C2C tab Figure 6 6 allows you to run test designs using the respective transceiver interfaces on FPGA 1 57 Torun the SFP designs using this GUI use the USER1_DIPSW to enable or disable SFP lasers To turn the SFP_A laser on ensure that USER1 DIPSW 4 is in the OFF position toward the HSMC connector To turn on the SFP B laser ensure that USER1_DIPSWJ5 is in the OFF position Figure 6 6 SFP SMA C2C Tab Boara Test system aT Configure Help About PLL lock locked Pattern sync synced Control Port FPGA 1 Chip to Chip XCVR x8 PMA Setting C SMA GXB 111 SFP_A GXB 19 Bull s Eye 115 Chip to Chip LVDS x28 Bull s Eye GXB R16 C SFP B GXB L14 C Bull s Eye GXB R17 Data type or control Detected errors 0 presis Inserted errors 0 Insert Error Clear Word error rate 9 378107e 10 Detected XCVR 2 Project The following sections describe the controls on the SFP SMA C2C tab Status The Status control displ
65. tes the flash memory on your board To update the flash memory contents change values in the table and click Write The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents 2 7 To prevent overwriting the dedicated portions of flash memory the application limits the user writable flash memory address range to the uppermost 128 KB memory block as shown in Figure 6 1 on page 6 1 and Table A 1 on page 1 Random Test Starts a random data pattern test to flash memory which is limited to a scratch page in the upper 128K block CFI Query The CFI Query control updates the memory table displaying the CFI ROM table contents from the flash device Increment Test Starts an incrementing data pattern test to flash memory which is limited to a scratch page in the upper 128K block Reset The Reset control executes the flash device s reset command and updates the memory table displayed on the Flash tab Erase Erases flash memory which is limited to a scratch page in the upper 128K block Flash Memory Map Displays the flash memory map for the Arria V GT FPGA Development Kit Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 9 Using the Board Test System The HSMA Tab HSMA tab Figure 6 5 allows you to perform loopback tests on the transceiver XCVR and
66. the Arria VGT FPGA Development Kit contents Hardware The Arria V GT FPGA Development Kit includes the following hardware Arria V GT FPGA development board A development platform that allows you to develop and prototype hardware designs running on the Arria V GT 5AGTFD7K3F40N FPGA St For detailed information about the board components and interfaces refer to the Arria V GT FPGA Development Board Reference Manual HSMC loopback daughtercard m HSMC debug daughtercard m Power supply and cables The kit includes the following items Power supply and AC adapters for North America Japan Europe and the United Kingdom m USB cable Ethernet cable Samtec high speed Bull s Eye kit with 22 position connector four SMA cables and tool Software The software for this kit described in the following sections is available on the Altera website for immediate downloading You can also request to have Altera mail the software to you on DVDs Quartus Software Your kit includes a license for the Development Kit Edition DKE of the Quartus II software Windows platform only For one year this license entitles you to most of the features of the Subscription Edition excluding the IP Base Suite November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide Chapter 1 About This Kit Kit Features gt After the year your DKE license will no longer be valid and you will not be permitted to u
67. u 14 i J28 installed 23 O Figure 4 2 shows the switch locations and the default position of each switch on the bottom side of the board Figure 4 2 Switch Locations and Default Settings on the Board Bottom sw MSEL2 12 4 T SW6 x FEET A 5 MSEL 1 PCle Width 1 24 0000 SW8 Arria V GT FPGA Development Kit User Guide November 2012 Altera Corporation Chapter 4 Development Board Setup 4 3 Factory Default Switch and Jumper Settings To restore the switches to their factory default settings perform the following steps 1 Set DIP switch bank SW4 to match Table 4 1 and Figure 4 2 Table 4 1 SW4 FPGA2 MSEL Dip Switch Settings 7 Default Position Board Switch Label Function Switch 1 has the following options 1 FPGA2 MSEL 1 m When ON a logic 0 is selected ON m When OFF a logic 1 is selected Switch 2 has the following options 2 FPGA2 MSEL 2 When a logic 0 is selected OFF m When OFF a logic 1 is selected 3 ON Switch 4 has the following options 4 FPGA2_MSEL 4 When a logic 0 is selected OFF m When OFF a logic 1 is selected Note to Table 4 1 1 Ensure that all MSEL setting are in a defined configuration s
68. u have difficulty installing the Quartus II software refer to Altera Software Installation and Licensing Manual Licensing Considerations Purchasing this kit entitles you to a one year license for the Development Kit Edition DKE of the Quartus II software After the year your DKE license will no longer be valid and you will not be permitted to use this version of the Quartus II software To continue using the Quartus II software you should download the free Quartus II Web edition or purchase a subscription to Quartus II software Before using the Quartus II software you must activate your license identify specific users and computers and obtain and install a license file If you already have a licensed version of the subscription edition you can use that license file with this kit If not you need to obtain and install a license file To begin go to the Self Service Licensing Center page of the Altera website log into or create your myAltera account and take the following actions 1 On the Activate Products page enter the serial number provided with your development kit in the License Activation Code box November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 3 2 Chapter 3 Software Installation Installing the Quartus Subscription Edition Software Ka Your serial number is printed on the development kit box below the bottom bar code The number is 10 or 11 alphanumeric characters and does not co
69. u last clicked Start m TXandRX performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve m Tx MBps and Rx MBps Show the number of bytes of data analyzed per second The Power Monitor The Power Monitor measures and reports current power information for the board To start the application click Power Monitor in the Board Test System application 7 You can also run the Power Monitor as a stand alone application PowerMonitor exe resides in the install dir NkitsNarriaV GT 5agtfd7kf40 fpgaNexamplesVboard test system directory On Windows click Start gt All Programs gt Altera gt Arria V GT FPGA Development Kit version Power Monitor to start the application November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide 6 24 Chapter 6 Board Test System The Power Monitor The Power Monitor communicates with the MAX II device on the board through the JTAG bus A power monitor circuit attached to the MAX II device allows you to measure the power that the Arria V GT FPGA is consuming Figure 6 10 shows the Power Monitor Figure 6 10 The Power Monitor I Power Monitor 5 Em xl ANU S RYA General Information Power Information MAX II Version 10 RMS Maximum Minimum Power Rail A54 xcv Gxe connections USB Blaster on sd hwlab 1 USB 0 5M 12702F324 22102 221 063 Th
70. ures Each design provides data for one or more tabs in the application The Configure menu identifies the appropriate design to download to the FPGA for each tab After successful FPGA configuration the appropriate tab appears and allows you to exercise the related board features Highlights appear in the board picture around the corresponding components The Power Monitor button starts the Power Monitor application that measures and reports current power information for the board Because the application communicates over the bus to the MAX II device you can measure the power of any design in the FPGA including your own designs To use the Power Monitor GUI the MAX II device needs to be programmed with the default factory MAX II design The Board Test System and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the SignalTap II Embedded Logic Analyzer Because the Quartus II programmer uses most of the bandwidth of the JTAG bus other applications using the JTAG bus might time out Be sure to close the other applications before attempting to reconfigure the FPGA using the Quartus II Programmer Preparing the Board With the power to the board off follow these steps 1 Connect the USB cable to the board 2 Ensure that the Ethernet patch cord is plugged into the RJ45 connector 3 Ensure that the development board switches and jumpers are set to the default positions as shown in the Facto
71. ye Connector 2 2 2 6 28 Appendix A Programming the Flash Memory Device CFI Flash Memory Map ettet e ea aia Meine en e decern A 1 Preparing Design Files for Flash Programming A 2 Creating Flash Files Using the Nios EDS A 2 Programming Flash Memory Using the Board Update Portal A 2 Programming Flash Memory Using the Nios A 3 Restoring the Flash Device to the Factory Settings A 4 Restoring the MAX II CPLD to the Factory Settings A 5 Additional Information Document Revision ElistOty ence 9 eee aee ees ree e E e ReneS Info 1 Howto Contact Alteri eas reet tei deb Rasse E E brides Info 1 Typographic Conventions Info 1 November 2012 Altera Corporation Arria V GT FPGA Development Kit User Guide vi Contents Arria V GT FPGA Development Kit November 2012 Altera Corporation User Guide N SYN 1 About This Kit The Altera Arria V GT FPGA Development Kit is a complete design environment that includes both the hardware and software you need to develop Arria V GT FPGA designs Kit Features This section briefly describes

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