Integrator/IM-PD1 User Guide
Contents
1. Red Line Out L Line Out R Line In L Yellow SI Line In R Figure 3 12 Supplied audio cable Note For correct operation of the CODEC interface you must mute the PC Beep input by setting bit 15 in the PC Beep register within the CODEC see the LM4549 datasheet available from National Semiconductors ARM DUI 0152C Copyright O 2001 All rights reserved 3 13 Hardware Reference 3 7 MMC and SD flash card interface Figure 3 13 shows the MMC and SD flash card interface that can be driven as both an MMC or SD interface A suitable MMC interface is the PrimeCell MMCI PL181 e MCI_1 gt e MCI 2 gt MCI_5 3 g e MCI_7 gt Mc s J9 a r x x D MCLO e MCI_nCARDIN la MCI_WPROT Figure 3 13 MMC SD The function of the interface signals depend on whether an MMC or SD card is fitted Both card types default to MMC but the SD card has an additional operating mode called widebus mode Table 3 7 shows the use of the signals for both modes of operation Table 3 7 MMC SD interface signals Signal name EXPIM connector Widebus mode MMC mode nMCI_ON IM BBANK7 Controls card power Controls card power LOW z power ON LOW z power ON HIGH power OFF HIGH power OFF MCI 1 IM BBANK8 Card detect Data 3 Chip select active LOW MCI 2 IM BBANK9 Command Response Command Response MCI 5 I2. DILL DD DILL 0000000000000000000 0000000000000000000 guuuuuuuuummuuuuuuu co eo eo d Figure A 4 J19 pin locations Table A 4 shows the pinout of the logic analyzer connector Table A 4 J19 connector pinout Signal Pin Pin Signal No connect 1 2 No connect GND 3 4 No connect SYSCLK 5 6 CLK1 B31 7 8 B15 B30 9 10 B14 B29 11 12 B13 B28 13 14 B12 B27 15 16 B11 B26 17 18 B10 B25 19 20 B9 B24 21 22 B8 B23 23 24 B7 A 8 Copyright 2001 All rights reserved ARM DUI 0152C Signal Descriptions Table A 4 J19 connector pinout continued Signal Pin Pin Signal B22 25 26 B6 B21 27 28 B5 B20 29 30 B4 B19 31 32 B3 B18 33 34 B2 B17 35 36 B1 B16 37 38 BO ARM DUI 0152C Copyright 2001 All rights reserved A 9 Signal Descriptions AAT Multi ICE JTAG Figure A 5 shows the pinout of the Multi ICE connector J21 For a description of the JTAG signals see the user guide for your logic module 3V3 3V3 nTRST GND TDI GND TMS GND TCK GND RTCK GND TDO GND nSRST GND GND GND Figure A 5 Multi ICE connector pinout A 10 Copyright 2001 All rights reserved ARM DUI 0152C Appendix B Mechanical Specification This appendix contains the mechanical specification for Integrator IM PD1 It contain
3. ARM DUI 0152C Copyright 2001 All rights reserved A 5 Signal Descriptions A 3 EXPIM This connector is the same type of as that used for EXPA Figure A 3 shows the pin numbers for the EXPIM socket on the interface module 1 Cen 2 GND 3 IM BO 4 IM BT 5 IM B2 6 GND 7 IM B3 8 IM B4 9 IM B5 10 GND IM B6 12 IM B7 13 IM B8 14 GND 15 IM BS 16 IM BO 17 MBT 18 GND 19 MBZ 20 IM Bi3 21 T IM Bi4 22 GND 23 MB 24 IM Bi6 25 IM Bi7 26 GND 27 IM B8 28 IM B9 29 IM B20 30 GND 31 MBZ 32 IM B22 33 IM B23 34 GND 35 IM B24 36 IM B25 37 IM B26 38 GND 39 IM B27 40 IM B28 41 IM B29 42 GND 43 IM B30 44 IM B3T 45 IM B32 46 GND 47 IM B33 48 IM B34 49 IM B35 50 GND 51 IM B36 52 IM B37 53 IM B38 54 GND 55 IM B39 56 1M_B40 57 IM B4T 58 GND 59 IM B42 60 IM B43 61 WE 62 GND 63 IM B45 64 IM B46 65 IM B48 66 GND 67 IM B48 68 IM B49 69 IM B50 70 GND n IM B5T 72 IM B52 73 IM B53 74 GND 75 IM B54 76 IM B55 77 IM B56 78 GND 79 1M_B57 80 IM B58 81 IM B59 82 GND 83 IM B60 84 IM B6T 85 EXP185 86 GND 87 EXP187 88 EXP188 89 EXP189 90 GND 91 EXP191 92 EXP192 93 EXP193 94 EXP194 95 EX
4. Bits Name Access Function 7 4 RESERVED 3 TOUCHSCREENSELECT Read write This bit is used to select the touch screen controller 0 Use PLO22 and PLO61 PrimeCells to control touchscreen e 2 Use the TSCI to control the touch screen 2 DISPLAY ENABLE Read write This bit enables and disables the selected display 0 DISABLED ENABLED 1 0 DISPLAY SELECT Read write These bits control the display outputs 00 Sharp 8 4 inch display 012 VGA SVGA monitor 10 2 LCDI connector 11 Reserved Note When the TSCI is used to control the touchscreen the SSP signals are routed to the prototyping area on the logic module Table 4 8 shows the assignment of the SSP signals to the prototyping grid when the TSCI is selected Table 4 8 Assignment of SSP signals to module prototyping holes Prototyping S I Hen hole SSPTXD C13 SSPCLKOUT D13 SSPFSS E13 SSPRXD F13 ARM DUI 0152C Copyright 2001 All rights reserved 4 11 Reference Design Example 4 2 7 Touch screen controller interface registers The mapping of the TSCI registers is shown in Table 4 9 Table 4 9 Touch screen controller registers Offset address Name Type Function 0x0000000 TS CON Read write Control register 0x0000004 TS AUTORDXY Read X Y auto read register 0x0000008 Reserved Touch screen control register Table 4 10 describes the operation of this register Table 4 10 TS CON re
5. C Care of modules 1 8 CE Declaration of Conformity ii CONFIG link 1 3 1 7 Connecting Multi ICE 2 5 Connectors audio DIN 3 13 backlight J32 3 23 display interface J27 3 20 EXPB A 4 EXPIM A 6 logic analyzer A 8 MMC SD card 3 15 MMC SD 333 3 16 Multi ICE A 10 RS232 3 8 touchscreen J31 3 22 USB 3 11 D Diagnostic connectors A 8 Display interface bias control 3 18 Display interface control signals 3 17 Display interface signal routing 1 4 Display interface description 3 17 Display support 1 4 E Example memory map 4 6 F FPGA signal routing 3 2 Infrared interface 3 6 Integrator system memory map 4 6 Integrator IM PD1 layout 1 3 L LCD1 connector 1 3 Logic analyzer connector A 8 Logic module registers 4 7 ARM DUI 0152C Copyright 2001 All rights reserved Index 1 Index M Memory map example 4 6 MMC card 3 15 MMC connector 1 3 MMC interface 3 14 MMC SD card socket 3 15 Multi ICE JTAG connector 1 3 A 10 Multi ICE connecting 2 5 O Oscillator divisor registers 4 7 Oscillator lock register 4 9 P Peripheral signals routing 1 4 PrimeCell AACI PLO41 3 12 PrimeCell CLCD controller PL110 3 17 PrimeCell GPIO PL061 3 24 PrimeCell MMCI PL181 3 14 PrimeCell SCI PL130 3 3 PrimeCell SSP PLO21 3 21 PrimeCell UART PLO11 3 6 3 7 Push button interrupt register 4 10 R Registers LM_CONTROL 4 10 LM_INT 4 7 LM_LEDS 4 7 LM_LOCK 4 7 LM OSCI 4 7 LM
6. L1 Samtec SOLC series VCosansune 2 5 Figure A 1 shows the how the pins on the EXPA socket on the on underside of the interface module are numbered Figure A 1 EXPA socket pin numbering Copyright O 2001 All rights reserved ARM DUI 0152C Signal Descriptions The signals present on the EXPA connector are described in Table A 1 Table A 1 AHB signal assignment Pinlabel Signal Description A 31 0 Notused B 31 0 B 31 0 These signals connect to the FPGA on the logic module They are used to carry display interface signals see Display interface on page 3 17 C 31 0 Notused D 31 0 Notused ARM DUI 0152C Copyright 2001 All rights reserved A 3 Signal Descriptions A 2 EXPB Figure A 2 shows the pin numbers of the EXPB socket on the underside of the inteface module Figure A 2 EXPB socket pin numbering Table A 2 describes the signal
7. Multi ICE User Guide ARM DUI 0048 Other publications This section lists relevant documents published by third parties LM4549 AC 97 Rev 2 1 Codec with Sample Rate Conversion and National 3D Sound Data sheet DS101035 available at http www national com pf LM LM4549 html IRMS6400 and IRMT6400 4 Mb s Infrared Data Transceiver Data sheet IRMS6400 IRMT6400 available at Copyright 2001 All rights reserved ARM DUI 0152C Preface http www infineon com cmc upload 0 000 019 200 IRMS T6400 pdf PDIUSBPI1A Universal Serial Bus Transceiver Data sheet 853 2008 21712 available at http www us6 semiconductors com acrobat data sheets PDIUSBP11A 2 pdf DAC Controlled Boost Inverter LCD Bias Supply with Internal Switch Data sheet 19 1327 available at http pdfserv maxim ic com arpdf MAX686 pdf ARM DUI 0152C Copyright 2001 All rights reserved xi Preface Feedback ARM Limited welcomes feedback on both the Integrator IM PD1 and its documentation Feedback on this document If you have any comments on this book please send email to errata arm com giving the document title the document number the page number s to which your comments apply a concise explanation of your comments General suggestions for additions and improvements are also welcome Feedback on the Integrator IM PD1 If you have any comments or suggestions about this product please contact your supplier giv
8. see the schematic diagram for more details 3 20 Copyright O 2001 All rights reserved ARM DUI 0152C Hardware Reference 3 9 Touchscreen controller The touchscreen interface is designed to connect to a 4 wire resistive touchscreen It can be driven by the PrimeCell SSP PL021 PrimeCell SSP PL022 or similar peripheral Figure 3 20 shows the touch screen interface The signals to the touchscreen are routed to the 50 pin connector J27 and also to J31 TS DCLK ADS7843 ui e 9 x o o o a x D Figure 3 20 Touch screen interface The touch screen interface uses an Analog Devices ADS7843 U9 controller to provide an interface with a 4 wire resistive touch screen It communicates with the host using a serial interface The host interface signals are shown in Table 3 8 Table 3 8 Touch screen host interface signal assignment Signal name EXPIM connector Description TS DIN IM BBANKAI Serial data input to controller TS nCS IM BBANK42 Controller chip select TS DCLK IM BBANK43 Clock input to controller TS DOUT IM BBANK44 Data output from controller TS BUSY IM BBANKA45 Busy indicator from controller TS nPENIRQ IM BBANKA46 Interrupt from controller ARM DUI 0152C Copyright 2001 All rights reserved 3 21 Hardware Reference Figure 3 21 shows the pinout of the connector J31 TS YP TS XP TS YN TS XN Figure
9. 3 21 J31 pinout 3 22 Copyright O 2001 All rights reserved ARM DUI 0152C Hardware Reference 3 10 Backlight control The interface module provides an adjustable LCD backlight voltage controlled by the 2kQ potentiometer R153 This enables you to adjust the BL_ADJ output between 0V and 2 5V This is available from the connector J32 Figure 3 22 shows the pinout of J32 12V 12V GND GND 5V BL_ADJ gt 8 Figure 3 22 Backlight connector pinout ARM DUI 0152C Copyright 2001 All rights reserved 3 23 Hardware Reference 3 11 Push buttons The interface module is fitted with six push buttons These can be monitored using a PrimeCell GPIO PL061 or other suitable peripheral Each switch is a normally open type and is connected to the EXPIM connector through inverters so that pressing the button drives the associated input to the GPIO HIGH Table 3 9 shows the assignment of the push button inputs to the EXPIM connector Table 3 9 Push button interface signal assignment Signal name EXPIM connector Description PBO IM BBANKI Input from S1 PB1 IM BBANK2 Input from S2 PB2 IM BBANK3 Input from S3 PB3 IM BBANK4 Input from S4 PB4 IM BBANK5 Input from S5 PRS IM BBANK6 Input from S6 3 24 Copyright O 2001 All rights reserved ARM DUI 0152C Hardware Reference 3 12 Buzzer The buzzer on the interface module ca
10. Chapter 3 Hardware Reference This chapter describes the hardware on the interface module The descriptions assume that PrimeCell peripherals are being used to control these interfaces This chapter contains the following sections Differences in signal naming between supported logic modules on page 3 2 Smart card interface on page 3 3 IrDA interface on page 3 6 UART interface on page 3 7 USB interface on page 3 10 Audio CODEC on page 3 12 MMC and SD flash card interface on page 3 14 Display interface on page 3 17 Touchscreen controller on page 3 21 Backlight control on page 3 23 Push buttons on page 3 24 Buzzer on page 3 25 ARM DUI 0152C Copyright 2001 All rights reserved 3 1 Hardware Reference 3 1 Differences in signal naming between supported logic modules The Integrator LM XCV600E and Integrator LM EP20K600E logic module types route the signals between the FPGA and the interface module differently as follows the LM XCV600E is fitted with a Xilinx FPGA and routes the interface module ABANK 57 0 signals to bank O on the FPGA and the BBANK 12 0 signals to bank 1 on the FPGA the LM EP20K600E is fitted with an Altera FPGA and routes the interface module ABANK 57 0 signals to bank 5 on the FPGA and the BBANK 12 0 signals to bank 6 on the FPGA The logic module output voltage on these banks is adjustable Ensure that the logic module selection link is set to the 3V3 position Note These
11. OSC2 4 7 LM SW 4 7 RS232 connectors 1 3 RS232 interface 3 7 S SD flash card interface 3 14 Serialinterface 3 7 Serial interface connector assignment 3 8 Sharp TFT connector 1 3 Smartcard connectors 1 3 Smartcard contacts 3 4 Smartcard interface description 3 3 Smartcard signal assignment 3 4 Smartcard voltage select link 1 3 1 7 3 3 Smartcard J34 pinout 3 5 Switches register 4 10 T Touchscreen connector 3 22 Touchscreen interface description 3 21 U UART interface 3 7 USB connectors 1 3 3 11 USB interface description 3 10 USB speed selectlink 1 3 1 7 3 11 User buttons 3 24 User LEDs control register 4 9 V VGA socket 1 3 Index 2 Copyright 2001 All rights reserved ARM DUI 0152C
12. each different interrupt source The software can control each request line to generate software interrupts 4 4 Copyright O 2001 All rights reserved ARM DUI 0152C Reference Design Example 4 2 2 Supplied VHDL files Table 4 1 provides a summary description of the supplied VHDL files A more detailed description of each VHDL block is included within the files in the form of comments Table 4 1 VHDL file descriptions File Description AHBTop vhd This file is the top level VHDL that instantiates all of the PrimeCells for the example The VHDL for the PrimeCells themselves are not supplied but are available from ARM as separate products AHBDecoder vhd The decoder block provides the high speed peripherals with select lines These are generated from the address lines and the module ID position in stack signals from the motherboard The decoder block also contains the default slave peripheral to simplify the example structure The Integrator family of boards uses a distributed address decoding system see Address assignment of logic modules on page 4 7 AHBMux8S1M vhd This is the AHB multiplexor that connects the read data buses and the HRESP and HREADY signals from all of the slaves to the AHB master AHBZBTRAM vhd High speed peripherals require SSRAM controller block to support word halfword and byte operations to the SSRAM on the logic module AHB2APB vhd This is the bridge block requi
13. pin assignments are contained in the example pin constraints file on the CD that accompanies the interface module 3 2 Copyright O 2001 All rights reserved ARM DUI 0152C Hardware Reference 3 2 Smart card interface Figure 3 1 shows the architecture of the Smart Card Interface SCI This provides a suitable interface for the PrimeCell SCI PL130 or similar peripheral The diagram shows the tristate buffers that are used to provide the interface between the SCI and the card itself An additional 10 way box header J34 is provided to enable you to monitor the signals or to connect an off board smartcard connector SC nRESET SC nRESET SC V Smartcard socket SC nSCICLKOUTEN O SC_nSCIDATAOUTEN SC_SCICLKIN SC_SCIDATAIN You can set the SCI to operate at 3 3V or at 5V by setting the solder link LK2 The default setting is 5V et o Xx o o o a x Figure 3 1 Smart card interface ARM DUI 0152C Copyright O 2001 All rights reserved 3 3 Hardware Reference The signals associated with the SCI are assigned to the EXPIM socket pins as shown in Table 3 1 Table 3 1 Smartcard signal assignment Signal name EXPIM connector Description SC SCICLKIN IM BBANK34 Clock input to controller SC SCIDATAIN IM BBANK35 Serial data input to controller SC nSCIDATAOUTEN IM BBANK26 Data output enable SC nSCICLKOUTEN IM BBANK37 Clock buffer output control SC SCICLKOUT IM BBANK38 Clock output fro
14. the modules in the stack on which the interface module is mounted ARM DUI 0152C Copyright 2001 All rights reserved 1 5 Introduction Push LA connector B bus 419 buttons Video DAC MMC SD J9 VGA J30 Host USB USBO J11 USB1 J13 EXPA Socket Device Buffer USB Sharp 8 4 TFT J14 3V3 ON OFF UART 0 Serial O J12A Serial 1 J12B Buffer EXPIM Socket ES KR a 23 2 c o o ge o D o 5 o o c bal Q O 2 Audio J6 J7 J8 J29 Bias Touchscreen adjust controller n c Ze Touchscreen J31 IrDA transceiver EXPB Socket Smartcard interface Figure 1 2 Integrator IM PD1 block diagram 1 6 Copyright O 2001 All rights reserved ARM DUI 0152C Introduction 1 3 Links The interface module provides four links CONFIG link J22 Buzzer enable link J23 USB device port speed select link LKI Smartcard voltage select link LK2 1 3 1 CONFIG link J22 The CONFIG link is a jumper type link that is used to enable and disable config mode Fitting the CONFIG link places the modules in the stack onto which the interface module is mounted into CONFIG mode there are no components on the interface module that use Multi ICE This mode enables you to reprogram the FPGA image in the configuration flash on the logic module s in the stack using Multi ICE see the user guide for the logic module The CONFIG LED lights to indicate th
15. the locations to which logic modules are assigned by the main address decoder on the motherboard The diagram also shows how the example decodes the address space for the logic module when it is LMO bottom of the stack Refer to the release notes shipped with the example for more information OxCFFFFFFF 0xE0000000 0xD0000000 0xC0000000 peripherals Core module alias memory 0xC1000000 LM registers c0000000 Core module motherboard memory and peripherals Figure 4 2 Integrator system memory map Note The Integrator system implements a distributed address decoding scheme in which each core or logic module is responsible for decoding its own address space It is important when implementing a logic module design to ensure that the module responds to all memory accesses in the appropriate memory region see the user guide for your motherboard 4 6 Copyright O 2001 All rights reserved ARM DUI 0152C Reference Design Example 4 2 5 Address assignment of logic modules You can mount up to four logic modules on an Integrator AP motherboard The base address of each logic module depends on its position in the stack This defines the value of bits 31 28 of the address of devices on the logic module as shown in Table 4 2 Table 4 2 Logic module addresses Position Bits 31 28 0 bottom 0xC 1 0xD 2 OxE 3 top OxF 4 2 6 Example APB register peripheral Table 4 3 shows the mapping of the l
16. written for all developers who are using the Integrator IM PD1 interface module with an Integrator LM XCV600E or LM EP20K600E logic module to develop ARM based devices It assumes that you are an experienced developer and that you are familiar with the ARM development tools Using this book This book is organized into the following chapters Chapter 1 Introduction Read this chapter for an introduction to the Integrator IM PD1 interface module This chapter describes the main features of the interface module and identifies the main components Chapter 2 Getting Started Read this chapter for information about preparing the interface module for use with a logic module Chapter 3 Hardware Reference Read this chapter for a description of the interface module hardware Chapter 4 Reference design example Read this chapter for a description of the example logic module configuration supplied that allows you to experiment with the interface module Appendix A Signal Descriptions Read this appendix for connector pinout information Appendix B Mechanical Specification Refer to this appendix for mechanical details of the Integrator IM PD1 viii Copyright O 2001 All rights reserved ARM DUI 0152C Preface Typographical conventions Further reading The following typographical conventions are used in this book italic Highlights important notes introduces special terminology denotes internal cross references and citations b
17. Integrator IM PD1 User Guide ARM Copyright O 2001 All rights reserved ARM DUI 0152C Integrator IM PD1 User Guide Copyright O 2001 AII rights reserved Release Information Date Issue Change June 2001 A Initial issue July 2001 B Corrections to Table 3 3 on page 3 7 July 2001 C Corrections to Appendix A Proprietary Notice Words and logos marked with or are registered trademarks or trademarks owned by ARM Limited except as otherwise stated below in this proprietary notice Other brands and names mentioned herein may be the trademarks of their respective owners Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder The product described in this document is subject to continuous developments and improvements All particulars of the product and its use contained in this document are given by ARM in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product Conforman
18. M BBANKIO CLK CLK MCI 7 IM BBANKII Data 0 Data MCI 8 IM BBANKI2 Data 1 not used 3 14 Copyright O 2001 All rights reserved ARM DUI 0152C Hardware Reference Table 3 7 MMC SD interface signals continued Signal name EXPIM connector Widebus mode MMC mode MCI 9 IM BBANKI3 Data 2 not used MCI nCARDIN M BBANKI4 Card presence detect active LOW Card presence detect active LOW MCI WPROT IM BBANKI5 Card write protection detect Card write protection detect The MMC SD card socket J9 provides nine pins that connect to a card when it is inserted into the socket Figure 3 14 shows the pin numbering and signal assignment In addition the socket contains switches that operated are by card insertion and provide signaling on the MCI nCARDIN and MCI WPROT signals 876543219 MCI 8 MCI 9 MCI 7 1 MCI 1 TT Li B GND MCI 2 MCI 5 GND MCI PWR Figure 3 14 MMC SD card socket pin numbering The MMC card uses seven pins and the SD card uses all nine pins The additional pins are located as shown in Figure 3 14 with pin 9 next to pin 1 and pins 7 and 8 spaced more closely together than the other pins Figure 3 15 shows an MMC card with the contacts face up 1234567 Figure 3 15 MMC card ARM DUI 0152C Copyright 2001 All rights reserved 3 15 Hardware Reference Insert the card into the socket with the contacts face down Cards are nor
19. N Audio CODEC LINE LEV OUT L CODEC ar U2 CODEC LINE LEV OUT R gt E a AACL RESET gt CODEC MEI 2 CODEC MIC2 S E r 19 CODEC AUX R Se CODEC AUS L S Figure 3 10 Audio interface The signals associated with the audio CODEC interface are assigned to the EXPIM socket pins as shown in Table 3 6 Table 3 6 Audio CODEC signal assignment Signal name EXPIM connector Description AACI SDATA OUT IM_ABANK8 Serial data from AACI to the CODEC AACI BIT CLK IM ABANK9 Clock from the CODEC AAC SYNC IM ABANKIO Frame synchronization signal from the AACI AACI SDATA IN IM ABANKII Serial data from the CODEC to the AACI AACI RESET IM ABANKI2 Reset signal from the PrimeCell AACI 3 12 Copyright O 2001 All rights reserved ARM DUI 0152C Hardware Reference Note For a description of the audio CODEC signals refer to the LM4549 datasheet available from National Semiconductors The interface module provides three jack plugs that allow you to connect to the microphone and auxiliary inputs and line level output on the CODEC Stereo inputs and outputs are also provided by a 5 pin 180 DIN socket Figure 3 11 shows the pinout of the DIN socket CODEC LINE OUT L CODEC LINE IN L CODEC LINE OUT R CODEC LINE IN R SCREEN Figure 3 11 Audio DIN connector pinout A cable is supplied with the interface module to enable you to connect audio devices with phono sockets to the DIN socket This cable is shown in Figure 3 11
20. O U D Sharp LQ084V1DG2 J14 Figure 3 17 Display interfaces ARM DUI 0152C Copyright 2001 All rights reserved 3 17 Hardware Reference The interface module provides two power outputs for the display interfaces as shown in Figure 3 18 These are LCD1_BIAS LCD 3V3 1 control IC IRF7306 Di LCD1 BIAS U18 U21 G1 DN o x O o 10 lt x D gt lt LI S2 IRF7306 LCD 3V3 U21 G2 EXPB socket Figure 3 18 LCD1 power supply control LCD1_BIAS is a variable supply controlled by the MAX686 DAC IC U18 and switched ON and OFF by the MOSFET switch U21 LCD1_BIAS is varied between 11 5V and 24V in 64 steps using the inputs on pins B30 and B31 on the EXPA socket These are edge triggered inputs The MAX686 is reset to the midpoint by a power on reset The MOSFET switch is controlled by the input from B29 LCD 3V3 is fixed level power output that is controlled by a second MOSFET switch within U21 The switch is controlled by the input on the pin F31 on the EXPB connector The interface module provides two connectors One J14 is a dedicated connector for a 8 4 inch Sharp LCD display and the second J27 provides a generic interface Figure 3 19 on page 3 20 shows the pinout of connector J27 3 18 Copyright 2001 All rights reserved ARM DUI 0152C Hardware Reference Note If the logic module is mounted in the EXPA EXPB position on an Integrator AP the pins
21. P195 96 EXP196 97 EXP197 98 EXP198 99 1V8 100 1V8 Figure A 3 EXPIM socket pin numbering A 6 Copyright 2001 All rights reserved ARM DUI 0152C Signal Descriptions Table A 3 shows the signals for the interface module for Integrator LM XCV600E or LM EP20K600E logic module types Table A 3 EXPIM signal assignment Label LM XCV600E LM EP20K600E Description IM ABANK 12 0 IM_0BANK 12 0 IM SBANK 12 0 FPGA input output pins IM BBANK 57 0 IM I1BANK 57 0 IM 6BANK S7 0 FPGA input output pins EXP 96 85 Not used Not used EXP97 VCCO 0 VCCO 5 Configurable voltage power supply rail Not used socket EXP98 VCCO 0 VCCO 5 Configurable voltage power supply rail Not used socket EXP185 Not used Not used EXP 189 187 Not used Not used EXP191 CLK1 1 CLK1 1 Clock signal from the CLK1 buffer on the logic module EXP 196 192 Not used Not used EXP197 VCCO 1 VCCO 6 Configurable voltage power supply rail Not used socket EXP198 VCCO 1 VCCO 6 Configurable voltage power supply rail Not used socket Caution For correct operation of the interface module VCCO A and VCCO B must be set to 3 3V Ensure that the VCCO links are set correctly on the logic module ARM DUI 0152C Copyright 2001 All rights reserved A 7 Signal Descriptions AA Logic analyzer connector Figure A 4 shows the pin numbers of this type of connector n2
22. RT1 interrupt controller PL190 ao ao 20 GPIOO Address decoder GPIO1 d Q S CLCD controller M ZBT SSRAM controller MMCI AACI TSCI Figure 4 1 Design example ARM DUI 0152C Copyright 2001 All rights reserved A 3 Reference Design Example Note The example FPGA image shipped with the board does not contain all of the peripherals shown in Figure 4 1 on page 4 3 Universal serial bus Connectors and circuitry are provided for the two USB boxes shown in Figure 4 1 on page 4 3 However there are no USB PrimeCells currently available from ARM Limited These blocks can be licensed from other IP providers Vectored interrupt controller The PrimeCell PL190 Vectored Interrupt Controller VIC provides a software interface to the interrupt system In an ARM system two levels of interrupt are available Fast Interrupt Request FIQ for fast low latency interrupt handling Interrupt ReQuest IRQ for more general interrupts Only a single FIQ source at a time is generally used in a system to provide a true low latency interrupt This has the following benefits You can execute the interrupt service routine directly without determining the source of the interrupt Interrupt latency is reduced You can use the banked registers available for FIQ interrupts more efficiently because a context save is not required There are 32 interrupt lines The VIC uses a bit position for
23. SIR TXD IM BBANK56 Transmit data SIR RXD IM BBANK57 Receive data 3 6 Copyright O 2001 All rights reserved ARM DUI 0152C 3 4 UART interface EXPIM Socket Hardware Reference The interface module provides two serial transceivers suitable for use with the PrimeCell UART PLO11 or other similar peripherals Figure 3 5 shows the architecture of one UART interface channel UARTO TXD UARTO_RTS UARTO DTR AE UARTO_RXD ZA UARTO DCD IZ UARTO_DSR AA t UARTO CTS UARTO RI AA MAX3243E RS232 transceiver U4 SERO_TXD ML SERO RTS SERO_DTR gt SERO_RXD AE SERO DCD 4 SERO DSR Sees SERO_CTS A Le SEROR Figure 3 5 Serial interface one channel The signals associated with the UART interface are assigned to the EXPIM socket pins as shown in Table 3 3 Table 3 3 Serial interface signal assignment Signal name EXPIM connector Description UARTO TXD IM BBANK47 Transmit data UARTO RTS IM BBANK48 Ready to send UARTO DIR IM BBANK49 Data terminal ready UARTO CTS IM BBANK50 Clear to send UARTO DSR IM BBANKS5I Data set ready UARTO DCD IM BBANK52 Data carrier detect UARTO RXD IM BBANK53 Receive data UARTO RI IM BBANK54 Ring indicator UART1 TXD IM ABANKO Transmit data ARM DUI 0152C Copyright 2001 All rights reserved Hardware Reference Table 3 3 Serial interface s
24. ansceivers e IrDA transceiver Multi ICE connector logic analyzer connector connected to the B bus six push buttons buzzer 1 2 2 Architecture Figure 1 2 on page 1 6 shows the architecture of the interface module The routing of the various interface signals from the logic module is as follows e The peripheral input output devices are connected to the FPGA on the logic module using the EXPIM socket that connects to EXPIM plug on the logic module The display interfaces are connected to the FPGA on the logic module using the B bus pins on the EXPA socket and one F bus pin on the EXPB socket The logic module FPGA supplies the pixel data and control signals for the display interface buffers The B bus can be monitored with a logic analyzer connected to J19 Note If the logic module is mounted in the EXPA EXPB position on an Integrator AP the pins marked F bus connect to the GPIO bus on the Integrator AP This bus is routed between the system controller FPGA on the motherboard and the FPGA on the logic module These signals are available for your own applications 1 4 Copyright O 2001 All rights reserved ARM DUI 0152C Introduction Ifthe logic module is mounted in the HDRA HDRB position on the motherboard these pins connect to the F bus that is routed between any modules in the stack there are no signals from the motherboard present on these pins The Multi ICE connector enables you to gain access to the JTAG signals on
25. at the stack is in CONFIG mode 1 3 2 Buzzer enable link J23 The buzzer enable link is a jumper type link used to connect and disconnect the buzzer see Buzzer on page 3 25 1 3 3 USB device port speed select link LK1 The USB speed select link is a soldered link that is used to set the operating speed of the USB device port see USB interface on page 3 10 1 3 4 Smartcard voltage select link LK2 The smartcard voltage select link is a soldered link that is used to set the operating voltage of the smartcard interface see Smart card interface on page 3 3 ARM DUI 0152C Copyright 2001 All rights reserved 1 7 Introduction 1 4 Care of modules This section contains advice about how to prevent damage to your Integrator modules Caution To prevent damage to your Integrator system observe the following precautions When removing a core or logic module from a motherboard or when separating modules take care not to damage the connectors Do not apply a twisting force to the ends of the connectors Loosen each connector first before pulling on both ends of the module at the same time Use the system in a clean environment and avoid debris fouling the connectors on the underside of the PCB Blocked holes can cause damage to connectors on the motherboard or module below Visually inspect the module to ensure that connector holes are clear before mounting it onto another board Observe ElectroStatic Discharg
26. ce eet piece Eege dei dede Ann dati dra aede cc 3 7 3 5 USB nterface mene eeh E 3 10 3 6 Audio CODEC Luca fete ec dtes e ettet 3 12 ARM DUI 0152C Copyright 2001 All rights reserved V Contents Chapter 4 Appendix A Appendix B 3 7 MMC and SD flash card interface ccccccccccccnncnininananinananananrnoncnnnononons 3 14 3 8 Display Interface cia 3 17 3 9 Touchscreen controller sas e oet ner ir n 3 21 3 10 Backlight corntfol eite et ca ae Saleen 3 23 3 11 PUSH buttons acce et tete cbe cete rode az 3 24 3 12 BUZZ ec er 3 25 Reference design example 4 1 About the design example ss 4 2 4 2 Desigri exa mple 42 tot dote cadet ecce ib 4 3 Signal Descriptions A 1 EXPA qa AA tl A 2 A 2 EXPB nacio eite ecc A 4 A 3 STT A 6 A 4 Logic analyzer Connector eee A 8 Mechanical Specification B 1 Mechanical information rto iia Marec vada d B 2 vi Copyright O 2001 All rights reserved ARM DUI 0152C Preface This preface introduces the Integrator IM PD1 interface module and its user documentation It contains the following sections About this book on page viii Feedback on page xii ARM DUI 0152C Copyright 2001 All rights reserved vii Preface About this book This book provides user information for the ARM Integrator IM PD1 interface module It describes the major and how to use the interface module with an Integrator development platform Intended audience This book is
27. ce Notices This section contains conformance notices Federal Communications Commission Notice This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15 103 c Confidentiality Status This document is Open Access This document has no restriction on distribution Product Status The information in this document is final information on a developed product Copyright O 2001 All rights reserved ARM DUI 0152C Web Address http www arm com ARM DUI 0152C Copyright 2001 All rights reserved Copyright O 2001 All rights reserved ARM DUI 0152C Contents Integrator IM PD1 User Guide Chapter 1 Chapter 2 Chapter 3 Preface Aboutthis BOOK aii ta viii Eeedback i TT xii Introduction 1 1 About the Integrator IM PD1 ss 1 2 1 2 Interface module features and architecture 1 4 1 3 Tr c MR RE 1 7 1 4 Care of modules inner 1 8 Getting Started 2 1 Setting up the logic module c oococncccncccinccnnnonanccnoncanonnn occ narco 2 2 2 2 Fitting the interface module rra 2 3 2 3 Connecting Multi ICE or other JTAG equipment occccncccincconcccnoccnancnnanccnnnons 2 5 Hardware Reference 3 1 Differences in signal naming between supported logic modules 3 2 3 2 Smart card lu CEET 3 3 3 3 IrDA interface ressenti datent nine 3 6 3 4 UART interfa
28. e CONFIG LED 3 J7 b 00 d Off PCB MMC SD a Line level connector J33 o o ES Y out J6 Lu on SP oad S EH AUX in og ELE J8 LA connector Gs 00 Y for B bus J19 4 o ood oa oo Audio Multi ICE DIN socket J21 oo J29 oa LCD1 and nu touchscreen zm GANE 427 Si oo monitor socket User switches Off PCB smartcard Buzzer connector J34 enable link J23 Smart card voltage select link LK2 Buzzer EH Sharp 8 4 TFT EB 414 Ds Ed BE Smart card Jo x RS232 socket J10 J12A and J12B Figure 1 1 Integrator IM PD1 layout ARM DUI 0152C Copyright 2001 All rights reserved 1 3 Introduction 1 2 Interface module features and architecture This section describes the main features of the interface module and its architecture 1 2 1 Features The main features of the interface module are as follows display support interface to 8 4 inch Sharp color full VGA LCD generic interface to LCD with touch screen video DAC to support the connection of a VGA or SVGA PC monitor USB type A host and type B device interfaces e audio CODEC combined MultiMedia Card MMC and SD card interface smartcard socket e two serial RS232 tr
29. e ESD precautions when handling any Integrator board 1 8 Copyright O 2001 All rights reserved ARM DUI 0152C Chapter 2 Getting Started This chapter describes how to set up and start using the logic module It contains the following sections Setting up the logic module on page 2 2 Fitting the interface module on page 2 3 Connecting Multi ICE or other JTAG equipment on page 2 5 ARM DUI 0152C Copyright 2001 All rights reserved 2 1 Getting Started 2 1 Setting up the logic module Before the interface module can be used it is necessary to load the required peripheral controllers into the logic module FPGA to drive the interfaces The interface module is supplied with an example configuration that provides PrimeCell peripherals for supported logic modules The logic module user guide describes how to download new FPGA configurations When the interface module is fitted to the logic module there is no access to the manufacturer specific FPGA programming tool connector This means that the logic module FPGA must be configured from flash or directly using the Multi ICE connector if the logic module supports direct Multi ICE configuration 2 2 Copyright O 2001 All rights reserved ARM DUI 0152C Getting Started 2 2 Fitting the interface module The interface module is designed to be mounted on top of a logic module and provides connectivity for peripherals in the logic module FPGA The interface modu
30. erential input USB1_MODE IM_BBANK32 Mode USB1_SPEED IM_BBANK33 Edge rate control Configure the device USB interface to operate at slow or full speed by moving the soldered link LK1 The two settings are Full speed Fit link in position A B default Slow speed Fit link in position B C Note For a full description of the USB signals refer to the datasheet for the Philips PDIUSBP11AD transceiver The two USB interfaces provide different types of USB connector manufactured by Berg Figure 3 9 identifies the connectors for the host and device interfaces and shows how the pins are numbered 1234 2 1 F Device Figure 3 9 Identifying the USB connectors ARM DUI 0152C Copyright 2001 All rights reserved Hardware Reference 3 6 Audio CODEC The interface module provides a National Semiconductors LM4549 audio CODEC The audio CODEC is compatible with AC 97 Rev 2 1 is PC98 compliant and features sample rate conversion and analog 3D sound The CODEC can be driven with a PrimeCell AACI PL041 or similar peripheral Figure 3 10 shows the audio CODEC AACI SDATA OUT CODEC LINE OUT L gt gt z CODEC_LINE_OUT_R gt n QAACIBITCLK SIS 2 CODEC LINE IN L amp a AACI SYNC gt CODEC LINE IN R E z LM4549 i a ACL SDATA I
31. face Figure 3 8 shows one of the two USB interfaces USBO MODE gt USBO nOE pl USBO SUSPEND gt USBO_DATAP x S B USB0 VMO gt PDIUSBP11AD M o B np d aa Po DATA li a USBO SPEED x U3 qUSBO_RCV USBO_vP USBO_VM Figure 3 8 USB interface one channel USBO provides a USB host interface and connects through the type A connector J11 USB1 provides a USB device interface and connects through the type B connector J13 The signals associated with the USB interfaces are assigned to the EXPIM socket pins as shown in Table 3 5 Table 3 5 Serial interface signal assignment Signal name EXPIM connector Description USBO0 VM IM ABANKI6 Gated version of D USBO VP IM BBANKI7 Gated version of D USBO RCV IM BBANKIS Receive data USBO SUSPEND IM BBANKI9 Suspend for power save USBO0 nOE IM BBANK20 Output enable USB0_VMO IM BBANK2I Differential input USBO VPO IM BBANK22 Differential input USBO0 MODE IM BBANK23 Mode 3 10 Copyright O 2001 All rights reserved ARM DUI 0152C Hardware Reference Table 3 5 Serial interface signal assignment continued Signal name EXPIM connector Description USBO0 SPEED IM BBANK24 Edge rate control USBI VM IM ABANK25 Gated version of D USB1 VP IM BBANK26 Gated version of D USB1 RCV IM BBANK27 Receive data USB1 SUSPEND IM BBANK28 Suspend for power save USB1 nOE IM BBANK29 Output enable USB1_VMO IM_BBANK30 Differential input USB1_VPO IM_BBANK31 Diff
32. gister Bit Name Access Function 1 PENDOWN Read write This bit reads the Pen Down status Write 0 to clear 0 pen up 1 pen down or SoftPenDown 0 SOFTPENDOWN Read write Setting this bit to 1 is the software equivalent of touching the screen Used for test and reading auxiliary input channels Touch screen X Y auto read register Table 4 11 describes the operation of this register Table 4 11 TS_AUTORDXY register Bit Name Access Function 27 16 Read Last Y value 11 0 Read Last X value 4 12 Copyright O 2001 All rights reserved ARM DUI 0152C Reference Design Example How to use the TSCI The PENDOWN bit in the touchscreen control register will remain set until 0 is written A pendown event will cause the X and Y registers to be updated This can be used to generate an interrupt ARM DUI 0152C Copyright 2001 All rights reserved 4 13 Reference Design Example Copyright O 2001 All rights reserved ARM DUI 0152C Appendix A Signal Descriptions This appendix describes the Integrator IM PD1 interface connectors and signal connections It contains the following sections EXPA on page A 2 EXPB on page A 4 EXPIM on page A 6 Logic analyzer connector on page A 8 ARM DUI 0152C Copyright 2001 All rights reserved A 1 Signal Descriptions A 1 EXPA Pin numbers for 200 way socket viewed from below board 101 os od geg o 04 2 we PO aa pon De
33. ignal assignment continued Signal name EXPIM connector Description UARTI RTS IM ABANKI Ready to send UART1 DIR IM ABANK2 Data terminal ready UARTI CTS IM ABANK3 Clear to send UARTI DSR IM ABANKA4 Data set ready UART1 DCD IM ABANKS5 Data carrier detect UART1 RXD IM ABANK6 Receive data UARTI RI IM ABANK7 Ring indicator Figure 3 6 shows the assignment of the two serial interfaces to the 9 pin D type male connector at J12 Serial transceiver U4 Serial transceiver U19 J12B Figure 3 6 Serial interface connector assignment Figure 3 7 on page 3 9 shows the pin numbering for a 9 pin D type male connector and Table 3 4 on page 3 9 shows the signal assignment for the two connectors The pinout shown in Figure 3 7 on page 3 9 is configured as a Data Communications Equipment DCE device 3 8 Copyright O 2001 All rights reserved ARM DUI 0152C Hardware Reference Figure 3 7 Serial connector pinout Table 3 4 Serial plug signal assignment Pin J12A J12B 1 SERO DCD SERI DCD 2 SERO RX SERI RX 3 SERO TX SERI TX 4 SERO DIR SERI DIR 5 SERO GND SERI GND 6 SERO DSR SERI DSR 7 SERO RTS SERI RTS 8 SERO CTS SERI CTS 9 SERO RI SERI RI ARM DUI 0152C Copyright O 2001 All rights reserved 3 9 Hardware Reference 3 5 USB inter
34. ing the product name an explanation of your comments xii Copyright O 2001 All rights reserved ARM DUI 0152C Chapter 1 Introduction This chapter introduces the Integrator IM PD1 It contains the following sections About the Integrator IM PD1 on page 1 2 Interface module features and architecture on page 1 4 Links on page 1 7 Care of modules on page 1 8 ARM DUI 0152C Copyright 2001 All rights reserved 1 1 Introduction 1 1 About the Integrator IM PD1 The Integrator IM PD1 is an interface module that is designed to be used in conjunction with the Integrator LM XCV600E or LM EP20K600E and future compatible logic modules It provides standard interfaces to enable you to make external connections to PrimeCell or your own peripherals implemented in the logic module FPGA Figure 1 1 on page 1 3 shows the layout of the Integrator IM PD1 Circuit diagrams of the Integrator IM PD1 and third party data sheets are available as pdf files after installation from the CDROM 1 2 Copyright O 2001 All rights reserved ARM DUI 0152C Introduction i B MMC SD card socket Device USB Host USB Bond oec IrDA Back light J32 J9 J13 E 411 y link LK2 transceiver Touch screen U8 J22 ES D H CONFIG link E S Microphon
35. le can be installed at the top of a stack of up to four logic modules However it only provides interface connections for the logic module immediately beneath it Figure 2 1 shows an example system comprising a core module and logic module attached to an Integrator AP see the Integrator AP User Guide for more details with interface module installed on top of the logic module Core module 0 Interface module Logic module O Figure 2 1 Assembled Integrator AP development system 2 2 1 Using the Integrator IM PD1 without an Integrator AP motherboard This option uses a core module at the bottom of a stack of one or more other modules One logic module must be included that provides the system control function for example a system bus arbiter normally provided by the motherboard ARM DUI 0152C Copyright O 2001 All rights reserved 2 3 Getting Started Note Module stacking without a motherboard is supported by later core module types that have a link similar to LK3 on the logic module At the time of publication supporting core modules are Integrator CM9x6E S rev C and later Integrator CM9x0T ETM rev C and later Integrator CM10200 rev C and later For up to date information about core module support for this stacking option refer to the ARM web site To use this option on the core module at the bottom of the stack set the link to the appropriate position see the user guide for you
36. m controller SC nRESET IM BBANK39 Reset to card SC PRESENT IM BBANKAO Card detect signal Figure 3 2 shows the signal assignment of a smartcard Pins 4 and 8 are not connected and are omitted on some cards ES 5V 3V3 GND SC nRESET SC V SC CLK SC V SC DATA SC V E Figure 3 2 Smartcard contacts assignment The smart card is inserted into the smartcard socket with the contacts face down Figure 3 3 on page 3 5 shows the pinout of the connector J34 This can be used to connect to an off PCB smart card device 3 4 Copyright O 2001 All rights reserved ARM DUI 0152C SC DATA SC V SC nRESET SC V SC CLK SC V SC PRESENT 5V 3V3 Hardware Reference GND GND GND GND GND Figure 3 3 J34 pinout ARM DUI 0152C Copyright 2001 All rights reserved Hardware Reference 3 3 IrDA interface Figure 3 4 shows the infrared interface suitable for use with a PrimeCell UART PLO11 or similar peripheral The example IRMS6400 is an IrDA compatible transceiver produced by the Infineon Technologies Corp SIR_TXD S 5 T sreo e E x DI Figure 3 4 IrDA interface The signals associated with the infrared interface are assigned on the EXPIM socket pins as shown in Table 3 1 Table 3 2 IrDA interface signal assignment Signal name EXPIM connector Description SIR SCLK IM BBANKS55 Serial clock
37. mally labelled on the top surface and provide an arrow to indicate the correct way to insert them Remove the card by gently pressing it into the socket It springs back and can be removed This ensures that the card detection switches within the socket operate correctly The connector J33 enables you to access the signals for debugging or to an off PCB card socket The pinout of J33 is shown in Figure 3 16 MCI 1 NA GND MCI 2 GND MCI PWR GND MCI 5 GND MCI 7 GND MCI 8 GND MCI 9 GND MCL nCARDIN GND MCI WPROT GND GND GND 19 20 Figure 3 16 J33 pinout 3 16 Copyright O 2001 All rights reserved ARM DUI 0152C Hardware Reference 3 8 Display interface EXPA Socket The interface module provides a display interface with outputs for a VGA or SVGA monitor connected to J30 Sharp LQ084V1DG2 8 4 inch TFT VGA LCD panel connected to J14 Generic LCD and touchscreen connector A suitable peripheral for driving these types of display is the PrimeCell CLCD controller PL110 Figure 3 17 shows the architecture of the display interface The diagram shows the signals used to provide pixel data and for buffer control B27 is used to enable the signals on J27 and B28 is used to enable the buffers for the Sharp display signals on J14 VGA connector J30 Generic LCD J27 LCDO CLK LCDO HSYNC LCDO VSYNC Buffers U11 U12 LCD
38. marked F bus connect to the GPIO bus on the Integrator AP This bus is routed between the system controller FPGA on the motherboard and the FPGA on the logic module These signals are available for your own applications If the logic module is mounted in the HDRA HDRB position on the motherboard these pins connect to the F bus that is routed between any modules in the stack there are no signals from the motherboard present on these pins The release note provided with the shipped example provides information on how the signals shown in Figure 3 19 on page 3 20 are connected to the PrimeCell If you intend to use anything other than the shipped example then signal allocation is a user decision ARM DUI 0152C Copyright 2001 All rights reserved 3 19 Hardware Reference LCD1 0 LCD1 1 GND LCD1 4 LCD1 5 GND LCD1 8 LCD1 9 GND LCD1 12 LCD1 13 GND LCD1 16 LCD1 17 GND LCD1 20 LCD1 21 GND TS XP TS YP GND LCD1 BIAS LCD1 3V3 Note GND 12V 49 50 GND LCDi2 LCD1 3 GND LCD1 6 LCDi7 GND LCD1 10 LCD1 11 GND LCD1 14 LCD1 15 GND LCD1 18 LCD1 19 GND LCD1 22 LCD1 23 GND TS XN TS YN GND 3V3 5V BL_ADJ Figure 3 19 J27 pinout The LCD1 23 0 signals are 3V3 buffered versions of B 23 0
39. n be driven with a PrimeCell GPIO PL061 or other suitable peripheral The buzzer is connected to the drain of a MOSFET device within U17 and the gate is controlled by an output from the GPIO Enable the buzzer inserting fitting the jumper J23 Disable the buzzer by removing jumper J23 The signal assignment is shown in Table 3 10 Table 3 10 Buzzer interface signal assignment Signal name EXPIM connector Description nBUZZER IM BBANKO Controls power to the buzzer LOW power ON HIGH power OFF ARM DUI 0152C Copyright O 2001 All rights reserved 3 25 Hardware Reference 3 26 Copyright O 2001 All rights reserved ARM DUI 0152C Chapter A Reference Design Example This chapter describes how to set up and start using the logic module It contains the following sections About the design example on page 4 2 Design example on page 4 3 ARM DUI 0152C Copyright O 2001 All rights reserved 4 1 Reference Design Example 4 1 About the design example This chapter describes the reference design example supplied with the interface module The interface module is not fitted with any programmable devices because it is intended to provide interfaces for peripherals instantiated into a logic module FPGA A VHDL example is supplied for the Integrator LM XCV2000E and LM EP20K1000E logic modules with PrimeCell peripherals instantiated into the FPGA design This example is designed to operate with the logic mod
40. ogic module registers The addresses shown are offsets from the base addresses shown in Figure 4 2 on page 4 6 Table 4 3 Logic module registers Offset address Name Type Function 0x0000000 LM OSCI Read write Oscillator 1 divisor register 0x0000004 LM OSC2 Read write Oscillator 2 divisor register 0x0000008 LM LOCK Read write Oscillator lock register 0x000000C LM LEDS Read write User LEDs control register 0x0000010 LM INT Read write Push button interrupt register 0x0000014 LM SW Read Switches register 0x0000018 LM CONTROL Read write Control register Oscillator divisor registers The oscillator registers control the frequency of the clocks generated by the two clock generators on the logic module ARM DUI 0152C Copyright 2001 All rights reserved 4 7 Reference Design Example Before writing to the oscillator registers you must unlock them by writing the value 0x0000A05F to the LM LOCK register After writing the oscillator register relock them by writing any value other than 0x0000A05F to the LM LOCK register Table 4 4 describes the oscillator register bits Table 4 4 LM OSCx registers Bits Name Access Function 18 16 OD Read write Output divider 000 divide by 10 001 divide by 2 010 divide by 8 011 divide by 4 100 divide by 5 101 divide by 7 110 divide by 9 111 divide by 6 15 9 RDW Read write Reference divider word Defines the binary val
41. old Highlights interface elements such as menu names Denotes ARM processor signal names Also used for terms in descriptive lists where appropriate monospace Denotes text that can be entered at the keyboard such as commands file and program names and source code monospace Denotes a permitted abbreviation for a command or option The underlined text can be entered instead of the full command or option name monospace italic Denotes arguments to commands and functions where the argument is to be replaced by a specific value monospace bold Denotes language keywords when used outside example code This section lists publications from both ARM Limited and third parties that provide additional information on developing code for the ARM family of processors ARM periodically provides updates and corrections to its documentation See http www arm com for current errata sheets and addenda See also the ARM Frequently Asked Questions list on the ARM website ARM publications The following documents provide information about related Integrator products ARM Integrator AP User Guide ARM DUI 0098 ARM Integrator CM920T ETM User Guide ARM DUI 0149 e ARM Integrator CM9x0T and CM7x0T User Guide ARM DUI 0157 ARM Integrator CM7TDMI User Guide ARM DUI 0126 Integrator CM946E S Integrator CM966E S User Guide ARM DUI 0138 ARM Integrator LM XCV600E LM EP20K600E User Guide ARM DUI 0146 ARM DUI 0152C Co
42. package The Integrator IM PD1 provides a socket into which an MMC or SD can be placed for reading or writing Smartcard A card of similar size to a credit card that typically contains a microcontroller and memory that can be used to store secure data SSP Synchronous Serial Port UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus VIC Vectored Interrupt Controller The PrimeCell VIC provides an interface to the interrupt system and improves interrupt latency in two ways moves the interrupt controller to the AMBA AHB provides vectored interrupt support for high priority interrupt sources Video DAC Video Digital to Analog Converter A device that converts digital data into analog signals for a display monitor The Integrator IM PD1 provides a video DAC that converts 24 bit parallel data into red green and blue signals for a display and generates horizontal and vertical synchronization signals from a clock input ZBT SSRAM Zero Bus Turnaround Synchronous Static Random Access Memory 2 Copyright O 2001 All rights reserved ARM DUI 0152C Index The items in this index are listed in alphabetical order with symbols and numerics appearing at the end The references given are to page numbers A Audio cable 3 13 Audio CODEC 3 12 Audio connectors 1 3 Audio DIN connector pinout 3 13 B Backlight connector 3 23 Backlight control 3 23 Block diagram 1 6 Buzzer 3 25 Buzzer enablelink 1 3 1 7 3 25
43. pyright 2001 All rights reserved ix Preface The following publication provide information about ARM PrimeCell devices that can be used to control the interfaces described in this manual ARM PrimeCell UART PL011 Technical Reference Manual ARM DDI 0183 ARM PrimeCell Synchronous Serial Port Master and Slave PL022 Technical Reference Manual ARM DDI 0171 ARM PrimeCell Advanced Audio CODEC Interface PL041 Technical Reference Manual ARM DDI 0173 ARM PrimeCell GPIO PL061 Technical Reference Manual ARM DDI 0187 ARM PrimeCell Color LCD Controller PL110 Technical Reference Manual ARM DDI 0161 ARM PrimeCell Smartcard Interface PL130 Technical Reference Manual ARM DDI 0148 ARM PrimeCell Vectored Interrupt Controller PL190 Technical Reference Manual ARM DDI 0181 ARM PrimeCell Multimedia Card Interface PL181 Technical Reference Manual ARM DDI 0205 The following publications provide reference information about ARM architecture AMBA Specification ARM IHI 0011 ARM Architectural Reference Manual ARM DDI 0100 The following publications provide information about the ARM Developer Suite Getting Started ARM DUI 0064 ADS Tools Guide ARM DUI 0067 ADS Debuggers Guide ARM DUI 0066 ADS Debug Target Guide ARM DUI 0058 ADS Developer Guide ARM DUI 0056 ADS CodeWarrior IDE Guide ARM DUI 0065 The following publication provides information about Multi ICE
44. r IM PD1 User Guide Advanced Audio CODEC Interface The ARM open standard for on chip buses AHB conforms to this standard The ARM open standard for peripheral buses APB conforms to this standard COder DECoder Hardware or software that converts analog sound speech or video to digital code analog to digital and vice versa digital to analog Hardware codecs are built into devices such as digital telephones and videoconferencing stations Software codecs are used to record and play audio and video over the web utilizing the CPU for processing Although hardware codecs are faster than software routines as desktop machines become more powerful they can more adequately handle the processing load required for the conversion Field Programmable Gate Array General purpose input output ARM DUI 0152C Copyright O 2001 All rights reserved 1 Glossary JTAG Joint Test Action Group The committee which defined the IEEE test access port and boundary scan standard Multi ICE Multi ICE is a system for debugging embedded processor cores using a JTAG interface MMC MultiMedia Card A type of removable memory device that consists of a ROM or flash memory within a compact package The Integrator IM PD1 provides a socket into which an MMC or SD can be placed for reading or writing MMCI MultiMedia Card Interface SCI Smartcard Interface SD A type of removable memory device that consists of a ROM or flash memory within a compact
45. r core module on any logic modules set LK3 to the C D position on one logic module program and enable the CLK2 clock generator see ARM Integrator LM XCV600E LM EP20K600E User Guide 2 4 Copyright O 2001 All rights reserved ARM DUI 0152C Getting Started 2 3 Connecting Multi ICE or other JTAG equipment JTAG equipment such as Multi ICE is connected to the 20 way box header as shown in Figure 2 2 Connect the JTAG equipment to the interface module at the top of the logic module stack Refer to the logic module user guide for a description of the JTAG system Multi ICE VA server debugger 000 exon 0 D ee X Parallel cable o Multi ICE unit ix D Ex OL JO Pen VE a E dg n qe il K n O a i Interface module Figure 2 2 Connecting Multi ICE Note There are no components on the interface module that use the JTAG signals The connector provides you with access to the JTAG signals on the modules below ARM DUI 0152C Copyright 2001 All rights reserved 2 5 Getting Started 2 6 Copyright O 2001 All rights reserved ARM DUI 0152C
46. red to connect APB peripherals to the AMBA AHB bus It produces the peripheral select signals for each of the APB peripherals APBRegs vhd The APB register peripheral provides memory mapped registers that you can use to configure the two clock generators write to the user LEDs on the logic module read the user switch inputs on the logic module It also latches the pressing of the push button to generate an expansion interrupt BuildOptions vhd This file defines generation of the PrimeCells in the example and allows control over the synthesis so that PrimeCells can be included or excluded Tsci vhd This is a touchscreen controller that can be used as an alternative to the SSP and GPIO PrimeCell You can select the touchscreen controller in the control register LM CONTROL see Control register on page 4 10 Note The HDL files provided are only for information and will not build without additional components that can be licensed separately ARM DUI 0152C Copyright O 2001 All rights reserved 4 5 Reference Design Example 4 2 3 Loading the FPGA image Multi ICE configuration files the progcards utility and the FPGA images for the supported logic modules are available after installation from the CDROM Refer to the Logic Module User Guide for programming information 4 2 4 Example memory map The supplied examples set up the memory map for the logic module as shown in Figure 4 2 This shows
47. s User LEDs control register The LEDs register is used to control the user LEDs on the logic module Writing a 0 to a bit lights the associated LED ARM DUI 0152C Copyright 2001 All rights reserved 4 9 Reference Design Example Push button interrupt register The push button interrupt register contains 1 bit It is a latched indication that the push button on the logic module has been pressed The output from this register is used to drive an input to the interrupt controller Table 4 6 describes the operation of this register Table 4 6 LM INT register Bits Name Access Function 0 LM INT Read This bit when SET is a latched indication that the push button has been pressed Write Write 0 to this register to CLEAR the latched indication Writing 1 to this register has the same effect as pressing the push button Switches register This register is used to read the setting of the 8 way DIP switch on the logic module A 0 indicates that the associated switch element is CLOSED ON Control register This register controls the multiplexors that are used to select the display type touchscreen controller see Touch screen controller interface registers on page 4 12 for more information Table 4 7 on page 4 11 describes the operation of this register 4 10 Copyright O 2001 All rights reserved ARM DUI 0152C Reference Design Example Table 4 7 LM CONTROL register
48. s the following section Mechanical information on page B 2 ARM DUI 0152C Copyright O 2001 All rights reserved B 1 Mechanical Specification B 1 Mechanical information The Integrator IM PD1 is designed to be stackable Figure B 1 on page B 2 shows the mechanical outline of a board on which you would mount an Integrator IM PD1 board and shows the location of pin 1 of the Samtec connectors All dimensions are in mm 5 200 way connector 120 way connector o 4 col x 50 row 4 col x 30 row Plug on top and Plug on top and socket on underside socket on underside EXPB v Xa Detail A A 10 0 Figure B 1 Board dimensions B 2 Copyright 2001 All rights reserved ARM DUI 0152C Mechanical Specification Note In Figure B 1 on page B 2 the 148 0 and 100 0 dimensions show the size of a standard module produced by ARM Limited B 1 1 Connector part numbers The Samtec connector part numbers are listed in Table B 1 Table B 1 Samtec connector part numbers Type Part number 200 way connector TOLC 150 32 F Q P A 120 way connector TOLC 130 32 F Q P A ARM DUI 0152C Copyright 2001 All rights reserved B 3 Mechanical Specification B 4 Copyright O 2001 All rights reserved ARM DUI 0152C Glossary AACI AMBA High performance Bus AMBA Peripheral Bus CODEC FPGA GPIO This glossary lists all the abbreviations used in the Integrato
49. s on the pins labeled H 31 0 J 16 0 Table A 2 EXPB signal assignment Pin label Name Description H 31 29 Not used H28 SYSCLK System clock from the logic module H 27 0 Not used J 16 14 Not used A 4 Copyright O 2001 All rights reserved ARM DUI 0152C Signal Descriptions Table A 2 EXPB signal assignment continued Pin label Name Description J13 nCFGEN Sets motherboard into configuration mode J12 nSRST Multi ICE reset open collector J11 Not used J10 RTCK Returned JTAG test clock J9 Not used J8 nTRST JTAG reset J7 TDO JTAG test data out J6 TDI JTAG test data in J5 TMS JTAG test mode select J4 TCK JTAG test clock J 3 0 Not used F31 F31 Used used by the interface module to control the 3 3V power output for LCD1 from J27 and J14 see Display interface on page 3 17 See note below F 30 0 Not used See note below Note If the logic module is mounted in the EXPA EXPB position on an Integrator AP the pins marked F bus connect to the GPIO bus on the Integrator AP This bus is routed between the system controller FPGA on the motherboard and the FPGA on the logic module These signals are available for your own applications If the logic module is mounted in the HDRA HDRB position on the motherboard these pins connect to the F bus that is routed between any modules in the stack There are no signals from the motherboard present on these pins
50. ue of the R 6 0 pins of the clock generator 8 0 VDW Read write VCO divider word Defines the binary value of the V 8 0 pins of the clock generator Note The default values set CLK1 to 25MHz and CLK2 to 48MHz The reference divider R 6 0 and VCO divider V 8 0 are used to calculate the output frequency as follows V 8 0 8 Frequency 48MHz R 6 0 2 OD You must also observe the operating range limits V 8 0 8 10MHz 48MHz R 6 0 2 R 6 0 lt 118 4 8 Copyright 2001 All rights reserved ARM DUI 0152C Reference Design Example Note You can calculate values for the clock control signals using the ICS525 calculator on the Integrated Circuit Systems website at http www icst com products ics525inputForm html Oscillator lock register The lock register is used to control access to the oscillator registers allowing them to be locked and unlocked This mechanism prevents the oscillator registers from being overwritten accidently Table 4 5 describes the lock register bits Table 4 5 LM LOCK register Bits Name Access Function 16 LOCKED Read This bit indicates if the oscillator registers are locked or unlocked 0 unlocked 1 locked 15 0 LOCKVAL Read write Write the value 0x0000A05F to this register to enable write accesses to the oscillator registers Write any other value to this register to lock the oscillator register
51. ule mounted on a suitable motherboard for example the Integrator AP If you are using your own peripheral designs the example will help you become familiar with using the interface module 4 1 1 About PrimeCells The interface module is supplied with executable software that demonstrates the functionality of the PrimeCells included in the design example The ARM PrimeCells are a range of synthesizable peripherals that are ideally suited for use in ARM based designs The interface module is supplied with an FPGA image containing PrimeCell peripherals for each supported interface on the board and the accompanying CD contains documentation for them HDL and device source code for the PrimeCell peripherals are not supplied with the interface module You must license the PrimeCell peripherals to obtain the source code 4 2 Copyright O 2001 All rights reserved ARM DUI 0152C Reference Design Example 4 2 Design example The interface module design example is supplied in VHDL The example is an AHB design with an APB subsystem The PrimeCell peripherals are instantiated in the top level VHDL file 4 2 1 Example architecture The architecture of the example is shown in Figure 4 1 The interface module is provided with an example and release notes that define the clock sources interrupt assignments memory map and peripherals Control System registers Bus Unidirectional M to bidirectional interface S UARTO Vectored UA
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