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MSM9563 IC for FM Multiplex Data Demodulation User's Manual

1. This is the register for setting the conditions of interrupt after the first horizontal error correction During the initial setting all packets received in a synchronization state are set to generate an interrupt Itis possible to specify the four types of interrupt conditions shown in the following table regarding good error free packets frame synchronization and specified SI service identifier It is possible to specify 16 types of service identifiers SIO to 5115 for which it is necessary to set this register and the register 0x35 The packets that generated an interrupt after the first horizontal error correction are recorded in the frame memory Receiving state 1 DB5 INTO after the second horizontal error correction Therefore there is no need to read out good packets after the first horizontal error correction after the second horizontal error correction Table 5 3 3 2 Interrupt conditions after the first horizontal error correction Interrupt condition Set value Set value of 0x35 of 0x34 1 All packets received in a synchronization state 0x20 2 Good packets received in a synchronization state 0x70 Packets in a frame synchronization state including bad packets 4 Good packets with the specified service 0x7A 510 to SI7 written in units of a bit identifier SI Ox B 518 to 5115 written in units of a bit MSM9563 User s Manual Chapter 5
2. This is the register for controlling the selection of test output pins MOUTO to and is used for testing only Set value Pin Extention port LSI internal signal monitor name 0xC0 0x00 0x20 0x40 0x60 0x80 OxEO TSTO TSTT1 TSTBO TSTB1 TSTC MOUTO DBO of register 0x0F BPF LimOut TS11 FRCKO FSYNC Note 1 MOUT1 DB1 of register OXOF Delay detector Out TS21 FRCK1 BSYNC Note 2 MOUT2 DB2 of register OxOF LPF LimOut 7510 FRCK2 RAMOUT BICO Note 3 MOUT3 DB3 of register OxOF SCF clock GATE FRCK3 BICDET2 BIC1 Note 3 MOUT4 DB4 of register OXOF Fixed to L PHCK1 BCK BICDET BICDET1 Note 3 Note 1 FSYNC 1 Frame synchronized 0 Frame out of synchronization Note 2 BSYNC 1 Block synchronized 0 Block out of synchronization 5 42 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Note 3 BIC Detection BICDET1 BICO BIC NO 1 0 0 1 1 0 1 2 1 1 0 3 1 1 1 4 0 Not detected 5 12 2 Test control 1 Table 5 12 2 Test Control 1 Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W e nm Serial output PN Decoding Differential Clock Serial output Output controli contro decoding output output 0x33 control1 control 0 control control control 0 Initial value 0 0 0 0 1 0 0 Th
3. 0 Note 1 The setting RDBSCK_SUB 0 05 DB3 0 should have been made in the register 0x05 Note 2 The setting RDBSCK SUB 1 R_05 DB3 1 should have been made in the register 0x05 Note 3 The setting SETINTCK SUB R_05 DB4 0 R_05 DB5 1 should have been made the register Ox05 Read RDBSCK 1 BCK8 SUB MSB to SUB LSB indicate the bit numbers of the packet being received The upper 5 bits indicate the byte number Read RDBSCK 0 PRE BCK8 SUB MSB to PRE BCKO SUB LSB indicate the bit numbers of the packet immediately before the subchannel enters block synchronization Write SETINTCK SUB This is the register for specifying the subchannel interrupt byte number Before setting this register make the setting of SETINTCK SUB in the register 0x05 This matches with the byte number of received data in a block synchronization state The interrupt occurs at the leading part of a change in the byte number Specify bytes 0 to 35 using the 6 bits INTBCKS to INTBCK8 5 4 5 Interrupt packet number setting subchannel Table 5 4 5 Interrupt timing setting SUB packet number Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R FRCK7 FRCK6 FRCK5 FRCK4 FRCK3 FRCK2 FRCK1 FRCKO _SUB _SUB _SUB _SUB _SUB _SUB _SUB _SUB W FRCK7 FRCK6 FRCK5 FRCK4 FRCK3 FRCK2 FRCK1 FRCKO 0x08 Note 1 _SUB _SUB _SUB _SUB _SUB _SUB _SUB _SUB W INT
4. RF m hi 05 y MOUT6 INT utput v DBO to DB7 a XOUT Vin DV 2 MD pS 3 Input current 1 A ViL DGND 2 on IL1 GR Vin AVpp 2 4 Input current 2 ADETIN lio Vit AGND 2 5 Input current 3 Vin DVpp 2 pA DVpp 3 V XOUTC 6 Pull up current 3 15 50 A p pull H AVpp _ _ Output off leakage on During nonmonitoring Hiz 7 uA MON current Vor AGND 1 During nonmonitoring Hiz During operation no load 14 28 mA f 8 192 MHz 8 Supply current Ipp AVpp DVpp During power down 50 no load MSM9563 User s Manual Chapter 4 ELECTRICAL CHARACTERISTICS 4 4 AC CHARACTERISTICS DVpp AVpp 2 7 to 3 6 V DGND AGND 0 V Ta 40 to 85 C No Parameter Symbol Condition Min Unit Applied Pin See figure 4 1 3 e WR CS 1 Write setup time ns AO to Ad tswr2 See figure 4 1 90 DBO to DB7 tHwR1 See figure 4 1 18 WR CS 2 Write hold time ns AO to tuwR2 See figure 4 1 10 DBO to DB7 3 Write pulse width twwr See figure 4 1 90 ns WR 4 Read setup ti t See fi 4 2 3 Au im n ead setup time SRD ee figure S AO to A5 5 Read hold ti t See fi 4 2 18 ead hold time ns HRD ee figure AO to A5 6 Read pulse
5. 1 1 1 1 15 5 34 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Read When synchronization points cannot be detected successively in a frame synchronization state the number of detection failures is decremented from the set number of frame synchronization forward protection steps and when the value of this register changes from 1 to 0 the frame is considered to have been out of synchronization Remaining number of IN DB3 DB2 DB1 DBO frame synchronization Out of synchronization forward protection steps PUE O 0 0 0 0 0 etection When frame 0 1 gt Synchronization y 4 y point cannot be detected 1 1 1 1 15 Loaded during synchronization detection 5 7 3 Frame synchronization monitor Table 5 7 3 Frame synchronization monitor Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R FSYN Ox1A SING Initial value 0 DBO Frame synchronization monitor 0 Frame out of synchronization 1 Frame synchronized 5 7 4 Setting frame synchronization Table 5 7 4 Setting frame synchronization Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W x x x x x x x x 0x1B Initial value x x x x x x x x 5 7 5 Clearing frame synchronization Table 5 7 5 Clearing frame synchronization Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB
6. Byte No BYTE23 First horizontal correction receive data No 21 BYTE24 CRC BYTE25 PARITY CRC BYTE26 PARITY BYTE35 PARITY BYTEO and BYTE1 of the receive RAM data after the first horizontal error correction indicate the status of the received packet BYTE2 to BYE23 are data and BYTE 24 to BYTE 35 are the CRC parity data BYTE24 to BYTE35 are for testing and cannot be read out MSM9563 User s Manual Chapter 5 CONTROL REGISTERS BYTEO 1 DB7 CRCO 1 Indicates that there is an error in the CRC of the packet after the first horizontal error correction 0 Indicates that the CRC of the packet is normal after the first horizontal error correction 2 DB6 ERCO 1 Indicates that there is an error in the correction result of the packet after the first horizontal error correction 0 Indicates that the correction result of the packet is normal after the first horizontal error correction 3 085 RECCRC 1 Indicates that there is error in the CRC of the received packet before error correction 0 Indicates that the CRC of the received packet is normal before error correction 4 084 FSYNC 1 Indicates that the received packet is a frame synchronization state 0 Indicates that the received packet is in a frame out of synchronizaiton state 5 DB3 BSYNC 1 Indicates that the received packet is in a block synchronization state 0 Indicates that the received packet is in a
7. 5 44 Chapter 6 EXTERNAL CONNECTION EXAMPLE MSM9563 User s Manual Chapter 6 EXTERNAL CONNECTION EXAMPLE 6 EXTERNAL CONNECTION EXAMPLE CPU interface 1 CLR MON 5 Section 2 ADETIN A2 330 pF 10 gt IH ain 5 XOUT SG AU 2 2 uF 1 CS oe E XTAL2 15 pF 8 192 MHz crystal i Note 3 25819 XTAL1 hse Note 2 _ 3 App 28 Note 2 2 AGND DGND l 14 DB7 a MOUT6 DB6 24 MOUTS DB5 gt MOUTA 084 gt 0 MOUT3 DB3 2 mout2 DB2 mourt DBI 20 MOUTO DBO RD 18 RD WR 16 5 DVpp 3 V power supply input AVpp 3 Note 2 ii DGND AGND Note 1 Use a tantalum capacitor Note 2 The AVpp and DVpp should have different paths respectively Note 3 The AGND and tuner ground should use the same ground MSM9563 User s Manual Chapter 6 EXTERNAL CONNECTION EXAMPLE 6 2 Chapter 7 APPLICATION CIRCUIT MSM9563 User s Manual Chapter 7 APPLICATION CIRCUIT 7 APPLICATION CIRCUIT Antena FM tuner 8 bits E NI J ulation ROM MSM9563 Font LCD control SRAM ROM driver LCD display 16 kanji characters x 2 lines 7 1 MSM9563 Use
8. Chapter 1 GENERAL DESCRIPTION MSM9563 User s Manual Chapter 1 GENERAL DESCRIPTION GENERAL DESCRIPTION The MSM9563 is an IC which demodulates FM character multiplex signals in the DARC DAta Radio Channel format to acquire digital data This IC operates at 3 V In the DARC format baseband signals at ordinary FM broadcasting frequencies are multiplexed with 16 kbps digital data which is L MSK modulated at 76 kHz The MSM9563 has a bandpass filter consisting of an SCF frame synchronization circuit and error correction circuit on a single chip They allow a system for acquisition of digital data to be easily constructed by externally mounting an FM receiver tuner microcontroller for control and memory for temporary storage of data The 5 9563 a FM multiplex demodulator has a simple configuration and is equipped with only necessary functions By making changes to software for the external microcontroller the MSM9563 meets the various requirements of FM multiplex broadcasting services to be offered in future 1 DARC is a registered trademark of NHK Engineering Services Any manufacturer licensed by NHK Engineering Service can manufacture and sell products that utilize the DARC technology For detailed information on license please contact NHK Engineering Service Phone 81 3481 2650 FEATURES Built in two receive channels including main channel and sub channel one of two FM stations can be selected Pin compat
9. SG 5 0 Analog reference voltage pin Connect a capacitor between this pin and the analog ground pin to prevent noise Analog section MON 1 0 Analog section waveform monitoring pin The test mode setting for the blocks in the analog section is specified by the analog section control register ADETIN 2 Analog signal input pin for testing Digital section MOUTO to 8to 14 0 Digital section test signal output and monitor test MOUT6 output pins Clock XTAL1 29 8 192 MHz crystal connection XTAL2 30 0 8 192 MHz crystal connection XOUT 32 0 Pin to supply variable clock 64 kHz to 8 192 MHz to external devices XOUTC 7 XOUT control L sets XOUT output H sets XOUT output inhibit This pin is pulled up internally Power supply AVpp 3 Analog power supply AGND 4 Analog ground DVpp 28 Digital power supply DGND 27 Digital ground Chapter 4 ELECTRICAL CHARACTERISTICS MSM9563 User s Manual Chapter 4 ELECTRICAL CHARACTERISTICS 4 ELECTRICAL CHARACTERISTICS 4 1 ABSOLUTE MAXIMUM RATINGS No Parameter Symbol Condition Rating Unit AVpp 1 Power supply voltage a 0 3 to 47 0 DVpp AVpp DVpp V Input voltage Vi Ta 25 C 0 3 to AVpp 0 3 Output voltage Vo 0 3 to DVpp 0 3 Maximum power Ta 25 C per package 400 3 BA Pp mW dissipation Ta 25 C per output 50 4 Storage temperature 55 to 150 C 4 2 RECOMMEND
10. 0 R Block synchronization monitor 5 83 0 0 R 0x13 0x14 Block synchronization setting clearing 5 33 00 00 W 0x14 0x15 Block synchronization clearing XXXXXXXX W 0x15 0x16 In block bit number monitor 1 2 00000000 R Timing Interrupt timing byte number 1 2 5 23 00000000 R W 0x16 0x17 In block bit number monitor 2 2 0 R interrupt Interrupt timing _MAIN byte number 2 2 5 23 0 RW 0x17 0x18 Frame Number of block synchronization backward protection steps 01 11111100 W Frame Number of frame synchronization backward protection steps 5 34 01 00 W 0x18 Ox19 synchronization Number of block synchronization forward protection steps 0100 11110100 W synchronization Number of frame synchronization forward protection steps 5 34 0100 RW 0x19 Frame synchronization monitor 0000 0 m R Frame synchronization monitor 5 35 0 R Ox1B Frame synchronization setting 5 35 Undefined W 0x1B 0x1C Frame synchronization clearing XXXXXXXX W Frame synchronization clearing 5 35 Undefined W 0 1 0x1D In frame block number monitor 1 2 00000000 R Timing Interrupt timing packet number 1 2 5 23 00000000 RW 0 10 0x1E In frame block number monitor 2 2 R interrupt Interrupt timing packet number 2 2 5 24 0000 00 RW 0x1E Ox1F International frame format specification W Operating mode Fra
11. SGAIN1 to SGAINO These set the variable gain amplifier for the analog signal input composite signal Set so that peak value of the analog input signal composite signal xgain 0 5 to 0 9Vp p DB2 DB1 SGAIN1 SGAINO 0 0 x 1 0 1 x1 5 1 0 x2 1 1 x3 DB3 to DB5 M2 to MO This register controls the monitor terminal MON pin for the analog section output waveform DB5 DB4 DB3 mE MON Pin pin1 M2 M1 MO 0 0 0 Internal monitor pin power off Hz output 0 0 1 LPF output of input stage 0 1 0 BPF output 2 0 1 1 BPF output 4 1 0 0 BPF output 6 1 0 1 BPF output 8 1 1 0 Internal amplifier output 1 1 1 Equivalent waveform output for observing the eye pattern 5 40 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS DB6 DESTODTST For testing purpose only Normally use with the setting DB6 0 DB6 DBO A DET data identification circuit input control DETODTST DETC 0 0 AIN pin input enable FM multiplex broadcast reception 0 1 ADETIN pin input enable analog input 1 0 i ADETIN pin input enable digital input 511 POWER DOWN REGISTER Table 5 11 Power down Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0x31 W XCK2 XCK1 XCKO B2 B1 BO Initial value 0 0 0 0 0 0 DB4 to DB6 XCKO to 2 setting the divided frequency of external clock Set the divided frequenc
12. TH3 TH2 TH1 THO Initial value 1 1 1 0 1 1 1 0 5 37 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 9 LAYER 4 CRC REGISTERS 5 9 1 Layer 4 CRC registers Table 5 9 1 Layer 4 CRC register Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R L4CRC T 0x28 W MOD2 MOD1 MODO MEMTST CLRCRC Initial value 1 1 0 0 0 0 0 Write 1 DBO CLRCRC Write 1 before executing layer 4 CRC However 111X0001 is valid only when DB5 DB6 DB7 1 2 DB1 MEMTEST The use of any value other than 0 is prohibited 3 DB5 to DB7 Setting of the test mode Use one of the modes given in the following table Set mode DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO CLRCRC 1 1 1 0 0 0 1 Other than CLRCRC 0 1 0 0 0 1 0 0 0 0 Read 1 DB7 LACRCOUT Display of layer 4 CRC result 1 There is an error in the layer 4 CRC result 0 The layer 4 CRC result is normal 5 9 2 Layer 4 CRC data port Table 5 9 2 Layer 4 CRC data port Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R B7 B6 B5 B4 B3 B2 B1 BO 0x29 W B7 B6 B5 B4 B3 B2 B1 B0 Initial value x x x x x x x x Write the data group for which CRC processing is to be made in units of a byte at a cycle period of 620ns or more 5 38 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 9 3 Layer 4 CRC
13. _ERCFR2 _ERCFR3 0x37 W BANKLT MOD EXPCTCNT BANK BANK BANK BANK _CLR EXERC STARTB ERCFRO ERCFR1 ERCFR2 ERCFR3 Initial value 0 0 0 0 0 0 0 Read 1 DBO to DB3 BANK ERCFR3 to BANK ERCFRO When data is read after a receive interrupt after the second horizontal error correction these four bits indicate whether the four packet groups listed in the following table are in a frame synchronization state or not The vertical error correction is carried out only when DBO DB1 DB2 DB3 1 The second horizontal error correction is carried out only for the concerned packet group among DBO to DB3 However a separate setting and implementation of error correction for testing are required in the case of parity packets Frame format Format B Format A1 A0 083 Packet with a block number of 0 to 12 A1 Packet with a block number of 0 to 59 082 Packet with a block number of 13 to 135 AO A1 Packet with a block number of 60 to 129 DB1 Packet with a block number of 136 to 148 AO Packet with a block number of 130 to 189 DBO Packet with a block number of 149 to 271 Packet with a block number of 190 to 271 A1 Packet with a block number of 190 to 283 Note The packet numbers are expressed in this manual as 0 to 271 A1 0 to 283 2 DB7 BANK For testing purposes only Write This register is for making settings for testing and wr
14. 0x38 after second horizontal error correction from which data can be read out in units of a frame after the second horizontal error correction has been completed Receive port after the first horizontal error correction Since the receive port after the first horizontal error correction is internally separated into one for the main channel and one for the subchnnel it is necessary to select the required port before reading data The receive data interrupt after the first horizontal error correction can be set to be enabled or disabled according to the conditions of parity packet error correction result service identifier etc Receive port after the second horizontal error correction The receive data of the receive port after the second horizontal error correction is reported by an interrupt at the timing of the 13th packet of the next frame When all the packets of the frame have been received the vertical error correction would have been completed However the vertical error correction would have been omitted when all the packets in the frame have not been received such as when frame synchronization is entered in the middle of a frame The second horizontal error correction is carried out for the packet received under frame synchronization and its result is indicated in register 0x37 by dividing it into four groups as the frame synchronization condition The test settings described later are necessary for reading the received data including
15. CONTROL REGISTERS 5 3 4 Specification of SI Service identifier Table 5 3 4 SI Specification Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W SI7 516 515 54 513 512 51 510 Note 1 0x35 W 515 514 513 512 5111 5110 519 518 Note 2 Initial value 1 1 1 1 1 1 1 1 Note 1 The setting SISEL 0 should have been made in the register 0x34 Note 2 The setting SISEL 1 should have been made in the register 0x34 This is the register for setting the service identifier SI which is an interrupt condition after the first horizontal error correction It is possible to specify multiple service identifiers by setting 1 to the bits corresponding to the required service identifiers among the 16 types SIO to 515 in the above table 5 3 5 Receive port after the second horizontal error correction Table 5 3 5 Receive data port after the second horizontal error correction Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R B7 B6 B5 B4 B3 B2 B1 BO 0x38 W B7 B6 B5 B4 B3 B2 B1 BO Initial value The receive port after the second horizontal error correction is connected to the frame memory It is possible to read the frame memory successively since the frame memory address is incremented automatically whenever this port is read It is also possible to read this port starting from any required address Packets in a frame synchronization state are accumulated in the frame
16. See the precautions to be taken at the time of reading out the packet number and byte number given in the next page Byte number 17 DBO R 16 DB7 DB3 0 1 2 3 4 33 34 35 Packet number lt R_1E DB0 R_1D DB7 DB0 gt WN YN NN AN Y HONI 9 Y RRR RRR RRR SRNR mr EE EE Memory access inhibited ME segment due to vertical and NETT Second horizontal error 11 AN PWY RRR ERIK RRR RRR RR corrections N USA AQUA AQUA TRAN AN Y A Receive interrupt after the second horizontal error correction gt Memory access inhibited segment due to the first horizontal error correction when using only the main channel Memory access inhibited segment due to the first horizontal error correction when receiving by switching between main and sub channels 5 13 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Precautions in reading the packet number and byte number Since the microcontroller and data clocks are not mutually synchronized it is possible that wrong values are read out when reading out is made when the packet number or the byte number is changing Therefore it is necessary to read them twice successively and use only after confirming that there is a match between the two successive values 1 Memory access
17. after the first horizontal error correction MAIN 1 Indicates that a packet was received in the main channel 0 There is no interrupt in the main channel 5 5 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 7 DBO REAL This bit is not an interrupt This bit is cleared simultaneously with the receive interrupt after the first horizontal error correction when 1 is written in DB1 1 Indicates that the received packet is a REAL packet 0 The received packet is not a REAL packet 5 2 2 Interrupt mask This is a register that controls the interrupts corresponding to the bit numbers of the interrupt register 0x00 Table 5 2 2 Interrupt mask Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0x01 W Interrupt mask Interrupt mask Interrupt mask Interrupt mask Interrupt mask Interrupt mask Initial value 0 0 0 0 0 0 1 Interrupt enabled 0 Interrupt disabled 5 3 5 3 1 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS RECEIVE DATA REGISTERS When data is received that fact is reported by generating an interrupt and setting the INT pin to the 0 level after which the received data should be read out from the receive data port The receive data ports are the recive port 0x03 after first horizontal error correction from which data should be read out in units of a packet after the first horizontal error correction has been completed and the receive port
18. bit 0 0 0 No correction 0 0 1 1 bit 0 1 0 2 bits 0 1 1 3 bits 1 0 0 4 bits 1 0 1 5 bits 1 1 0 6 bits 1 1 1 7 bits 5 27 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 5 CLOCK REGENERATION REGISTERS 5 5 1 Fixed phase adjustment Table 5 5 1 Fixed phase adjustment Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W B B B4 B B2 B1 B 0x0B _ 6 5 3 0 Initial value 0 0 0 0 0 0 0 The phase of the regenerated data clock is adjusted Use with the initial value left unchanged 5 5 2 Integration constant before synchronization Table 5 5 2 Integration constant before synchronization Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W B3 B2 B1 BO 0x0C Initial value 0 0 1 0 This register specifies the number of times of extracting the timing necessary for carrying out phase control before block synchronization Specify 6 0x06 as a typical setting value 5 5 3 Integration constant after synchronization Table 5 5 3 Integration constant after synchronization Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W B B4 B B2 B1 B 0x0D 2 E Initial value 0 1 1 0 0 0 This register specifies the number of times of extracting the timing necessary for carrying out phase control after block synchronization Specify 16 0x10 as a typical setting value MSM956
19. block out of synchronization state 6 DB2toDB0 BIC Data Indicate the detection condition of the block identification code BIC DB2 DB1 DBO BIC No 1 0 0 1 1 0 1 2 1 1 0 3 1 1 1 4 0 E Not detected BYTE1 1 DB7 VICSRDY 1 Indicates that the received packet is a VICS packet 0 Indicates that the received packet is not a VICS packet 2 DB6 PARITY This bit indication is made only in a frame synchronization state 1 Indicates that the received packet is a parity packet 0 Indicates that the received packet is not a parity packet 5 9 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 3 DB5 INTO This bit indicates the receive interrupt after the first horizontal error correction Even though this bit indication is made in the reception condition after the second horizontal correction it is possible to confirm that reading has been made when a receive interrupt has occurred after the first horizontal error correction 1 Indicates that the received packet is one in which the receive interrupt occurred after the first horizontal error correction 0 Indicates that the received packet is one in which no receive interrupt occurred after the first horizontal error correction 4 DB4 DB3 0 fixed 5 DB2 FNCHG This bit indication is made only in a frame synchronization state 1 Indicates that the packet is one given in the following table 0 Indicates that the pack
20. leading byte 5 7 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS DBO MAINB SUB 1 The receive port after the first horizontal error correction is connected to the RAM LIBF SUB for the subchannel 0 The receive port after the first horizontal error correction is connected to the RAM LIBF for the main channel 5 3 2 Receive port after the first horizontal error correction and the receive data format Table 5 3 2 1 Receive port after the first horizontal error correction Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R B7 B6 B5 B4 B3 B2 B1 BO 0x03 W B7 B6 B5 B4 B3 B2 B1 BO Initial value Read This is the one packet receive data port after the first horizontal error correction The read address ofthe internal RAM is 0x00 when a receive interrupt after the first horizontal error correction has occurred When this port is read the read address is automatically incremented to the next read address and hence it is possible to carry out successive reads Write For testing only Writing to this port is prohibited during normal use Table 5 3 2 2 Receive data format after the first horizontal error correction Bit No DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO BYTEO CRCO ERCO RECCRC FSYNC BSYNC BICDET BIC1 BICO BYTE1 VICSRDY PARITY INTO 0 0 FNCHG FRNO1 FRNOO BYTE2 First horizontal correction receive data No 0
21. result Table 5 9 3 Layer 4 CRC result Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R L4CRC 0x2A result Initial value m 0 1 DBO L4CRC result 0 Normal 1 Error Read out the layer 4 CRC result when a time of 1 2us or more has elapsed after writing the last data of the data group 5 9 4 Layer 4 CRC register This is the register for writing the initial value directly in the CRC computation registers and for reading out the intermediate result It is possible to execute the layer 4 CRC processing of a short data group by interrupting the layer 4 CRC processing of a long data group Table 5 9 4 1 Layer 4 CRC register upper 8 bits Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R W B7 B6 B5 B4 B3 B2 B1 BO 0x2B m Initial value 0 0 0 0 0 0 0 0 Table 5 9 4 2 Layer 4 CRC register lower 8 bits Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R W B7 B6 B5 B4 B3 B2 B1 BO 0x2C Initial value 0 0 0 0 0 0 0 0 5 39 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 10 ANALOG TEST REGISTER Table 5 10 1 Analog test Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W DETO M2 M1 MO SGAIN1 SGAINO DETC 0x30 DTST Initial value 0 0 0 0 0 0 0 1 DBO DETC 3 For testing purposes only Use normally with DETC 0 DB2 to DB1
22. subchannel block synchronization DB5 DB4 Setting or clearing synchronization 1 0 Clearing synchronization 0 1 Setting synchronization 5 33 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 7 FRAME SYNCHRONIZATION REGISTERS 5 7 1 Number of frame synchronization backward protection steps Table 5 7 1 Number of frame synchronization backward protection steps Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W B1 BO 0x18 T Initial value 0 1 This register is used for setting the number of successive detections of synchronization points required before considering that the frame has been synchronized Number of frame synchronization DB1 DBO backward protection steps 0 0 1 0 1 2 1 0 3 1 1 4 5 7 2 Number of frame synchronization forward protection steps Table 5 7 2 Number of frame synchronization forward protection steps Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R B B2 B1 B 0x19 5 0 Initial value 0 1 0 0 Write This register is used for setting the number of successive detection failures of synchronization points before considering that the frame has been out of synchronized Number of frame synchronization DB3 DB2 DB1 DBO forward protection steps 0 0 0 0 0 Prohibited 0 0 0 1 1
23. successive DB1 DBO backward protection steps detections of BIC 0 0 1 1 0 1 2 2 1 0 3 3 1 1 4 4 Number of subchannel block synchronization backward protection steps Set value Number of block synchronization Number of successive DB5 DB4 backward protection steps detections of BIC 0 0 1 1 0 1 2 2 1 0 3 3 1 1 4 4 5 31 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 6 3 Number of block synchronization forward protection steps Table 5 6 3 Number of block synchronization forward protection steps Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO x12 R W SUB B2 SUB SUB SUB B3 B2 B1 BO Initial value 1 0 0 0 1 0 0 0 Write This register is used for setting the number of successive detection failures of the block identification code BIC before considering that the block has been synchronized DBO to DB3 Setting of the main channel block synchronization forward protection steps DB4 to DB7 Setting of the subchannel block synchronization forward protection steps Number of block synchronization DB7 DB2 086 DB5 DBO 084 forward protection steps 0 0 0 0 0 Prohibited 0 0 0 1 1 y 1 1 1 1 1 15 When BICs cannot be detected successively a block synchronization state the number of detection failures is decremented from the number of block syn
24. the parity packet and in this case the reception is reported by an interrupt generated at the timing of the 15th packet Before reading data from the receive port afterthe second horizontal error correction itis necessary to set the address pointer to Ox3D and the access mode 0x39 of the frame memory The address pointer consists of the packet number and the byte number and specifies the starting address of reading The setting of the access mode consists of setting the modes of horizontal vertical reading direction the parity read etc of the frame memory The frame data for example 190x24 bytes of the receive port after the second horizontal error correction can be read out either successively or intermittently Switching the receive port after the first horizontal error correction Table 5 3 1 Switching the receive port after the first horizontal error correction Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0x02 W MAINB SUB Initial value 0 Since the receive port after the first horizontal error correction is connected to the 36 byte RAM for the main channel LIBF and the RAM for the subchannel LIBF_SUB see Figure 5 1 it is necessary to switch between them according to the content of the receive interrupt register When a value is set in this register the RAM address pointer is reset and it is possible to read from the
25. width twRD See figure 4 2 90 ns RD a Read data output B RD delay 1 URBI ee DBO to DB7 Read data output RD 8 t i 20 ns delay 2 DRD2 See figure 4 2 DBO to DB7 Layer 4 data A CRC mod 9 Interval between write tiwawre coer 620 ns WR See figure 4 3 and write Layer 4 data A REOR 10 Interval between write tiwerpi ayer 1 2 us WR RD See figure 4 3 and read Interval between write uu 11 tIWRWR See figure 4 4 300 ns WR and write Continuously writing Interval between write 0x3B to 0x3D to the 12 tiwRWR1 550 ns WR and write same address See figure 4 5 Interval between write 13 tIWRRD See figure 4 4 300 ns and read Interval between read 14 tIRDRD See figure 4 6 300 ns RD and read INT 15 Interrupt CLR delay tpINTCLR See figure 4 7 200 ns WR 16 CLR pulse width twoLr See figure 4 8 200 ns CLR See TIMING DIAGRAM 4 8 MSM9563 User s Manual Chapter 4 ELECTRICAL CHARACTERISTICS 4 5 FILTER CHARACTERISTICS DVpp AVpp 2 7 to 3 6 V DGND AGND 0 V Ta 40 to 85 C No Parameter Symbol Condition Min Typ Max Unit Applied Pin BPF pass band nn 1 GAIN1 Variable gain amplifier 3 0 dB MON attenuation gain 0 dB BPF block band 2 GAIN2 Variable gain amplifier 50 dB MON attenuati
26. 0 should have been made in the register Ox39 Note 2 The setting PCTL1BL2 1 should have been made in the register 0x39 Write Before reading from the receive port after the second horizontal error correction of the register 0x38 it is necessary to set the packet number and the byte number in the register Specify the packet number of the starting byte and the starting byte number of the data to be read according to Table 5 3 6 1 Data configuration of the receive frame memory after the second horizontal error correction Thereafter successive reads will be possible according to the Access mode setting of the receive frame memory after the second horizontal error correction MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Read PCTL1BL2 0 Itis possible to know the byte number and the packet number of the data to be read next by reading these registers Ox3B Ox3C and Ox3D However it is necessary to set PCTL1BL2 of the register Ox39 to 0 Before reading these registers Read PCTL1BL2 1 The registers Ox3C and 0x3D indicate the frame memory address packet number of the data packet received after the first horizontal error correction which is to be written next 5 3 9 Reception status of the receive frame memory after the second horizontal error correction Table 5 3 9 Frame synchronization status Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R BANK BANK BANK BANK BANK _ _ERCFR1
27. 1 DBO W x x x x x x x x 0x1C A Initial value x x x x x x x x 5 35 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 8 ERROR CORRECTION REGISTERS The first horizontal error correction vertical error correction and the second horizontal error correction have been automated The results of correction and CRC can be read together with the receive data from the receive port after the first horizontal error correction and the receive port after the second horizontal error correction In addition the number of corrections and the threshold value have been set optimally Therefore normally there is no need to set the registers 0x20 0x21 0x22 0x23 0x24 and 0x25 5 8 1 Clearing address Table 5 8 1 Clearing address Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W B1 BO 0x20 Initial value 0 0 B1 BO Address Clear 0 1 for testing 1 0 5 8 2 Error correction data port Table 5 8 2 Error correction data port Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R B7 B6 B5 B4 B3 B2 B1 BO 0x21 W B7 B6 B5 B4 B3 B2 B1 BO Initial value 5 8 3 Error correction start Table 5 8 3 Error correction start Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Second i First R m m m m m horizontal horizontal correction correction state state st
28. 3 User s Manual Chapter 5 CONTROL REGISTERS 5 5 4 Phase correction step Table 5 5 4 Phase correction step Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W B B B4 B2 B1 B OxOE 5 5 U Initial value 0 0 1 0 0 1 This register is used for setting the phase correction step width of the digital PLL for data clock regeneration DBO to DB2 The phase correction step before block synchronization DB4 to DB6 The phase correction step after block synchronization DB2 DB6 DB1 DB5 DBO DB4 Phase correction step width 0 0 0 Prohibited 0 0 1 250nSec 0 1 0 500nSec 0 1 1 750nSec 1 0 0 1000nSec 1 0 1 1250nSec 1 1 0 1500nSec 1 1 1 1750nSec Set 1000ns 0x33 as a typical setting value 5 29 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 6 BLOCK SYNCHRONIZATION REGISTERS 5 6 1 Allowable number of BIC errors Table 5 6 1 Allowable number of BIC errors Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W BICGATE BICGATE B3 B2 B1 BO 0x10 SEL1 SUBISELO SUB Initial value 0 1 0 1 1 0 This is a specification related to the synchronization and clock regeneration processing of the MSM9563 and consists of the specification of the allowable number of error bits in the block identification code BIC 1 DB1toDB0 Allowable number of BIC errors before block synchronization common to ma
29. 5 DB4 DB3 DB2 DB1 DBO R Receive interrupt TIMINT TIMINT Receive interrupt Out of Receive interrupt REAL fter the fi fter the second ization after the fi eee SUB MAIN Synchronization Packet 0x00 correction SUB correction interrupt correction MAIN W Clear interruptClear interruptClear interruptiClear interrupt Clear interruptClear interrupt Initial value 0 0 0 0 0 0 0 1 Receive interrupt after the first horizontal error correction SUB 1 Indicates that a packet was received in a subchannel 0 There is no interrupt in the subchannels 2 DB6 TIMINT SUB 1 Indicates that an interrupt set by the subchannel timer has occurred 0 There is no interrupt in the subchannels 3 DB5 TIMINT MAIN 1 Indicates that an interrupt set by the main channel timer has occurred 0 There is no interrupt in the main channel Settings of the registers 0x05 0x16 0x17 Ox1D and Ox1E are necessary to activate the main channel timer interrupt 4 DB4 Receive interrupt after the second horizontal error correction 1 Indicates that an interrupt of the frame data reception after the second horizontal error correction of the main channel has occurred 0 There is no interrupt in the main channel 5 DB2 Out of synchronization interrupt 1 Indicates that an interrupt of frame out of synchronization has occurred 0 There is no interrupt in the main channel DB1 Receive interrupt
30. C Layer 4 CRC 5 38 110 0000 R W 0x28 0x29 Layer 4 CRC data buffer 00000000 RW Layer 4 CRC data buffer 5 38 Undefined R W 0x29 0x2A Layer 4 CRC result display 0 R Layer 4 CRC result display 5 39 0 R 0x2A 0x2B Layer 4 CRC register 1 2 00000000 RW Layer 4 CRC register upper 8 bits 5 39 00000000 R W 0x2B 0x2C Layer 4 CRC register 2 2 00000000 R W Layer 4 CRC register lower 8 bits 5 39 00000000 R W 0x2C 0x2D Ox2E 0x30 Analog control Analog section control monitor 000000 11111110 W Analog control Analog test 5 40 0000000 W 0x30 0x31 Power down Power down register 000 000 10001111 Power down Power down 5 41 000 000 W 0x31 0x32 Test control Test control 0 000 00011111 W Test control Test control O 5 42 000 W 0x32 0x33 Test control 1 0000000 10010111 W Test control 1 5 43 0000100 W 0x33 0x34 Receive data Receive interrupt conditions after first horizontal error correction 5 11 100100000 W 0x34 0x35 SI service identifier specification 532 11111111 W 0x35 0x37 Frame synchronization condition 5 20 0000000 R W 0x37 0x38 Receive port after second horizontal error correction 5 12 Undefined R W 0x38 0x39 Frame memory access mode 5 18 100000100 W 0x39 Ox3B Frame memory address 1 3 5 19 000000 R W Ox3B 0x3C Frame memory address 2 3 5 19 00000000 R W 0x3C 0x3D Frame memory addre
31. ED OPERATING CONDITIONS No Parameter Symbol Condition Range Unit Applied Pin AVpp AVpp 1 Power supply voltage AVpp DVpp 2 7 to 3 6 VI DVpp DVpp 2 Crystal oscillation 8 192 MHz 100 XTAL1 frequency MAE v Se S XTAL2 Variable amplifier gain 1 0 6 to 0 9 FM multiplex signal Variable amplifier gain x 1 5 0 4 to 0 6 3 VAN EE Vp p AIN input voltage Variable amplifier gain x 2 0 3 to 0 4 Variable amplifier gain x 3 0 2 to 0 3 4 Operating temperature Ta 40 to 85 C Peak values total voltage of the following signals of composite signals including multiplex signals a Voice signals 100 modulated voice max b Pilot signal c FM multiplex signals 1096 LMSK max The maximum amplitude of an input signal is in the range of 0 9 Vp p in which the internal IC circuit is not saturated Therefore multiplex singnals of up to 0 9 Vp p can be input if only multiplex signals excluding composite signals are input from a signal generator MSM9563 User s Manual Chapter 4 ELECTRICAL CHARACTERISTICS 4 3 DC CHARACTERISTICS DVpp AVpp 2 7 to 3 6 V DGND AGND 0 V Ta 40 to 85 C No Parameter Symbol Condition Min Typ Max Unit Applied Pin 0 8 x WR RD V MN IH DVpp XOUTC 1 Input voltage V DBO to DB7 V e CS A0 to A5 IL 2 DVpp CLR DVpp MOUTO to V 1 mA
32. FRCK7IINT FRCK6INT FRCKSINT FRCK3INT FRCK2INT FRCK1INT FRCKO Note 2 _SUB _SUB _SUB _SUB _SUB _SUB _SUB _SUB Initial value 0 0 0 0 0 0 0 0 Note 1 The setting SETTIMCK SUB R_05 DB4 1 05 DB5 0 should have been made the register 0x05 Note 2 the register 0x05 5 25 The setting SETINTCK SUB 05 DB4 0 05 DB5 1 should have been made in MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Read FRCK8 SUB MSB to FRCKO SUB LSB indicate the packet number of the packet being received FRCK8 SUB is allocated to DBO of the register 0x09 Write FRCK8 SUB to FRCKO SUB This is the register for specifying the initial value of the packet number in the subchannel packet counter Since the subchannel does not have a built in frame synchronization circuit it is necessary for the user to set the packet number To obtain the packet number achieve frame synchronization temporarily with the main channel and write that packet number FRCK8_SUB is allocated to DBO of the register 0x09 Write INTFRCKO SUB to INTFRCK8 SUB This is the register for specifying the interrupt packet number of the subchannel Timing interrupts occur at all packets if the setting INTALLFRCK SUB 1 register 0x09 is made Carry out the setting of SETINTCK SUB in the register 0x09 before setting this register INTFRCK8 SUB is allocated to DBO of the register 0x09 5 4 6 Interrupt frame number se
33. OKI MSM9563 IC for FM Multiplex Data Demodulation User s Manual Hardware SECOND EDITION ISSUE DATE Dec 1999 FEUL9563 02 IMPORTANT NOTICE DARC DAta Radio Channel an FM multiplex broadcast technology has been developed by NHK Japan Broadcasting Corporation DARC is a registered trademark of NHK Engineering Service NHK ES Any manufacturer who intends to manufacture sell products that utilize DARC technology needs to be licensed by NHK ES For detailed information on licenses please contact NHK Engineering Service Phone 481 3 3481 2650 DARC DAta Radio Channel an FM multiplex broadcast technology has been developed by NHK Japan Broadcasting Corporation DARC is a registered trademark of NHK Engineering Service NHK ES Any manufacturer licensed by NHK ES can manufacture and sell products that utilize the DARC technology The products utilizing the DARC technology can be marked with the logotype shown to the left In the DARC system 16kbps of digital data L MSK modulated at 76KHz are multiplied on an ordinary FM broadcast base band signal An FM multiplex demodulation LSI performs decoding of the digital data DATA RADIO CHANNEL signal RU For detailed information license please contact NHK Engineering Service Phone 81 3 3481 2650 E2Y0002 29 62 NOTICE 1 9 The information contained herein can change without notice owing to product and or technical improvement
34. RC of the packet after the first horizontal error correction 0 Indicates that the CRC of the packet is normal after the first horizontal error correction 2 DB6 ERCO 1 Indicates that there is an error in the correction result of the packet after the first horizontal error correction 0 Indicates that the correction result of the packet is normal after the first horizontal error correction MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 3 085 RECCRC 1 Indicates that there is an error in the CRC of the received packet before error correction 0 Indicates that the CRC of the received packet is normal before error correction 4 DB4 FSYNC 1 Indicates that the received packet is in a frame synchronization state 0 Indicates that the received packet is in a frame out of synchronizaiton state 5 083 BSYNC 1 Indicates that the received packet is in a block synchronization state 0 Indicates that the received packet is in a block out of synchronization state 6 DB2 DBO BIC Monitor Indicate the detection condition of the block identification code BIC DB2 DB1 DBO BIC No 1 0 0 1 1 0 1 2 1 1 0 3 1 1 1 4 0 Not detected Reception status 1 1 DB7 VICSRDY 1 Indicates that the received packet after the second horizontal error correction is a VICS packet 0 Indicates that the received packet after the second horizontal error correction is not a VICS
35. S 19SN E9SGINSIN SH31SIO3H TOHINOD 491deyo 5 1 3 Page mode Table 5 1 3 Page mode MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W MAINCH MOD CLRMCO MOD PAGEO Ox3E Note _CLRB PARITERC2 _PAGE PAGE Initial value 0 0 0 0 0 0 Note The settings MOD 508 1 and MOD MAIN O should be made in the register 0x04 By setting the page mode it is possible to automatically accumulate the received data after the first horizontal error correction in the frame memory However the frame synchronization vertical error correction and the second horizontal error correction are not made in the page mode The frame memory can be divided into the receive data accumulation area after first horizontal error correction and the user area and the sizes of the two areas are variable DB3 The received packets are written startig from the packet address 0 if CLRMCO PAGE is set to 1 Frame memory configuration page mode Receive data accumulation area after the first horizontal error correction User area Receive data accumulation area after the first horizontal error correction and user area Register 0x3E Receive data accumulation area User area set value after the first horizontal error correction 0x04 Packets 0 to 31 Packets 32 to 272 0x05 Packets 0 to 63 Packets 64 to 272 0x06 Packets 0 t
36. aaa aani enia 3 2 4 ELECTRICAL CHARACTERISTICS 4 1 4 1 ABSOLUTE MAXIMUM RATINGS 4 1 4 2 RECOMMENDED OPERATING CONDITIONS 4 1 43 DG CHARACTERISTICS ri nte 4 2 4 4 AG CHARACTERISTICS iii iiiter 4 3 4 5 FILTER CHARACTERISTICS 4 4 4 6 TIMINGIDIAGRAM 2 2 tot reed ea 4 5 5 CONTROL REGISTERS ii aeo otn attt tre rece 5 1 5 1 OPERATING MODE REGISTERSG retinent trentaine 5 1 5 2 INTERRUPT REGISTERS ettet 5 5 5 3 RECEIVE DATA REGISTERS ritenere teer un 5 7 5 4 TIMING INTERRUPT REGISTERS 5 21 5 5 CLOCK REGENERATION REGISTERS esee 5 28 5 6 BLOCK SYNCHRONIZATION REGISTERS sese 5 30 5 7 FRAME SYNCHRONIZATION REGISTERS 5 34 5 8 ERROR CORRECTION REGISTERS 5 36 5 9 LAYER 4 CRO REGISTERS nitet inet rire 5 38 5 10 ANALOG TEST REGISTER rancia 5 40 5 11 POWER DOWN REGISTER 5 41 512 TEST CONTROL REGISTERS ict ortae ecrit iti 5 42 5 13 EXTENSION PORT REGISTER 5 44 6 EXTERNAL CONNECTION EXAMPLE 6 1 7 APPLICATION GIRGUIT seco teen eese cash 7 1 APPENDIX LIST OF REGISTER rnnt tatit er eese Appendix 1
37. annel reception mode MOD_OFF 0 0 The mode used for isolating the synchronization circuit after tuner switching until the tuning becomes stable 5 1 2 Frame format Table 5 1 2 Frame format Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W B1 BO Ox1F Initial value 1 0 Set value Frame Symbol Remarks DB1 DBO configuration 0 0 Format A A0 0 1 A1 Includes real time information blocks 1 0 Format B B Used in Japan 1 1 Format C C 5 1 eS Sub eee Tuner switching _MAIN SUB Tuner Data reproduction Main station Timing interrupt SUB R 00 Channel connection Timer SUB Bus disconnection _SUB R_04 amp Clock regeneration Block synchronization _SUB _SUB Receive Receive RAM after first L1BF_SUB RAM switching horizontal error correction _SUB d R_02 Xo Receive RAM after first horizontal error correction MAIN L1BF Frame memory Clock regeneration Block synchronization Frame synchronization MAIN MAIN 7 _MAIN Channel connection disconnection MAIN R 04 Timer MAIN Timing interrupt MAIN MSM9563 Figure 51 Main Subchannel switching receive block diagram jenueyy
38. ate 0x22 W _ Startsecond Start Start first horizontal vertical horizontal correction correction correction Initial value 5 36 5 8 4 Number of corrections and error correction results MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Table 5 8 4 Number of corrections and error correction results Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R Result of Result of Second First NW horizontal horizontal correction correction CRC result 0x23 W Number of Number of Number of Number of Number of Numberof MOD MOD f e ME MES BL corri acions B2 correctors Bi conetons 80 A M A Initial value 1 1 1 1 1 0 1 1 5 8 5 Results of vertical error correction Table 5 8 5 Results of vertical error correction Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0x24 R CRCOUT7 CRCOUTE6 CRCOUTS CRCOUT4 CRCOUTS8 CRCOUT2 CRCOUT1 CRCOUTO Initial value 0 0 0 0 0 0 0 0 5 8 6 Number of corrections and threshold value Table 5 8 6 Number of corrections and threshold value Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W Number of of Number of Threshold Threshold Threshold Threshold Threshold 0x25 horizontal horizontal horizontal Value value value value value corrections _B2 corrections _B1 corrections_BO
39. byte counter Data clock _SUB Figure 5 4 2 TIMINT_SUB block diagram 5 21 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 4 1 Timing interrupt mode Since some of the interrupt timing registers have been mapped to the same address this register controls their selection and timing enable conditions Table 5 4 1 Interrupt timing mode Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W TIMINTEN SETCK1 SETCKO RDBSCK TIMINT SETINT 0x05 _SUB _SUB _SUB _SUB EN_MAIN CK_MAIN Initial value 0 0 0 0 0 0 1 DB6 SUB 1 Activates the timing interrupt of the subchannel 0 Disables the timing interrupt operation of the subchannel Set the interrupt timing after making this bit 0 and change this bit to 1 after the setting is completed 2 DB5 DB4 SETCK1 SUB SUB DB5 DB4 Set mode Description 1 1 SETMAX_SUB Enables the setting of a count value of the maximum number of frames in the register 0x09 1 0 SETINTCK SUB Enables the setting of the interrupt timing value in the registers 0x06 to 0x09 0 1 TSETTIMCK SUB Enables the setting of the initial value of the timer counter in the registers 0x08 to 0x09 3 DB3 RDBSCK SUB 1 Makes it possible to read the block counter value of the subchannel 0 Makes it possible to read the block counter value latched immediately before block s
40. chronization forward protection steps and when the value of this register changes from 1 to O the block is considered to have been out of synchronization Remaining number of DES ei n DBA block synchronization uu Out of synchronization forward protection steps Synchronization detection 0 0 0 0 0 a 1 When BIC gt cannot be detected 1 1 1 1 15 Loaded during synchronization 5 32 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 6 4 Block synchronization monitor Table 5 6 4 Block synchronization monitor Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R BSYN B BSYN 0x13 _ SYNC SU SYNC Initial value 0 0 DBO Main channel block synchronization state 0 Block out of synchronization 1 Block synchronized DB4 Subchannel block synchronization state 0 Block out of synchronization 1 Block synchronized 5 6 5 Setting clearing block synchronization Table 5 6 5 Setting clearing block synchronization Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W B1 B1 B 0x14 _ _SU 0_SU 0 Initial value 0 0 0 0 Setting clearing main channel block synchronization DB1 DBO Setting or clearing synchronization 1 0 Clearing synchronization 0 1 Setting synchronization Setting clearing
41. cket being received The upper 6 bits indicate the byte number Write This is the register for specifying the main channel interrupt byte number Before setting this register set TIMINTEN MAIN 1 and SETINTCK 1 in the register 0x05 This matches with the received data byte number in a block synchronization state The interrupt occurs at the leading part of a change in the byte number Specify bytes 0 to 35 using the 6 bits INTBCKS to INTBCK8 5 4 3 Interrupt packet number specification main channel Table 5 4 3 1 Interrupt timing MAIN packet number 1 2 Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R FRCK7 FRCK6 FRCK5 FRCK4 FRCK3 FRCK2 FRCK1 FRCKO W INT INT INT INT INT INT INT INT Note 1 FRCK7 FRCK6 FRCK5 FRCK4 FRCK3 FRCK2 FRCK1 FRCKO Initial value 0 0 0 0 0 0 0 0 Note 1 The setting SETINTCK 1 should have been made in the register 0x05 5 23 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Table 5 4 3 2 Interrupt timing MAIN packet number 2 2 Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R ACTMCO ACTMC2 ACTMC1 ACTMCO FRCK8 _SUB Ox1E W INT INT Note 1 ALLFRCKTIM FRCK8 Initial value 0 0 0 0 0 0 Note 1 The setting SETINTCK 1 should have been made in the register 0x05 Read FRCK8 MSB to FRCKO LSB indicate the packet number of the packet being received Write This is the register for specifying the main channel i
42. ercial applications e g office automation communication equipment measurement equipment consumer electronics etc These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans Such applications include but are not limited to traffic and automotive equipment safety devices aerospace equipment nuclear power control medical equipment and life support systems Certain products in this document may need government approval before they can be exported to particular countries The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these No partofthe contents contained herein may be reprinted or reproduced without our prior permission MS DOS is a registered trademark of Microsoft Corporation Copyright 1999 Oki Electric Industry Co Ltd Printed in Japan TABLE OF CONTENTS 1 GENERAL DESCRIBTION LLO FY LED noda dan n nr ardid 1 1 2 BLOCK DIAGRAM eit teet tentia eei trate rear 2 1 3 PIN INFORMATION m 3 1 3 1 PIN CONFIGURATION TOP VIEW 3 1 3 2 PIN DESCRIPTIONS riti cte rene
43. et is one other than those indicated in the following table Frame format Format B Format A1 Packet with a block number of 0 13 136 Packet with a block number of 0 60 130 or 149 or 190 Note The packet numbers are expressed in this manual as 0 to 271 A1 O to 283 DB1 DBO FRNO1 FRNOO These bit indications are made only in a frame synchronization state These bits indicate that the packet is one with the block numbers given in the following table Frame format DBO Format B Format A1 A0 Packet with a block number of 0 to 12 Packet with a block number of 0 to 59 Packet with a block number of 13 to 135 Packet with a block number of 60 to 129 Packet with a block number of 136 to 148 Packet with a block number of 130 to 189 Packet with a block number of 149 to 271 Packet with a block number of 190 to 271 Packet with a block number of 190 to 283 Note packet numbers are expressed in this manual as 0 to 271 A1 O to 283 5 10 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 3 3 Conditions of receive interrupt after the first horizontal error correction Table 5 3 3 1 Conditions of receive interrupt after the first horizontal error correction Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W MOD MODCH MOD MOD MOD MOD MOD SISEL 0x34 FSYNC OFFDET INTO ERCO PARITO BICDETO 51 Initial value 0 0 1 0 0 0 0 0
44. frame number The range of setting is Oto 15 Carry out the settings of TIMINTEN SUB and SETINTCK ofthe register 0x05 before setting this register Write MAXFNCKO SUB to MAXFNCKS3 SUB This is the register for setting the maximum value of the frame number counter The range of setting is O to 15 When the frame number counter reaches the set value it is reset to 0 and continues counting 5 4 7 Clock timing adjustment subchannel Table 5 4 7 Subchannel BCK adjustment Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W BCKINC B2 B1 BO 0x0A _SUB Initial value 0 0 0 0 The subchannel packet interval is adjusted in units of a bit When intermittent reception is being made at intervals of several frames this function enables the accurate setting of the position of the packet to be received next The range of adjustment at a time is 7 bits Carry out this adjustment at the most once per packet when no reception is being made The number of bits of adjustment required is the difference between 16 and the value of the registers 0x06 to 0x07 when a subchannel packet is received 1 083 BCKINC SUB 1 Added the number of correction bits set in DBO to DB2 0 Eliminated the number of correction bits set in DBO to DB2 2 DBOto DB2 BO to B2 These specify the range of adjustment in number of bits The maximum value is 7 bits DB2 DB1 DBO Correction
45. ible with MSM9553 MSM9555 Internal frame memory enables automatic error correction Built in bandpass filter SCF Built in block synchronization circuit and frame synchronization circuit The number of synchronization protecting steps can be set Regeneration of data clocks by digital PLL 1T delay detector Built in error correcting circuit Vertical Horizontal Built in layer 4 and layer 2 CRC processing circuit International frame formats A supporting a real time block B and C available Microcontroller parallel interface Clock output for external devices 64 kHz to 8 192 MHz selectable Power source 2 7 to 3 6 V Package 44 pin plastic QFP QFP44 P 910 0 80 2K Product name MSM9563GA 1 1 MSM9563 User s Manual Chapter 1 GENERAL DESCRIPTION 1 2 Chapter 2 BLOCK DIAGRAM FM multiplex 1 O signal input Block Frame Timing Clock synchronization synchronization control generator Filter Section PN Error Descrambler Receive RAM Layer 4 CRC Layer 2 CRC IC internal clock Data bus Delay Detection Section Address bus Frequency O s CPU interface 1T delay ERES XTAL2 XTAL1 Data Add RD WR CS CLR INT Digital Signal Processing Section Figure 2 1 Block Diagram lt INVH9VIG 320718 INVHOVIG 42018 1919 45 jenueyy S Jesf 9S6WSW MSM9563 User s Manual Chapter 2 BLOCK DIAGRAM 2 2 Chapter 3 PIN INFORMATION MSM9563 User s Manual Cha
46. in channel and subchannels Set value Allowable number of BIC errors DB1 DBO before block synchronization 0 0 0 0 1 1 1 0 2 1 1 3 2 DB3to DB2 Allowable number of BIC errors after block synchronization common to main channel and subchannels Set value Allowable number of BIC errors DB3 DB2 after block synchronization 0 0 0 0 1 1 1 0 2 1 1 3 3 DB7 to DB6 BICGATESEL1 SUB to BICGATE SELO SUB The segments given in the following table are added to the BIC detection segments in addition to the leading two bytes of the packet when used in the subchannel mode Set value BIC Detection gate width DB7 DB6 0 0 0 1 1 Byte 1 0 1 5 Byte 1 1 2 Byte 5 30 5 6 2 Number of block synchronization backward protection steps MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Table 5 6 2 Number of block synchronization backward protection steps Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W B1 SUB SUB B1 B0 0x11 Initial value 0 0 0 1 This register is used for setting the number of successive detections of the block identification code BIC before considering that a block has been synchronized Number of main channel block synchronization backward protection steps Set value Number of block synchronization Number of
47. ing settings for testing purposes Normally use with the settings of DB7 DB6 0 2 DB5 VLBCNT 1 The frame memory is read in the vertical direction in an ascending order ofthe packet number with the byte number being kept fixed 0 The frame memory is read in the horizontal direction in an ascending order ofthe byte number with the packet number being kept fixed The packet number is incremented by 1 when the byte number reaches that specified by LBACKO and LBACK1 3 DB4 PCTL1BL2 The readable frame memory address packet number is selected from the registers OX3C and 0x3D 1 Enables the MSM9563 to read the address packet number of the receive data packet that is being written 0 Enables an external microcontroller to read the address packet number of the receive data packet that is being accessed 4 DBS VBACK 1 When the packet number becomes 272 the next packet number will be reset to 0 For testing purposes only 0 When the packet number becomes 189 the next packet number will be reset to 0 5 DB2 DB1 LBACK1 LBACKO The next byte number is reset to the byte number specified by LSTART when the current byte number becomes the returning byte number given in the following table LBACK1 Returning byte No 0 0 1 0 1 2 1 0 23 1 1 35 69 DBO LSTART 1 The next byte number is reset to 2 when the current byte number becomes equal to the val
48. is possible for about 2 Checking the byte number and 16msec after the timing interrupt the packet number of Figure 5 3 Timing interrupt setting Timing interrupt setting Second horizonta correction receive interrupt Second horizonta correction receive interrupt FLG_ERC2 1 Timing interrupt setting MAIN R_05 0x01 Byte number 2 setting MAIN R_16 0x10 R_17 0x00 Timing interrupt setting MAIN for each packet Timing interrupt setting R_1E 0x02 Byte number read Timing interrupt EN_MAIN R_05 0x02 First read second read Timing interrupt setting 1 lt Byte number lt 34 Y Access possible Access possible n is the time of accessing the memory 5 14 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 3 6 Data configuration of the receive frame memory after the second horizontal error correction Table 5 3 6 1 Receive frame memory data configuration after the second horizontal error correction Byte No Packet No 0 1 2 23 24 35 Reception Reception Data 0 Data 21 CRC PARITY 0 status 0 status 1 PARITY Reception Reception Data 0 Data 21 CRC PARITY 189 status 0 status 1 PARITY Reception Reception Vertical Vertical Vertical Vertical Vertical Vertical 190 tatus 0 tatus 1 correction correction correction correc
49. is register controls serial receive data and the switching of the test output pins MOUT5 and MOUT6 This is used for testing only 1 DBO DB4 Serial receive data output DB4 DBO MOUTS pin output 0 0 Fixed to L 0 1 Serial receive data after descrambling 1 0 1 1 Serial receive data before descrambling 2 DB1 16kHz regeneration data clock 0 The MOUTS pin is fixed to 1 1 A 16kHz regeneration data clock is output to the MOUTS pin 3 DB2 Differential decoding control 0 Performs differential decoding to input data 1 Does not perform differential decoding This is used for receiving FM multiplex broadcast 4 DB3 Descramber control 0 Descrambles data other than BIC This is used for receiving FM multiplex broadcast 1 Does not descramble other than BIC 5 43 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 DB5 DB6 Delay detector output control DB6 DB5 Delay detector control 0 0 ENOR FM multiplex broadcast reception 0 1 Through data before 1T 1 0 EOR 1 1 5 13 EXTENSION PORT REGISTER It is possible to output the write data DBO to of this register to the monitor output terminal by setting and or 0x00 in the register 0x32 Table 5 13 Extension port register Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W DB4 DB3 DB2 DB1 DBO OxOF Initial value 0 0 0 0 0
50. iting is prohibited under normal use 5 20 5 4 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS TIMING INTERRUPT REGISTERS There are the two timing interrupts of TIMINT_MAIN which operates in synchronization with the main channel and the timing interrupt TIMINT_SUB which operates in synchronization with the subchannel The block diagram of TIMINT_MAIN is shown in Figure 5 4 1 The timing interrupt TIMINT_MAIN occurs when the packet number and byte number of the main channel match with the set interrupt timing The block diagram of TIMINT_SUB is shown in Figure 5 4 2 The timing interrupt TIMINT_SUB occurs when the packet number byte number and frame number of the subchannel match with the set interrupt timing It is possible to set TIMINT_SUB at intervals of 0 to 15 frames Itis necessary to carry out initial setting of the timing of the packet number and frame number when synchronized with a subchannel Bus Setting of FRCK_MAIN TIMINTEN_MAIN and BCK_MAIN Timing interrupt setting register Compare TIMINT_MAIN amp enable Packet and byte counter Data clock _MAIN Figure 5 4 1 TIMINT_MAIN block diagram Bus INTFRCK_SUB and B INTBCK SUB M Timing interrupt setting register Setting of MAXFNCK SUB Compare SUB FNCK SUB and FRCK SUB amp A enable BCK_SUB Adjustment Frame packet and
51. me format specification 5 1 10 W 0x1F 1 Unused bits are entered as 1 2 Unused bits are entered as 2 1 593151999 JO 157 XIGNAddV Jenue y 195 9S6lA SIN c xIpueddy MSM9552 9553 reference MSM9562 9563 Register Initial Recommended Initial Recommended Register Category Register name R W Category Register name R W address value value No value value address 0x20 Error Internal address counter clear XXXXXXXX W Error Internal address counter clear 5 36 00 W 0x20 0x21 correction Data transfer port for error correction Undefined R W correction Data transfer port for error correction 5 36 R W 0x21 0x22 Start signal for error correction 000 R W Start signal for error correction 5 36 R W 0x22 0x23 CRC Result display second horizontal error 0 0 R Number of corrections and error correction result 5 37 111111011 R W 0x23 0x24 Error correction result display 00000000 R Vertical error correction result 5 37 100000000 R 0x24 0x25 Majority logic threshold value 01000 11101001 W Number of vertical error corrections and threshold value 5 37 11101110 W 0x25 0x28 Layer 4 CRC Clear layer 4 CRC registers 11000000 R W Layer 4 CR
52. memory When the reception of one full frame is completed the vertical error correction and the second horizontal error correction are made and the receive interrupt after the second horizontal error correction occurs at the timing of the 13th packet in the next frame Although it is possible to receive from the middle of a frame the vertical error correction will be omitted in that case The frame synchronization state is indicated in the register 0x37 by dividing it into four groups On the other hand it is also possible to know this from the status indication byte at the beginning of each packet The volume of data in the frame memory is 24x190 bytes in the case of 4 layer data including packet status indication 36x273 bytes in the case of data including parity etc See the data format of the receive frame memory after the second horizontal error correction in Section 5 3 6 for the detailed contents of data CAUTION The frame memory has segments that are prohibited from being accessed See Figure 5 3 for details 5 12 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Figure 5 3 Access prohibited segments of the frame memory R 38 1 Theframe memory access inhibited time occurs when the intersection of the packet number and the byte number correspond to the hatched parts in the follwoing figure 2 Itis possible to know the packet number and the byte number by reading out the registers 1D 16 and 17
53. nterrupt packet number Timing interrupts occur at all packets when the setting ALLFRCKTIM 1 is made Before setting this register set TIMINTEN MAIN 0 and SETINTCK 1 in the register 0x05 This matches with the packet number of received data in a frame synchronization state 544 Interrupt byte number specification subchannel Table 5 4 4 1 Interrupt timing SUB byte number 1 2 Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R PRE BCK7PRE BCK3PRE BCK2PRE BCK1PRE BCKO Note 1 _SUB _SUB _SUB _SUB _SUB _SUB _SUB _SUB R BCK7 BCK6 BCK5 BCK4 BCK3 BCK2 BCK1 BCKO 0x06 Note 2 _SUB _SUB _SUB _SUB _SUB _SUB _SUB _SUB W INTBCK7 INTBCK6 INTBCK5 INTBCK4 INTBCK3 Note 3 _SUB _SUB _SUB _SUB _SUB Initial value 0 0 0 0 0 0 0 0 Note 1 The setting RDBSCK_SUB 0 R_05 DB3 0 should have been made in the register 0x05 Note 2 The setting RDBSCK_SUB 1 R_05 DB3 1 should have been made in the register 0x05 Note 3 The setting SETINTCK_SUB R_05 DB4 0 R_05 DB5 1 should have been made in the register 0x05 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Table 5 4 4 2 Interrupt timing SUB byte number 2 2 Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R m m 8 Note 1 _SUB R BCK8 0x07 Note 2 _SUB W INTBCK8 Note 3 _SUB Initial value
54. o 127 Packets 128 to 272 0x07 Packets 0 to 271 Not present 5 3 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 1 4 Main channel clear bit MAINCH_CLRB This MAINCH CLRB bit DB6 of register OX3E has been provided to speed up switching to the main channel When this bit is set to 1 MAINCH CLRB BIT 6 1 the main channel synchronization error correction internal frame memory control section and interrupt will be reset However the parameter setting registers the counter for synchronization and the pointer for reading out the frame memory are not cleared Since the reset condition is retained after switching the tuner reset this bit to 0 MAINCH CLRB DB6 0 thereby releasing the reset condition Thereafter reception starts even if the register is not set again Although the frame memory is not cleared the new receive data will be written over the old ones Main channel tuner switching Main channel clearing R_3E 0x40 Tuner switching Main channel reset release 3bE 0x00 End MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 2 INTERRUPT REGISTERS 5 2 1 Interrupt register When an interrupt occurs 1 is written in this register and the INT Pin is set to the 0 level After reading out this register write a 1 in the corresponding bit of this register to clear the interrupt Table 5 2 1 Interrupt register Address R W DB7 DB6 DB
55. on 1 gain 0 dB BPF block band un 3 GAIN3 Variable gain amplifier 50 dB MON attenuation 2 gain 0 dB 4 4 MSM9563 User s Manual Chapter 4 ELECTRICAL CHARACTERISTICS 4 6 TIMING DIAGRAM Address input X X CS input WR input Figure 4 1 Write Timing Address input x X sm mp j CS input i tup twa o DRD2 Data bus output Figure 4 2 Read Timing MSM9563 User s Manual Chapter 4 ELECTRICAL CHARACTERISTICS Address input X 0x29 X 0x2A Data bus input Layer 4 data Layer 4 data Layer 4 data CRC result lWRWR2 tIWRRD1 Figure 4 3 Layer 4 CRC mode and Layer 4 VICS mode Timing Address input 0x3B X 0x3C X 0x3D x 0x38 i tiwrRD Figure 4 4 Internal between write and write or between write and read 0x3D 0x3D 0x3C 0x3C Address input Ox3B ES 0x3B lIWRWRI Figure 4 5 When 0x3B to 0x3D are continuously written at the same address This is a rare case MSM9563 User s Manual Chapter 4 ELECTRICAL CHARACTERISTICS Address input xX X X IRDRD i RD Figure 4 6 Intarval between read and read Address signal input x 0x00 x Data signal input XXXX01XX WR input INTCLR signal a TNT outpu
56. or 191 in the case of the frame formats AO and A1 0 Indicates that the packet is one other than the above 7 DB1 DBO FRNO1 FRNOO These bit indications are made only in a frame synchronization state These bits indicate that the packet is one with the block numbers given in the following table Frame format DB1 DBO Format B Format A1 A0 Packet with a block number of 0 to 12 Packet with a block number of 0 to 59 Packet with a block number of 13 to 135 Packet with a block number of 60 to 129 Packet with a block number of 136 to 148 Packet with a block number of 130 to 189 1 Packet with a block number of 149 to 271 AO Packet with a block number of 190 to 271 A1 Packet with block number of 190 to 283 Note The packet numbers are expressed in this manual as O to 271 A1 O to 283 0 0 1 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 3 7 Setting the receive frame memory access mode after the second horizontal error correction Table 5 3 7 Frame memory access mode Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W BANK BANK VLBCNT PCTL1 VBACK LBACK1 LBACKO LSTART 0x39 CONT1 CONTO BL2 Initial value 0 0 0 0 0 1 0 0 This is the register for setting the access mode so that reading can be done efficiently when reading the frame memory successively 1 DB6 BANK1 BANKO These bits are for mak
57. packet 2 086 PARITY This bit indication is made only in a frame synchronization state 1 Indicates that the received packet is a parity packet 0 Indicates that the received packet is not a parity packet 3 DB5 INTO 1 Indicates that the received packet is the one in which the receive interrupt occurred after the first horizontal error correction It is not necessary to read this if the reading has already been done during the reception after the first horizontal error correction 0 Indicates that the received packet is one in which no receive interrupt occurred after the first horizontal error correction 5 16 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 4 DB4 CRC2 1 Indicates that there is an error in the CRC of the packet after the second horizontal error correction 0 Indicates that the CRC of the packet is normal after the second horizontal error correction 5 DB3 ERC2 1 Indicates that there is an error in the correction result of the packet after the second horizontal error correction 0 Indicates that the correction result of the packet is normal after the second horizontal error correction Note CRC2 ERC2 0 is necessary for the packet to be good error free 6 DB2 FNCHG This bit indication is made only in a frame synchronization state 1 Indicates that the packet is one with a block number of 1 14 137 or 150 in the case of the frame format B and with a block numaber of 1 61 131
58. pter 3 PIN INFORMATION 3 PIN INFORMATION 3 1 PIN CONFIGURATION TOP VIEW cc m NC NC NC NC 5 2 N N co LO lt Ut Ut MON 9 33 A0 ADETIN 32 XOUT AVpp 31 CS AGND 30 XTAL2 SG 29 XTAL1 AIN 281 DVpp XOUTC 27 DGND MOUTO 26 DB7 MOUT1 25 086 MOUT2 24 085 MOUT3 23 084 8 LO co E cc o aO T N 88 o o o 44 Pin Plastic QFP Figure 3 1 Pin Layout Leave the NC pins 17 39 41 42 43 and 44 open 3 1 MSM9563 User s Manual Chapter 3 PIN INFORMATION 3 2 PIN DESCRIPTIONS Table 3 1 Pin Description Function Symbol Pin Type Description Microcontroller WR 16 Write signal to internal register interface RD 18 Read signal to internal register INT 15 0 Interrupt signal to microcontroller When set to L an interrupt is generated CS 31 Chip select signal When set to L the read write and data bus signals become effective CLR 40 When set L the internal register is initialized and the IC enters power down mode A0 to A5 33 to 38 Address signal to internal register DBO to DB7 19to 26 1 0 Data bus signal to internal register Tuner interface AIN 6 FM multiple signal input
59. r s Manual Chapter 7 APPLICATION CIRCUIT 7 2 APPENDIX L xipueddy MSM9552 9553 reference MSM9562 9563 Register Initial Recommended Page Initial Recommended Register Category Register name R W Category Register name R W address value value 1 No value value 2 address 0x00 Interrupt Interrupt cause 0 000000 R W Interrupt Interrupt register 5 5 0000 000 R W 0x00 0x01 Interrupt mask 000000 W Interrupt mask 5 6 0000 00 W 0x01 0x02 Receive data Receive block condition 00000000 data Receive port selection after first horizontal error correction 5 7 0 W 0x02 0x03 Receive data and first horizontal error correction data port Undefined R Receive port after first horizontal error correction 5 8 Undefined R W 0x03 0x04 Receive RAM data accumulation condition and address clear 0 11111111 W Operating mode Main channel subchannel mode setting 5 1 0 1 W 0x04 0x05 Timing iming interrupt mode 5 22 0000 00 W 0x05 0x06 interrupt Interrupt timing SUB byte number 1 2 5 24 00000000 R W 0x06 0x07 BIC Monitor 000 R nterrupt timing _SUB by
60. s Before using the product please make sure that the information being referred to is up to date The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product When planning to use the product please ensure that the external conditions are reflected in the actual circuit assembly and program designs When designing your product please use our product below the specified maximum ratings and within the specified operating ranges including but not limited to operating voltage power dissipation and operating temperature Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse neglect improper installation repair alteration or accident improper handling or unusual physical or electrical stress including but not limited to exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range Neither indemnity against nor license ofa third party s industrial and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof The products listed in this document are intended for use in general electronics equipment for comm
61. ss 3 3 5 19 0 R W Ox3D Ox3E Operating mode Page mode clear main channel 5 3 1 0 00000 W OxOF Extension port Extension port 00000 W Extension Extension port 5 43 00000 W OxOF SH31SI938 JO 151 XIGNAddV jenueyy S 19SN E9SGINSIN MSM9563 User s Manual First Edition January 1999 Second Edition December 1999 1999 Oki Electric Industry Co Ltd FEUL9563 02
62. t piNTCLR Figure 4 7 Interrupt CLR Timing O LR signal Y tweLR Figure 4 8 Clear pulse width MSM9563 User s Manual Chapter 4 ELECTRICAL CHARACTERISTICS 4 8 Chapter 5 CONTROL REGISTERS 5 CONTROL REGISTERS 5 1 OPERATING MODE REGISTERS MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 1 1 Mode setting of main channel and subchannel Table 5 1 1 Main channel mode and subchannel mode Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO W MOD MOD 0x04 SUB MAIN Initial value 0 1 There are two modes available namely the main channel mode in which connection is made to the broadcasting station of the same channel and reception is made in units of a frame the conventional method and the subchannel mode in which the tuner is switched intermittently to other channels and reception is made in units of several packets of information The channel switching mode setting for simultaneously receiving subchannels by switching to high speed subchannel during main channel reception is shown in the following table Channel switching mode setting for simultaneous reception of main channel and subchannels Mode walle Description DB4 DBO MOD_MAIN SUB 1 1 The mode used for subchannel timing extraction at the time of initial setting MOD_MAIN 0 1 Main channel reception mode MOD_SUB 1 0 Subch
63. te number 2 2 5 25 0 R W 0x07 0x08 Clock Fixed phase adjustment 0000000 10000000 R nterrupt timing _SUB packet number 5 25 00000000 R W 0x08 0x09 regeneration Bit gate 0000 11110000 R nterrupt timing _SUB frame interval 5 26 000000 R W 0x09 0x0A Integration constant 1 4 0010 11110110 R Clock timing adjustment subchannel 5 27 0000 W 0x0A 0x0B Integration constant 2 4 0010 11110110 R Clock Fixed phase adjustment 5 28 0000000 W 0x0B 0x0C Integration constant 3 4 011000 11010000 regeneration Integration constant before sysnchronization 5 28 0010 0110 W 0x0C 0x0D Integration constant 4 4 011000 11010000 R integration constant after synchronization 5 28 011000 010000 W 0x0D Phase correction step 0101 11111111 Phase correction step 5 29 001 001 011 011 W 0x10 Block Allowable number of BIC errors 0110 11111001 W Block Allowable number of BIC errors 5 30 01 0110 00 1001 W 0x10 Ox11 synchronizaiton Number of block synchronization backward protection steps 01 11111101 W synchronization Number of block synchronization backward protection steps 5 31 00 01 01 10 0 11 0x12 Number of block synchronization forward protection steps 1000 11111111 W Number of clock synchronization forward protection steps 5 32 10001000 01001111 R W 0x12 0x13 Block synchronization monitor 0000
64. tion correction correction Status Status parity parity parity parity parity parity Reception Reception Vertical Vertical Vertical Vertical Vertical Vertical 271 tatus 0 tatus 1 correction correction correction correction correction correction status status parity parity parity parity parity parity Vertical Vertical 272 correction correction result result 33 The frame memory data configuration is shown in Table 5 3 6 1 The data consists of 190 data packets 82 parity packets and one vertical correction result packet Normally the second horizontal error correction of the parity packets 190 to 271 are omitted To read packets including the parity packets after the second horizontal error correction it is necessary to set and carry out the error correction separately for testing purposes The leading two bytes of each packet indicate the reception status The details of the reception status are shown in Table 5 3 6 2 Table 5 3 6 2 Reception status after the second horizontal error correction DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Reception status 0 CRCO ERCO RECCRC FSYNC BSYNC BICDET BIC1 BICO Reception status 1 VICSRDY PARITY INTO CRC2 ERC2 FNCHG FRNO1 FRNOO Reception status 0 The reception status 0 is equal to the contents of BYTEO received after the first horizontal error correction 1 DB7 CRCO 1 Indicates that there is an error in the C
65. tting subchannel Table 5 4 6 Interrupt timing setting SUB frame interval Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R FNCK3 FNCK2 FNCK1 FNCKO FNCK8 _SUB _SUB _SUB _SUB _SUB W FNCK3 FNCK2 FNCK1 FNCKO FNCK8 0x09 Note 1 _SUB _SUB _SUB _SUB _SUB W INTALLFRCKINT FNCK3INT FNCK2INT FNCK1 INT FNCKOINT FNCK8 Note 2 _SUB _SUB _SUB _SUB _SUB _SUB W FNCK3IMAX FNCK2MAX FNCK1MAX Note 3 _SUB _SUB _SUB _SUB Initial value m re 0 0 0 0 0 0 Note 1 The setting SETTIMCK SUB 05 DB4 1 R_05 DB5 0 should have been made in the register 0x05 Note 2 The setting SETINTCK SUB 05 DB4 0 R_05 DB5 1 should have been made the register 0x05 Note 3 The setting SETMAX_SUB 05 DB4 1 05 DB5 0 should have been made in the register 0x05 Read FNCKO to FNCK3 FNCK3 MSB to FNCKO LSB indicate the frame number being counted Write FRCKO_SUB to FRCK3_SUB This is the register for specifying the initial value of the frame number in the 4 bit frame number counter of the subchannel The 4 bit frame number counter is one for generating subchannel timing interrupts at intervals of 0 to 15 frames The frame interval is specified by MAXFNCKO_SUB to MAXFNCK3_SUB MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Write SUB to SUB This is the register for specifying the subchannel interrupt
66. ue specified by LBACKO and LBACK1 0 The next byte number is reset to 0 when the current byte number becomes equal to the value specified by LBACKO and LBACK1 5 18 5 3 8 Receive frame memory pointer after the second horizontal error correction Table 5 3 8 1 Frame memory address 1 3 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R W EXT EXT EXT EXT EXT EXT 0x3B BYTES BYTE4 BYTES BYTE2 BYTE BYTEO Initial value _ 0 0 0 0 0 0 Table 5 3 8 2 Frame memory address 2 3 Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R EXT EXT EXT EXT EXT EXT EXT EXT Note 1 PCT7 PCT6 PCT5 PCT4 PCT3 PCT2 PCT1 PCTO R L1BF L1BF L1BF L1BF L1BF L1BF L1BF L1BF 0x3C Note 2 PCT7 PCT6 PCT5 PCT4 PCT2 W EXT EXT EXT EXT EXT EXT EXT EXT PCT7 PCT6 PCT5 PCT4 PCT3 PCT2 PCT1 PCTO Initial value 0 0 0 0 0 0 0 0 Note 1 The setting PCTL1BL2 0 should have been made in the register 0x39 Note 2 Thesetting PCTL1BL2 1 should have been made in the register 0x39 used in the page mode Table 5 3 8 3 Frame memory address 3 3 Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R MEMSTAT E EXT Note 1 PCT8 R L1BF 0x3D Note 2 PCT8 W x m m EXT PCT8 Initial value 0 Note 1 The setting PCTL1BL2
67. y of the clock that is output to the XOUT pin as follows when XOUTC 0 DB6 DB5 DB4 XOUT Pin output clock frequency 0 0 0 8 192 MHz 0 0 1 4 096 MHz 0 1 0 2 048 MHz 0 1 1 1 024 MHz 1 0 0 0 512 MHz 1 0 1 0 256 MHz 1 1 0 0 128 MHz 1 1 1 0 064 MHz DB2 External clock input This controls the operation of the crystal oscillator circuit as follows when the XOUTC pin is 1 Also in this case the XOUT output pin is set to the L level 0 The operation of the crystal oscillator circuit is stopped 1 The crystal oscillator circuit is acrivated When the XOUTC pin is 0 the crystal oscillator circuit will be operating continuously and the XOUT pin also will be outputting the clock signal continuously 5 41 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 3 DB1 Digital section power down 0 The power is down and the internal clock stops at the H level 1 The power is turned on and the clock for operating the digital section starts from the H level 4 DBO Analog section power down 0 Power down operation stops 1 Power on several milliseconds will be required for the circuit operation to become stable after the power is turned on 5 12 TEST CONTROL REGISTERS 5 12 1 Test control 0 Table 5 12 1 Test control 0 Address R W DB7 DB6 085 DB2 _ W B7 B B 0x32 5 Initial value 0 0 0
68. ynchro nization of the subchannel 4 DB1 TIMINTEN MAIN 1 Activates the timing interrupt of the main channel 0 Disables the timing interrupt operation of the main channel Set the interrupt timing after setting this bit to O and set this bit to 1 after the interrupt timing setting is completed 5 DBO SETINTCK MAIN 1 Makes it possible to write the main channel interrupt timing values in the registers 0x16 0x17 Ox1D and Ox1E 0 It is not possible to write the main channel interrupt timing values in the registers 5 22 MSM9563 User s Manual Chapter 5 CONTROL REGISTERS 5 4 2 Interrupt byte number specification main channel Table 5 4 2 1 Interrupt timing MAIN byte number 1 2 Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R BCK7 BCK6 BCK5 BCK4 BCK3 BCK2 BCK1 BCKO 0x16 W INTBCK7 INTBCK6 INTBCK5 INTBCK4 INTBCK3 Note 1 Initial value 0 0 0 0 0 0 0 0 Note 1 The setting SETINTCK 1 should have been made in the register 0x05 Table 5 4 2 2 Interrupt timing MAIN byte number 2 2 Address R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO R BCK8 0x17 W s INTBCK8 Note 1 Initial value 0 Note 1 The setting SETINTCK 1 should have been made in the register 0x05 Read BCK8 MSB to BCKO LSB indicate the bit numbers of the pa

MSM9563 IC for FM Multiplex Data Demodulation User's Manual

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