A5191HRTNGEVB Manual A5191HRTNGEVB_MANUAL
Contents
1. 1 Il It 1 w ba 0 1 1 ND MAN serene UU ee ee 1 a 1 0 i CR i ESO i ene E ARO o 15dB ceo peo i yn ll e ti Ad 3 a fr de e al da B 129 ll e id di aa x gn do w pd 200 lu Pee Pei ym a le a ng ii del HRS re y 40 eee 0 at iti WW R T UH i ti i i NU Pa torri i VO host i i i bo se I OU i i E4 A i b tb 1 bo iene l ta hb pb O O men a 4 pi 06 6 88 1 1 a a 1 1 ro as Itri 8 E tti 20dB ieee i ee no a MH 1 TE a tti 20 CUO0D lt pasen separano e ls A pepe A A pia o A Tete Hed cau A dd yn gp ag o ymau gu us nn dl anapak ywi lou Apts adio dedi ds A A Ub ess sess pae ymn de p eee i 1 1 Ce i tti 1 ii 0 4 0 tti bob 1 O N Eb bb et It Vir DHUH PRE EA A I IR A PI SA FYTH NI Ep HU 0 1 D 9 TA 1 It Lor bL 1 Lot tti 1 i 1 1 Seg 1112. 2 Vasa Rs 20mA R R When the DAC is not a switching topology we can now choose Ry and C4 We have 300 Y R 1mA RZ Where z lsc Rl In practice Cy is chosen sufficiently small so that Z Ri For a PWM or sigma delta output DAC the circuit gets a bit more complicated as we need to filter away high frequency DAC components but leave HART signals intact If the bandwidth of the DAC is larger than 2 2 kHz adding C3 introduces a low pass filter to the loop that will remove most of the switching noise 1 2 om fas Ro http onsemi com 15 AND9012 D Where Rp is the parallel circuit of R4 Rs and Ry If the bandwidth of the DAC is close to the HART freguencies an alternate high freguency feedback path must be introduced so that HART signals are not removed by the low pass filter of the DAC The exact calculation of component values in this case is more complicated However it is based on a similar principle but now with two summing junctions for low frequency and high frequency signals separated Resistor R3 may be needed to compensate for amplifier bias current It is chosen so that its resistance is similar to resistance seen on the positive terminal Depending on the amplifier used it may also be required to provide a compensation capacitance C4 Vad CJ Loop KVDE20110406 7 Figure 21 Sample Slave Implementation Master Implementation An example of a possible master implementation is shown in Figure 2
3. RS A Meee ee ee 240 270 100dB wwe ee ee te ee AS AAA et aaa a kaa ka ats CT R E A A EA E bet ee be te ee te ete ees 300 120dB 330 140dB ailW 2 2 onto nto te et pt te ee en aba LOL dd a d INGRAD te ee ee ee ee te et e 360 160dB 390 10008 HF ERREI O naan 420 1Hz 10Hz 100Hz 1KHz 10KHz 100KHz 1MHz V n006 A0dB gt Ti AAA AAA AAA 7 390 Te ee ria ct 2 DT oL ob LL NU a od tt 11 1 i Tins DD 1 UM 20dB 4 lt ay St nas apie CYD ccs shah New e aR sasso a ED FD WT YN ED DID WD dei ii UE eee 120 iag A LLAU Si 4 TR A A A A eee ES OS O a pde 180 Ra I Fd 4 i A e e IIN UU e A UN GU a abahahahahahaahi O NG Jatah e e e e E A ded e 210 a FL A RE PO SR E E kaka bak kaka bak ii TT E IS pi 240 ds porra oi TAg 80dB iii tn fot lolita eta Y Giai Mil ni dio ee pilu hadas id Td ds ci Se es Pe gne Us E ELLE ELE CERERE Se rdhah adha es ymn TP y gt PESA en gt e badi 270 iti 4 ag ty TH TW a 100dB nn n nn n dro de de J wh e Ua de d A E ba o ala e ts do akak dial fala ir CN UN J k e ooo ooo dro deso h bh kh d ro o o ooo bana o GI 300 120dB cs ct EN am yd ea y saeba dhak A y ss Cl ay i eta laaah d dhan adhakah T a mies cio eos aka a de ii
4. and 3 for V1 resp V2 we find y 1 4 sh C3 y V 4 _ SR4C4 en SR V AAA Fae For Eguation 2 we find F 1 1 K Vs sc sC Re z Fs Y sc a eq 6 http onsemi com 17 AND9012 D Or with the substitution a 1 n 1 R R R Equation 6 simplifies to a K Ra Ra Substituting V1 and V2 in Equation 7 using Equations 4 and 5 and simplifying we find the transfer function ig uao o uM i Vn s a s a 5 a Where 1 1 1 1 1 ao RG RG RG sdh Oz E gt RRGC RRGC RRGC 0 RR RRC GC Adding the compensation capacitor on the operational amplifier results in the following transformation on the transfer function 1tsR C 7 rs R C Where Ry Ri Rs Since K is present in the numerator of the transfer function the zero of this factor will be present in the transformed transfer function The denominator of the transformed transfer function is a forth order function with the following coefficients The transfer function now has the following form Kxs 1 b 8 His aa aL 1 5 st b 53 b 52 b ss by Where b Ry Ca ia MW a 2 EA RG RG RG RGA C CASUAL RG 27 AGRC RaCaRaCa RaCoRsCi RGRG RaCa r 1 n a PI zi 0 KE 1 RiR3C Cs RAGO RARO C O RI RR Ro RE a gt 1 A 1 z a K R R tt RRRAGG Erbe RR RGGC a a t RRR GOGG RRRGGCG b http onsemi com 18 AND9012 D a
5. and VDD pin signals during startup are shown in Figure 5 The measured start up delay is 2 6 ms O 4 21ms 2 8S4V i O 1 58ms 2 52 Y A2 63ms A320mV A AS O 100v 62 100v amp Ji 20005 RRS ud value Mean Min Max Std Dev W Y0 00000 5 1M points JU Peak Peak 3 24 Y 3 24 3 24 3 24 0 00 23 Feb T 11 04 08 Figure 5 Power and RESETB Waveform During Startup Showing 2 63 ms Startup Delay C1 C2 and C6 are 100 nF ceramic decoupling capacitors located directly adjacent to each power pin For analog power pins an additional large value ceramic capacitor may be needed in addition to the 100 nF decoupling capacitor when the application Is intended for high noise environments For loop powered devices additional decoupling with a large value capacitor is advised to prevent digital noise from being transmitted on the current loop The ferrite beads FB1 FB2 and FB3 in series with power supply lines help to reduce EMI http onsemi com 5 AND9012 D Reference voltages and comparator bias A5191HRT needs an external analog reference voltage for the receiver or demodulator RX comparator and carrier detect CD The AREF reference voltage sets the trip point of the demodulation operational amplifier of the 5191HRT The AREF reference voltage is also used in setting the DC operating point of the received signal after 1t has passed through the band pass receive filter The ideal value for the AREF reference volt
6. and output introduces another high frequency pole and zero pair The zero of which can easily be determined to be 1 2a C R1 R2 Determining the exact location of the extra pole requires extra calculation Indeed the location of the other poles will also be shifted by this extra circuit element Introducing R44 does not introduce another pole or zero but changes the denominator of the transfer function and thus the location of the poles The final transfer function of the first filter stage is thus a fourth order filter of the form Gesi l 4bh s 54 _ bas b g b 5 Bo 109 kHz His The poles of this transfer function are located at P1 P2 195 Hz D3 1 220 KHz Pa 22 kHz The input impedance of this filter stage is higher than 89 kQ at frequencies below 50 kHz http onsemi com 13 AND9012 D 010E 08 LLL e AAA 001E 08 1 000E 04 100E 04 Imput Impedance Ohm 010E 04 001E 00 010E 00 100E 00 1 000E 00 001E 04 010E 04 100E 04 Frequency Hz Figure 18 Input Impedance of the First Filter Stage Second Stage The second stage of the receive filter is a simple band pass filter consisting of cascaded passive low and high pass filter AREF Ri C2 Stage 1 1 Vout C 4 KVDE20110406 4 Figure 19 Second Filter Stage Schematic Again the AREF voltage can be considered ground for AC frequencies and serves only to bias the output of the
7. com 6 AND9012 D witnessed by utilizing an external oscillator is 70 100 uA less However care must be taken that this external signal has the required accuracy 1 Duty cycle of the clock signal is specified between 40 and 60 No errors were observed during testing in operation between 20 and 80 duty cycle However operation on such very small or very large duty cycle is not recommended due to the possibility of timing errors that may occur under specific circumstances including but not limited to temperature variations P o 4 Os EXT CLOCK e ere o se O al PC20110513 3 a Resonator Option b External Clock Option Figure 7 Clock Generation Circuit Microcontroller Interface IDC 1 Vcc PC201105134 KVDE20110406 8 Figure 8 Microcontroller Interface Table 5 MICROCONTROLLER INTERFACE Type Description Reset signal from the voltage supervisor open drain with pull up Output Carrier Detect Receive from microcontroller Output Transmit towards microcontroller Request to send 3 V nominal http onsemi com 7 AND9012 D The interface towards a microcontroller is provided in IDC1 This interface can also be used to supply power to the module The nominal supply voltage for the module is 3 V For more information see the section on power supply and references The RESETB line to the modem is an open drain signal A pull up resistor of 2
8. 00 KQ is provided on the board and should not be duplicated on the microcontroller side The reset signal is generated on the board and could be used as reset signal for other IC such as the microcontroller The CD signal rises when a HART signal of ca 100 mVpp is detected on the current loop See the section on reference voltages for more information on these threshold level settings When no signal or a signal of limited amplitude is present the CD line is pulled down to 0 V The RxD TxD and RTSB signals implement a standard UART interface at 1200 baud with start bit 8 data bits parity bit and stop bit 11 bit frame The RTSB signal disconnects the transmitter circuit when pulled high and should be held low before any data is transmitted Data frames are not buffered by the modem Instead data is transmitted bit by bit Care should be taken to avoid clock skew in the receiving UART If the same time base is used for both the modem and the UART a 1 accurate time base may not be sufficient The problem is a combination of receive data jitter and clock skew between transmitting and receiving HART devices If the transmit time base is at 9990 of nominal and the receive time base in another device is at 101 of nominal the receive data at the receiving UART will be skewed by roughly 21 of one bit time at the end of each 11 bit byte This is shown in Figure 9 The skew time is measured from the initial falling edge of the start bit to the center o
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10. 191HRTNGEVB The values are listed in Table 6 and the filter schematic is displayed in Figure 12 For cost purposes this filter can be implemented using E12 value resistors with minimal changes to the filter characteristic This implementation will have a slightly reduced gain in the pass band C7 Rg Rio RXAFI RxAF PC20101124 1 O HART IN 300 pF O 0 Carrier Comp 1 235 Vpc AREF 80 mV DEMODULATOR Figure 12 Receive Filter Table 6 RECEIVE FILTER COMPONENT VALUES Value E12 Reference Value E96 Low cost ai as dia as nao am http onsemi com 10 AND9012 D V n006 V vout 1Hz 10Hz 100Hz 1KHz 10KHz 100KHz 1MHz Figure 13 Filter Characteristic First Stage black Total Blue In Figure 13 the simulated characteristic of the entire filter is shown in both variations for the first stage black and total filter blue The normal and low cost variations are superimposed showing that the variations are minimal However when the tolerance on the values is also loosened a bigger variation in the characteristic is observed Figures 14a and 14b show a monte carlo analysis for resistors of 1 and 1090 It is advised to use resistors of at least 1 accuracy v n006 Tr LL 90 E E A A o O nn A A A A A A A A didnt 120 a dl e cs ra OLER Ei datado iat dl bea bak fa 150 ee ee eee ee A PERE ee eee ee A 180 SN ben do eb eb eb deb ence cere eee 210 ee ee ee eee eee eet eee a eee O
11. 2 To use this schematic the coupling capacitor C4 on the A5191HRTNGEVB will need to be replaced by a O Q resistor or new biasing must be provided The current loop master has a sense resistor over which the current flowing through the loop can be measured The value of this resistor varies depending on the sensitivity required and range of the ADC A HART Master can have a sense resistor ranging from 230 Q to 600 Q Increasing the sense resistor will result in higher amplitude HART signal received but will also reduce the voltage available on the slave side Furthermore if you wish to sense the analog transmitted signal the MSB of your DAC may limit the resistor size If this limitation is too stringent the sense resistor can be split in two resistors as shown in the figure effectively creating a resistor divider To transmit a HART signal the TxA signal will need to be amplified as the A5191HRT transmit circuit can only drive high impedance circuits gt 30 kQ An additional operational amplifier is required Depending on the sense resistor used some gain or attenuation may be required to get a 1 mA peak to peak HART output signal This can be accomplished by the resistors R3 and R4 For a typical sense resistor of 500 Q a unity gain suffices and a unity gain operational amplifier configuration can be used instead The amplifier however has a low impedance output which cannot be paralleled with the sense resistor as this would cause problems
12. AND9012 D A5191HRTNGEVB User Manual Prepared by Koenraad Van den Eeckhout ON Semiconductor Introduction The A5191HRTNGEVB evaluation board includes all external components needed for operating the A5191HRT IC and demonstrates the small PCB surface area such an implementation requires The EVB allows easy design of HART implementations using A5191 HRT Overview The A5191HRT is a single chip CMOS modem for use in highway addressable remote transducer HART field instruments and masters The modem and a few external passive components provide all of the functions needed to satisfy HART physical layer requirements including modulation demodulation receive filtering carrier detect and transmit signal shaping The A5191HRT uses phase continuous frequency shift keying FSK at 1200 bits per second To conserve power the receive circuits are disabled during transmit operations and vice versa This provides the half duplex operation used in HART communications Features e Single chip Half duplex 1200 Bits per Second FSK Modem ON Semiconductor http onsemi com APPLICATION NOTE Bell 202 Shift Frequencies of 1200 Hz and 2200 Hz 3 0 V 5 5 V Power Supply Transmit signal Wave Shaping Receive Band pass Filter Low Power Optimal for Intrinsically Safe Applications Compatible with 3 3 V or 5 V microcontroller Internal Oscillator Requires 460 8 kHz Crystal or Ceramic Resonator e Meets HART Physical Layer
13. EF reference voltage on the A5191HRTNGEVB is generated by a resistor division of the AREF reference This will create an extra load on the low pass filter of AREF However the drop on the resistor of the low pass can be considered negligible An external resistor is required to set the bias current The voltage over the bias resistor is regulated to AREF so that the resistor determines a bias current This bias current controls the operating parameters of the internal operational amplifiers and comparators and should be set to approximately 2 5 uA A bias resistor of 499 KQ is used on the A5191HRTNGEVB For low cost solutions a 470 k9 is acceptable with minimal effect on operation Table 4 REFERENCE VOLTAGES PC20110513 5 CBIAS Figure 6 Reference Voltages Schematic Clock Generation A5191HRT is operated on a 460 8 kHz clock signal The AS191HRINGEVB has two options for providing this clock signal The first method is by using a ceramic resonator or a crystal The standard populated option is a Murata CSB460J ceramic resonator loaded with two 220 pF capacitors Alternatively a clock signal can be provided externally when R3 is removed and C3 is replaced by a resistor of O 2 This signal can be provided by a microcontroller or any other external oscillator circuit The module uses less power when clock signal is applied externally as this allows the modem to shut down the oscillator circuit A typical current consumption http onsemi
14. Requirements e Industrial Temperature Range of 40 C to 85 C Available in 28 pin PLCC 32 pin OFN and 32 pin LOFP Packages Applications e HART multiplexers e HART Modem Interfaces e 4 20 mA Loop Powered Transmitters Figure 1 The A5191HRTNGEVB Evaluation Board O Semiconductor Components Industries LLC 2011 May 2011 Rev 0 Publication Order Number AND9012 D AND9012 D ELECTRICAL CHARACTERISTICS Table 1 ELECTRICAL CHARACTERISTICS OF THE A5191HRTNGEVB BOARD Vale DC aw SEE CURRENT CONSUMPTION oo 10000 000 TTT Tw o I SS w o wmeme ___5_ _ a fa eo E N wl w TRANSMITTED FREQUENCY LEVELS REFERENCE VOLTAGES A5191HRT DESCRIPTION The A5191HRT modem is a single chip CMOS modem for use in HART field instruments and masters It includes on chip oscillator and a modulator and demodulator module communicating with a UART without internal buffer The A5191HRT requires some external filter components and a 460 8 kHz clock source This clock source can either be the interface oscillator by using a crystal or ceramic resonator or an external clock signal When the device is transmitting data the receive module is shut down and vice versa to conserve power With simple power saving maneuvers the IC can be made to operate with a current consumption of as little as 250 uA For more information related to this subject a Design Note A5191HRT Design for Low Power Environme
15. age depends on the voltage supply and is chosen roughly half way the operating range of the operational amplifiers This ensures the range of the operational amplifier is maximized For operation at 3 V a 1 24 V reference voltage is recommended For operation at 5 V a 2 5 V reference voltage is recommended For A5191HRTNGEVB the TLV431 shunt regulator is used with an internal reference of 1 24 V This reference is compared against the output voltage and the shunt transistor base is adjusted until it sinks enough current to drop the output to 1 24 V A simple low pass filter formed by R12 and C11 is added to increase reference stability A slight voltage drop is observed over this filter caused by loading of the reference voltage However the voltage drop and the influence on the operation of the IC is minimal Measurements show a voltage drop of 22 mV over R12 indicating a current of 22 uA Of this current ca 5 uA is consumed by the CDREF resistor division The rest ca 17 uA is used internally by the IC through the AREF pin Current consumption through the CDREF pin is negligible The CDREF reference voltage sets the threshold for the carrier detect comparator As the received signal is biased at AREF the difference between CDREF and AREF will determine the minimum amplitude needed for the carrier detect comparator to flip A AREF CDREF of 80 mV corresponds to signal of approximately 100 mV peak to peak at the input of the receive filter The CDR
16. ation of Different Sections Power Supply and References Power Supply PC20110513 2 Figure 4 Supply Voltage and Power on Reset The A5191HRTNGEVB is designed for a nominal voltage of 3 V However AS191HRT can be operated up to 6 V For optimal functioning of the board the values of several resistors should be changed for operation at voltages higher than 3 V See the sections on reference voltages and bias for more information on this Current consumption of the module is very limited making it ideal to be battery or loop powered Measurements of the power consumption of the module are listed in Table 3 http onsemi com 4 AND9012 D Table 3 MODULE CURRENT CONSUMPTION o wen na INN EE ECN oo Yoo Svevi oo Vo Sven a AN oo 00400 e 00 E Os Woo SV mese os an The module will use less power when clock signal is applied externally as this allows the modem to shut down the oscillator circuit As is to be expected a higher supply voltage increases current consumption It is advised to use a voltage supervisor such as CAT808 to prevent the modem to begin operation when the supply voltage is not yet reliable This will guarantee correct operation of the digital circuitry The voltage supervisor will keep the RESETB pin low until its threshold value is reached 2 7 V on the AS191HRTNGEVB This ensures that some time has passed after the supply voltage reaches the turn on voltage level of 2 5 V The RESETB
17. ban Na ERA ES Adding a series resistor to the capacitor results in the following transformation Es C gt 3 14s RC Since C3 is not present in the numerator or in the highest order coefficient no extra poles or zeros will be introduced by this transformation The form of the transfer function hence remains the same The transformed coefficients are TT A Gret Pa Rs Eta RaC4 RG Rs R7 C Cy Cs 7 RaR3 R R C Cy 1 1 1 1 1 1 1 1 02 RRGC R ERRE o a Ri R3 R G Hla E E RR ROC Ra Ro RaR4Ca WC Cad RAR RAGANG Co Eo Ra 1 CCE RaRa RRR CGG 1 b 1 2 1 ua Tn nA A ee Re 1 BR FRORG CAG CJ VW RAR RR CGC a P 1 a R R3 R3 RaC3Ca Cy Co RiRo R3 Ry C CLC CE 2062 RRa R3 Ry RsCyCr Cg Cy http onsemi com 19 AND9012 D EVALUATION BOARD Layout e or e Bu dom ES Me cn g E E e MM MM ee DO mm 6o eu B HE HE Siew mm mum 6 WE HE UN kab an mM eo o m BE ETA mn 0 9 o T Figure 23 Top Layer Layout Figure 24 Bottom Layer Layout ON Semiconductor and D are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liabi
18. ee A A a a aa A ada Mr aia ws es e pareen en DU a u r dad 1990 y 330 i a id o i ra E 140dB lt 7 2 4 ddd a i ddd drdd drdd ddu pd dodet 360 DELI wrtn 1 eet Eee si 160dB Ss la a is lea kb o Ua ce il abaan a a ee ds ga ee mus y prp ee ae eU Tarro door orora r anno a dn gynt gl PE Ties re NASA me y ee y 390 1 eie eka a IS 10008 HF rau 11 1 1 420 1Hz 10Hz 100Hz 1KHz 10KHz 100KHz 1MHz Figure 14 Monte Carlo Analysis of the First Filter Stage for 10 above and 1 below Accuracy http onsemi com 11 AND9012 D In Figure 15 the measured filter characteristic of both variations are shown next to a simulated result These characteristics are only of the first stage of the filter as the output of the second stage is not accessible We notice an additional pole showing up at high frequencies This only improves the filter by rejecting high frequency noise and is too high in frequency to have an influence on the phase of HART signals Figure 16 shows the group delay of the total filter It is important that the difference in group delay between the mark and space is minimal so that the output of the filter still has coherence between both signals The plot of Figure 16 shows that the difference is indeed minimal So ere et r r r rrr BI WU yn i ehe clan a clean dodo dab damm ween eek ewan chee ab ww bh a ceu Jn eau Dew ewe dew ew baw da eb ab ok Je henne dnd
19. f the 11th bit cell This 2190 skew by itself is a relatively good result However there is another error source for bit boundary jitter The Phase Lock Loop demodulator in the A5191HRT produces jitter in the receive data that can be as large as 1290 of a bit time Therefore a bit boundary can be shifted by as much as 2490 of a bit time relative to its ideal location based on the start bit transition The start bit transition and a later transition can be shifted in opposite directions for a total of 2490 The clock skew and jitter added together is 45 which is the amount that a bit boundary could be shifted from its expected position UARTs that sample at mid bit will not be affected However there are UARTS that take multiple samples during each bit to try to improve on error performance These UARTS may not be satisfactory depending on how close the samples are to each other and how samples are interpreted A UART that takes a majority vote of three samples is acceptable BIT t Transmitter teit ter 99 nominal CLK 2 Receiver 45 tar 1200 21 tar 12007 Wm TH AU WWW mmm WWT 1 WW OWN WWT YTT 977777 WT PC20101209 1 UART mid bit sample moment 12 jitter y Figure 9 Clock Skew Even if your own time base is perfect you still must plan on a possible 35 shift in a bit boundary since you don t have control ove
20. filter around AREF It can be shown that this stage has the following transfer function s H2 C2 bacini 1 s R1C1 F1C2 R2C2 s7 RIRAC1 C2 This stage has two poles that can easily be calculated p1 36 Hz p2 3316 Hz http onsemi com 14 AND9012 D 0dB bd 100 ara wre IC o ss 0 O OO ORDNI LEO ER ee ae bakah Lah Lli torres LG i mw i WN i ANAN i EE 5dB 1 et IL 1 1 LALA 1 WM 1 i LLL i EN i LLL 80 cun V wv wr tr ge rb SS al e mM 6 NSA era kak Taha feat da lt lt 4b AN Frech el ft a poer wrest Ss 8 a8 Mdn CM aka ESTO 8k ce 8 1 y 1 1 i ti iti no ti UU tti mee 1 1 1 I ti 1 ho 1 et bh Vit 1 on 508 04 1 1 1 1 P eD 1 1 ro as 1 A hid ene tti 1 ii ti 7 8 1 1 TAN DES 1 i 1 1 od i GU 8 8 o 10dB era g money ep y y n gau ae ch A cm a aw 2 s gt ym ee ye da 2 yn a m gt gt e kadhak Am e e n a ynn Dadi Ao di aha dl Mk y 92 PAS 60 vt 1 1 E 3 0 Vi tt Vir Vr i 1 E I 11
21. hbedehbeu Joe ehe nn Gele de i aM te DO Po i I Jer 1 1 Las qn beni 4 LL Loose i 8 RR ween FAN o oo Roco A AS yd 1 o e AA i i NE aas in lasa mah a CI 66 TA meee JU Wa A a E a a a eb a go E dl pa CESTI 1Hz 10Hz 100Hz 1KHz 10KHz 100KHz 1MHz Figure 15 Measured and Simulated Filter Characteristic of the First Filter Stage 2 iii TIRI i e ni 1 5 IA E y O O Ta L m 1 dn En 0 5 el eld E E pai Ka NE aki 001E 00 010E 00 100E 00 1 000E 00 DOLE 04 DLOE 04 100E 04 Frequency Hz Figure 16 Group Delay of the Total Filter http onsemi com 12 AND9012 D First Stage The first stage of the filter is implemented as a modified third order high pass active filter Consider the circuit shown in Figure 17 This resembles the implemented filter except for the coupling capacitor on the operational amplifier and the removal of R14 The filter is a variation on the Sallen Key topology with three poles The AREF voltage serves here as a biasing voltage but can for ac frequencies be regarded as ground For a complete analysis of this filter type see the Appendix on Page 17 AREF Vout KVDE20110406 3 Figure 17 Simplified First Filter Stage Schematic The transfer function of this type of filter is Kas His TAI JU S a 5 a 5 Up Taking into account the compensation capacitance present on the operational amplifier between input
22. is circuit let us first look at an example where the DAC is not of a switching topology In this case R gt and R3 can be O Q and Cy C3 and Cs can be left out As one end of Re is tied to local ground it can easily be seen that the voltage at the negative loop terminal is negative with respect to the local ground Resistors R4 and Rs are then chosen so that in steady state their common terminal is a virtual ground point in the absence of HART signals since the negative terminal of the amplifier is also connected to ground A similar principle applies when HART signals are applied So both amplifier inputs are regulated to ground A compensation capacitor C4 may be required depending on the operational amplifier used To avoid offset generated by bias current in the operational amp R3 should be dimensioned to approach the impedance seen by the positive terminal The amplifier will then determine the current flowing through the loop by changing the base of a transistor in emitter feedback configuration The value for R7 is determined by the output range Vo max of the amplifier used Momo Ver R7 max a mi It is often recommended to take a value as large as possible so that noise effects are minimal Typically the value of Re is chosen equal to R7 The voltage over Re and R7 combined should however be less than 12 V when the current setting 1s 20 mA Next the values of R4 and R5 are chosen depending on the most significant bit of the DAC
23. lity arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirma
24. nb 6 0 1 i tt Vit 1 i t Ia re O bh Vir ene 1 ta hL ot Sey I ti ieee 8 0 A Oy TE 8 8 8 Vr Lo osa 1 B6 A ge Vv ti I 11 et mM vir Vr 45dB scanio Case adorada i deb AA A ka ab aa Kaka AA ad Fe m en Bad AAA PA kie A men mae edd isa PE as bw GB ace es es a we Gere ans Kb Bad 80 eee 1 1 1 ieee 1 iti dirti 1 eL eee tti Boi RAI MW Vir mn HN 1 0 Ti a E A A 50dB TH 100 1Hz 10Hz 100Hz 1KHz 10KHz 100KHz 1MHz Figure 20 Characteristic of the Second Stage of the Filter APPLICATION IDEAS The A5191HRT takes care of the HART modulation This HART signal must then be superimposed on a 4 20mA current loop Below are some possible implementations of both a master and slave transmitter Slave implementation A simple slave implementation is shown in Figure 21 The analog loop current is set by a DAC from the microcontroller while HART signals are added in from the A5191HRT The DAC can be PWM or sigma delta topology To explain the operation of th
25. nts will be released shortly TEST AND MEASUREMENT TOOLS Listed below are the tools used to acquire the values presented in this application note Oscilloscope Tektronix DPO4034 350 MHz Signal Generator Agilent 33120A Network Analyzer AP Instruments 300 http onsemi com 2 AND9012 D A5191HRTNGEVB DESCRIPTION Schematic Diagram BOM List Vcc FB2 s AUU ih Cy Co Ce Vcc Us Ry DYDD DVERI SERI RESET pate O Vcc i 2 R2 i i R23 Voc IDC A5191HRT J2 ov d o pa i 1 Y i A n 1 3 4 5 11 28 6 20 12 19 CONNECTOR u I F a ii Er OA R3 j Y i R7 EXT C5 C3 PC20110513 1 CLOCK Figure 2 Schematic of A5191HRTNEVB Table 2 A5191HRTNEVB BILL OF MATERIALS aa T A TANANAN HR 2 0 0 es n I 00000 DE I CI I I O TL NANA I gt pere 0 0 eee ST E A ts laira 000 TLV431ASNT1G 460 8 kHz http onsemi com 3 AND9012 D General Overview The A5191HRTNGEVB evaluation board demonstrates the external components required for the operation of the IC We will cover the different sections below as well as possible alternatives A drawing of the board where the different sections are indicated is shown below J1 A5191 HART MODEM www ONSEMI com 5 esonator J1 Optional Loop Connector IDC1 uC I F Voltage Supervisor Barale Filter IDC2 Loop I F J2 External Reference Clock Voltage IDC3 Test I F Figure 3 Board Drawing With Indic
26. r time bases in other HART devices Transmitter The TxA modem pin is decoupled through a 100 nF capacitor to pin 7 of IDC2 For certain applications it might be required to remove this capacitor and replace it by a 0 Q resistor The output on this pin is a 500 mV signal trapezoid waveform shown in Figures 10 and 11 This pin can only drive impedances higher than 30 KQ and as a consequence may need to be amplified to drive low impedances For a given implementation of a master or slave it may be required to remove C4 and replace it with a O Q resistor to allow the decoupling to occur elsewhere in the master implementation The nominal freguency of the output is 1196 9 Hz for mark and 2194 3 Hz for space These freguencies are dependent on the accuracy of the A5191 clock http onsemi com 8 AND9012 D O 4214s 78 134UV i o 418us 750 0uY AS39ps A828 1uY omy a 200us 500MS s b 7 000v value Mean Min Max Std Dev tv0 00000s 1M points Peak Peak 493 8mV 493 7m 493 5m 493 9m 73 54M 23 Feb 2011 10 16 05 Figure 10 Output Waveform Mark Tek Stop _ 459us 1 031mY Y 280ns 1 047mY A459us A15 63MV O i00mV 20045 500MS S b 7 0 00v value Mean Min Max Std Dev i gt v0 00000 5 1M points Peak Peak 491 2mV 491 3m 491 0m 512 0m 807 64 23 Feb 2011 10 20 47 Figure 11 Output Waveform Space http onsemi com 9 AND9012 D Receiver The receive band pass filter is implemented on the AS
27. tive Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5773 3850 Sales Representative AND9012 D
28. when the slave is transmitting This problem is solved by adding a series switch such as MC74VHC1G66DTT1G controlled by the RTS signal For a normally open switch the nRTS signal as applied to the A5191 must be inverted first To reduce power usage the operational amplifier can be disabled when the transmitter is turned off This is both done by inserting PNP transistor Qjon the Vpp connection of the amplifier To couple the signal into the current loop a single capacitor was used For other coupling techniques see application note AND8346 D http onsemi com 16 AND9012 D KVDE20110406 5 Loop Loop Figure 22 Sample Master Implementation APPENDIX Calculation of a three Pole Sallen Key High Pass Filter The first stage of the receive filter uses a three pole active high pass filter with a topology similar to the one shown in Figure 17 We will derive the transfer function of this filter below We will denote the gain configured with Ra and Rg as K Ra R gpz A B Ra Resistors R34 and Rap serve only to bias the amplifier input in DC and can for the rest of the calculations be considered parallel and replaced by one resistor Pp Raa Rap yg R3aRga Using Kirkhof s current law we get in the three nodes of the filter Tr F3 Va V lsCa V3 als 3 R O eq 1 V ui Vout F Ra Ry VM V sC KA 60506 pa 0 in 1 FI 2 2 Ri eq 3 Solving Equations 1
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