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USER'S MANUAL

1. Interrupt Mask Register Global Interrupt Control El DI or SYM O manipulation Figure 5 4 Interrupt Function Diagram 5 6 ELECTRONICS S3F84K4 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 2 Table 5 2 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s PO O external interrupt POCONL E7H PO 1 external interrupt POPND E8H Timer 0 A match interrupt TACON P2CONL Timer B match interrupt TBCON PWM overflow interrupt IRQ2 PWMCON F3H POCONH E6H ELECTRONICS 5 7 INTERRUPT STRUCTURE S3F84K4 SYSTEM MODE REGISTER SYM The system mode register SYM DEH is used to globally enable and disable interrupt processing and to control fast interrupt processing see Figure 5 5 A reset clears SYM 1 and SYM 0 to 0 The 3 bit value for fast interrupt level selection SYM 4 SYM 2 is undetermined The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the norm
2. fxx divided by 256 64 8 or 1 for timer A fxx divided by 256 64 8 or 1 for timer B 8 bit counter TACNT TBCNT 8 bit comparator and 8 bit reference data register TBDATA Timer A match interrupt IRQ1 vector F6H generation Timer A control register TACON D2H read write Timer B match interrupt IRQ1 vector F4H generation Timer B control register TBCON EEH read write Function Description Interval Timer Function The timer A and B module can generate an interrupt the timer A match interrupt TAINT and the timer B match interrupt TBINT TAINT belongs to the interrupt level IRQ1 and is assigned a separate vector address F6H TBINT belongs to the interrupt level IRQ1 and is assigned a separate vector address F4H The TAINT and TBINT pending condition should be cleared by software after they are serviced In interval timer mode a match signal is generated when the counter value is identical to the values written to the TA or TB reference data registers TADATA or TBDATA The match signal generates corresponding match interrupt TAINT vector F6H TBINT vector F4H and clears the counter If for example you write the value 10H to TBDATA 0 to TACON 7 and OEH to TBCON the counter will increment until it reaches 10H At this point the TB interrupt request is generated the counter value is reset and counting resumes Timer A and B Control Register TACON TBCON You use
3. ELECTRONICS 6 27 INSTRUCTION SET S3F84K4 CLR Clear CLR dst Operation dst lt 0 The destination location is cleared to O Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R 4 B1 IR Examples Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR OOH gt Register OOH OOH CLR 01H gt Register 01H 02H register 02H OOH In Register R addressing mode the statement CLR OOH clears the destination register OOH value to OOH In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to OOH 6 28 ELECTRONICS S3F84K4 COM Complement COM Operation Flags Format Examples dst dst NOT dst INSTRUCTION SET The contents of the destination location are complemented one s complement all 1s are changed to Os and vice versa C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Bytes Cycles opc dst 2 4 4 Given R1 07H and register 07H OF1H COM RI gt R1 OF8H COM QRI gt R1 07H register 07H OEH Opcode Addr Mode Hex dst 60 R 61 IR In the first example destination working register R1 contains the value 07H 000001 11B The statement COM R1 complements all the bits in R1 all logic ones ar
4. A 12 bit address bus supports program memory operations separate 8 bit register bus carries addresses and data between the CPU and the internal register file The S3F84K4 have 4 Kbytes of multi time programmable Flash program memory which is configured as the Internal ROM mode all of the 4 Kbyte internal program memory is used The S3F84K4 microcontroller has 208 general purpose registers in its internal register file 37 bytes in the register file are mapped for system and peripheral control functions ELECTRONICS 2 1 ADDRESS SPACES S3F84K4 PROGRAM MEMORY ROM Normal Operating Mode The S3F84K4 have 4 Kbytes locations OH OFFFH of internal multi time programmable Flash program memory The first 256 bytes of the ROM 0H OFFH are reserved for interrupt vector addresses Unused locations except 3CH 3DH 3EH 3FH in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations 3CH 3DH 3EH 3FH is used as smart option ROM cell The program Reset address in the ROM is 0100H Decimal 4 095 4K Byte Internal Program Memory Area Interrupt Vector Area Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS S3F84K4 ADDRESS SPACES Smart Option Smart option is the ROM option for starting condition of the chip The ROM addresses used by smart option are from 003CH to 003FH T
5. In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations COH FFH in set 1 using the Indirect Register addressing mode Program Memory Register File Bothegster dl ADDRESS OPCODE Point to One Register in Register One Operand File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3F84K4 INDIRECT REGISTER ADDRESSING MODE Continued Register File Program Memory Example REGISTER Instruction PAIR References OPCODE Points to Program Register Pair 1 16 Bit Memory Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND 4 CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3F84K4 AD
6. Watchdog RESET RESET Internal System RESETB When the Von level is lower than VLvR Smart Option 3EH 7 NOTES 1 The target of voltage detection level is the one you selected at smart option 3EH 2 BGR is Band Gap voltage Reference Figure 8 1 Low Voltage Reset Circuit NOTE To program the duration of the oscillation stabilization interval you must make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON 8 2 ELECTRONICS S3F84K4 RESET and POWER DOWN MCU Initialization Sequence The following sequence of events occurs during a Reset operation All interrupts are disabled The watchdog function basic timer is enabled Ports 0 2 are set to input mode Peripheral control and data registers are disabled and reset to their initial values see Table 8 1 The program counter is loaded with the ROM reset address 0100H When the programmed oscillation stabilization time interval has elapsed the address stored in ROM location 0100H and 0101H is fetched and executed Smart Option nRESET wu 3EH 7 Internal nRESET LVR nRESET Watchdog nRESET Figure 8 2 Reset Block Diagram Oscillation Stabilization Wait Time 65 5 ms at 8 MHz nRESET Input Idle
7. 10 12 4 ELECTRONICS S3F84K4 A D CONVERTER INTERNAL A D CONVERSION PROCEDURE 1 2 Analog input must remain between the voltage range of Vgs and Vpp Configure the analog input pins to input mode by making the appropriate settings in POCONH POCONL and P2CONH registers Before the conversion operation starts you must first select one of the nine input pins ADCO ADCS by writing the appropriate value to the ADCON register When conversion has been completed 50 clocks have elapsed the EOC flag is set to 1 so that a check can be made to verify that the conversion was successful The converted digital value is loaded to the output register ADDATAH 8 bit and ADDATAL 2 bit then the ADC module enters an idle state The digital conversion result can now be read from the ADDATAH and ADDATAL register Analog Input Pin ADCO ADC8 S3F84K4 Figure 12 5 Recommended A D Converter Circuit for Highest Absolute Accuracv ELECTRONICS 12 5 A D CONVERTER S3F84K4 GF PROGRAMMING TIP Configuring A D Converter ORG 0000H jM lt lt Smart Option gt gt ORG 003CH DB OFFH DB OFFH DB OFFH DB OFEH d lt lt Interrupt Vector Address gt gt VECTOR 0F6H INT TIMERO d lt lt Initialize System and Peripherals gt gt ORG 0100H RESET DI LD SPL H0COH LD BTCON 10100011B LD POCONH 11111111B LD POCONL 11111111B LD P2CONH 00100000B EI jM lt lt Main loop gt gt MAIN CALL AD CONV JR
8. Example dst b dst b lt NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC R11 gt R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101B in register R1 Because the result of the complement is not 0 the zero flag Z in the FLAGS register OD5H is cleared ELECTRONICS 6 19 INSTRUCTION SET S3F84K4 BITR Bit Reset BITR dst b Operation dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst dst b 0 2 4 77 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITR R11 gt R1 05H If the value of working register R1 is 07H 00000111B th
9. ORG 0100H RESET DI LD SPL 0COH LD BTCON 10100011B LD POCONH 10011010B LD PWMCON 01000110B LD PWMEX 00H LD PWMDATA 80H El lt lt Main loop gt gt JR t MAIN INT PWM AND PWMCON 11111110B IRET END ELECTRONICS 003CH must be initialized to 1 003DH must be initialized to 1 003EH enable LVR 3 0 003FH External RC oscillator SSF84K4 PWM interrupt vector disable interrupt Stack pointer must be set Watchdog disable Configure P0 6 PWM output fOSC 64 counter interrupt enable Enable interrupt PWM interrupt service routine pending bit clear 12 BIT PWM S3F84K4 NOTES 11 8 ELECTRONICS S3F84K4 A D CONVERTER A D CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the nine input channels to equivalent 10 bit digital values The analog input level must lie between the Vpp and Vss values The A D converter has the following components Analog comparator with successive approximation logic D A converter logic ADC control register ADCON Nine multiplexed analog data input pins ADCO ADCS 10 bit A D conversion data output register ADDATAH L To initiate an analog to digital conversion procedure you write the channel selection data in the A D converter control register ADCON to select one of the nine analog input pins ADCn n 0 8 and set the conversion start o
10. Register R Indirect Register IR Indexed X Direct Address DA Indirect Address IA Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3F84K4 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File D c __ MEER posu ane OPERAND Ailsa M ORCODE Register in Register L One Operand 47 File Instruction Example Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RPO ot RP1 RPO or RP1 e 34 Selected RP points to start p of working Working Register dst sic e 2 LSPS deed Point to the OPGODE Working Register Two Operand 1 of 8 Instruction Example Program Memory Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS S3F84K4 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR
11. Register File EE RPO or RP1 p RPO or RP1 Selected block RP points to start of Program Memory as OFFSET NEXT 2 Bits Register Register Address OPCODE Point to Working Pair A DL ro 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in 16 Bits Instruction Sample Instructions LDC R4 404H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 404H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 ELECTRONICS S3F84K4 ADDRESSING MODES INDEXED ADDRESSING MODE Concluded Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points Program Memory to start of working OFFSET register block OFFSET NEXT 2 Bits l R R Me king tp dst sre src e 4 gt Register egister ress Point to Working Pair OPCODE Register Pair 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in 16 Bits 1 Instruction Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 I
12. 0 256 0 004 1 50 0 10 0 059 0 004 0 10 MAX 0 004 MAX 0 45 0 018 0 10 0 30 0 07 0 004 0 012 0 003 NOTE Dimensions are in millimeters Figure 14 6 16 SSOP BD44 Package Dimensions ELECTRONICS S3F84K4 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provide a powerful and ease to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win98 2000 XP as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator OPENice i500 for the S3C7 S3C9 and S3C8 microcontroller families OPENice i500 is supported by a third party tool vendor System It also offers supporting software that includes debugger an assembler and a program for setting options SASM The SASM takes a source file containing assembly language statements and translates them into a corresponding source code an object code and comments The SASM supports macros and conditional assembly It runs on the MS DOS operating system As it produces the re locatable object codes only the user should link object files Object files can be linked with other object files and loaded into memory SASM requires a source file and auxiliary register file device name reg with device specific information S
13. 8 bvte register slices at one time as active working register space After a reset RPO points to address COH selecting the 8 bvte working register slice COH C7H 2 0 Not used for the S3F84K4 RP1 Register Pointer 1 D7H Reset Value 1 1 0 0 1 Read Write R W R W R W R W R W 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 208 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H selecting the 8 byte working register slice C8H CFH 2 0 Not used for the S3F84K4 4 22 ELECTRONICS S3F84K4 CONTROL REGISTERS SPL Stack Pointer D9H Reset Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W 7 0 Stack Pointer Address Low Byte The SP value is undefined following a reset STO PCON STOP Mode Control Register F4H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W T 0 Watchdog Timer Function Enable Bit 10100101 Enable STOP instruction Other value Disable STOP instruction NOTES 1 Before execute the STOP instruction set this STPCON register as 10100101b 2 When STOPCON register is not 20A5H value if you use STOP instruction PC is changed to reset address ELECTRONICS 4 2 CONTROL REGISTERS S3F84K4 SVM Svstem Mode Register DEH Re
14. ADD R1 R2 gt R1 1CH R2 03H ADD 01H 02H 3 Register 01H 24H register 02H 03H ADD 01H 02H gt Register 01H 2BH register 02H 03H ADD 01H 425H gt Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 ELECTRONICS 6 15 INSTRUCTION SET S3F84K4 AND Logical AND AND Operation Flags Format Examples dst src dst lt dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 53 r Ir opc src dst 3 6 54 R R 55 R IR opc dst src 3 6 56 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register O3H OAH AND R1 R2 gt R1 02H R2 03H AND R1 R2 gt R1 02H R2 03H AND 01H 02H gt Register 01H 01H register 02H 03H gt gt AND 01H 02H Register 01H 00H register 02H 03H AND 01H 25H Register 01H 2
15. Cycles 4 Opcode Hex 40 41 Carry After DA o 0 a Addr Mode dst R IR 6 33 INSTRUCTION SET S3F84K4 DA pecimal Adjust DA Example Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD R1 R0 C lt lt 0 Bits 4 7 3 bits 0 3 C R1 3CH DA R1 R1 lt 3CH 06 If addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO C lt H lt 0 Bits 4 7 3 bits 0 3 1 DA R1 R1 lt 31 0 leave the value 31 BCD in address 27H EORI ELECTRONICS S3F84K4 DEC Decrement DEC Operation Flags Format Examples dst dst dst 1 The contents of the destination operand are decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles opc dst 2 4 4
16. P2 5 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 1 0 Port 2 P2 4 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output NOTE When noise problem is important issue you had better not use CLO output Figure 9 9 Port 2 Control Register P2CONH High Byte 9 10 ELECTRONICS S3F84K4 I O PORTS Port 2 Control Register Low Byte EBH R W 7 6 Port 2 P2 3 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 5 4 Port 2 P2 2 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 3 2 Port 2 P2 1 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 1 0 Port 2 P2 0 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 TO match output Figure 9 10 Port 2 Control Register P2CONL Low Byte ELECTRONICS 9 11 I O PORTS S3F84K4 NOTES 9 12 ELECTRONICS S3F84K4 BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 MODULE OVERVIEW The S3F84K4 has two default timers an 8 bit basic time
17. note 1110 nete 1001 0001 1010 Always false Always true Carry No carry Zero Not zero Plus Minus Overflow No overflow Equal Not equal Greater than or equal Less than Greater than O 1 0 0 1 1 0 1 0 XX o R S XOR V 0 0010 Less than or equal R S XOR V 21 1111 note Unsigned greater than or equal 0111 note Unsigned less than 1011 Unsigned greater than 0011 Unsigned less than or equal NOTES 1 It indicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 Foroperations involving unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS S3F84K4 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by
18. registers and peripheral control registers The lower 192 bytes of internal register file 00H BFH is called the general purpose register space 245 registers in this space can be accessed 208 are available for general purpose use For many SAM8RC microcontrollers the addressable area of the internal register file is further expanded by additional register pages at the general purpose register space 00H BFH pageo This register file expansion is not implemented in the S3F84K4 however The specific register types and the area in bytes that they occupy in the internal register file are summarized in Table 2 1 Table 2 1 Register Type Summary Register Type Number of Bytes CPU and system control registers peripherals I O and clock control and data registers General purpose registers including the 16 bit common working register area Total Addressable Bytes ELECTRONICS 2 5 ADDRESS SPACES S3F84K4 Peripheral Control Registers 64 Bytes of Common Area System Control Registers Working Registers General Purpose 192 Bytes Register File and Stack Area Figure 2 3 Internal Register File Organization 2 6 ELECTRONICS S3F84K4 ADDRESS SPACES COMMON WORKING REGISTER AREA COH CFH The SAM8RC register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time This 16 byte address range is called common a
19. 003CH must be initialized to 0 003DH must be initialized to 0 003EH enable LVR 3 0v 003FH External RC oscillator disable interrupt Watch dog disable Select non divided CPU clock Stack pointer must be set PO O PO 7 push pull output PO O PO 1 interrupt enable P1 1 push pull output P2 0 P2 6 push pull output Enable IRQO IRQ1 IRQ2 interrupt IRQ2 gt IRQ1 gt IRQO fosc 256 Timer A interrupt enable fosc 256 Timer B interrupt enable Enable interrupt 8 7 RESET and POWER DOWN E PROGRAMMING TIP Sample S3F84K4 Initialization Routine Continued mannen lt lt Main loop gt gt MAIN NOP LD BTCON 02H ca KEY_SCAN on LED DISPLAY on JOB T MAIN JA lt lt Subroutines gt gt KEY SCAN NOP RET LED DISPLAY NOP RET JOB NOP RET 8 8 Start main loop Enable watchdog function Basic counter BTCNT clear S3F84K4 ELECTRONICS S3F84K4 RESET and POWER DOWN E PROGRAMMING TIP Sample S3F84KA Initialization Routine Continued Timer A interrupt service routine gt INT TIMERA AND TACON 11111110B IRET Timer B interrupt service routine gt INT TIMERB AND TBCON 11111110B IRET PWM overflow interrupt service routine gt PWMOVF INT AND PWMCON 11111110B IRET i External interruptO service routine gt INT EXTO 6 AND POPND 11111110B IRET External interrupt1 service
20. 03H ADC R1 R2 gt R1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H 03H ADC 01H 02H gt Register 01H 2BH register 02H 03H ADC 01H 11H gt Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 ELECTRONICS S3F84K4 INSTRUCTION SET ADD Add ADD Operation Flags Format Examples dst src dst lt dst src The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed Set if there is a carry from the most significant bit of the result cleared otherwise Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise lt ONO D Always cleared to 0 H Set if a carry from the low order nibble occurred Bytes Cycles Opcode Addr Mode Hex dst src 6 03 r Ir opc src dst 3 6 04 R R 05 R IR opc dst src 3 6 06 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H OAH ADD R1 R2 gt R1 15H R2 03H
21. 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3F84K4 CALL Call Procedure CALL Operation Flags Format Examples dst SP lt SPA BSP lt PCL SP c SP 1 OSP lt PCH PC lt dst The current contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 IA Given RO 35H R1 21H PC 1A47H and SP 0002H CALL 3521H gt SP 0000H Memory locations 0000H 1AH 0001H 4AH where 4AH is the address that follows the instruction CALL RRO gt SP 0000H 0000H 1AH 0001H 49H CALL 40H gt SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 000
22. 10 7 BASIC TIMER and TIMER 0 S3F84K4 Timer 0 Control Register TACON You use the timer 0 control register TACON to Enable the timer 0 operating interval timer Select the timer 0 input clock frequency Clear the timer 0 counter TACNT and TBCNT Enable the timer 0 interrupt Clear timer 0 interrupt pending condition TACON is located at address DOH and is read write addressable using register addressing mode A reset clears TACON to 00H This sets timer O to disable interval timer mode selects an input clock frequency of fxx 256 and disables timer 0 interrupt You can clear the timer 0 counter at any time during the normal operation by writing a 1 to TACON 3 To enable the timer 0 interrupt IRQ1 vector F6H you must write TACON 7 TACON 2 and TACON 1 to 1 To generate the exact time interval you should set TACON 3 and TACON 0 to 10B which clear counter and interrupt pending bit When the TOINT sub routine is serviced the pending condition must be cleared by software by writing a to the timer 0 interrupt pending bit TACON O Timer 0 Control Register TACON Always 0 Timer 0 interrupt pending bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt is pending when read Timer 0 clock 1 No effect when write selection bits Timer 0 interrupt enable bit 00 fxx 256 0 Disable interrupt 01 fxx 64 1 Enable interrupt 10 fxx 8 11 fxx Timer 0 counte
23. 1234H 02H 0FEDH gt gt fy R6 06H R7 1CH R4 06H R5 1CH Register 00H 03H register 01H OFH register 02H register OFH R2 03H R3 OFH Register 04H 03H register 05H OFH R6 12H R7 34H Register 02H OFH register OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H into the destination word 00H 01H This leaves the value 03H in general register 00H and the value OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS S3F84K4 MULT multiply Unsigned MULT Operation Flags Format Examples dst src dst lt dst src The 8 bit destination operand even register of the register pair is multiplied by the source INSTRUCTION SET operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers C Set if result is 255 cleared otherwise Z Set if the result is 0 cleared otherwise S Set if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Bytes Cycles opc src dst 3 22 22 22 Given Register 00H 20H register 01H register 02H MULT OOH 02H gt Register 00H 01H register 01H MULT 00H 01H gt Register 00H 00H
24. Bit Not pending Pending 6 Level 6 IRQ6 Request Pending Bit 0 1 Not pending Pending 5 Level 5 IRQ5 Request Pending Bit Not pending 1 Pending 4 Level 4 IRQ4 Request Pending Bit Not pending Pending 3 Level 3 IRQ3 Request Pending Bit Not pending Pending 2 Level 2 IRQ2 Request Pending Bit Not pending 1 Pending 1 Level 1 IRQ1 Request Pending Bit Not pending Pending 0 Level 0 IRQ0 Request Pending Bit Not pending Be Pending ELECTRONICS 4 1 CONTROL REGISTERS S3F84K4 POCONH Port 0 Control Register High Byte E6H Bit Identifier 7 6 8 4 3 2 1 0 0 0 0 0 0 0 0 0 RESET Value Read Write RAN R W R W R W R W R W R W R W 7 6 Port 0 PO 7 INT7 Configuration Bits ojo Schmitt trigger input pull up enable Schmitt trigger input 1 A D converter input ADC7 Schmitt trigger input off 5 4 Port 0 P0 6 ADC6 PWM Configuration Bits FJES Schmitt trigger input pull up enable 0 i Alternative function PWM output IEWIEN Push pull output A D converter input ADC6 Schmitt trigger input off 3 2 Port 0 P0 5 ADC5 Configuration Bits Polo Schmitt trigger input pull up enable 1 Schmitt trigger input 0 Push puloupat A D converter input ADC5 Schmitt trigger input off 1 0 Port 0 P0 4 ADC4 Configuration Bits FEN Schmitt trigger input
25. Given R1 03H and register 03H 10H DEC RI gt R1 02H DEG QR gt Register 03H OFH INSTRUCTION SET Opcode Addr Mode Hex dst 00 R 01 IR In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET S3F84K4 D ECW Decrement Word DECW Operation Flags Format Examples NOTE dst dst dst 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 80 RR 81 IR Given RO 12H R1 34H R2 30H register 30H OFH and register 31H 21H DECW RRO gt RO 12H R1 33H DECW R2 Register 30H OFH register 31H 20H In the first example destination register RO contains the value 12H and register R1 the value 34H The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value
26. Idle mode is released by a reset or by an interrupt external or internally generated SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in location DAH It is read write addressable and has the following functions Oscillator IRQ wake up function enable disable CLKCON 7 Oscillator frequency divide by value non divided 2 8 or 16 CLKCON 4 and CLKCON 3 The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release This is called the IRQ wake up function The IRQ wake up enable bit is CLKCON 7 After a reset the external interrupt oscillator wake up function is enabled the main oscillator is activated and the fosc 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to fosc fosc 2 or fosc 8 Svstem Clock Control Register CLKCON D4H R W Oscillator IRQ wake up enable bit Not used for 0 Enable IRQ for main system S3F84K4 oscillator wake up function in power mode Divide by selection bits for 1 Disable IRQ for main system CPU clock frequency oscillator wake up function in 00 fosc 16 power down mode 01 fosc 8 10 fosc 2 11 fosc non divided Not used for S3F84K4 Figure 7 3 System Clock Control Register CLKCON 7 2 ELECTRONICS S3F84K4 Internal RC Oscillator 8 MHz Internal RC Oscillator 1 MHz External Crystal Ceramic
27. Low Byte DBH Reset Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH ELECTRONICS 4 11 CONTROL REGISTERS S3F84K4 IPR Interrupt Priority Register FFH Bit Identifier 8 4 3 2 4 0 X X X X X X X Reset Value X Read Write R W R W R W R W R W R W R W R W 7 4 and 1 Priority Control Bits for Interrupt Groups A B and C note Group priority undefined B gt CsA A gt B gt C B gt A gt C C gt A gt B 1 C gt BsA A gt C gt B 1 1 Group priority undefined 6 Interrupt Subgroup C Prioritv Control Bit IRQ6 gt IRQ7 IRQ7 gt IRQ6 fel 5 Interrupt Group C Prioritv Control Bit IRQ5 IRQ6 IRQ7 1 IRQ6 IRQ7 IRQ5 3 Interrupt Subgroup B Priority Control Bit IRQ3 gt IRQ4 IRQ4 gt IRQ3 2 Interrupt Group B Priority Control Bit IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group Priority Control Bit IRQO gt IRQ1 IRQ1 gt IRQO NOTE Interrupt Group IRQO IRQ1 Interrupt Group B IRQ2 IRQ3 IRQ4 Interrupt Group C IRQ5 IRQ6 IRQ7 4 12 ELECTRONICS S3F84K4 CONTROL REGISTERS IRQ Interrupt Request Register DCH Reset Value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R 7 Level 7 IRQ7 Request Pending
28. NOPs are executed in sequence in order to effect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex opc 1 4 FF When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 61 INSTRUCTION SET S3F84K4 Logical OR OR Operation Flags Format Examples dst src dst lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 43 r Ir opc src dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO 3FH R1 2AH OR RO R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register 00H 3FH register 01H 37H OR 01H O00H gt Register OOH 08H register 01H OBFH OR 00H 02H gt Register OOH OAH In the first example if working register RO contains the value 15H and registe
29. PortO pins can also be used as A D converter PWM input PWM output or external interrupt input P1 1 Bit programmable I O port for Schmitt trigger input or E 2 Xour push pull open drain output Pull up resistors or pull down resistors are assignable by software IPi2 l I Schmitt trigger input port B RESET P2 0 P2 6 lO Bit programmable I O port for Schmitt trigger input or push E pull open drain output Pull up resistors are assignable by ADC8 CLO software TO Xin Xout Crystal Ceramic or RC oscillator signal for system clock Xour is shared with P1 1 naeser memsvRoremaRESEr sy me Von Vss JVoltageinput pin and ground PP Go o wemcxkopupn fer ms toan fexemalimerptmputpon Poopo 0 eStghsedPWAoupa fer ms o ADCO ADC8 A D converter input E 1 P0 0 P0 7 E P2 6 1 6 ELECTRONICS S3F84K4 PRODUCT OVERVIEW Table 1 2 Descriptions of Pins Used to Read Write the Flash ROM Main Chip During Programming PO 1 pi I O Serial data pin output when reading Input pi when writing Input and push pull output port can be assigned 20 Serial clock pin input only pin 16 P1 0 Power supply pin for flash ROM cell writing indicates that MTP enters into the writing mode When 12 V is applied MTP is in writing mode and when 5 V is applied MTP is in reading mode Option Note A 100pF capacitor mus
30. R8 ODDH R6 10H R7 34H ELECTRONICS 6 55 INSTRUCTION SET S3F84K4 LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples dst src r rr 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given RO 77H R6 30H and R7 00H LDCPD RR6 RO RR6 lt RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH LDEPD RR6 RO RR6 lt RR6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 ELECTRONICS S3F84K4 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples dst src Ir rr 1 dst lt src These instructions are used for block transfers of data from program or data memory from t
31. Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W 7 6 PWM Input Clock Selection Bits 5 4 Not used for S3F84K4 3 PWM Counter Clear Bit No effect 1 Clear the PWM counter when write 2 PWM Counter Enable Bit 0 Stop counter 1 Start Resume countering 1 PWM Overflow Interrupt Enable Bit 12 Bit Overflow Disable interrupt 1 Enable interrupt 0 PWM Overflow Interrupt Pending Bit No interrupt pending when read 0 Clear pending bit when write Interrupt is pending when read No effect when write NOTE PWMCON O is not auto cleared You must pay attention when clear pending bit Refer to page 11 7 4 20 ELECTRONICS S3F84K4 CONTROL REGISTERS PP Register Page Pointer DFH Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W T 0 Not used for the S3F84K4 NOTE In S3F84KA only page 0 settings are valid Register page pointer values for the source and destination register page are automatically set to OOF following a hardware reset These values should not be changed during normal operation ELECTRONICS 4 21 CONTROL REGISTERS S3F84K4 RPO Register Pointer 0 D6H Reset Value 1 1 0 0 0 Read Write R W R W R W R W R W T 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 208 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two
32. an interrupt is determined by the setting in basic timer control register BTCON BTCON 3 BTCON 2 t wAIT When fosc is 8 MHz LI amme o eme Figure 10 3 Oscillation Stabilization Time on STOP Mode Release ELECTRONICS BASIC TIMER and TIMER 0 S3F84K4 G PROGRAMMING TIP Configuring the Basic Timer This example shows how to configure the basic timer to sample specification RESET ORG 0000H lt lt Smart Option gt gt ORG 003CH DB OFFH DB OFFH DB OFFH DB OFEH lt lt Interrupt Vector Address gt gt lt lt Initialize System and Peripherals gt gt ORG 0100H DI LD CLKCON 00011000B LD SPL 0COH LD BTCON 02H EI LD BTCON 02H JR T MAIN END 003CH must be initialized to 1 003DH must be initialized to 1 003EH enable LVR 3 0v 003FH External RC oscillator Disable interrupt Select non divided CPU clock Stack pointer must be set Enable watchdog function Basic timer clock fosc 4096 Basic counter BTCNT clear Enable interrupt Enable watchdog function Basic counter BTCNT clear ELECTRONICS S3F84K4 BASIC TIMER and TIMER 0 ONE 16 BIT TIMER MODE TIMER 0 The 16 bit timer 0 is used in one 16 bit timer or two 8 bit timers mode When TACON 7 is set to 1 it is in one 16 bit timer mode When TACON 7 is set to 0 the timer 0 is used as two 8 bit timers One 16 bit timer mode Timer 0 Two 8 bit t
33. counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE Incase of using DJNZ instruction the working register being used as a counter should be set at the one of location OCOH to OCFH with SRP SRPO or SRPI instruction Flags No flags are affected Format Example Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken rA RA 8 no jump r 0toF Given R1 02H and LOOP is the label of a relative address SRP 0 DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3F84K4 El Enable Interrupts El Operation SYM 0 1 An El instruction sets bit zero of the system mode register SYM 0 to 1 This allows in
34. file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 3 8 82 IR R Given Register 00H 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H gt Register 00H 02H register 01H 05H register 02H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET S3F84K4 PUSHUI Push user Stack Incrementing PUSHUI Operation Flags Format Example dst src IR lt IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 3 8 83 IR R Given Register 00H register 01H 05H and register 04H 2AH PUSHUI 900H 04H gt Register OOH 04H register 01H 05H register 04H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUI 00H 01H in
35. not mapped Basic timer control register BTCON RW Jojojojojojoj Clock controlregister CLKCON RW o0 fo fol Register Pointero RW 1 1 0 0 0 Register Pointert Rm RW lilijojolil I Location D8H is not mapped Interrupt Request Register jojo ojojo Interrupt Mask Register mr pos mw pojojojojo System Mode Register sym ben RW j O0 x x Register Page Pointer RW jojo ojojo NOTE Not mapped or not used x undefined ELECTRONICS 8 5 RESET and POWER DOWN S3F84K4 Table 8 1 Register Values After a Reset Continued o mm LU P Ga Hex Izlejsjaljsizjijoj PortOdataregister Ji Po RW Jojojojojoljojojo Port 1 dataregister Pt ew RW l l l l l Jojol Port2dataregister P2 en RW jojojo ojojojo Locations E3H E5H are not mapped Port 0 control register High byte POCONH RW 0 00 Port 0 control register Low byte POCONL emm RW 0 0 00 Port interrupt pending register RW l l l l Jolojojo Port control register Picon RW o0 Jo o Port 2 control register High byte P2CONH EAH RW l jojojojojojojo Port 2 control register Low byte P2CONL RW 0 0 00 Timer B count
36. programmable ROM sizes Important CPU features include Efficient register oriented architecture Selectable CPU clock sources Idle and Stop power down mode release by interrupt Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels S3F84K4 MICROCONTROLLER The S3F84K4 single chip CMOS micro controller is fabricated using a highly advanced CMOS process and is based on Samsung s newest CPU architecture Its design is based on the powerful SAM8RC CPU core Stop and idle power down modes were implemented to reduce power consumption The S3F84K4 is a micro controller with a 4k byte multi time programmable Flash ROM embedded Using the SAM8RC design approach the following peripherals were integrated with the SAM8RC core Three configurable I O ports 17 pins Five interrupt sources with five vectors and three interrupt levels A 16 bit timer 0 with one 16 bit timer or two 8 bit timers mode Analog to digital converter with nine input channels MAX and 10 bit resolution One 12 bit PWM output The S3F84K4 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer counter PWM ADC S3F84K4 is available in a 20 16 pin DIP and a 20 16 p
37. pull up enable of Schmitt trigger input A D converter input ADC4 Schmitt trigger input off 4 14 ELECTRONICS S3F84K4 CONTROL REGISTERS POCON L Port 0 Control Register Low Byte E7H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 Port 0 P0 3 INT3 Configuration Bits Polo Schmitt trigger input Schmitt trigger input pull up enable 1 A D converter input ADC3 Schmitt trigger input off 5 4 Port 0 P0 2 ADC2 Configuration Bits Polo Schmitt trigger input 0 i Schmitt trigger input pull up enable EXE Push pull output A D converter input ADC2 Schmitt trigger input off 3 2 Port 0 PO 1 ADC1 INT1 Configuration Bits eTe Schmitt trigger input falling edge interrupt input 1 Schmitt trigger input pull up enable falling edge interrupt input e KARA A D converter input ADC1 Schmitt trigger input off 1 0 Port 0 P0 0 ADCO INTO Configuration Bits pague Schmitt trigger input falling edge interrupt input KEN Schmitt trigger input pull up enable falling edge interrupt input 1 Push pull output A D converter input ADCO Schmitt trigger input off ELECTRONICS 4 15 CONTROL REGISTERS S3F84K4 POPN D Porto Interrupt Pending Register E8H Bit Identifier _ 5 4 3 2 a 0 0 0 0 0 RESET Value Read Write R W R W R W R W 7 4 Not used for the S3F84K4 3 Port 0 1 ADC1 INT
38. register 01H Opcode Addr Mode Hex dst 84 RR 85 RR 86 RR src 09H register O3H 06H 20H register 02H 09H OCOH MULT OOH 30H gt Register OOH O6H register 01H OOH In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register 00H of the register pair 00H 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair 00H 01H ELECTRONICS 6 59 INSTRUCTION SET S3F84K4 NEXT next NEXT Operation Flags Format Example Address 0120 0120 44 Address L PC lt Q IP IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 10 OF The following diagram shows one example of how to use the NEXT instruction Before After Address Data Data Address Data 43 Address H 44 Address L 45 Address Address Data 43 PC 0130 45 Address 120 130 Routine Memory Memory ELECTRONICS S3F84K4 INSTRUCTION SET NOP no Operation NOP Operation Flags Format Example No action is performed when the CPU executes this instruction Typically one or more
39. routine gt INT EXTI AND POPND 11111011B IRET END ELECTRONICS Pending bit clear Interrupt return Pending bit clear Pending bit clear Interrupt return EXTO Pending bit clear Interrupt return EXT1 Pending bit clear Interrupt return RESET and POWER DOWN 8 10 NOTES S3F84K4 ELECTRONICS S3F84K4 I O PORTS I O PORTS OVERVIEW The S3F84K4 has three I O ports with 17 pins total You access these ports directly by writing or reading port data register addresses All ports can be configured as LED drive High current output typical 10 mA Table 9 1 S3F84K4 Port Configuration Overview Function Description Programme Bit programmable I O port for Schmitt trigger input or push pull output Pull up resistors are assignable by software Port 0 pins can also be used as alternative function ADC input external interrupt input Bit programmable I O port for Schmitt trigger input or push pull open drain output Pull up resistors are assignable by software Port 2 can also be used as alternative function ADC input CLO TO clock output Bit programmable I O port for Schmitt trigger input or push pull open drain output Pull up or pull down resistors are assignable by software Port 1 pins can also be oscillator input output or reset input by smart option P1 0 is input only ELECTRONICS 9 1 I O PORTS S3F84K4 PORT DATA REGISTERS Table 9 2 gives you an overview of the port data regi
40. t MAIN AD CONV LD ADCON 00000001B NOP NOP NOP 003CH must be initialized to 0 003DH must be initialized to 0 003EH enable LVR 3 0v 003FH external RC oscillator Timer 0 interrupt vector disable interrupt Stack pointer must be set Watchdog disable Configure PO 4 PO 7 AD input Configure P0 0 P0 3 AD input Configure P2 6 AD input Enable interrupt Subroutine for AD conversion Select analog input channel gt P0 0 select conversion speed fosc 16 set conversion start bit If you select conversion speed to fosc 16 at least three nops must be included ELECTRONICS S3F84K4 A D CONVERTER 8 PROGRAMMING TIP Configuring A D Converter Continued CONV LOOP TM JR LD LD LD CONV LOOP2 TM JR LD LD RET INT TIMERO AND IRET END ELECTRONICS ADCON 00001000B Z CONV_LOOP RO ADDATAH R1 ADDATAL ADCON 00010011B ADCON 00001000B Z CONV_LOOP2 R2 ADDATAH R3 ADDATAL TACON 11111110B Check EOC flag If EOC flag 0 jump to CONV_LOOP until EOC flag 1 High 8 bits of conversion result are stored to ADDATAH register Low 2 bits of conversion result are stored to ADDATAL register Select analog input channel 1 Select conversion speed fosc 8 Set conversion start bit Check EOC flag Pending bit clear A D CONVERTER S3F84K4 NOTES 12 8 ELECTRONICS S3F84K4 ELECTRICAL DATA OVERVIEW ELECTRICAL DATA In this section the following S3F84K4 elec
41. the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 CO R C1 IR Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC OOH gt Register 00H 2AH C 1 01H gt Register 01H 02H register 02H OBH C 1 In the first example if general register OOH contains the value 55H 01010101B the statement RRC 00H rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in destination register 00H The sign flag and overflow flag are both cleared to 0 ELECTRONICS S3F84K4 INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONICS 6 75 INSTRUCT
42. the timer A and B control register TACON and TBCON to Enable the timer A and B operating interval timer Select the timer A and B input clock frequency Clear the timer A and B counter TACNT and TBCNT Enable the timer A and B interrupts Clear timer A and B interrupt pending conditions ELECTRONICS 10 11 BASIC TIMER and TIMER 0 S3F84K4 TACON and TBCON are located at address D2H and EEH and is read write addressable using register addressing mode A reset clears TACON and TBCON to 00H This sets timer A and B to disable interval timer mode selects an input clock frequency of fxx 256 and disables timer A and B interrupt You can clear the timer A and B counter at any time during normal operation by writing a 1 to TACON 3 and TBCON 3 To enable the timer A and B interrupt IRQ1 vector F6H F4H you must write TACON 7 to 0 TACON 2 TBCON 2 and TACON 1 TBCON 1 to 1 To generate the exact time interval you should set TACON 3 TBCON 3 and TACON 0 TBCON 0 to 10B which clear counter and interrupt pending bit respectively When the TAINT or TBINT sub routine is serviced the pending condition must be cleared by software by writing a 0 to the timer A or B interrupt pending bits TACON O or TBCON O Timer A Control Register TACON D2H R W Always 0 Timer A interrupt pending bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt is pending when read 1 No effect when
43. up resistors Vin 20 V Ta 25 C Vpp 5 25 50 100 kQ Ports 0 1 2 Pull down Vin 0 V Ta 25 C Vpp 5 V resistors Ports 1 Supply current Ipp1 Run mode Vpp 2 0 to 5 5 V 8 MHz CPU clock Inp2 Idle mode Vpp 2 0 to 5 5 V 8 MHz CPU clock Ippa Vpp 2 0 to 5 5 V 25 NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads and ADC module ELECTRONICS 13 3 ELECTRICAL DATA S3F84K4 Table 13 3 AC Electrical Characteristics Ta 25 to 85 Vpp 2 0 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Interrupt input tINTL INTO INT1 500 ns low width Vpp 5V 10 RESET input tas Input 10 us low width Vpp 5V 10 Figure 13 1 Input Timing Measurement Points 13 4 ELECTRONICS S3F84K4 ELECTRICAL DATA Table 13 4 Oscillator Characteristics Ta 25 to 85 0 Clock Creu TestCondion Wim max Uni Main crystal or Vpp 4 5 to 5 5 V 1 MHz ceramic mess fi Messerv fr p pwe External clock Vop 4 5 to 5 5 V Main System Q Messe 3 p Ds pee External RC Vpp 5V oscillator Internal RC Vpp 5V oscillator Tolerance 2096 at TA 1 MHz 25 NOTES For the resistor of External RC oscillator we recommend using 28 for 8MHz at TA 25 Table 13 5 Oscillation Stabilization Time TA 25 to 8
44. use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH in set 1 using Indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or RP1 Value used in points to Instruction sabu working register block Program Memorv dus F Base Address peran dst src X Instruction Point to One of the Example Woking Register 1 of 8 Sample Instruction LD RO BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES S3F84K4 INDEXED ADDRESSING MODE Continued
45. user stack incrementing Push to stack Push user stack decrementing Push user stack incrementing ELECTRONICS S3F84K4 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3F84K4 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit
46. writ Timer A clock o effect when write selection bits Timer A interrupt enable bit 0 Disable interrupt 01 fxx 64 1 Enable interrupt 10 fxx 8 11 fxx Timer counter run enable bit 0 Disable counter running 1 Enable counter running Timer A operation mode selection bit 0 Two 8 bi timers mode Timer Ag 00 00299 1 One 16 bit timer mode Timer 0 Timer A counter clear bit 0 No affect 1 Clear the timer A counter when write NOTE TACON 6 must be always 0 during normal operation Figure 10 7 Timer A Control Register TACON 10 12 ELECTRONICS S3F84K4 BASIC TIMER and TIMER 0 Timer B Control Register TBCON EEH Not used for S3F84K4 Timer B interrupt pending bit 0 No interrupt pending Timer B clock selection bits 0 Clear pending bit when write 00 fxx 256 1 Interrupt is pending when read 01 fxx 64 1 No effect when write 10 fxx 8 Timer B interrupt enable bit 11 fxx 0 Disable interrupt 1 Enable interrupt Timer B counter run enable bit 0 Disable counter running 1 Enable counter running Timer B counter clear bit 0 No affect 1 Clear the timer B counter when write Figure 10 8 Timer B Control Register TBCON ELECTRONICS 10 13 BASIC TIMER and TIMER 0 256 64 8 2 TA Buffer Register i TA Counter Clear Signal TA Match Signal MOAN TB Counter Clear Signal TB Match Sign
47. 0 control register Low byte POCONL RW Port 0 interrupt pending register Port 2 control register High byte P2CONH EA 1010 10 1010 010 H R W EBH RW Timer B counter register jojojojojoj ojo o Timer control register TBCON RW l l Jojojojojojoj Locations EFH FOH are not mapped PWM extension data register em mw F AD convener data register High rev m ofofo FDH rR Jojojojojojojojo External memory timing register EMT FEH RW Jojilijiji ijol Interrupt priority register PR RW NOTES 1 Not mapped or not used x Undefined ELECTRONICS 4 3 CONTROL REGISTERS Bit number s that is are appended to the register name for bit addressing Kea GE individual Register bit or related bits ID Register name S3F84K4 Register address hexadecimal FLAGS System Flags Register Bit Identifier RESET Value Read Write R W Carry Flag C R W R W R W R W 0 Operation dose not generate a carry or borrow condition Operation generates carry out or borrow into high order bit7 Zero Flag KU Operation result is a non zero value Operation result is zero Sign Flag EN Operation generates positive number MSB Operation generates negative numbe
48. 00111B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F84K4 INSTRUCTION SET BXOR Bit XOR BXOR BXOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 XOR src b or dst b s dst b XOR sre 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 27 Rb 0 NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 gt R1 06H register 01H 03H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value
49. 1 Interrupt Enable Bit EY INTI falling edge interrupt disable NT1 falling edge interrupt enable 1 I 2 Port 0 1 ADC1 INT1 Interrupt Pending Bit No interrupt pending when read Pending bit clear when write Interrupt is pending when read No effect when write 1 Port 0 0 ADCO INTO Interrupt Enable Bit 0 INTO falling edge interrupt disable 1 INTO falling edge interrupt enable 0 Port 0 0 ADCO INTO Interrupt Pending Bit ES No interrupt pending when read Pending bit clear when write Interrupt pending when read No effect when write 4 16 ELECTRONICS S3F84K4 CONTROL REGISTERS P1CON Port 1 Control Register E9H RESET Value 0 0 0 0 Read Write R W R W R W R W R W R W 7 Part 1 1 N channel open drain Enable EZ Configure P1 1 as a push pull output Configure P1 1 as a n channel open drain output 6 4 Not used for S3F84K4 3 2 Port 1 P1 1 Interrupt Pending Bits EXE Schmitt trigger input 0 i Schmitt trigger input pull up enable ENKNETT Schmitt trigger input pull down enable 1 0 Not used for S3F84K4 NOTE When vou use external oscillator P1 1 must be set to output port to prevent current consumption ELECTRONICS 4 17 CONTROL REGISTERS S3F84K4 P2CONH Port 2 Control Register High Byte EAH Bit Identifier RESET Value Read Write _ 5 4 3 2 a 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W Not used for the S3F8
50. 1H 04H LDC R0 1104H RO lt contents of program memory location 1104H RO 88H LDE R0 1104H RO lt contents of external data memory location 1104H RO 98H LDC note 1105H RO 11H contents of RO is loaded into program memory location 1105H 1105H lt 11H LDE 1105H RO 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE These instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET S3F84K4 LDCD LDED Load Memory and Decrement LDCD LDED dst src Operation Flags Format Examples dst lt src rr rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory location 1033H OCDH and external data memory location 1033H ODDH LDCD R8 RR6 contents of program memory location 1033H is loaded into R8 and RR6 i
51. 1H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS S3F84K4 INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 AND src b or dst b lt dst b AND src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 67 Rb 0 NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101B and destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1
52. 21 S3 F84K4 072006 USER S MANUAL S3F84K4 8 Bit CMOS Microcontrollers Revision 1 ELECTRONICS NOTIFICATION OF REVISIONS ORIGINATOR Samsung Electronics LSI Development Group Ki Heung South Korea PRODUCT NAME S3F84K4 8 bit CMOS Microcontroller DOCUMENT NAME S3F84K4 User s Manual Revision 1 DOCUMENT NUMBER 21 S3 F84K4 072006 EFFECTIVE DATE September 2006 SUMMARY As a result of additional product testing and evaluation some specifications published in S3F84K4 User s Manual Revision 0 have been changed These changes for S3F84K4 microcontroller which are described in detail in the Revision Descriptions section below are related to the followings Chapter 1 Overview Chapter 2 Address Spaces Chapter 7 Clock Circuit Chapter 8 RESET and Power Down Chapter 10 Basic Timer and Timer 0 Chapter 12 A D Converter Chapter 13 Electrical Data DIRECTIONS Please note the changes in your copy copies of the S3F84K4 User s Manual Revision 0 Or simply attach the Revision Descriptions of the next page to S3F84K4 User s Manual Revision 0 REVISION HISTORY o xe G July 2005 Preliminary Spec for internal release only September 2006 First edition S3F84K4 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 S3F8 SERIES MICROCONTROLLERS Samsung s S3C8 S3F8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask
53. 2H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location 0000H The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL QRRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS S3F84K4 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C lt NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero if C O the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one
54. 4K4 Port 2 P2 6 ADC8 CLO Configuration Bits ojojo Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 x ADC input 1 o o JPusnepullovtput O 1 0 1 Open drain output pull up enable S O 1 1 0 Open drain output S O Port 2 2 5 Configuration Bits 0 Schmit rigger inout paupere oo i 0 1 Schmitt trigger input output Port 2 2 4 Configuration Bits Schmitt trigger input pull up enable Schmitt trigger input Push pull output NOTE When noise problem is important issue you had better not use CLO output ELECTRONICS S3F84K4 CONTROL REGISTERS P2CON L Port 2 Control Register Low Byte EBH RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 Part 2 P2 3 Configuration Bits EXE Schmitt trigger input pull up enable o 1 Open drain output 5 4 Port 2 P2 2 Configuration Bits Fo o Senmittrggerinputipuliupenae 0 i Schmitt trigger input r opem 3 2 Port 2 P2 1 Configuration Bits pool Schmitt trigger input pull up enable 1 Schmitt trigger input Cr s Posten 1 1 Open drain output o OS 1 0 Port 2 P2 0 Configuration Bits Polo Schmitt trigger input pull up enable KEN Schmitt trigger input afo asmo ELECTRONICS 4 19 CONTROL REGISTERS S3F84K4 PWMCON PWM Control Register F3H RESET
55. 5 C Vpp 2 0 V to 5 5 V Oscillator Test Condition Min Typ Unit ancy femte gt a ms Main ceramic Oscillation stabilization occurs when Vpp is 10 ms equal to the minimum oscillator voltage range 25 500 ns External clock Xn input high and low width ty main system Oscillator twarr When released by a reset 1 2 fosc ms stabilization Wait time twarr When released by an interrupt 2 NOTES 1 foscis the oscillator frequency 2 The duration of the oscillator stabilization wait time tWAIT when it is released by an interrupt is determined by the settings in the basic timer control register BTCON Vr ELECTRONICS 13 5 ELECTRICAL DATA S3F84K4 4 4 5 5 5 5 6 Supply Voltage V Figure 13 2 Operating Voltage Range 0 3 VDD 0 7 VDD Figure 13 3 Schmitt Trigger Input Characteristics Diagram 13 6 ELECTRONICS S3F84K4 ELECTRICAL DATA Table 13 6 Data Retention Supply Voltage in Stop Mode TA 25 to 85 Vpp 2 0 to 5 5 V Data retention VDDDR Stop mode 2 0 supply voltage Data retention IpppR Stop mode Vpppn 2 0 V 100 supply current Oscillation Stop Mode Stabilization Data Retention Mode gt Execution Of Operating Stop Instrction Mode NOTE twarr is the same as 4096 x 16 x 1 fosc Figure 13 4 Stop Mode Release Timing When
56. AMA ASSEMBLER The Samsung Arrangeable Microcontorller SAM Assembler SAMA is a universal assembler and generating an object code in the standard hexadecimal format Assembled program codes include the object code used for ROM data and required In circuit emulators program control data To assemble programs SAMA requires a source file and an auxiliary definition device name def file with device specific information OPENice SLD OPENice SLD Host Interface for In Circuit Emulator is a multi window based debugger for OPENice i500 OPENice SLD provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be easily sized moved scrolled highlighted added or removed HEX2ROM HEX2ROM file generates a ROM code from a HEX file which is produced by the assembler A ROM code is needed to fabricate a microcontroller which has a mask ROM When generating a ROM code OBJ file by HEX2ROM the value FF is automatically filled into the unused ROM area up to the maximum ROM size of the target device ELECTRONICS 15 1 DEVELOPMENT TOOLS S3F84K4 TARGET BOARDS Target boards are available for all S3C8 series microcontrollers All required target system cables and adapters are included with the device specific target board TB84KA is a specific target board for S3F84K4 development IBM PC AT or Compat
57. ANDs the bit 1 value of the source register 0 with the bit 0 value of register R1 destination leaving the value 06H 00000110B in register R1 ELECTRONICS 6 17 INSTRUCTION SET S3F84K4 BCP pit Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison C Unaffected Z Set if the two bits are the same cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H R1 01H 1 gt R1 07H register 01H 01H If destination working register R1 contains the value 07H 000001 11B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register 0D5H ELECTRONICS S3F84K4 INSTRUCTION SET BITC pit Complement BITC Operation Flags Format
58. An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags Format Examples C Set if the bit shifted from the LSB position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 DO R D1 IR Given Register 00H 9AH register 02H 03H register 03H OBCH and C 1 SRA 00H gt Register 00H 0CD C 0 SRA 02H gt Register 02H register 0 In the first example if general register contains the value 9AH 10011010B the statement SRA 00H shifts the bit values in register 00H right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value OCDH 11001101B in destination register 00H ELECTRONICS 6 79 INSTRUCTION SET SRP SRPO SRPI set Register Pointer SRP SIC SRPO SIC SRP1 SIC Operation If src 1 1 and src 0 then If src 1 0 and src 0 1 then If src 1 0 and src 0 Othen RP1 3 TET TT lt S3F84K4 src 3 7 src 3 7 src 4 7 0 src 4 7 1 The source data bits one and zer
59. BD44 ELECTRONICS S3F84K4 PRODUCT OVERVIEW BLOCK DIAGRAM P0 0 ADCO INTO SCL P0 1 ADC1 INT1 SDA P0 2 ADC2 Port I O and Interrupt Control PO 7 ADC7 Timer O SAM8RC CPU ADCO ADC8 3 P2 0 TO NEN BH P2 1 P0 6 PWM lt 4 4 KB ROM B E g P2 6 ADC8 CLO fi NOTE 1 P1 2 is used as input only P1 0 is reserved 2 IVC Internal Voltage Converter is for S3F84K4 s 0 35um process It s not configurable Figure 1 1 Block Diagram ELECTRONICS 1 3 PRODUCT OVERVIEW S3F84K4 PIN ASSIGNMENTS Vss VDD XIN P0 0 ADCO INTO SCL XouT P1 1 PO 1 ADC1 INT1 SDA VPP nRESET P1 2 P0 2 ADC2 P2 0 TO S3F84K4 P0 3 ADC3 P2 1 P0 4 ADC4 20 DIP 300A P2 2 20 SOP 375 P0 5 ADC5 P2 3 P0 6 ADC6 PWM P2 4 P0 7 ADC7 P2 5 P2 6 ADC8 CLO Figure 1 2 Pin Assignment Diagram 20 Pin DIP SOP Package 1 4 ELECTRONICS S3F84K4 Vss XIN XouT P1 1 VPP nRESET P1 2 P2 0 TO P2 1 P2 2 P2 3 S3F84K4 16 DIP 300A PRODUCT OVERVIEW VDD P0 0 ADCO INTO SCL P0 1 ADC1 INT1 SDA P0 2 ADC2 P0 3 ADC3 P0 4 ADC4 PO 5 ADC5 P0 6 ADC6 PWM Figure 1 3 Pin Assignment Diagram 16 Pin DIP Package ELECTRONICS 1 5 PRODUCT OVERVIEW S3F84K4 PIN DESCRIPTIONS Table 1 1 S3F84K4 Pin Descriptions Input Pin Description Pin Output Type P0 0 P0 7 y o Bit programmable I O port for Schmitt trigger input or ADCO ADC7 push pull output Pull up resistors are assignable by INTO INT 1 software
60. C LABEL_W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair 00H and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3F84K4 JR Jump Relative JR Operation Flags Format Example cc dst If cc is true PC PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Given The carry flag 2 1 and LABEL X 1FF7H JR C LABEL_X gt PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the sta
61. CTION SET INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 AO RR A1 IR Given RO 1AH R1 02H register 02H OFH and register 03H OFFH INCW RRO gt RO 1AH R1 03H INCW R1 gt Register 02H 10H register 00H In the first example the working register pair RRO contains the value 1AH in register RO and 02H in register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value 03H in register R1 In the second example the statement INCW R1 uses Indirect Register IR addressing mode to increment the contents of general register 03H from OFFH to OOH and register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP INOCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3F84K4 IRET Interrup
62. DB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 47 Rb 0 NOTE Inthe second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and general register OOH 05H LDB R0 00H 2 gt RO LDB 00H 0 R0 gt RO 07H register 00H 05H 06H register OOH 04H In the first example destination working register RO contains the value 06H and the source general register 00H the value 05H The statement LD R0 00H 2 loads the bit two value of the OOH register into bit zero of the RO register leaving the value 07H in register RO In the second example OOH is the destination register The statement LD 00H 0 R0 loads bit zero of register RO to the specified bit bit zero of the destination register leaving 04H in general register 00H ELECTRONICS 6 51 INSTRUCTION SET LDC LDE Load Memory LDC LDE Operation Flags Format 10 dst src dst lt src S3F84K4 This instruction l
63. DRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points Program Memory to start fo 4 bit working register block dst Working Register gt dt Point to the ADDRESS Address Working Register etg LL GN Value used in OPERAND mr Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES S3F84K4 INDIRECT REGISTER ADDRESSING MODE Concluded Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points to start of working register block Program Memory 4 bit Working Register Address Register Next 2 bit Point Pair NNN RE NN References either Register Pair Program Memory or 1 of 4 Data Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in Instruction OPERAND Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS S3F84K4 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can
64. H 1EH register 02H 03H SUB 01H 02H SUB 01 90 SUB 01H f65H Register 01H 17H register 02H 03H Register 01H 91H C S and V 1 Register 01H OBCH C 5 1 V 0 EE EE In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 ELECTRONICS S3F84K4 SWAP SWAP Operation Flags Format Examples Swap Nibbles dst dst 0 3 dst 4 7 INSTRUCTION SET The contents of the lower four bits and upper four bits of the destination operand are swapped 7 4 43 0 t C Undefined Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Hex opc dst 2 4 FO FI Given Register 00H 3EH register 02H 03H and register O3H QA4H SWAP 00H gt Register OOH OE3H SWAP 02H gt Register 02H 03H register 03H 4AH Addr Mode dst R IR In the first example if general register contains the value 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the 00H register leaving the value OESH 11100011B ELECTRONICS 6 83 INSTRUCTION SET S3F84K4 TCM rest Complement U
65. ICS 3 11 ADDRESSING MODES S3F84K4 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory Next Instruction LSB Must be Zero es urren Instruction gt OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS S3F84K4 ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform condi
66. INSTRUCTION SET LDC LDE Load Memory LDC LDE Continued Examples Given RO 11H R1 34H R2 01H R3 04H Program memory locations 0103H 4FH 0104H 1A 0105H 6DH and 1104H 88H External data memory locations 0103H 5FH 0104H 2AH 0105H 7DH and 1104H 98H LDC R0 RR2 RO lt contents of program memory location 0104H RO R2 01H 04H LDE RO GRR2 RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H LDC nete RR2 RO 11H contents of RO is loaded into program memory location 0104H RR2 working registers RO R2 R8 no change LDE RR2 RO 11H contents of RO is loaded into external data memory location 0104H RR2 working registers RO R2 R8 no change LDC R0 201H RR2 RO contents of program memory location 0105H 01H 4 RR2 RO 6DH R2 01H 04H LDE R0 01H RR2 RO contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H R3 04H LDC nete 401H RR2 RO 11H contents of RO is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 RO 11H contents of RO is loaded into external data memory location 0105H 01H 0104H LDC R0 1000H RR2 RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H 04H LDE R0 1000H RR2 RO contents of external data memory location 1104H 1000H 0104H RO 98H R2 0
67. ION SET S3F84K4 SB1 Select Bank 1 SB1 Operation BANK lt 1 The SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3C8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented 6 76 ELECTRONICS S3F84K4 INSTRUCTION SET SBC subtract with Carry SBC dst src Operation dst lt dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Flags C Set if a borrow occurred src dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always s
68. In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register 6 46 ELECTRONICS S3F84K4 INSTRUCTION SET JP Jump JP JP Operation Flags Format 1 Examples cc dst Conditional dst Unconditional If cc is true PC lt dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC No flags are affected Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 ccD DA cc 2 0to F opc dst 2 8 30 IRR NOTES 1 The 3 bvte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL W gt LABEL 1000H PC 1000H JP 00H gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP
69. Initiated by a RESET ELECTRONICS 13 7 ELECTRICAL DATA S3F84K4 Table 13 7 A D Converter Electrical Characteristics TA 259 to 85 Vpp 2 0 V to 5 5 V Vss 0 V Parameter Symbol Test Conditions Min Typ Max Unit Total accuracy Vpp 5 12 V 3 LSB CPU clock 8 MHz Vsg OV Integral linearity error Differential linearity DLE 1 error Offset error of top Offset error of bottom m tcon fosc 8 MHz time 1 Analog input VIAN voltage Analog input impedance Analog input TADIN Vpp 25M 10 HA current Analog block lape Vpp 5V current 2 Vop 3V Vpp 5 Moon SY power down mode NOTES 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 lang is operating current during A D conversion 13 8 ELECTRONICS S3F84K4 ELECTRICAL DATA Table 13 8 LVR Circuit Characteristics TA 25 Low voltage reset VLVR MAX VLVR VLVR MIN Figure 13 5 LVR Reset Timing ELECTRONICS 13 9 ELECTRICAL DATA S3F84K4 NOTES 13 10 ELECTRONICS S3F84K4 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3F84K4 is available in a 20 pin DIP package Samsung 20 DIP 300A a 20 pin SOP package Samsung 20 SOP 375 a 20 pin SSOP package Samsung 20 SSOP 225 a 16 pin DIP package Samsung 16 DIP 300A a 16 pin SOP package Samsung 16 SOP BD300 SG a 16 pin SSOP package Samsung 16 SSOP BD44 Package dimensions are sho
70. Mode Operation Mode Normal Mode or coe Power Down Mode 1 RESET Operation Figure 8 3 Timing for S3F84K4 after RESET ELECTRONICS 8 3 RESET and POWER DOWN S3F84K4 POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 200 uA except that the LVR Low Voltage Reset is enable All system functions are halted when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by an nRESET signal or by an external interrupt Using RESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to High level All system and peripheral control registers are then reset to their default values and the contents of all data registers are retained A Reset operation automatically selects a slow clock fosc 16 because CLKCON 3 and CLKCON 4 are cleared to 00B After the oscillation stabilization interval has elapsed the CPU executes the system initialization routine by fetching the 16 bit address stored in ROM locations 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Clock related external interrupts cannot be used External interrupts INTO INT1 i
71. Name Mnemonic Funcion PWM data registers PWMDATA F2H 6 bit PWM basic cycle frame value PWMEX 6 bit extension stretch value PWM control registers PWMCON F3H PWM counter stop start resume and Fosc clock settings PWM function Description The PWM output signal toggles to Low level whenever the lower 6 bit counter matches the reference value stored in the module s data register PWMDATA If the value in the PWMDATA register is not zero an overflow of the lower counter causes the PWM output to toggle to High level In this way the reference value written to the data register determines the module s base duty cycle The value in the 6 bit extension counter is compared with the extension settings in the 6 bit extension data register PWMEX This 6 bit extension counter value together with extension logic and the PWM module s extension register is then used to stretch the duty cycle of the PWM output The stretch value is one extra clock period at specific intervals or cycles see Table 16 2 If for example the value in the extension register is 04H the 32nd cycle will be one pulse longer than the other 63 cycles If the base duty cycle is 50 96 the duty of the 32nd cycle will therefore be stretched to approximately 51 duty For example if you write 80H to the extension register all odd numbered pulses will be one cycle longer If you write FCH to the extension register all pulses will be stretched by one cyc
72. OR BXOR dst src Bit XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS S3F84K4 Mnemonic Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI EI IDLE NOP RCF SBO SB1 SCF SRP SIC SRPO SIC SRP1 SIC STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode INSTRUCTION SET S3F84K4 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions two others FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instruc
73. OR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location GROD c Branch to the service routine specified by the concatenated 16 bit vector address NOTE A 16 bit vector address always begins at an even numbered ROM address within the range of 00H FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends execute DI restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the
74. Oscillator External RC Oscillator Smart Option 3F 1 0 in ROM Stop Instruction Oscillator Stop Selected OSC Oscillator Wake up Noise Filter CLKCON 7 INT Pin CLOCK CIRCUIT CLKCON 4 3 CPU Clock P2 6 CLO P2CONH 6 4 NOTE Anexternal interrupt with RC delay noise filter can be used to release stop mode and wake up the main oscillator In the S3F84K4 the INTO INT1 external interrupts are of this type ELECTRONICS Figure 7 4 System Clock Circuit Diagram CLOCK CIRCUIT S3F84K4 NOTES 7 4 ELECTRONICS S3F84K4 RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW By smart option 3EH 7 in ROM user can select internal RESET LVR or external RESET When using internal RESET LVR nRESET pin P1 2 can be used by normal I O pin The S3F84K4 can be RESET in four ways by external power on reset by the external nRESET input pin pulled low by the digital watchdog peripheral timing out by Low Voltage Reset LVR During an external power on reset the voltage at Vpp is High level and the nRESET pin is forced to Low level The nRESET signal is an input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This brings the S3F84K4 into a known operating status To ensure correct start up the user should take care that nRESET signal is not released before the Vnp level is sufficient to allow MCU operation at the chosen freq
75. REGISTER ADCON The A D converter control register ADCON is located at address F7H ADCON has four functions Bits 7 4 select an analog input pin ADCO ADCS Bit 3 indicates the status of the A D conversion Bits 2 1 select a conversion speed Bit 0 starts the A D conversion Only one analog input channel can be selected at a time You can dynamically select any one of the nine analog input pins ADCO ADCS by manipulating the 4 bit value for ADCON 7 ADCON 4 A D Converter Control Register ADCON F7H R W 1 A D Conversion input pin selection bits Conversion start bit 0 No effect 1 A D conversion start ADCO P0 0 ADCI P0 1 P0 2 ADC3 P0 3 ADCA P0 4 5 PO 6 PO 7 P2 6 PO Conversion speed selection bits 00 fosc 16 fosc 8 MHz 01 fosc 8 fosc 8 MHz 10 fosc 4 fosc 8 MHz 11 fosc 1 fosc 4 MHz ADC5 P0 5 ADG6 P0 6 ADG7 PO 7 ADCS P2 6 L Invalid Selection End of conversion ECO status bit 0 A D conversion is in progress 1 A D conversion complete 1 Maximum ADC clock input 4 MHz 2 Do NOT set ADCON 7 4 to any value of the Invalid Selection Figure 12 1 A D Converter Control Register ADCON 12 2 ELECTRONICS S3F84K4 A D CONVERTER INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain
76. RQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Read only IR IRQ1 bi IRQ2 IRQ3 IROS IRQ4 IRQ6 IRQ7 Interrupt level request pending bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ 5 12 ELECTRONICS S3F84K4 INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routin
77. ULT MULT LD RRI IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 x r2 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x ri A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 r1 Irr2 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r1 Irr2 RR2 RR1 IRZ RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irr r2 RA r2 lrr1 IA1 IR1 IM Ir1 r2 HR HR LDCD LDCI LD LD LD LDC R1 IR1 r1 Irr2 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 lrri r2 lrri IRR1 IR2 R1 DA1 r2 Irri xs ELECTRONICS S3F84K4 INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX ELECTRONICS 6 11 INSTRUCTION SET CONDITION CODES S3F84K4 The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes 0000 1000 0111 1111 note note 0110 note 1110 note 1101 0101 0100 1100 0110
78. ack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3F84K4 PUSH Push To Stack PUSH Operation Flags Format Examples SIC SP SP 1 QSP src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH OAAH SPH OOH and SPL OOH PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value 0000H and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3F84K4 INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example dst src IR IR 1 dst lt src This instruction is used to address user defined stacks in the register
79. al TBDATA LUGO TB Buffer Register fxx 256 TBCON 2 fxx 64 Comparator fxx 8 MUX fxx TBCNT R TBCON 5 4 S3F84K4 P2 0 TO P2CONL 1 0 TACON O Pending TACON 1 Low TBCON 1 TBCON O Pending Clear TBCON 3 NOTE When TACON 7 is 0 two 8 bit timer A B Figure 10 9 Timer A and B Function Block Diagram 10 14 ELECTRONICS S3F84K4 BASIC TIMER and TIMER 0 NOTES ELECTRONICS 10 15 S3F84K4 12 BIT PWM 1 1 12 BIT PWM PULSE WIDTH MODULATION OVERVIEW This microcontroller has the 12 bit PWM circuit The operation of all PWM circuit is controlled by a single control register PWMCON The PWM counter is a 12 bit incrementing counter It is used by the 12 bit PWM circuits To start the counter and enable the PWM circuits you set PWMCON 2 to 1 If the counter is stopped it retains its current count value when re started it resumes counting from the retained count value When there is a need to clear the counter you set PWMCON 3 to 1 You can select a clock for the PWM counter by set PWMCON 6 7 Clocks which you can select are Fosc 256 Fosc 64 Fosc 8 Fosc 1 FUNCTION DESCRIPTION PWM The 12 bit PWM circuits have the following components 6 bit comparator and extension cycle circuit 6 bit reference data registers PWMDATA 6 bit extension data registers PWMEX PWM output pins P0 6 PWM PWM counter The PWM counter is a 12 bit incrementing counter comprised of a
80. al operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH R W Global interrupt enable bit Always logic 0 0 Disable all interrupts processing Fast interrupt level 1 Enable all interrupts processing selection bits Fast interrupt enable bit 0 Disable fast interrupts processing 1 Enable fast interrupts processing Not used for the S3F84K4 i mi k O0O Figure 5 5 System Mode Register SYM 5 8 ELECTRONICS S3F84K4 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask register IMR DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH R W IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt level enable bit 0 Disable mask interr
81. anying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a Reset In other words during normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a Reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a Reset or when Stop mode has been released by an external interrupt In Stop mode whenever a Reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of 557 4096 for Reset or at the rate of the preset clock source for an external interrupt When BTCNT 7 is set a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when Stop mode is released 1 During Stop mode an external power on Reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts 2 lf an external power on Reset occurred the basic timer c
82. atement TM RO R1 tests bit one in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET S3F84K4 WFI wait for Interrupt WFI Operation Flags Format Example The CPU is effectively halted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex opc 1 4n 3F 1 2 3 The following sample program structure shows the sequence of operations that follow WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS S3F84K4 INSTRUCTION SET XOR Logical Exclusive OR XOR dst src Operation dst lt dst src The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a 0 bit is stored Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is se
83. ation 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS S3F84K4 INSTRUCTION SET RL Rotate Left RL Operation dst C lt dst 7 dst 0 lt dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags Format Examples C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 91 IR Given Register 00H OAAH register 01H 02H and register 02H 17H RL OOH gt Register OOH 55H C 1 RL 01H gt Register 01H 02H register 02H 2EH C 0 In the first example if general register OOH contains the value OAAH 10101010B the statement RL 00H rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 71 INSTRUCTION SET S3F84K4 RLC Rotate Left Through Carry RLC Operation dst dst 0 lt C C lt dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left o
84. ber and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when you execute the SB1 in
85. c timer counter BTCNT can be cleared during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers for both the basic timer input clock and the timer 0 clock you write a 1 to BTCON O Basic Timer Control Register BTCON R W Divider clear bit for basic timer and timer 0 0 No effect 1 Clear both dividers Watchdog timer enable bits 1010B Disable watchdog function Other value Enable watchdog function Basic timer counter clear bits 0 No effect 1 Clear basic timer counter Basic timer input clock selection bits 00 fosc 4096 01 fosc 1024 10 fosc 128 11 Invalid selection NOTE When you write a 1 to BTCON 0 or BTCON 1 the basic timer divider or basic timer counter is cleared The bit is then cleared automatically to 0 Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS S3F84K4 BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a Reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watchdog function A Reset clears BTCON to 00H automatically enabling the watchdog timer function A Reset also selects the oscillator clock divided by 4096 as the BT clock A Reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accomp
86. crements the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3F84K4 INSTRUCTION SET Reset Carry Flag RCF Operation Flags Format Example RCF C c 0 The carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 CF Given C 2 1 or 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 69 INSTRUCTION SET S3F84K4 RET return RET Operation Flags Format Example PC OSP SP e SP 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Given SP OOFCH SP 101AH and PC 1234 RET gt PC 101AH SP 00FEH The statement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at loc
87. e Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3F84K4 interrupt structure no interrupt belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register ELECTRONICS 5 13 INTERRUPT STRUCTURE S3F84K4 INTERRUPT SOURCE POLLING SEQUENCE The dme 4 interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowl
88. e relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F84K4 DA pecimal Adjust DA dst Operation dst lt DA dst Instruction Carry Before DA 0 0 0 ADD 0 ADC 0 0 1 1 1 0 SUB 0 SBC 1 1 Flags C INSTRUCTION SET The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Bits 4 7 Value Hex 0 9 0 8 0 9 A F 9 F A F 0 2 0 2 0 3 0 9 0 8 7 F 6 F H Flag Before DA O Oj O O O O O Bits 0 3 Value Hex 0 9 A F 0 3 0 9 A F 0 3 0 9 A F 0 3 0 9 6 F 0 9 6 F Number Added to Byte 00 06 06 60 66 66 60 66 66 00 00 FA 06 AO 60 9A 66 Set if there was a carry from the most significant bit cleared otherwise see table Set if result is 0 cleared otherwise Set if result bit 7 is set cleared otherwise Unaffected Unaffected Format Z S V Undefined D H ELECTRONICS dst Bytes 2
89. e changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001 110B ELECTRONICS 6 29 INSTRUCTION SET S3F84K4 CP Compare CP Operation Flags Format Examples dst src dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison C Set if a borrow occurred src dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 2 4 A2 r r src 6 A3 r Ir opc src dst 3 6 A4 R R A5 R IR opc dst src 3 6 A6 R IM 1 Given R1 02H and R2 03H CP R1 R2 gt Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination wor
90. e next instruction is executed If three or more NOP instructons are not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F Example The instruction IDLE stops the CPU clock but not the system clock NOP NOP NOP ELECTRONICS 6 43 INSTRUCTION SET S3F84K4 INC Increment INC Operation Flags Format Examples dst dst lt dst 1 The contents of the destination operand are incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst r 0toF opc dst 2 4 20 R 21 IR Given RO 1BH register 00H OCH and register 1BH OFH INC RO gt RO 1CH INC OOH gt Register OOH ODH INC BRO gt RO 1BH register 01H 10H In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register OOH assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H ELECTRONICS S3F84K4 INSTRU
91. e statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B 6 20 ELECTRONICS S3F84K4 INSTRUCTION SET BITS pit set BITS Operation Flags Format Example dst b dst b lt 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITS R13 gt R1 OFH If working register R1 contains the value 07H 000001 11B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111B ELECTRONICS 6 21 INSTRUCTION SET S3F84K4 BOR BOR BOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 OR src b or dst b lt dst b OR sre 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opc
92. ed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 92 R IR Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H gt Register 00H 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement POPUD 02H 200H loads the contents of register 42H into the destination register 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3F84K4 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst lt src IR lt IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H 900H gt Register OOH 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination general register 02H The user st
93. edge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The 1 2 3 4 CPU then initiates an interrupt machine cycle that completes the following processing sequence Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to process the next interrupt request ELECTRONICS S3F84K4 INTERRUPT STRUCTURE GENERATING INTERRUPT VECT
94. er register mont ecu Jojojojojojojojo Timer B data register TBDATA EDH RW 111111 Timer B controlregister TBCON een RW j j ojojo ojojo Location FOH is not mapped PWM extension data register FH RW Joljojojojojol l I PWM data register PWMDATA Fen RW l l Jojojojojojo RW ojo o o ojo o RW Jololojojolojojo om n OR F Locations FAH FCH are not mapped External memory timing register FE Interrupt priority register IR NOTE Not mapped or not used x undefined H H ofo RW jo t 8 6 ELECTRONICS S3F84K4 RESET and POWER DOWN G PROGRAMMING TIP Sample S3F84K4 Initialization Routine ORG 0000H lt lt Smart Option gt gt ORG 003CH DB OFFH DB OFFH DB OFFH DB OFEH d lt lt Interrupt Vector Address gt gt VECTOR 2 PWMOVF INT VECTOR TIMERB VECTOR O0F6H INT TIMERA VECTOR INT EXT1 VECTOR OFCH INT EXTO i lt lt Initialize System and Peripherals gt gt ORG 0100H RESET DI LD BTCON 10100011B LD CLKCON 00011000B LD SPL 0COH LD POCONH 10101010B LD POCONL 10101010B LD POPND 00001010B LD P1CON 00001000B LD P2CONH 01001010B LD P2CONL 10101010B LD IMR 00000111B LD IPR 00010011B lt lt Timer 0 settings gt gt LD TADATA 50H LD TBDATA 50H LD TACON 00000110B LD TBCON 00000110B ELECTRONICS
95. eset 00H PWM input clock PWM 12 bit OVF Interrupt pending bit selection bits 0 No interrupt pending 00 fosc 256 0 Clear pending condition when write 01 fosc 64 1 Interrupt is pending 10 fosc 8 11 fosc 1 PWM counter interrupt enable bit 0 Disable PWM OVF interrupt Not used for S3F84K4 1 Enable PWM OVF interrupt PWM counter enable bit 0 Stop counter 1 Start resume countering PWM counter clear bit 0 No effect 1 Clear the 12 bit up counter Figure 11 3 PWM Capture Module Control Register PWMCON ELECTRONICS 11 5 12 BIT PWM S3F84K4 fOSC 64 fOSC fOSC 256 fOSC 8 PWMCON 6 7 From 6 bit up counter 11 6 From 6 bit up counter 5 0 6 bit 6 bit PWMCON 0 PWMCON 1 PWMCON 2 1 When PWMDATA gt Counter 0 When PWMDATA lt Counter 6 bit C mum O P0 6 PWM MDATA Counter 6 bit Data Extension Buffer Control Logic Extension Data Buffer 6 bit PWM Data Register F2H PWMCON 3 clear 6 bit up counter overflow DATA BUS 7 0 Figure 11 4 PWM Capture Module Functional Block Diagram 11 6 ELECTRONICS S3F84K4 12 BIT PWM PROGRAMMING TIP Programming the PWM Module to Sample Specification ORG 0000H ammen lt lt Smart Option gt gt ORG 003CH DB OFFH DB OFFH DB OFFH DB OFEH jamne lt lt Interrupt Vector Address gt gt VECTOR OF2H INT PWM lt lt Initialize System and Peripherals gt gt
96. esponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3F84K4 INSTRUCTION SET TM Test Under Mask TM Operation Flags Format Examples dst src dst AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir opc src dst 3 6 74 R R 75 R IR opc dst src 3 6 76 R IM Given RO 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM RO R1 TM RO ORI TM 00H 01H TM 00H 01H RO 0C7H 1 02H 2 0 RO OC7H R1 02H register 02H 23H Z 0 Register 00H 2BH register 01H 02H Z 0 Register 00H 2BH register 01H 02H register 02H 23H Z 0 TM 00H f54H gt Register 00H 2BH Z 1 m EN m E In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the st
97. et to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src 6 33 r Ir opc src dst 3 6 34 R R 35 R IR opc dst src 3 6 36 R IM Examples Given R1 10H R2 03H C 1 register 01H 20H register 02H 03H and register 03H OAH SBC R1 R2 gt R1 OCH R2 03H SBC R1 R2 gt R1 05H R2 03H register O3H OAH SBC 01H 02H gt Register 01H 1CH register 02H 03H SBC 01H 02H gt Register 01H 15H register 02H 03H register O3H 0AH SBC 01H 428AH gt Register 01H 95H C S and V 1 In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 77 INSTRUCTION SET S3F84K4 SCF set Carry Flag SCF Operation Flags C Format Example C 1 The carry flag C is set to logic one regardless of its previous value Set to 1 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 DF The statement SCF sets the carry flag to logic one ELECTRONICS S3F84K4 INSTRUCTION SET SRA shift Right Arithmetic SRA Operation dst dst 7 s dst 7 C lt dst 0 dst lt dst n 1 0 6
98. format Control register descriptions are arranged in alphabetical order according to register mnemonic More information about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this manual ELECTRONICS 4 1 CONTROL REGISTERS S3F84K4 Table 4 1 System and Peripheral Control Registers address mw 7 5 2 1 FTinerAcounterregister maon om m Jofofofefofo o Timer control register macon bm mw Basic timer controlregister mw o o o o o o o o Clock contolregister acon pe Aw o 9 9 System tags register mass mw x x x x x x 9 9 Register Pointer 0 RPO D6H R W 1 1 Location D8H is not mapped r Jojojojojojojojoj RW Jojojojojojojojoj DEH RW jJO x x x O0 0 DFH RW Jolojojolojojojoj System Mode Register Register Page Pointer Interrupt Mask Register NOTE Not mapped or not used x Undefined 4 2 ELECTRONICS S3F84K4 CONTROL REGISTERS Table 4 1 System and Peripheral Control Registers Continued Fr ed eese e m Hex Fordmamgse f me mw Port tdataregister Pm RW l l l l l jolol Port 2 data register 2 RW l Jojojojojolojo Locations E3H E5H are not mapped Port 0 control register High byte POCONH RW Jolojojojojojojo Port
99. he register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F3 Ir r Given RO 7FH R6 21H and R7 OFFH LDCPI RR6 RO RR6 lt RR6 1 7FH contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 00H LDEPI RR6 RO RR6 lt RR6 1 7FH contents of RO is loaded into external data memory location 2200H 21FFH 1H 7FH R6 22H R7 00H ELECTRONICS 6 57 INSTRUCTION SET L DW Load Word LDW Operation Flags Format Examples dst src dst lt src S3F84K4 The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected src dst dst Bytes Cycles Opcode Addr Mode Hex dst src 3 8 C4 RR RR C5 RR IR src 4 8 C6 RR IML Given R4 06H R5 1CH R6 05H R7 02H register 00H 1AH register 01H 02H register 02H 03H and register 03H OFH LDW LDW LDW LDW LDW LDW RR6 RR4 00H 02H RR2 R7 04H 01H RR6
100. he S3F84K4 only uses 003EH and 003FH Not used ROM address 003CH 003DH should be initialized to OFFH The default value of ROM is FFH LVR enable internal RC oscillator ROM Address 003CH Must be initialized to OFFH ROM Address 003DH Must be initialized to OFFH ROM Address 003EH LVR enable disable bit LVR level selection bits Not used 0 Disable 10 2 2v 1 Enable 1123 0v 0 1 3 9v ROM Address 003FH Not used Oscillator selection bits 1 1 External crystal ceramic oscillator 10 External RC NOTES 0 1 Internal RC 1MHz when Voo 5 V 1 When you use external oscillator P1 1 must be set to output 0 0 Internal RC 8MHz when Vpp 5 V port to prevent current consumption 2 The unused bits in must be initialized to 1 Figure 2 2 Smart Option ELECTRONICS 2 3 ADDRESS SPACES 8 PROGRAMMING TIP Smart Option Setting 2 4 ORG 0000H lt lt Smart Option Setting gt gt ORG 003CH DB OFFH DB OFFH DB OFFH DB OFEH lt lt Interrupt Vector Address gt gt VECTOR 0F6H INT TIMERO lt lt Reset gt gt ORG 0100H RESET DI S3F84K4 003CH must be initialized to OFFH 003DH must be initialized to OFFH 003EH enable LVR 3 0v 003FH External RC oscillator Timer 0 interrupt ELECTRONICS S3F84K4 ADDRESS SPACES REGISTER ARCHITECTURE The upper 64 bytes of the S8F84K4 s internal register file are addressed as working registers system control
101. he carry flag C Flags Format Examples C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R 4 E1 IR Given Register 00H 31H register 01H 02H and register 02H 17H RR OOH gt Register 00H 98H C 1 RR 01H gt Register 01H 02H register 02H 8BH C 1 In the first example if general register contains the value 31H 00110001B the statement RR rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3F84K4 RRC Rotate Right Through Carrv RRC Operation dst dst 7 C C lt dst 0 dst n dst n 1 n 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB Flags Format Examples C Set if
102. hmitt trigger input off 5 4 Port 0 P0 6 ADC6 PWM Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Alternative function PWM output 10 Push pull output 1 1 A D converter input ADC6 schmitt trigger input off 3 2 Port 0 PO 5 ADC5 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 10 Push pull output 1 1 A D converter input ADC5 schmitt trigger input off 1 0 Port 0 PO 4 ADCA Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 10 Push pull output 1 1 A D converter input ADC4 schmitt trigger input off Figure 9 3 Port 0 Control Register POCONH High Byte 9 4 ELECTRONICS S3F84K4 I O PORTS Port 0 Control Register Low Byte E7H R W 7 6 Port 0 PO 3 ADC3 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input pull up enable 1 0 Push pull output 1 1 A D converter input ADC3 Schmitt trigger input off 5 4 Port 0 P0 2 ADC2 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input pull up enable 1 0 Push pull output 1 1 A D converter input ADC2 Schmitt trigger input off 3 2 Port 0 PO 1 ADC1 INT1 Configuration Bits 0 0 Schmitt trigger input falling edge interrupt input 0 1 Schmitt trigger input pull up enable falling edge interrupt input 1 0 Push pull output 1 1 A D converter input ADC 1 Schmitt tr
103. ible RS 232C Emulator SMDS2 SMDS2 i Target EPROM Writer Unit Application RAM Break Displav Unit Svstem Probe Adapter Trace Timer Unit TB84K4 SAMS Base Unit Target Board EVA Power Supply Unit Chip Figure 15 1 SMDS2 SMDS2 Product Configuration 15 2 ELECTRONICS S3F84K4 DEVELOPMENT TOOLS TB84K4 TARGET BOARD The TB84K4 target board is used for the S3F84K4 microcontrollers It is supported by the SMDS2 SMDS2 development systems NOTES Don t care about the US It s a test socket only for the chip designer To User Vcc Jon TB84K4 84P4 128 QFP S3E84KO EVA Chip 20 Pin Connector L o c c o Br e e Reserved oh 555 PWM JP4 O OIX TAL om NR EES ON OO JP2 OOO X TAL Socket SMDS SMDS2 Figure 15 2 TB84K4 Target Board Configuration ELECTRONICS 15 3 DEVELOPMENT TOOLS S3F84K4 Table 15 1 Power Selection Settings for TB84K4 To User Vcc Operating Mode Comments Settings To user Vcc The SMDS2 SMDS2 main board supplies Vcc to the TB84K4 External CC off og en Tee Vel target board evaluation chip me and the target system To user Vcc The SMDS2 SMDS2 main board supplies Vcc only to the oe Vcc get board evaluation chip The target system must have its own power supply NOTE The following symbol in the To User Vcc Setting column indicates the electrical short off configuration SMDS2 Selection SAM8 In order to
104. igger input off 1 0 Port 0 PO 0 ADCO INTO Configuration Bits 0 0 Schmitt trigger input falling edge interrupt input 0 1 Schmitt trigger input pull up enable falling edge interrupt input 1 0 Push pull output 1 1 A D converter input ADCO Schmitt trigger input off Figure 9 4 Port 0 Control Register POCONL Low Byte ELECTRONICS 9 5 I O PORTS S3F84K4 Port 0 Interrupt Pending Register E8H R W 7 4 Not used for S3F84K4 3 Port 0 1 ADC1 INT1 Interrupt Enable Bit 0 INT1 falling edge interrupt disable 1 INT1 falling edge interrupt enable 2 Port 0 1 ADC1 INT1 Interrupt Pending Bit 0 No interrupt pending when read 0 Pending bit clear when write 1 Interrupt is pending when read 1 No effect when write 1 Port 0 0 ADCO INTO Interrupt Enable Bit 0 INTO falling edge interrupt disable 1 INTO falling edge interrupt enable 0 Port 0 0 ADCO INTO Interrupt Pending Bit 0 No interrupt pending when read 0 Pending bit clear when write 1 Interrupt is pending when read 1 No effect when write Figure 9 5 Port 0 Interrupt Pending Registers POPND 9 6 ELECTRONICS S3F84K4 I O PORTS PORT 1 Port 1 is a 2 bit I O port with individually configurable pins It can be used for general I O port Schmitt trigger input mode push pull output mode or n channel open drain output mode In addition you can configure a pull up and pull down resistor to individual p
105. imers mode Timer A and B Overview The 16 bit timer 0 is a 16 bit general purpose timer Timer 0 includes interval timer mode using appropriate TACON setting Timer 0 has the following functional components Clock frequency divider fxx divided by 256 64 8 or 1 with multiplexer 16 bit counter TACNT TBCNT 16 bit comparator and 16 bit reference data register TADATA TBDATA Timer 0 match interrupt IRQ1 vector F6H generation Timer 0 control register TACON D2H read write Function Description Interval Timer Function The timer 0 module can generate an interrupt the timer 0 match interrupt TOINT TOINT belongs to the interrupt level IRQ1 and is assigned a separate vector address F6H The TOINT pending condition should be cleared by software after IRQ1 is serviced The TOINT pending bit must be cleared by the application sub routine by writing a 0 to the TACON O pending bit In interval timer mode a match signal is generated when the counter value is identical to the values written to the TO reference data registers TADATA and TBDATA The match signal generates a timer 0 match interrupt T1INT vector F6H and clears the counter If for example you write the value 10H and 32H to TADATA and TBDATA respectively and to TACON the counter will increment until it reaches 3210H At this point the TO interrupt request is generated the counter value is reset and counting resumes ELECTRONICS
106. in SOP and a 20 16 pin SSOP package ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAM8RC CPU core Memory e 4 Kbyte internal program memory e 208 bvte general purpose register area Instruction Set e 78 instructions e Idle and Stop instructions added for power down modes Instruction Execution Time e 500 ns at 8 MHz fosc minimum Interrupts e 3 interrupt levels and 5 interrupt sources 2 external interrupt and 3 internal interrupt e Fast interrupt processing feature General I O e Three I O ports Max 17 pins e Bit programmable ports 12 bit High speed PWM e 12 bit PWM 1 ch e 6 bit base 6 bit extension Built in Reset Circuit e Low voltage detector for safe Reset S3F84K4 Timer Counters e One 8 bit basic timer for watchdog function e One 16 bit timer or two 8 bit timers A B with time interval mode A D Converter e Nine analog input pins MAX e 10 bit conversion resolution Oscillation Frequency e 1 MHz to 8 MHz external crystal oscillator e Typical 4MHz external RC oscillator e Internal RC 8 MHz typ 1 MHz typ at Vpp 5V e Maximum 8 MHz CPU clock Operating Temperature Range e 25 C to 85 C Operating Voltage Range e 2 0Vto 5 5 V LVR disable e LVR to 5 5V LVR enable Smart Option e LVR enable disable e Oscillator selection Package Types e S3F84K4 20 SSOP 225 20 DIP 300A 20 SOP 375 16 SOP BD300 SG 16 DIP 300A 16 SSOP
107. in using control register settings It is designed for high current functions such as LED direct drive P1 1 is used for oscillator output by smart option Also P1 2 is used for RESET pin by smart option NOTE When P1 2 is configured as a general I O port it can be used only for Schmitt trigger input One control register is used to control port 1 P1 CON E9H You address port 1 bits directly by writing or reading the port 1 data register P1 E1H When you use external oscillator P1 1 must be set to output port to prevent current consumption VDD Pull Up Register 50 kO typical Pull up Enable Open Drain Smart option P1 Data o In Out Output Disable input mode Input Data Circuit type A XIN Xour or RESET Pull Down Enable Pull Down Register 50 typical Input Data NOTE I O pins have protection diodes Output through VDD and Vss Figure 9 6 Port 1 Circuit Diagram ELECTRONICS 9 7 I O PORTS S3F84K4 Port 1 Control Register E9H R W 7 Port 1 1 N Channel Open Drain Enable Bit 0 Configure P1 1 as a push pull output 1 Configure P1 1 as a n channel open drain output 6 4 Not used for S3F84K4 3 2 Port 1 P1 1 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input pull up enable 1 0 Output 1 1 Schmitt trigger input pull down enable 1 0 Not used for S3F84K4 When you use external oscillator P1 1 must be set
108. inter is initialized to COH to set upper address of stack to BFH 2 8 ELECTRONICS S3F84K4 ADDRESS SPACES E PROGRAMMING Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD SPL Z0COH SP lt Normally the SP is set to COH by the initialization routine PUSH SYM Stack address 4 SYM PUSH R15 Stack address lt R15 PUSH 20H Stack address OBDH 20H PUSH R3 Stackaddress OBCH R3 POP R3 R3 lt Stack address OBCH POP 20H 20H lt Stack address OBDH POP R15 R15 lt Stack address OBEH POP SYM SYM lt Stack address OBFH ELECTRONICS 2 9 ADDRESS SPACES S3F84K4 NOTES 2 10 ELECTRONICS S3F84K4 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are
109. it NOTE No effect 1 Clear the timer 0 A counter when write 2 Timer 0 A Counter Run Enable Bit Disable Counter Running 1 Enable Counter Running 1 Timer 0 A Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer 0 A Interrupt Pending Bit No interrupt pending when read E Clear pending bit when write Interrupt is pending when read No effect when write NOTE 1 When you write 1 to TACON 3 the Timer 0 A counter value is cleared to 00H Immediately following the write operation the TACON 3 value is automatically cleared to 2 TACON 6 must be always 0 during normal operation ELECTRONICS 4 25 CONTROL REGISTERS S3F84K4 TBCON Timer B Control Register EEH RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W 7 and 6 Not used for the S3F84K4 5 and 4 Timer B Clock Selection Bits fa po mess 7 0 1 fxx 64 1 fxx 8 3 Timer B Counter Clear Bit NOTE No effect 1 Clear the timer B counter when write 2 Timer B Counter Run Enable Bit EI Disable Counter Running Enable Counter Running 1 Timer B Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer B Interrupt Pending Bit No interrupt pending when read Em Clear pending bit when write Interrupt is pending when read No effect when write NOTE When you write a 1 to TBCON 3 the Timer B counter value is cleared to 00H Immediately following the
110. king register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 ELECTRONICS S3F84K4 CPIJE CPIJE Operation Flags Format Example INSTRUCTION SET Compare Increment and Jump on Equal dst src RA If dst src 0 PC PC RA Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 3 12 C2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 03H and register 03H 02H CPIJE R1 R2 SKIP gt R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 0000001 0B to 02H 00000010B Because the result of the c
111. le except the 64th pulse PWM output goes to an output buffer and then to the corresponding PWM output pin In this way you can obtain high output resolution at high frequencies 11 2 ELECTRONICS S3F84K4 12 BIT PWM Table 11 2 PWM output stretch Values for Extension Registers PWMEX PWMEX Bit 1 3 5 7 9 55 57 59 61 63 2 6 10 14 50 54 58 62 4 12 20 44 52 60 8 24 40 56 16 48 32 Not used Not used OH 40H 80H PWM Clock 4MHz OH PWMDATA Register Values 20H 3FH Figure 11 1 12 Bit PWM Basic Waveform ELECTRONICS 11 3 12 BIT PWM PWM Clock 4MHz PWMDATA Register 2H Values 02H B 64th 1st Register Values 1 Extended FT unb vc Ke l Value is 04H gt 750ns Figure 11 2 12 Bit Extended PWM Waveform 32th 64th 7 S3F84K4 ELECTRONICS S3F84K4 12 BIT PWM PWM CONTROL REGISTER PWMCON The control register for the PWM module PWMCON is located at register address F3H PWMCON is used the 12 bit PWM modules Bit settings in the PWMCON register control the following functions PWM counter clock selection PWM data reload interval selection PWM counter clear PWM counter stop start or resume operation PWM counter overflow upper 6 bit counter overflow interrupt control A reset clears all PWMCON bits to logic zero disabling the entire PWM module PWM Control Registers PWMCON F3H R
112. lobally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The EI and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register IMR enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 1 Interrupt Control Register Overview Control Register EEE Function Description Interrupt mask register R W _ Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQO IRQ7 Interrupt priority register Controls the
113. lower 6 bit counter and an upper 6 bit counter To determine the PWM module s base operating frequency the lower byte counter is compared to the PWM data register value In order to achieve higher resolutions the six bits of the upper counter can be used to modulate the stretch cycle To control the stretching of the PWM output duty cycle at specific intervals the 6 bit extended counter value is compared with the 6 bit value bits 7 2 that you write to the module s extension register ELECTRONICS 11 1 12 BIT PWM S3F84K4 PWM data and extension registers PWM duty data registers located in F1H and F2H determine the output value generated by the 12 bit PWM circuit 8 bit data register PWMDATA F2H of which only bits 5 0 are used 8 bit extension registers PWMEX F1H of which only bits 7 2 are used To program the required PWM output you load the appropriate initialization values into the 6 bit data registers PWMDATA and the 6 bit extension registers PWMEX To start the PWM counter or to resume counting you set PWMCON 2 to 1 A reset operation disables all PWM output The current counter value is retained when the counter stops When the counter starts counting resumes at the retained value PWM clock rate The timing characteristic of PWM output is based on the fosc clock frequency The PWM counter clock value is determined by the setting of PWMCON 6 7 Table 11 1 PWM Control and Data Registers Register
114. mple Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3F84K4 BTJRT pit Test Jump Relative on True BTJRT Operation Flags Format Example dst src b If src b is a 1 then PC lt PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 000
115. n Code Basic Timer 8 Bit Counter Clear Bit EN No effect Clear the basic timer counter value 0 Basic Timer Divider Clear Bit ES No effect Clear both dividers NOTE When you write a 1 to BTCON 0 or BTCON 1 the basic timer counter or basic timer divider is cleared The bit is then cleared automatically to O 4 6 ELECTRONICS S3F84K4 CONTROL REGISTERS CLKCON Clock Control Register D4H RESET Value 0 0 0 Read Write R W R W R W 7 Oscillator IRQ Wake up Function Enable Bit lo Enable IRQ for main system oscillator wake up function Disable IRQ for main system oscillator wake up function 6 5 Not used for S3F84K4 4 3 Divided T Selection Bits for CPU Clock frequency Divide by 16 fosc 16 KEN Divide by 8 fosc 8 mE Divide by 2 fosc 2 Non divided clock fosc 2 0 Not used for S3F84K4 ELECTRONICS 4 7 CONTROL REGISTERS S3F84K4 EMT External Memory Timing Register FEH Reset Value 0 1 1 1 1 1 0 Read Write R W R W R W R W R W R W R W 7 External wait Input Function Enable Bit Disable wait input function for external device 1 Disable wait input function for external device 6 Slow Memory Timing Enable Bit Disable slow memory timing Enable slow memory timing 1 5 and 4 Program Memory Automatic Wait Control Bits No wait Wait one cycle Fy Wait two cycles Wait three cycles 3 and 2 Data Memory Automatic Wait Control Bits Wait
116. n because of the floating state in the internal bus Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F Example The statement STOP halts all microcontroller operations NOP NOP NOP ELECTRONICS 6 81 INSTRUCTION SET S3F84K4 SU B subtract SUB Operation Flags Format Examples dst src dst lt dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand C Set if a borrow occurred cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src opc dst l 2 4 22 r r SIC 6 23 r Ir opc src dst 3 6 24 R R 25 R IR opc dst src 3 6 26 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register O3H OAH SUB R1 R2 R1 OFH R2 03H SUB R1 R2 R1 08H R2 03H SUB 01H 02H Register 01
117. n the S3F84K4 interrupt structure meet this criterion Note that when Stop mode is released by an external interrupt the current values in system and peripheral control registers are not changed When you use an interrupt to release Stop mode the CLKCON 3 and CLKCON 4 register values remain unchanged and the currently selected clock value is used If you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must put the appropriate value to BTCON register before entering Stop mode The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In Idle mode CPU operations are halted while select peripherals remain active During Idle mode the internal clock signal is gated off to the CPU but not to interrupt logic and timer counters Port pins retain the mode input or output they had at the time Idle mode was entered There are two ways to release Idle mode 1 Execute a Reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The Reset automatically selects a slow clock fosc 16 because CLKCON 3 and CLKCON 4 are cleared to 00B If interrupts are masked a Reset is the o
118. n the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source S4 Type 2 One level IRQn one vector V4 multiple sources S S Type 3 One level IRQn multiple vectors V4 V multiple sources S4 S5 S4 4 Spam In the S3F84K4 microcontroller two interrupt types are implemented Levels Vectors Sources Type1 IRQn vi Type 2 IRQn NOTES 1 The number of Sn and Vn value is expandable 2 In the S3F84K4 implementation interrupt types 1 and 3 are used Figure 5 1 S3C8 S3F8 Series Interrupt Types 5 2 ELECTRONICS S3F84K4 INTERRUPT STRUCTURE S3F84K4 INTERRUPT STRUCTURE The S3F84K4 microcontroller supports 5 interrupt sources Every interrupt source has a corresponding interrupt address Three interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the p
119. nd lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers Flags C Set if the V flag is set and quotient is between 28 and 29 1 cleared otherwise Z Set if divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Set if quotient is gt 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 03H R2 40H register 40H 80H DIV RRO R2 gt RO 03H R1 40H DIV RRO R2 gt RO R1 20H DIV RRO 20H gt RO 03H R1 80H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 6 38 ELECTRONICS S3F84K4 INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ Operation r dst rsr 1 If r 0 PC PC dst The working register being used as a
120. nder Mask TCM Operation Flags Format Examples 6 84 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir opc src dst 3 6 64 R R 65 R IR opc dst src 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM RO R1 gt RO 0C7H R1 02H 2 1 TCM RO GR1 gt RO 0C7H R1 02H register 02H 23H 2 0 TCM 00H 01H gt Register 00H 2BH register 01H 02H 2 1 gt TCM 00H 01H Register OOH 2BH register 01H 02H register 02H 23H 2 1 TCM 00H 34 gt Register 00H 2BH Z 0 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TCM R0 R1 tests bit one in the destination register for a 1 value Because the mask value corr
121. ndexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES S3F84K4 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte dst src c LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H ldentical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS S3F84K4 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOBI is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRON
122. ne bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Flags Format Examples C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 10 R 4 11 IR Given Register 00H register 01H 02H and register 02H 17H 0 RLC 00H gt Register 00H 54H C 1 RLC Q01H gt Register 01H 02H register 02H 2EH C 0 In the first example if general register 00H has the value OAAH 10101010B the statement RLC 00H rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H leaving the value 55H 01010101B The MSB of register OOH resets the carry flag to 1 and sets the overflow flag ELECTRONICS S3F84K4 INSTRUCTION SET RR Rotate Right RR Operation dst C lt dst 0 dst 7 lt dst 0 dst n lt dst n 1 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces t
123. nly way to release Idle mode 2 Activate any enabled interrupt causing Idle mode to be released When you use an interrupt to release Idle mode the CLKCON 3 and CLKCON 4 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced Following the IRET from the service routine the instruction immediately following the one that initiated Idle mode is executed NOTES 1 Only external interrupts that are not clock related can be used to release stop mode To release Idle mode however any type of interrupt that is internal or external can be used 2 Before enter the STOP or IDLE mode the ADC must be disabled Otherwise the STOP or IDLE current will be increased significantly 8 4 ELECTRONICS S3F84K4 RESET and POWER DOWN HARDWARE RESET VALUES Table 8 1 lists the values for CPU and system registers peripheral control registers and peripheral data registers following a Reset operation in normal operating mode A 1 ora 0 shows the Reset bit value as logic one or logic zero respectively An means that the bit value is undefined following a reset dash means that the bit is either not used or not mapped Table 8 1 Register Values After a Reset Register name RESET value Bit address mw 7 e s s 2 Timer A counter register TACNT pon 0 Timer 0 A control register 2 RW jojo ojoj0 0 Location D2H is
124. ntrolled by IPR settings let you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 S3F8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3F84K4 uses 5 vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the S3F84K4 interrupt structure there are 5 possible interrupt sources When a service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3F84K4 INTERRUPT TYPES The three components of the S3C8 S3F8 interrupt structure described before levels vectors and Sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ i
125. ntrollers use the system stack for subroutine calls and returns and to store data The PUSH and POP instructions are used to control system stack operations The S3F84K4 architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls and interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address is always decremented before a push operation and incremented after a pop operation The stack pointer SPL always points to the stack frame stored on the top of the stack as shown in Figure 2 5 High Address Stack contents Stack contents after a call Low Address after an instruction interrupt Figure 2 5 Stack Operations Stack Pointer SP Register location D9H contains the 8 bit stack pointer SPL that is used for system stack operations After a reset the SPL value is undetermined Because only internal memory space is implemented in the S3F84K4 the SPL must be initialized to an 8 bit value in the range 00H 0COH NOTE In case a Stack Pointer is initialized to 00H it is decreased to FFH when stack operation starts This means that a Stack Pointer access invalid stack area We recommend that a stack po
126. o LSB determine whether to write one or both of the register pointers RPO and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one Flags No flags are affected Format opc SIC Examples The statement SRP 40H Bytes Cycles Opcode Addr Mode Hex src 4 31 IM sets register pointer 0 RPO at location OD6H to 40H and register pointer 1 RP1 at location OD7H to 48H The statement SRPO 50H sets RPO to 50H and the statement SRP1 68H sets RP1 to 68H 6 80 ELECTRONICS S3F84K4 INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the nRESET pin must be held to Low level until the required oscillation stabilization interval has elapsed In application programs a STOP instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after STOP instruction leakage current could be flow
127. oads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes Irr or rr values an even number for program memory odd an odd number for data memory No flags are affected O EL fe a fej a fej 1 o gt o p opc opc opc opc opc d o o o m o 1 n dst src src dst dst 0000 src 0000 opc dst 0001 opc NOTES n gt lt Pc r XL DA DA DA DA gt lt as I XL DA DA DA DA Cycles 10 10 12 12 14 14 14 14 14 14 Opcode Hex C3 D3 E7 F7 A7 B7 A7 B7 A7 B7 Addr Mode dst src r Irr Irr r r XS rr XS rr r r XL rr XL rr r r DA DA r r DA DA r 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 Forformats 3 and 4 the destination address XS rr and the source address XS rr are each one byte 3 For formats 5 and 6 the destination address XL rr and the source address XL rr are each two bytes 4 The DA andr source values for formats 7 and 8 are used to address program memory the second set of values used in formats 9 and 10 are used to address data memory ELECTRONICS S3F84K4
128. ode Addr Mode Hex dst src opc dst 3 6 07 Rb NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H BOR R1 01H 1 gt R1 07H register 01H 03H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 0000001 1B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the second example destination register 01H contains the value 03H 0000001 1B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H in register 01H ELECTRONICS S3F84K4 INSTRUCTION SET BTJRF sit Test Jump Relative on False BTJRF Operation dst src b If src b is a 0 then PC s PC 4 dst The specified bit within the source operand is tested If it is a 0 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed Flags No flags are affected Format Exa
129. of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 R0 JR NZ LOOP ELECTRONICS S3F84K4 INSTRUCTION SET DI Disable Interrupts DI Operation SYM 0 0 Bit zero of the system mode control register SVM O is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 8F Example Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure DI state ELECTRONICS 6 37 INSTRUCTION SET S3F84K4 DIV pivide Unsigned DIV dst src Operation dst src dst UPPER lt REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper a
130. omparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3F84K4 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example dst src RA If dst src 0 RA Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 03H and register 03H 04H CPIJNER1 R2 SKIP gt R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal th
131. one cycle EN Wait two cycles Wait three cycles 1 Stack Area Selection Bit Select internal register file area Select external register file area 0 Not used for the S3F84K4 NOTE The EMT register is not used because an external peripheral interface is not implemented The program initialization routine should clear the EMT register to 00H following a reset Modification of EMT values during normal operation may cause a system malfunction 4 8 ELECTRONICS S3F84K4 CONTROL REGISTERS FLAGS Svstem Flags Register D5H Bit Identifier Reset Value Read Write Addressing Mode ELECTRONICS E xm rou aj a a ES X X X X X X 0 0 R W R W R W R W R W R W R R W Register addressing mode only Carry Flag C o Operation does not generate a carry or borrow condition Operation generates a carry out or borrow into high order bit 7 Zero Flag Z o Operation result is a non zero value Operation result is zero Sign Flag S Operation generates a positive number MSB 0 1 Operation generates a negative number MSB 1 Overflow Flag V Operation result is lt 127 or 128 Operation result is gt 127 or lt 128 Decimal Adjust Flag D Add operation completed Subtraction operation completed Half Carry Flag H Lo No carry out of bit 3 or no borrow into bit 3 by addition or subtraction Addition generated carry out of bit 3 or subtraction generated borrow into bit 3 Fast Inte
132. onnect the oscillation source to the on chip clock circuit Simplified external RC oscillator and crystal ceramic oscillator circuits are shown in Figures 7 1 and 7 2 When you use external oscillator P1 1 must be set to output port to prevent current consumption Vcc R XIN S3F84K4 S3F84K4 XOUT Figure 7 1 Main Oscillator Circuit Figure 7 2 Main Oscillator Circuit RC Oscillator with Internal Capacitor Crystal Ceramic Oscillator MAIN OSCILLATOR LOGIC To increase processing speed and to reduce clock noise non divided logic is implemented for the main oscillator circuit For this reason very high resolution waveforms square signal edges must be generated in order for the CPU to efficiently process logic operations ELECTRONICS 7 1 CLOCK CIRCUIT S3F84K4 CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect clock oscillation as follows n Stop mode the main oscillator freezes halting the CPU and peripherals The contents of the register file and current system register values are retained Stop mode is released and the oscillator started by a reset operation or by an external interrupt with RC delay noise filter for S3F84K4 INTO INT1 n Idle mode the internal clock signal is gated off to the CPU but not to interrupt control and the timer The current CPU status is preserved including stack pointer program counter and flags Data in the register file is retained
133. ould select the group relationship B gt C gt A The setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows IPR 5 controls the relative priorities of group C interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C IPR O controls the relative priority setting of IRQO and IRQI interrupts 5 10 ELECTRONICS S3F84K4 INTERRUPT STRUCTURE Interrupt Priority Register IPR FFH R W Group priority D7 D4 0 IRQO gt IRQ1 1 IRQ1 gt IRQO Undefined Group B B gt C gt A 0 IRQ2 gt IRQ3 IRQ4 A gt B gt C 1 IRQ3 IRQ4 gt IRQ2 B gt A gt C Subgroup B C gt A gt B 0 IRQ3 gt IRQ4 C gt B gt A 1 IRQ4 gt IRQ3 A gt C gt B Group C Undefined 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Figure 5 8 Interrupt Priority Register IPR ELECTRONICS 5 11 INTERRUPT STRUCTURE S3F84K4 INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to I
134. ounter will increase at the rate of f95c 4096 If an external interrupt is used to release Stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 7 of the basic timer counter is set When a BTONT 7 is set normal CPU operation resumes Figure 10 2 and 10 3 shows the oscillation stabilization time on RESET and STOP mode release ELECTRONICS 10 3 BASIC TIMER and TIMER 0 S3F84K4 Oscillation Stabilization Time Normal Operating mode Reset Release Voltage trst RC Internal 1 U U U eset Release Oscillator X OUT Oscillator Stabilization Time 1 1 10000000B 00000000B tWAIT 4096x128 fosc gt Basic timer increment and CPU operations are IDLE mode NOTE Duration of the oscillator stabilization wait time t WAIT when it is released by a Power on reset is 4096 x 128 fosc tRsT 7 RC R and C are value of external power on Reset Figure 10 2 Oscillation Stabilization Time on RESET 10 4 ELECTRONICS S3F84K4 Normal STOP Mode Operating Mode STOP Instruction Execution External Interrupt Release Signal Oscillator X OUT BASIC TIMER and TIMER 0 Oscillation Stabilization Time Normal Operating Mode STOP Mode Release Signal 10000000B 00000000B tWAIT tH Basic Timer Increment NOTE Duration of the oscillator stabilzation wait time t WAIT it is released by
135. procedure above to some extent INSTRUCTION POINTER IP The instruction pointer IP is adopted by all the S3C8 S3F8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair DAH and DBH The names of IP registers are IPH high byte IP15 IP8 and IPL low byte IP7 IPO FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles To select a specific interrupt level for fast interrupt processing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 ELECTRONICS 5 15 INTERRUPT STRUCTURE S3F84K4 FAST INTERRUPT PROCESSING Continued Two other system registers support fast interrupt processing The instruction pointer IP contains the starting address of the service routine and is later used to swap the program counter values and When a fast interrupt occurs the contents of the FLAGS register are stored in an unmapped dedicated register called FLAGS FLAGS prime NOTE For the S3F84K4 microcontroller the service routine for any one of the eight interrupt levels IRQO IRQ7 can be selected for fast interrupt processing PROCEDURE FOR INITIATING FAST INTERRUPTS To initiate fast interrupt processing follo
136. r MSB 419 R Read only W Write only R W Read write Not used bit settings Description of the effect of specific RESET value notation Not used x Undetermind value 0 Logic zero Bit number MSB Bit 7 LSB Bit 0 Figure 4 1 Register Description Format ELECTRONICS S3F84K4 CONTROL REGISTERS ADCON A D Converter Control Register F7H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 4 A D Converter Input Pin Selection Bits o ojo opjApco Poo 0 J 0 0 0 1 AD P 0 0 0 0 pojojij ojADO2 PO2 0 5 0 0 1 1 ADC3 P03 o o 1 o 0 ADC4 P0 4 0 1 0 1 ADOS POU5 5 5 5 JADC6 PO 4 4 0 1 1 1 JADOZ PO 0 0 0 0 0 C1 o o ance P26 3 End of Conversion Status Bit 0 A D conversion is in progress o y O 2 1 Clock Source Selection Bit note 0 0 fosc 16 fosc 8 MHz p 1 o fosc fosc lt 4 MHz 0 Conversion Start Bit ELECTRONICS o Nomeaning A D conversion start NOTE Maximum ADC clock input 4 MHz CONTROL REGISTERS S3F84K4 BTCON Basic Timer Control Register D3H RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 4 Watchdog Timer Function Enable Bit aojo Disable watchdog timer function Others Enable watchdog timer function 3 2 Basic Timer Input Clock Selectio
137. r and a 16 bit general purpose timer called timer 0 Basic Timer BT You can use the basic timer BT in two different ways As a watchdog timer to provide an automatic Reset mechanism in the event of a system malfunction To signal the end of the required oscillation stabilization interval after a Reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider fosc divided by 4096 1024 or 128 with multiplexer 8 bit basic timer counter BTCNT FDH read only Basic timer control register BTCON D3H read write Timer 0 The 16 bit timer 0 is used in one 16 bit timer or two 8 bit timers mode When TACON 7 is set to 1 itis in one 16 bit timer mode When TACON 7 is set to 0 the timer 0 is used as two 8 bit timers One 16 bit timer mode Timer 0 Two 8 bit timers mode Timer A and B ELECTRONICS 10 1 BASIC TIMER and TIMER 0 S3F84K4 BASIC TIMER BT BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function A Reset clears BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of fosc 4096 To disable the watchdog function you must write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON 4 The 8 bit basi
138. r R1 the value 2AH the statement OR RO R1 logical ORs the RO and H1 register contents and stores the result SFH in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS S3F84K4 INSTRUCTION SET POP Pop From Stack POP Operation Flags Format Examples dst dst lt ESP SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 50 R 51 IR Given Register OOH 01H register 01H 1BH SPH 0D8H OOH SPL OD9H OFBH and stack register OFBH 55H POP 00H gt Register 00H 55H SP 00FCH POP 00H gt Register 00H 01H register 01H 55H SP 00FCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location OOFBH 55H into destination register OOH and then increments the stack pointer by one Register 00H then contains the value 55H and the SP points to location OOFCH ELECTRONICS 6 63 INSTRUCTION SET S3F84K4 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst lt src IR IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location address
139. r enable bit ADCON O The read write ADCON register is located at address F7H During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 7 4 in the ADCON register To start the A D conversion you should set a the enable bit ADCON 0 When a conversion is completed ACON 3 the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATA register where it can be read The A D converter then enters an idle state Remember to read the contents of ADDATA before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the ADC does not use sample and hold circuitry it is important that any fluctuations in the analog level at the ADCO ADC8 input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to circuit noise will invalidate the result ELECTRONICS 12 1 A D CONVERTER S3F84K4 USING A D PINS FOR STANDARD DIGITAL INPUT The ADC module s input pins are alternatively used as digital input in port 0 and P2 6 A D CONVERTER CONTROL
140. r run enable bit 0 Disable counter running 1 Enable counter running Timer 0 operation mode selection bit 0 Two 8 bit timers mode Timer A B 1 One 16 bit timer mode Timer 0 Timer 0 counter clear bit 0 No affect 1 Clear the timer 0 counter when write NOTE TACON 6 must be always 0 during normal operation Figure 10 4 Timer 0 Control Register TACON 10 8 ELECTRONICS S3F84K4 Compare Value TBDATA TADATA Up Counter Value TBCNT TACNT 00H Count start TACON 2 1 Counter Clear TACON 3 Interrupt Request TACON 0 TO Match Output P2 0 Figure 10 5 Timer 0 Timing Diagram ELECTRONICS Match Match Match Match Match Match Match TBDATA TADATA BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 S3F84K4 BLOCK DIAGRAM fxx 256 fxx 64 16 Bit Up Counter Read Only lt TBCNT TACNT gt anna P2 0 TO P2CONL 1 0 Counter Clear Signal Match Signal Timer 0 Data Register Read Write lt TBDATA TADATA gt NOTE When TACON 7 is 1 16 bit timer 0 Figure 10 6 Timer 0 Functional Block Diagram 10 10 ELECTRONICS S3F84K4 BASIC TIMER and TIMER 0 TWO 8 BIT TIMERS MODE TIMER A and B OVERVIEW The 8 bit timer A and B are the 8 bit general purpose timers Timer A and B support interval timer mode using appropriate TACON and TBCON setting respectively Timer A and B have the following functional components Clock frequency divider with multiplexer
141. rea That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages However because the S3F84K4 uses only page 0 you can use the common area for any internal data operation The Register R addressing mode can be used to access this area Registers are addressed either as a single 8 bit register or as a paired 16 bit register In 16 bit register pairs the address of the first 8 bit register is always an even number and the address of the next register is an odd number The most significant byte of the 16 bit data is always stored in the even numbered register the least significant byte is always stored in the next 1 odd numbered register n Even address Figure 2 4 16 Bit Register Pairs G PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Examples 1 LD 0C2H 40H Invalid addressing mode Use working register addressing instead LD R2 40H R2 C2H lt the value in location 40H 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead ADD R3 45H R3 C3H lt 45 ELECTRONICS 2 7 ADDRESS SPACES S3F84K4 SYSTEM STACK S3C8 series microco
142. relative processing priorities of the interrupt levels The eight levels of S3F84K4 are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode register SYM R W _ This register enables disables fast interrupt processing and dynamic global interrupt processing NOTE All interrupts must be disabled before IMR register is changed to any value Using DI instruction is recommended ELECTRONICS 5 5 INTERRUPT STRUCTURE S3F84K4 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM 0 Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information El S Q Interrupt Request Register Read only nRESET R IRQO IRQ7 Interrupts Interrupt Prioritv Vector Register Interrupt Cvcle
143. rogram counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed Levels Vectors Sources Reset Clear RESET 100H Basic timer overflow FOH External interrupt 0 IRQO FAH External interrupt 1 c F6H Timer 0 A match interrupt IRQ1 Timer B match interrupt IRQ2 F2H PWM overflow interrupt NOTE External interrupts are triggered by a falling edge Figure 5 2 S3F84K4 Interrupt Structure ELECTRONICS 5 3 INTERRUPT STRUCTURE S3F84K4 Interrupt Vector Addresses All interrupt vector addresses for the S3F84K4 interrupt structure is stored in the vector address area of the first 256 bytes of the program memory ROM You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses The program reset address in the ROM is 0100H Decimal 4 095 4K byte Program Memory Area 100H lt Reset FFH Address Interrupt Vector Address Area Figure 5 3 ROM Vector Address Area 5 4 ELECTRONICS S3F84K4 INTERRUPT STRUCTURE Enable Disable Interrupt Instructions EI DI Executing the Enable Interrupts El instruction g
144. rrupt Status Flag FIS EN Interrupt return IRET in progress when read Fast interrupt service routine in progress when read Bank Address Selection Flag BA Lo Bank 0 is selected Bank 1 is selected CONTROL REGISTERS S3F84K4 I IMR Interrupt Mask Register DD Reset Value X X X X X X X x Read Write R W R W R W R W R W R W R W R W 7 Interrupt Level 7 IRQ7 0 Disable mask 1 Enable unmask 6 Interrupt Level 6 IRQ6 Disable mask 1 Enable unmask 5 Inte rupt Level 5 IRQ5 Disable mask 1 Enable unmask 4 Interrupt Level 4 IRQ4 Disable mask 1 Enable unmask 3 Interrupt Level 3 IRQ3 Disable mask je Enable unmask 2 Interrupt Level 2 IRQ2 Disable mask Je Enable unmask 1 Interrupt Level 1 IRQ1 Disable mask fel Enable unmask 0 Interrupt Level 0 IRQO Disable mask 1 Enable unmask NOTE When an interrupt level is masked the CPU does not recognize any interrupt requests that may be issued 4 10 ELECTRONICS S3F84K4 CONTROL REGISTERS IPH instruction Pointer High Byte DAH Reset Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer
145. s H PC SP 20 00 110 Routine 21 IPL 50 sr Memory 22 Data Memory Stack ELECTRONICS 6 41 INSTRUCTION SET S3F84K4 EXIT Exit EXIT Operation Flags Format Example Address IP PC SP 20 21 22 6 42 IPH Data Stack IP lt ESP SP lt 2 lt IP IP lt 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack The diagram below shows one example of how to use an EXIT statement Before After Address Data IP 0052 Data Address Data PC 0060 PCL old PCH 60 Main SP 0022 Exit 00 50 22 Data Memory Stack ELECTRONICS S3F84K4 INSTRUCTION SET IDLE Operation IDLE Operation The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation In application programs a IDLE instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before th
146. s decremented by one R8 R6 10H R7 32H RR6 RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt HRR6 1 R8 ODDH R6 10H R7 32H ELECTRONICS S3F84K4 INSTRUCTION SET LDCI LDEI Load Memorv and Increment LDCI LDEI Operation Flags Format Examples dst src dst lt src rr rr 4 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes even for program memory and odd for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory locations 1033H OCDH and 1034H OC5H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 RR6 1
147. set Value 0 X X X 0 0 Read Write R W R W R W R W R W R W 7 Tri state External Interface Control Bit 1 Normal operation disable tri state operation Set external interface lines to high impedance enable tri state operation 6 5 Not used for the SSF84K4 4 2 Fast Interrupt Level Selection Bits 2 1 Fast Interrupt Enable Bit 3 Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit 4 EN Disable all interrupt processing Enable all interrupt processing NOTES 1 Because an external interface is not implemented SYM 7 must always be 0 2 You can select only one interrupt level at a time for fast interrupt processing 3 Setting SYM 1 to 1 enables fast interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 4 Following a reset you must enable global interrupt processing by executing an EI instruction not by writing a 1 to SYM 0 4 24 ELECTRONICS S3F84K4 CONTROL REGISTERS TACON Timer 0 A Control Register D2H Bit Identifier 7 6 5 4 2 1 0 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W 7 Timer 0 Operating Mode Selection Two 8 bit timers mode Timer A B 1 One 16 bit timer mode Timer 0 Must be always 0 5 4 Timer 0 A Clock Selection Bits 0 fxx 256 1 fxx 64 0 fxx 8 fxx e e l l 3 Timer 0 A Counter Clear B
148. ster an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Chapter 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Chapter 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET Mnemonic Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI Operands dst dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst dst src dst src src dst src dst src S3F84K4 Table 6 1 Instruction Group Summary Instruction Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre decrement Load program memory with pre decrement Load external data memory with pre increment Load program memory with pre increment Load word Pop from stack Pop user stack decrementing Pop
149. ster names locations and addressing characteristics Data registers for ports 0 2 have the structure shown in Figure 9 1 Table 9 2 Port Data Register Summary NOTE Areset operation clears the P0 P2 data register to 00H I O Port n Data Register n 0 2 Figure 9 1 Port Data Register Format 9 2 ELECTRONICS S3F84K4 I O PORTS PORT 0 Port 0 is a bit programmable general purpose I O ports You can select normal input or push pull output mode In addition you can configure a pull up resistor to individual pins using control register settings It is designed for high current functions such as LED direct drive Part 0 pins can also be used as alternative functions ADC input external interrupt input and PWM output Three control registers are used to control Port 0 POCONH E6H POCONL E7H and POPND E8H You access port 0 directly by writing or reading the corresponding port data register PO EOH Pull up Pull up register Enable 50 typical POCONH PWM PO Data Output Disable input mode Input Data External Interrupt Input To ADC NOTE 1 0 pins have protection diodes Input Data put Figure 9 2 Port 0 Circuit Diagram ELECTRONICS 9 3 I O PORTS S3F84K4 Port 0 Control Register High Byte E6H R W 7 6 Port PO 7 ADC7 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 10 Push pull output 1 1 A D converter input ADC7 sc
150. struction ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION S3F84K4 Table 6 2 Flag Notation Conventions O Z S V D H 0 1 Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode ELECTRONICS S3F84K4 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Condition code See list of condition codes in Table 6 6 Working register only Rn n 0 15 Bit b of working register Rn b n 2 0 15 b 0 7 Bit 0 LSB of working register Rn n 2 0 15 Working register pair RRp p 0 2 4 14 Register or working register reg or Rn reg 0 255 n 0 15 Bit b of register or working register reg b reg 0 255 b 0 7 Register pair or working register pair reg or RRp reg 0 254 even number only where p 0 2 14 Indirect addressing mode addr addr 0 254 even number only Indirect working register only Rn n 0 15 Indirect register or indirect working register Rn or Greg reg 0 255 0 15 Indirec
151. t cleared otherwise V Always reset to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 6 r Ir opc src dst 3 6 B4 R R B5 R IR opc dst src 3 6 B6 R IM Examples Given RO 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR RO R1 gt RO OC5H R1 02H XOR RO QGRHR1 gt RO OE4H R1 02H register 02H 23H XOR 00H 01H gt Register 00H 29H register 01H 02H gt gt XOR 00H 01H Register OOH 08H register 01H 02H register 02H 23H XOR 00H 454H Register 00H 7FH In the first example if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement XOR R0 R1 logically exclusive ORs the R1 value with the RO value and stores the result 0C5H in the destination register RO ELECTRONICS 6 87 INSTRUCTION SET S3F84K4 NOTES 6 88 ELECTRONICS S3F84K4 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW By smart option 3FH 0 in ROM user can select internal oscillator or external oscillator When using external RC oscillator or internal RC oscillator XOUT P1 1 can be used as normal I O pins An internal RC oscillator source provides a typical 8 MHz or 1 MHz at Vpp 5 V depending on smart option An external RC oscillation source provides a typical 4 MHz clock for S3F84K4 An external crystal or ceramic oscillation source provides a maximum 8 MHz clock The and pins c
152. t Return IRET IRET Normal IRET Fast Operation FLAGS SP PC o IP SP lt SP 1 FLAGS lt FLAGS PC OSP FIS 0 SP lt SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine Flags All flags are restored to their original settings that is the settings before the interrupt occurred Format IRET Bytes Cycles Opcode Hex Normal opc 1 10 internal stack BF 12 internal stack IRET Bvtes Cvcles Opcode Hex Fast opc 1 6 BF Example In the figure below the instruction pointer is initiallv loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normallv is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH 100H Interrupt Service Routine JP to FFH FFFFH NOTE
153. t be connected between Vpp and Vss when data in the flash ROM are read or written by a tool SPW2 Gang Writer Vpp Vss Vpp Vss E 20 date 16 16 pin Logic power supply pin 20 pin ie pin ELECTRONICS 1 7 PRODUCT OVERVIEW S3F84K4 PIN CIRCUITS VDD P channel IN IN oe gt 0 gt 4 N channel Figure 1 5 Pin Circuit Type A Figure 1 6 Pin Circuit Type B VDD Pull up Enable Out Data S B Fu Circuit utput Disable Output Disable Digital Input Figure 1 7 Pin Circuit Tvpe C Figure 1 8 Pin Circuit Tvpe D 1 8 ELECTRONICS S3F84K4 PRODUCT OVERVIEW Open drain Enable Pull up P2CONH enable P2CONL OQ Alternative Output O P2 X O Output Disable Input Mode Digital Input Analog Input Enable ADC Figure 1 9 Pin Circuit Type E Pull up enable POCONH OQ Alternative Output O PO x Output Disable Input Mode Digital Input Interrupt Input Analog Input Enable ADC Figure 1 10 Pin Circuit Type E 1 ELECTRONICS 1 9 PRODUCT OVERVIEW Output Disable Input Mode Digital Input XIN XOUT Open drain Figure 1 11 Pin Circuit Type E 2 S3F84K4 Pull up enable Pull down enable ELECTRONICS S3F84K4 PRODUCT OVERVIEW NOTES ELECTRONICS 1 11 S3F84K4 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3F84K4 microcontroller has two kinds of address space Internal program memory ROM Internal register file
154. t working register pair only RRp p 0 2 14 Indirect register pair or indirect working RRp or Greg reg 0 254 even only where register pair p 0 2 14 Indexed addressing mode treg Rn reg 0 255 n 0 15 Indexed short offset addressing mode addr RRp addr range 128 to 127 where 0 2 14 Indexed long offset addressing mode addr RRp addr range 0 65535 where p 0 2 14 Direct addressing mode addr addr range 0 65535 Relative addressing mode addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction Immediate addressing mode data data 0 255 Immediate long addressing mode data data range 0 65535 ELECTRONICS 6 9 INSTRUCTION SET S3F84K4 Table 6 5 Opcode Quick Reference OPCODE MAP LOWER NIBBLE HEX DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r0 Rb 1 RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 ri r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r0 Rb 3 JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 b RA 5 POP POP AND AND AND AND AND BITC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ri b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 ri r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r0 Rb PUSH PUSH TM TM TM TM TM BIT R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ri b DECW DECW PUSHUD PUSHUI MULT M
155. tement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS S3F84K4 INSTRUCTION SET L D Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst opc src 2 4 rC r IM 4 r8 r R src opc dst 2 4 r9 R r r OtoF 4 D7 Ir r SIC dst 3 E4 R R E5 R IR opc dst src 3 6 E6 R IM D6 IR IM opc src dst 3 6 F5 IR R op 6 ELECTRONICS 6 49 INSTRUCTION SET LD Load LD Continued Examples Given RO 01H R1 register 02H 02H LO LD RO 10H gt LD R0 01H gt LD 01H RO gt LD R1 RO gt LD RO R1 gt LD 00H 01H gt LD 02H 00H gt LD 00H 0AH gt LD 00H 10H gt LD 00H 02H gt LD RO LOOP R1 gt LD LOOP RO R1 gt Uo AH register 00H 01H register 01H 20H 30H and register OFFH RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 OAH register 01H OAH Register 00H 20H register 01H 20H Register 02H 20H register 00H 01H Register OOH OAH Register OOH 01H register 01H 10H S3F84K4 Register 00H 01H register 01H 02 register 02H 02H RO OFFH R1 0AH Register 31H OAH RO 01H R1 OAH ELECTRONICS S3F84K4 INSTRUCTION SET L
156. terrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the El instruction Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 9F Example Given SYM 00H EI If the SYM register contains the value OOH that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts SYM 0 is the enable bit for global interrupt processing 6 40 ELECTRONICS S3F84K4 INSTRUCTION SET ENTER Enter ENTER Operation Flags Format Example SP lt 5 2 QSP lt IP IP lt lt IP IP lt IP 2 This instruction is useful when implementing threaded code languages contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 14 1F The diagram below shows one example of how to use an ENTER statement Before After Address Data IP Address Data 40 Enter 1F 41 Address H 01 42 Address L 10 43 Address H Data Enter 1F Address H 01 Address L 10 Addres
157. the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3F84K4 ADC Add with carry ADC Operation Flags Format Examples dst src dst dst src c The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 6 13 r Ir opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Given Ri 10H R2 C flag 1 register 01H 20H register 02H and register OAH ADC R1 R2 gt R1 14H R2
158. the only way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing an El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends 5 16 ELECTRONICS S3F84K4 INTERRUPT STRUCTURE NOTES ELECTRONICS 5 17 S3F84K4 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8RC instruction set is specifically designed to support the large register files that are typical of most SAMB microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide No special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual regi
159. tional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE TX Program Memory Address Used PC Value Current Instruction OPCODE Signed oe Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES S3F84K4 IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD RO0 0AAH Figure 3 14 Immediate Addressing 3 14 ELECTRONICS S3F84K4 ADDRESSING MODES NOTES ELECTRONICS 3 15 S3F84K4 CONTROL REGISTERS CONTROL REGISTERS OVERVIEW In this section detailed descriptions of the S3F84K4 control registers are presented in an easy to read format These descriptions will help familiarize you with the mapped locations in the register file You can also use them as a quick reference source when writing application programs System and peripheral registers are summarized in Table 4 1 Figure 4 1 illustrates the important features of the standard register description
160. tions such as AND OH XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H R W Bank address Carry flag C status flag BA Fast interrupt Zero flag 2 status flag FIS Sign flag S Half carry flag H Overflow flag V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS S3F84K4 INSTRUCTION SET FLAG DESCRIPTIONS C FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive num
161. to output port to prevent current consumption Figure 9 7 Port 1 Control Register P1CON 9 8 ELECTRONICS S3F84K4 I O PORTS PORT 2 Port 2 is a 7 bit I O port with individually configurable pins It can be used for general I O port Schmitt trigger input mode push pull output mode or N channel open drain output mode You can also use some pins of port 2 as ADC input CLO output and TO match output In addition you can configure a pull up resistor to individual pins using control register settings It is designed for high current functions such as LED direct drive You address port 2 bits directly by writing or reading the port 2 data register P2 E2H The port 2 control registers 2 and P2CONL is located at addresses EAH EBH respectively Pull up Pull up register Enable 9 3 50 typical Open Drain P2CONH L CLO TO P2 Data Output Disable input mode Input Data Circuit Type A NOTE I O pins have protection diodes input Data through VDD and Vss P Figure 9 8 Port 2 Circuit Diagram ELECTRONICS 9 9 I O PORTS S3F84K4 Port 2 Control Register High Byte EAH R W 7 Not used for S3F84K4 6 4 Port 2 P2 6 ADC8 CLO Configuration Bits 0 0 0 Schmitt trigger input pull up enable 0 0 1 Schmitt trigger input 0 1x ADC input 100 Push pull output 1 0 1 Open drain output pull up enable 1 10 Open drain output 1 1 1 Alternative function CLO output 3 2 Port 2
162. trical characteristics are presented in tables and graphs Absolute maximum ratings D C electrical characteristics A C electrical characteristics Input timing measurement points Oscillator characteristics Oscillation stabilization time Operating voltage range Schmitt trigger input characteristics Data retention supply voltage in stop mode Stop mode release timing when initiated by a RESET A D converter electrical characteristics LVR circuit characteristics LVR reset timing ELECTRONICS ELECTRICAL DATA S3F84K4 Table 13 1 Absolute Maximum Ratings 25 Parameter Symbol Conditions rating Um Supply voltage imwa omae 0 _ AILO pins active ME ee Output current low lov One I O pin active 13 2 ELECTRONICS S3F84K4 ELECTRICAL DATA Table 13 2 DC Electrical Characteristics TA 25 to 85 Vpp 2 0 to 5 5 V mee emi Wn M wir Input high Vind Ports 0 1 2 and Vpp 2 0 to 5 5 V voltage RESET Input low Vil 4 Ports 0 1 2 and Vpp 2 0 to 5 5 V voltage RESET Output high Vou 11 10 mA Vpp 4 5105 5 V Vpp 1 5 Vpp 0 4 BM Output low Vo 25 mA Vpp 4 5 to 5 5 V leakage current line Input low lity All input except Vn 0V 1 uA leakage current lino Output high All output pins Vout Vpp 2 uA leakage current Output low lo All output pins Voyur 0V 2 uA leakage current Pull
163. uency The nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize The minimum required oscillation stabilization time for a reset is approximately 65 5 ms amp 216 fosc fosc 8 MHz When a reset occurs during normal operation with both Vpp and nRESET at High level the signal at the nRESET pin is forced Low and the Reset operation starts All system and peripheral control registers are then set to their default hardware Reset values see Table 8 1 The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overflow is reached the internal reset will be activated The on chip Low Voltage Reset features static Reset when supply voltage is below a reference value Typ 2 2 3 0 3 9V Thanks to this feature external reset circuit can be removed while keeping the application safety As long as the supply voltage is below the reference value there is an internal and static RESET The MCU can start only when the supply voltage rises over the reference value When you calculate power consumption please remember that a static current of LVR circuit should be added a CPU operating current in any operating modes such as Stop Idle and normal RUN mode ELECTRONICS 8 1 RESET and POWER DOWN S3F84K4
164. upt level 1 Enable un mask interrupt level Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 9 INTERRUPT STRUCTURE S3F84K4 INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA IRQO IRQI GroupB IRQ2 IRQ3 IRQ4 GroupC IRQ5 IRQ6 IRQ7 B21 B22 C21 C22 IRQO IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits w
165. w these steps 1 Load the start address of the service routine into the instruction pointer IP 2 Load the interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register FAST INTERRUPT SERVICE ROUTINE When an interrupt occurs in the level selected for fast interrupt processing the following events occur The contents of the instruction pointer and the PC are swapped The FLAG register values are written to the FLAGS FLAGS prime register The fast interrupt status bit in the FLAGS register is set The interrupt is serviced RON Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register The fast interrupt status bit in FLAGS is cleared automatically D RELATIONSHIP TO INTERRUPT PENDING BIT TYPES As described previously there are two types of interrupt pending bits One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared by the application program s interrupt service routine You can select fast interrupt processing for interrupts with either type of pending condition clear function by hardware or by software PROGRAMMING GUIDELINES Remember that
166. within the range Vss to Vpp Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first bit conversion is always 1 2 Vpp A D Converter Control Register ADCON F7H ADCON 0 ADEN ADCON 7 4 Control Clock ADCON 3 Circuit Selector EOC Flag ADCO PO0 0 ADC1 P0 1 ADC2 P0 2 Successive Approximation Circuit Analog Comparator ADC7 P0 7 ADC8 P2 6 Imxmr 0 4 lt Conversion Result D A Converter ADDATAH ADDATAL F8H F9H To data bus Figure 12 2 A D Converter Circuit Diagram eom T T T LI I2I2 e Figure 12 3 A D Converter Data Register ADDATAH L ELECTRONICS 12 3 A D CONVERTER S3F84K4 ADCON 0 4 1 Conversion Y 50 ADC clock Start ECO ADDATA Privious i Value i Set up time 40 clock 10 clock Figure 12 4 A D Converter Timing Diagram CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to step up A D conversion Therefore total of 50 clocks are required to complete an 10 bit conversion With an 8 MHz CPU clock frequency one clock cycle is 500 ns 4 fosc If each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits step up time 10 clock 50 clocks 50 clock x 500 ns 25 us at 8 MHz 1 clock time 4 fosc assuming ADCON 2 1
167. wn in Figure 14 1 14 2 14 3 14 4 14 5 and 14 6 20 DIP 300A O 6 40 0 20 26 80 MAX 26 40 0 20 5 08 MAX o N EN 3 30 0 30 NOTE Dimensions are in millimeters Figure 14 1 20 DIP 300A Package Dimensions ELECTRONICS 14 1 MECHANICAL DATA S3F84K4 10 30 0 30 7 50 0 20 0 85 0 20 13 14 MAX 12 74 0 20 2 50 MAX e e H e N A 010 WAX NOTE Dimensions are in millimeters Figure 14 2 20 SOP 375 Package Dimensions ELECTRONICS S3F84K4 MECHANICAL DATA 20 SSOP 225 6 40 0 20 4 40 0 10 0 50 0 20 6 90 MAX 6 50 40 20 1 85 MAX o o H e 5070 WAX NOTE Dimensions are in millimeters Figure 14 3 20 SSOP 225 Package Dimensions ELECTRONICS 14 3 MECHANICAL DATA S3F84K4 gt 16 DIP 300A O 6 40 0 20 19 80 MAX 19 40 0 20 1 0 46 40 10 x lt gt 1 50 0 10 4 0 38 MIN 3 30 0 30 NOTE Dimensions are in millimeters Figure 14 4 16 DIP 300A Package Dimensions 14 4 ELECTRONICS S3F84K4 MECHANICAL DATA NOTE Dimensions are in millimeters Figure 14 5 16 SOP BD300 SG Package Dimensions ELECTRONICS 14 5 S3F84K4 MECHANICAL DATA 16 SSOP BD44 4 40 0 10 0 173 0 004 0 10 0 15 0 05 0 004 0 006 0 002 pHa 6 40 0 20 0 252 0 008 0 50 0 20 0 019 0 008 6 50 0 10
168. write operation the TBCON 3 value is automatically cleared to 0 4 26 ELECTRONICS S3F84K4 CONTROL REGISTERS NOTES ELECTRONICS 4 27 S3F84K4 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 S3F8 series interrupt structure has three basic components levels vectors and sources The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and I O blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQO IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3F84K4 interrupt structure recognizes three interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic co
169. write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a switch as follows Otherwise the program memory writing function is not available Table 15 2 The SMDS2 Tool Selection Setting SWi Seting Operating Mode SMDS mo SMDS2 R W SMDS2 15 4 ELECTRONICS S3F84K4 DEVELOPMENT TOOLS Table 15 3 Using Single Header Pins to Select Clock Source and Enable Disable PWM JP4 X TAL Clock Source Use SMDS2 SMDS2 internal clock source as the system clock JP4 X TAL HH Clock Source Use external crystal or ceramic oscillator as the system clock PWM function is DISABLED PWM function is ENABLED SW2 o T e mlu M ON High Default NOTE 1 For EVA chip smart option is determined by DIP Switch not software 2 Please keep the reserved bits as default value high Reserved Figure 15 3 DIP Switch for Smart Option ELECTRONICS 15 5 DEVELOPMENT TOOLS XIN XOUT P1 1 RESET P1 2 TO P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 1351208 did Nid 02 VDD P0 0 ADCO INTO P0 1 ADC1 INT1 P0 2 ADC2 P0 3 ADC3 P0 4 ADC4 P0 5 ADC5 P0 6 ADC6 PWM P0 7 ADC7 P2 6 ADC8 CLO Figure 15 4 20 Pin Connector for TB84K4 Target Board N I gt Q o Target System Figure 15 5 S3F84K4 Probe Adapter for 20 DIP Package J012euuo Uld 0Z S3F84K4 ELECTRONICS

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