DE2 Development and Education Board User Manual
Contents
1. cd root altera 13 1 hld board terasic deSnet host linux64 driver there are source code makefile and readme txt to locate at the driver source code directory and type make_all to compile and generate the new driver Before that user need to install the kernel related development package matched the current kernel kernel devel package via issuing yum install kernel devel command E Test aocl program Command In the Linux terminal type cd root altera 13 1 hld board terasic tests blank to go to blank OpenCL project folder then type aocl program blank aocx to configure the FPGA of DES NET with blank aocx OpenCL image Firstly the programmer will try to configure the FPGA of DES NET through PCI Express CvP Configuration via Protocol If the CvP is not found the programmer will extract reprogram_temp sof from the blank aocx and try to use reprogram_temp sof to configure the FPGA through USB Blaster as shown in Figure 3 7 It is normal for the programmer can t find CvP at first time because the startup configuration on flash of DES NET does not contain required CvP Periphery image file Next section will show how to use aocl flash command to write a CvP enabled startup configuration on flash DE5 Net OpenCL 23 www terasic com ter CT rea www terasic com root localhost blank aocl program blank aocx aocl program Running reprogram from root altera 13 1 hld board terasic deSnet li2. 2012 they can use the trial version of Visual Studio 2012 Express The software can be downloaded from the web site http www microsoft com en us download details aspx 1d 34673 DE5 Net OpenCL 5 www terasic com asie PET www terasic com NOS RYA UNIVERSITY PROGRAM E DES NET OpenCL SDK After Quartus II and OpenCL SDK are installed copy the whole terasic folder in Terasic OpenCL Kit into the folder C altera 13 1 hld board where assumed Quartus IT is installed on the folder C Altera 13 1 Figure 2 1 shows file folder content when terasic folder is copied er Si in C altera 131 Hild board Organize Include in library Share with Burn New folder Vin Er Name Date modified Type BE Desktop de chsoc 12 30 2013 1 38 PM File folder Ja Downloads de pcie385n 12 30 2013 1 38 PM File folder E Recent Places i s5pho 12 30 2013 1 38 PM File folder 12 30 2013 1 45 PM File folder al Libraries al Ninermante 4 items Figure 2 1 Copy Terasic Folder to hid bolard Folder 2 2 OpenCL License Installation An OpenCL license is required for Altera OpenCL SDK to compile any OpenCL projects successfully Developers can purchase the OpenCL license from either Altera or Terasic Assuming that developers have obtained a license file with the filename license dat and it is saved in the local disk with the file path such as c license dat The license can then be set u
3. JA DTE RA ES Administrator Command Prompt e md Microsoft Windows Nerzion 66 1 7601 Copyright tc 2009 Microsoft Corporation All rights reserved CiXUsers remote LABI1 gt cd C sers remote LAB11 Desktop app_aocx blank CC Users renmote LAEB11 Desktop app_aocx blankiaocl program blank aocx aocl program Running reprogram from C altera 13 1 hld board teras ic deSnet uin dows64 bin Given SOF reprogram_temp sof Given RBF none gt Given core HBF reprogram_temp core rbf UDG _DriverOpen success UDG _PcisScanDevices success Programming this device H Vendor ID bx1172 Device ID BxABBO Bus 1 Slot B Function Selected bus 1 slot B function Reading 4096 bytes of conf igurat ion space data WDC _PciReadCfgqByS lot succes WDC PciGetDbewvicelInfo eco WDC PcibevicEOpen success PCle to fabric read test failed read HxfFFFFFFff Hot doing CuP on FPGA with version below ii UDO DriverOpen success Running quartus_pgm c 1 m jtag o F ireprogram_temp s0f Info Info Running Quartus II 32 bit Programmer Info Version 13 1 8 Build 162 1872372813 SJ Full Version Info Copyright lt C3 1991 2613 Altera Corporation All rights reserved Info Your use of Altera Corporation s design tools logic functions Info and other software and tools and its AMPP partner logic Info functions and any output Files from any of the foregoing Info including device programming or simulation files and any Info a
4. OpenCL Download and install instructions If you have not installed the Quartus Il software 1 Download the Quartus software and device support and the Altera SDK for OpenCL into a temporary directory 2 Run the QuartusSetup 13 1 0 162 run file All software and components downloaded into the same temporary directory are automatically installed Hf you have installed the Quartus Il software 1 Download the Altera SDK for OpenGL into a temporary directory 2 Run the AGCL Setup 13 10 162 run file Akera FPGA Design Software Quartus Il Software includes Nios ll EDS UPDATE Sire 1 8 GB MDS FAATDBA6BC428 AA GT AL Cyclone V device support includes all variations O Site 010 4 MB MDS 0758 CE BEC FF SCA Stratix V device support includes all variations Size 19 GB MDS B3975AB190C4C47C Altera SDK for OpenCL requires FPGA Design Software Altera SDK for Open CL Size ME MDS E11 F56 Tee Figure 3 2 OpenCL Linux version download Quartus II software uses the built in USB Blaster II drivers on Linux to access USB Blaster II asic DE5 Net OpenCL 18 www terasic com aad ast July Ta 2014 download cable on DES Net but after installed the Quartus II software with built in drivers User need to change the port permission for USB Blaster II via issuing gedit etc udev rules d 5 1 usbblaster rules to create and add the following lines to the etc udev rules d 51 usbblaster rules file USB Bla
5. 13 The execute file is generate in the same directory which named boardtest_host 28 www terasic com July 7 2014 DE5 Net OpenCL www terasic com root localhost altera 1L3 1L hld board terasic tests boardtest OVX Elle Edit View Terminal Tabs Help root localhost boardtest aocl program boardtest aocx aocl program Running reprogram from root altera 13 1 hld board terasic deSnet linux64 bin Device aclo Given SOF reprogram temp sof Given RBF null Given core RBF reprogram temp core rbf Saving PCI control registers of the board PCIe to fabric read test passed Starting CvP reprogramming of the device with 33677312 bytes of data PCIe to fabric read test passed Uniphys are calibrated CvP worked Restoring PCI control registers of the board Link is operating as PCIe gen2 x 8 Vendor id x1172 device id xab root localhost boardtest make f Makefile Linux g 34 host main cpp host timer cpp host reorder cpp host memspeed cpp host reorder ocl cpp host hostspeed ocl cpp host hostspeed cpp host aclutil cpp o boardtest host I host DLINUX I root altera 13 1 hld host include L root alt era 13 1 hld linux64 lib L root altera 13 1 hld host linux64 lib lalteracl la lterahalmmd lalterammdpcie lelf lrt lstdc root localhost boardtest Figure 3 13 successful Message for boardtest Host Program build E Test boardtest project Firstly In the terminal type cd root
6. For detailed usage of aoc please refer to the Altera SDK for OpenCL Programming Guide http www altera com literature hb opencl sdk aocl_programming_guide pdf DE5 Net OpenCL 27 www terasic com asie rea www terasic com rootelocalhost altera L3 Ll hid board terasic tests boardtest Ale Edit View Terminal Tabs Help Refer to quartus sh compile log for the output log root localhost boardtest aoc board deSnet a boardtest cl sw dimm partiti on Unused Unused Unused Unused Unused Unused Unused Unused kernel kernel kernel kernel kernel kernel kernel kernel argument argument argument argument argument argument argument argument aoc Selected target board deSnet a7 Warning Warning Warning Warning Warning Warning Warning Warning arg arg arg arg2 src dst arg Estimated Resource Usage Summary hummm ETTI TTT TTT TTT TTT TETTE RE O Resource PO ARE bese see eb eee eee Bee woes La Logic utilization Dedicated logic registers Memory blocks DSP blocks hamssmsz Rs Figure 3 12 aoc boardtest cl OpenCL kernel compile successfully E Compile Host Program In the terminal cd root altera 13 1 hld board terasic tests boardtest and then type type make f Makefile linux to compile the host program When build is successfully you will see successful message as show in Figure 3
7. Microsoft Corporation Llers ion 6 1 7681 1 a All rights reserved C Users remote LABIL1 gt cd C altera 13 1 hld board terasic tests boardtest Unused Unused z Unused Warning Warning Warning Warning Warning Unused Unused Unused Unused Unused kernel kernel kernel kernel kernel kernel kernel kernel arg arg arg argument argument argument argument argument argument argument argument C altera 13 1 hld board terasic tests boardtest gt _ Figure 2 11 aoc boardtest cl OpenCL kernel compile successfully Compile Host Program Visual Studio C C 2012 1s used to compile the Host Program Launch Visual Studio and select menu item FILE Open Project C altera 13 1 hld board terasic tests boardtest host and select boardtest sln as shown Figure 2 12 In the Open Project dialog go to the folder dg Qpen Project Go terasic tests amp boardtest host Le Search host Organize New folder il Date modified Type Marne UF Favorites ME Desktop Pi Downloads Recent Places 10202013 12 01 10202013 Microsoft Wi YC Projec mi boardtest sln Del boardtestvexproj A Libraries Documents al Music Pictures Je Computer E Win Ca Le C on RICHARD F F a RI F Al Project Files sla dan ec File name boardtest sln Cancel Figure 2 12 O
8. Open OpenCL DES Net Jo 4 CE a be eI IAL pe fi art L O O O 0 a O pa Copyright 2003 2013 Terasic Technologies Inc All Rights Reserved UNIVERSITY PROG M pr ro 1 CHAPTER 1 DES NET OPENGL scccicsacccuszsasvecsssasveasdeasscaencanveasaenssecencavteasiuaceontatesteaedsasseuosinaVoucdaeteascesssiasteaessaencaeets 3 LIL SYSTEM REQUIREMENT lan pae igloo 3 DP Fa a0 E e lia 4 CHAPTER 2 OPENCL FOR WINDOW S eeeeecssscecsssscecsssccecossceccsssceccssseccsssecccsssseccsseccccssscecossccccssseesssecccsssceeso 5 2 1 SOFTWARE INSTALLATION sani iii 5 2A OPENCLLIC ENSF INSTALLATION tia RT Aaa 6 L OF ETE EA decsieesmeSopeesaidousueeteatesustedscoisdanitoeniasas 7 LONI PUP iaia iaia 8 25 OPENCL ENVIRONMENT VERIFY AND FLASH CVP aa 8 2 6 COMPILE AND TEST OPENCL PROJECT ccccscceccceccecceccesceccccccceeccsccescsscescesceecesccsscsscescescescesscssesscssesscsscsscescescees 13 CHAPTER 3 OFENCEFOREN lia 17 LESOFT VARE INSTALLATION carini 17 3 2 OPENC L LICENSE INSTALLATION illa 20 OIG ORE a AEEA AE EAEAN AEE A AE A EA AEEA AS 20 OA RD ETU ea E TEE EE a 2 3 5 OPENCL ENVIRONMENT VERIFY AND FLASH CVP essence see ceeceeceeseecececeececcecceecesneseececeecesees 22 3 6 COMPILE AND TEST OPENCL PROIECT L aria a ria a 27 asic DE5 Net OpenCL 2 www terasic com www terasic com July 7 2014 Chapter 1 DE5 Net OpenCL DES NET an unparalleled and powerful platform for h
9. alog as shown in Figure 2 3 type AOCL_BOARD_PACKAGE ROOT in the Variable name edit box and type ALTERAOCLSDKROOT board terasic deSnet in the Variable value edit box 6 In Command Prompt window type aocl install to install PCI Express driver Note that users need to have administrator privileges to install the driver New User Variable Variable name 40CL BOARD PACKAGE ROOT Variable value PeoALTERAOCLSDKEROOT board terasicide 9K J cane Figure 2 3 Setup AOCL BOARD PACKAGE ROOT Environment Variable DE5 Net OpenCL 7 www terasic com asie ENT www terasic com 2 4 Board Setup Before testing OpenCL on DES NET please following below procedures to set up DES NET board on your PC as shown in Figure 2 4 1 Make sure your PC is powered off 2 Insert DES NET board into PCI Express x8 or x16 slot 3 Connect PC s 12V PCI Express 6 pin power source to the DES NET 4 Connect PC s USB port to DES NET mini USB port using an USB cable Note the usb cable can be removed later if OpenCL code had been programming to the startup configuration flash of DES NET by aocl flash command Figure 2 4 Setup DE5 NET board on PC 2 5 OpenCL Environment Verify and Flash CvP This section will show how to make sure the OpenCL environment is setup correctly First please open Command Prompt windows by click Windows Start button clicking All Programs clicking Accessories and then click Command Prom
10. altera I13 1 hid board terasic tests boardtest to go to the boardtest project folder then type aocl program boardtest aocx to configure FPGA with the OpenCL Image boardtest aocx Then launch the compiled Host Program to start boardtest execute file for test In the terminal type boardtest_host Figure 3 14 shows the execution is successful DE5 Net OpenCL 29 www terasic com ter ET ren T www terasic com root localhost altera 13 1L hild board terasic tests boardtest File Edit View Terminal Tabs 18539 10809 10545 16819 10542 10857 10575 10543 mem stream 11213 11300 11300 11300 11301 11273 11300 11275 mem writestream 10406 10612 10405 10615 10375 10614 10400 18377 mem burstcoalesced Kernel mem bandwidth assuming ideal memory 30325 MB s If this is lower than your board s peak memory bandwidth then your kernel s clock isn t fast enough to saturate memory KERNEL TO MEMORY BANDWIDTH 16864 MB s bank did dd e ae a a dd dd dd dad dii a ee ee ce a a GC e o o o e cc 1 Cache Snoop Test a a i oo OM e co e cc OC O Sf i Ci RU Dl Diff i i o Do OA i CC DO Dop Dc o CC MAO Dop De fici Do Dei Di fc i DO Dec Dic OMO DO Di De if o Dl Di De CA CD Dip Dec e ic De Dip Dec Dc ic Di Dei Dec i CRC I De De Hc DU Mi Created Kernel reorder const Min time 28000 Max time 2263838008 Avg time 664442 Finished 4000 iterations with errors SNOOP TEST PASSED root localhost boardtest Figure 3 14 successful M
11. asic com ter ET ren T www terasic com NOS RA 9 UNIVERSITY PROGRAM startup configuration flash of DES NET Before flash programming the programmer will ask users which startup configuration image area will be used as shown in Figure 3 8 This is because DES NET provides two startup configuration image areas called as Factory Image and User Image Typing 1 to select User Image area is recommended root localhost altera L3 L1 hid board terasic tests blank File Edit View Terminal Tabs Help Linux64 bin Couldn t open the device acl Did you load the driver aocl program Program failed root localhost blank aocl flash blank aocx aocl flash Running flash from root altera 13 1l hld board terasic deSnet linux6 4 bin massssssssesessssssssssss Page Selection ssssssssssssssssssssssess Please select the flash page where to store your FPGA configure data 9 Factory Image Location Address 0x00040000 SW2 2 1 Right Position 1 User Image Location Address 0X6020C60000 5W2 2 Left Position Enter a digital number 6 or 1 Or other values to exit the program followed by pressing the Enter key 1 Flash Programming Info oi Info Running Quartus II 64 Bit Convert programming file Info Version 13 1 0 Build 162 10 23 2013 5J Full Version Info Copyright C 1991 2013 Altera Corporation All rights reserved Info Your use of Altera Corporation s design tools logic functions Info and other software a
12. configuration space data UDC_PciWriteCfoqBuslot success Link currently operating at 5 GIs Board max upstream width x Board max upstream speed 5 4 GIs Current upstream status Ox12d4082 Current upstream control 648 Max upstream width x16 Max upstream speed 8 0 GT s Link training completed in 1 ms Link operating at Gen 2 with lanes Expected peak bandwidth 4000 MB s Co Usersrenmote LAB11 Desktop app_aocx blank Figure 2 6 aocl program blank aocx Command DE5 Net OpenCL 10 www terasic com LasiC July 7 2014 www terasic com E Test aocl flash Command In Command Prompt window type cd C altera 13 1 hld board terasic tests blank to go to blank OpenCL project folder then type aocl flash blank aocx to write blank aocx OpenCL image onto the startup configuration flash of DES NET Before flash programming the programmer will ask users which startup configuration image area will be used as shown in Figure 2 7 This is because DES NET provides two startup configuration image areas called as Factory Image and User Image We recommend users to keyin 1 to select User Image area Es Administrator Command Prompt aocl flash blank aocx Par n Microsoft Windows Wersion 6 1 7601 Copyright c 2009 Microsoft Corporation All rights reserved Cc Users remote LABLIScd C salteras 13 1 hld board terasic tests blank C salteras13 1 hld board terasic tests blankiaocl flash blank a
13. ct position developers can power off PC and turn it back on and check whether the blank OpenCL image which 1s CvP enabled configures the FPGA successfully In Command Prompt window type cd C altera 13 1 hld board terasic tests blank to go to blank project folder then type aocl program blank aocx to configure the FPGA with blank aocx OpenCL image If the programing message displays CvP worked as shown in Figure 2 10 it means the blank OpenCL image is programmed into the flash correctly and CvP works well DE5 Net OpenCL 12 www terasic com asie ET www terasic com E Administrator CAWindowstsyster32 cmd exe C altera 13 1 hld board terasic tests blankaocl program blank a0cx aocl program Running reprogram from C altera 13 1 hld board teras ic deSnet win dows64 bin Given SOF reprogram_temp sof Given HBF lt none gt Given core REF reprogram_temp core rbf UDO DriverOpen success UDC_PciScanlDeuices success Programming this device AH Vendor ID bx1172 Device ID BxABOB Bus 1 Slot A Function W Wi 1 slot B function Reading 4096 bytes of configuration space data UDG_PciReadCfgBySlot success UDO _PciGetDevicelnfo success WDC _PcibevicEOpen success PCle to fabric read test passed Starting CuP reprogramming of the device OK to proceed with CuPt Setup is done Starting to write CuP datat INFO Reached the end of the core programming file CuP has finished The Application Layer is rea
14. dy for normal operation Merifying device functionality right after CuP PCle to fabric read test passed Iniphys are calibrated ATO FT Crvaltenast 1 hld boardterasic tests lt blank gt Figure 2 10 aocl program blank aocx use CvP 2 6 Compile and Test OpenCL Project This section will show how to compile and test OpenCL kernel and OpenCL Host Program for the boardtest project Developers can use the same procedures to compile and test other OpenCL examples for DES NET Compile OpenCL Kernel The utility aoc Altera SDK for OpenCL Kernel Compiler is used to compile OpenCL kernel In Command Prompt window type cd C altera 13 1 hld board terasic tests boardtest to go to boardtest project folder then type aoc boardtest cl sw dimm partition to compile the OpenCL kernel It will take about one hour for compiling When the compilation process is finished OpenCL image file boardtest aocx is generated Figure 2 11 is the screenshot when OpenCL kernel is compiled successfully For required parameters to compile boardtest cl please refer to the README txt that is in the same folder as the boardtest cl For detailed usage of aoc please refer to the Altera SDK for OpenCL Programming Guide http www altera com literature hb opencl sdk aocl_programming_guide pdf DE5 Net OpenCL 13 www terasic com Tijasic July 7 2014 www terasic com EES Administrator Command Prompt Microsoft Windows Copyright lt c 2009
15. e Browser File Edit View Go Bookmarks Help 2 Le D 3 Back Up Reload Home Computer Search 18 Location root altera 13 1 nid board are 4x D p DI c5s0c pcie385n sSphq terasic Desktop File System Figure 3 3 Copy Terasic Folder to hid bolard Folder 3 2 OpenCL License Installation An OpenCL license is required to compile the OpenCL projects for Altera OpenCL SDK Developers can purchase the OpenCL license from either Altera or Terasic Assuming that developers have obtained a license file with the filename license dat and it is saved in the local disk with the file path such as root altera 13 1 hld license dat The license can then be set up by creating an environment variable LM _ LICENSE FILE and set its value as root altera 13 1 hld license dat Note that this environment value needs to correspond to the actual license dat file location The next chapter will describe the license environment setting up 3 3 Configure If you install the ALTERA FPGA development software and OpenCL SDK on a system that does not contain any cshrc or Bash Resource file bashrc in your directory you must set the ALTERAOCLSDKROOT and PATH environment variables manually And for Altera OpenCL SDK able to find the kit location of DES NET correctly the developers need to create an environment variable for the DES NET board AOCL BOARD PACKAGE ROOT and set its value as ALTERAOCLSDKROOT boa
16. e for testing Please copy C altera 13 1 hld board terasic tests boardtest host x64 Release boardtest exe to the folder C altera 13 1 hld board terasic tests boardtest In Command Prompt window type cd C altera 13 1 hld board terasic tests boardtest and execute boardtest exe Figure 2 15 is the screen shot when the test is successful E Administrator Command Prompt Launching kernel 2 on accelerator Accelerator 4 reporting status 2 Accelerator 4 is done Launching kernel 2 on accelerator Accelerator 4 reporting status 2 Accelerator 4 is done Launching kernel 2 on accelerator Accelerator 4 reporting status 2 Accelerator 4 is done Launching kernel 2 on accelerator Accelerator 4 reporting status 2 Accelerator 4 is done Launching kernel 2 on accelerator Accelerator 4 reporting status 2 Accelerator 4 is done Launching kernel 2 on accelerator Accelerator 4 reporting status 2 Accelerator 4 is done Launching kernel 2 on accelerator Accelerator 4 reporting status 2 Accelerator 4 is done Min time 166618 Max time 693123000 Avg time 466637 Finished 4000 iterations with 6 errors SNOOP TEST PASSED C altera 13 1 hld board terasic tests hoardtest gt Figure 2 15 boardtest test successfully DE5 Net OpenCL 16 www terasic com TigasiC July 7 2014 www terasic com Chapter 3 OpenCL for Linux This chapter describe how to setup DES NET OpenCL development environmen
17. essage for boardtest test asic DE5 Net OpenCL 30 www terasic com tercoN July T 2014
18. igh speed computation is now officially also an Altera certified board for Altera s Preferred Board Partner Program for OpenCL It supports both 64 bit Windows and Linux This document will introduce you how to setup OpenCL development environment for DES NET board and how to compile and execute the example projects for DES Net Note that OpenCL coding instruction is not in the scope of this document but the user can refer to Altera SDK for OpenCL Programming Guide for more details http www altera com literature hb opencl sdk aoc programming_ guide pdf 1 1 System Requirement The following items are required to set up OpenCL for DES NET board Terasic DES NET Board with two 2GB DDR3 SODIMM installed Host PC with E USB Host Port E One PCI Express x8 x16 slot with 12V power pin E 32GB memory is recommended 24GB is minimal E 2x3 pin 12V Power for DES Net optional An USB Cable type A to mini B 64 bit Windows7 or Linux Installed Altera Quartus II 13 1 Installed licensed is required Altera OpenCL 13 1 Installed license is required Visual Studio 2012 C C installed for Windows7 GNU development tools for Linux Tasic DE5 Net OpenCL 3 www terasic com July 7 2014 www terasic com Note Altera OpenCL only supports 64 bit OS and x86 architecture 1 2 OpenCL Architecture An OpenCL project is composed of both OpenCL Kernel and Host Program as shown in Figure 1 1 OpenCL kernel is compiled with Al
19. nd asic DE5 Net OpenCL 21 www terasic com sterco July Ta 2014 Figure 3 4 Setup DE5 NET board on PC 3 5 OpenCL Environment Verify and Flash CvP This section will show how to make sure the OpenCL environment is setup correctly Firstly please open the Linux system terminal window by right click the Mouse on system desktop then clicking on Open Terminal E Target Board In the Linux terminal type aoc list boards command and make sure deSnet_a7 is listed in Board list as shown in Figure 3 5 root localhost File Edit View Terminal Tabs Help root localhost aoc list boards Board list deSnet a7 root localhost Figure 3 5 debnet_a7 is listed in Board list DE5 Net OpenCL 22 www terasic com ter CT rea www terasic com rootalocalhost altera 13 L hld board terasic tests blank File Edit View Terminal Tabs Help root localhost blank aocl install aocl install Running install from root altera 13 1 hld board terasic deSnet li nux64 bin Using kernel source files from usr src kernels 2 6 18 239 e15 x86 64 make Entering directory usr src kernels 2 6 18 238 e15 xB6 64 Building modules stage 2 MODPOST make Leaving directory usr src kernels 2 6 18 238 e15 x86 64 root localhost blank Figure 3 6 driver installation Note if user don t using the recommended Linux system or different version recompile the driver is needed You can compile it by typing
20. nd tools and its AMPP partner logic Info functions and any output files from any of the foregoing Info including device programming or simulation files and any Info associated documentation or information are expressly subject Info to the terms and conditions of the Altera Program License Figure 3 8 Select Flash Page After selecting the desired flash area it will take about 20 minutes for flash programming Figure 3 9 is the screen shot when flash programming is done successfully DE5 Net OpenCL 23 www terasic com ter CT irta www terasic com root localhost altera 13 1 hid board terasic tests blank File Edit View Terminal Tabs Help Info 209005 Programming status programming flash memory at byte address x0F FBOGGO Info 209005 Programming status programming flash memory at byte address x F F90000 Info 209005 Programming status programming flash memory at byte address Bx0F FAGGGG Info 209905 Programming status programming flash memory at byte address x0F FBERGO Info 2090085 Programming status programming flash memory at byte address Ox0F FCBBdO Info 209005 Programming status programming flash memory at byte address OxOF FDOGGO Info 289085 Programming status programming flash memory at byte address x F FEBO Info 209005 Programming status programming flash memory at byte address Bx0F FFOBGO Info 209011 Successfully performed operation s Info 209061 Ended Programmer operati
21. nux64 bin Device acl Given SOF reprogram temp sof Given RBF null Given core REF reprogram temp core rbf Saving PCI control registers of the board PCIe to fabric read test failed read xffffffff Not doing CvP since test read failed Need to program the board via SOF Programming the board with new SOF Executing quartus pgm c 1 m jtag o F reprogram temp sof Info ie Ci cul ilo DOC ON CAS CN On D CO CON Zn OC Gio CONS CU CE OC iso ON Del le Le Giai passi Dil Cole lisi asi Da Cale Da OR DONS CO pi Da Gini OS Gil Lei Die Vi CON Gas Di Li Li Gai Dar Lei Li li Nar CO Lei Li li Na Dei Li ai li i ai Info Running Quartus II 64 Bit Programmer Info Version 13 1 0 Build 162 10 23 2013 SJ Full Version Info Copyright C 1991 2813 Altera Corporation All rights reserved Info Your use of Altera Corporation s design tools logic functions Info and other software and tools and its AMPP partner logic Info functions and any output files from any of the foregoing Info including device programming or simulation files and any Info associated documentation or information are expressly subject Info to the terms and conditions of the Altera Program License Info Subscription Agreement Altera MegaCore Function License Info Agreement or other applicable license agreement including Info without limitation that your use is for the sole purpose of Info programming logic devices manufactured by Altera and sold by Info Altera
22. ocx aocl flash Running flash from C saltera 13 1 hld hoard teras ic debnet uindous 4 hin GC altera 13 1 hld board terasicxtests blank gt GC xaltera 13 1 quartus bin64 perl binsperl GC i altera 13 1 hld board terasic deSnet windows64 bin flash pl fpga temp hbin Page Selection Please select the flash page where to store your FPGA configure data A Factory Image LocationAddress 6806040060 542 2 1 Right Position gt 1 User Image Location Address 0x9269C0006 gt 542 2 O Left Position Enter a digital number or 1 0r other values to exit the program followed hy pressing the Enter key Figure 2 7 Select Flash Page After users select desired flash area it will take about 20 minutes for flash programming Figure 2 8 is the screen shot when flash programming is done successfully DE5 Net OpenCL 11 www terasic com LasiC July 7 2014 www terasic com ES Administrator Command Prompt sy C altera 13 1 hld board terasic tests blanki Figure 2 8 aocl flash blank aocx successfully To make sure a correct image is used when FPGA boots up please make sure the dip switch SW2 2 on DES NET is changed to the correct location If a User Image area 1s selected the dip switch SW2 2 on the DES NET should be moved to left position as shown in Figure 2 9 Figure 2 9 Set SW2 2 to Left Position User Image Page After flash programming is done successfully and SW2 2 is set to corre
23. on at Mon Feb 17 19 35 42 2014 Info Quartus II 64 Bit Programmer was successful 6 errors 8 warnings Info Peak virtual memory 2629 megabytes Info Processing ended Mon Feb 17 19 35 42 2014 Info Elapsed time 06 11 63 Info Total CPU time on all processors 00 02 46 E root localhost blank Figure 3 9 aocl flash blank aocx successfully To make sure correct image is used when FPGA boot please make sure the dip switch SW2 2 on DES NTE 1s located at correct location If User Image area is selected the dip switch SW2 2 on the DES NET should be move to left position as shown in Figure 3 10 Figure 3 10 Set SW2 2 to Left Position User Image Page After flash programming is done successfully and SW2 2 is set to correct position developers can reboot the PC and check whether the blank OpenCL image which is CvP enabled configures the FPGA successfully when DES NET is power on In the Linux terminal type cd root altera 13 1 hld board terasic tests blank to go to blank project folder then type aocl program blank aocx to configure the FPGA with blank aocx OpenCL image If the programing DE5 Net OpenCL 26 www terasic com ter ET imma www terasic com message displays CvP worked as shown in Figure 3 11 it means the blank OpenCL image is programmed into the flash correctly and CvP works well root localhost blank aocl program blank aocx aocl program Running reprogram from root altera 13 1 hld boa
24. or its authorized distributors Please refer to the Info applicable agreement for further details Info Processing started Mon Feb 17 21 38 31 2014 Info Command quartus pgm c 1 m jtag o P reprogram temp sof Info 213045 Using programming cable DES Standard USB 1 1 3 Info 213011 Using programming file reprogram temp sof with checksum Ox 8 5E5 F for device SSGAEA N2F45 1 Info 209060 Started Programmer operation at Mon Feb 17 21 38 47 2014 Info 209016 Confiquring device index 1 Info 209017 Device 1 contains JTAG ID code 0x0290300D Info 209007 Configuration succeeded 1 device s configured Info 209011 Successfully performed operation s Info 209061 Ended Programmer operation at Mon Feb 17 21 38 58 2014 Info Quartus II 64 Bit Programmer was successful 8 errors 8 warnings Info Peak virtual memory 964 megabytes Info Processing ended Mon Feb 17 21 38 58 2014 Info Elapsed time 00 00 27 Info Total CPU time on all processors 00 00 08 Restoring PCI control registers of the board Link is operating as PCIe gen2 x 8 Vendor id 6x1172 device id Oxab0o root localhost blank Figure 3 7 aocl program blank aocx Command E Test aocl flash Command In the terminal type cd root altera 13 1 hld board terasic tests blank to go to blank OpenCL project folder then type aocl flash blank aocx to program blank aocx OpenCL image onto the DE5 Net OpenCL 24 www ter
25. p by creating an environment variable LM_LICENSE_ FILE and set its value as c license dat Note that this environment value needs to correspond to the actual license dat file location Now here are the procedures to create the required LM_LICENSE_FILE environment variable on Windows 7 1 Open the Start Menu and right click on Computer Select Properties 2 Select Advanced system settings 3 Inthe Advanced tab select Environment Variables 4 Select New 5 In the popup New User Variable dialog as shown in Figure 2 2 type LM_LICENSE_FILE in the Variable name edit box and type c license dat in the Variable value edit box DE5 Net OpenCL 6 www terasic com asie PET www terasic com Edit User Variable a Variable name LM LICENSE FILE Variable value ciilicense dat OK Cancel Figure 2 2 Setup LM LICENSE FILE Environment Variable 2 3 Configure For Altera OpenCL SDK to be able to find the kit location of DES NET correctly developers need to create an environment variable AOCL BOARD PACKAGE ROOT and set its value as ALTERAOCLSDKROOT board terasic deSnet Here are the procedures to create the required AOCL_BOARD_PACKAGE_ ROOT environment variable on Windows 7 1 Open the Start Menu and right click on Computer Select Properties 2 Select Advanced system settings 3 Inthe Advanced tab select Environment Variables 4 Select New 5 In the popup New User Variable di
26. pen bloardtest sin Host Program 14 www terasic com July 7 2014 Tasic DE5 Net OpenCL www terasic com After boardtest Host Program project is opened successfully BUILD Build Solution successful message as show in Figure 2 13 The execute file is generate in C altera 13 1 hld board terasic tests boardtest host x64 Release boardtest exe in Visual Studio IDE select menu item to build host program When build is successfully you will see 2 show output from Build 1 gt alteracl lib acl_offline_hal obj warning LNK4 99 PDB 1 gt alteracl lib acl platform obj warning LNK4 99 PDB l1 gt alteracl lib acl_ printf obj l1 gt alteracl lib acl_program obj l1 gt alteracl lib acl support obj Toke aren eae warning LNK4999 PDB warning LNK4 99 PDB nane LNK4899 PDB G adi vc98 pdb was not found with vc9 pdb was not found with vc9 pdb was not found with vc9 pdb was not found with daga DEE was not found with 2 ra alteracl libl acl_offli alteracl lib acl platforn alteracl lib acl_ printf ob alteracl lib acl_program c i lib acl_ SR la Figure 2 13 Message for boardtest Host Program build successfully E Test boardtest project First use the compiled OpenCL image file boardtest aocx to configure the FPGA In Command Prompt window type cd C altera 13 1 hid boarditerasic tests boardtest to go to boardtest project folder then type aocl program board
27. pt DE5 Net OpenCL 8 www terasic com asie rta www terasic com E Target Board In Command Prompt window type aoc list boards command and make sure deSnet a7 is listed in Board list as shown in Figure 2 5 Es Administrator Command Prompt ox sa Microsoft Windows Version 6 1 76011 Copyright tc 2009 Microsoft Corporation All rights reserved C Users remote LABlil gt aoc list_ hboards Board list deSnet_a Ci xUsers pemote LABII Figure 2 5 deSnet_a7 is listed in Board list E Test aocl program Command In Command Prompt window type cd C altera 13 1 hld board terasic tests blank to go to blank OpenCL project folder then type aocl program blank aocx to configure the FPGA of DES NET with blank aocx OpenCL image First the programmer will try to configure the FPGA of DES NET through PCI Express CvP Configuration via Protocol If the CvP is not found the programmer will extract reprogram_temp sof from the blank aocx and try to use reprogram_temp sof to configure the FPGA through USB Blaster as shown in Figure 2 6 It is normal for the programmer not being able to find CvP for the first time because the startup configuration on flash of DES NET does not contain required CvP Next section will show how to use aocl flash command to write a CvP enabled startup configuration on flash DE5 Net OpenCL 9 www terasic com TigasiC July 7 2014 www terasic com
28. rd terasic deSnet Alternatively you can edit the etc profile profile file and append the environment variables to it DE5 Net OpenCL 20 www terasic com Kjas c MT www terasic com To do this type gedit etc profile command on Linux Terminal to open the profile file by the gedit editor tool and append the following setting to the profile file Then save the file and type source etc profile command in Linux Terminal to make the settings make effect export QUARTUS_ROOTDIR root altera 13 1 quartus export ALTERAOCLSDKROOT root altera 13 1 hld export PATH PATH QUARTUS_ROOTDIR bin ALTERAOCLSDKROOT linux64 bin export LD_LIBRARY_PATH ALTERAOCLSDKROOT linux64 lib export AOCL_BOARD_PACKAGE_ROOT ALTERAOCLSDKROOT board terasic deSnet export QUARTUS_64BIT 1 export LM_LICENSE_FILE root altera 13 1 hld license dat 3 4 Board Setup Before testing OpenCL on DES NET please following the below procedure to setup DES NET board on your PC as shown in Figure 3 4 Make sure your PC is power off Insert DES NET board into PCI Express x8 or x16 slot 3 Connect PC s 12V PCI Express 6 pin power to the DES NET source if there s not ignore this step 4 Connector PC s USB port to DES NET mini USB port using an USB cable Note the usb cable can be removed later if any one of OpenCL code had been programming to the startup configuration flash of DES NET by aocl flash comma
29. rd terasic desnet linux64 bin Device acl Given SOF reprogram temp sof Given RBF null Given core RBF reprogram temp core rbf Saving PCI control registers of the board PCle to fabric read test passed Starting CYP reprogramming of the device with 33677312 bytes of data PCIe to fabric read test passed Uniphys are calibrated CvP worked Restoring PCI control registers of the board Link is operating as PCIe gen x B Vendor id 080x1172 device id xab root localhost blank Figure 3 11 aocl program blank aocx use CvP 3 6 Compile and Test OpenCL Project This section will show how to compile and run the OpenCL kernel and OpenCL Host Program for the boardtest example project Developers can use the same procedures to compile and test other OpenCL examples included in the kit for DES NET E Compile OpenCL Kernel In the terminal type cd root altera 13 1 hld board terasic tests boardtest to go to boardtest project folder then type aoc boardtest cl sw dimm partition report to compile the OpenCL kernel It will takes about one hour for compiling After that the OpenCL image file boardtest aocx is generated Figure 3 12 is the screen shot when OpenCL kernel is compiled successfully For required parameters to compile boardtest cl please refer to the README txt that is in the same directory The utility aoc Altera SDK for OpenCL Kernel Compiler is used to compile OpenCL kernel
30. ssociated documentation or information are expressly subject Info to the terms and conditions of the Altera Program License Info Subscription Agreement Altera MegaCore Function License Info Agreement or other applicable license agreement including Info without limitation that your use is for the sole purpose of Info programming logic devices manufactured by Altera and sold by Info Altera or its authorized distributors Please refer to the Info applicable agreement for further details Info Processing started Mon Dec ona 16 42 41 2013 Info Command quartus_pgm c 1 m jt o F ireprogram_temp sof Info 213845 Using programming Cable DES Standard USB 11 Info 2138115 Using programming file reprogram_temp sof with checksum 4xA78762C F for device S5GH4EA7 N2F4501 Info 209066 gt Started Programmer operation at Mon Dec 30 16 02 51 2013 Info 20960163 Configuring device index 1 Info 2096017 gt Device 1 contains JTAG ID code Hx029030DD Info 2095073 Configuration succeeded 1 devices configured Info 2095113 Successfully performed operations Info lt 2898612 Ended Programmer operation at Mon Dec 36 16 93 63 26013 Info Quartus II 32 bit Programmer was successful 4 errors A warnings Info Peak virtual memory 646 megabytes Info Processing ended Mon Dec 309 16 03 03 2013 Info Elapsed time 00 00 22 Info Total CPU time Con all processors 66 60 16 Waiting 2 seconds Writing 4696 bytes of
31. ster BUS usb SYSFS idVendor 09rb SYSFS i1dProduct s6001 MODE 0660 BUS usb SYSFS idVendor 09fb SYSFS idProduct 6002 MODE 0666 BUS USb SYSES rdVendor O09Eb SYSEFS 1dProduct 6003 MODE 066O T USB Blaster II BUsS usb SYSFS i1dVendor 09Lfb SYSFS i1cdProduct 6010 MODE 0666 BUS ME ENS vores MaMendo Reid dae AO DE ARG Note You must have system administration root privileges to configure the USB Blaster download cable drivers E GNU development tools GNU development tools such as gec include g and make are required to build the driver and application under Linux User can issue yum install gcc ccompat gcc 34 c make command to download and install them and their dependencies via internet Note To install the SDK on Linux you must install it in a directory that you own that is a directory that is not a system directory You must also have sudo or root privileges E DES NET openCL BSP After Quartus II and OpenCL SDK are installed copy the whole terasic folder in Terasic OpenCL Kit into the folder root altera 13 1 hld board where assumed Quartus II is installed on the folder root altera 13 1 Figure 3 3 shows file folder content when terasic folder is copied DE5 Net OpenCL 19 www terasic com asie ET www terasic com NOTES RYA UNIVERSITY PROGRAM Applications Places System esAS X board Fil
32. t on 64 bit Linux Red Hat Enterprise Linux 5 6 or later and CentOS 6 4 or later are recommended and how to compile and test the OpenCL examples for DES Net For more details about Altera OpenCL please refer to Altera SDK for OpenCL Getting Started document http www altera com literature hb opencl sdk aocl_getting_started pdf 3 1 Software Installation This section describes how to download and install the required software for OpenCL E Altera Quartus II and OpenCL Altera Quartus II and OpenCL can be download from the web site http dl altera com opencl open the link and select the Linux operation system and the needed version default the latest as Figure 3 1 shows DE5 Net OpenCL 17 www terasic com asie oe TT www terasic com Release date November 2013 Altera SDK for OpenCL v131 Altera SDK for Select a previous version of Altera SDK for OpenCL f 13 1 Open LE Operating System iii fo B Lul Select the operating system on which you will run the Altera SDK for OpenCl Download Method Akamai DLM3 Download Manager Direct Download Select whether you will use the download manager Windows only or directly download the files Figure 3 1 OpenCL Linux version selection In the OpenCL software download selection form choose and click the Altera FPGA Design Software and SDK for OpenCL as Figure 3 2 show if selected Altera FPGA Design software please make sure the Stratix V device is included
33. tera OpenCL compiler provided by the Altera OpenCL SDK The Host Program is compile by Visual Studio C C in Windows or GCC on Linux OpenCL Kernel Host Program main _ kernel void sum __global const float a _ global const float b read_data_from_file _ global float answer maninpulate data int xid get global id answer xid a xid b xid mels clEnqueueWriteBuffer clEnqueueKernel sum clEnqueueReadBuffer Host Program Ke int xid get global id 0 answer xid a xid b xid display result _ to user Figure 1 1 Altera OpenCL Architecture asic DE5 Net OpenCL 4 www terasic com Biases July Ta 2014 Chapter 2 OpenCL for Windows This chapter describes how to set up DES NET OpenCL development environment on 64 bit Windows and how to compile and test the OpenCL examples for DE5 Net For more details about Altera OpenCL started guide please refer to http www altera com literature hb opencl sdk aocl getting started pdf 2 1 Software Installation This section describes where to get the required softwares for OpenCL E Altera Quartus II and OpenCL SDK Altera Quartus II and OpenCL SDK can be download from the web site http dl altera com opencl For Quartus II installation please make sure that the Stratix V device 1s included E Visual Studio 2012 If developers don t have Visual studio C C
34. test aocx to configure FPGA with the OpenCL Image boardtest aocx If configuration is successfully you will see the successful message as shown in Figure 2 14 Es Administrator Command Prompt C altera 13 1 hld board terasic tests boardtestaocl program boardtest aocx aocl program dows64 bin Given SOF reprogram_temp s0f Given HBF none Given core REF reprogram_temp core rbf UDO DriverOpen success UDC_PciScanleuices success Programming this device H gt Vendor ID bx1172 Device ID BxABBO Bus i Slot 6 Function 6 1 slot A function A Reading 4696 bytes of configuration space data UDC_PciReadCfoqBuyS lot success WDG_PeiGetDeviceInfo success UDC PcibevicEOpen success PCle to fabric read test passed Starting CUP reprogramming of the device OK to proceed with GuP Setup is done Starting to write CuP data INFO Reached the end of the core programming file CuP has finished The Application Layer is ready for normal operation Verifying device functionality right after CuP PCle to fabric read test passed Uniphys are calibrated CuP worked GC altera 13 1 hld board terasic tests boardtest gt _ Running reprogram from C altera 13 1 hld board terasic de net uwin Figure 2 14 aocl program boardtest aocx configured successfully 15 Tasic DE5 Net OpenCL www terasic com www terasic com July 7 2014 Then launch the compiled Host Program to start boardtest executable fil
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