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Xilinx UG534 ML605 Hardware, User Guide

1. FMC LPC LA28 FMC L FMC LPC_LA29 FMC FMC FMC PC LAZO FMC LPC LA31 FMC L FMC LPC LA32 FMC FMC FMC NET PC LA33 p PC LA06 N p PC LAO7 N p PC LA08 N p PC LAO9 N p PC LA10 N p PC LA11 N p PC LA12 N p PC LA13 N p PC LA14 N p PC LA15 N p PC LA16 N p PC LA17 CC N PC LA17 CC p PC LA18 CC N PC LA18 CC P PC LA19 N p PC LA20 N p PC LA21 N p PC LA22 N p PC LA23 N p PC LA24 N p PC LA25 N p PC LA26 N p PC LA27 N p PC LA28 N p PC LA29 N p PC LAZO N p PC LA31 N p PC LA32 N p PC LA33 N p LPC PRSNT M2C L F PGA CCLK NET FPGA DONE NET FPGA DX N NET FPGA DX P NET FPGA FCS B NET FPGA FOE B LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC H34 J34 K33 H32 G32 K29 330 L26 L25 G30 F30 D32 D31 E33 E32 C34 D34 B34 C33 B32 C32 B33 A33 N29 N28 L30 L29 N30 M30
2. LED GRN SMT LED GRN SMT LED GRN SMT LED GRN SMT LED GRN SMT LED GRN SMT o o o R12 27 4 1 1 16W GPIO LED C GPIO LED W GPIO LED E GPIO LED S GPIO LED N This group of LEDs is mounted adjacent to their respective direction pushbuttons as seen on the right side g of the LCD on the board photo Figure 8 5 1 2 E GPIO LED N R UG534 18 081109 Figure 1 18 User LEDs and GPIO Connector Directional LEDs Note See User Pushbutton Switches page 51 for more details about the LEDs 50 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description Table 1 21 User LED Connections FPGA U1 Pin Schematic Net Name GPIO J62 Pin Controlled LED AC22 GPIO LED 0 1 DS12 AC24 GPIO LED 1 2 DS11 AE22 GPIO_LED_2 3 DS9 AE23 GPIO_LED_3 4 DS10 AB23 GPIO_LED_4 5 DS15 AG23 GPIO_LED_5 6 DS14 AE24 GPIO_LED_6 7 DS22 AD24 GPIO LED 7 8 DS21 AP24 GPIO LED C DS16 AD21 GPIO LED W DS17 AE21 GPIO_LED_E DS19 AH28 GPIO LED S DS18 AH27 GPIO_LED_N DS20 User Pushbutton Switches The ML605 provides six active High pushbutton switches e SW5 SW6 SW7 SW8 and SW9 arranged in a diamond configuration to depict directional headings North South East West and Center respectively e SW10 CPU Reset pushbutton The six pushbuttons all have the same active High topology as the sample shown in F
3. Preface About This Guide Guide Contents schoo geo dae earned ada 7 Additional Documentation 7 Additional Support Resources we ae w inibit eed edn ski kk sie ke ek 8 Chapter 1 ML605 Evaluation Board OV EKV OW II aga T SIKA tea teases TA 9 Additional Information sossun NNN 9 Feat Seos l m ia a daa sacle O E S at 10 Block Diagram sussa sia at ii Ube duo b E E 12 Related Xilinx Documents nn LLA 12 Detailed Description ovnis sota Pauk FISA KKKA V NSI IATA AAA 13 1 Virtex 6 XC6VLX240T 1FFG1156 FPGA Lea 15 Config UTA ON ibid io a aye Sit path ande aI EES a KSS KE ee ad 15 I O Voltage RAS w w isa cess 32254 KEI ee eee bee VEN YVA Sas ed 16 2 512 MB DDR3 Memory SODIMM Lee 17 3 128 Mb Platform Flash XL LL 22 4 32 MB Linear BPI Flash 2 LLA 22 ML605 Flash Boot Options 0 eee see eee ke cc 23 5 System ACE CF and CompactFlash Connector a 26 6 USB JTAG issiru sa mwa rs ace hoo a do AK vers dan te ob als 28 7 Clock Generation 29 Oscillator Differential 2034 avew wee aa kone aa eb eed bead VN s Vaya saaga s v 29 Oscillator Socket Single Ended 2 5V eee 29 SMA Connectors Differential soon nnn 31 8 Multi Gigabit Transceivers GTX MGTS osuneen 33 9 PCI Express Endpoint Connectivity oloon kanna 34 10 SFP Module Connector o 37 11 10 100 1000 Tri Speed Ethernet PHY sossun eee 38 SGMII GTX Transceiver Clock Generation eee 39 12 105
4. PC LA01 CC N PC LA01 CC p PC LA02 N PC LAO2 P PC LA03 N PC LA0O3 P PC LAOA4 N PC LAO4 P PC LAOS N PC LAOS P PC LA06 N PC LA06 P PC LAO7 N PC LAO7 P PC LA08 N PC LA08 P PC LA09 N PC LA09 P PC LA10 N PC LA10 P PC LA11 N PC LA11 P PC LA12 N PC LA12 P PC LA13 N PC LA13 P PC LA14 N LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AP33 AP32 HH AM31 dif AL30 AL33 AM33 HH AN34 HH AN33 44 AE26 HH AF26 HH AH34 44 AJ34 AK32 AK33 AK34 HH AL34 HH AF29 AF28 AJ30 AJ29 HH AJ32 AJ31 HH AH32 44 AH33 44 AD27 44 AE27 AE29 AE28 AH30 44 AH29 dif AG28 AG27 AD26 44 AD25 dif AK31 AL31 AF21 HH AF20 AL19 44 AK19 HH AD20 if AC20 AD19 44 AC19 dif AE19 44 AF19 AH22 44 AG22 AG21 AG20 AJ21 AK21 AJ22 AK22 AL18 AM18 44 AL2
5. R29 P29 T26 R26 P27 N27 R27 R28 P32 N32 P30 P31 M32 L33 R32 R31 M33 N33 P34 N34 M27 M26 L31 M31 M25 N25 K31 K32 ADO K8 R8 W17 W18 Y24 AA24 HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH D11 C11 C10 H14 H13 G13 G12 D15 D14 CIS C14 H17 H16 G16 G15 D18 D17 c19 C18 H20 H19 G19 G18 D21 D20 C23 C22 H23 H22 G22 G21 H26 H25 G25 G24 D24 D23 H29 H28 G28 G27 D27 D26 C27 C26 H32 H31 G31 G30 H35 H34 G34 G33 H38 H37 G37 G36 H2 SEE 4 HH HH HH SEE SEE on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 NET FLASH NN GROUP on on on DONE J35 J35 LED DS13 NET FLASH NN GROUP NET FLASH
6. MDC MDIO p PHY RESET PHY RXCLK PHY RXCTL RXDV RXDO PHY PHY PHY PHY PHY PHY PHY PHY PHY RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXER PHY TXCLK PHY TXCTL TXEN PHY TXC GTXCLK TXDO TXD1 PHY PHY PHY PHY PHY PHY PHY PHY PHY TXD2 TXD3 TXDA TXD5 TXD6 TXD7 TXER LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC 33 K6 K5 LA L3 Nan N3 Ran R3 UA U3 WA W3 DAA AA3 FQ FL H2 H1 K2 K1 M2 M1 pan PL Tan TIN V2 VL yan yin AD22 AK13 AL13 AH14 AP14 AN14 AH13 AP11 AM13 AN13 AF14 AE14 AN12 AM12 AD11 AC12 AC13 AG12 AD12 AJ10 AH12 AM11 AL11 AG10 AG11 AL10 AM10 AE11 AF11 AH10 AC23 HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH B14 B20 B19 B24
7. USB WR B LS USER CLOCK USER SMA CLOCK N USER SMA CLOCK P USER SMA GPIO N USER SMA GPIO P VAUX CURR N VAUX CURR P VAUX VOLT N VAUX VOLT P LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC T31 T29 V28 V27 U25 Y28 W32 W31 Y29 W29 Y34 Y 33 Y31 Y27 W25 T25 V25 U23 M22 L23 W34 V34 P26 P25 M28 L28 HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH H H H H vi Ho pH H H on on on on on on on on on on on on on on on on on on on on on on on on on on U31 U31 U31 U31 U30 U29 U29 U29 U30 U30 U30 U30 U30 U29 U29 U30 U29 X5 J55 J58 J56 J57 SMA SMA SMA SMA series series series series R373 R370 R371 R372 H H H H OOK OOK OOK OOK 94 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Appendix E Regulatory and Compliance Information This product is designed and tested to conform to the European Union directives and standards described in this section Declaration of Conformity Directives Standards To view the Declaration of Conformity online visit http www xilinx com support documentation boards and kits ce d
8. 169 171 186 188 116 120 110 30 114 121 198 113 63 62 61 60 59 58 55 54 53 52 51 50 18 56 57 0 H N NNN NN N 0 O H N W PB U LV H U H N W P U A J ou on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI U38 U38 U38 U38 U38 U38 U38 U38 U38 U38 U38 U38 U38 U32 U38 U32 U38 U38 U38 GQGOGGGQGGGGG SEP PF PP PPP C C G G SEPP PPP PP ib thru series thru series thru series thru series thru series thru series thru series thru series thru series thru series thru series thru series not wired to thru series R111 47 R110 47 R109 47 R108 47 R107 47 R106 47 R105 47 R104 47 R103 47 R102 47 R101 47 R100 47 R112 47 U38 R113 47 5 UT LI LI LI LI LI LI LI LI UI LI LI VI O 0 0 0 0 O 0 0 0 O 0 6 DVI RESET B pin 13 on thru series thru series Al on U27 B1 on U27 CI on U27 D1 on U27 D2 on U27 A2 on U27 C2 on U27 A3 on U27 B3 on U27 C3 on U27 D3 on U27 C4 on U27 A5 on U27 B5 on U27 C5 on U27 D7 on U27 D8 on U27 A7 on U27 R114 47 5 lt o O ML605 H
9. G20 DDR3 D25 59 DO25 E19 DDR3_D26 67 DQ26 F20 DDR3_D27 69 DQ27 A20 DDR3_D28 56 DQ28 A21 DDR3 D29 58 DO29 F22 DDR3 D30 68 DQ30 E23 DDR3_D31 70 DQ31 G21 DDR3_D32 129 DQ32 B21 DDR3 D33 131 DQ33 A23 DDR3_D34 141 DQ34 A24 DDR3_D35 143 DQ35 C20 DDR3_D36 130 DO36 D20 DDR3 D37 132 DO37 J20 DDR3 D38 140 DQ38 G22 DDR3_D39 142 DQ39 D26 DDR3_D40 147 DQ40 F26 DDR3_D41 149 DO41 B26 DDR3 D42 157 DQ42 E26 DDR3_D43 159 DQA3 C24 DDR3 D44 146 DQ44 D25 DDR3 D45 148 DQ45 D27 DDR3 D46 158 DO46 C25 DDR3 D47 160 DO47 C27 DDR3 D48 163 DO48 B28 DDR3 D49 165 DQ49 D29 DDR3_D50 175 DQ50 B27 DDR3_D51 177 DO51 G27 DDR3_D52 164 DQ52 A28 DDR3_D53 166 DO53 ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com 19 Chapter 1 ML605 Evaluation Board XILINX Table 1 4 DDR3 SODIMM Connections Cont d J1 SODIMM U1 FPGA Pin Schematic Net Name Pin Number Pin Name E24 DDR3_D54 174 DQ54 G25 DDR3 D55 176 DO55 F28 DDR3 D56 181 DO56 B31 DDR3 D57 183 DO57 H29 DDR3_D58 191 DQ58 H28 DDR3_D59 193 DQ59 B30 DDR3_D60 180 DQ60 A30 DDR3_D61 182 DO61 E29 DDR3_D62 192 DQ62 F29 DDR3_D63 194 DQ63 Ell DDR3 DMO 11 DMO B11 DDR3_DM1 28 DM1 El4 DDR3_DM2 46 DM2 D19 DDR3_DM3 63 DM3 B22 DDR3_DM4 136 DM4 A26 DDR3_DM5 153 DM5 A29 DDR3_DM6 170 DM6 A31 DDR3_DM7 187 DM7 E12 DDR3_DOS0_N 10 DOS0_N D12
10. U38 DVI CODEC CHRONTEL SFP MOD DEF2 SFP MODULE CH730C TF SFP MOD DEF1 CONNECTOR Addr 0b1110110 Addr 0b1010000 UG534 14 092109 Figure 1 14 IIC Bus Topology ML605 Hardware User Guide www xilinx com 45 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board 8 Kb NV Memory XILINX The ML605 hosts an 8 Kb ST Microelectronics M24C08 WDW6TP IIC parameter storage memory device U6 The IIC address of U7 is 0b1010100 and U6 is not write protected WP pin 7 is tied to GND The IIC memory is shown in Figure 1 15 VCC3V3 IIC SCL MAIN IIC SDA MAIN Figure 1 15 IIC Memory U6 Table 1 18 IIC Memory Connections VCC3V3 VCC3V3 1 C65 X5R 2 10V 0 1UF UG534_15_072109 IIC Memory U6 FPGA U1 Pin Schematic Net Name Pin Number Pin Name Not Applicable Tied to GND 1 AO Not Applicable Tied to GND 2 A1 Not Applicable Pulled up 09 to VCC3V3 3 A2 AF9 IIC SDA MAIN 5 SDA AKI IIC SCL MAIN 6 SCL Not Applicable Tied to GND 7 WP References See the ST Micro M24C08 Data Sheet for more information Ref 31 In addition see the Xilinx XPS IIC Bus Interface v2 00a Data Sheet Ref 21 46 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX 16 Status LEDs Table 1 19 defines the status LEDs Detailed Description Table 1 19 Status LEDs Designator Signal Name Color L
11. UG534 v1 8 October 2 2012 XILINX FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and configuration status LEDs are present on the ML605 Detailed Description The red INIT LED DS31 comes on momentarily after the FPGA powers up and during its internal power on process The DONE LED DS13 comes on after the FPGA programming bitstream has been downloaded and the FPGA successfully configured FPGA INIT B VCC2V5 NDS336P Figure 1 17 FPGA INIT and DONE LEDs Table 1 20 FPGA INIT and DONE LED Connections FPGA_DONE FPGA U1 Pin Schematic Net Name Controlled LED P8 FPGA_INIT_B DS31 INIT Red R8 FPGA_DONE DS13 DONE Green 17 User I O VCO2V5 LED GRN SMT o D N 27 4 1 1 16W UG534 17 050510 The ML605 provides the following user and general purpose I O capabilities e User LEDs 8 with parallel wired GPIO male pin header e User Pushbutton 5 switches with associated direction LEDs e CPU Reset pushbutton switch e User DIP switch 8 pole e User SMA GPIO e LCD Display 16 char x 2 lines ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com 49 Chapter 1 ML605 Evaluation Board XILINX User LEDs The ML605 provides two groups of active High LEDs as described in Figure 1 18 and Table 1 21 GPIO LED 0 GPIO LED 1 GPIO LED 2 GPIO LED 3 GPIO LED 4 GPIO LED 5 GPIO LED 6 GPIO LED 7 LED GRN SMT
12. 1 FMC_TDI_BUF Bypass FMC HPC J64 Jumper 1 2 2 FMC_LPC_TDI A Include FMC HPC J64 Jumper 2 3 FMC HPC TDO H 1x3 UG534_05_081309 Figure 1 5 VITA 57 1 FMC HPC J64 JTAG Bypass Jumper J17 J18 1 FMC_LPC_TDI Bypass FMC LPC J63 Jumper 1 2 2 SYSACE_TDI 3 Include FMC LPC J63 Jumper 2 3 FMC LPC TDO H 1x3 UG534 06 081309 Figure 1 6 VITA 57 1 FMC LPC J63 JTAG Bypass Jumper J18 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug The JTAG connector USB Mini B J22 allows a host computer to download bitstreams to the FPGA using the Xilinx iMPACT software tool In addition the JTAG connector allows debug tools such as the ChipScope Pro Analyzer tool or a software debugger to access the FPGA The iMPACT software tool can also program the BPI flash via the USB J22 connection iMPACT can download a temporary design to the FPGA through the JTAG This provides a connection within the FPGA from the FPGA s JTAG port to the FPGA s BPI interface Through the connection made by the temporary design in the FPGA iMPACT can indirectly program the BPI flash or the Platform Flash XL from the JTAG USB J22 connector For an overview on configuring the FPGA see Configuration Options page 76 7 Clock Generation There are three FPGA fabric clock sources available on the ML605
13. 21 and Table 1 24 J56 32K10K 400E3 USER SMA GPIO N USER SMA GPIO P UG534_21_072109 Figure 1 21 User SMA GPIO Table 1 24 User SMA Connections U1 FPGA Pin Schematic Net Name SMA Pin W34 USER_SMA_GPIO_N J56 1 V34 USER_SMA_GPIO_P J57 1 ML605 Hardware User Guide www xilinx com 53 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX LCD Display 16 Character x 2 Lines The ML605 board has a 16 character x 2 line LCD Display Tech S162D BA BC installed onto J41 2x7 header on the board to display text information Potentiometer R270 adjusts the contrast of the LCD A ST2378E U33 2 5V to 5V level shifter is used to shift the voltage level between the FPGA and the LCD The data interface to the LCD is connected to the FPGA to support 4 bit mode only The LCD module has a connector that allows the LCD to be removed from the board to access to the components below it Caution Care should be taken not to scratch or damage the surface of the LCD window VCC5 VCC5 R158 J41 o LCD DB7 1 2 LCD DB6 32 N N LCD DB5 3 o ran LCD_DB4 32 BIR 1 NC 5 e NC NC 7 ERA NC R270 LCD_E 9 LCD RW 32 0 2K LCD_RS 11 FOOT LCD_VEE 2 1 2W 107 01 T silkscreen APP si LCD Contrast ii UG534 22 073109 Figure 1 22 LCD Header J41 and Contrast Trimpot R270 Table 1 25 LCD Header Connections U1 FPGA Pin Schematic Net Name J41 Pin AD14 LCD_DB4_LS 4
14. B23 PETp2 A Integrated Endpoint block GTXE1 X0Y13 L4 PCIE_RX2_N B24 PETn2 receive pair N3 PCIE RX3 P B27 PETp3 A Integrated Endpoint block GTXE1 X0Y12 N4 PCIE RX3 N B28 PETn3 receive pair PCIE_RX4 P B33 PETp4 Integrated Endpoint block GTXEL X0Y11 R4 PCIE_RX4_N B34 PETn4 receive pair X U3 PCIE_RX5_P B37 PETp5 P Integrated Endpoint block GTXE1_X0Y10 U4 PCIE_RX5_N B38 PETn5 TECIE pau w3 PCIE_RX6_P Bal PETp6 Integrated Endpoint block GTXE1 X0Y9 W4 PCIE RX6 N B42 PETn6 receive pair ii ML605 Hardware User Guide www xilinx com 35 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX Table 1 8 PCle Edge Connector Connections Cont d P1 PCle Edge Connector I ge Schematic Net Name Description ET t Ju Pin Number Pin Name A EMEN AA3 PCIE RX7 P B45 PETp7 Integrated Endpoint block GTXE1_X0Y8 AA4 PCIE RX7 N B46 PETn7 PRESI pan P6 PCIE 100M MGTO P U14 16 Q0 Sourced from U14 ICS854104 IBUF P5 PCIE 100M MGTON Ul4 15 NQO clock driver GIXE1_X0Y6 V6 PCIE_250M_MGT1_P U9 18 Q Sourced from U9 ICS874001 IBUF V5 PCIE 250M MGT1 N U9 17 NQ clock multiplier driver GTXEI X0Y4 U14 6 PCIE CLK QO P A13 REFCLK Integrated Endpoint block differential clock pair from PCle U14 7 PCIE CLK OO N A14 REFCLK edge connector J42 2 4 6 PCIE PRSNT B Al PRSNT 1 J42 Lane Size Select jumper Integrated Endpoint block wake AD22 PCIE WAKE B B11 WAKE signal not connected o
15. DDR3 SODIMM Micron 512 MB MT4JSF6464HY 1G1 15 3 128 Mb Platform Flash XL Xilinx XCF128X FTG64C 25 4 Linear BPI Flash Numonyx JS28F256P30T95 26 System ACE CF controller CF Xilinx XCCACE TO144I 5 13 connector bottom of board 6 J TAG cable connector USE USB JTAG download circuit 46 Mini B ML605 Hardware User Guide www xilinx com 13 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board 14 XILINX Table 1 1 ML605 Features Cont d Number Feature Notes schematic Page Clocle generation 200 MHz OSC oscillator socket SMA 30 connectors a 200 MHz oscillator Of crime 200 MHz 25V LVDS OSC 30 backside 7 b Oscillator socket single MMD Components 66 MHz 2 5V 30 ended c SMA connectors SMA pair 30 d MGT REFCLK SMA SMA pair 30 connectors 8 GTX RX TX port SMA x4 30 PCIe Geni 8 lane 9 Gen 4 lane Card edge connector 8 lane 21 10 SFP connector and cage AMP 136073 1 23 11 Ethernet 10 100 1000 with rvell M88E1111 EPHY 24 SGMII 12 USBMini B USB to UART gilicon Labs CP2103GM bridge 33 bridge 13 USB A Host USB Mini B Cypress CV7C67300 100AXI 27 peripheral connectors controller 14 Video DVI connector Chrontel CH7301C TF Video codec 28 29 15 IIC NV EEPROM 8 Kb ST Microelectronics M24C08 32 on backside WDW6TP Status LEDs 13 24 31 a Ethernet status Right angle link rate and direction 24 LEDs 16 b FPGA INIT DONE I
16. EPC v1 02a Data Sheet for more information Ref 20 42 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description 14 DVI Codec The ML605 features a DVI connector P3 to support an external video monitor The DVI circuitry utilizes a Chrontel CH7301C U38 capable of 1600 X 1200 resolution with 24 bit color The video interface chip drives both the digital and analog signals to the DVI connector A DVI monitor can be connected to the board directly A VGA monitor can also be connected to the board using the supplied DVI to VGA adaptor The Chrontel CH7301C is controlled by way of the video IIC bus The DVI connector Table 1 17 supports the IIC protocol to allow the board to read the monitor s configuration parameters These parameters can be read by the FPGA using the DVIIIC bus see 15 IIC Bus page 44 Table 1 17 DVI Controller Connections U38 Chrontel CH7301C U1 FPGA Pin Schematic Net Name Pin Number Pin Name AJ19 DVI DO 63 DO AH19 DVI_D1 62 D1 AM17 DVI_D2 61 D2 AM16 DVI_D3 60 D3 AD17 DVI_D4 59 D4 AF17 DVI D5 58 D5 AK18 DVI_D6 55 D6 AK17 DVI_D7 54 D7 AE18 DVI D8 53 D8 AF18 DVI D9 52 D9 AL16 DVI D10 51 D10 AK16 DVI_D11 50 D11 AD16 DVI DE 2 DE AN17 DVI H 4 H AP17 DVI RESET B LS 13 RESET B AD15 DVI V b V AC17 DVI_XCLK_N 56 XCLK_N AC18 DVI_XCLK_P 57 XCLK_P No Connect DVI_GPIOO 8 GPIOO No Conne
17. FMC HPC LA19 P NET FMC HPC LA20 N NET FMC HPC LA20 P NET FMC HPC LA21 N NET FMC HPC LA21 P NET FMC HPC LA22 N NET FMC HPC LA22 P NET FMC HPC LA23 N NET FMC HPC LA23 P NET FMC HPC LA24 N NET FMC HPC LA24 P NET FMC HPC LA25 N NET FMC HPC LA25 P NET FMC HPC LA26 N NET FMC HPC LA26 P NET FMC HPC LA27 N NET FMC HPC LA27 P NET FMC HPC LA28 N NET FMC HPC LA28 P NET FMC HPC LA29 N NET FMC HPC LA29 P NET FMC HPC LA30 N NET FMC HPC LA30 P NET FMC HPC LAZI N NET FMC HPC LA31 P NET FMC HPC LA32 N NET FMC HPC LA32 P NET FMC HPC LA33 N NET FMC HPC LA33 P NET FMC HPC PG M2C LS NET FMC HPC PRSNT M2C L HH NET FMC LPC CLKO M2C N NET FMC LPC CLKO M2C P NET FMC LPC CLK1 M2C N NET FMC LPC CLK1 M2C Pp NET FMC LPC DPO C2M N NET FMC LPC DPO C2M P NET FMC LPC DPO M2C N NET FMC LPC DPO M2C Pp NET FMC LPC GBTCLKO M2C NET FMC LPC GBTCLKO M2C NET FMC LPC IIC SCL LS NET FMC LPC IIC SDA LS NET FMC LPC LAOO CC N NET FMC LPC LAOO CC Pp NET FMC LPC LA01 CC N NET FMC LPC LA01 CC p NET FMC LPC LAO2 N NET FMC LPC LAO2 P NET FMC LPC LAO3 N NET FMC LPC LAO3 P NET FMC LPC LAO4 N NET FMC LPC LA04 P NET FMC LPC LAO5 N LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC
18. LOC AE23 2 on LED DS10 4 on J62 NET GPIO LED 4 LOC AB23 2 on LED DS15 5 on J62 NET GPIO LED 5 LOC AG23 2 on LED DS14 6 on J62 NET GPIO LED 6 LOC AE24 2 on LED DS22 7 on J62 NET GPIO LED 7 LOC AD24 2 on LED DS21 8 on J62 HH NET GPIO LED C LOC AP24 2 on LED DS16 NET GPIO LED E LOC AE21 HH 2 on LED DS19 NET GPIO LED N LOC AH27 2 on LED DS20 NET GPIO LED S LOC AH28 HH 2 on LED DS18 NET GPIO LED W LOC AD21 2 on LED DS17 HH NET GPIO SW C LOC G26 2 on SW9 pushbutton active High NET GPIO SW E LOC G17 HH 2 on SW7 pushbutton active High NET GPIO SW N LOC A19 2 on SW5 pushbutton active High NET GPIO SW S LOC Al8 HH 2 on SW6 pushbutton active High NET GPIO SW W LOC H17 2 on SW8 pushbutton active High HH NET IIC SCL DVI LOC AN10 2 on 05 15 on U38 NET IIC SCL MAIN LS LOC AK9 2 on 019 NET IIC SCL SFP LOC AA34 2 on 023 NET ITC SDA DVI LOC AP10 2 on 06 14 on U38 NET IIC SDA MAIN LS LOC AE9 2 on Q20 NET IIC SDA SFP LOC AA33 2 on Q21 HH NET LCD DB4 LS LOC AD14 4 on J41 NET LCD DB5 LS LOC AK11 3 on J41 NET LCD DB6 LS LOC AJ11 2 on J41 NET LCD DB7 IS LOC AE12 1 on J41 NET LCD E LS LOC AK12 9 on J41 NET LCD RS IS LOC T28 HH 11 on J41 NET LCD RW IS LOC AC14 10 on J41 HH NET P30 CS SEL LO
19. MPOE AL14 SYSACE MPWE 76 MPWE AC8 SYSACE CFGTDI 81 CFGTDI AE8 FPGA_TCK 80 CFGTCK AD8 FPGA TDI 82 CFGTDO AF8 FPGA TMS 85 CFGTMS AE16 CLK_33MHZ_SYSACE 93 CLK Notes 1 The System ACE CF clock is sourced from U28 33 000 MHz osc References See the System ACE CF product page and the System ACE CompactFlash Solution Data Sheet Ref 18 ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com 27 28 a m a 5 Chapter 1 ML605 Evaluation Board XILINX 6 USB JTAG JTAG configuration is provided through onboard USB to JTAG configuration logic where a computer host accesses the ML605 JTAG chain through a Type A computer host side to Type Mini B ML605 side USB cable The JTAG chain of the board is illustrated in Figure 1 4 JTAG configuration is allowable at any time under any mode pin setting JTAG initiated configuration takes priority over the mode pin settings UG534_04_081309 Figure 1 4 JTAG Chain Diagram FMC bypass jumpers J17 and J18 must be connected between pins 1 2 bypass to enable JTAG access to the FPGA on the basic ML605 board without FMC expansion modules installed as shown in Figure 1 5 and Figure 1 6 When either or both VITA 57 1 FMC expansion connectors are populated with an expansion module that has a JTAG chain the respective jumper s must be set to connect pins 2 3 in order to include the FMC expansion module s JTAG chain in the main ML605 JTAG chain J17
20. N HA15 P HA16 N HA16 P HA17 CC N HA17 CC P HA18 N HA18 P HA19 N HA19 P HA20 N HA20 P HA21 N HA21 P HA22 N HA22 P HA23 N HA23 P HBOO CC N HB00 CC Pp HB01 N HB01 P LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AL3 ANA AN3 AM6 AM5 AP2 APL AP6 APS ADS AD6 AKS AKE AF33 AE33 AC29 AD29 AC25 AB25 Y26 AA25 AC28 AB28 AC27 AB27 AA29 AA28 AB26 DA26 AF31 AG31 AB31 AB30 AC34 AD34 AG32 AG33 AE32 AD32 AD31 AE31 AA31 AA30 AC32 AB32 AB33 AC33 W30 V30 T34 T33 U32 U33 V33 V32 U30 U31 V29 U28 U27 U26 AG30 AF30 AM32 AN32 A18 B37 B36 B17 B16 B33 B32 B13 B12 D5 D4 B21 B20 F5 F4 E3 E2 K8 K7 J7 J6 F8 F7 E7 E6 K11 K10 J10 J9 F11 F10 E10 E9 K14 K13 J13 J12 F14 F13 E13 E12 J16 J15 FIT F16 E16 E15 K17 K16 J19 J18 F20 F19 E19 E18 K20 K19 J22 J21 K23 K22 K26 K25 J25 J24 on on on on on on on on on on on on on on on
21. ROHIBIT ROHIBIT ROHIBIT ROHIBIT ROHIBIT H22 F21 B20 F19 C13 M12 L13 K14 F25 C29 C28 D24 See the Micron Technology Inc for more information Ref 22 In addition see the Virtex 6 FPGA Memory Interface Solutions User Guide Ref 6 and the Virtex 6 FPGA Memory Resources User Guide Ref 9 ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com 21 Chapter 1 ML605 Evaluation Board XILINX 3 128 Mb Platform Flash XL A 128 Mb Xilinx XCF128X FTG64C Platform Flash XL device is used with an onboard 47 MHz oscillator X4 to configure the FPGA in less than 100 ms from power valid as required by the PCI Express Card Electromechanical Specification This allows the PCle interface to be recognized and enumerated when plugged into a host PC To achieve the fastest configuration speed the FPGA mode pins are set to Slave SelectMAP and the onboard 47 MHz clock source external to the FPGA is used for configuration Configuration DIP switch S2 switch 1 controls the 47 MHz oscillator enable as outlined in 18 Switches page 55 See S2 switch setting details in Table 1 26 page 58 Also see the FPGA Design Considerations for the Configuration Flash page 25 for FPGA design recommendations 4 32 MB Linear BPI Flash FPGA U1 Bank 34 A Numonyx JS28F256P30 Linear BPI Flash memory P30 on the ML605 provides 32 MB of non volatile storage that can be used for configuration as wel
22. USB Type A connector J5 A USB keyboard without an internal USB hub will be able to connect to this USB Host port to demonstrate functionality The peripheral port is a USB Type Mini B J20 Table 1 16 USB Controller Connections U81 USB Controller Sa me Schematic Net Name Pin Ten Number Y32 USB A0 IS 52 GPIO19 A0 CS0 52 W26 USB A1 IS 50 50 GPIO20 A1 CS1 W27 USB CS B IS 49 49 GPIO21 CS N R33 USB D0 LS 94 GPIO0 DO 94 R34 USB D1 LS 93 GPIO1 D1 93 T30 USB D2 LS 92 GPIO2 D2 92 T31 USB D3 LS 91 GPIO3 D3 91 T29 USB D4 IS 90 GPIO4 D4 90 V28 USB D5 LS 89 GPIO5 D5 89 V27 USB D6 IS 87 GPIO6 D6 87 U25 USB D7 IS 86 GPIO7 D7 86 Y28 USB_D8_LS 66 GPIO8_D8_MISO_66 W32 USB D9 LS 65 GPIO9 D9 nSSI 65 W31 USB D10 LS 61 GPIO10 D10 SCK 61 Y29 USB D11 LS 60 GPIO11_D11_MOSI_60 W29 USB D12 LS 59 GPIO12 D12 59 Y34 USB_D13_LS 58 GPIO13_D13_58 Y33 USB_D14_LS 57 GPIO14_D14_57 Y31 USB_D15_LS 56 GPIO15_D15_SSI_N_56 Y27 USB_INT_LS 46 46_GPIO24_INT_IORDY_IRQO W25 USB RD B LS 47 47 GPIO23 RD N IOR T25 USB RESET B LS 85 RESET N 85 V25 USB WR B LS 48 48 GPIO22 WR N IOW References See the Cypress CY7C67300 Data Sheet for more information Ref 29 In addition see the USB Specifications for more information Ref 30 The FPGA requires implementation of a peripheral controller in order to communicate with the Cypress USB device See the XPS External Peripheral Controller
23. circuit It is recommended that this jumper is installed during operations utilizing the CompactFlash card Every time a CompactFlash card is inserted into the System ACE CF socket a configuration operation is initiated Pressing the System ACE CF reset button re programs the FPGA Note System ACE CF configuration is enabled by way of DIP switch S1 See 18 Switches page 55 for more details The System ACE CF MPU port is connected to the FPGA This connection allows the FPGA to use the System ACE CF controller to reconfigure the system or access the CompactFlash card as a generic FAT file system www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Table 1 6 lists the System ACE CF connections Table 1 6 System ACE CF Connections Detailed Description U19 XCCACETQ1441 U1 FPGA Pin Schematic Net Name Pin Number Pin Name AM15 SYSACE DO 66 MPD00 AJ17 SYSACE_D1 65 MPD01 AJ16 SYSACE_D2 63 MPD02 AP16 SYSACE D3 62 MPD03 AGI16 SYSACE_D4 61 MPD04 AH15 SYSACE D5 60 MPD05 AFI6 SYSACE D6 59 MPD06 AN15 SYSACE_D7 58 MPD07 AC15 SYSACE MPA00 70 MPA00 AP15 SYSACE MPA01 69 MPA01 AG17 SYSACE_MPA02 68 MPA02 AH17 SYSACE MPA03 67 MPA03 AGI5 SYSACE_MPA04 45 MPA04 AF15 SYSACE_MPA05 44 MPA05 AK14 SYSACE MPA06 43 MPA06 AJ15 SYSACE MPBRDY 39 MPBRDY AJl4 SYSACE_MPCE 42 MPCE L9 SYSACE MPIRO 41 MPIRO AL15 SYSACE_MPOE 77
24. refer to Table 1 7 Oscillator Differential The ML605 has one 2 5V LVDS differential 200 MHz oscillator U11 soldered onto the board and wired to an FPGA global clock input The 200 MHz signal names are SYSCLK_N and SYSCLK_P e Crystal oscillator SiTime SiT9102A1 243N25E200 00000 e Frequency stability 50 ppm For more details see the SiTime SiT9102 data sheet Ref 25 For more information about LVDS clocking refer to DS152 Ref 4 Oscillator Socket Single Ended 2 5V One populated single ended clock socket X5 is provided for user applications The X5 socket is populated with a 66 MHz 2 5V single ended MMD Components MBH2100H 66 000 MHz oscillator The 66 MHz signal name is USER_CLOCK For more information about LVDS clocking refer to DS152 Ref 4 ML605 Hardware User Guide www xilinx com 29 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX 2 ommlci 25 Silkscreened outline X has beveled corner ta 31 200850 BZAEBHNEBZ TAIWAN IGIN U S LEAD FREE C3 8500S 7 0B C1 10 156AGW0929 902A KHPE8 1 Mm Figure 1 7 ML605 Oscillator Socket Pin 1 Location Identifiers UG534 07 092109 30 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 Detailed Description XILINX 7 90 C1 Se Oscillator top has E j corner dot marking l SITE a N 4 E 3 31 200850 BZAEBIN992 IGIN U S LEAD FREE C3 8500S UG534 08
25. sent to the GTX driving the SGMII interface Series AC coupling capacitors are also present to allow the clock input of the FPGA to set the common mode voltage VDDA_SGMIICLK VDD_SGMIICLK ICS8440211 B t a Ma Gamz Slul El SGMIICLK_QO_C_P O 2 3 T SGMIICLK_QO_P X3 orx A y SGMIICLK XTAL OUT SGMIICLK 00 CN SGMIICLK_QO_N SGMIICLK_XTAL_IN jo BL 25 000MHZ See GND_SGMIICLK 125 00 MHz Clock UG534 13 111709 Figure 1 13 Ethernet SGMII Clock 125 MHz Table 1 13 shows the connections and pin numbers for the PHY Table 1 13 Ethernet PHYConnections U80 M88E1111 U1 FPGA Pin Schematic Net Name Pin Number Pin Name AN14 PHY_MDIO 33 MDIO AP14 PHY MDC 35 MDC AH14 PHY INT 32 INT B AH13 PHY RESET 36 RESET B AL13 PHY CRS 115 CRS AK13 PHY COL 114 COL AP11 PHY_RXCLK 7 RXCLK AG12 PHY_RXER 8 RXER AM13 PHY_RXCTL_RXDV 4 RXDV AN13 PHY RXD0 3 RXD0 AF14 PHY_RXD1 128 RXD1 AE14 PHY RXD2 126 RXD2 AN12 PHY RXD3 125 RXD3 ML605 Hardware User Guide www xilinx com 39 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board 40 Table 1 13 Ethernet PHYConnections Cont d XILINX U80 M88E1111 U1 FPGA Pin Schematic Net Name Pin Number Pin Name AM12 PHY_RXD4 124 RXD4 AD11 PHY_RXD5 123 RXD5 AC12 PHY_RXD6 121 RXD6 AC13 PHY RXD7 120 RXD7 AH12 PHY_TXC_GTXC
26. v4 2 User Guide DS581 XPS External Peripheral Controller EPC v1 02a Data Sheet DS606 XPS IIC Bus Interface v2 00a Data Sheet i i i ja rw N N N Rh me me pp m O ve AND v ML605 Hardware User Guide www xilinx com 77 UG534 v1 8 October 2 2012 Appendix A References 78 XILINX Additional documentation 22 23 24 25 26 21 28 29 30 31 32 Micron Technology Inc DDR3 SODIMM Specification MT4JSF6464HY 1G1 Winbond Serial Flash Memory Data Sheet W25Q64VSFIG Numonyx Embedded Flash Memory Data Sheet TE28F128J3D 75 SiTime Oscillator Data Sheet SiT9102AI 243N25E200 00000 MMD Components MBH Series Data Sheet MBH2100H 66 000 MHz PCI SIG PCI Express Specifications Marvell Alaska Gigabit Ethernet Transceivers Product Page Cypress Semiconductor CY7C67300 Data Sheet USB Implementers Forum Inc USB Specifications ST Micro M24C08 Data Sheet Samtec Inc www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Default Switch and Jumper Settings Appendix B Table B 34 Default Switch Settings REFDES Function Type Default SW2 Board power slide switch off User GPIO 8 pole DIP switch 8 off off 6 off SW1 5 off 4 off 3 off 2 off 1 off System ACE CF configuration and image select 4 pole DIP switch 4 SysACE Mode 1 off S1 3 SysAce C
27. 0 AM20 AN22 44 AM22 44 AL21 AM21 44 AN18 4 APIO dif AN20 if F23 F22 E22 E21 F26 F25 E25 E24 K29 K28 J28 J27 F29 F28 E28 E27 K32 K31 J31 J30 F32 F31 E31 E30 K35 K34 J34 J33 F35 F34 K38 K37 J37 J36 E34 E33 G7 G6 D9 D8 H8 H7 G10 G9 H11 H10 D12 D11 C11 C10 H14 H13 G13 G12 D15 D14 c15 C14 H17 H16 G16 G15 D18 D17 C19 on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 88 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX N p NET FMC HPC LA14 P NET FMC HPC LA15 N NET FMC HPC LA15 P NET FMC HPC LA16 N NET FMC HPC LA16 P NET FMC HPC LA17 CC N NET FMC HPC LA17 CC p NET FMC HPC LA18 CC N NET FMC HPC LA18 CC Pp NET FMC HPC LA19 N NET
28. 0 p31 D32 D33 D34 p35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DMO DM1 DM2 DM3 DM4 DM5 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC K13 K12 D11 M13 J14 B13 B12 G10 M11 C12 A11 G11 F11 D14 C14 G12 G13 F14 H14 C19 G20 E19 F20 A20 A21 E22 E23 G21 B21 H A23 A24 C20 D20 J20 G22 D26 F26 B26 H E26 C24 D25 D27 C25 C27 B28 H D29 B27 G27 A28 E24 G25 F28 B31 H29 H28 B30 A30 E29 H F29 E11 B11 E14 D19 B22 H A26 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 1
29. 092109 Figure 1 8 ML605 Oscillator Pin 1 Location Identifiers SMA Connectors Differential A high precision clock signal can be provided to the FPGA using differential clock signals through the onboard 502 SMA connectors J58 P J55 N This differential user clock has the signal names USER SMA CLOCK N and USER SMA CLOCK P ML605 Hardware User Guide www xilinx com 31 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX GTX SMA Clock The ML605 includes a pair of SMA connectors for a GTX MGT Clock as described in Figure 1 9 and Table 1 7 J30 32K10K 400E3 i SMA_REFCLK_C_N1 C6111 S z s SMA_REFCLK_N SMA_REFCLK_P lw SMA REFCLK C P1 ali SIG GND4 Sob a GND5 OFZ Sex GND6 GND7 UG534 09 081309 Figure 1 9 GTX SMA Clock Table 1 7 ML605 Clock Connections U1 FPGA Pin Schematic Net Name SMA Pin H9 SYSCLK_N U11 5 J9 SVSCLK P U1ll 4 U23 USER_CLOCK X5 5 F5 SMA REFCLK N J30 1 F6 SMA REFCLK P J31 1 M22 USER SMA CLOCK N J55 1 L23 USER SMA CLOCK P J58 1 32 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description 8 Multi Gigabit Transceivers GTX MGTs The ML605 provides access to 20 MGTs e Eight 8 of the MGTs are wired to the PCIe x8 Endpoint P1 edge connector fingers e Eight 8 of the MGTs are wired to the FMC HPC connector J64 e One 1 MGT is wired to SMA connectors J26 J2
30. 15 SODIMM Socket 204 pin DDR3 Decoupling Caps PCle X8 Edge Connector MGT SMA REF Clock MGT RX TX SMA Port BANK14 33 36 BANK24 34 BANK14 BANK24 User LED SW User DIP SW User LCD 200 MHz LVDS Clock SMA Clock User S E 2 5V Clock USB Controller Host Type A Peripheral Mini B Connectors CP2103 USB TO UART Bridge USB Mini B MEM Vterm Regulator UG534 01 092709 Figure 1 1 ML605 High Level Block Diagram Related Xilinx Documents Prior to using the ML605 Evaluation Board users should be familiar with Xilinx resources See Appendix A References for a direct link to Xilinx documentation See the following locations for additional documentation on Xilinx tools and solutions e ISE wwuwxilinx com ise e EDK www xilinx com edk e Intellectual Property www xilinx com ipcenter e Answer Browser www xilinx com support 12 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description Detailed Description Figure 1 2 shows a board photo with numbered features corresponding to Table 1 1 and the section headings in this document on backside P Lo UG534 02 091312 Figure 1 2 ML605 Board Photo The numbered features in Figure 1 2 correlate to the features and notes listed in Table 1 1 Table 1 1 ML605 Features Number Feature Notes apriematie Page 1 Virtex 6 FPGA XC6VLX240T 1FFG1156 2 12 2
31. 2C L AP25 G3 FMC HPC CLK1 M2C N AP21 H4 FMC HPC CLK0 M2C P K24 G6 FMC HPC LA00 CC P AF20 H5 FMC HPC CLKO M2C N K23 G7 FMC HPC LA00 CC N AF21 H7 FMC HPC LA02 P AC20 G9 FMC HPC LA03 P AC19 H8 FMC HPC LA02 N AD20 G10 EMC HPC LA03 N AD19 H10 FMC HPC LA04 P AF19 G12 FMC HPC LA08 P AK22 H11 FMC HPC LA04 N AE19 G13 EMC HPC LA08 N AJ22 H13 FMC HPC LA07 P AK21 G15 EMC HPC LA12 P AM21 H14 FMC_HPC_LA07_N AJ21 G16 FMC HPC LA12 N AL21 H16 FMC_HPC_LA11_P AM22 G18 FMC_HPC_LA16_P AP22 H17 FMC HPC LAN N AN22 G19 EMC HPC LA16 N AN23 H19 FMC HPC LA15 P AM23 G21 FMC HPC LA20 P AK23 H20 FMC HPC LA15 N AL23 G22 FMC HPC LA20 N AL24 H22 FMC HPC LA19 P AN25 G24 EMC HPC LA22 P AP27 H23 FMC HPC LA19 N AN24 G25 FMC HPC LA22 N AP26 H25 FMC HPC LA21 P AN29 G27 FMC HPC LA25 P AN28 H26 FMC HPC LA21 N AP29 G28 FMC HPC LA25 N AM28 H28 FMC HPC LA24 P AN30 G30 EMC HPC LA29 P AL28 H29 FMC HPC LA24 N AM30 G31 EMC HPC LA29 N AK28 H31 FMC HPC LA28 P AK27 G33 FMC HPC LA31 P AL29 H32 FMC HPC LA28 N AJ27 G34 EMC HPC LA31 N AK29 H34 FMC HPC LA30 P AJ24 G36 FMC HPC LA33 P AH23 H35 FMC HPC LA30 N AK24 62 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Table 1 28 VITA 57 1 FMC HPC Connections Cont d Detailed Description ear Schematic Net Name vi i PCE Schematic Net N
32. 64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 026 027 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 J63 ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com 89 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FMC 1 FMC FMC FMC LPC LAO5 PC LA06 FMC LPC LAO7 FMC L FMC LPC LAO8 FMC EMC EMC PC LAO9 FMC LPC LA10 FMC L FMC LPC LA11 FMC FMC FMC PC LA12 FMC LPC LA13 FMC L FMC LPC LA14 FMC FMC FMC PC LA15 FMC LPC LA16 FMC L FMC L FMC FMC FMC FMC LPC LA19 FMC L FMC LPC LA20 FMC FMC FMC PC LA21 FMC LPC LA22 FMC L FMC LPC LA23 FMC FMC FMC PC LA24 FMC LPC LA25 FMC L FMC LPC LA26 FMC FMC FMC PC LA27
33. 64008 oe VASEN TNA ea wa 67 AC Adapter and Input Power Jack Switch eee 67 Onboard Power Regulation lt s 6 0 ccc kn knn kon kon ake kaa kana ne 68 22 System MONITO wise ccd inesi och l kanali ia b ee kk tn AK kasa k 71 Configuration Options ww vw e vese looks kicks kw does vas von eee es a 76 Appendix A References Appendix B Default Switch and Jumper Settings Appendix C VITA 57 1 FMC LPC J63 and HPC J64 Connector Pinout Appendix D ML605 Master UCF Appendix E Regulatory and Compliance Information Declaration of Conformity r t ak aaa vasa aan ka cetera ve AKS eR RS 95 Directives etier l ds ii debi di e 95 Standard 213 it ot aie a os sd re oo ba e E ped 95 Electromagnetic Compatibility eeeeeeeeeeeeeeeeeeeeeeeeeeeeo 95 SAFE a tr il Le fan one 95 Markings tiara a Kaa II KUKAA salaries arriba 96 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Preface About This Guide This manual accompanies the Virtex 6 FPGA ML605 Evaluation Board and contains information about the ML605 hardware and software tools Guide Contents This manual contains the following chapters Chapter 1 ML605 Evaluation Board provides an overview of the embedded development board and details the components and features of the ML605 board Appendix B Default Switch and Jumper Settings Appendix C VITA 57 1 FMC LPC J63 and HPC J64 Connector Pinout Appendix D ML605 Ma
34. 7 e One 1 MGTs is wired to the FMC LPC connector J63 e One 1 MGT is wired to the SFP Module connector P4 e One 1 MGT is used for an SGMII connection to the Ethernet PHY U80 Note xxx MHz user specified frequency I TX XoY19 SGMII 125 MHz LVDS HH REFCLKO i l SMA xxx MHz LVDS AE ReFctki SFP FMCH2 PCle Lane1 PCle Lane 2 100 MHz LVDS FMC 2 LPC xxx MHz GBTCLKO LVDS AC coupling on Mezz PCle Lane 3 250 MHz LVDS PCle Lane 4 PCle ICS 854104 PCle Lane 5 PCle Lane 6 100 MHz in from PCle Fingers No Connect L sii REFCLKO No Connect No Connect REFCLKI PCle Lane 7 PCle Lane 8 me HEG OMN LVDS GBTCLKO A FMC 1 coupling on Mezz LVDS FMC 1 FMC 1 HPC CLK2_M2C LVDS ICS Q 854104 To FPGA CLK2_M2C_IO CC pin FMC 1 HPC xxx MHz LVDS GBTCLK1 L N AC coupling on Mezz J I LVDS REFCLKO l REFCLK1 FMC 1 HPC CLK3 M2C ICS LVDS 854104 To FPGA CLK3 M2C 10 CC pin UG534 10 021012 Figure 1 10 MGT Clocking References See the Virtex 6 FPGA GTX Transceivers User Guide Ref 12 ML605 Hardware User Guide www xilinx com 33 UG534 v1 8 October 2 2012 34 Chapter 1 ML605 Evaluation Board XILINX 9 PCI Express Endpoint Connectivity The 8 lane PCle edge connector performs data transfers at the rate of 2 5 GT s for a Genl application and 5 0 GT s for a Gen2 a
35. 7 1 FMC LPC J63 and HPC J64 Connector Pinout Any signal named FMC_LPC_xxxx that is wired between a U1 FPGA pin and some other device does not appear in this table Table 1 30 VITA 57 1 FMC LPC Connections 5 Schematic Net Name so dun Schematic Net Name ja S C2 FMC_LPC_DP0_C2M_P D1 D4 FMC_LPC_GBTCLK0_M2C_P M6 C3 FMC LPC DPO C2M N D2 D5 FMC LPC GBTCLKO M2C N M5 C6 FMC LPC DPO M2C P G3 D8 FMC_LPC_LA01_CC_P F31 C7 FMC LPC DPO M2C N GA D9 FMC_LPC_LA01_CC_N E31 C10 FMC_LPC_LA06_P K33 D11 FMC_LPC_LA05_P H34 C11 FMC_LPC_LA06_N J34 D12 FMC_LPC_LA05_N H33 C14 FMC_LPC_LA10_P F30 D14 FMC_LPC_LA09_P L25 C15 FMC_LPC_LA10_N G30 D15 FMC_LPC_LA09_N L26 C18 FMC_LPC_LA14 P C33 D17 FMC_LPC_LA13_P D34 C19 FMC LPC LA14 N B34 D18 FMC_LPC_LA13_N C34 C22 FMC_LPC_LA18_CC_P L29 D20 FMC_LPC_LA17_CC_P N28 C23 FMC_LPC_LA18_CC_N L30 D21 FMC_LPC_LA17_CC_N N29 C26 FMC_LPC_LA27_P R31 D23 FMC_LPC_LA23_P R28 C27 FMC_LPC_LA27_N R32 D24 FMC_LPC_LA23_N R27 D26 FMC_LPC_LA26_P L33 D27 FMC_LPC_LA26_N M32 G2 FMC_LPC_CLK1_M2C_P F33 H2 FMC_LPC_PRSNT_M2C_L AD9 G3 FMC_LPC_CLK1_M2C_N G33 H4 FMC LPC CLKO M2C P A10 G6 FMC LPC LA00 CC P K26 H5 FMC_LPC_CLK0_M2C_N B10 G7 FMC LPC LA00 CC N K27 H7 FMC LPC LA02 P G31 G9 FMC_LPC_LA03_P J31 H8 FMC_LPC_LA02_N H30 G10 FMC LPC LA03 N J32 H10 FMC LPC LAQA P K28 G12 FMC LPC LA08 P
36. 74 176 181 183 191 193 180 182 192 194 LI 28 46 63 136 153 on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI JI 84 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX NET DDR3 DM6 NET DDR3 DM7 NET DDR3 DOSO N NET DDR3 DOSO P NET DDR3 DOS1 N NET DDR3 DQSI P NET DDR3 DOS2 N NET DDR3 DOS2 P NET DDR3 DOS3 N NET DDR3 DOS3 P NET DDR3 DOS4 N NET DDR3 DOS4 P NET DDR3 DQS5 N NET DDR3 DQS5 P NET DDR3 DOS6 N NET DDR3 DOS6 P NET DDR3 DOS7 N NET DDR3 DOS7 P NET DDR3 ODTO NET DDR3 ODTI NET DDR3 RAS B NET DDR3 RESET B NET DDR3 SO B NET DDR3 S1 B NET DDR3 TEMP EVENT NET DDR3 WE B HH NET DVI DO NET DVI Di NET DVI D2 NET DVI D3 NET DVI D4 NET DVI D5 NET DVI D6 NET DVI D7 NET DVI D8 NET DVI D9 NET DVI D10 NET DVI D11 NET DVI DE NET DVI GPIO1 FMC C2M PG IS NET DVI H NET DVI RESET B IS NET DVI V NET
37. AK11 LCD_DB5_LS 3 AJ LCD_DB6_LS 2 AE12 LCD_DB7_LS 1 AC14 LCD_RW_LS 10 T28 LCD_RS_LS 11 AK12 LCD E IS 9 54 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX 18 Switches Detailed Description The ML605 Evaluation board includes the following switches e Power On Off Slide Switch SW2 e FPGA_PROG_B SW4 active Low e SYSACE RESET B SW3 active Low e System ACE CF CompactFlash Image Select DIP Switch S1 active High e MODE Boot EEPROM Select and CCLK Osc Enable DIP switch 52 active High Power On Off Slide Switch SW2 SW2 is the ML605 board main power on off switch Sliding the switch actuator from the off to on position applies 12V power from either J60 6 pin Mini Fit or J25 4 pin ATX power connector to the VCC12 P power plane via the 1m421 3W series current sense resistor R346 See 22 System Monitor page 71 for further details on 12V input current sensing Green LED DS25 will illuminate when the ML605 board power is on See section 21 Power Management page 67 for details on the onboard power system VCC12 P IN e VCC12 P DPDT R346 Power ATX Peripheral Cable Connector can plug into J25 when ML605 is in PC and the desk top AC adapter brick is not used J25 1 2 C280 E2 OLF 0 5 0 001R 2 1 16w 16V Y14880R00100B09R v ELEC sw2 awe 1201M2S3ABE2 3 Y o Ix z o lo 3 CAUTION DO NOT plug a PC ATX power supply 6 pin
38. B to UART Bridge scrise saa dv aaa sede VYT SIN NN SEN SN RA INN aa dea 41 13 USB Controller ooo 24455 feiss aa a BR A A ES 42 M DVI Codec six seduce tn so avs ou don k s K LVI B N hate arte KA saaa at haan 43 15 JIE BWS ii INES ASEA LASK a a ai KSS wade a AIR 44 8 KD NV Memory s siwi saba Bar ed ode boots PSN eee ala VAIN daa 46 16 Status LEDS opeens peere naair A A KASAN add Reda ASSA 47 Ethernet PHY Status LEDs e seee eeeeeoseueeseueusenucuns 48 FPGA INIT and DONE LEDs 1 2 ee n an n ka na n n n ann 49 V7 User IO aasian sat A EUS oN e ak A SRS A Na ee io 49 User LEDS ise ew ees A eee Ae Re Ree AA AAA ARA A any 50 User Pushbutton Switches 0c cetaa errai eataa kan an kan enn n 51 User DIP Switch a bn wie ala asa a ee ee ae a 52 User SMA GPIO 0 Sana ba A beet ened eee eee ee dk ed 53 LCD Display 16 Character x 2 Lines 54 18 SWIC hes sa masa nate ei edule head so Kasa ganas a aa tate 55 Power On Off Slide Switch SW2 6 eee 55 ML605 Hardware User Guide www xilinx com UG534 v1 8 October 2 2012 XILINX FPGA_PROG_B Pushbutton SW4 Active Low 0 2 0 0 ccc cee ee eee eens 56 SYSACE RESET B Pushbutton SW3 Active LOW LL 56 System ACE CF CompactFlash Image Select DIP Switch SI 57 Mode Osc Enable Boot EEPROM Select and Addr Select DIP Switch S2 58 19 VITA 57 1 FMC HPC Connector 0 eee 59 20 VITA 57 1 FMC LPC Connector eee 65 21 Powet Managements ss 006
39. B23 B28 B27 B34 B33 B38 B37 B42 B41 B46 B45 A17 A16 A22 A21 A26 A25 A30 A29 A36 A35 A40 A39 A44 A43 A48 A47 B11 114 115 32 35 33 36 128 126 125 124 123 121 120 10 16 14 18 19 20 24 25 26 28 29 13 SEE on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl Pl U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 U80 NET FLASH NN GROUP 92 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX NET PMBUS ALERT LS NET PMBUS CLK LS NET PMBUS CTRL LS NET PMBUS DATA LS HH NET SFP LOS NET SFP RX N NET SFP RX P NET SFP TX DISABLE FPGA NET SFP TX N NET SFP TX P HH NET SGMIICLK_QO_N NET SGMIICLK QO P NET SGMII RX N NET SGMII RX P NET SGMII TX N NET SGMII TX P HH NET SMA REFCLK N NET SMA REFCLK P NET SMA RX N NET SMA RX P NET SMA TX N NET SMA TX P HH NET SM FAN PWM NET SM FAN TACH HH NET SYSACE CFGTDI NET SYSACE DO NET SYSACE D1 NET SYSACE D2 NET SYSACE D3 NET SYSACE
40. C AJ12 H 2 on S2 DIP switch active High 1 on U10 HH NET PCIE 100M MGTO_N LOC P5 Hf 15 on Ul4 NET PCIE 100M MGTO P LOC P6 16 on U14 NET PCIE 250M MGT1 N LOC v5 18 on U9 NET PCIE 250M MGT1 P LOC V6 17 on U9 NET PCIE PERST B LS LOC AE13 HH 4 on U32 NET PCIE RXO N LOC J4 Hf B15 on P1 ML605 Hardware User Guide www xilinx com UG534 v1 8 October 2 2012 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET HH NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET HH NET PLATFLASH L B PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PHY PHY PHY PHY PHY E RX0 p E RX1 N E RX1 p E RX2 N E RX2 p E RX3 N E RX3 p E RX4 N E RX4 p E RX5 N E RX5 p E RX6 N E RX6 p E RX7 N E RX7 p E TXO N E TX0 p E TX1 N E TX1 p E TX2 N E TX2 p E TX3 N E TX3 p E TX4 N E TX4 p E TX5 N E TX5 p E TX6 N E TX6 p E TX7 N E TX7 E WAKE B LS COL CRS INT
41. C HA00 CC N AF33 E7 FMC_HPC_HA05_N AC27 F7 FMC HPC HA04 P AB28 F9 FMC HPC HA09 P AB30 F8 FMC HPC HA04 N AC28 F10 FMC HPC HA09 N AB31 F10 FMC HPC HA08 P AG31 E12 FMC HPC HA13 P AF31 F11 FMC_HPC_HA08_N AF31 F13 FMC_HPC_HA13_N AD31 F13 FMC_HPC_HA12_P AD32 E15 FMC_HPC_HA16_P AC33 F14 FMC HPC HA12 N AF32 E16 FMC HPC HAl6 N AB33 F16 FMC HPC HA15 P AB32 E18 FMC HPC HA20 P V32 F17 FMC HPC HA15 N AC32 F19 FMC_HPC_HA20_N V33 F19 FMC_HPC_HA19_P U33 F21 FMC_HPC_HB03_P AL30 F20 FMC_HPC_HA19_N U32 E22 FMC_HPC_HB03_N AM31 F22 FMC HPC HB02 P AP32 E24 FMC HPC HB05 P AN33 F23 FMC HPC HB02 N AP33 ML605 Hardware User Guide www xilinx com 61 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board Table 1 28 VITA 57 1 FMC HPC Connections Cont d XILINX en Schematic Net Name vi ST pect Schematic Net Name us tee F25 FMC HPC HB05 N AN34 F25 FMC HPC HB04 P AM33 E27 FMC HPC HB09 P AL34 F26 FMC HPC HB04 N AL33 F28 FMC HPC HB09 N AK34 F28 FMC HPC HB08 P AK33 E30 FMC HPC HB13 P AH33 F29 FMC HPC HB08 N AK32 F31 FMC HPC HB13 N AH32 F31 FMC HPC HB12 P AJ31 E33 FMC HPC HB19 P AL31 F32 FMC HPC HB12 N AJ32 E34 FMC HPC HB19 N AK31 F34 FMC HPC HB16 P AH29 F35 FMC HPC HB16 N AH30 G2 FMC_HPC_CLK1_M2C_P AP20 H2 FMC HPC PRSNT M
42. C2 FMC HPC DPO C2M P ABI D4 FMC HPC GBTCLKO M2C P AD6 C3 FMC HPC DPO C2M N AB2 D5 FMC HPC GBTCLKO M2C N AD5 C6 FMC HPC DPO M2C P AC3 D8 FMC HPC LA01 CC P AK19 C7 FMC HPC DPO M2C N AC4 D9 FMC HPC LA01 CC N AL19 60 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description Table 1 28 VITA 57 1 FMC HPC Connections Cont d cer Schematic Net Name vi ie CEI Schematic Net Name a a hy C10 FMC HPC LA06 P AG20 D11 FMC HPC LA05 P AG22 C11 FMC HPC LA06 N AG21 D12 FMC_HPC_LA05_N AH22 C14 FMC_HPC_LA10_P AM20 D14 FMC_HPC_LA09_P AM18 C15 FMC_HPC_LA10_N AL20 D15 FMC HPC LA09 N AL18 C18 FMC_HPC_LA14 P AN19 D17 FMC HPC LA13 P AP19 C19 FMC_HPC_LA14_N AN20 D18 FMC_HPC_LA13_N AN18 C22 FMC HPC LA18 CC P AH25 D20 FMC_HPC_LA17_CC_P AN27 C23 FMC HPC LA18 CC N AJ25 D21 FMC HPC LA17 CC N AM27 C26 FMC HPC LA27 P AP30 D23 FMC HPC LA23 P AL26 C27 FMC HPC LA27 N AP31 D24 FMC HPC LA23 N AM26 C30 1IC SCL MAIN Is AK9 D26 FMC HPC LA26 P AM25 C31 IIC SDA MAIN LSW AE9 D27 FMC_HPC_LA26_N AL25 D29 FMC_HPC_TCK_BUF U88 15 D30 FMC TDI BUFQ J17 1 D31 FMC HPC TDOQ J17 3 D33 FMC TMS BUFQ U88 17 E2 FMC HPC HA01 CC P AD29 FI FMC HPC PG M2C 1L8 J27 E3 FMC_HPC_HA01_CC_N AC29 F4 FMC_HPC_HA00_CC_P AE33 E6 FMC HPC HA05 P AB27 F5 FMC HP
43. C2M P FMC HPC DP3 M2C N FMC HPC DP3 M2C P FMC HPC DP4 C2M N FMC HPC DP4 C2M P FMC HPC DP4 M2C N FMC HPC DP4 M2C P FMC HPC DP5 C2M N FMC HPC DP5 C2M P FMC HPC DP5 M2C N LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC APO AN9 AF10 AF9 AL9 AA23 AF24 AF25 W24 V24 H24 H25 P24 R24 G23 H23 N24 N23 F23 F24 L24 M23 326 AF23 DA24 K8 AC23 Y24 K23 K24 AP21 AP20 AC30 AD30 ABS AB6 AF34 AE34 AHS AH6 AB2 AB1 ACA AC3 AD2 AD1 AEA AE3 AF2 AFL AF6 AF5 AH2 AHL AGA AG3 AK2 AK1 AJA AJ3 AM2 AM1 ALA HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH 30 on U4 17 16 11 10 26 34 36 39 41 47 49 51 53 35 37 40 42 48 50 52 54 56 14 32 on on on on on on on on on on on on on on on on on on on on on on on on on U4 B7 on U27 U4 C7 on U27 U4 C8 on U27 U4 A8 on U27 U4 Gl on U27 U4 U4 thru series U4 thru series U4 thru serie
44. CLK1 N LOC L16 104 on J1 NET DDR3 CLK1 P LOC K16 102 on J1 NET DDR3 DO LOC J11 5 on JI NET DDR3 D1 LOC E13 7 on J1 NET DDR3_D2 LOC F13 15 on JI NET DDR3_D3 LOC K11 17 on JI NET DDR3_D4 LOC L11 HH 4 on J1 ML605 Hardware User Guide www xilinx com 83 UG534 v1 8 October 2 2012 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET D DO OO 0 0 0 OO Oo 0 OO Y 0 00 O 00 OTO GOTOO Y O Oo 00 DEO 0 00 0 Oo OO 000 Y 0 OO Oe eo 00 0 0 0 GI O 0 000 0 0 0 0 oO y Co OO OOO O O O 0 00 0 0 00 0 0 0 OO YU Y Co O 0 0 0 0 O O O 0 OO 0 OOO OO OOO O y Co UU VOU R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 l R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 R3 l D5 D6 D7 D8 D9 D10 DIl D12 DI3 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3
45. D4 NET SYSACE D5 NET SYSACE D6 NET SYSACE D7 NET SYSACE MPA00 NET SYSACE MPA01 NET SYSACE MPA02 NET SYSACE MPA03 NET SYSACE MPA04 NET SYSACE MPA05 NET SYSACE MPA06 NET SYSACE MPBRDY NET SYSACE MPCE NET SYSACE MPIRO NET SYSACE MPOE NET SYSACE MPWE HH NET SYSCLK N NET SYSCLK P HH NET USB 1 CTS NET USB 1 RTS NET USB 1 RX NET USB 1 TX HH NET USB A0 LS NET USB A1 LS NET USB CS B LS NET USB D0 LS NET USB D1 LS NET USB D2 LS LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AHO AC1O ATO AB10 V23 EA E3 AP12 Can C3 HS He B6 B5 AA A3 ES FE D6 D5 B2 B1 L10 M10 ACB AM15 AJ17 AJ16 AP16 AG16 AH15 AF16 AN15 AC15 AP15 AG17 AH17 AG15 AF15 AK14 AJ15 AJ14 LO AL15 AL14 Ho J9 T24 T23 J25 J24 y32 W26 W27 R33 R34 T30 HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH
46. DDR3_DOS0_P 12 DQSO P J12 DDR3_DQS1_N 27 DOS1_N H12 DDR3_DOS1_P 29 DOS1_P Al4 DDR3_DQS2_N 45 DOS2 N A13 DDR3 DOS2 P 47 DOS2 P H20 DDR3_DQS3_N 62 DOS3 N H19 DDR3 DOS3 P 64 DOS3 P C23 DDR3 DOS4 N 135 DOS4 N B23 DDR3 DOS4 P 137 DOS4 P A25 DDR3 DOS5 N 152 DOS5 N B25 DDR3 DOS5 P 154 DOS5 P G28 DDR3 DOS6 N 169 DOS6 N H27 DDR3_DQS6_P 171 DQS6_P D30 DDR3_DQS7_N 186 DQS7_N 20 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description Table 1 4 DDR3 SODIMM Connections Cont d J1 SODIMM U1 FPGA Pin Schematic Net Name Pin Number Pin Name C30 DDR3 DOS7 P 188 DOS7 P F18 DDR3 ODTO 116 ODTO E17 DDR3_ODT1 120 ODT1 E18 DDR3_RESET_B 30 RESET_B K18 DDR3 SO B 114 so B K17 DDR3 SI B 121 S1 B D17 DDR3 TEMP EVENT 198 EVENT B B17 DDR3 WE B 113 WE B C17 DDR3_CAS_B 115 CAS B L19 DDR3 RAS B 110 RAS B M18 DDR3 CKEO 73 CKEO M17 DDR3_CKE1 74 CKE1 H18 DDR3 CLKO N 103 CKO_N G18 DDR3 CLKO P 101 CKO P L16 DDR3 CLKI N 104 CK1 N K16 DDR3 CLK1 P 102 CKI P The Memory Interface Generator MIG tool guidelines specify a set of UI FPGA No Connect pins These should be added to the UCF as CONFIG PROHIBIT pins as follows References CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG P P P P v U U U v U U U ROHIBIT ROHIBIT ROHIBIT ROHIBIT ROHIBIT ROHIBIT ROHIBIT
47. DVI XCLK N NET DVI XCLK P HH NET FI NET FI NET FI NET FI NET FI NET FI NET FI NET FI NET FI NET FI NET FI NET FI NET FI NET FI NET FI NET FI NET FI NET FI LASH AO LASH A1 LASH A2 LASH A3 LASH A4 LASH AS LASH A6 LASH A7 LASH A8 LASH A9 LASH A10 LASH A11 LASH A12 LASH A13 LASH A14 LASH A15 LASH A16 LASH A17 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC A29 A31 E12 D12 J12 H12 A14 A13 H20 H19 C23 B23 A25 B25 G28 H27 D30 C30 F18 ELT L19 E18 K18 K17 D17 B17 AJ19 AH19 AM17 AM16 AD17 AE17 AK18 AK17 AE18 AF18 AL16 AK16 AD16 KO AN17 AP17 AD15 AC17 AC18 ALB AKS ACO AD10 cg B8 E9 ES A8 A9 D9 Cg D10 C10 F10 FO AH8 AG8 HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH 170 187 10 12 27 29 45 47 62 64 135 137 152 154
48. E Off SFP Disabled On SFP Enabled Test Point J53 SFP MOD DETECT High Module Not Present Low Module Present Jumper J54 SFP RT SEL Jumper Pins 1 2 Full Bandwidth Jumper Pins 2 3 Reduced Bandwidth Test Point J51 SFP LOS High Loss of Receiver Signal Low Normal Operation ML605 Hardware User Guide www xilinx com 37 UG534 v1 8 October 2 2012 38 Chapter 1 ML605 Evaluation Board XILINX Table 1 10 SFP Module Connections P4 SFP Module Connector U1 FPGA Pin Schematic Net Name Pin Number Pin Name F3 SFP RX P 13 RDP 13 F4 SFP RX N 12 RDN 12 C3 SFP_TX_P 18 TDP_18 C4 SFP_TX_N 19 TDN_19 V23 SFP LOS 8 LOS AP12 SFP TX DISABLEM 3 TX DISABLE Notes 1 The SFP TX Disable pin 3 is driven by transistor Q22 the base of which is driven by the FPGA signal SFP_TX_DISABLE_FPGA 11 10 100 1000 Tri Speed Ethernet PHY The ML605 utilizes the onboard Marvell Alaska PHY device 88E1111 for Ethernet communications at 10 100 or 1000 Mb s The board supports MII GMI RGMII and SGMII interfaces from the FPGA to the PHY Table 1 11 The PHY connection to a user provided Ethernet cable is through a Halo HFJ11 1G01E RJ 45 connector with built in magnetics Table 1 11 PHY Default Interface Mode Jumper Settings Mode J66 J67 J68 GMII MII to copper i A default Jumper over pins 1 2 Jumper over pi
49. FGAddr 2 0 off 2 SysAce CFGAddr 1 0 off 1 SysAce CFGAddr 0 0 off FPGA mode boot PROM select and FPGA CCLK select 6 pole DIP switch 6 FLASH_A23 0 off 5 M2 0 off 2 4 M1 1 S M 2 0 010 Master BPI Up 3 M0 0 off 2 CS SEL 1 boot from BPI Flash on 1 EXT_CCLK 0 off Notes 1 S1 position 4 is the System ACE controller enable switch When ON this switch allows the System ACE to boot at power on if it finds a CF card present In order to boot from BPI Flash or Xilinx Platform Flash without System ACE contention S1 switch 4 must be OFF ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com Appendix B Default Switch and Jumper Settings 80 Table B 35 Default Jumper Settings XILINX Jumper REFDES Function Default J69 System ACE CF Error LED Enable Jump 1 2 GMII 166 Bing 2 3 SGMI to Cu no clk jump 1 2 J7 Bing 23 SGM to Cu no clk Jump 1 2 J68 J66 pins 1 2 J68 ON RGMII modified MII in Cu no jumper FMC JTAG Bypass J18 exclude FMC LPC connector Jump 1 2 J17 exclude FMC HPC connector Jump 1 2 System Monitor J19 Test mon vrefp sourced by U23 REF3012 Jump 1 2 J35 measure voltage across R kelvin on VCCINT Rapa Jump 10 12 SFP Module J54 Full BW Jump 1 2 J65 SFP Enable Jump1 2 PCIe Lane Size J42 1 lane Jump1 2 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Appe
50. HH HH HH HH HH HH HH HH HH HH HH HH N N NPN N 12 13 19 H H H H N N H H H p H H 81 66 65 63 62 61 60 59 58 70 69 68 67 45 44 43 39 42 41 77 76 22 23 24 25 14 18 14 6 on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on Q15 Q18 Q16 017 P4 P4 P4 Q22 P4 P4 series series series series series series series series series series J27 SMA J26 SMA Q24 R368 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U34 U34 U34 U34 U30 U29 U29 U31 U31 U31 C55 0 1uF C56 0 1uF C163 0 01uF C162 0 01uF C164 0 01uF C165 0 01uF C61 0 luF C62 0 luF C57 0 luF C58 0 1uF Uli 5 on U89 U11 4 on U89 DNP DNP ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com 93 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET HH NET NET NET NET NET HH NET NET NET NET USB D3 LS USB D4 LS USB D5 LS USB D6 LS USB D7 LS USB D8 LS USB D9 LS USB D10 LS USB D11 LS USB D12 LS USB D13 LS USB D14 LS USB D15 LS USB INT LS USB RD B LS USB RESET B LS
51. H_A15 1 A16 D7 A15 AH8 FLASH_A16 55 A17 D8 A16 AG8 FLASH_A17 18 A18 A7 A17 AP9 FLASH_A18 17 A19 B7 A18 AN9 FLASH A19 16 A20 C7 A19 AF10 FLASH A20 11 A21 C8 A20 AF9 FLASH A21 10 A22 A8 A21 AL9 FLASH_A22 9 A23 Gl A22 AA23 FLASH_A23 26 A24 NC A23 ML605 Hardware User Guide www xilinx com 23 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX Table 1 5 Platform Flash and BPI Flash Connections Cont d U4 BPI Flash U27 Platform Flash U1 FPGA Pin Schematic Net Name Pin Number Pin Name Pin Number Pin Name AF24 FLASH D0 34 DO0 F2 DO00 AF25 FLASH DI 36 DO1 F2 DO01 W24 FLASH D2 39 DQ2 G3 DO02 V24 FLASH D3 41 DQ3 E4 DO03 H24 FLASH D4 47 DO4 E5 DO04 H25 FLASH D5 49 DO5 G5 DO05 P24 FLASH D6 51 DQ6 G6 DQ06 R24 FLASH_D7 53 DQ7 H7 DO07 G23 FLASH D8 35 DO8 E1 DO08 H23 FLASH D9 37 DO9 E3 DO09 N24 FLASH D10 40 DO10 F3 DO10 N23 FLASH D11 42 DON F4 DON F23 FLASH D12 48 DQ12 F5 DQ12 F24 FLASH_D13 50 DQ13 H5 DQ13 L24 FLASH D14 52 DQ14 G7 DQ14 M23 FLASH_D15 54 DO15 E7 DO15 J26 FLASH_WAIT 56 WAIT NA NAO AF23 FPGA_FWE_B 14 WE G8 W AA24 FPGA FOE B 32 OE F8 G K8 FPGA_CCLK NA NA FI K AC23 PLATFLASH L B NA NAO H1 L Y24 FPGA FCS B0 NA NA NA NAQ NAY PLATFLASH FCS BO NA NAO B4 E NA FLASH CE BO 30 OE NA NAQ Notes 1 Not Applicable 2 FPGA control flash memory select signal connected to pin U10 3 3
52. J30 H11 FMC_LPC_LA04_N J29 G13 FMC_LPC_LA08_N K29 H13 FMC_LPC_LA07_P G32 G15 FMC_LPC_LA12_P E32 H14 FMC LPC LA07 N H32 G16 FMC_LPC_LA12_N E33 H16 FMC_LPC_LA11_P D31 G18 FMC_LPC_LA16_P A33 H17 FMC LPC LA1I1 N D32 G19 FMC_LPC_LA16_N B33 H19 FMC_LPC_LA15_P C32 66 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Table 1 30 VITA 57 1 FMC LPC Connections Cont d Detailed Description odu Schematic Net Name Ma s odo Schematic Net Name a v G21 FMC_LPC_LA20_P P29 H20 FMC_LPC_LA15_N B32 G22 FMC_LPC_LA20_N R29 H22 FMC_LPC_LA19_P M30 G24 FMC LPC LA22 P N27 H23 FMC_LPC_LA19_N N30 G25 FMC LPC LA22 N P27 H25 FMC LPC LA21 P R26 G27 FMC_LPC_LA25_P P31 H26 FMC LPC LA21 N T26 G28 FMC_LPC_LA25_N P30 H28 FMC_LPC_LA24 P N32 G30 FMC_LPC_LA29_P N34 H29 FMC_LPC_LA24 N P32 G31 FMC_LPC_LA29_N P34 H31 FMC LPC LA28 P N33 G33 FMC LPC LA31 P M31 H32 FMC_LPC_LA28_N M33 G34 FMC_LPC_LA31_N L31 H34 FMC_LPC_LA30_P M26 G36 FMC_LPC_LA33_P K32 H35 FMC LPC LA30 N M27 G37 FMC LPC LA33 N K31 H37 FMC_LPC_LA32_P N25 H38 FMC_LPC_LA32_N M25 References See the data sheet for the ROHS compliant FMC HPC Samtec SEARAY connector carrier side socket ASP 134486 01 module side plug ASP 134488 01 and the high speed characterization report for this connector system on the Samtec website Ref 32 21 Power Manageme
53. LED Group 2 directional 5 User pushbuttons directional 5 CPU reset pushbutton User DIP switch GPIO 8 pole User SMA GPIO connectors 2 LCD character display 16 characters x 2 lines Switches Power on off slide switch System ACE CF reset pushbutton System ACE CF bitstream image select DIP switch Configuration MODE DIP switch VITA 57 1 FMC HPC Connector VITA 57 1 FMC LPC Connector Power Management PMBus voltage and current monitoring via TI power controller 22 System Monitor Configuration Options 3 128 Mb Platform Flash XL 4 32 MB Linear BPI Flash 5 System ACE CF and CompactFlash Connector 6 USB JTAG www xilinx com 11 Chapter 1 ML605 Evaluation Board XILINX Block Diagram Figure 1 1 shows a high level block diagram of the ML605 and its peripherals System ACE CF S A CompactFlash S A 8 bit MPU I F JTAG USB Mini B USB JTAG Circuit VITA 57 1 FMC HPC Connector VITA 57 1 FMC LPC Connector BANK32 Platform Flash Linear BPI Flash BANK24 BANK12 13 BANK15 16 BANK14 22 BANK34 116 BANK23 24 SYSMON I F INIT DONE LEDs PROG PB MODE SW BANK34 BANK112 113 BANKO IIC Bus IIC EEPROM FMC HPC DDR3 SODIMM IIC FMC LPC DVI Codec VGA Video DVI Video Connector BANK32 BANK33 BANK34 Virtex 6 FPGA XC6VLX240T 1FFG1156 10 100 1000 Ethernet PHY MII GMII RMII SFP Module Connector SGMII BANK33 BANK116 BANK 25 35 BANK 26 36 BANK114 BANK1
54. LK 14 GTXCLK AD12 PHY_TXCLK 10 TXCLK AH10 PHY_TXER 13 TXER AJ10 PHY_TXCTL_TXEN 16 TXEN AMI1 PHY TXDO 18 TXDO ALI PHY_TXD1 19 TXD1 AG10 PHY_TXD2 20 TXD2 AGI1 PHY TXD3 24 TXD3 AL10 PHY TXD4 25 TXD4 AM10 PHY_TXD5 26 TXD5 AE11 PHY_TXD6 28 TXD6 AF11 PHY_TXD7 29 TXD7 A3 SGMII_TX_P 113 SIN_P A4 SGMII_TX_N 112 SIN_N B5 SGMII_RX_P 107 SOUT_P B6 SGMII RX N 105 SOUT N References See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information Ref 28 Also see the LogiCORE IP Tri Mode Ethernet MAC User Guide Ref 19 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description 12 USB to UART Bridge The ML605 contains a Silicon Labs CP2103GM USB to UART bridge device U34 which allows connection to a host computer with a USB cable The USB cable is supplied in this evaluation kit Type A end to host computer Type Mini B end to ML605 connector J21 Table 1 14 details the ML605 J21 pinout Xilinx UART IP is expected to be implemented in the FPGA fabric for instance Xilinx XPS UART Lite The FPGA supports the USB to UART bridge using four signal pins Transmit TX Receive RX Request to Send RTS and Clear to Send CTS Silicon Labs provides royalty free Virtual COM Port VCP drivers which permit the CP2103GM USB to UART bridge to appear as a COM port to host computer communications application software for example HyperTerm or TeraTerm The VCP
55. LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC AN19 AL23 AM23 AN23 AP22 AM27 AN27 AJ25 AH25 AN24 AN25 AL24 AK23 AP29 AN29 AP26 AP27 AM26 AL26 AM30 AN30 AM28 AN28 AL25 AM25 AP31 AP30 AJ27 AK27 AK28 AL28 AK24 AJ24 AK29 AL29 AG26 AG25 AH24 AH23 J27 AP25 B10 A10 G33 E33 D2 DI Gan G3 M5 M6 AF13 AG13 K27 K26 E31 E31 H30 G31 332 J31 J29 K28 H33 HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH C18 H20 H19 G19 G18 D21 D20 C23 C22 H23 H22 G22 G21 H26 H25 G25 G24 D24 D23 H29 H28 G28 G27 D27 D26 C27 C26 H32 H31 G31 G30 H35 H34 G34 G33 H38 H37 G37 G36 FI H2 H5 H4 G3 G2 C3 C2 C7 C6 D5 D4 G7 G6 D9 D8 H8 H7 G10 G9 H11 H10 D12 on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on of of on on on on on on on on on on on J64 J
56. MB Linear BPI Flash page 22 for details 19 VITA 57 1 FMC HPC Connector The ML605 implements both the High Pin Count HPC J64 and Low Pin Count LPC J63 connector options of VITA 57 1 1 FMC specification This section discusses the FMC HPC J64 connector Note The FMC HPC J64 connector is a keyed connector oriented so that a plug on card faces away from the ML605 board The FMC standard calls for two connector densities a High Pin Count HPC and a Low Pin Count LPC implementation A common 10 x 40 position 400 pin locations connector form factor is used for both versions The HPC version is fully populated with 400 pins present and the LPC version is partially populated with 160 pins The 10 x 40 rows of a FMC HPC connector provides connectivity for e 160 single ended or 80 differential user defined signals e 10MGTs e 2 MGT clocks e 4 differential clocks e 159 ground 15 power connections Of the above signal and clock connectivity capability the ML605 implements the following subset e 78 differential user defined pairs e 34 LA pairs e 24 HA pairs e 20 HB pairs e 8MGTs ML605 Hardware User Guide www xilinx com 59 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX e 2 MGT clocks e 4 differential clocks Note The ML605 board VADJ voltage for the FMC HPC and LPC connectors J64 and J63 is fixed at 2 5V non adjustable The 2 5V rail cannot be turned off The ML605 VITA 57 1 FMC in
57. ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX amp XILINX Copyright 2009 2012 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Virtex Zyng and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners DISCLAIMER The information disclosed to you hereunder the Materials is provided solely for the selection and use of Xilinx products To the maximum extent permitted by applicable law 1 Materials are made available AS IS and with all faults Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability for any loss or damage of any kind or nature related to arising under or in connection with the Materials including your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct
58. NN GROUP 90 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX NET FPGA FWE B LOC AF23 SEE NET FLASH NN GROUP HH NET FPGA INIT B LOC P8 HH 1 on 014 INIT LED DS31 driver NET FPGA MO LOC U8 3 on S2 DIP switch active High NET FPGA M1 LOC W8 HH 4 on S2 DIP switch active High NET FPGA M2 LOC V8 4 on S2 DIP switch active High NET FPGA PROG B LOC L8 HH l on SW4 pushbutton active Low NET FPGA TCK LOC AE8 80 on U19 NET FPGA TDI LOC AD8 82 on U19 NET FPGA TMS LOC AF8 85 on U19 NET FPGA VBATT LOC N8 HH l on B1 battery terminal HH NET GPIO DIP swi LOC D22 1 on SWI DIP switch active High NET GPIO DIP SW2 LOC C22 2 on SWI DIP switch active High NET GPIO DIP SW3 LOC L21 3 on SWI DIP switch active High NET GPIO DIP SW4 LOC L20 4 on SWI DIP switch active High NET GPIO DIP SWS LOC C18 5 on SWI DIP switch active High NET GPIO DIP SW6 LOC B18 6 on SWI DIP switch active High NET GPIO DIP SW7 LOC K22 7 on SWI DIP switch active High NET GPIO DIP Swe LOC K21 8 on SWI DIP switch active High HH NET GPIO LED O LOC AC22 2 on LED DS12 1 on J62 NET GPIO LED 1 LOC AC24 Hf 2 on LED DS11 2 on J62 NET GPIO LED 2 LOC AE22 2 on LED DS9 3 on J62 NET GPIO LED 3
59. Platform Flash select signal connected to pin U10 6 4 BPI Flash select signal connected to pin U10 4 24 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description FPGA Design Considerations for the Configuration Flash After FPGA configuration the FPGA design can disable the configuration flash or access the configuration flash to read write code or data When the FPGA design does not use the configuration flash the FPGA design must drive the FPGA FCS_B pin High in order to disable the configuration flash and put the flash into a quiescent low power state Otherwise the Platform Flash XL in particular can continue to drive its array data onto the data bus causing unnecessary switching noise and power consumption For FPGA designs that access the flash for reading writing stored code or data connect the FPGA design or EDK embedded memory controller EMC peripheral to the flash through the pins defined in Table 1 5 page 23 The Platform Flash XL defaults to a synchronous read mode Typically the Platform Flash XL requires an initialization procedure to put the Platform Flash XL into the common asynchronous read mode before accessing stored code or data To put the Platform Flash XL into asynchronous read mode apply the Set Configuration Register command sequence See the Platform Flash XL High Density Configuration and Storage Device Data Sheet for details on the Set Configuration Regis
60. REF3012AIDBZT C79 X5R 10v 0 1UF NY Ferrie Bead AGND Jumper on pins 1 2 Default Setting 1 2 Select External Reference NY AGND 2 3 Select On Chip Reference UG534_29_081209 Figure 1 29 System Monitor External Reference ML605 Hardware User Guide www xilinx com 71 UG534 v1 8 October 2 2012 72 Chapter 1 ML605 Evaluation Board XILINX System Monitor Header J35 Figure 1 30 shows the pinout for the System Monitor 12 pin header The header provides user access to the analog power supply Ayqq and the 1 25V reference shown in Figure 1 29 page 71 Access to the FPGA thermal diode and dedicated analog input channel Vp Vn is also provided on this header The header can be used to connect user specific analog signals and sensors to the system monitor The kelvin points for a 5 mQ current sensing shunt in the FPGA 1V V cint core supply are also available on this header By connecting header pins 9 to 11 and 10 to 12 using jumpers the system monitor can be used to monitor the FPGA core current and power consumption This can be used to collect useful power information about a particular design or implementation N FPGA System Monitor Tkernat Diode Header J35 e s FPGA DX P FPGA DX N SXSMON AVDD 1 25V Reference Anti alias Filter ccint shunt P Vecint shunt N 1 16W SXSMON VN SXSMON VP To Measure VCCINT Current Dedicated Analog Inputs Jumper o
61. SACE RESET Pushbutton 1 4 2 3 UG534 25 073109 Figure 1 25 System ACE CF RESET B Pushbutton SW3 56 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash CF image select DIP switch S1 switches 1 3 select which CF resident bitstream image is downloaded to the FPGA Figure 1 26 SI switches 1 3 offer eight binary addresses When ON High the S1 switch 4 enables the System ACE CF controller to configure the FPGA from the CF card when a card is inserted or when the SYSACE RESET button is pressed See 5 System ACE CF and CompactFlash Connector page 26 for more details about the System ACE controller VCC2V5 1 16W 1 16W 1 16W Del 5 5 5 R62 5 N 1 16W VW 510 W WW 510 510 WN 510 o st Lo S1 O O LO a a a 5 4 A s 1 SYSACE CFGMODEPIN 7 AN O M SYSACE CFGADDR2 8 Bi e M SYSACE CFGADDR1 6 M SYSACE CFGADDRO n SDMX 4 X 2 1 00K Wo v 1 00K o 1 00K o MW 1 00K WWW v 1 16W 1 16W 1 16W T O o O O LO 10 a E a a o oo n UG534 26 110409 Figure 1 26 System ACE CF CompactFlash Image Select DIP Switch S1 Note S1 switch 4 is the System ACE controller enable switch When ON this switch allows the System ACE to boot at power on if it finds a CF card present I
62. Updated Package Placement column in Table 1 8 Updated Figure 1 17 Added notes about FMC HPC J64 and J63 connectors to 19 VITA 57 1 FMC HPC Connector and 20 VITA 57 1 FMC LPC Connector respectively Updated description of PMBus Pod and TI Fusion Digital Power Software GUI in Onboard Power Regulation Updated Table B 35 Appendix C VITA 57 1 FMC LPC J63 and HPC J64 Connector Pinout and Appendix D ML605 Master UCF 10 12 10 1 4 Updated description of Fusion Digital Power Software in Onboard Power Regulation 02 15 11 1 5 Revised note in Table 1 6 Revised oscillator manufacturer information from Epson to SiTime on page page 14 page 29 and page 78 07 18 11 1 6 Corrected jitter to stability in section Oscillator Differential page 29 Added Table 1 32 page 69 and table notes in Table 1 31 Revised the FPGA U1 Pins for IC SDA MAIN and IIC SCL MAIN in Table 1 18 page 46 ML605 Hardware User Guide www xilinx com UG534 v1 8 October 2 2012 Date Version Revision 06 19 12 1 7 Added Ref 4 link to Oscillator Differential page 29 Revised Oscillator Socket Single Ended 2 5V page 29 Revised Figure 1 10 page 33 10 02 12 1 8 Updated Figure 1 2 page 13 Added Regulatory and Compliance Information page 95 UG534 v1 8 October 2 2012 www xilinx com ML605 Hardware User Guide ML605 Hardware User Guide www xilinx com UG534 v1 8 October 2 2012 Table of Contents
63. V 37 PTD08A010W U91 10A 0 6V 3 6V Adj Switching Regulator VCCAUX 2 50V 38 UCD9240PFCQ U25 PMBus Controller Aux Addr 53 40 UCD7230RGWR U35 6A 0 6V 3 6V Adj Switching Regulator MGT_AVCC 1 00V 41 UCD7230RGWR U36 6A 0 6V 3 6V Adj Switching Regulator MGT_AVTT 1 20V 42 PTD08A010W U20 10A 0 6V 3 6V Adj Switching Regulator VCC_1V5 1 50V 43 PTD08A010W U21 10A 0 6V 3 6V Adj Switching Regulator VCC_3V3 3 30V 44 TPS79518DCOR U79 500 mA Fixed Linear Regulator VCC 1V8 1 80V 45 TPS51200DRCT U17 3A DDR3 VTERM Tracking Linear VTTDDR 0 75V 45 Regulator TPS51200DRCT U17 10 mA Tracking Reference output VTTVREF 0 75V 45 TL1963 U8 1 5A Fixed Linear Regulator VCC5 5 00V 35 Notes 1 See Table 1 32 part 1 addr 52 2 See Table 1 32 part 2 addr 53 Table 1 32 Power Rail Specifications UCD9240 PMBus Conirollers at Addresses 52 and 53 stati Schomette Vout PG On Econ Ruse OM rent Over 5 over 5 on 5 Device Rail Name RailName V V v ma ms la ms Faut 8 Fault 8 Fault E V a A a C o 1 Rail vccinr 1 0925 09 5 1 1 14 A 2 Rail vecavs 25 2313 225 10 10 5 10 275 Shut ae oe e 3 Rall vecaux 25 2325 225 5 2 8 9 p KT pon 1 025 0 948 0 923 1 128 5 20 via a a 1 25 1 156 1 125 10 187 ut vse age i Addr 53 Tea down 145 down down 3 Grew 15 1388 135 10 10 1 65 4 Rail vecava 33 3052 297 5 5 0 3 63 ML605 Hardware User G
64. X 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K isa o o o o o o VA WA LA A Ar AW A AA 1 16w W 1 16w n 5 1 16w w 5 1 16w ro 5 1 16w ro 5 5 gog UG534_27_110409 Figure 1 27 Multi Purpose Select DIP Switch S2 Table 1 26 shows the FPGA configuration modes controlled by S2 switches 3 4 and 5 Table 1 26 ML605 Configuration Modes Configuration Mode M 2 0 Bus Width CCLK Master BPI Up 010 8 16 Output JTAG 101 1 Input TCK Slave SelectMAP 110 8 16 32 Input www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description Table 1 27 Switch S2 Configuration Details Switch Configuration Mode Method Switch Net Name JTAG Slave SelectMAP Master BPI System ACE CF Platform Flash XL P30 Linear Flash 2 1 CCLK_EXTERNAL Off On Off 2 2 P30_CS_SEL On Off On 2 3 FPGA MO On Off Off 2 4 FPGA_M1 Off On On 2 5 FPGA_M2 On On Off 2 6 FLASH_A23 Off Don t Care Off Notes 1 InJTAG mode 52 2 is shown as ON for FPGA access to the P30 Linear Flash Alternatively set 52 2 to OFF for FPGA access to the Platform Flash XL 2 In Master BPI mode 52 6 is shown as OFF for selecting initial configuration from BPI address 0x000000 Alternatively set S2 6 to ON to select initial configuration from BPI address 0x800000 See 3 128 Mb Platform Flash XL page 22 and 4 32
65. abel Description DS1 SYSACE_STAT_LED GREEN System ACE CF System ACE CF Status Status LED DS2 TI PWRGOOD and GREEN POWER GOOD Both UCD9240 controllers MGT TI PWRGOOD report power good DS13 FPGA DONE GREEN DONE FPGA configured successfully DS23 LED GRN GREEN STATUS USB JTAG Connection Status Dual LED LED RED RED DS25 12V GREEN 12V 12V Power On DS27 MGT AVCC GREEN AVCCGD MGT AVCC Power On DS28 MGT AVTT GREEN MGT AVIT MGT AVTT Power On DS29 DDR3_VTTDDR_PWRGOOD GREEN DDR3 PWR GD DDR3 VTTDDR Power Good DS30 SYSACE_ERR_LED RED System ACE CF System ACE CF Error Error LED DS31 FPGA_INIT_B RED INIT FPGA Initialization in progress DS32 DVI_GPIO1_FMC_C2M_PG GREEN FMC PWR GD FMC Power Good ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com 47 Chapter 1 ML605 Evaluation Board XILINX Ethernet PHY Status LEDs The Ethernet PHY status LEDs are mounted to be visible when the ML605 board is installed into a PC motherboard They are mounted in right angle plastic housings and can be seen on the connector end of the board This cluster of six LEDs is installed adjacent to the RJ45 Ethernet jack P2 Direction Link Rate Indicator Mbps DUP O O 10 TX O O 100 RX O O 1000 P2 15 End view of ML605 Ethernet jack and status LEDs when installed vertically in a PC chassis UG534 16 101209 Figure 1 16 Ethernet PHY Status LEDs 48 www xilinx com ML605 Hardware User Guide
66. ame a Tipi G37 FMC_HPC_LA33_N AH24 H37 FMC_HPC_LA32_P AG25 H38 FMC_HPC_LA32_N AG26 J2 FMC HPC CLK3 M2C P U84 6 K4 FMC HPC CLK2 M2C PO U83 6 J3 FMC HPC CLK3 M2C NI U84 7 K5 FMC HPC CLK2 M2C NO U83 7 J6 FMC HPC HA03 P AA25 K7 FMC HPC HA02 P AB25 J7 FMC HPC HA03 N Y26 K8 FMC_HPC_HA02_N AC25 J9 FMC HPC HAO7 P AA26 K10 FMC HPC HA06 P AA28 J10 FMC HPC HA07 N AB26 K11 FMC HPC HA06 N AA29 J12 FMC_HPC_HA11_P AG33 K13 FMC_HPC_HA10_P AD34 J13 FMC_HPC_HA11_N AG32 K14 FMC_HPC_HA10_N AC34 J15 FMC HPC HA14 P AA30 K16 FMC HPC HA17 CC P V30 J16 FMC HPC HA14 N AA31 K17 FMC HPC HA17 CC N W30 J18 FMC_HPC_HA18 P T33 K19 FMC HPC HA21 P U31 J19 FMC_HPC_HA18_N T34 K20 FMC HPC HA21 N U30 J21 FMC HPC HA22 P U28 K22 FMC HPC HA23 P U26 J22 FMC HPC HA22 N V29 K23 FMC HPC HA23 N U27 J24 FMC HPC HB01 P AN32 K25 FMC HPC HB00 CC P AF30 J25 FMC HPC HB01 N AM32 K26 FMC HPC HB00 CC N AG30 J27 FMC_HPC_HB07_P AJ34 K28 FMC_HPC_HB06_CC_P AF26 J28 FMC_HPC_HB07_N AH34 K29 FMC_HPC_HB06_CC_N AE26 J30 FMC_HPC_HB11_P AJ29 K31 FMC_HPC_HB10_P AF28 J31 FMC_HPC_HB11_N AJ30 K32 FMC_HPC_HB10_N AF29 J33 FMC_HPC_HB15_P AE28 K34 FMC_HPC_HB14_P AE27 J34 FMC HPC HB15 N AF29 K35 FMC HPC HB14 N AD27 J36 FMC_HPC_HB18_P AD25 K37 FMC_HPC_HB17_CC_P AG27 J37 FMC HPC HB18 N AD26 K38 FMC HPC HB17 CC N AG28 Notes 1 Signals ending with LS are not directly connected to the FMC HPC connector LS signals are connected between the listed U1 FPGA pin and a level shifter device The signal connected bet
67. any errors contained in the Materials or to advise you of any corrections or update You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http www xilinx com warranty htm IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in Critical Applications http www xilinx com warranty htm critapps Revision History The following table shows the revision history for this document Date Version Revision 8 17 09 1 0 Initial Xilinx release 11 17 09 11 e Updated Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 11 and Figure 1 14 e Added Figure 1 7 Figure 1 8 Figure 1 10 and Figure 1 13 e Updated Table 1 15 and Table 1 18 e Updated Appendix C VITA 57 1 FMC LPC J63 and HPC J64 Connector Pinout and Appendix D ML605 Master UCF e Minor typographical edits 01 15 10 1 2 e Updated Figure 1 2 Figure 1 3 Figure 1 17 Table 1 3 Table 1 8 Table 1 9 Table B 34 and Table B 35 Miscellaneous typographical edits 1 21 10 1 2 1 e Corrected typos in Table 1 31 and Figure 1 28 05 18 10 1 3 Updated 7 Clock Generation including Table 1 7
68. ardware User Guide UG534 v1 8 October 2 2012 www xilinx com 85 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET HH HH NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FLASH A18 FLASH A19 FLASH A20 FLASH A21 FLASH A22 FLASH A23 FLASH DO FLASH D1 FLASH D2 FLASH D3 FLASH D4 FLASH D5 FLASH D6 FLASH D7 FLASH D8 FLASH D9 FLASH D10 FLASH D11 FLASH D12 FLASH D13 FLASH D14 FLASH D15 FLASH WAIT FPGA FWE B FPGA FOE B FPGA CCLK PLATFLASH L B FPGA FCS B FMC HPC CLKO M2C N FMC HPC CLKO M2C Pp FMC HPC CLK1 M2C N FMC HPC CLK1 M2C P FMC HPC CLK2 M2C TO N FMC HPC CLK2 M2C IO P FMC HPC CLK2 M2C MGT C N FMC HPC CLK2 M2C MGT C P FMC HPC CLK3 M2C TO N FMC HPC CLK3 M2C IO P FMC HPC CLK3 M2C MGT C N FMC HPC CLK3 M2C MGT C P FMC HPC DPO C2M N FMC HPC DPO C2M P FMC HPC DPO M2C N FMC HPC DPO M2C P FMC HPC DP1 C2M N FMC HPC DP1 C2M P FMC HPC DP1 M2C N FMC HPC DP1 M2C P FMC HPC DP2 C2M N FMC HPC DP2 C2M P FMC HPC DP2 M2C N FMC HPC DP2 M2C P FMC HPC DP3 C2M N FMC HPC DP3
69. clocking the internal configuration logic See the Virtex 6 FPGA Configuration User Guide for more details Ref 5 3 This is the default setting due to internal pull up termination on mode pins For an overview on configuring the FPGA see Configuration Options page 76 Note The mode switches are part of DIP switch S2 The default mode setting see Table B 34 page 79 is M 2 0 010 which selects Master BPI Up at board power on Switch S1 position 4 must be OFF to disable the System ACE controller from attempting to boot if a CF card is present References See the Virtex 6 FPGA Configuration User Guide for detailed configuration information Ref 5 I O Voltage Rails There are 16 I O banks available on the Virtex 6 device The voltage applied to the FPGA I O banks used by the ML605 board is summarized in Table 1 3 Table 1 3 Voltage Rails U1 FPGA Bank I O Rail Voltage Bank 0 VCC2V5 FPGA 2 5V Bank 12 1 FMC_VIO_B_M2C 2 5V Bank 13 VCC2V5_FPGA 2 5V Bank 14 VCC2V5_FPGA 2 5V Bank 15 VCC2V5_FPGA 2 5V Bank 16 VCC2V5_FPGA 2 5V Bank 22 VCC2V5_FPGA 2 5V Bank 23 VCC2V5_FPGA 2 5V 16 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description Table 1 3 Voltage Rails Cont d U1 FPGA Bank I O Rail Voltage Bank 24 VCC2V5 FPGA 2 5V Bank 25 VCC1V5 FPGA 1 5V Bank 26 VCC1V5 FPGA 1 5V Bank 32 VCC2V5 FPGA 2 5V Ba
70. connector into the J60 connector on the ML605 board The ATX 6 pin connector has a different pinout than J60 and will damage the ML605 board and void the board warranty DO NOT plug an auxilliary PCle 6 pin molex power connector into the J60 connector as this could damage the PCle motherboard and or the ML605 board J60 is marked with a NO PCIE POWER label to warn users of the poten tial hazard DO NOT apply power to J60 and the 4 pin ATX disk drive connector J25 at the same time as this will damage the ML605 board UG534 23 081209 Figure 1 23 Power On Off Slide Switch SW2 ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com 55 Chapter 1 ML605 Evaluation Board XILINX FPGA_PROG_B Pushbutton SW4 Active Low This switch grounds the FPGA s PROG_B pin when pressed This action clears the FPGA See the Virtex 6 FPGA Data Sheet for more information on clearing the contents of the FPGA Ref 4 VCC2V5 FPGA PROG FPGA_PROG_B Silkscreen PROG UG534 24 073109 Figure 1 24 FPGA PROG B Pushbutton SW4 SYSACE RESET B Pushbutton SW3 Active Low When the System ACE CF configuration mode pin is high enabled by closing DIP switch S1 switch 4 the System ACE CF controller configures the FPGA from the CompactFlash card when a card is inserted or the SYSACE RESET button is pressed See 5 System ACE CF and CompactFlash Connector page 26 for more details silkscreen SYSACE RESET B SY
71. ct DVI GPIO1 7 GPIO1 ML605 Hardware User Guide www xilinx com 43 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX 15 IIC Bus The ML605 implements four IIC bus interfaces at the FPGA The MAIN IIC bus hosts four items e FPGAUI Bank 34 MAIN IIC interface e 8Kb NV Memory U6 e FMC HPC connector J64 e DDR3SODIMM Socket J1 The DVI TIC bus hosts two items e FPGA U1 Bank 34 DVI IIC interface e DVI codec U38 and DVI connector J63 The LPC IIC bus hosts two items e FPGA U1 Bank 33 LPC IIC interface e FMC LPC connector J63 The SFP IIC bus hosts two items e FPGA U1 Bank 13 SFP IIC interface e SFP module connector P4 The ML605 IIC bus topology is shown in Figure 1 14 44 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description IIC SDA MAIN LS BANK 34 IIC SDA SFP O a BANK 13 5 IIC SDA DVI LEVEL g if BANK 34 IC SCL DVI SHIFTER ST MICRO LL e FMC LPC IC SDA LS a a ri BANK 33 through 0b1010111 LEVEL LEVEL LEVEL J64 SHIFTER SHIFTER SHIFTER FMC HPC eS COLUMN C 2 EES 2 Kb EEPROM on onf EMC LPC lIC SCL MIN any FMC LPC any FMC LPC Mezzanine Card Mezzanine Card FMC LPC IIC SDA Addr 091010001 Addr 0b1010000 DDR3 SODIMM IC CLK DVI F DVI CONN Z IC SCL MAIN SOCKET IIC SDA DVI F Addr ob1010011 Addr 0b1010000 IC SDA MAIN 2 Kb EEPROM Addr oboo11011 Temperature Sensor
72. ded development board Keep Out areas and drill holes are defined around the FPGA to support an Ironwood Electronics SG BGA 6046 FPGA socket References See the Virtex 6 FPGA Data Sheet Ref 4 Configuration The ML605 supports configuration in the following modes Slave SelectMAP using Platform Flash XL with the onboard 47 MHz oscillator Master BPI Up using Linear BPI Flash device JTAG using the included USB A to Mini B cable JTAG using System ACE CF and CompactFlash card ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com 15 Chapter 1 ML605 Evaluation Board XILINX The ML605 supports Master BPI Up JTAG and Slave SelectMAP These are selected by setting M 2 0 options 010 101 and 110 shown in Table 1 2 Table 1 2 Virtex 6 FPGA Configuration Modes Configuration Mode M 2 0 Bus Width 1 CCLK Direction Master Serial 2 000 1 Output Master SPI 001 1 Output Master BPI Up 2 010 8 16 Output Master BPl Down 2 011 8 16 Output Master SelectMAP 2 100 8 16 Output JTAG 101 1 Input TCK Slave SelectMAP 110 8 16 32 Input Slave Serial 3 111 1 Input Notes 1 The parallel configuration modes bus is auto detected by the configuration logic 2 In Master configuration mode the CCLK pin is the clock source for the Virtex 6 FPGA internal configuration logic The Virtex 6 FPGA CCLK output pin must be free from reflections to avoid double
73. device driver must be installed on the host PC prior to establishing communications with the ML605 Refer to the evaluation kit Getting Started Guide for driver installation instructions Table 1 14 USB Type B Pin Assignments and Signal Definitions Wee Signal Name Description 1 VBUS 5V from host system not used 2 USB DATA N Bidirectional differential serial data N side 3 USB DATA P Bidirectional differential serial data P side 4 GROUND Signal ground Table 1 15 USB to UART Connections U1 FPGA Pin UART function Schematic Net U34 CP2103GM UART Function in FPGA Name Pin in CP2103GM T24 RTS output USB 1 CTS 22 CTS input T23 CTS input USB 1 RIS 23 RIS output J25 TX data out USB 1 RX 24 RXD data in J24 RX data in USB 1 TX 25 TXD data out References Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers In addition see some of the Xilinx UART IP specifications at e http www xilinx com support documentation ip documentation xps uartlite pdf e http www xilinx com support documentation ip documentation xps uart16550 pdf ML605 Hardware User Guide www xilinx com 41 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX 13 USB Controller The ML605 provides USB support via a Cypress CY7C67300 EZ Host Programmable Embedded USB Host and Peripheral Controller U81 The host port is a
74. e 55 Never connect an auxiliary PCle 6 pin molex power connector to J60 6 pin molex on the ML605 board as this could result in damage to the PCle motherboard and or ML605 board The 6 pin molex connector is marked with a no PCle power label to warn users of the potential hazard www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description References See the following websites for more Virtex 6 FPGA Integrated Endpoint Block for PCI Express information e http www xilinx com products ipcenter V6 PCI Express Block htm e http www xilinx com support documentation ipbusinterfacei o pci express v6pciexpressendpointblock htm In addition see the PCI Express specifications for more information Ref 27 10 SFP Module Connector The board contains a small form factor pluggable SFP connector and cage assembly that accepts SFP modules The SFP interface is connected to MGT Bank 116 on the FPGA The SFP module serial ID interface is connected to the SFP IIC bus see 15 IIC Bus page 44 for more information The control and status signals for the SFP module are connected to jumpers and test points as described in Table 1 9 The SFP module connections are shown in Table 1 10 page 38 Table 1 9 SFP Module Control and Status SFP Control Status Board Connection Signal Test Point J52 SFP TX FAULT High Fault Low Normal Operation Jumper J65 SFP TX DISABL
75. e SelectIO resources available in all Virtex 6 devices e Virtex 6 FPGA GTX Transceivers User Guide This guide describes the GTX transceivers available in all Virtex 6 FPGAs except the XC6VLX760 e Virtex 6 FPGA Embedded Tri Mode Ethernet MAC User Guide This guide describes the dedicated Tri Mode Ethernet Media Access Controller available in all Virtex 6 FPGAs except the XC6VLX760 e Virtex 6 FPGA DSP48E1 Slice User Guide This guide describes the architecture of the DSP48E1 slice in Virtex 6 FPGAs and provides configuration examples e Virtex 6 FPGA System Monitor User Guide The System Monitor functionality available in all Virtex 6 devices is outlined in this guide e Virtex 6 FPGA PCB Design Guide This guide provides information on PCB design for Virtex 6 devices with a focus on strategies for making design decisions at the PCB and interface level Additional Support Resources To search the database of silicon and software guestions and answers or to create a technical support case in WebCase see the Xilinx website at http www xilinx com support 8 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Chapter 1 ML605 Evaluation Board Overview The ML605 board enables hardware and software developers to create or evaluate designs targeting the Virtex 6 XC6VLX240T 1FFG1156 FPGA The ML605 provides board features common to many embedded processing systems Some comm
76. eclarations of conformity xtp251 zip 2006 95 EC Low Voltage Directive LVD 2004 108 EC Electromagnetic Compatibility EMC Directive EN standards are maintained by the European Committee for Electrotechnical Standardization CENELEC IEC standards are maintained by the International Electrotechnical Commission IEC Electromagnetic Compatibility Safety EN 55022 2010 Information Technology Equipment Radio Disturbance Characteristics Limits and Methods of Measurement EN 55024 2010 Information Technology Equipment Immunity Characteristics Limits and Methods of Measurement This is a Class A product In a domestic environment this product can cause radio interference in which case the user might be required to take adequate measures IEC 60950 1 2005 Information technology equipment Safety Part 1 General requirements EN 60950 1 2006 Information technology equipment Safety Part 1 General requirements ML605 Hardware User Guide www xilinx com 95 UG534 v1 8 October 2 2012 Appendix E Regulatory and Compliance Information XILINX Markings This product complies with Directive 2002 96 EC on waste electrical and electronic equipment WEEE The affixed product label indicates that the user must not discard this electrical or electronic product in domestic household waste This product complies with Directive 2002 95 EC on the restriction of hazardous substances RoHS in electrical and elec
77. h the xilinx sys file located in the root directory The xilinx sys file is used by the System ACE CF controller to define the project directory structure which consists of one main folder containing eight sub folders used to store the eight ACE files containing the configuration images Only one ACE file should exist within each sub folder All folder names must be compliant to the DOS 8 3 short file name format This means that the folder names can be up to eight characters long and cannot contain the following reserved characters lt gt This DOS 8 3 file name restriction does not apply to the actual ACE file names Other folders and files may also coexist with the System ACE CF project within the FAT16 partition However the root directory must not contain more than a total of 16 folder and or file entries including deleted entries When ejecting or unplugging the CompactFlash device it is important to safely stop any read or write access to the CompactFlash device to avoid data corruption System ACE CF error and status LEDs indicate the operational state of the System ACE CF controller e Ablinking red error LED indicates that no CompactFlash card is present e Asolid red error LED indicates an error condition during configuration e A blinking green status LED indicates a configuration operation is ongoing e A solid green status LED indicates a successful download Note Jumper J69 can be removed to disable the Red Error LED
78. igure 1 19 The five directional pushbuttons are assigned as GPIO and the sixth is assigned as CPU_RESET Figure 1 19 and Table 1 22 page 52 describe the pushbutton switches VCC1V5 Pushbutton CPU RESET UG534 19 072109 Figure 1 19 User Pushbutton Switch Typical ML605 Hardware User Guide www xilinx com 51 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX Table 1 22 User Pushbutton Switch Connections U1FPGAPin Schematic Net Name E A19 GPIO SW N SW5 2 A18 GPIO SW S SW6 2 G17 GPIO_SW_E SW7 2 H17 GPIO SW W SW8 2 G26 GPIO SW C SW9 2 H10 CPU RESET SW10 2 User DIP Switch The ML605 includes an active High eight pole DIP switch as described in Figure l 20 and Table 1 23 VCC1V5 GPIO DIP SW2 GPIO DIP SW3 GPIO DIP SW4 GPIO DIP SW5 GPIO DIP SW6 GPIO DIP SW7 GPIO DIP SW8 UG534 20 072109 Figure 1 20 User 8 pole DIP Switch Table 1 23 User DIP Switch Connections U1 FPGA Pin Schematic Net Name DIP Switch Pin D22 GPIO_DIP_SW1 SW1 1 C22 GPIO_DIP_SW2 SW1 2 L21 GPIO_DIP_SW3 SW1 3 L20 GPIO_DIP_SW4 SW1 4 C18 GPIO_DIP_SW5 SW1 5 B18 GPIO_DIP_SW6 SW1 6 K22 GPIO_DIP_SW7 SW1 7 K21 GPIO_DIP_SW8 SW1 8 52 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description User SMA GPIO The ML605 includes an pair of SMA connectors for GPIO as described in Figure 1
79. igure 1 32 TI_V3P3 PMBus Connector UDC9240 PMBUS ALERT 35 PMBUS CLK 19 PMBUS CTRL 36 BANK 34 lan 6vlx240tffll56 PMBUS CTRL LS PMBUS ALERT LS PMBUS DATA LS PMBUS CLK LS SM FAN TACH IO LI1IN SRCC 34 AJ9 IO L11P SRCC 34 AH9 IO L10N MRCC 34 AB10 IO L10P MRCC 34 AC10 IO L9N MRCC 34 M10 IO L9P MRCC 34 L10 UG534 35 081209 Figure 1 33 UDC9240 PMBus Access System Monitor ML605 Demonstration Design The various features described in this section are easily evaluated using a MicroBlaze based reference designed provided with the ML605 Evaluation Board This reference design supports a UART based interface using a terminal program such as Hyperterminal to provide information on the FPGA power supplies temperature and power consumption In addition the UART interface can be used to margin the FPGA supplies over the PMBus The System Monitor functionality can also be accessed at any time via JTAG using the ChipScope Pro Analyzer tool without design modifications or cores inserted into a user design The ChipScope Pro Analyzer tool automatically connects to the System Monitor via a JTAG cable after a connection is established References For more information on using the System Monitor and an overview of the tool support for this feature see the Virtex 6 FPGA System Monitor User Guide Ref 15 ML605 Hardware User Guide www xilinx com 75 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluat
80. ion Board XILINX Configuration Options 76 The FPGA on the ML605 Evaluation Board can be configured by the following methods e 3 128 Mb Platform Flash XL page 22 e 4 32 MB Linear BPI Flash page 22 e 5 System ACE CF and CompactFlash Connector page 26 e 6 USB JTAG page 28 For more information see the Virtex 6 FPGA Configuration User Guide at http www xilinx com support documentation user_guides ug360 pdf Table 1 33 Mode Switch S2 Settings Mode Pins M2 M1 MO Configuration Mode 110 Slave SelectMAP 010 BPI Mode 101 JTAG With the mode set to JTAG 101 the ML605 will not attempt to boot or load a bitstream from either of the Flash devices If a CompactFlash CF card is installed in the CF socket U73 System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1 With no CF card present the ML605 can be configured via the onboard JTAG controller and USB download cable as described above With the mode set to either Slave Select MAP 110 or BPI Mode 010 the FPGA will attempt to configure itself from the selected Flash device as described in 3 128 Mb Platform Flash XL page 22 Note S1 switch 4 is the System ACE controller enable switch When ON this switch allows the System ACE to boot at power on if it finds a CF card present In order to boot from BPI Flash U4 or Xilinx Platform Flash U27 without System ACE contention S1 switch 4
81. itor ML605 Hardware User Guide www xilinx com 73 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX Fan Controller In highly demanding situations active thermal management in the form of a heat sink and fan may be required In order to support this drive circuitry for an external fan has been provided on the ML605 A fan with tach output can be connect at header J59 as shown in Figure 1 32 The fan PWM signal is generated by the FPGA and the tach input can be used to close the control loop and regulate the fan speed Alternatively the FPGA temperature as recorded by the System Monitor can be used to close the PWM control loop for the fan vcc12 P SM FAN TACH VCC2V5 1N4148 UG534 39 081209 Figure 1 32 ML605 Fan Driver 74 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description FPGA Power Supply Margining The PMBus IIC which provides access to the 2 x UDC9240 power controllers can also be accessed via FPGA I O in addition to a dedicated header J3 see Figure 1 33 A full description of the UDC9240 functionality is outside the scope of this user guide However this useful feature can be used for example to margin the FPGA and board power supplies when evaluating a design The System Monitor provides accurate measurements of the on chip supply voltages as the FPGA supplies are margined The PMBus and fan connections are shown in F
82. l as software storage The Linear BPI Flash shares the dual use configuration pins in parallel with the XCF128 Platform Flash XL The P30_CS net is used to select the P30 or the XCF128 Power on configuration is selected by the P30 CS net which is tied to a dip switch S2 selects pullup pulldown and is also wired to an FPGA non config pin The dip switch allows power selection for the configuration device P30 or XCF128XL The dip switch selection can be overridden by the FPGA after configuration by controlling the logic level of the P30_CS signal See S2 switch setting details in Table 1 26 page 58 For an overview on configuring the FPGA see Configuration Options page 76 Figure 1 3 shows a block diagram for the Platform Flash and BPI Flash S1 Switch 4 PLATFORM OFF Disable System ACE FLASH enable U4 U27 flash boot ON Enable System ACE boot when CF card i t FLASH_D 15 0 FPGA U1 card is presen VCC2V5 Bank 24 U10 6 2 SWITCH 6 PLATFLASH FCS B ON U4 BPI Upper Half OFF U4 BPI Lower Half VCOC2V5 EEGA tin Add 510 s2 2 FPGA uy FLASH AI2SI 11 22 S2 SWITCH 2 E ve ON U4 BOOT OFF U27 BOOT VCC2V5 VCC2V5 510 2 S2 6 E ri 3 FPGAFCSB FPGAUt FLASH CE B AKEn 22 UG534 03 011110 Figure 1 3 Platform Flash and BPI Flash Block Diagram www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description ML605 Flash Boot Options The ML605 has two para
83. llel wired flash memory devices as shown in Figure 1 3 At ML605 power up before FPGA configuration DIP switch 2 switch 2 selects which flash device U4 BPI or U27 Platform Flash provides the boot bitstream Typically 52 switch 2 will be open OFF to select the U27 Platform Flash Given that the mode switches S2 switch 3 M0 switch 4 M1 and switch 5 M2 are set to Slave SelectMAP mode then U27 driven at 47 MHz can load a PCIe core bitstream before a host PC motherboard can scan its PCIe slots When S2 switch 2 is closed ON at power up the FPGA will be configured from the BPI flash device U4 Note that U4 address bit A23 is switched by S2 switch 6 which allows the lower or upper half of U4 to be chosen as a data source Table 1 5 shows the connections and pin numbers for the boot flash devices Table 1 5 Platform Flash and BPI Flash Connections U4 BPI Flash U27 Platform Flash U1 FPGA Pin Schematic Net Name Pin Number Pin Name Pin Number Pin Name AL8 FLASH AO 29 Al Al A00 AK8 FLASH_A1 25 A2 B1 A01 AC9 FLASH_A2 24 A3 C1 A02 AD10 FLASH_A3 23 A4 D1 A03 C8 FLASH_A4 22 A5 D2 A04 B8 FLASH_A5 21 A6 A2 A05 E9 FLASH_A6 20 A7 C2 A06 E8 FLASH_A7 19 A8 A3 A07 A8 FLASH_A8 8 A9 B3 A08 A9 FLASH_A9 7 A10 C3 A09 D9 FLASH_A10 6 All D3 A10 C9 FLASH All 5 A12 C4 All D10 FLASH_A12 4 A13 A5 A12 C10 FLASH_A13 3 Al4 B5 A13 F10 FLASH_A14 2 A15 C5 A14 F9 FLAS
84. must be OFF www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Appendix A References This section provides references to documentation supporting Virtex 6 FPGAs tools and IP For additional information see www xilinx com support documentation index htm Documents supporting the ML605 Evaluation Board UG535 ML605 Reference Design User Guide UG525 Getting Started with the Xilinx Virtex 6 FPGA ML605 Evaluation Kit DS150 Virtex 6 Family Overview DS152 Virtex 6 FPGA Data Sheet DC and Switching Characteristics UG360 Virtex 6 FPGA Configuration User Guide UG406 Virtex 6 FPGA Memory Interface Solutions User Guide UG361 Virtex 6 FPGA SelectIO Resources User Guide UG362 Virtex 6 FPGA User Guide Clocking Resources UG363 Virtex 6 FPGA Memory Resources User Guide UG364 UG365 UG366 UG369 SO SU SON OE e Oo ee 4 gt G364 Virtex 6 FPGA Configurable Logic Block User Guide G365 Virtex 6 FPGA Packaging and Pinout Specifications G366 Virtex 6 FPGA GTX Transceivers User Guide G369 Virtex 6 FPGA DSP48E1 Slice User Guide DS186 Virtex 6 FPGA Memory Interface Solutions Data Sheet UG370 Virtex 6 FPGA System Monitor User Guide DS715 Virtex 6 FPGA Integrated Block v1 2 for PCI Express Data Sheet DS617 Platform Flash XL High Density Configuration and Storage Device Data Sheet DS080 System ACE CompactFlash Solution Data Sheet UG138 LogiCORE IP Tri Mode Ethernet MAC
85. n 9 11 10 12 Connect Vccint shunt to Vp Vn UG534 37 081209 Figure 1 30 System Monitor Header J35 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description ML605 Board Power Monitor In addition to monitoring the FPGA core supply power consumption two auxiliary analog input channels of the 16 that are available are used to implement a power monitor for the entire ML605 board The board power is monitored at the 12V power input connector Figure 1 31 shows how the power monitor is implemented and connected to the System Monitor auxiliary input channels 12 and 13 A simple resistor divider is used to monitor the 12V supply voltage and to provide a reference voltage to an instrumentation amplifier InAmp The voltage on the auxiliary channel 12 is equal to supply voltage divided by 24 0 5V The InAmp is used to amplify by a factor of 50 the voltage dropped across a 2 mQcurrent sense shunt The voltage at the output of the InAmp is proportional to the current The voltage on auxiliary channel 13 Current amps x 0 002 x 50 e g 5A 0 5V 12V Supply Monitor 2m 1 Ri R2 amp O Ki k2 O yy IN 6 IN O O 11 5k 0 5 V INA213 470 SC70 6 OUT 1k REET Package T e x VAUXP 13 499 0 5 50V V 10nF 10nF Current Channel O X VAUXN 13 1k 2470 10nF 1k X VAUXP 12 O 10nF Voltage Channel X VAUXN 12 UG534 38 081209 Figure 1 31 ML605 12V Power Mon
86. n ML605 board AE13 PCIE PERST B An PERST Integrated Endpoint block reset signal Notes 1 PCIE TXn P N pairs are capacitively coupled to FPGA 2 PCIE 100M MGTO P N pairs are capacitively coupled to FPGA 3 PCIE 250M MGTI P N pairs are capacitively coupled to FPGA 4 PCIE PERST B is level shifted by U32 5 For ML605 access is through MGT Banks 114 and 115 36 The PCle interface obtains its power from the DC power supply provided with the ML605 or through the 12V ATX power supply connector The PCle edge connector is not used for any power connections The board can be powered by one of two 12V sources J60 a 6 pin 2x3 molex type connector and J25 a 4 pin inline ATX disk drive type connector The 6 pin molex type connector provides 60W 12V 5A from the AC power adapter provided with the board while the 4 pin ATX disk drive connector is provided for users who want to power their board while it is installed inside a PC chassis For applications reguiring additional power such as the use of expansion cards drawing significant power a larger AC adapter might be reguired If a different AC adapter is used its load regulation should be better than 10 ML605 power switch SW2 turns the board on and off by controlling the 12V supply to the board Caution Never apply power to the power brick connector J60 and the 4 pin ATX disk drive connector J25 at the same time as this will result in damage to the board See Figure 1 23 pag
87. n order to boot from BPI Flash U4 or Xilinx Platform Flash U27 without System ACE contention S1 switch 4 must be OFF ML605 Hardware User Guide www xilinx com 57 UG534 v1 8 October 2 2012 58 Chapter 1 ML605 Evaluation Board XILINX Mode Osc Enable Boot EEPROM Select and Addr Select DIP Switch S2 DIP switch S2 is a multi purpose selector switch Figure 1 27 and Table 1 27 page 59 FPGA Mode S2 switches 3 4 and 5 control the FPGA mode Table 1 26 Oscillator Enable S2 switch 1 CCLK EXTERNAL controls the enable pin of the 47 MHz oscillator SiT8102 X4 When switch 1 is closed CCLK EXTERNAL High X4 drives a 47 MHz clock onto the FPGA CCLK signal Boot EEPROM Select S2 switch 2 is used to select the between the Xilinx Platform Flash or the Numonyx Linear BPI Flash for the FPGA boot memory device Upper or Lower Address Select S2 switch 6 is used to select the upper or lower half of flash memory U4 as the source of the FPGA bitstream image When FLASH A23 is High the upper half of the address is selected When FLASH A23 is Low the lower half of the address is selected VCC2V5 1 16W 510 gt 1 16W o 510 gt 1 16W o 51 gt 1 16W o 2 D 2 EEN E l m El a x 6 g M FLASH A23 5 e M FPGA_M2 4 e M FPGA Mi 3 o M FPGA MO 2 e m P30 CS SEL 1 Q M CCLK EXTERNAL O L Tt O o L L L L L a a a a a a SDMX 6
88. ndix C VITA 57 1 FMC LPC J63 and HPC J64 Connector Pinout Figure C 34 shows the pinout of the FMC LPC connector Pins marked NC are not connected hm J eS eee GT A D BLAS NC GN DE NC N P xi Wi LAON e pe e NG Nc aN ono NC iski a D O Figure C 34 FMC LPC Connector Pinout For more information refer to the VITA 57 1 FMC LPC Connections table Table 1 30 ML605 Hardware User Guide www xilinx com 81 UG534 v1 8 October 2 2012 Appendix C VITA 57 1 FMC LPC J63 and HPC J64 Connector Pinout XILINX Figure C 35 shows the pinout of the FMC HPC connector GND GND GND GND GND S 2 n a Figure C 35 FMC HPC Connector Pinout For more information refer to the VITA 57 1 FMC HPC Connections table Table 1 28 82 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Appendix D ML605 Master UCF The UCF template is provided for designs that target the ML605 Net names provided in the constraints below correlate with net names on the ML605 schematic On identifying the appropriate pins the net names below should be replaced with net names in the user RTL See the Constraints Guide for more information Users can refer to the UCF files generated by tools such as MIG Memory Interface Generator for memory interfaces and BSB Base System Builder for more detailed information concerning the I O standards req
89. nit red Done green 31 c System ACE CF status Status green Error red 13 User I O 31 a User LEDs green 8 User I O active High 30 31 33 b User pushbuttons N O i momentary e User I O active High 31 17 c User LEDs green 5 User I O active High 31 d User DIP switch 8 pole User I O active High 31 e User GPIO SMA SMA pair 30 connectors f LCD 16 character x 2 line Displaytech 162D BA BC 33 display www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description Table 1 1 ML605 Features Cont d Number Feature Notes ae mAN Page Switches 13 25 39 a Power On Off Slide switch 39 b FPGA PROG B i 18 pushbutton active Low 13 Con Bch ae 4 pole DIP switch active High 25 Select d Mode Switch 6 pole DIP switch active High 25 19 FMC HPC connector Samtec ASP 134486 01 16 19 20 FMC LPC connector Samtec ASP 134603 01 20 Power management 35 44 a PMBus controllers 2 x TI UCD9240PFC 35 40 REVAN Ba on 2 x PTD08A020W 3 x PTDOSA010W a 21 E Pant 6 pin Molex mini fit connector 39 connector lt N 4 pin ATX disk type connector 39 connector 22 i 100 2x6 DIP male pin header 34 connector 23 System ACE Error DS30 LED Jumper on enable LED 13 disable jumper J69 Jumper off disable LED 1 Virtex 6 XC6VLX240T 1FFG1156 FPGA A Virtex 6 XC6VLX240T 1FFG1156 FPGA is installed on the embed
90. nk 33 VCC2V5 FPGA 2 5V Bank 34 VCC2V5 FPGA 2 5V Bank 35 VCC1V5 FPGA 1 5V Bank 36 VCCIV5 FPGA 1 5V Notes 1 TheVITA 57 1 specification stipulates that the Bank 12 voltage named FMC_VIO_B_M2C is supplied by the FMC card plugged onto the relevant FMC connector ML605 J64 FMC VIO B M2C cannot exceed the base board ML605 Vadj of the FMC connector The ML605 FMC Vadj maximum is 2 5V References See the Xilinx Virtex 6 FPGA documentation for more information at http www xilinx com support documentation virtex 6 htm 2 512 MB DDR3 Memory SODIMM A 512MB DDR3 SODIMM is provided as a flexible and efficient form factor volatile memory for user applications The ML605 SODIMM socket is wired to support a maximum SODIMM size of 2 GB The ML605 DDR3 64 bit wide interface has been tested to 800 MT s The DDR3 interface is implemented in FPGA banks 25 26 35 and 36 DCI VRP N resistor connections are only implemented banks 26 and 36 DCI functionality in banks 25 and 35 is achieved in the UCF by cascading DCI between adjacent banks as follows CONFIG DCI CASCADE 36 35 CONFIG DCI CASCADE 26 25 Table 1 4 shows the connections and pin numbers for the DDR3 SODIMM Table 1 4 DDR3 SODIMM Connections J1 SODIMM U1 FPGA Pin Schematic Net Name Pin Number Pin Name L14 DDR3 A0 98 AO Al6 DDR3_A1 97 Al B16 DDR3_A2 96 A2 E16 DDR3_A3 95 A3 D16 DDR3_A4 92 A4 J17 DDR3_A5 91 A5 ML605 Hardware U
91. ns 1 2 No jumper SGMII to copper A lod Jumper over pins 2 3 Jumper over pins 2 3 No jumper RGMII Jumper over pins 1 2 No jumper Jumper on On power up or on reset the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1 12 These settings can be overwritten via software commands passed over the MDIO interface Table 1 12 Board Connections for PHY Configuration Pins Pin Connection on Bit 2 Bit 1 Bit 0 Board Definition and Value Definition and Value Definition and Value CEGO Vec 2 5V PHYADR 2 1 PHYADRI 1 1 PHYADRI0 1 CFG1 Ground ENA PAUSE 0 PHYADR 4 0 PHYADRI3 0 CFG2 Vec 2 5V ANEG 3 1 ANEG 2 1 ANEG 1 1 CFG3 Vec 2 5V ANEG 0 1 ENA XC 1 DIS 125 1 CFG4 Vec 2 5V HWCFG MD 2 1 HWCFG MD 1 1 HWCFG MD 0 1 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description Table 1 12 Board Connections for PHY Configuration Pins Cont d Pin Connection on Bit 2 Bit 1 Bit 0 Board Definition and Value Definition and Value Definition and Value CFG5 Vec 2 5V DIS FC 1 DIS_SLEEP 1 HWCFG_MDI 3 1 CFG6 PHY LED RX SEL BDT 0 INT POL 1 75 500 0 SGMII GTX Transceiver Clock Generation An Integrated Circuit Systems ICS8440211 chip generates a high quality low jitter 125 MHz LVDS clock from an inexpensive 25 MHz crystal oscillator This clock is
92. nt AC Adapter and Input Power Jack Switch The ML605 is powered from a 12V source that is connected through a 6 pin 2X3 right angle Mini Fit type connector J60 The AC to DC power supply included in the kit has a mating 6 pin plug When the ML605 is installed into a table top or tower PC s PCle slot the ML605 is typically powered from the PC ATX power supply One of the ATX hard disk type 4 pin power connectors is plugged into ML605 connector J25 The ML605 can be powered with the AC power adapter even when plugged into a PC PCle motherboard slot however users are cautioned not to also connect an ATX 4 pin power connector to J25 See the caution notes below and in Figure 1 23 page 55 Caution DO NOT plug a PC ATX power supply 6 pin connector into ML605 connector J60 The ATX 6 pin connector has a different pinout than ML605 J60 and connecting the ATX 6 pin connector will damage the ML605 and void the board warranty Caution DO NOT apply power to J60 and the 4 pin ATX disk drive connector J25 at the same time as this will damage the ML605 board Refer to Figure 1 23 page 55 for details The ML605 power can be turned on or off through the board mounted slide switch SW2 When the switch is in the on position a green LED DS25 is illuminated ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com 67 Chapter 1 ML605 Evaluation Board XILINX Onboard Power Regulation Figure 1 28 shows the ML605 onboa
93. on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 ML605 Hardware User Guide UG534 v1 8 Octo ber 2 2012 www xilinx com 87 Appendix D ML605 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET PC HB02 N PC HB02 P PC HB03 N PC HB03 P PC HB04 N PC HB04 P PC HBO5 N PC HBO5 P PC HB06 CC N PC HB06 CC P PC HBO7 N PC HB07 P PC HB08 N PC HB08 P PC HB09 N PC HB09 P PC HB10 N PC HB10 P PC HB11 N PC HB11 P PC HB12 N PC HB12 P PC HB13 N PC HB13 P PC HB14 N PC HB14 P PC HB15 N PC HB15 P PC HB16 N PC HB16 P PC HB17 CC N PC HB17 CC Pp PC HB18 N PC HB18 P PC HB19 N PC HB19 P PC LA0O CC N PC_LAOO CC p
94. only used features include a DDR3 SODIMM memory an 8 lane PCI Express interface a tri mode Ethernet PHY general purpose I O and a UART Additional user desired features can be added through mezzanine cards attached to the onboard high speed VITA 57 FPGA Mezzanine Connector FMC high pin count HPC expansion connector or the onboard VITA 57 FMC low pin count LPC connector Features page 10 provides a general listing of the board features with details provided in Detailed Description page 13 Additional Information Additional information and support material is located at e http www xilinx com ml605 This information includes e Current version of this user guide in PDF format e Example design files for demonstration of Virtex 6 FPGA features and technology e Demonstration hardware and software configuration files for the System ACE M CF controller Platform Flash configuration storage device and linear flash chip e Reference design files e Schematics in PDF and DxDesigner formats e Bill of materials BOM e Printed circuit board PCB layout in Allegro PCB format e Gerber files for the PCB Many free or shareware Gerber file viewers are available on the internet for viewing and printing these files e Additional documentation errata frequently asked questions and the latest news For information about the Virtex 6 family of FPGA devices including product highlights data sheets user guides and application notes
95. pplication The Virtex FPGA GTX MGTs are used for the multi gigabit per second serial interfaces The ML605 board trace impedance on all PCle lanes supports both Gen1 and Gen2 applications The ML605 supports up to Gen1 x8 and Gen2 x4 as shipped with a 1 speed grade for the LX240T device Figure 1 11 is a diagram of the PCle MGT bank 114 and 115 clocking Note PCle edge connector signal nomenclature is from perspective of the system motherboard P1 U14 U9 Q1 NQA PCIE_100M_MGT1_P N CLK NCLK Q NQ REFCLK PCIE_CLK_Q0_PIN OLK NCLK QO NQO ICS874001 ICS854104 PCIE 100M MGTO C P N PCIE 250M MGT1 C P N PCIE 100M MGTO P N PCIE 250M MGT1 PIN PERp n 7 0 U1 U1 PETp n 7 0 Bank 115 Bank 114 MGTREFCLKO P N jf MGTREFCLKO P N f MGTTX MGTRX MGTTX MGTRX PCle P N 3 0 P N 3 0 P N 7 4 P N 7 4 8 Lane Edge PCIE_TX 7 0 _P N Connector PCIE_RX 7 0 _P N UG534_11_100809 Figure 1 11 PCle MGT Banks 114 and 115 Clocking PCIe lane width size is selected via jumper J42 as shown in Figure 1 12 The default lane size selection is 1 lane J42 pins 1 and 2 jumpered J42 PCIE_PRSNT_X1 tale PCIE_PRSNT_B PCIE_PRSNT_X4 oka PCIE PRSNT X8 6 5 H 2X3 UG534 12 111709 Figure 1 12 PCle Lane Size Select Jumper J42 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Descrip
96. rd power supply architecture The ML605 uses power solutions from Texas Instruments 12V Power Suppl PWR Jack id J25 J60 Linear Regulator TL1963 VCC5 5 0V 1 5A max U8 Power Controller 1 UCD9240PFC U24 Switching Module PTDO8A020W VCCINT 1 00V 20A max U42 Switching Module PTDO8AO10W VCC2V5 FPGA_VCC2V5 2 50V 10A max U91 Switching Module PTDO8A020W VCCAUX 2 5V 20A max U43 Linear Regulator TL1963A VCC1V8 1 8V 500mA max U79 Power Controller 2 UCD9240PFC U25 Switching Regulator UCD7230RG MGT_AVCC 1 00V 6A max U35 m Switching Regulator UCD7230RG MGT AVTT 1 20V 6A max U36 IN Switching Module PTDO8A010W VCC1V5 FPGA VCC1V5 1 5V 10A max U20 z Switching Module PTDO8A010W VCC3V3 3 3VQ10A max U21 Sink Source DDR Regulator Linear Regulator TPS51200 VTTDDR 0 75V 3A max U17 UG534 28 060311 Figure 1 28 ML605 Onboard Power Regulators 68 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description Table 1 31 Onboard Power System Devices Device Type Designator Description jeanne Evens ha UCD9240PFC U24 PMBus Controller Core Addr 52 35 PTD08A020W U42 20A 0 6V 3 6V Adj Switching Regulator VCCINT FPGA 1 00V 36 PTDO8A020W U43 20A 0 6V 3 6V Adj Switching Regulator VCC2V5 FPGA 2 50
97. s U4 thru series U4 thru series U4 thru series U4 thru series U4 thru series U4 thru series U4 thru series U4 thru series U4 thru series U4 thru series U4 thru series U4 thru series U4 thru series U4 U4 G8 on U27 U4 F8 on U27 F1 on U27 H1 on U27 B4 on U27 R215 R216 R217 R218 R219 R220 R221 R222 R223 R224 R225 R226 R227 R228 R229 R230 select either U4 or U27 H5 H4 G3 G2 15 16 2 2 J3 J2 2 2 C3 C2 C7 C6 A23 A22 A3 A2 A27 A26 A7 A6 A31 A30 A11 A10 A35 A34 A15 A14 A39 A38 A19 on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on J64 J64 J64 J64 U83 U83 series series J64 J64 series series J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 J64 iC C Cc G 399 0 398 0 397 0 396 0 luF luF luF luF 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 O 00 0 0 0 0 00 00 0 0 70 A 0 O D 3 D a PPEOEEEEESDB py p 3333333333 33 D 3 3 F2 E2 G3 E4 E5 G5 G6 H7 El E3 F3 F4 F5 H5 G7 E7 on on on on on on on on on on on on on on on on EE Grae eau e d E ae oa se 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 U10 and switch S2 2 setting 86 www xilinx com ML605 Hardware User G
98. see the Virtex 6 FPGA documentation page at http www xilinx com support documentation virtex 6 htm ML605 Hardware User Guide www xilinx com 9 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board Features The ML605 provides the following features 1 Virtex 6 XC6VLX240T 1FFG1156 FPGA 2 512 MB DDR3 Memory SODIMM 10 3 128 Mb Platform Flash XL 4 32 MB Linear BPI Flash 5 System ACE CF and CompactFlash Connector 6 USB JTAG 7 Clock Generation 9 PCI Express Endpoint Connectivity 10 11 12 15 14 15 Fixed 200 MHz oscillator differential Socketed 2 5V oscillator single ended SMA connectors differential FMC HPC connector FMC LPC connector SMA PCle SFP Module connector Ethernet PHY SGMII interface Geni 8 lane x8 Gen2 4 lane x4 SFP Module Connector 10 100 1000 Tri Speed Ethernet PHY USB to UART Bridge USB Controller DVI Codec IIC Bus IIC EEPROM 1 KB DDR3 SODIMM socket DVI CODEC DVI connector FMC HPC connector FMC LPC connector SFP module connector www xilinx com SMA connectors for MGT clocking 8 Multi Gigabit Transceivers GTX MGTs XILINX ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX ML605 Hardware User Guide UG534 v1 8 October 2 2012 16 17 19 20 21 Overview Status LEDs Ethernet status FPGA INIT FPGA DONE System ACE CF Status User I O USER LED Group 1 GPIO 8 USER
99. ser Guide www xilinx com 17 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX Table 1 4 DDR3 SODIMM Connections Cont d J1 SODIMM U1 FPGA Pin Schematic Net Name Pin Number Pin Name A15 DDR3 A6 90 A6 B15 DDR3 A7 86 A7 G15 DDR3_A8 89 A8 F15 DDR3 A9 85 A9 M16 DDR3 A10 107 A10 AP M15 DDR3 All 84 All H15 DDR3 A12 83 AD BCN J15 DDR3_A13 119 A13 D15 DDR3_A14 80 Al4 C15 DDR3_A15 78 A15 K19 DDR3 BAO 109 BAO J19 DDR3_BA1 108 BA1 L15 DDR3_BA2 79 BA2 J11 DDR3_D0 gt DQO E13 DDR3_D1 7 DQI F13 DDR3 D2 15 DQ2 K11 DDR3 D3 17 DO3 L11 DDR3 D4 4 DO4 K13 DDR3 D5 6 DO5 K12 DDR3 D6 16 DQ6 D11 DDR3_D7 18 DQ7 M13 DDR3_D8 21 DQ8 J14 DDR3_D9 23 DQ9 B13 DDR3_D10 33 DQ10 B12 DDR3_D11 35 DQ11 G10 DDR3_D12 22 DQ12 M11 DDR3_D13 24 DQ13 C12 DDR3_D14 34 DQ14 A11 DDR3_D15 36 DQ15 G11 DDR3_D16 39 DQ16 F11 DDR3_D17 41 DQ17 D14 DDR3_D18 51 DQ18 C14 DDR3_D19 53 DQ19 18 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description Table 1 4 DDR3 SODIMM Connections Cont d J1 SODIMM U1 FPGA Pin Schematic Net Name Pin Number Pin Name G12 DDR3 D20 40 DO20 G13 DDR3 D21 42 DO21 F14 DDR3 D22 50 DO22 H14 DDR3 D23 52 DO23 C19 DDR3 D24 57 DO24
100. ster UCF Appendix A References Additional Documentation The following documents are also available for download at http www xilinx com support documentation virtex 6 htm ML605 Hardware User Guide UG534 v1 8 October 2 2012 Virtex 6 Family Overview The features and product selection of the Virtex 6 family are outlined in this overview Virtex 6 FPGA Data Sheet DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex 6 family Virtex 6 FPGA Packaging and Pinout Specifications This specification includes the tables for device package combinations and maximum I Os pin definitions pinout tables pinout diagrams mechanical drawings and thermal specifications Virtex 6 FPGA Configuration Guide This all encompassing configuration guide includes chapters on configuration interfaces serial and SelectMAP bitstream encryption boundary scan and JTAG configuration reconfiguration techniques and readback through the SelectMAP and JTAG interfaces Virtex 6 FPGA Clocking Resources User Guide This guide describes the clocking resources available in all Virtex 6 devices including the MMCM and PLLs www xilinx com 7 Preface About This Guide XILINX e Virtex 6 FPGA Memory Resources User Guide The functionality of the block RAM and FIFO are described in this user guide e Virtex 6 FPGA SelectIO Resources User Guide This guide describes th
101. ter command Ref 17 References See the Numonyx StrataFlash Embedded Memory Data Sheet Ref 24 Visit the Xilinx Platform Flash product page and click the Resources tab for more information Also see the Platform Flash XL High Density Configuration and Storage Device Data Sheet Ref 17 and the Virtex 6 Configuration User Guide Ref 10 ML605 Hardware User Guide www xilinx com 25 UG534 v1 8 October 2 2012 26 Chapter 1 ML605 Evaluation Board XILINX 5 System ACE CF and CompactFlash Connector The Xilinx System ACE CompactFlash CF configuration controller allows a Type I or Type II CompactFlash card to program the FPGA through the JTAG port Both hardware and software data can be downloaded through the JTAG port The System ACE CF controller supports up to eight configuration images on a single CompactFlash card The configuration address switches allow the user to choose which of the eight configuration images to use The CompactFlash CF card shipped with the board is correctly formatted to enable the System ACE CF controller to access the data stored in the card The System ACE CF controller requires a FAT16 file system with only one reserved sector permitted and a sector per cluster size of more than one UnitSize greater than 512 The FAT16 file system supports partitions of up to 2 GB If multiple partitions are used the System ACE CF directory structure must reside in the first partition on the CompactFlash wit
102. terfaces are compatible with 2 5V mezzanine cards capable of supporting 2 5V VADJ Table 1 28 shows the VITA 57 1 FMC HPC connections The connector pinout is in Appendix C VITA 57 1 FMC LPC J63 and HPC J64 Connector Pinout Any signal named FMC_HPC_xxxx that is wired between a U1 FPGA pin and some other device does not appear in this table Table 1 28 VITA 57 1 FMC HPC Connections bc Schematic Net Name ja 5 R ECR Schematic Net Name U h A2 FMC_HPC_DP1_M2C_P AE3 B12 FMC_HPC_DP7_M2C_P AP5 A3 FMC_HPC_DP1_M2C_N AF4 B13 FMC_HPC_DP7_M2C_N AP6 A6 FMC HPC DP2 M2C P AF5 B16 FMC HPC DP6 M2C P AM5 A7 FMC HPC DP2 M2C N AF6 B17 FMC_HPC_DP6_M2C_N AM6 A10 FMC HPC DP3 M2C P AG3 B20 FMC_HPC_GBTCLK1_M2C_P AK6 All FMC_HPC_DP3_M2C_N AG4 B21 FMC HPC GBTCLKI M2C N AK5 Al4 FMC_HPC_DP4_M2C_P AJ3 B32 FMC_HPC_DP7_C2M_P API A15 FMC HPC DP4 M2C N AJ4 B33 FMC HPC DP7 C2M N AP2 A18 FMC HPC DP5 M2C P AL3 B36 FMC HPC DP6 C2M P AN3 A19 FMC HPC DP5 M2C N AL4 B37 FMC_HPC_DP6_C2M_N AN4 A22 FMC_HPC_DP1_C2M_P AD1 A23 FMC_HPC_DP1_C2M_N AD2 A26 FMC_HPC_DP2_C2M_P AFI A27 FMC HPC DP2 C2M N AF2 A30 FMC HPC DP3 C2M P AH1 A31 FMC_HPC_DP3_C2M_N AH2 A34 FMC HPC DP4 C2M P AKI A35 FMC HPC DP4 C2M N AK2 A38 FMC HPC DP5 C2M P AMI A39 FMC HPC DP5 C2M N AM2
103. tion Table 1 8 shows the PCle connector P1 that provides up to 8 lane access through the GTX transceivers to the Virtex 6 FPGA integrated Endpoint block for PCle designs Table 1 8 PCle Edge Connector Connections P1 PCle Edge Connector a E Schematic Net Name Description Son t in Pin Number Pin Name acemen Pl KA Al6 PERpO Integrated Endpoint block GTXE1 X0Y15 F2 PCIE TXO N A17 PERn0 transmit pair PCIE TX1_P A21 PERp1 Integrated Endpoint block GTXEL X0Y14 H2 PCIE TX1 N A22 PERn1 transmit pair ii ao PCIE_TX2_P A25 PERp2 Integrated Endpoint block GTXEL X0Y13 K2 PCIE TX2 N A26 PERn2 transmit pair E M1 PCIE_TX3_P A29 PERp3 Integrated Endpoint block GTXE1 X0Y12 M2 PCIE TX3 N A30 PERn3 transmit pair ka A TXA A35 PERp4 Integrated Endpoint block GTXE1 X0Y11 P2 PCIE TX4 N A36 PERn4 transmit pair A TI PCIE TX5 P A39 PERp5 Integrated Endpoint block GTXE1 X0Y10 T2 PCIE_TX5_N A40 PERn5 transmit pair v PCIE_TX6_P A43 PERp6 Integrated Endpoint block GTXEL X0Y9 V2 PCIE_TX6_N A44 PERn6 transmit pair ii YA PCIE DY P A47 PERp7 Integrated Endpoint block GTXE1 X0Y8 Y2 PCIE_TX7_N A48 PERn7 transmit pair il Js PCIE_RXO_P Bis PETpO Integrated Endpoint block GTXEL XOY15 J4 PCIE_RXO_N B15 PETn0 receive pair ii K5 PCIE RX1 P B19 PETp1 A Integrated Endpoint block GTXE1 X0Y14 K6 PCIE RX1 N B20 PETn1 receive pair L3 PCIE RX2 P
104. tronic equipment This product complies with CE Directives 2006 95 EC Low Voltage Directive LVD and 2004 108 EC Electromagnetic Compatibility EMC Directive 96 www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012
105. uide UG534 v1 8 October 2 2012 XILINX NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC P5 M2C p P6 C2M N P6 C2M Pp P6 M2C N P6 M2C p P7 C2M N P7 C2M Pp P7 M2C N P7 M2C p GBTCLKO M2C N K RS A Mea KK NX KO Ko NET FMC HPC GBTCLKO M2C P NET FMC HPC GBTCLK1 M2C N NET FMC HPC GBTCLK1 M2C P NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC NET FMC HPC A00 CC N IA00 CC Pp AOL CC N A01 CC Pp HA02 N HA02 P HA03 N HA03 P HA04 N HA04 P HAOS N HAO5 P HA06 N HA06 P HAO7 N HAO7 P HA08 N HA08 P HA09 N HA09 P HA10 N HA10 P HA11 N HA11 P HA12 N HA12 P HA13 N HA13 P HA14 N HA14 P HA15
106. uide www xilinx com 69 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX 70 Voltage and current monitoring and control are available for selected power rails through Texas Instruments Fusion Digital Power graphical user interface GUI Both onboard TI power controllers are wired to the same PMBus The PMBus connector J3 is provided for use with the TI USB Interface Adapter PMBus pod TI part number EVM USB TO GPIO refer to http focus ti com docs toolsw folders print usb to gpio html The ML605 board is shipped with a TI flyer containing information that allows the user to purchase this EVM at a discount TI provides the Fusion Digital Power Designer software package http focus ti com docs toolsw folders print fusion digital power designer html which includes several tools capable of communicating with the UCD92xx series of controllers from a Windows based host computer via the PMBus pod The ML605 onboard connector J3 is wired for the TI EVM interface and provides access to the PMBUS and UCD9240s for monitoring purposes This is the simplest and most convenient way to monitor the power rails See Table 1 31 and Table 1 32 For details concerning the use of the Fusion software tool refer to the documentation offered in the Fusion Digital Power Designer GUI help system select Help gt Documentation and Help Center References For more detailed information about this technology and the
107. uired for each particular interface The FMC connectors J63 and J64 are connected to 2 5V V co banks Because each user s FMC card implements customer specific circuitry the FMC bank I O standards must be uniguely defined by each customer The latest version of the UCF can be found on the ML605 board documentation website at http www xilinx com ml605 NET CLK 33MHZ SYSACE LOC AE16 93 on U19 NET CPU RESET LOC H10 2 on SW10 pushbutton active High HH NET DDR3_A0 LOC L14 98 on JI NET DDR3 Al LOC Al6 97 on JI NET DDR3 A2 LOC B16 96 on JI NET DDR3 A3 LOC E16 95 on JI NET DDR3 A4 LOC D16 92 on JI NET DDR3 A5 LOC J17 91 on JI NET DDR3 A6 LOC A15 90 on JI NET DDR3 A7 LOC B15 86 on JI NET DDR3_A8 LOC G15 H 89 on JI NET DDR3_A9 LOC F15 85 on JI NET DDR3_A10 LOC M16 107 on J1 NET DDR3_A11 LOC M15 84 on JI NET DDR3 A12 LOC H15 83 on JI NET DDR3 A13 LOC JIS 119 on J1 NET DDR3_A14 LOC D15 80 on JI NET DDR3 A15 LOG C15 78 on JI NET DDR3 BAO LOC K19 109 on J1 NET DDR3 BA1 LOC J19 108 on J1 NET DDR3 BA2 LOC L15 79 on JI NET DDR3 CAS B LOC C17 115 on JI NET DDR3 CKEO LOC M18 73 on JI NET DDR3 CKE1 LOC M17 74 on JI NET DDR3 CLKO N LOC H18 103 on J1 NET DDR3 CLKO P LOC G18 101 on J1 NET DDR3
108. used for both versions The HPC version is fully populated with 400 pins present and the LPC version is partially populated with 160 pins The 10 x 40 rows of a FMC LPC connector provides connectivity for e 68 single ended or 34 differential user defined signals e 1MGT e 1 MGT clock e 2 differential clocks e 61 ground 10 power connections Of the above signal and clock connectivity capability the ML605 implements the full set e 34 differential user defined pairs e 34 LA pairs e 1MGT e 1 MGT clock e 2 differential clocks Signaling Speed Ratings e Single ended 9 GHz 18 Gb s e Differential e Optimal Vertical 9 GHz 18 Gb s e Optimal Horizontal 16 GHz 32 Gb s e High Density Vertical 7 GHz 15 Gb s Mechanical specifications e Samtec SEAM SEAF Series e 1 27mm x 1 27mm 0 050 x 0 050 pitch The Samtec connector system is rated for signaling speeds up to 9 GHz 18 Gb s based on a 3 dB insertion loss point within a two level signaling environment Note The ML605 board VADJ voltage for the FMC HPC and LPC connectors J64 and J63 is fixed at 2 5V non adjustable The 2 5V rail cannot be turned off The ML605 VITA 57 1 FMC interfaces are compatible with 2 5V mezzanine cards capable of supporting 2 5V VADu ML605 Hardware User Guide www xilinx com 65 UG534 v1 8 October 2 2012 Chapter 1 ML605 Evaluation Board XILINX Table 1 30 shows the VITA 57 1 FMC LPC connections The connector pinout is in Appendix C VITA 5
109. various power management controllers and regulator modules offered by Texas Instruments visit http www ti com ww en analog digital power index html www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description 22 System Monitor The System Monitor provides information regarding the FPGA on chip temperature and power supply conditions via JTAG and an internal FPGA interface The System Monitor can also be used to monitor external analog signals via 17 external analog input channels For more information regarding this functionality which is featured on every Virtex 6 family member see http www xilinx com systemmonitor This section provides a brief overview of the System Monitor related functionality that is supported on the ML605 Reference and Power Supply The System Monitor has dedicated analog power supply pins and supports the use of an external 1 25V reference IC U23 for the analog to digital conversion process An option using jumper J19 to select an on chip reference is also provided however the highest accuracy over a temperature range of 40 C to 125 C is obtained using an external reference Figure 1 29 illustrates the power supply and reference options on the ML605 For a more detailed discussion of these requirements see the Virtex 6 FPGA System Monitor User Guide Ref 15 VCC2V5 Analog Supply Filter SYSMON_AVDD a ai NO SYSMON VREFP REF3012
110. ween the shifted side of said device and the FMC HPC pin listed has the same signal name without the LS on the end 2 These signals do not connect to U1 FPGA pins The pin numbers in the right hand column identify the device and pin these signals are connected to U88 17 U88 pin 17 and so on ML605 Hardware User Guide UG534 v1 8 October 2 2012 www xilinx com 63 Chapter 1 ML605 Evaluation Board 64 Table 1 29 Power Supply Voltages for HPC Connector XILINX Voltage Supply Gia ne No Pins Max Amps Tolerance mex ars VADJ Fixed 2 5V 4 5 1000 uF VIO_B_M2C 0 VADJ 1 15 5 500 uF VREF A M2C 0 VADJ 1 mA 2 10 uF VREF_B_M2C 0 VIO_B_M2C 1 mA 2 10 uF 3P3VAUX 3 3V 20 mA 5 150 uF 3P3V 3 3V 3 5 1000 uF 12POV 12V 1 5 1000 uF www xilinx com ML605 Hardware User Guide UG534 v1 8 October 2 2012 XILINX Detailed Description 20 VITA 57 1 FMC LPC Connector The ML605 implements both the High Pin Count HPC J64 and Low Pin Count LPC J63 connector options of VITA 57 1 1 FMC specification This section discusses the FMC LPC J63 connector Note The FMC LPC J63 connector is a keyed connector oriented so that a plug on card faces away from the ML605 board The FMC standard calls for two connector densities a High Pin Count HPC and a Low Pin Count LPC implementation A common 10 x 40 position 400 pin locations connector form factor is

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