User Guide
Contents
1. APEX FPGA 1 EPM7064 CPLD 1 0 1 0 The JTAG connection is most commonly used to download user configuration files sof to the APEX device chip during logic development and debugging In this case it is usually most convenient to leave switches n 2 and n 4 in the connect position and switches n 1 and n 3 in the unconnected position The EPM7064 device U2 is programmed as a configuration controller Most users will never need to reprogram the configuration controller Re programming U2 may result in an inoperable FPGA board Therefore it s strongly recommended to leave switches n 1 and n 3 in the unconnected position The design implementation and programming files for the configuration controller are available at user s disposal JTAG connector on the interface adapter TCK 1 2 GND TDO 3 4 3 3V TMS 5 6 TRST N C 7 8 N C TDI 9 10 GND Figure 16 Signals on the JTAG connector of the interface cable FPGA Module User Guide St phane Hofmann 2 4 7 Configuration controller The configuration controller U4 is an Altera Max7000 device family PLD EPM7064AE It was factory programmed with logic that configures the APEX device U1 from data stored in flash U3 on power up On power up or when the reset switch SW2 is pressed the configuration controller begins reading data out of the flash memory The flash memory APEX device and configuration controller are connected so that data from the flash conf2. A distinct UART port is connected with the Khepera s one e K NET bus This is a SPI based bus but it allows to addressing many different turrets like the DC bus See K NET bus documentation from K team In such a configuration all extension turrets are in Slave mode e Address decoding The FPGA module works directly with the Khepera addresses and data The communication controller on the FPGA module should be implemented with program which is executed by the Nios Hardware implementation on the FPGA is also possible but requires more time 23 FPGA Module User Guide St phane Hofmann 5 3 Design download on FPGA After the design has been successfully compiled it can be downloaded with JTAG interface in the FPGA for testing and evaluation Quartus provides also a simulation tool Executables files srec can also be downloaded with the serial line connector with help of Bash terminal nios run command but C C file should be previously compiled with the nios build command Debugging can be performed either by sending data on the bash terminal or by using the SignalTap functionality in Quartus SignalTap allows capturing functional data with JTAG while a device is operating 5 4 Design download tn flash Once successfully tested the users can download the design on the flash so the FPGA configures automatically with the user design on power up or on system reset To perform this stage the reference_design_32_b
3. Signals on J2 connector pins 22 St phane Hofmann FPGA Module User Guide St phane Hofmann 5 Typical FPGA Development Flow This chapter is user oriented and gives typical stages for new design implementation on the FPGA board turret with or without the Khepera 5 1 Reference design selection Four different reference designs are available with a Nios Processor see table 6 These designs can be found in the FPGA_module_ref_designs directory Table 6 Reference designs and their features Reference 5 S reference reference SE EE _design_16_bit _design_32_bit 16 bit Nios 32 bit Nios 16 bit Nios 32 bit Nios EE E UART1 115 200 baud used to download executable files with PC H UART2 38 400 baud connected on Khepera s serial port Internal ROM with resident GERM boot monitor program Interface to 32KByte of Interface to 256KByte of Internal RAM 4Kbytes 0 wait state external 0 wait state external SRAM SRAM Flash Interface to 1Mbyte external Flash memory Parallel I O The user can start his design from one of these reference designs All user I O signals are grouped in a schematic file FPGA_module_pins bdf and can be copied and added in the design 5 2 Communication protocols with Khepera There are three ways to communicate with the Khepera e Serial Line It s a simple way to communicate with the FPGA in a Master mode In the actual reference designs only that communication mode is used
4. 5V tolerant extension MicroMaTch connector Serial connection or 2 user I O One RS 232 serial port Two user definable push button switches Three user definable LEDs Joint Test Action Group JTAG connector for ByteBlasterMV and MasterBlasters Programmers Oscillator and zero skew clock distribution circuitry Power on reset circuitry Excalibur development board compatible peripherals Excalibur development board compatible software development Kit 2 3 Layout SW3 SW5 CPU reset push button CLEAR Top side Configuration 8 DIP Switch array TPCLK TP_GNDA TP_GNDB Clock TP pin Additional GND pins J2 18 pin 3 3V Extension Connector 2 TP1_8A TP1_8B 1 8V TP pins Di D1 D2 D3 Ble XT1 user LEDs Ke Wat 33 33MHz Oscillator q5 U1 E J1 APEX EP20K200E device D I We 18 pin 3 3V FPGA Vd Extension Connector 1 p a R Le SI TP_3_3A TP_3_3B TP_3_3C SW4 3 3V TP pins System reset push button RESET D4 J3 Flash byte LED 14 pin J4 4 pin 5V tolerant Extension connector Configuration connector JTAG amp Serial port connector Figure 5 TOP side FPGA Board component layout FPGA Module User Guide St phane Hofmann Bottom side U7 RS232 transceiver TP_GNDA TP_GNDB cl Additional GND pins controller CPLD SW1 TP1_8A TP1_8B User push button 1 1 8V TP pins El TPCLK U4 Clock TP pin au Suppl
5. power LED fee eb 6 88 Sal git Rak eRe ee Bi Led enable switch Ys Push button enable switch User Figure 28 Demo Module layout 4 2 Features 11 user LEDs D1 to D11 Power indicating LEDs 3 3V D12 and 5V D13 2 user push buttons PB1 amp PB2 A MicroMatch 18 pin female connector J1 to connect the J3 connector of FPGA module with an interface cable e A 18 DIP extension male header J2 witch same pins order than extension connector J3 of FPGA_module e A 14 DIP 5V tolerant male connector J3 compatible with the Excalibur Board s LCD module e ALED enable switch LED_EN e A push button enable switch PB_EN 20 G LCD connector rr e User push button 1 push button 2 kik Figure 29 Picture of Demo Board FPGA Module User Guide 4 3 Demo Board components 18 pin female MicroMatch connector 31 This connector must be connected with a specific interface connector to only J3 3 3V extension connector of FPGA module for pin compatibility Push buttons amp PB enable switch As in the FPGA module push button switches are connected to a pull up resistor disconnects these resistors which allows using pin 17 and A switch PB_en 18 as a normal user I O on connector J2 LEDs The 11 user LEDs can be disconnected by a switch too Ext lt 10 0 gt on J2 connector can be used in any case LEDs on LEDs off LED_en Nevertheless signals Interface connector
6. wm ww ww ww ww ww ww mm vm ww ww vm mm mm mm wm Khepera bus Configuration download Extension connectors Vcc 5V GND RxD TxD Figure 2 Global architecture of FPGA module Khepera extension bus FPGA Module User Guide St phane Hofmann 2 FPGA Board Turret 2 1 Architecture Extension connector 1 Extension connector 2 Serial ext nea gt FLASH CPLD JAF RS232 Gm gt Transceiver demm Ji Configuration amp download connector f FPGA board turret Figure 3 FPGA Board Architecture Em o aa O iF T WAN AEN ke a TE OO Seef ae o 900 Pi ve ce Sata D stustan n ANADAN mro rs 7 F H imha a t L d d WI ose et teen i ps de ies EIS e A zu J See SE Zu aa i ri ii Wi G CT gp H AU EZE Fr i A et a w s ee Er EA II 4 E E f E E E z2 AF staitiEISt t tiSIsratist Let risi idtitipISb Aere Heel mu prey j ITT WE rf PS a kr See EI E SI d z ETJ ee Figure 4 Pictures of FPGA Board turret left top side right bottom side FPGA Module User Guide St phane Hofmann 2 2 Features e An APEX 20K200E 2X device FPGA 1 Mbyte 512 K x 16 bit of Flash memory o pre configured with a 32 bit Nios reference design and software 256 Kbytes of SRAM in 2 64K x 16 bit chips On board logic for configuring APEX device from flash memory 3 3V compact extension connector access to 22 user I O
7. 13 ClockLock amp ClockBoost PLL features Some APEX devices with a X suffix after the speed grade like the EP20K200EQC208 2X on the FPGA board have C ockLock amp ClockBoost PLL features The C ockBoost feature is used in conjunction with the C ockLock phase locked loop feature It can be used to generate internal clocks that operate at frequencies that are multiples of the frequency of the system clock The C ockBoost feature also provides clock delay reduction Programmable clock delay and phase shift is also provided by a ClockShift circuitry with a resolution range of 0 4 ns to 1 0 ns Roe rr nn nr nn ne nn ne nn nn ne ne ne ne ne ne ne ne ne nn ne nn no oo oe Phase Comparator Voltage Controlled Oscillator e e MN A j ClockShift Circuitry A Figure 20 Schematic view of the altcklock megafunction ClockLock and C ockBoost features are available in Quartus with the help of the altclklock megafunction In the actual APEX device up to two PLLs can be implemented see figure 20 Each PLL includes circuitry that provides clock synthesis for two outputs using m n x k and m n x v scaling factors m n and v are integer values When a PLL is locked the locked output aligns to the rising edge of the input clock 13 FPGA Module User Guide St phane Hofmann 4 Dedicated Clocks G4 G1 Extension connectors CLK4p 33MHz oscillator CLK2p CLKLK_FB2p i Yod CLKLK_OUT2p l
8. D gt FACULTE DES SCIENCES ET FPGA Module User Guide St phane Hofmann KI ere er eee IR BT TECHNIQUES DE L INGENIEUR E ECOLE POLYTECHNIQUI AER JE LAUSANNI ee AUTONOMOUS SYSTEM LAB 2 ASL2 FEDERALE Content E 1 FPGA Module Architecture sssssssssonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnna 1 U se r G u id e 2 FPGA Board Turret E 2 Do PT O eege 2 RN EE 3 De NSA OM A EE TT EATE A E E A E A OE E SEE A 3 F PG A Tu rret Fo r 2 A Component description EE 4 PA DN E 4 Pe Bed DEEN e 5 Khepera Mobile Robot GT EE 5 2 4 4 Tee 3 2 4 5 5V tolerant extension Connector sa cccneercsaleetiseceenebiceuudterarntecceneomeniieediueceetesneuuieeliwedes 6 2 4 6 Configuration Download connector cceceessseccecceecesessseceeeeeceeseeeessseeeeeeecesseeeesaaeas 7 24 7 Configuration controller asser iaie E nia 9 SR Me E EE 10 SEENEN 11 AOE EE 11 SEENEN 12 2 4 12 Apex Self configuration optional Teature 13 2 4 13 ClockLock amp ClockBoost PLL features ccccccccccceccecceesesessssseeeeeeeeeeeeeeeas 13 2 4 14 Multiple FPGA Boards configuration sooenoenneeeonssessssseeeesesssssnsreressssssssesreeee 15 3 Power Board Turret ess egiesggekieek ek sek SER KEEN Sek a a 17 3 1 Power Board architecture c cccccccccceccesssssscceeeceeceseseessnseeeeeececeeeeesesssaeeeeeeeeeseesessnnaaeess 17 EE 17 33 Layout amp COMMON NiS seirinin i e e ariasi 18 3 3 1 1 8 V 3 3V and GND OUtputs 22 ccc
9. EXT pin it is important to configure correctly the pin property on each board The switches n 7 and n 8 of SW5 allow the user to configure the clock circuitry mode clk_Apex0 clk clk_Apex1 driver ck D ck_Osc2 driver Pik _Osc3 Oscillator Single FPGA board DIP SW7 DIP SW8 Figure 23 Clock signal connections in Single FPGA board configuration Multiple FPGA boards mode MASTER The oscillator drives the devices on the board through the clock driver and the CLK_EXT clk output Switches configuration o switch n 7 on o switch n 8 on Multiple FPGA boards mode SLAVE The oscillator is unconnected and the devices on the board are driven by the CLK_EXT pin clk input through the clock driver Switches configuration o switch n 7 off o switch n 8 on 15 FPGA Module User Guide St phane Hofmann Master Slave clk_Apex0 clk_Apex0 ana ck D ck Apext BEER ck EU ck Apexi driver driver Oscillator clk_Osc2 driver Pk Osc3 DIP SW7 DIP SW7 DIP SW8 DIP SW8 Figure 24 Clock circuit in a Multiple FPGA Boards in a master slave configuration If both switches are off no clock signal feeds the board s devices and the FPGA module cannot operate It is recommended to avoid driving devices with more than one oscillator This may alter the modules functionality The communication between the modules can be performed with the Khepera bus pins or through the extension c
10. L s output from U5 A 5V power supply pin connected physically to VCC_EXT Khepera power pin A regulated 3 3 V power supply pin A ground connection The user should be careful with pins numeration because it unhappily doesn t begin on the same side for both J1 and J2 connectors FPGA Module User Guide St phane Hofmann Pin 1 of J2 J2 3 3V 2 1 5V clk_APEX0 4 3 GND FAST Ext lt 0 gt 181 6 5 clk_Osc2 FAST Ext lt 2 gt 77 8 7 FAST Ext lt 1 gt 81 Ext lt 4 gt 116 10 9 Ext lt 3 gt 119 Ext lt 6 gt 88 12 11 Ext lt 5 gt 89 Ext lt 8 gt 85 14 13 Ext lt 7 gt 87 Ext lt 10 gt 124 16 15 Ext lt 9 gt 84 Ext lt 12 gt 113 18 17 Ext lt 11 gt 117 Figure 8 Signals on J2 connector Ji 3 3V 2 1 5V clk_APEXi1 4 3 GND Ext lt 13 gt 13 6 5 clk_Osc3 il PX Ey Ext lt i5 gt 15 8 7 Ext lt 14 gt 14 SS BE N y Pin 1 of J1 Ext lt 17 gt 116 10 9 Ext lt 16 gt 119 Ext lt 19 gt 88 12 11 Ext lt 18 gt 89 Figure 7 3 3V extension connectors Ext lt 21 gt 85 14 13 Ext lt 20 gt 87 Ji and J2 Ext lt 23 gt 124 16 15 Ext lt 22 gt 84 Ext lt 25 gt 113 18 17 Ext lt 24 gt 117 Figure 9 Signals on J1 connector 2 4 5 5V tolerant extension connector J4 is a 5V tolerant little MicroMaTch 90 4 pin connector It has only two general 5V I O and two GND pins It can be used as an additional 5V serial line with RxD and TxD lines The serial resistances should be adapted according t
11. __ J d a J d H a d W H 3 3V part J d a ad J 1 d 3 3V Khepera 5V power enable Standard serial S connector switch 5V Rxd TxD GND GND Figure 27 Power Board layout of components At first sight the power PCB seems symmetrical cf figure 27 The dual step down is placed in the center and on each side are the parts related with the correspondent step down inductance output capacitor resistor divider etc 3 3 1 1 8V 3 3V and GND outputs The outputs of generated voltages are connected to supplementary TP pins The 1 8V is available on two pins and the 3 3V on three pins Multiple pins for the same tension prevents the voltage from decreasing due to the serial resistance contact between the female TP pin on that board and the male TP pin of the plugged FPGA turret or any other turret For the same reason two GND TP pins are added In the whole there are four GND TP pins 3 3 2 Power indicator LEDs On the edge of the board two LEDs indicate to the user the presence of voltages e A yellow LED D7 informs about the presence the input voltage 5V e A green LED D8 is connected on the 3 3V output and therefore indicates the presence of a voltage on the 3 3V output and indirectly on the 1 8V too because of the output sequence 18 FPGA Module User Guide St phane Hofmann 3 3 3 Standard serial S connector The con
12. cable SAMTEC 18 pins male connector to plug on the FPGA hoard 12 St phane Hofmann 5V 3 3V GND clk_Apex clk_Osc Ext lt 0 gt LED1 Ext lt 1 gt LEID Ext lt 2 gt LEID Ext lt 3 gt LED4 10 Ext lt 4 gt LED5 11 Ext lt 5 gt LED6 12 Ext lt 6 gt LED7 13 Ext lt 7 gt LED8 14 Ext lt 8 gt LED9 15 Ext lt 9 gt LED10 16 Ext lt 10 gt LED11 17 Ext lt 11i gt PB1 18 Ext lt 11 gt PB2 WOON AU Ob Ee 18 pin MicroMaTch male connector to plug on the DEMO Board J1 Figure 31 Interface connector cable 5V header LCD connector J3 The power pins of these connector are compliant witch the LCD module if the Excalibur Development Board All signal pins on this connector have a serial resistance of 15092 and clamping diode are connected to 3 3V as on the FPGA module GND N C Ext lt 1 gt Ext lt 3 gt Ext lt 5 gt Ext lt 7 gt Ext lt 9 gt ON OW k 13 J3 2 5V 4 Ext lt 0 gt 6 Ext lt 2 gt 8 Ext lt 4 gt 10 Ext lt 6 gt 12 Ext lt 8 gt 14 Ext lt 10 gt Figure 32 Signals on J3 connector pins 21 Figure 30 Signals on J1 connector pins FPGA Module User Guide 3 3V extension connector J2 5V GND Clk_Osc Ext lt 1 gt Ext lt 3 gt Ext lt 5 gt Ext lt 7 gt Ext lt 9 gt Ext lt 11 gt J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 3 3V clk_Apex Ext lt 0 gt Ext lt 2 gt Ext lt 4 gt Ext lt 6 gt Ext lt 8 gt Ext lt 10 gt Ext lt 12 gt Figure 33
13. ccavcsesseecicdeatandsaedsesnsesdecsasseaveredaeedocdactaacsasiesenscnees 18 3 3 2 Power mdicator E CR CN 18 3 3 3 Standard serial S connector cee ccecessssccececcceeeeeessseceeeeeceeseesessnsceeeeeeeeseseessseaaees 19 SE ACU STS E 19 4 Demo Module Board sessisiisstecidccecteciddedsveneecctessuntsnstcancecedectitantaensensisensenane 20 a E 20 LLE E 20 4 3 Demo Board components 0 ccececeessssccecceceeeeesssecceeeeccceeseesseeeeeeeeeeeseseeessseaeeeeceeseseeneas 21 5 Typical FPGA Development FIOW sscscsscssesssenseseeeeseeenseeeeenseeenensensnenees 23 5 1 Reference design SCS e EE 23 5 2 Communication protocols with Kheperg 23 5 5 Design download on R NNEN 24 St phane Hofmann 5 4 Design download ENEE 24 February 2003 FPGA Module User Guide St phane Hofmann 1 FPGA Module Architecture FPGA Board turret digital part FPGA module Power Board turret analog part Figure 1 FPGA module picture The system is composed of two different functional parts 1 The digital part FPGA Board which includes the major components as the FPGA the CPLD the memories the oscillator the transceiver 2 The analog part Power Board which comprises the voltage regulators that generates the 1 8V and the 3 3V needed to supply the digital part GND 5V 3 3V 1 8V Kee ll seen el eh i Extension turret s ieas a vill JJ see ee nahe des a ellllll IEF s da ape enn ellllt Mew ew ew
14. ch switch is given in the table 3 Figure 17 8 DIP Switch array position Table 3 Function name Description Switch n If ON the JTAG connector pin TDO is connected to the MAX7064 CPLD If ON the JTAG connector pin TDO is connected to the APEX FPGA JTAG target device selection If ON the JTAG connector pin TDI is connected to the MAX7064 CPLD If ON the JTAG connector pin TDI is connected to the APEX FPGA If ON the default FPGA configuration on the flash is Configuration file charged on the FPGA at next power up sequence even selection if there is a user configuration in the second part of the flash Auto configuration If ON the auto configuration ability of the Apex is ability activated If ON connect the oscillator clock signal to the on Clock circuitry board devices configuration If ON the click output or input is enabled 10 FPGA Module User Guide St phane Hofmann 2 4 9 Push buttons SW1 91 SW2 90 and SW4 184 are momentary contact push button switches Each is connected to an APEX device general purpose I O and a pull up resistor The APEX device will see a logic 0 when each switch is pressed SW1 and SW2 which can be found on the reverse side of the FPGA board are user definable The other switches SW3 and SW4 are dedicated and have the following fixed functio
15. ded can identify the 1 MB flash in its address space and includes monitor software that can download files either new APEX device configurations Nios software or both into flash memory The Nios SDK includes subroutines for writing and erasing this specific type of AMD flash memory 2 4 3 SRAMs U3 and U8 IDT71V016SA12BF are 256 Kbytes 64K x 16 bit asynchronous SRAM chips They are connected to the APEX device so that they can be used by a Nios processor as general purpose zero wait state memory The SRAMs can be configured for use with either 16 bit 64K x 16 or 32 bit 64K x 32 applications The two 16 bit devices can be used in parallel to implement a 32 bit wide memory subsystem The Nios 32 bit reference design identifies these SRAM chips in its address space as a contiguous 256 Kbytes 32 bit wide zero wait state main memory The Nios 16 bit reference design uses only one memory chip 2 4 4 3 3V Extension connectors Ji and J2 are compact SAMTEC 18 pins female black connectors that can be used as an interface to a user board for example These connectors can drive a 5V logic device but a 5V logic device cannot drive the APEX device unless a clamping diode is added with a serial resistance see APEX 5 V tolerance White Paper Each 3 3V extension connector interface includes 13 APEX device general purpose I O signals A buffered zero skew copy of the on board oscillator from U5 A buffered zero skew copy of the APEX PL
16. device but only that the configuration controller has finished sending data to the APEX device 11 FPGA Module User Guide St phane Hofmann 2 4 11 Clock circuitry DIP SW8 fh clk EXT TP U1 FPGA APEX CLK2 CLK4 CLKLK_OUT2p CLKLK_FB2n Clk_Apex0 J1 pin 4 33MHz oscillator DIP SW7 CPLD MAX7064 pin 37 Clk_Osc2 Ji pin 5 Clk_Osc3 J2 pin 5 Clk_Apex1 J2 pin 4 Figure 18 Clock circuitry The FPGA board includes a 33 33MHz oscillator and a zero skew clock distribution networks e The first network drawn in blue is generated by the board s own oscillator or an external one Components are driven by the clock distribution chip U5 The oscillator is driven to the APEX pin 131 the configuration controller U2 and the two extension connectors J1 and J2 e The second type of clock network drawn in red carries a signal produced by the phase locked loop circuitry on the APEX EP20K200E device The user has the option of producing a clock with the PLL circuitry by the use of the a tck ock megafunction in the Quartus II software see ClockLock amp ClockBoost PLL Features in 2 4 13 which may be driven off chip via pin 120 CLKLK_OUT2p The signal is also fed to the clock distribution chip U5 and fed to both main extension connectors J1 amp J2 The oscillator may be replaced at the user s discretion but the configuration controller design may fail to s
17. ication with a desktop APEX Pin 37 38 workstation using a 9 pin serial cable Connector Pin 2 2 3 4 5 connected to a COM port The transmit TXD receive RXD clear to send CTS and ready to send RTS signal use RS 232 standard high voltage levels U7 is a level shifting buffer that presents or accepts 3 3V versions of these Connector Pin 6 7 8 9 signals to and from the APEX device APEX Pin 40 34 Function N C CTS RTS N C Figure 15 Signals on the serial port connector pins of the interface cable FPGA Module User Guide St phane Hofmann 2 4 6 2 JTAG connector part The JTAG connector on the interface adaptor is compatible with Altera ByteBlasterMV and MasterBlaster programming cable The JTAG connection can be used for one of two purposes 1 Quartus II software can configure the APEX device U1 with a new bitstream file sof via a MasterBlaster or ByteBlasterMV programming cable 2 Quartus II or MAX PLUS II software can re program the EPM7064 device U4 with a new pof file via a MasterBlaster or ByteBlasterMV programming cable For each device two switches connect or unconnect the TDI and TDO JTAG lines Only one device can be configured at the same time with a new JTAG chain The four switches on the switch array determine which device is connected for configuration through its JTAG pins Table 1 Switch array configuration for JTAG connection on FPGA 8 DIP Switch array SW5 Selected device n 4
18. igures the APEX device in passive parallel mode 2 4 7 1 Configuration Data The Quartus II software can optionally produce hexout configuration files which are directly suitable for download and storage in the flash memory as configuration data A hexout configuration file for the APEX20K200E device U1 is a little less than 256Kbytes and thus occupies about 1 4 of the flash memory U3 New hexout can be stored in the flash memory U3 by software running on a Nios processor The preloaded 32 bit Nios reference design includes the GERMS monitor program that supports downloading hexout files from a host e g desktop workstation into flash memory See the Nios Embedded Processor Software Development User Guide for a detailed description of the GERMS monitor program 2 4 7 2 Factory and User Configurations The configuration controller can manage two separate APEX device configurations stored in flash memory These two configurations hexoutfiles are conventionally referred to as the user configuration and the factory configuration Upon reset or when the reset switch SW2 is pressed the configuration controller will attempt to load the APEX device with user configuration data If this process fails either because the user configuration is invalid or not present the configuration controller will then load the APEX device with factory configuration data The configuration controller expects user configuration and factory configurati
19. it should be first be implemented on the FPGA with a GERMS monitor which allows the user to download a configuration file in the flash But before the configuration file should be converted in an adequate format flash hexout2flash routine converts the hexout configuration file in the adequate format The file can then be downloaded in flash with the n os run command automatically at 0x180000 flash memory location and the design becomes the default booting design for the FPGA module Executable file can also be stored on the flash The GERMS monitor will automatically execute code from flash to SRAM after initialisation see srec2flash routine A detailed description is given in the Nios Embedded Processor Software Development Reference 24
20. nector is a MicroMaTch 90 with 6pins The pins are compatible with the serial line S connector furnished with the Khepera kit 1 VCC Power supply 5V 2 RxD Serial receive data TTL levels 3 TxD Serial transmit data TTL levels 4 GND Power supply ground 5 GND Power supply ground 6 GND Power supply ground Figure 27 Signals on S line connector 3 4 Characteristics 3 3V Output Voltage versus Current load amp Vin 4 0V m Vin 4 5V Vin 5 0V Vin 5 5V Output voltage V 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 1 6 1 8 Current A Graph 1 3 3V output voltage versus current load 3 3V Output Voltage versus Current load A Vin 4 0V a Vin 4 5V Vin 5 0V Vin 5 5V Output voltage V 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 1 6 1 8 Current A Graph 2 3 3V output voltage versus current load 19 FPGA Module User Guide 4 Demo Module Board St phane Hofmann A demonstration Module board was realised to extend the FPGA module s user interfaces This module can be connected on J2 3 3V extension connector 4 1 Layout 18 pin MicroMatch 11 user LEDs connector J1 to connect to FPGA module 18 pin male header 3 3V extension connector J2 YI is wm we See 3 3V power LED memana Sc Sa mv mr my mv an FREED NA N geliest connector J3 S F ez 8 8 elja a E 5V
21. ns 2 4 9 1 SW3 CLEAR When SW3 is pressed a logic 0 is driven onto the APEX devices DEV_CLRn pin and user I O 184 The result of pressing SW3 depends on how the APEX device is currently configured The pre loaded Nios reference design treats SW3 as a CPU reset pin The reference Nios CPU will reset and start executing code from its boot address 0 when SW2 is pressed 2 4 9 2 SW4 RESET When SW4 is pressed a logic O value is driven to U7 the power on reset controller Pressing SW4 is equivalent to a power on reset When SW4 is pressed or when the board is power cycled the configuration controller will load the APEX device from flash memory See 2 4 7 more information When the development board is delivered from the factory the APEX device will be configured with the 32 bit reference design at power up or when SW4 is pressed The reference design will then begin executing the GERMS monitor a serial debug download utility 2 4 10 LEDs 2 4 10 1 User LEDs Three users LEDs D1 D2 D3 of different colours are each controlled by a general purpose I O of the Apex device Each LED will light up when the APEX device drives a logic 1 on its controlling output Table 4 LEDs color ep name zent agoe os e e o 2 4 10 2 Dedicated LED The green LED D4 indicates that the configuration controller has finished configuring the APEX EP20K200E device This LED does not indicate successful configuration of the APEX
22. o the connected 5V device 3 3V devices can drive the APEX through this interface without any restrictions J4 APEX e E ke Ze KE 1 5V UO 98 ZE 2 5V 1 0 97 ii 3 GND P2 Pa Tao wear Tee mea 4 GND ma Ss PAA Figure 10 Signals on J4 connector Pin 1 of J4 Figure 11 J4 connector position FPGA Module User Guide St phane Hofmann 2 4 6 Configuration Download connector On the Excalibur development board the serial port connector and the JTAG connector are separated but in the FPGA board because of limited area they are combined in one compact SAMTEC 14 pin female connector The first eight pins are dedicated to the JTAG part and the other pins are dedicated for the serial port A special interface adapter allows the user to connect both the ByteBlasterMV download cable on the JTAG part and the serial port cable see figure 14 J3 2 GND TCK 1 4 43 3V TDO 3 JTAG pins 6 TRST TMS 5 8 GND TDI 7 10 RTS TXD 9 Serial port 12 CTS RXD 11 DINS 14 N C GND 13 Pin 1 of J3 Figure 13 Signals on J3 pins 10 pin connector header to lt q connect the ByteBlasterMV flat bus cable download cable SAMTEC male connector to plug on wm Female DB9 pin for serial the FPGA board flat bus cable cable Ww Figure 14 Interface cable 2 4 6 1 Serial Port connector part The serial port connector part is typically used Function GND N C RXD TXD N C for host commun
23. on files to be stored at fixed locations offsets in flash memory The following table Table 2 shows how the configuration controller expects flash memory contents to be arranged Table 2 Flash Memory Allocation Flash Memory Allocation 0x100000 0x17FFFF 512 Kbytes Nios instruction and nonvolatile data space User defined APEX device configuration data 0x180000 0x1BFFFF 256 Kbytes 0x1C0000 0x1FFFFF 256 Kbytes Kbytes Factory default APEX device configuration The 32 bit Nios reference design is pre loaded into the factory configuration region of the flash memory It is recommends that users avoid overwriting the factory configuration data FPGA Module User Guide St phane Hofmann The switch n 5 of the 8 DIP Switch array SW5 changes the behavior of the configuration controller If the switch is ON the configuration controller will ignore the user configuration and always configure the APEX device from the factory configuration The switch allows the user to escape from the situation where a valid but non functional user configuration is present in flash memory In the pre loaded Nios reference design the 1 MB flash memory is mapped at base address 0x100000 Thus user hexout files should be downloaded to address 0x180000 flash base address user configuration offset 2 4 8 8 DIP Switch array This switch array is used to configure different options on the FPGA board The function of ea
24. onnectors As many slave FPGA boards can be used unless the power board is unable to power all FPGA boards Multiple FPGA boards feature gives a high level of flexibility Table 5 Resume of the modes and their configuration on 8 DIP Switch array SW5 Multiple FPGA board mode MASTER Multiple FPGA board mode SLAVE 16 FPGA Module User Guide St phane Hofmann 3 Power Board Turret 3 1 Power Board architecture 5V power 3 3V amp LSV indicator power indicator GND 5V 3 3V 1 8V TxD RxD GND step down WG RR LS Power board turret S line connector Khepera bus Figure 25 Power Board architecture 3 2 Features e 1 8V and 3 3V general use TP connectors with maximum load of 1 4A for each voltage level Power supply 4 5V to 25V 5V Khepera compatible Power indicator LEDs green 1 8V and 3 3V and yellow 5V Khepera compatible 6 pins connectors for separate external power input A switch to connect the separate external input power to the Khepera 5V TP connector VCC_Ext e Ability to connect any extension turret above and in particular up to three FPGA boards under some conditions ul m Ta E i a S i of Salat i A Figure 26 Power Board picture scale 1 1 17 FPGA Module User Guide St phane Hofmann 3 3 Layout amp Components Dual step down LT1940 1 8V and 3 3V GND power LED E es m al Bag DV power LED 1 8V part
25. t 4 Figure 21 FPGA s PLLs architecture A generated clock might be driven off chip via pin 120 CLKLK_OUT2p which are fed to the main extension connectors J1 amp J2 For a complete and detailed description of the features associated with altclklock megafunction see the Altera application note AN 115 14 FPGA Module User Guide St phane Hofmann 2 4 14 Multiple FPGA Boards configuration Extension turret s Slave 2 FPGA board 3 Slave 1 FPGA board 2 CLK_EXT Master FPGA board 1 Power board Khepera Figure 22 Multiple FPGA Boards configuration e Single FPGA board mode cf figure 23 The oscillator drives the devices on the board through the clock driver The CLK_EXT pin is unconnected Switches configuration o switch n 7 on o switch n 8 off To improve the resources the FPGA module can be used with two or more FPGA boards in master slave architecture as shown in figure 22 In such architecture each FPGA requires a common clock Signal in order to synchronize the communication between the devices In this configuration the master oscillator s output should be tied to all FPGAs clock s input The data indeed has to be latched or read on the same clock rising edge A dedicated supplementary TP pin called CLK_EXT can be used either as a clock input either as a clock output or as a non connected pin As all FPGA boards have the same physical connection with their CLK_
26. uccessfully configure the APEX EP20K200E device if the clock frequency is greater than 66 8MHz If the user oscillator s frequency is not 33 33MHz but less than 66 8MHz the CPLD configuration should be adapted according to comments in dclk_divider tdf source file In a single FPGA board use switches n 7 of SW5 switch array and should be on and n 8 off These switches are needed to configure the clock circuitry architecture in multiple FPGA boards use 2 4 14 The FPGA has four clock inputs CLK1 to CLK4 but only two inputs are used in the actual design 12 FPGA Module User Guide St phane Hofmann 2 4 12 Apex Self configuration optional feature Sophisticated Apex designs e g CPU systems might wish to reconfigure themselves That functionality is provided by the Apex_reload_n input pin35 in the MAX7064 CPLD If this pin is driven low OV the configure from flash sequence will restart A pull up resistance puts the Apex_reload_n signal in logic high level by default If an APEX user implementation always drives the Apex_reload_n low by error the system eternally reconfigures itself A dedicated switch switch n 6 on SW5 cf figure 19 allows the user to inactivate switch in off position the self configuration ability in such a situation in order to stop the process and then download a new configuration N 6 of SW5 Apex_reload_n spare0 Figure 19 Self configuration circuitry 2 4
27. y monitor U5 Se Clock distribution chip 7a U3 amp U8 E 4 SRAM U6 Se U2 Flash memory device Soha APEX configuration Wyer D I F a CC ip CE i SW2 User push button 2 TP_3_3A TP_3_3B TP_3_3C 3 3V TP pins Figure 6 BOTTOM side FPGA Board component layout 2 4 Component description 2 4 1 FPGA U1 is an APEX 20K200E device whose characteristics are given in the next table It can be configured with two separate methods e A JTAG interface can be used with Quartus II software via a programming cable e A configuration controller U2 that configures the device at power up from hexout files stored in the flash memory U6 EP20KE200EQC208 2xX characteristics EP20KE200EQC208 2X Device Family APEX 20KE Total Pins Speed grande PLLs Yes 30 4 x 30 4 FPGA Module User Guide St phane Hofmann 2 4 2 Flash memory U6 is an advanced micro devices AMD AM29LV800BB 1Mbyte flash memory chip It is connected to the APEX device so that it can be used for two purposes simultaneously 1 A Nios processor implemented on the APEX device can use the flash as general purpose readable writable non volatile memory 2 The flash memory can hold an APEX device configuration file that is used by the configuration controller to load the APEX device at power up A hexout configuration file that implements the 32 bit Nios reference design is pre loaded in this flash memory The 32 bit reference design once loa
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