MSP430x4xx Family User's Guide (Rev. G - webwww03
Contents
1. SCLK Figure 20 2 shows the USCI as a master in both 3 pin and 4 pin configurations The USCI initiates data transfer when data is moved to the transmit data buffer UCxTXBUF The UCxTXBUF data is moved to the TX shift register when the TX shift register is empty initiating data transfer on UCxSIMO starting with either the most significant or least significant bit depending on the UCMSB setting Data on UCxSOM1 is shifted into the receive shift register on the opposite clock edge When the character is received the receive data is moved from the RX shift register to the received data buffer UCxRXBUF and the receive interrupt flag UCxRXIFG is set indicating the RX TX operation is complete A set transmit interrupt flag UCxTXIFG indicates that data has moved from UCxTXBUF to the TX shift register and UCxTXBUF is ready for new data It does not indicate RX TX completion To receive data into the USCI in master mode data must be written to UCxTXBUF because receive and transmit operations operate concurrently Universal Serial Communication Interface SPI Mode 20 7 USCI Operation SPI Mode Four Pin SPI Master Mode In 4 pin master mode UCxSTE is used to prevent conflicts with another master and controls the master as described in Table 20 1 When UCxSTE is in the master inactive state 1 UCxSIMO and UCxCLK are set to inputs and no longer drive the bus J The error bit UCFE is set indicating a communication integrity violation t2. Chapter 20 Universal Serial Communication Interface SPI Mode The universal serial communication interface USCI supports multiple serial communication modes with one hardware module This chapter discusses the operation of the synchronous peripheral interface or SPI mode Topic Page 20 1 R LL e Raa TZ 20 2 20 2 USCI Introduction SPI Mode sss c cx x e e x c x eee Ke 20 3 20 3 USCI Operation SPI Mode ceeeeee cece eee e eee e eee 20 5 20 4 USCI Registers SPI Mode cece eee 20 14 20 1 USCI Overview 20 1 USCI Overview The universal serial communication interface USCI modules support multiple serial communication modes Different USCI modules support different modes Each different USCI module is named with a different letter For example USCI_A is different from USCI_B etc If more than one identical USCI module is implemented on one device those modules are named with incrementing numbers For example if one device has two USCI_A modules they are named USCI_AO and USCI_A1 See the device specific data sheet to determine which USCI modules if any are implemented on which devices The USCI_Ax modules support Q UART mode _j Pulse shaping for IrDA communications Automatic baud rate detection for LIN communications Lj SPI mode The USCI_Bx modules support 1 12C mode Lj SPI mode 20 2 Universal Serial Communication Interface SPI Mode USCI Introduction SPI M
3. SPI Mode 20 19 USCI Registers SPI Mode UCAxRXBUF USCI_Ax Receive Buffer Register UCBxRXBUF USCI_Bx Receive Buffer Register 7 6 5 4 3 2 1 0 r r r r r r r r UCRXBUFx Bits The receive data buffer is user accessible and contains the last received 7 0 character from the receive shift register Reading UCxRXBUF resets the receive error bits and UCxRXIFG In 7 bit data mode UCxRXBUF is LSB justified and the MSB is always reset UCAxTXBUF USCI_Ax Transmit Buffer Register UCBxTXBUF USCI_Bx Transmit Buffer Register 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UCTXBUFx Bits The transmit data buffer is user accessible and holds the data waiting to 7 0 be moved into the transmit shift register and transmitted Writing to the transmit data buffer clears UCxTXIFG The MSB of UCxTXBUF is not used for 7 bit data and is reset 20 20 Universal Serial Communication Interface SPI Mode USCI Registers SPI Mode IE2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 UCBOTXIE UCBORXIE UCAOTXIE UCAORXIE Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 These bits may be used by other modules See device specific data sheet USCI_BO transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_BO receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_AO transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_AO receive interrupt enable 0 Interrupt disabled 1 Interr
4. keeping the USCI in a reset condition When set the UCSWRST bit resets the UCxRXIE UCxTXIE UCxRXIFG UCOE and UCFE bits and sets the UCxTXIFG flag Clearing UCSWRST releases the USCI for operation e SD E RED Note Initializing or Re Configuring the USCI Module The recommended USCI initialization re configuration process is 1 Set UCSWRST BIS B UCSWRST amp UCxCTL1 2 Initialize all USCI registers with UCSWRST 1 including UCxCTL1 3 Configure ports 4 Clear UCSWRST via software BIC B UCSWRST amp UCxCTL1 5 Enable interrupts optional via UCxRXIE and or UCxTXIE ee 20 3 2 Character Format 20 6 The USCI module in SPI mode supports 7 and 8 bit character lengths selected by the UC7BIT bit In 7 bit data mode UCxRXBUF is LSB justified and the MSB is always reset The UCMSB bit controls the direction of the transfer and selects LSB or MSB first C O QQqo _ Note Default Character Format The default SPI character transmission is LSB first For communication with other SPI interfaces it MSB first mode may be required ee __ _ __ gt oe en G Note Character Format for Figures Figures throughout this chapter use MSB first format ss Universal Serial Communication Interface SPI Mode USCI Operation SPI Mode 20 3 3 Master Mode Figure 20 2 USCI Master and External Slave MASTER Receive Buffer UCxRXBUF Receive Shift Register MSP430 USCI COMMON SPI
5. x low byte rw rw rw rw rw rw rw rw UCAxBR1 USCI_Ax Bit Rate Control Register 1 UCBxBR1 USCI_Bx Bit Rate Control Register 1 7 6 5 4 3 2 1 0 UCBRx high byte rw rw rw rw rw rw rw rw UCBRx Bit clock prescaler setting The 16 bit value of UCxxBRO UCxxBR1x256 form the prescaler value 20 18 Universal Serial Communication Interface SPI Mode USCI Registers SPI Mode UCAXSTAT USCI_Ax Status Register UCBXxSTAT USCI_Bx Status Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 t UCAxSTAT USCI_Ax UCBxSTAT USCI_Bx UCLISTEN Bit7 UCFE Bit 6 UCOE Bit 5 Unused Bits 4 1 UCBUSY Bit 0 rw ot rot Listen enable The UCLISTEN bit selects loopback mode 0 Disabled 1 Enabled The transmitter output is internally fed back to the receiver Framing error flag This bit indicates a bus conflict in 4 wire master mode UCFE is not used in 3 wire master or any slave mode 0 No error 1 Bus conflict occurred Overrun error flag This bit is set when a character is transferred into UCxRXBUF before the previous character was read UCOE is cleared automatically when UCxRXBUF is read and must not be cleared by software Otherwise it will not function correctly 0 No error 1 Overrun error occurred Unused in synchronous mode UCSYNC 1 USCI busy This bit indicates if a transmit or receive operation is in progress 0 USCI inactive 1 USCI transmitting or receiving Universal Serial Communication Interface
6. in 4 pin mode when the UCxSTE is in the slave active state The SPI receives data when a transmission is active Receive and transmit operations operate concurrently 20 10 Universal Serial Communication Interface SPI Mode USCI Operation SPI Mode 20 3 6 Serial Clock Control UCxCLK is provided by the master on the SPI bus When UCMST 1 the bit clock is provided by the USCI bit clock generator on the UCxCLK pin The clock used to generate the bit clock is selected with the UCSSELx bits When UCMST 0 the USCI clock is provided on the UCxCLK pin by the master the bit clock generator is not used and the UCSSELx bits are don t care The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer The 16 bit value of UCBRx in the bit rate control registers UCxxBR1 and UCxxBRO is the division factor of the USCI clock source BRCLK The maximum bit clock that can be generated in master mode is BRCLK Modulation is not used in SPI mode and UCAxMCTL should be cleared when using SPI mode for USCI_A The UCAxCLK UCBxCLK frequency is given by i _ BRCLK BitClock UCBRx Serial Clock Polarity and Phase The polarity and phase of UCxCLK are independently configured via the UCCKPL and UCCKPH control bits of the USCI Timing for each case is shown in Figure 20 4 Figure 20 4 USCI SPI Timing with UCMSB 1 UC UC CKPH CKPL Cycle 3 140 2 Rea ee Gs 7 8 0 0 UCxXCLK 0 1 UCXCLK 1
7. 0 UCKCLK 1 1 UCxCLK i Move to UCxTXBUF TX Data Shifted Out j j j j j j j j RX Sample Points Universal Serial Communication Interface SPI Mode 20 11 USCI Operation SPI Mode 20 3 7 Using the SPI Mode with Low Power Modes The USCI module provides automatic clock activation for SMCLK for use with low power modes When SMCLK is the USCI clock source and is inactive because the device is in a low power mode the USCI module automatically activates it when needed regardless of the control bit settings for the clock source The clock remains active until the USCI module returns to its idle condition After the USCI module returns to the idle condition control of the clock source reverts to the settings of its control bits Automatic clock activation is not provided for ACLK When the USCI module activates an inactive clock source the clock source becomes active for the whole device and any peripheral configured to use the clock source may be affected For example a timer using SMCLK will increment while the USCI module forces SMCLK active In SPI slave mode no internal clock source is required because the clock is provided by the external master It is possible to operate the USCI in SPI slave mode while the device is in LPM4 and all clock sources are disabled The receive or transmit interrupt can wake up the CPU from any low power mode 20 3 8 SPI Interrupts The USCI has one interrupt vector for transmission and
8. O_RX_USCIBO_ RX ISR BIT B UCAORXIFG amp IFG2 USCI_AO Receive Interrupt JNZ USCIAO_RX_ISR USCIBO_RX_ISR Read UCBORXBUF clears UCBORXIFG RETI USCIAO_RX_ISR Read UCAORXBUF clears UCAORXIFG RETI The following software example shows an extract of an interrupt service routine to handle data transmit interrupts from USCI_AO in either UART or SPI mode and USCI_BO in SPI mode USCIA0_TX USCIBO_TX_ISR BIT B UCAOTXIFG amp IFG2 USCI_AO Transmit Interrupt JNZ USCIAO TX ISR USCIBO_TX ISR Write UCBOTXBUF clears UCBOTXIFG RETI USCIAO_TX_ISR Write UCAOTXBUF clears UCAOTXIFG RETI Universal Serial Communication Interface SPI Mode 20 13 USCI Registers SPI Mode 20 4 USCI Registers SPI Mode The USCI registers applicable in SPI mode for USCI_AO and USCI_BO are listed in Table 20 2 Registers applicable in SPI mode for USCI_A1 and USCI_B1 are listed in Table 20 3 Table 20 2 USCI_A0O and USCI_BO Control and Status Registers Register Short Form Register Type Address Initial State USCI_AO control register 0 UCAOCTLO Read write 060h Reset with PUC USCI_AO control register 1 UCAOCTL1 Read write 061h 001h with PUC USCI_AO Baud rate control register 0 UCAOBRO Read write 062h Reset with PUC USCI_AO Baud rate control register 1 UCAOBR1 Read write 063h Reset with PUC USCI_AO modulation control register UCAOMCTL Read write 064h Reset with PUC USCI_AO status register UCAOSTAT Read write 065h Reset with PUC USCI_AO Receive
9. Reset with PUC USCI_A1 modulation control register UCA1MCTL Read write 0D4h Reset with PUC USCI_A1 status register UCA1STAT Read write OD5h Reset with PUC USCI_A1 Receive buffer register UCA1RXBUF Read OD6h Reset with PUC USCI_A1 Transmit buffer register UCA1TXBUF Read write OD7h Reset with PUC USCI_B1 control register 0 UCB1CTLO Read write OD8h 001h with PUC USCI_B1 control register 1 UCB1CTL1 Read write OD9h 001h with PUC USCI_B1 Bit rate control register 0 UCB1BRO Read write ODAh Reset with PUC USCI_B1 Bit rate control register 1 UCB1BR1 Read write ODBh Reset with PUC USCI_B1 status register UCB1STAT Read write ODDh Reset with PUC USCI_B1 Receive buffer register UCB1RXBUF Read ODEh Reset with PUC USCI_B1 Transmit buffer register UCB1TXBUF Read write ODFh Reset with PUC USCI_A1 B1 interrupt enable register UC1IE Read write 006h Reset with PUC USCI_A1 B1 interrupt flag register UC1IFG Read write 007h 00Ah with PUC Universal Serial Communication Interface SPI Mode 20 15 USCI Registers SPI Mode UCAxCTLO USCI_Ax Control Register 0 UCBxCTLO USCI_Bx Control Register 0 1 0 7 6 5 4 3 2 UCCKPH UCCKPL UCMSB UC7BIT UCMST UCMODEx UCSYNC 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 UCCKPH Bit 7 Clock phase select 0 Data is changed on the first UCLK edge and captured on the following edge 1 Data is captured on the first UCLK edge and changed on the following edge UCCKPL Bit 6 Clock polarity select 0 The inactive state is low 1 The ina
10. SCI_A1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled Universal Serial Communication Interface SPI Mode 20 23 USCI Registers SPI Mode UC1IFG USCI_A1 USCI_B1 Interrupt Flag Register 7 6 5 4 3 2 1 0 UCB1 UCB1 UCA1 UCA1 TXIFG RXIFG TXIFG RXIFG rw 1 rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 Unused UCB1 TXIFG UCB1 RXIFG UCA1 TXIFG UCA1 RXIFG 20 24 Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 Unused USCI_B1 transmit interrupt flag UCB1TXIFG is set when UCB1TXBUF is empty 0 No interrupt pending 1 Interrupt pending USCI_B1 receive interrupt flag UCB1RXIFG is set when UCB1RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending USCI_A1 transmit interrupt flag UCA1TXIFG is set when UCA1TXBUF empty 0 No interrupt pending 1 Interrupt pending USCI_A1 receive interrupt flag UCA1RXIFG is set when UCA1RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending Universal Serial Communication Interface SPI Mode
11. buffer register UCAORXBUF Read 066h Reset with PUC USCI_AO Transmit buffer register UCAOTXBUF Read write 067h Reset with PUC USCI_BO control register 0 UCBOCTLO Read write 068h 001h with PUC USCI_BO control register 1 UCBOCTL1 Read write 069h 001h with PUC USCI_BO Bit rate control register 0 UCBOBRO Read write O6Ah Reset with PUC USCI_BO Bit rate control register 1 UCBOBR1 Read write O6Bh Reset with PUC USCI_BO status register UCBOSTAT Read write O06Dh Reset with PUC USCI_BO Receive buffer register UCBORXBUF Read O6Eh Reset with PUC USCI_BO Transmit buffer register UCBOTXBUF Read write O6Fh Reset with PUC SFR interrupt enable register 2 IE2 Read write 00ih Reset with PUC SFR interrupt flag register 2 IFG2 Read write 003h 00Ah with PUC a Oe a aay Note Modifying SFR bits To avoid modifying control bits of other modules it is recommended to set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B Or CLR B instructions eee eee 20 14 Universal Serial Communication Interface SPI Mode USCI Registers SPI Mode Table 20 3 USCI_A1 and USCI_B1 Control and Status Registers Register Short Form Register Type Address Initial State USCI_A1 control register 0 UCA1CTLO Read write ODOh Reset with PUC USCI_A1 control register 1 UCA1CTL1 Read write OD1h 001h with PUC USCI_A1 Baud rate control register O UCA1BRO Read write OD2h Reset with PUC USCI_A1 Baud rate control register 1 UCA1BR1 Read write OD3h
12. ctive state is high UCMSB Bit 5 MSB first select Controls the direction of the receive and transmit shift register 0 LSB first 1 MSB first UC7BIT Bit 4 Character length Selects 7 bit or 8 bit character length 0 8 bit data 1 7 bit data UCMST Bit 3 Master mode select 0 Slave mode 1 Master mode UCMODEx Bits USCI Mode The UCMODEx bits select the synchronous mode when 2 1 UCSYNC 1 00 3 Pin SPI 01 4 Pin SPI with UCXSTE active high slave enabled when UCXSTE 1 10 4 Pin SPI with UCXSTE active low slave enabled when UCxSTE 0 11 12C Mode UCSYNC Bit 0 Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode 20 16 Universal Serial Communication Interface SPI Mode USCI Registers SPI Mode UCAxCTL1 USCI_Ax Control Register 1 UCBxCTL1 USCI_Bx Control Register 1 7 6 5 4 3 2 1 0 ot rw 0 rw 0 pe rw 0 rw 0 rw 0 rw 0 rw 1 T UCAxCTL1 USCI_Ax UCBxCTL1 USCI_Bx UCSSELx Bits USCI clock source select These bits select the BRCLK source clock in 7 6 master mode UCxCLK is always used in slave mode 00 NA 01 ACLK 10 SMCLK 11 SMCLK Unused Bits Unused in synchronous mode UCSYNC 1 5 1 UCSWRST_ Bit 0 Software reset enable 0 Disabled USCI reset released for operation 1 Enabled USCI logic held in reset state Universal Serial Communication Interface SPI Mode 20 17 USCI Registers SPI Mode UCAxBRO USCI_Ax Bit Rate Control Register 0 UCBxBRO USCI_Bx Bit Rate Control Register 0 7 6 5 4 3 2 1 0 UCBR
13. fer UCxTXBUF poste ransmit Buffer X Transmit Enable lt 9 Control Set UCFE Transmit State Machine 20 4 Universal Serial Communication Interface SPI Mode K Set UCxTXIFG 20 3 USCI Operation SPI Mode USCI Operation SPI Mode In SPI mode serial data is transmitted and received by multiple devices using a shared clock provided by the master An additional pin UCxSTE is provided to enable a device to receive and transmit data and is controlled by the master Three or four signals are used for SPI data exchange L UCxSIMO LJ UCxSOMI LJ UCxCLK L UCxSTE Table 20 1 UCxSTE Operation UCMODEx 01 10 low Slave in master out Master mode UCxSIMO is the data output line Slave mode UCxSIMO is the data input line Slave out master in Master mode UCxSOM is the data input line Slave mode UCxSOMI is the data output line USCI SPI clock Master mode UCxCLK is an output Slave mode UCxCLK is an input Slave transmit enable Used in 4 pin mode to allow multiple masters on a single bus Not used in 3 pin mode Table 20 1 describes the UCxSTE operation UCxSTE Active State UCxSTE Slave Master l 0 inactive active high 1 active inactive 0 active inactive 1 inactive active Universal Serial Communication Interface SPI Mode 20 5 USCI Operation SPI Mode 20 3 1 USCI Initialization and Reset The USCI is reset by a PUC or by the UCSWRST bit After a PUC the UCSWRST bit is automatically set
14. ng that data has been received The overrun error bit UCOE is set when the previously received data is not read from UCxRXBUF before new data is moved to UCxRXBUF Four Pin SPI Slave Mode In 4 pin slave mode UCXSTE is used by the slave to enable the transmit and receive operations and is provided by the SPI master When UCxSTE is in the slave active state the slave operates normally When UCXSTE is in the slave inactive state _j Any receive operation in progress on UCxSIMO is halted 1 UCxSOM1 is set to the input direction J The shift operation is halted until the UCxSTE line transitions into the slave transmit active state The UCxSTE input signal is not used in 3 pin slave mode Universal Serial Communication Interface SPI Mode 20 9 USCI Operation SPI Mode 20 3 5 SPI Enable Transmit Enable Receive Enable When the USCI module is enabled by clearing the UCSWRST bit it is ready to receive and transmit In master mode the bit clock generator is ready but is not clocked nor producing any clocks In slave mode the bit clock generator is disabled and the clock is provided by the master A transmit or receive operation is indicated by UCBUSY 1 A PUC or set UCSWRST bit disables the USCI immediately and any active transfer is terminated In master mode writing to UCxTXBUF activates the bit clock generator and the data will begin to transmit In slave mode transmission begins when a master provides a clock and
15. o be handled by the user _j The internal state machines are reset and the shift operation is aborted If data is written into UCxTXBUF while the master is held inactive by UCxSTE it will be transmit as soon as UCXSTE transitions to the master active state If an active transfer is aborted by UCXSTE transitioning to the master inactive state the data must be re written into UCxTXBUF to be transferred when UCXSTE transitions back to the master active state The UCxSTE input signal is not used in 3 pin master mode 20 8 Universal Serial Communication Interface SPI Mode 20 3 4 Slave Mode USCI Operation SPI Mode Figure 20 3 USCI Slave and External Master MASTER COMMON SPI SPI Receive Buffer Receive Buffer UCxRXBUF Data Shift Register DSR Receive Shift Register UCxCLK MSP430 USC Figure 20 3 shows the USCI as a slave in both 3 pin and 4 pin configurations UCxCLK is used as the input for the SPI clock and must be supplied by the external master The data transfer rate is determined by this clock and not by the internal bit clock generator Data written to UCxTXBUF and moved to the TX shift register before the start of UCxCLK is transmitted on UCxSOMI Data on UCxSIMO is shifted into the receive shift register on the opposite edge of UCxCLK and moved to UCxRXBUF when the set number of bits are received When data is moved from the RX shift register to UCxRXBUF the UCxRXIFG interrupt flag is set indicati
16. ode 20 2 USCI Introduction SPI Mode In synchronous mode the USCI connects the MSP430 to an external system via three or four pins UCxSIMO UCxSOMI UCxCLK and UCXSTE SPI mode is selected when the UCSYNC bit is set and SPI mode 8 pin or 4 pin is selected with the UCMODEx bits SPI mode features include 7 or 8 bit data length LSB first or MSB first data transmit and receive 3 pin and 4 pin SPI operation Master or slave modes Independent transmit and receive shift registers Continuous transmit and receive operation Selectable clock polarity and phase control Programmable clock frequency in master mode Independent interrupt capability for receive and transmit E E E E E 1 Separate transmit and receive buffer registers E L J L J L J E Slave operation in LPM4 Figure 20 1 shows the USCI when configured for SPI mode Universal Serial Communication Interface SPI Mode 20 3 USCI Introduction SPI Mode Figure 20 1 USCI Block Diagram SPI Mode Receive State Machine K Set UCOE UCLISTEN UCMST Receive Buffer UCx RXBUF UCxSOMI Receive Shift Register K Set UCXRXIFG UCMSB_ UC7BIT R UCSSELx Bit Clock Generator UCxBRx UCCKPH UCCKPL N A Y UCxCLK ACLK ere gt Prescaler Divider Clock Direction lt gt SMCLK Phase and Polarity SMCLK UCMSB_ UC7BIT r UCxSIMO L Transmit Shift Register L gt lt gt UCMODEx T it Buf
17. one interrupt vector for reception SPI Transmit Interrupt Operation The UCxTXIFG interrupt flag is set by the transmitter to indicate that UCxTXBUF is ready to accept another character An interrupt request is generated if UCxTXIE and GIE are also set UCxTXIFG is automatically reset if a character is written to UCxXTXBUF UCxTXIFG is set after a PUC or when UCSWRST 1 UCXTXIE is reset after a PUC or when UCSWRST 1 Note Writing to UCxTXBUF in SPI Mode Data written to UCxTXBUF when UCxTXIFG 0 may result in erroneous data transmission ss SPI Receive Interrupt Operation 20 12 The UCxRXIFG interrupt flag is set each time a character is received and loaded into UCxRXBUF An interrupt request is generated if UCxRXIE and GIE are also set UCxRXIFG and UCXRXIE are reset by a system reset PUC signal or when UCSWRST 1 UCXRXIFG is automatically reset when UCXRXBUF is read Universal Serial Communication Interface SPI Mode USCI Operation SPI Mode USCI Interrupt Usage USCI_Ax and USCI_Bx share the same interrupt vectors The receive interrupt flags UCAxRXIFG and UCBxRXIFG are routed to one interrupt vector the transmit interrupt flags UCAxTXIFG and UCBxTXIFG share another interrupt vector Shared Interrupt Vectors Software Example The following software example shows an extract of an interrupt service routine to handle data receive interrupts from USCI_AO in either UART or SPI mode and USCI_BO in SPI mode USCIA
18. upt enabled Universal Serial Communication Interface SPI Mode 20 21 USCI Registers SPI Mode IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UCBO UCBO UCAO UCAO TXIFG RXIFG TXIFG RXIFG rw 1 rw 0 rw 1 rw 0 UCBO TXIFG UCBO RXIFG UCAO TXIFG UCAO RXIFG 20 22 Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 These bits may be used by other modules See device specific data sheet USCI_BO transmit interrupt flag UCBOTXIFG is set when UCBOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USCI_BO receive interrupt flag UCBORXIFG is set when UCBORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending USCI_AO transmit interrupt flag UCAOTXIFG is set when UCAOTXBUF empty 0 No interrupt pending 1 Interrupt pending USCI_AO receive interrupt flag UCAORXIFG is set when UCAORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending Universal Serial Communication Interface SPI Mode USCI Registers SPI Mode UC1IE USCI_A1 USCI_B1 Interrupt Enable Register 7 rw 0 Unused UCB1iTXIE UCB1RXIE UCA1TXIE UCA1RXIE rw Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 me me UCB1TXIE UCB1RXIE UCA1TXIE UCA1RXIE 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused USCI_B1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_B1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled U
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