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Video and Image Processing Suite User Guide

1. ee Memory Combinational Logic fmax LUTALUTS Registers quur Bits MLAB Bits MHz Stratix 2 292 458 10 6 43 008 40 226 Notes to Table 1 15 1 EP3C10F256C6 devices 2 EP3SE50F780C2 devices Clocked Video Output Table 1 16 shows the performance figures for the Clocked Video Output Table 1 16 Clocked Video Output Performance Memory Combinational Logic fmax Device Family LUTS ALUTS Registers ALUTs M9K Bits MLAB Bits MHz Converts Avalon ST Video to DVI 1080p60 clocked video Cyclone III 7 261 221 7 51 200 191 Stratix 2 174 221 7 51 200 287 Converts Avalon ST Video to PAL clocked video Cyclone III 7 279 207 3 22 528 212 Stratix 2 213 207 3 22 528 317 Converts Avalon ST Video to SDI 1080i60 clocked video Cyclone III 1 294 216 6 43 008 199 Stratix 2 230 216 6 43 008 301 Converts Avalon ST Video to SDI 1080p60 clocked video Cyclone III 7 295 216 6 43 008 200 Stratix 2 229 216 6 43 008 271 Notes to Table 1 16 1 EP3C10F256C6 devices 2 EP3SE50F780C2 devices Color Plane Sequencer Table 1 17 shows the performance figures for the Color Plane Sequencer Table 1 17 Color Plane Sequencer Performance Part 1 of 2 Device Family C mbinational Logic Memory DSP Blocks fmi Rearranging a channels
2. Signal Direction Description m In The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is asserted reset In high The reset must be de asserted synchronously with respect to the rising edge of the clock signal In alpha in N port Avalon ST data bus for layer W Pixel data is CERE transferred into the MegaCore function over this bus 1 alpha in N port Avalon ST endofpacket signal This signal marks the elie dn A endotpackee i end of an Avalon ST packet 1 f alpha_in_N port Avalon ST alpha ready signal This signal indicates alpha in N ready Out when the MegaCore function is ready to receive data 7 alpha in N port Avalon ST startofpacket signal This signal marks alpha_in N startofpacket ul the start of an Avalon ST packet 7 sioka dade pie alpha in N port Avalon ST alpha valid signal This signal identifies the cycles when the port should input data 7 control Slave port Avalon MM address bus Specifies a word offset a into the slave address space Tere en In control Slave port Avalon MM chipselect signal The control port ignores all other signals unless this signal is asserted p Out control slave port Avalon MM readdata bus These output lines are used for read transfers in control slave
3. V Sync Data A D ES ES EF C3 CS X X X X X Sample Line 524 SOF SOFSubSample 0 SOFSample 0 SOFLine 0 SOF SOFSubSample 1 SOFSample 1 SOFLine 1 Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 41 Clocked Video Input The SOF signal can be set to any position within the incoming video frame The registers used to configure the SOF signal are measured from the rising edge of the FO vertical sync Due to registering inside the Clocked Video Input MegaCore function setting the SOF Sample and SOF Line registers to 0 results in a SOF signal rising edge six cycles after the rising edge of the vsync in embedded synchronization mode and three cycles after the rising edge of the vsync in separate synchronization mode A start of frame is indicated by a rising edge on the SOF signal 0 to 1 An example of how to set up the Clocked Video Input to output an SOF signal aligned to the incoming video synchronization in embedded synchronization mode is included in Table 5 18 Table 5 18 Example of Clocked Video Input To Output an SOF Signal Format SOF Sample Register SOF Line Register Refclk Divider Register 720p60 1644 lt lt 2 749 1649 1080160 2194 2 1124 2199 NTSC 856 lt l
4. Alpha Blending Mixer SCA OR a PRR HERE oaks en ed ach Clipper e tea ped eee textes Deinterlacet eerte ree ER em Re Inter acet Frame Buffer 2 eee Clocked Video Input Clocked Video Output Color Plane Sequencer Test Pattern Generator iid E T TP Chapter 2 Getting Started with Altera IP Cores Installation and Licensing Evaluating an IP Core OpenCore Plus Time Out Behavior July 2010 Altera Corporation Video and Image Processing Suite User Guide iv Contents Design PloWS secet Reto diea he er ere EHE pg diede 2 2 SOPC Builder Design Flow 4 2 kc 9e hee hee rhe b Ee a Ee re ae Era 2 4 Specify Parameters ith CREER Ged ey bd ESR eA bed ws Meus 2 4 Complete the SOPC Builder System sis in E nee een 2 5 Simulat the System sss esse deste wrai bigest PE RE M RE DUO eR 2 5 MegaWizard Plug In Manager Design Flow 00 0 6c e 2 6 Specify Parameters i esses dean ri UP uev pa orga DR Vallae Vea e Cate Vl e ce a 2 6 Simulate the Desigh ecco es Re EEC Ore a hPa EN ee ror 2 7 Compile and Program ces ene ert ie see ER eee ek g e a ai bp etes tea gie ood 2 8 Generated Files uas Hew
5. Video Locked Signal The vid locked signal indicates that the clocked video stream is active When the signal has a value of 1 the Clocked Video Input MegaCore function takes the input clocked video signals as valid and reads and processes them as normal When the signal has a value of 0 if for example the video cable is disconnected or the video interface is not receiving a signal the Clocked Video Input MegaCore function takes the input clocked video signals as invalid and does not process them If the vid locked signal goes invalid while frame of video is being processed the Clocked Video Input MegaCore function ends the frame of video early July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 38 Chapter 5 Functional Descriptions Clocked Video Input Control Port If you turn on Use control port in the MegaWizard interface for the Clocked Video Input its Avalon ST Video output can be controlled using the Avalon MM slave control port Initially the MegaCore function is disabled and does not output any data However it still detects the format of the clocked video input and raises interrupts The sequence for starting the output of the MegaCore function is as follows 1 Write 1 to Control register bit 0 2 Read Status register bit 0 When this is a 1 the MegaCore function outputs data This occurs on the next start of frame or field that matches the setting of the Fiel
6. Parameter Value Description Image width 32 2600 Default 640 Choose the required image width in pixels Image height 32 2600 Default 480 Choose the required image height in pixels E m per 4 20 Default 8 Choose the number of bits per pixel per color plane Number of color 1 3 The number of color planes that are sent in sequence over one data planes in sequence connection For example a value of 3 for R G B R G B R G B Filter size 3x3 5x5 Choose the size of kernel in pixels to take the median from Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 3 Parameter Settings Alpha Blending Mixer Alpha Blending Mixer Table 3 8 shows the Alpha Blending Mixer MegaCore function parameters 3 7 Table 3 8 Alpha Blending Mixer Parameter Settings Parameter Maximum layer width Value 32 2600 Default 1 024 Description Choose the maximum image width for the layer background in pixels No layer width can be greater than the background layer width The maximum image width is the default width for all layers at start up Maximum layer height 32 2600 Default 768 Choose the maximum image height for the layer background in pixels No layer height can be greater than the background layer height The maximum image height is the default height for all layers at start up Bits per pixel per color plane 4 20 Default 8 Choose the number of bit
7. Active picture line o FO active picture g E V front Ri porch 5 Ancillary line 4 Vsync 8 V back 2 porch gt front H back porch sync porch Active samples gt H blanking July 2010 Altera Corporation Video and Image Processing Suite User Guide Chapter 5 Functional Descriptions Clocked Video Output Table 5 21 shows how Figure 5 17 relates to the register map Table 5 21 Progressive Frame Parameter Descriptions Register Name ModeN Control Parameter N A Description The zeroth bit of this register is the Interlaced bit m Set to 0 for progressive Bit 1 of this register is the sequential output control bit only if the Allow output of color planes in sequence compile time parameter is enabled m Setting bit 1 to 1 enables sequential output from the Clocked Video Output such as for NTSC Setting bit 1 to a 0 enables parallel output from the Clocked Video Output such as for 1080p ModeN Sample Count Active samples The width of the active picture region in samples pixels ModeN FO Line Count Active lines The height of the active picture region in lines ModeN Horizontal Front Porch H front porch Separate synchronization mode only The front porch of the horizontal synchronization the low period before the synchronization starts ModeN Horizontal Sync Separate synchroniz
8. Signal Direction Description ast Out Clocked video data bus Video data is transferred into the MegaCore function over arc dd this bus Separate Synchronization mode Only Clocked video data valid signal This signal vid datavalid is asserted when an active picture sample of video data is present on vid data Separate Synchronization Mode Only Clocked video field signal For interlaced vid f Out input this signal distinguishes between field 0 and field 1 For progressive video this signal is unused id h Out Separate Synchronization Mode Only Clocked video horizontal blanking signal s This signal is asserted during the horizontal blanking period of the video stream Separate Synchronization Mode Only Clocked video horizontal synchronization vid h sync Out signal This signal is asserted during the horizontal synchronization period of the video stream Embedded Synchronization Mode Only Clocked video line number signal Used vid ln Out with the SDI MegaCore function to indicate the current line number when the vid trs signal is asserted PETS Out Clocked video mode change signal This signal is asserted on the cycle before a MAURUS mode change occurs Start of frame signal A rising edge 0 to 1 indicates the start of the video frame as vid sof Out d configured by the SOF registers id oor locked Out of frame locked signal When high the via signal is valid and can be MID Out Video
9. The Avalon Interface Specifications defines signal types of which many are optional Table 4 7 lists the signals for transmitting Avalon ST Video Table 4 7 does not show unused signals Table 4 7 Avalon ST Interface Signal Types Signal Width Direction ready 1 Sink to Source valid 1 Source to Sink data bits per symbol symbols per beat Source to Sink startofpacket 1 Source to Sink endofpacket 1 Source to Sink Packet Transfer Examples All packets are transferred using the Avalon ST signals in the same way Three examples are given here two showing video data packets and one showing a control data packet Each is an example of generic packet transmission Example 1 Data Transferred in Parallel This example shows the transfer of a video data packet in to and then out of a generic MegaCore function that supports the Avalon ST Video protocol Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 4 Interfaces 4 13 Avalon ST Video Protocol In this case both the input and output video data packets have a parallel color pattern and eight bits per pixel per color plane as shown in Table 4 8 Table 4 8 Parameters for Example of Data Transferred in Parallel Parameter Value Bits per Pixel per Color Plane 8 R Color Pattern Figure 4 12 shows how the first few pixels of a frame are processed Figure 4 12 Timing Diagram Showing R G B T
10. e Pali debate caen eade Fu doi ied nice FH eie 5 67 2D Median a cetus css Dots em lcu E LM M UM LA EE CO 5 67 Error Recovery 2a bre etia e dtes etc ba o I uela oe E Pate d e 5 68 Alpha Blending Mixer eee UR ERU PEE RR Iain e sale enable e ee godes 5 68 Error Recovery d ie E e eed ande de dei dee eee dedere eee oed 5 68 SCalebo eodein we th MEM a 5 69 Error Recovery deed eei dde Do ep Vac be de Pd usce ens 5 70 si cae mr eec n pex EE EEE E A EU 5 70 Error RecOVeEy sona bug he Ease oe athe kegs 5 70 Deinterlacet G 5 70 Video and Image Processing Suite User Guide July 2010 Altera Corporation Contents vii Error 052 200 nay ts ecce Eee P po o Qu d A doe Eoo et 5 71 Interlacet AAE EAEE Aw ae Ead Rad ERS 5 71 Error skr REIS rege hex eec Ete DER du atate ode tte eter 5 71 Frame Reade 4i iade beer PASAT OAR DOR HAD EAR HEAD DRO dac pP d E Ra 5 71 Frame Butter 2 5263 coms tbv EE dae dle bile a toe btn toe Race bine k pe AR Are 5 71 Erron v osea bcp ade cibos hte dosis dentes aut ties aa acess aeree atte 5 72 Color Plane Sequencer al ae EE gau Palate Weegee eee dte 5 72 RECOVERY lea tae ie dria tet qucd ea ed
11. tette Ede eren tede dee e Pt i eee detecte 5 8 Result to Output Data Type Conversion 2 0c n 5 8 2D Median Filter erred aee Ee eee pee p edd ee e ee cd e a ue e dca 5 9 Alpha Blendimne MIX E e RS tte s tiet edited wate etc atte petet ete others tr essi a 5 10 Alpha Blending x i tic DERI Ree tg giebt pide Ad eed eiie ob Edere ted 5 11 si PET 5 13 Nearest Neighbor Algorithm 00 5 13 Bilinear Algorithim ees eere en eie e Rete b ERREUR enge etti acia distet te i eds 5 13 Resource Usage iue een GERE acct en he ee e Pete e de eode rele ie eee 5 14 Algorithmic Description RE ERE HER Ra E Een 5 14 Polyphase and Bicubic Algorithms ssssssssss ee 5 14 Resource Usage denne 5 16 Algorithmic Description eens 5 17 Choosing and Loading Coefficients 6 6 cece eee eens 5 17 Recommended Parameters nnn eens 5 19 CIppet ttp date eique esce ted 5 20 Deinterlacer iade duet eec d ate ire ed bee i erede e tee i des tenen 5 21 Dbeinterlacing Methods nece Ceteri Rene tee enden eh ye eerie eed ee rater mas 5 22 Bob with Scanline Duplication 0 2 06 enne 5 22 Bob with Scanline Interpolation ene 5 22 hl em 5 23 MotionsAdaptive sergisi ee e d etos lecce qui er Nia te ts eie es 5 23 Pass Through Mo
12. ERES SPACE IRE RR CE e ne t pe Ea eee bb dee ad 7 11 Test Pattern Generator ERR exe Pedo avd us pde eres n dus tardis ab Rod oles 7 13 Control Synchronizer Le Le e Lea De EIER EE eet e EHI deleto dete uon ed 7 14 July 2010 Altera Corporation Video and Image Processing Suite User Guide viii Contents Switch ste tret ea ed estes b geli io tte deg b 7 15 Additional Information Document Revision History esee mem ehem ee eH puc eer ade ke Hc hoa e Receta hn Info 1 How to Contact Altera S REEL ER ER NER Ea PHOS I plecti Pepe dere pedes Info 1 Typographic Conventions essem et dene ess s e aee eee e eR e nah ee res Info 2 Referenced Documents Horie ete epe Pee Lid e ree E rale a dat dia eee a e ades Info 2 Video and Image Processing Suite User Guide July 2010 Altera Corporation N DTE RYN 1 About This MegaCore Function Suite This document describes the Altera Video and Image Processing Suite collection of IP cores that ease the development of video and image processing designs You can use the following IP cores in a wide variety of image processing and display applications The Video and Image Processing Suite contains the following MegaCore functions Color Space Converter CSC Chroma Resampler Gamma Corrector 2D FIR Filter 2D Median Filter Alpha Blending Mixer Sc
13. Parameter Value Frame Width Read from control packets at run time Frame Height Read from control packets at run time Interlaced Either Progressive July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 8 Chapter 5 Functional Descriptions 2D FIR Filter Table 5 3 Gamma Corrector Avalon ST Video Protocol Parameters Part 2 of 2 Parameter Bits per Color Sample Value Number of bits per color sample selected in the MegaWizard interface Color Pattern One two or three channels in sequence or parallel For example if three channels in sequence is selected where and y can be any color plane 2D FIR Filter The 2D FIR Filter performs 2D convolution using matrices of 3x3 5x5 and 7x7 coefficients The MegaCore function retains full precision throughout the calculation while making efficient use of FPGA resources With suitable coefficients the MegaCore function can perform several operations including but not limited to sharpening smoothing and edge detection An output pixel is calculated from the multiplication of input pixels in a filter size grid kernel by their corresponding coefficient in the filter These values are summed together Prior to output this result is scaled has its fractional bits removed is converted to the desired output data type and is constrained to a specified range The position of the output pixel corresp
14. lt lt lt 6 GB G Q GF hoped N Single Cycle Color valon Memory Map A A A A Read Master Port um cie GNE DN d Y 12 11 8 5 2 gt 8Bits EE LLL LL 2 Avalon Frame Reader Streaming Output MegaCore 13 10 7 4 1 f 8 Bits A _ 3 14 9 6 3 0 gt 8 Bits The Avalon Slave control port allows the specification of up to two memory locations each containing a video frame Switching between these memory locations is performed with a single register This allows the Frame Reader MegaCore function to read a series of frames from different memory addresses without having to set multiple registers within the period of a single frame This feature is useful when reading very small frames and helps to simplify control timing To aid the timing of control instructions and to monitor the core the Frame Reader MegaCore function also has an interrupt that fires once per video data packet output which is the frame completed interrupt The Avalon ST Video parameters for the Frame Reader MegaCore function are shown in Table 5 12 Table 5 12 Avalon ST Video Parameters Part 1 of 2 Parameter Value Frame Width Slave control port Maximum value Frame Height Ser MEIN IEEE Slave control port Maximum value Interlaced Progressive m nd Memory Mapped Slave control port all values July 2010 Altera Corporation Video and Ima
15. m Writing a 0 to the Go register waiting for the Status register to read 0 and then writing a 1 to the Go register m Writingalto the Output Switch register performs the same sequence but without the need for user intervention This is the recommended way to load a new configuration Mixer Layer Switching You can use the Switch MegaCore function in conjunction with the Alpha Blending Mixer MegaCore function and Control Synchronizer MegaCore function to perform run time configurable layer switching in the Alpha Blending Mixer Layer switching is the ability to change the layer that a video stream is on moving it in front of or behind the other video streams being mixed Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 65 Switch Figure 5 29 shows the system configuration used to achieve this Figure 5 29 Example of a layer Switching System Video Stream 1 Video Stream 2 Background Layer Switch MegaCore Alpha Control Function Layer 1 Blending Synchronizer Mixer MegaCore MegaCore Function Function Avalon MM n Master Avalon MM Slave Control The Control Synchronizer MegaCore function ensures that the switch of the video streams is performed at a safe place in the streams Performing the switch when the Alpha Blending Mixer MegaCore function is outputting the start of an image packet ens
16. 3 11 Table 3 13 shows the Deinterlacer MegaCore function parameters Table 3 13 Deinterlacer Parameter Settings Part 1 of 3 Parameter Maximum image width Value 32 2600 Default 640 Description Choose the maximum frame width in pixels The maximum frame width is the default width at start up Maximum image height 7 32 2600 Default 480 Choose the maximum progressive frame height in pixels The maximum frame height is the default progressive height at start up Bits per pixel per color plane 4 20 Default 8 Choose the number of bits per pixel per color plane Number of color planes Choose the number of color planes that are sent in sequence over 1 3 one data connection For example a value of 3 for R G B R G B in sequence mipi R G B Number of color planes 1 3 Choose the number of color planes in parallel in parallel Default initial field FO F1 Choose a default type for the initial field The default value is not used if the first field is preceded by an Avalon ST Control packet Deinterlacing Method 7 8 Bob Scanline Duplication Bob Scanline Interpolation Weave Motion Adaptive Refer to Deinterlacing Methods on page 5 22 Frame buffering mode 1 3 4 5 No buffering Double buffering Triple buffering with rate conversion Specifies whether external frame buffers are used In no buffering mode data is piped directly from
17. Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 5 Width 320 Light Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 4 Width 640 Control Data Packet and Video Data Packet Pair Numbers 6 to 13 are Stored in the Frame Buffer 4 The Scaler has been reconfigured to output width 320 frames The Control Synchronizer has resumed the video processing pipeline At no point did the Scaling ratio change from 1 1 as shown in Figure Figure 5 28 Figure 5 28 Reconfigured Scaler Avalon MM Master Avalon MM Test Pattern Control Scaler Generator Synchronizer Avalon MM Avalon MM Red Line Indicates Control Data Packet and Video Data Packet Pair Number 14 Width 320 Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 5 Width 320 Control Data Packet and Video Data Packet Pair Numbers 6 to 13 are Stored in the Frame Buffer You can customize the Control Synchronizer according to the parameters shown in Table 5 27 Table 5 27 Control Synchronizer Parameters Part 1 of 2 Parameter Value Frame Width Runtime controlled Any valid value supported Frame Height Runtime controlled Any valid value supported Interlaced Progressive Runtime controlled Any valid value supported July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 64 Switch Chapter 5 Functional Descriptions
18. IT LIT 2 These pixels are assembled into two 3x3 groups of pixels Figure 5 8shows the minimum absolute difference of the two groups Figure 5 8 Pixel Assembly for the Motion Adaptive Algorithm Previous Frame Current Frame Motion MAD 1 3 The minimum absolute difference value is normalized into the same range as the input pixel data If you select the Motion bleed algorithm the function compares the motion value with a recorded motion value for the same location in the previous frame If it is greater the function keeps the new value if the new value is less than the stored value the function uses the motion value that is the mean of the two values This action reduces unpleasant flickering artefacts but increases the memory usage and memory bandwidth requirements Two pixels are selected for interpolation by examining the 3x3 group of pixels from the more recent two fields for edges If the function detects a diagonal edge the function selects two pixels from the current field that lie on the diagonal otherwise the function chooses the pixels directly above and below the output pixel 57 The 4 2 2 compatibility mode prevents incorrect interpolation of the chroma samples along the diagonal edges The function uses a weighted mean of the interpolation pixels to calculate the output pixel and the equivalent to the output pixel in the previous field with the following equation Upper Pixe
19. The class of Lanczos N functions is defined as 1 x 0 LanczosN x numinum x 0A x lt N 0 x gt N As can be seen in the figure phase 0 centers the function over tap 1 on the x axis By the equation above this is the central tap of the filter Further phases move the mid point of the function in 1 P increments towards tap 2 The filtering coefficients applied in a 4 tap scaler for a particular phase are samples of where the function with that phase crosses 0 1 2 3 on the x axis The preset filtering functions are always spread over the number of taps given For example Lanczos 2 is defined over the range 2 to 2 but with 8 taps the coefficients are shifted and spread to cover 0 to 7 Figure 5 5 Lanczos 2 Function at Various Phases 1 2 T phase 0 2 phase P 1 0 2 1 0 Compile time custom coefficients are loaded from a CSV file One CSV file is specified for vertical coefficients and one for horizontal coefficients For N taps and P phases the file must contain N x P values The values must be listed as N taps in order for phase 0 N taps for phase 1 up to the Nth tap of the Pth phase Values do not need to be presented with each phase on a separate line Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 19 Scaler The values must be pre quantized in the range implied by the
20. 2 Read Status register bit 0 When this is a 0 the function has stopped video output This occurs at the end of the next frame or field boundary The starting and stopping of the MegaCore function is synchronized to a frame or field boundary Video Modes The video frame is described using the mode registers that are accessed via the Avalon MM control port If you turn off Use control port in the MegaWizard interface for the Clocked Video Output then the output video format always has the format specified in the MegaWizard interface Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 47 Clocked Video Output The MegaCore function can be configured to support between 1 to 14 different modes and each mode has a bank of registers that describe the output frame When the MegaCore function receives a new control packet on the Avalon ST Video input it searches the mode registers for a mode that is valid and has a field width and height that matches the width and height in the control packet The register Video Mode Match shows the selected mode When found it restarts the video output with those format settings If a matching mode is not found the video output format is unchanged and a restart does not occur Figure 5 17 shows how the register values map to the progressive frame format described in Video Formats on page 5 43 Figure 5 17 Progressive Frame Parameters
21. 2 Interrupt SN m When bit 2 is asserted the locked interrupt has triggered m The interrupts stay asserted until a write of 1 is performed to these bits 3 Used Words The used words level of the output FIFO 4 Video Mode Match One hot register that indicates the video mode that is selected Video Mode 1 Control Bit 0 of this register is the Interlaced bit m Setto 1 for interlaced Set to a 0 for progressive Bit 1 of this register is the sequential output control bit only if the Allow output 5 ModeX Control of color planes in sequence compile time parameter is enabled m Setting bit 1 to 1 enables sequential output from the Clocked Video Output e g for NTSC Setting bit 1 to a 0 enables parallel output from the Clocked Video Output e g for 1080p 6 odel Sample Count Video mode 1 sample count Specifies the active picture width of the field 7 eee ee agn Video mode 1 field 0 progressive line count Specifies the active picture height of the field 8 ini Tate Bak Video mode 1 field 1 line count interlaced video only Specifies the active TOS picture height of the field 9 odel Horizontal Front Video mode 1 horizontal front porch Specifies the length of the horizontal front Porch porch in samples 10 odel Horizontal Sync Video mode 1 horizontal synchronization length Specifies the length of the Length horizontal synchronization length in samples 11 odel Horizontal Video mode 1 horizontal blanking period Specifies the length of th
22. Clocked Video Input Table 3 17 shows the Clocked Video Input MegaCore function parameters Chapter 3 Parameter Settings Clocked Video Input Table 3 17 Clocked Video Input Parameter Settings Parameter Select preset to load Value DVI 1080p60 SDI 1080p60 SDI 1080160 PAL NTSC Description You can choose from a list of preset conversions or use the other fields in the dialog box to set up custom parameter values If you click Load values into controls the dialog box is initialized with values for the selected preset conversion Bits per pixel per color plane 4 20 Default 8 Choose the number of bits per pixel per color plane Number of color planes 1 4 Default 3 Choose the number of color planes Color plane transmission format Sequence Parallel Choose whether the color planes are transmitted in sequence or in parallel Field 0 first Field order Field 1 first E the field to synchronize to first when starting or stopping the Any field first put Progressive Choose the format to be used when no format can be automatically Interlaced or progressive interlaced detected Width 32 65 536 Choose the image width to be used when no format be automatically Default 1 920 detected 32 65 536 Choose the image height to be used when no format can be automatically Height Frame Field 0 Default 1 080 detected Height Field 1
23. H front porch Separate synchronization mode only The front porch of the horizontal synchronization the low period before the synchronization starts ModeN Horizontal Sync Separate synchronization mode only The synchronization length of the Length Bayni horizontal synchronization the high period of the sync a eie H blanking The horizontal blanking period non active picture portion of a line Separate synchronization mode only The front porch of the vertical ond Verti al Front V front porch synchronization the low period before the synchronization starts for field F1 ModeN Vertical Sync Separate synchronization mode only The synchronization length of the Length y vertical synchronization the high period of the sync for field F1 ModeN Vertical Blanking V blanking E vertical blanking period non active picture portion of a frame for field Separate synchronization mode only The front porch of the vertical Hd FO V front porch synchronization the low period before the synchronization starts for field FO ModeN FO Vertical Sync FOV sync Separate synchronization mode only The synchronization length of the Length y vertical synchronization the high period of the sync for field FO ModeN FO Vertical The vertical blanking period non active picture portion of a frame for field FO V blank Blanking FO ModeN Active Picture C The line number that the active picture
24. July 2010 Altera Corporation Video and Image Processing Suite User Guide Info 2 Additional Information Typographic Conventions Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Bold Type with Initial Capital Letters Indicate command names dialog box titles dialog box options and other GUI labels For example Save As dialog box For GUI elements capitalization matches the GUI bold type Indicates directory names project names disk drive names file names file name extensions software utility names and GUI labels For example qdesigns directory d drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example AN 579 Stratix IV Design Guidelines italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets For example file name and project gt file Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections within a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example res
25. color plane There must always be three color planes for this function but you can Color plane Parallel hoose whether the th itted i i configuration Sequence Paralle choose whether the three color planes are transmitted in sequence or in parallel Choose the format sampling rate format for the input frames Note that the Input Format 7 TTA HELM input and output formats must be different X Choose the format sampling rate format for the output frames Note that Pulau nna the input and output formats must be different Horizontal Filtering Filtered Choose the algorithm to use in the horizontal direction when re sampling Algorithm Nearest Neighbor data to or from 4 4 4 Luma adaptive On or Off Turn on to enable luma adaptive mode This mode looks at the luma channel during interpolation and uses this to detect edges Note to Table 3 3 1 The input and output formats must be different A warning is issued when the same values are selected for both Gamma Corrector Table 3 4 shows the Gamma Corrector MegaCore function parameters Table 3 4 Gamma Corrector Parameter Settings Parameter Value Description Bits per pixel per color plane 4 16 Default 8 Choose the number of bits per pixel per color plane Number of 1 3 The number of color planes that are sent in sequence or parallel over one color planes data connection Color plane Specifies whether the specified
26. the Preview coefficients button to view the current coefficients in a preview window Turn on to save coefficient memory by using symmetric Bam On or Off coefficients When on and Load coefficient data at runtime is y also on coefficient writes beyond phases 2 and 1 are ignored Horizontal Coefficient Data 1 6 Default 2 Choose the number of coefficient banks to enable double Memory banks buffering fast coefficient swapping or direct writes Horizontal Coefficient Data Filter function Lanczos 1 12 or Custom Default Lanczos 2 You can choose from 12 pre defined Lanczos functions or use the coefficients saved in a custom coefficients file Horizontal Coefficient Data When a custom function is selected you can browse for a comma separated value file containing custom coefficients Use Custom coefficient file user specified the Preview coefficients button to view the current coefficients in a preview window s Turn on to save coefficient memory by using symmetric Horizontal Dara On or Off coefficients When on and Load coefficient data at runtime is Symmetric also on coefficient writes beyond phases 2 and 1 are ignored You can create custom coefficient data using third party tools such as Microsoft Excel or the MATLAB Array Editor To do so click Preview coefficients under Vertical Coefficient Data and Horizontal Coefficient Data copy the data from the prede
27. 6 The signals associated with the ker writer control portare not present unless run time control for locked frame rate conversion is enabled Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 6 Signals 6 11 Interlacer Interlacer Table 6 8 shows the input and output signals for the Interlacer MegaCore function Table 6 10 Interlacer Signals Signal Direction Description The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is asserted reset In high The reset must be de asserted synchronously with respect to the rising edge of the clock signal control slave port Avalon MM address bus Specifies a word offset into clock In trol In the slave address space 1 control slave port Avalon MM chipselect signal The control port control av chipselect In ignores all other signals unless this signal is asserted 7 control slave port Avalon MM readdata bus These output lines are used control av readdata Out for read transfers 1 control av waitrequest Out cont rol Slave port Avalon MM waitrequest signal 7 control Slave port Avalon MM write signal When this signal is asserted control av Wirte j the control port accepts new data from the writedata bus 1 s T control slave port Avalon MM writedata bus Th
28. Address Register Description Bit 0 of this register is the Go bit all other bits are unused Setting this bit 0 Control to 0 causes the Scaler to stop the next time that control information is read Refer to Avalon MM Slave Interfaces on page 4 17 for full details Bit 0 of this register is the Status bit all other bits are unused The Scaler MegaCore function sets this address to 0 between frames It is set 1 Status to 1 while the MegaCore function is processing data and cannot be stopped Refer to Avalon MM Slave Interfaces on page 4 17 for full details 2 Output Width The width of the output frames in pixels 1 3 Output Height The height of the output frames in pixels 1 4 Horizontal Coefficient Specifies which memory bank horizontal coefficient writes from the Bank Write Address Avalon MM interface are made into Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 7 Control Register Maps Scaler 1 5 Table 7 7 Scaler Control Register Map Part 2 of 2 Address Register Description 5 Horizontal Coefficient Specifies which memory bank is used for horizontal coefficient reads Bank Read Address during data processing 6 Vertical Coefficient Bank Specifies which memory bank vertical coefficient writes from the Avalon Write Address MM interface are made into 2 7 Vertical Coefficient Bank Specifies which memory bank is used for vertical coefficient reads during R
29. Designs MegaWizard Plug In Manager Design Flow The MegaWizard Plug in Manager flow allows you to customize your IP core and manually integrate it in your design Specify Parameters To specify IP core parameters with the MegaWizard Plug In Manager follow these steps 1 Create a Quartus II project using the New Project Wizard available from the File menu 2 In the Quartus II software launch the MegaWizard Plug in Manager from the Tools menu and follow the prompts in the MegaWizard Plug In Manager interface to create or edit a custom IP core variation To select a specific Altera IP core click the IP core in the Installed Plug Ins list in the MegaWizard Plug In Manager For example to specify a RapidIO MegaCore function click Installed Plug Ins gt Interfaces RapidIO 4 Specify the parameters on the Parameter Settings pages For detailed explanations of these parameters refer to the Parameter Settings chapter in this document 5 If the IP core provides a simulation model specify appropriate options in the wizard to generate a simulation model amp Altera IP supports a variety of simulation models including simulation specific IP functional simulation models and encrypted RTL models and plain text RTL models These are all cycle accurate models The models allow for fast functional simulation of your IP core instance using industry standard VHDL or Verilog HDL simulators For some cores only the plain
30. Field 0 and the start of Field 1 Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 7 Control Register Maps Test Pattern Generator 7 13 Table 7 17 Clocked Video Output Control Register Map Part 3 of 3 Address Register Description 22 Model Standard The value output on the vid_std signal Start of frame sample register The sample and subsample upon which the SOF occurs and the vid_sof signal triggers 23 ModS et Sample Bits 0 1 are the subsample value m Bits 2 15 are the sample value 24 rm SOF line register The line upon which the SOF occurs measured from the rising edge of the FO vertical sync 25 odel Vcoclk Divider Number of cycles of vid clk vcoclk before vcoclk_div signal triggers 26 odel Ancillary Line The line to start inserting ancillary data packets 27 odel FO Ancillary Line The line in field FO to start inserting ancillary data packets Video mode 1 valid Set to indicate that this mode is valid and can be used for 28 odel Valid video output 29 ode2 Control 30 1 Note to Table 7 17 1 The rows in the table are repeated in ascending order for each video mode All of the Mode V registers are write only Test Pattern Generator The width of each register in the Test Pattern Generator control register map is 16 bits The control data is read once at the start of each frame and is buffered inside the MegaCore f
31. MegaCore function is ready to receive data din port Avalon ST startofpacket signal This signal marks the fpack In start of an Avalon ST packet din valid n din port Avalon ST valid signal This signal identifies the cycles when the port should input data _ dout port Avalon ST data bus Pixel data is transferred out of the dout data Out MegaCore function over this bus dout port Avalon ST endofpacket signal This signal marks the t fpack t REL See packs ay end of an Avalon ST packet dout port Avalon ST ready signal This signal is asserted by the dout ready In downstream device when it is able to receive data dout port Avalon ST startofpacket signal This signal marks t fpack t dout startofpacket the start of an Avalon ST packet Out dout port Avalon ST valid signal This signal is asserted when the MegaCore function is outputs data slave port Avalon MM address Specifies a word offset into the slave slave av address In address space Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 6 Signals Switch Table 6 17 Control Synchronizer Signals Part 2 of 2 6 21 Signal Direction slave port Avalon Description read signal When this signal is asserted the 1 In av read slave port drives new data onto the read data bus slave port Avalon readdata bus T
32. Precision Signed Number of horizontal 2 4 8 16 32 phases 64 128 256 Specify the number of horizontal phases Vertical Coefficient On or Off Turn on if you want the fixed point type that stores the vertical coefficients to have a sign bit Vertical Coefficient Precision Integer bits 0 15 Default 1 Specifies the number of integer bits for the fixed point type used to store the vertical coefficients Vertical Coefficient Precision Fraction bits 3 15 Default 7 Specifies the number of fractional bits for the fixed point type used to store the vertical coefficients Number of bits to preserve between vertical and horizontal filtering 7 3 32 Default 9 Specifies the number of bits to preserve between vertical and horizontal filtering Horizontal Coefficient Precision Signed On or Off Turn on if you want the fixed point type that stores the horizontal coefficients to have a sign bit Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 3 Parameter Settings Scaler 3 9 Table 3 10 Scaler Parameter Settings Tab Algorithm and Precision Page Part 2 of 2 Parameter Horizontal Coefficient Precision Integer bits Value 0 15 Default 1 Description Specifies the number of integer bits for the fixed point type used to store the horizontal coefficients Horizontal Coefficient Precision Fraction bits 0
33. Switch Table 5 27 Control Synchronizer Parameters Part 2 of 2 Parameter Value Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface Up to four color planes in parallel with any number of color planes in sequence Color Pattern The Switch MegaCore function allows the connection of up to twelve input video streams to twelve output video streams For example 1 to 2 4 to 1 6 to 6 and so on The connections can be reconfigured at run time via a control input Figure 5 27 shows an example 3 to 2 Switch with the possible connections for each input and output The Switch MegaCore function does not support duplication or combining of streams If these functions are required use the Color Plane Sequencer MegaCore function Each output from the Switch can be driven by only one input and each input to the Switch can drive only one output Any input can be disabled that is not routed to an output which stalls the input by pulling it s ready signal low The routing configuration of the Switch MegaCore function is run time configurable through the use of an Avalon MM slave control port The registers of the control port can be written to at anytime but the Switch loads the new values only when it is stopped Stopping the Switch MegaCore function causes all the input streams to be synchronized at the end of an Avalon ST Video image packet There are two ways to load a new configuration
34. you can find RapidIO by expanding Interface Protocols High Speed gt RapidIO Specify the required parameters on the Parameter Settings tabs of the MegaWizard interface For detailed explanations of these parameters refer to the Parameter Settings chapter in this document Click Finish to complete the IP core instance and add it to the system Complete the SOPC Builder System To complete the SOPC Builder system follow these steps 1 Add and parameterize any additional components Some IP cores include a complete SOPC Builder system design example Use the SOPC Builder Connection panel on the System Contents tab to connect the components By default clock names are not displayed To display clock names in the Module Name column and the clocks in the Clock column in the System Contents tab click Filters to display the Filters dialog box In the Filter list click All If you intend to simulate your SOPC builder system on the System Generation tab turn on Simulation to generate a functional simulation model for your system Click Generate to generate the system a Among the files generated by SOPC Builder is the qip file This file contains information about a generated IP core or system In most cases the qip file contains all of the necessary assignments and information required to process the IP core or system in the Quartus II Compiler Generally a single qip file is generated for each SOPC Builder system Ho
35. 0 0 0 0c ccc 4 2 4 2 Video Data Packets d 4 3 Static Parameters of Video Data Packets 0 0 ccc eee ent n teen e 4 3 Bits Per Pixel Per Color Plane sesseeeeeee RII n 4 4 Color Patteri TEENS Ll r 4 4 Specifying Color Pattern Options 0 0 menner iieiea ee nents 4 6 Structure of Video Data Packets 0 0 ccc ccc ene teen ene n n 4 7 Control Data Packets Re peregre pow hdc RR Pastas S ER RC OR EROR RR 4 7 Use of Control Data Packets cece e n 4 9 Structure of a Control Data Packet 0 eect ence ene nee 4 9 Ancillary Data Packets certe abetted oe PR eer dee aes eae E Y Ed ides 4 10 User Defined and Altera Reserved Packets 00sec cece ete etn tenn eens 4 11 Packet Propagation ss issver sies Rer e ee tte be ee eld eee Fed ace een ed we 4 11 Transmission of Avalon ST Video Over Avalon ST Interfaces 4 12 Packet Transfer Examples een a aa 4 12 Example 1 Data Transferred in Parallel lllsssssseseee ee 4 12 Example 2 Data Transferred in Sequence 000666 4 15 Example 3 Control Data Transfer lsssssssssses n 4 16 Avalon MM Slave Interfaces 2 0 0 0 0c ccc ec Rr rre 4 17 Video and Image Processin
36. 0 of each addressable register Table 7 12 Deinterlacer Control Register Map for Run Time Control of the Motion Adaptive Algorithm Address Register Description 0 Control Bit 0 of this register is the Go bit All other bits are unused Setting this bit to 1 causes the Interlacer MegaCore function to pass data through without modification 1 Bit 0 of this register is the Status bit All other bits are unused Refer to Avalon MM HEN Slave Interfaces on page 4 17 for full details 9 Progressive Setting bit 0 to 1 disables the Interlacer When disabled progressive inputs are pass through propagated without modification July 2010 Altera Corporation Video and Image Processing Suite User Guide 1 8 Frame Reader The width of each register of the frame reader is 32 bits The control data is read once at the start of each frame The registers may be safely updated during the processing of a frame Table 7 13 describes the Frame Reader runtime control registers Chapter 7 Control Register Maps Frame Reader Table 7 13 Frame Reader Register Map for Run Time Control Address Register Description Bit 0 of this register is the co bit Setting this bit to 1 causes the Frame Reader to start 0 Control outputting data Bit 1 of the control register is the interrupt enable Setting bit 1 to 1 enables the end of frame interrupt 1 SESE Bit 0 of this register is the S
37. 15 Default 7 Specifies the number of fractional bits for the fixed point type used to store the horizontal coefficients Notes to Table 3 10 1 These parameters determine the number and size of the DSP blocks For example with four vertical and four horizontal taps and nine bits preserved between vertical and horizontal filtering the scaler uses a total of eight 9x9 DSP blocks Table 3 11 Scaler Parameter Settings Tab Coefficients Page Parameter Value Description Load coefficient data at On or Off Turn on to load the coefficient data at runtime runtime Turn on to map horizontal and vertical coefficients to the same memory When on and Load coefficient data at runtime is also A e venta On or Off on writes to the vertical coefficients are ignored The choice of read bank remains independent for horizontal and vertical coefficients Vertical Coefficient Data Choose the number of coefficient banks to enable double 1 6 Default 2 Memory banks buffering fast coefficient swapping or direct writes Vertical Coefficient Data Filter function Lanczos 1 12 or Custom Default Lanczos 2 You can choose from 12 pre defined Lanczos functions or use the coefficients saved in a custom coefficients file Vertical Coefficient Data When a custom function is selected you can browse for a comma separated value file containing custom coefficients Use Custom coefficient file
38. 3 m 4 2 specifies full resolution in plane 1 half width and height resolution in planes 2 and 3 All modes of the Chroma Resampler assume the chrominance chroma and luminance luma samples are co sited that is their values are sampled at the same time The horizontal resampling process supports nearest neighbor and filtered algorithms The vertical resampling process only supports the nearest neighbor algorithm The Chroma Resampler MegaCore function can be configured to change image size at run time using control packets Horizontal Resampling 4 2 2 Figure 5 1 shows the location of samples in a co sited 4 2 2 image Figure 5 1 Resampling 4 4 4 to a 4 2 2 Image Sample No 1 2 3 4 5 6 7 8 O Y 6 O 89 O O ds 2 8 O 6 O 6 O 6 CbCr 3 O O O Y CbCr 4 6 O 6 8 O 6 Conversion from sampling rate 4 4 4 to 4 2 2 and back are scaling operations on the chroma channels This means that these operations are affected by some of the same issues as the Scaler MegaCore function However because the scaling ratio is fixed as 2x up or 2x down the Chroma Resampler MegaCore function is highly optimized for these cases The Chroma Resampler MegaCore Function only supports the cosited form of horizontal resampling the form for 4 2 2 data in ITU Recommendation BT 601 MPEG 2 and other standards For more information about the ITU standard refer to Recommendation ITU R BT 601
39. 32 65 536 Default 1 080 Choose the image height for interlaced field 1when no format can be automatically detected Sync Signals Embedded in video On separate wires Choose whether the synchronization signal is embedded in the video stream or provided on a separate wire Allow color planes in Choose whether run time switching is allowed between sequential and input On or Off parallel color plane transmission formats The format is controlled by the q p vid_hd_sdn signal Specifies whether the Avalon ST output and synchronization outputs sof sof_locked refclk_div are generated Generate m No Only Avalon ST Video output synchronization outputs No Yes Only mE m Yes Avalon ST Video output and synchronization outputs m Only Only synchronization outputs Width of bus vid std 1 16 The width in bits of the vid std bus Extract ancillary packets On or Off Specifies whether ancillary packets are extracted in embedded sync mode Pixel FIFO size 32 memory limit Default 1 920 Choose the required FIFO depth in pixels limited by the available on chip memory Video in and out use the same clock On or Off Turn on if you want to use the same signal for the input and output video image stream clocks Use control port On or Off Turn on to use the optional stop go control port Video and Image Processing Suite User Guide July 2010 Alter
40. 4 3 Recommended Color Patterns Recommended Color Patterns Color Space Parallel Sequence R R G B G B Y CbCr 4 2 2 Y CbGr 4 a 4 2 0 Y CbCr ober Following these recommendations ensures compatibility minimizing the need for color pattern rearranging These color patterns are designed to be compatible with common clocked video standards where possible If you must rearrange color patterns you can use the Color Plane Sequencer MegaCore function Specifying Color Pattern Options You can specify parameters in the MegaWizard interface that allow you to describe a color pattern that has its color planes entirely in sequence one per cycle or entirely in parallel all in one cycle You can select the number of color planes per pixel and whether the planes of the color pattern transmit in sequence or in parallel Some of the MegaCore functions user interfaces provide controls allowing you to describe a color pattern that has color plane samples in parallel with each other and in sequence such that it extends over multiple clock cycles You can select the number of color planes of the color pattern in parallel number of rows of the color pattern and the number of color planes in sequence number of columns of the color pattern Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 4 Interfaces 4 7 Avalon ST Video Protocol Structure of Video Data Packets
41. 7 2 3 read_master_N_av_readdata read_master_N port Avalon MM readdata bus These input lines carry data for read transfers 7 2 3 July 2010 Altera Corporation Video and Image Processing Suite User Guide 6 10 Table 6 9 Deinterlacer Signals Part 3 of 3 Chapter 6 Signals Deinterlacer Signal read master N av readdatavalid Direction In Description read master port Avalon MM readdatavalid signal This signal is asserted by the system interconnect fabric when requested read data has arrived 1 2 3 read master N av reset read master port reset signal The interface is asynchronously reset when reset is asserted high and must be de asserted synchronously with respect to the rising edge of the clock signal 1 2 3 4 read master N waitrequest read master N port Avalon MM waitrequest signal Asserted by the system interconnect fabric to cause the master port to wait 1 2 3 write master av address Out write master port Avalon MM address bus Specifies a byte address in the Avalon MM address space 1 3 write master av burstcount Out write master port Avalon MM burstcount signal Specifies the number of transfers in each burst 1 2 3 write master av clock write master port clock signal The interface operates on the rising edge of the clock signal 1 3 4 write maste
42. Avalon ST interfaces which allow them to stall the data while they perform internal calculations During control packet processing the MegaCore functions might stall frequently and read write less than once per clock cycle During data processing the MegaCore functions generally process one input output per clock cycle There are however some stalling cycles Typically these are for internal calculations between rows of image data and between frames fields When stalled the MegaCore function signals that it is not ready to receive or produce data The time spent in the stalled state varies between MegaCore functions and their parameterizations In general it is a few cycles between rows and a few more between frames Details of exceptions to this behavior and details of stalling due to internal buffering are given for each MegaCore function in the following sections If data is not available at the input when required all of the MegaCore functions stall and thus do not output data With the exceptions of the Deinterlacer and Frame Buffer in double or triple buffering mode none of the MegaCore functions ever overlap the processing of consecutive frames The first sample of frame F 1 is not input until after the last sample of frame F has been output The following sections give bounds and guidelines describing the stalling and throughput of the MegaCore functions but do not attempt to specify precise behavior down to the last clock cyc
43. Corporation Chapter 6 Signals 2D FIR Filter 6 3 Table 6 3 Gamma Corrector Signals Part 2 of 2 Signal Direction Description din port Avalon ST endofpacket signal This signal marks the end of an din endofpacket In Avalon ST packet din port Avalon ST ready signal This signal indicates when the din ready Out MegaCore function is ready to receive data din port Avalon ST startofpacket signal This signal marks the start of din startofpacket In an Avalon ST packet din valid m din port Avalon ST valid signal This signal identifies the cycles when the port should input data es Out dout port Avalon ST data bus Pixel data is transferred out of the im MegaCore function over this bus _ dout port Avalon ST endofpacket signal This signal marks the end of dout endofpacket Out an Avalon ST packet _ dout port Avalon ST ready signal This signal is asserted by the dout ready In downstream device when it is able to receive data dout port Avalon ST startofpacket signal This signal marks the start ee las Out of an Avalon ST packet dout port Avalon ST va1id signal This signal is asserted when the Gout elas MegaCore function outputs data m m gamma lut slave port Avalon MM address Specifies a word offset into g nii the slave address space gamma lut slave port Avalon MM chipselect signal The gamma 1ut gamma lUt av Chipselect i port ignores
44. Device Family Combinational DSP Blocks fmax gisters Bits M9K 9x9 18 18 MHz Interlacing 1080p 10 bit video 2 channels over a parallel interface Cyclone 111 1 460 400 222 Stratix 2 303 401 434 Interlacing 1080p 10 bit video 2 channels over a parallel inteface with runtime interlacing control Cyclone III 7 529 444 239 Stratix 2 360 444 434 Notes to Table 1 13 1 EP3C5F256C6 devices 2 EP3SL50F484C2 devices Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 1 About This MegaCore Function Suite Performance and Resource Utilization Frame Buffer Table 1 14 shows the performance figures for the Frame Buffer Table 1 14 Frame Buffer Performance Device Family Combinational E Memory DSP Blocks fmax gisters Bits M9K 9x9 18 18 MHz Double buffering XGA 1024x768 8 bit RGB with a sequential data interface Cyclone III 1 2 103 1 725 8 408 6 161 Stratix 111 2 1 749 1 726 8 432 11 300 Triple buffering VGA 640x480 8 bit RGB with a parallel data interface Cyclone III 1 2 121 1 670 7 368 6 169 Stratix 111 2 1 737 1 671 7 368 10 290 Triple buffering VGA 640x480 8 bit RGB buffering up to 32 large Avalon ST V
45. Each word of the control packet is transferred in the lowest four bits of a color plane starting with bits 3 0 then 13 10 Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 4 Interfaces 4 17 Avalon MM Slave Interfaces Example 1 uses the start of packet and end of packet lines in exactly the same way Figure 4 14 Example of Control Packet Transfer clock din valid j o mom L din_startofpacket din_endofpacket ML T 7 To we gt gt gt binary 720 0x02D0 240 0x00F0 ifo fO 10xx image data f1 11xx p 00xx Avalon MM Slave Interfaces The Video and Image Processing Suite MegaCore functions that permit run time control of some aspects of their behavior use a common type of Avalon MM slave interface for this purpose Each slave interface provides access to a set of control registers which must be set by external hardware You should assume that these registers power up in an undefined state The set of available control registers and the width in binary bits of each register varies with each control interface For a description of the control registers for each individual MegaCore function refer to Chapter 7 Control Register Maps The first two registers of every control interface perform the following two functions the others vary with each control interface m Register 0 is the Go register Bit zero of this register is the Go bit th
46. Encoding Parameters of Digital Television for Studios 1992 International Telecommunications Union Geneva 4 4 4 to 4 2 2 The nearest neighbor algorithm is the simplest way to down scale the chroma channels It works by simply discarding the Cb and Cr samples that occur on even columns assuming the first column is numbered 1 This algorithm is very fast and cheap but due to aliasing effects it does not produce the best image quality Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 5 Chroma Resampler To get the best results when down scaling you can apply a filter to remove high frequency data and thus avoid possible aliasing The filtered algorithm for horizontal subsampling uses a 9 tap filter with a fixed set of coefficients The coefficients are based on a Lanczos 2 function Choosing and Loading Coefficients on page 5 17 that the Scaler MegaCore function uses Their quantized form is known as the Turkowski Decimator For more information about the Turkowski Decimator refer to Ken Turkowski Graphics Gems chapter Filters for common resampling tasks pages 147 165 Academic Press Professional Inc San Diego CA USA 1990 The coefficients are fixed and approximate to powers of two therefore they can be implemented by bit shifts and additions This algorithm efficiently eliminates aliasing in the chroma channels and uses no memory or multipliers However i
47. Figure 4 6 shows the structure of a video data packet using a set parallel color pattern and bits per pixel per color plane Figure 4 6 Parallel Color Pattern Color gt Bits per pixel Video Data repeating a Pattern per color plane regular color pattern Symbols on bits 23 16 Symbols on bits 15 8 Symbols on bits 7 0 Video data packet type identifier 4 bits in least significant symbol X s for unused symbols Figure 4 7 on page 4 7 shows the structure of a video data packet using a set sequential color pattern and bits per pixel per color plane Figure 4 7 Sequence Color Pattern Color Bits per pixel Pattern B G R per color plane Video Data repeating a regular color pattern Symbols on bits 7 0 G RB GR BGR Start Video data packet type identifier 4 bits in least significant symbol X s for unused symbols Control Data Packets Control data packets configure the MegaCore functions so that they correctly process the video data packets that follow In addition to a packet type identifier of value 15 control data packets contain the following data Width 16 bit Height 16 bit Interlacing 4 bit The width and height values are the dimensions of the video data packets that follow The width refers to the width in pixels of the lines of a frame The height refers the number of lines in a frame or field such that a field of interlaced 1920x1080 108
48. MegaCore function The reading on non video packets is performed by handling any packet until one arrives with type 0 This means that when the Go bit is checked the non video type has been taken out of the stream but the video is retained Specification of the Type of Avalon MM Slave Interfaces The Avalon Interface Specifications define many signal types many of which are optional Table 4 10 lists the signals that the Avalon MM slave interfaces use in the Video and Image Processing Suite Table 4 10 does not show unused signals Table 4 10 Avalon MM Slave Interface Signal Types Signal Width Direction chipselect 1 1 Input read 1 1 input address Variable Input readdata Variable Output write 1 Input writedata Variable Input waitrequest 2 1 Output irq 3 1 Output Notes to Table 4 10 1 The Slave interfaces of the Video and Image Processing MegaCore functions may use either chipselect Or read 2 For slave interfaces that do not have a predefined number of wait cycles to service a read or a write request 3 For slave interfaces with an interrupt request line Ka Clock and reset signal types are not included The Video and Image Processing Suite does not support Avalon MM interfaces in multiple clock domains Instead the Avalon MM slave interfaces must operate synchronously to the main clock and reset signals of the MegaCore function The Avalon MM slave interfaces must ope
49. No Not used No Yes outputs m Yes Synchronization outputs from the Clocked Video Input MegaCore function sof so locked are used Width of vid std 0 16 Specifies the width of the via sta bus Notes to Table 3 18 1 This parameter is available only when Use control port is on Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 3 Parameter Settings Color Plane Sequencer Color Plane Sequencer Table 3 19 shows the Color Plane Sequencer MegaCore function parameters 3 19 Table 3 19 Color Plane Sequencer Parameter Settings Parameter Bits per pixel per color plane Value 4 20 Default 8 Choose the number of bits per pixel per color plane Description Two pixels per port 1 On or Off Turn on to enable two pixels on each port Color planes in parallel dinO 1 3 Choose the number of color planes in parallel for input port dino Color planes in sequence dinO 1 4 Choose the number of color planes in sequence for input port dino Port enabled din1 On or Off Turn on to enable input port dino Color planes in parallel din 1 3 Choose the number of color planes in parallel for input port dint Color planes in sequence din1 1 4 Choose the number of color planes in sequence for input port dint Port enabled doutO On or Off Turn on to enable output port aout 0 Source non image packets dinO dint dind Choose the sou
50. OpenCore Plus evaluation m SOPC Builder ready SOPC Builder systems use an active low reset while the Video and Image Processing Suite MegaCore functions use an active high reset Arbitrator logic in SOPC Builder automatically inverts the reset signals General Description This section provides a general description of each MegaCore function in the Video and Image Processing Suite July 2010 Altera Corporation Video and Image Processing Suite User Guide 1 4 Chapter 1 About This MegaCore Function Suite General Description Color Space Converter CSC The Color Space Converter MegaCore function transforms video data between color spaces These color spaces allow you to specify colors using three coordinate values The Color Space Converter supports a number of predefined conversions between standard color spaces and allows the entry of custom coefficients to translate between any two three valued color spaces You can configure the Color Space Converter to change conversion values at run time using an Avalon MM slave interface Chroma Resampler The Chroma Resampler MegaCore function resamples video data to and from common sampling formats The human eye is more sensitive to brightness than tone Taking advantage of this characteristic video transmitted in the Y CbCr color space often subsamples the color components Cb and Cr to save on data bandwidth Gamma Corrector The Gamma Corrector MegaCore function corrects
51. Recommended Parameters for the Scaler MegaCore Function lower quality Scaling Problem Taps Phases Precision Coefficients Scaling up with any input output resolution 4 16 Signed 1 integer bit 7 fraction bits es ad or Scaling down from M pixels to N pixels MM 16 Signed 1 integer bit 7 fraction bits Lanczos 2 ae Hs 16 Signed 1 integer bit 7 fraction bits Lanczos 1 The Scaler MegaCore function can process streams of pixel data of the types shown in Table 5 8 Table 5 8 Scaler Avalon ST Video Protocol Parameters Parameter Frame Width Value Maximum frame width is specified in the MegaWizard interface the actual value is read from control packets Frame Height Maximum frame height is specified in the MegaWizard interface the actual value is read from control packets Interlaced Progressive Progressive Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface Color Pattern One two or three channels in sequence or in parallel as selected in the MegaWizard interface For example if three channels in sequence is selected where y can be any color plane Clipper The Clipper MegaCore function provides a means to select an active area from a video stream and discard the remainder The active region can be specified by either providing the offsets from each border o
52. Slave Interfaces on page 4 17 For details of the register map for the Scaler MegaCore function refer to Table 7 7 on page 7 4 In the formal definitions of the scaling algorithms the width and height of the input image are denoted w and h respectively The width and height of the output image are denoted Wu and hout F is the function which returns an intensity value for a given pointon the input image and O is the function which returns an intensity value on the output image Nearest Neighbor Algorithm The nearest neighbor algorithm that the scaler uses is the lowest quality method and uses the fewest resources Jagged edges may be visible in the output image as no blending takes place However this algorithm requires no DSP blocks and uses fewer logic elements than the other methods Scaling down requires no on chip memory scaling up requires one line buffer of the same size as one line from the clipped input image taking account of the number of color planes being processed For example up scaling an image which is 100 pixels wide and uses 8 bit data with 3 colors in sequence but is clipped at 80 pixels wide needs 8 x 3 x 80 1920 bits of memory Similarly if the 3 color planes are in parallel the memory requirement is still 1920 bits For each output pixel the nearest neighbor method picks the value of the nearest input pixel to the correct input position Formally to find a value for an output pixel located at i j
53. Suite User Guide July 2010 Altera Corporation RA Contents Chapter 1 About This MegaCore Function Suite New Features Release Information Device Family Support OAPI CS PEE General Description Color Space Converter CSC Chroma 1 Gamma Corrector 2D FIR Filter 2 0 eee 2D Median Filter Alpha Blending Mixer Clippet Deinterlacer 2 22 e eher pue devine s Interlacer ee ae diated ees Frame Reader Frame Buffer 2 Clocked Video Input Clocked Video Color Plane Sequencer Test Pattern Control Synchronizer epe pbi eer Design Example MegaCore Verification Performance and Resource Utilization Color Space Converter Chroma Resampler Gamma Corrector 2D FIR Fiter 2D Median
54. There is no internal buffering in the Alpha Blending Mixer MegaCore function so the delay from input to output is just a few clock cycles and increases linearly with the number of inputs Error Recovery The Alpha Blending Mixer MegaCore function processes video packets from the background layer until the end of packet is received If an endofpacket signal is received too early for the background layer the Alpha Blending Mixer enters error mode and continues writing data until it has reached the end of the current line The endofpacket signal is then set with the last pixel sent If an endofpacket signal is received early for one of the foreground layers or for one of the alpha layers the Alpha Blending Mixer stops pulling data out of the corresponding input and pads the incomplete frame with undefined samples If an endofpacket signal is received late for the background layer one or more foreground layers or one or more alpha layers the Alpha Blending Mixer enters error mode When the Alpha Blending Mixer MegaCore function enters error mode because of an early endofpacket for the background layer or a late endofpacket for any layer it has to discard data until the endofpacket has been reached for all input layers Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 69 Stall Behavior and Error Recovery Scaler This error recovery process maintains the synchronization between a
55. a number of pixels from the middle of a frame are processed Figure 4 13 Timing Diagram Showing R G B Transferred in Sequence 1 2 3 4 5 6 T 8 9 cock LI LU LI LI Lt din_ready din valid din_data 7 0 7 dout ready ooo dout_valid dout_data 7 0 Bn Gan Rmn Note to Figure 4 13 1 The startofpacket and endofpacket signals are not shown but are always low during the sequence shown in this figure This example is similar to Figure 4 12 on page 4 13 except that it is configured to accept data in sequence rather than parallel The signals shown in the timing diagram are therefore the same but with the exception that the two data ports are only 8 bits wide The sequence of events shown in Figure 4 13 is 1 Initially din_ready is logic 1 The source driving the input port sets din_valid to logic 1 and puts the blue color value B on the din data port 2 The source holds din validat logic 1 and the green color value G is input 3 The corresponding red color value R is input July 2010 Altera Corporation Video and Image Processing Suite User Guide 4 16 Chapter 4 Interfaces Avalon ST Video Protocol 4 The MegaCore function sets dout valid to logic 1 and outputs the blue color value of the first processed color sample on the dout data port Simultaneously the sink connected to the output port sets dout ready to logi
56. and registered when receiving the image data header that signals new frame It can be safely updated during the processing of a frame Table 7 11 Deinterlacer Control Register Map for Synchronizing the Input and Output Frame Rates Address Register Description Bit 0 of this register is the co bit all other bits are unused Setting this bit to 0 causes the Deinterlacer MegaCore function to stop before control information is read and before 0 Control receiving and buffering the next frame While stopped the Deinterlacer may freeze the output and repeat a static frame if triple buffering is enabled Refer to Avalon MM Slave Interfaces on page 4 17 for full details 1 stat Bit 0 of this register is the Status bit all other bits are unused Refer to Avalon MM hha Slave Interfaces on page 4 17 for full details 2 Input frame Write only register An 8 bit integer value for the input frame rate This register cannot be rate read 1 3 Output frame Write only register An 8 bit integer value for the output frame rate The register cannot be rate read 1 Note to Table 7 11 1 The behavior of the rate conversion algorithm is not directly affected by a particular choice of input and output rates but only by their ratio 23 976 gt 29 970 is equivalent to 24 gt 30 Interlacer Table 7 12 describes the control register map for the Interlacer The control interface is 8 bits wide but the Interlacer only uses bit
57. are transmitted as two interlaced fields The synchronization bits do not affect the behavior of the Deinterlacer because the synchronization field is fixed at compile time However they do affect the behavior of the Frame Buffer when dropping and repeating pairs of fields Synchronizing on f0 means that a frame should be constructed from an f1 followed by an f0 Similarly synchronizing on f1 means that a frame should be constructed from an f0 followed by an f1 The other synchronization options are don t care when there is no difference in combining an f1 then f0 or an f0 then f1 The final option is don t know to indicate that the synchronization of the interlaced fields is unknown The encoding for these options are 00 for synchronize on f0 01 for synchronize on f1 11 for don t care and 10 for don t know If the first two bits indicate a progressive frame the second two bits indicate the last field type that the progressive frame was deinterlaced from The encoding for this is 10 for unknown or 11 for not deinterlaced 00 for f0 last and 0 for f1 last Table 4 4 gives some examples of the control parameters Table 4 4 Examples of Control Data Packet Parameters Parameters T Description Type Width Height Interlacing 15 1920 1080 0011 The frames that follow are progressive with a resolution of 1920x1080 15 640 480 0011 The frames that follow are progressive with a resolution of
58. as genuine interlaced video content although it may originate from a progressive source converted with a pull down Use of Control Data Packets A control data packet must immediately precede every video data packet To facilitate this any IP function that generates control data packets should do so once before each video data packet Additionally all other MegaCore functions in the processing pipeline must either pass on a control data packet or generate a new one before each video data packet If the function receives more than one control data packet before a video data packet it uses the parameters from the last received control data packet If the function receives a video data packet with no preceding control data packet the current functions keep the settings from the last control data packet received with the exception of the next interlaced field type toggling between f0 and f1 for each new video data packet that it receives La This behavior may not be supported in future releases Altera recommends for forward compatibility that functions implementing the protocol ensure there is a control data packet immediately preceding each video data packet Structure of a Control Data Packet A control data packet complies with the standard of a packet type identifier followed by a data payload The data payload is split into nibbles of 4 bits each data nibble is part of a symbol If the width of a symbol is greater than 4 b
59. bit R G B using 15 bit coefficients Cyclone III 1 3 584 3 612 230 400 30 20 164 Stratix 2 2 663 3 365 230 400 30 20 263 Notes to Table 1 7 1 EP3C10F256C6 devices 2 EP3SE50F780C2 devices 2D Median Filter Table 1 8 shows the performance figures for the 2D Median Filter Table 1 8 2D Median Filter Performance Part 1 of 2 Device Family Combinational Logic Memory DSP Blocks fux LUTS ALUTs Registers Bits M9K 9x9 18 18 MHz 3x3 median filtering HDTV 720 pixel monochrome video Cyclone III 7 1 575 1 200 25 600 6 233 Stratix 2 994 1 200 25 600 6 351 Median filtering 64x64 pixel R G B frames using a 3x3 kernel of pixels Cyclone III 1 1 535 1 154 3 072 2 230 Stratix 2 971 1 155 3 072 2 349 Median filtering 352x288 pixel two color frames using a 5x5 kernel of pixels Cyclone III 1 5 416 3 828 28 160 8 203 Stratix 2 2 682 3 832 28 160 8 300 7x7 median filtering 352x288 pixel monochrome video Cyclone III 3 10 813 7 296 16 896 6 191 July 2010 Altera Corporation Video and Image Processing Suite User Guide 1 10 Chapter 1 About This MegaCore Function Suite Performance and Resource Utilization Table 1 8 2D Median Filter Performance Part 2 of 2 Device Family Co
60. coefficients in the MegaWizard interface this setting is forced even when the coefficients are loaded at run time Using multiple coefficient banks allows double buffering fast swapping or direct writing to the Scaler s coefficient memories The coefficient bank to be read during video data processing and the bank to be written by the Avalon MM interface are specified separately at runtime Refer to the control register map in Table 7 7 on page 7 4 This means that you can accomplish double buffering by performing the following steps 1 Select two memory banks at compile time 2 Atstart up run time select a bank to write into for example 0 and write the coefficients 3 Setthe chosen bank 0 to be the read bank for the Scaler and start processing 4 For subsequent changes write to the unused bank 1 and swap the read and write banks between frames Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 17 Scaler Choosing to have more memory banks allows for each bank to contain coefficients for a specific scaling ratio and for coefficient changes to be accomplished very quickly by changing the read bank Alternatively for memory sensitive applications use a single bank and coefficient writes have an immediate effect on data processing Algorithmic Description This section describes how the algorithmic operations of the polyphase scaler can be modelled using a fra
61. data at an edge transition Without taking any account of the luma the interpolation to produce chroma values for sample 4 would weight samples 3 and 5 equally From the luma you can see that sample 4 falls on an the low side of an edge so sample 5 is more significant than sample 3 The luma adaptive mode looks for such situations and chooses how to adjust the interpolation filter From phase 0 it can shift to 1 4 0 or 1 4 from phase 1 2 it can shift to 1 4 1 2 or 3 4 This makes the interpolated chroma samples line up better with edges in the luma channel and is particularly noticeable for bold synthetic edges such as text July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 6 Chapter 5 Functional Descriptions Chroma Resampler The luma adaptive mode uses no memory or multipliers but requires more logic elements than the straightforward filtered algorithm Figure 5 2 4 2 2 Data at an Edge Transition CbCr Color Value Y x CbCr Y Intensity Y CbCr 1 2 3 4 5 6 E Sample No Vertical Resampling 4 2 0 The Chroma Resampler MegaCore function does not distinguish interlaced data with its vertical resampling mode It only supports the co sited form of vertical resampling shown in Figure 5 3 Figure 5 3 Resampling 4 4 4 to a 4 2 0 Image Sample No 1 2 3 4 5 6 7 8 o sv 6 86 O 8 O dns 2o Ff oO 0 CbCr 3 O
62. data packet which transmits color planes in sequence to a color pattern that transmits color planes in parallel Figure 5 21 Example of Rearranging Color Patterns B Color pattern of a video data Color pattern of a video data packet on the input stream packet on the output stream 3 color plane samples in sequence 3 color plane samples in parallel Combining Color Patterns The Color Plane Sequencer also allows the combination of two Avalon ST Video streams into a single stream In this mode of operation two input color patterns one for each input stream are combined and arranged to the output stream color pattern a user defined way so long as it contains a valid combination of channels in sequence and parallel In addition to this combination and arrangement color planes can also be dropped Avalon ST Video packets other than video data packets can be forwarded to the single output stream with the following options m Packets from input stream 0 port din0 and input stream 1 port din1 forwarded input stream 0 packets being transmitted last The last control packet received is the one an Avalon ST Video compliant MegaCore function uses m Packets from input stream 0 forwarded packets from input stream 1 dropped m Packets from input stream 1 forwarded packets from input stream 0 dropped July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 56 Chapter 5 Functional Descriptions
63. devices Scaler Table 1 10 shows the performance figures for the Scaler Table 1 10 Scaler Performance Part 1 of 2 Device Family C mbinational Logic Memory DSP Blocks fmax LUTs ALUTs Registers Bits M9K 9x9 1818 MHz Scaling 640x480 8 bit three color data up to 1 024x768 with linear interpolation This can be used to convert video graphics array format VGA 640x480 to video electronics standards association format VESA 1024x768 Cyclone III 1 945 687 30 720 6 4 191 Video and Image Processing Suite User Guide July 2010 A Itera Corporation Chapter 1 About This MegaCore Function Suite 1 11 Performance and Resource Utilization Table 1 10 Scaler Performance Part 2 of 2 Device Family Combinational Logic Memory DSP Blocks fmax LUTs ALUTs Registers Bits M9K 99 18x18 MHz Stratix 2 682 624 30 720 6 4 346 Scaling R G B QCIF to common intermediate format CIF with no interpolation Cyclone III 1 434 297 4 224 3 223 Stratix 2 304 298 4 224 3 393 Scaling up or down between NTSC standard definition and 1080 pixel high definition using 10 taps horizontally and 9 vertically Resolution and coefficients are set by a run time control interface Cyclone III 3 3 842 3 095 417 456 58 19 161 Stratix III 2 2 225 2 757 417 4
64. each input frame is the only exception Altera recommends using the Clipper MegaCore function to feed the Deinterlacer with an interlaced video stream that it can support Boh with Scanline Duplication The bob with scanline duplication algorithm is the simplest and cheapest in terms of logic Output frames are produced by simply repeating every line in the current field twice The function uses only the current field therefore if the output frame rate is the same as the input frame rate the function discards half of the input fields Boh with Scanline Interpolation The bob with scanline interpolation algorithm has a slightly higher logic cost than bob with scanline duplication but offers significantly better quality Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 23 Deinterlacer Output frames are produced by filling in the missing lines from the current field with the linear interpolation of the lines above and below them At the top of an F1 field or the bottom of an FO field there is only one line available so it is just duplicated The function only uses the current field therefore if the output frame rate is the same as the input frame rate the function discards half of the input fields Weave Weave deinterlacing creates an output frame by filling all of the missing lines in the current field with lines from the previous field This option gives good results for s
65. freezes the output when the input drops Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 35 Clocked Video Input The Frame Buffer MegaCore function can process streams of pixel data of the type shown in Table 5 13 on page 5 35 Table 5 13 Frame Buffer Avalon ST Video Protocol Parameters Parameter Value Frame Width Run time controlled Maximum value selected in the MegaWizard interface Frame Height Run time controlled Maximum value selected in the MegaWizard interface b Progressive although interlaced data can be accepted in some cases rogressive Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface Color Pattern Any combination of one two three or four channels in each of sequence or parallel For example for three channels in sequence where B and y can be any color plane Clocked Video Input The Clocked Video Input MegaCore function converts from clocked video formats such as BT656 BT1120 and DVT to Avalon ST Video The Clocked Video Input strips the incoming clocked video of horizontal and vertical blanking leaving only active picture data and using this data with the horizontal and vertical synchronization information creates the necessary Avalon ST Video control and active picture packets No conversion is done to the active picture data the color plane info
66. from introducing chroma artefacts when using bob deinterlacing for moving regions Use the Motion bleed algorithm to prevent the motion value from falling too fast at a specific pixel position If the motion computed from the current and the previous pixels is higher than the stored motion value the stored motion value is irrelevant and the function uses the computed motion in the blending algorithm which becomes the next stored motion value However if the computed motion value is lower than the stored motion value the following actions occur m The blending algorithm uses the stored motion value m The next stored motion value is an average of the computed motion and of the stored motion This computed motion means that the motion that the blending algorithm uses climbs up immediately but takes about four or five frames to stabilize July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 24 Chapter 5 Functional Descriptions Deinterlacer The motion adaptive algorithm fills in the rows that are missing in the current field by calculating a function of other pixels in the current field and the three preceding fields as shown in the following sequence 1 Pixels are collected from the current field and the three preceding it the X denotes the location of the desired output pixel Figure 5 7 Figure 5 7 Pixel Collection for the Motion Adaptive Algorithm C 3 C 2 C 1 Current Field C Z IT LIT
67. function is dictated by the outgoing video During horizontal and vertical blanking periods it stalls and does not take in any more video data Error Recovery If the Clocked Video Output MegaCore receives an early end of packet it will re synchronize the outgoing video to the incoming video data on the next start of packet it receives If the Clocked Video Output MegaCore receives a late start of packet it will re synchronize the outgoing video data to the incoming video immediately Note that when Genlock functionality is enabled the Clocked Video Output MegaCore does not re synchronize to the incoming video The Switch MegaCore function only stalls its inputs when performing an output switch Before switching its outputs it synchronize all its inputs and during this synchronization the inputs may be stalled Table 5 28 shows the approximate latency from the video data input to the video data output for typical usage modes of each MegaCore function You can use this table to predict the approximate latency between the input and the output of your video processing pipeline The latency is described using one or more of the following measures m the number of progressive frames m the number of interlaced fields m the number of lines when less than a field of latency July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 74 Chapter 5 Functional Descriptions m asmall number of cycles O cycles Table 5 28 Late
68. in one clock cycle defines the number of symbols transmitted in parallel for all packet types on a particular Avalon ST interface A color pattern can represent more than one pixel This is the case when consecutive pixels contain samples from different color planes There must always be at least one common color plane between all pixels in the same color pattern Color patterns representing more than one pixel are identifiable by a repeated color plane name The number of times a color plane name is repeated is the number of pixels represented Figure 4 4 shows two pixels of horizontally subsampled Y CbCr 4 2 2 where Cb and Cr alternate between consecutive pixels Figure 4 4 Horizontally Subsampled Y CbCr Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 4 Interfaces Avalon ST Video Protocol 4 5 In the common case each element of the matrix contains the name of a color plane from which a sample should be taken The exception is for vertically sub sampled color planes These are indicated by writing the names of two color planes in a single element one above the other Samples from the upper color plane are transmitted on even rows and samples from the lower plane transmitted on odd rows as shown in Figure 4 5 Figure 4 5 Vertically Subsampled Y ChCr Plane for even rows Cb Cr Plane for odd rows Table 4 2 lists the static parameters and gives some examples of how you can
69. interrupted as soon as possible and may be padded with a single undefined pixel Frame Reader The Frame Reader MegaCore function stalls the output for several tens of cycles before outputting each video data packet and stalls the output where there is contention for access to external memory The Frame Reader MegaCore can be stalled due to backpressure without consequences Frame Buffer The Frame Buffer MegaCore function may stall frequently and read or write less than once per clock cycle during control packet processing During data processing at the input or at the output the stall behavior of the Frame Buffer is largely decided by contention on the memory bus July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 72 Chapter 5 Functional Descriptions Stall Behavior and Error Recovery Error Recovery The Frame Buffer MegaCore function does not rely on the content of the control packets to determine the size of the image data packets There is consequently no error condition such as early or late endofpacket signal and any mismatch between the size of the image data packet and the content of the control packet is propagated unchanged to the next MegaCore function Nevertheless the Frame Buffer does not write outside the memory allocated for each non image and image Avalon ST Video packet and packets are truncated if they are larger than the maximum size defined at compile time Color Plane Sequencer The
70. lines sof cvo sof The Clocked Video Output MegaCore function then repeats or removes that number of samples and lines in the output video to align the two SOF signals If the SOF signals are separated by less than a threshold number of samples the value of the Vcoclk Divider register the Clocked Video Output does not alter the output video If your PFD clock tracking has a delay associated with it Altera recommends that even if the vcoclk div signal is not being used the Vcoclk Divider register should be set to a threshold value e g 1 This stops the Clocked Video Output MegaCore function from re syncing every time a delay in clock tracking causes the SOF signals to drift out by a clock cycle The current distance between the SOF signals is stored internally and when either the repeat registers or the remove registers read 0 then the locked interrupt triggers Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 53 Clocked Video Output Figure 5 20 shows an example of how to connect the Clocked Video Input and Clocked Video Output MegaCore functions to a video PLL Figure 5 20 Example System Connections Video PLL 27 MHz Phase Detector 2 Charge P Divider oO Pump gt VCXO Feedback Divider FPGA refclk div vid clk sof sof locked us
71. logic 1 and the second pixel is transferred on din_data Simultaneously the MegaCore function begins transferring data on the output port The example MegaCore function has an internal latency of three clock cycles so the first output is transferred three cycles after being received This output is the type identifier for a video packet being passed along the datapath For guidelines about the latencies of each Video and Image Processing MegaCore function refer to Latency on page 5 73 The third pixel is input and the first processed pixel is output For the final sample of a frame the source sets din endofpacket to logic 1 din validto 1 and puts the bottom right pixel of the frame on to din data Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 4 Interfaces 4 15 Avalon ST Video Protocol Example 2 Data Transferred in Sequence This example shows how a number of pixels from the middle of a frame could be processed by another MegaCore function This time handling a color pattern that has planes B G R in sequence This example does not show the start of packet and end of packet signals because these are always low during the middle of a packet The bits per pixel per color plane and color pattern are shown in Table 4 9 Table 4 9 Parameters for Example of Data Transferred in Sequence Parameter Value Bits per Color Sample 8 Color Pattern B GR Figure 4 13 shows how
72. number of These registers contain a look up table that is used to apply gamma correction to video data An input intensity value of x is gamma corrected by replacing it with the contents of the x 1 th entry in the look up table Changing the values of these Gamma Look recisters has an immediate effect on the behavior of the MegaCore function To bits per color plane Table ensure that gamma look up values do not change during processing of a video frame use the Go bit in Interface 0 to stop the MegaCore function while the table is changed Table 7 4 Gamma Corrector Control Register Map Interface 2 Part 1 of 2 Address Register Name Description Unused This register is not used Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 7 Control Register Maps 2D FIR Filter Table 7 4 Gamma Corrector Control Register Map Interface 2 Part 2 of 2 Address Register Name Description Unused This register is not used 2 to 2 1 where is the number of bits per color plane Gamma Look Up Table These registers contain a look up table that is used to apply gamma correction to video data An input intensity value of x is gamma corrected by replacing it with the contents of the x 1 th entry in the look up table Changing the values of these registers has an immediate effect on the behavior of the MegaCore function To ensure that gamm
73. number of color planes are transmitted in transmission ah sequence or in parallel For example a value of 3 planes in sequence for format R G B R G B R G B a You program the actual gamma corrected intensity values at run time using the Avalon MM slave interface Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 3 Parameter Settings 2D FIR Filter 2D FIR Filter Table 3 5 2D FIR Filter Parameter Settings Tab General Page 3 5 Table 3 5 and Table 3 6 on page 3 6 show the 2D FIR Filter MegaCore function parameters Parameter Maximum image width Value 32 2600 Default 640 Description Choose the maximum image width in pixels Number of color planes in sequence 1 3 The number of color planes that are sent in sequence over one data connection For example a value of 3 for R G B R G B R GB Input Data Type Bits per pixel per color plane 3 4 20 Default 8 Choose the number of bits per pixel per color plane Unsigned Signed aa input is unsigned or signed 2 s ur On or Off Turn on to enable a defined input range put Data WE 4 048 575 to 524 288 Default 255 Set input range maximum value 7 ur Data Type 4 048 575 to 524 288 Default 0 Set input range minimum value 1 Output Data Type Bits per pixel per color plane 3 4 20 Default 8 Choose the number of bits per pix
74. on when stream contains two subsampled channels For other MegaCore functions to be able to treat these channels as two fully sampled channels in sequence the control packet width must be halved Test Pattern Generator Table 3 20 shows the Test Pattern Generator MegaCore function parameters Table 3 20 Test Pattern Generator Parameter Settings Part 1 of 2 Run time control Parameter Value Description Turn on to enable run time control of the image size When on the output of image size Onor am size parameters control the maximum values Maximum image 32 2600 T width Default 640 Choose the required output width in pixels July 2010 Altera Corporation Video and Image Processing Suite User Guide 3 20 Chapter 3 Parameter Settings Control Synchronizer Tahle 3 20 Test Pattern Generator Parameter Settings Part 2 of 2 Parameter Value Description Maximum image 32 2600 Choose the required output height in pixels This value should be the height height Default 480 of the full progressive frame when outputting interlaced data Bits per pixel per 4 20 color plane Default 8 Choose the number of bits per pixel per color plane Color space RGB or YCbCr Choose whether to use an R G B or Y CbCr color space Output format 4 4 4 4 2 2 4 2 0 Choose the format sampling rate format for the output frames Sad Sequence Parallel This function always outputs t
75. penta te diced 5 56 subsampled Data ete yer coL REC ie Sn Wa ee eae E ee Rhea 5 57 Avalon ST Video Stream Requirements 5 57 Test Pattern Generator mer pew be ead MER Uu ek Aa ETE Y EE edema pones 5 58 Test Pattern gt dor Re RR UE RU RR ESCUrT I ka CI e V E Yu E ER CERT RETE 5 58 Generation of Avalon ST Video Control Packets and Run Time Control 5 59 Output Data Types i co tese dece mb ee ae ale tea area 5 59 Control Synchronizer eee b e AH AA 5 61 Using the Control Synchronizer eene 5 61 INNUMERIS 5 64 Mixer Layer ee aaa teni CRT MERE ege aeq e e nq eem ede 5 64 Stall Behavior and Error Recovery nnn 5 66 Color Space Converter et er e e Wm en e gres reete tie een 5 66 Error Recovery csi turba d ae pese Dag voee Dae A ee a o e uie Haee reden 5 66 Chroma R samplet es ente Ep pee REP aen gue Reader dba iohannes eti 5 66 Error Recovery dde aed dco d oe d cie ded e Edi deg eee dte dede eet reed 5 67 Gamina COrrectoE s oeste e os ed ees et Rowe Sve eate E Rd i oed cede mas 5 67 Brror RecOVery eet o Ed epe bd de D a a dee ad ea a dois 5 67 2D EIRTUOE eo E oT 5 67 Error Recovery
76. pixels for Horizontal front porch Default 20 Frame Field 1 Frame Field 1 1 65 536 Choose the size of the horizontal back porch period in pixels for Horizontal back porch Default 192 Frame Field 1 Frame Field 1 0 65 536 Choose the number of lines in the vertical synchronization period for Vertical sync Default 5 Frame Field 1 July 2010 Altera Corporation Video and Image Processing Suite User Guide 3 18 Chapter 3 Parameter Settings Clocked Video Output Table 3 18 Clocked Video Output Parameter Settings Part 2 of 2 Parameter Value Description Frame Field 1 0 65 536 Choose the number of lines in the vertical front porch period for Vertical front porch Default 4 Frame Field 1 Frame Field 1 0 65 536 Choose the number of lines in the vertical back porch period for Vertical back porch Default 36 Frame Field 1 Interlaced and Field 0 0 65 536 Choose the line when the rising edge of the field bit occurs for Interlaced F rising edge line Default 0 and Field 0 Interlaced and Field 0 0 65 536 Choose the line when the rising edge of the vertical blanking bit for Field 0 F falling edge line Default 18 occurs for Interlaced and Field 0 0 65 536 Choose the line when the vertical blanking rising edge occurs for 9 15109 Default 0 Interlaced and Field 0 edge line Interlaced and Field 0 0 65 536 Ancillary packet Choose the line where ancillary packet insertion sta
77. processing data path that do not have buffering in between The Control Synchronizer then writes the data stored in its Avalon Slave register map to the addresses that are also specified in the register map Once this writing is complete the Control Synchronizer resumes the Avalon ST video data flowing through it This function ensures that any cores after the Control Synchronizer have their control data updated before the start of the video data packet to which the control data applies Once all the writes from a Control Synchronizer trigger are complete an interrupt is triggered or is initiated which is the completion of writes interrupt The control synchronizer has an address in its Avalon Slave Control port that you can use to disable or enable the trigger condition The Control Synchronizer can optionally be configured before compilation to set this register to the disabled value after every trigger event this is useful when using the control synchronizer to trigger only on a single event Using the Control Synchronizer This section provides an example of how to use the Control Synchronizer MegaCore function The Control Synchronizer is set to trigger on the changing of the width field of control data packets In the following example the Control Synchronizer is placed in a system containing a Test Pattern Generator a Frame Buffer and a Scaler The Control Synchronizer must synchronize a change of the width of the generated video pac
78. pu function is ready to receive data r if din port Avalon ST startofpacket signal This signal marks the start of an ar Avalon ST packet din valid din port Avalon ST valid signal This signal identifies the cycles when the port should input data A Out dout port Avalon ST data bus Pixel data is transferred out of the MegaCore Mc function over this bus _ dout port Avalon ST endofpacket signal This signal marks the end of an dout endofpacket Out Avalon ST packet mes In dout port Avalon ST ready signal This signal is asserted by the downstream device when it is able to receive data dout port Avalon ST startofpacket signal This signal marks the start of an dout startofpacket Out Avalon ST packet 3 dout port Avalon ST valid signal This signal is asserted when the MegaCore Out function outputs data 2D Median Filter Table 6 5 shows the input and output signals for the 2D Median Filter MegaCore function Table 6 5 2D Median Filter Signals Part 1 of 2 Signal Direction Description if The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is asserted high The reset In reset must be de asserted synchronously with respect to the rising edge of the clock signal din port Avalon ST data bus Pixel data is transferred into the MegaCore function din data In over this bu
79. received too early or too late relative to the field dimensions contained in the last control packet processed In all its configurations the Deinterlacer discards extra data if the endofpacket signal is received too late If an early endofpacket signal is received when the Deinterlacer is configured for no buffering the MegaCore function interrupts its processing within one or two lines sending undefined pixels before propagating the endofpacket signal If an early endofpacket signal is received when the Deinterlacer is configured to buffer data in external memory the input side of the MegaCore function stops processing input pixels It is then ready to process the next frame after writing undefined pixels for the remainder of the current line into external RAM The output side of the Deinterlacer assumes that incomplete fields have been fully received and pads the incomplete fields to build a frame using the undefined content of the memory Interlacer While producing an interlaced output field the Interlacer MegaCore function alternates between propagating and discarding a row from the input port Consequently the output port is inactive every other row The delay from input to output is a few clock cycles when pixels are propagated Error Recovery The Interlacer MegaCore function discards extra data when the endofpacket signal is received later than expected When an early endofpacket signal is received the current output field is
80. reset when rst is asserted high The rst In reset must be de asserted synchronously with respect to the rising edge of the is clk signal vid clk In Clocked video clock All the video input signals are synchronous to this clock s eee In control slave port Avalon MM address bus Specifies a word offset into the slave address space 1 In control slave port Avalon MM read signal When this signal is asserted the control port drives new data onto the read data bus 7 Out control Slave port Avalon MM readdata bus These output lines are used for read transfers 7 ee eer Out control Slave port Avalon MM waitrequest bus When this signal is asserted the control port cannot accept new transactions 7 E lh control slave port Avalon MM write signal When this signal is asserted the control port accepts new data from the write data bus 7 eee in control slave port Avalon MM writedata bus These input lines are used for z write transfers 1 In Clock signal for Avalon ST ports dout and control The MegaCore function x operates the rising edge of the is_clk signal TERN In dout port Avalon ST data bus Pixel data is transferred into the MegaCore function over this bus L in dout port Avalon ST endofpacket signal This signal is asserted when the gu downstream device is ending a frame Out dout port Avalon ST ready signal This signal is asserted when the MegaCore dad function is able to receive data FE In dout
81. resulting simulation models are thoroughly simulated and the results verified against bit accurate master simulation models Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 1 About This MegaCore Function Suite 1 7 Performance and Resource Utilization Performance and Resource Utilization This section shows typical expected performance for the Video and Image Processing Suite MegaCore functions with the Quartus II software targeting Cyclone III and Stratix III devices 57 Cyclone devices use combinational look up tables LUTs and logic registers Stratix III devices use combinational adaptive look up tables ALUTs and logic registers Color Space Converter Table 1 4 shows the performance figures for the Color Space Converter Table 1 4 Color Space Converter Performance Memory DSP Blocks Device Family duos Bits M9K 99 18x18 aa Converting 1 080 pixel 10 bit Studio R G B to HDTV Y CbCr using 18 bit coefficients and 27 bit summands Cyclone III 1 517 592 6 237 Stratix IIl 2 430 505 6 350 Converting 1024x768 14 bit Y UV to Computer R G B using 18 bit coefficients and 15 bit summands Cyclone III 1 525 633 6 237 Stratix III 2 421 537 6 329 Converting 640x480 8 bit SDTV Y CbCr to Computer R G B using 9 bit coefficients and 16 bit summands color planes in parallel
82. right by two The coefficient at position m Row where 0 is the top row of the kernel is the integer value via the truncation of n Coefficient N 1 2 filter kernel width m Column where 0 is the far left row of the kernel is the remainder of 1 2 filter kernel width Alpha Blending Mixer Table 7 6 describes the Alpha Blending Mixer MegaCore function control register map July 2010 Altera Corporation Video and Image Processing Suite User Guide 7 4 Chapter 7 Control Register Maps Scaler The width of each register in the Alpha Blending Mixer control register map is 16 bits The control data is read once at the start of each frame and is buffered inside the MegaCore function so the registers may be safely updated during the processing of a frame Table 7 6 Alpha Blending Mixer Control Register Map Address Register s Description Bit 0 of this register is the Go bit all other bits are unused Setting this bit to 0 causes the Alpha 0 Control Blending Mixer MegaCore function to stop the next time control information is read Refer to Avalon MM Slave Interfaces on page 4 17 for full details 1 T Bit 0 of this register is the status bit all other bits are unused Refer to Avalon MM Slave paa Interfaces on page 4 17 for full details 2 Layer 1 X Offset in pixels from the left edge of the background layer to the left edge of layer 1 1 3 Layer 1 Offset in pixels from the top edge of the backg
83. set of eight vertical color bars of 75 intensity white yellow cyan green magenta red blue black Figure 5 24 Color Bar Pattern The sequence runs through the eight possible on off combinations of the three color components of the RGB color space starting with a 75 amplitude white Green is on for the first four bars and off for the last four bars red cycles on and off every two bars and blue cycles on and off every bar The actual numerical values are given in Table 5 25 assuming 8 bits per color samples If the output is requested in a different number of bits per color sample these values are converted by truncation or promotion Table 5 25 Test Pattern Color Values Part 1 of 2 R G B Y ChCr White Grey 180 180 180 180 128 128 Yellow 180 180 16 162 44 142 Cyan 16 180 180 131 156 44 Green 16 180 16 112 72 58 Magenta 180 16 180 84 184 198 Red 180 16 16 65 100 212 Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 59 Test Pattern Generator Table 5 25 Test Pattern Color Values Part 2 of 2 R G B Y ChCr Blue 16 16 180 85 212 114 Black 16 16 16 16 128 128 The choice of a specific resolution and subsampling for the output leads to natural constraints on the test pattern If the format has a horizontal subsampling period of two for the Cb and Cr components
84. starts on For non SDI output this Line active piotre ling can be left at 0 ModeN FO Vertical Rising F0 V rising edge line The line number that the vertical blanking period for field FO begins on ModeN Field Rising F rising edge line The line number that field F1 begins on ModeN Field Falling F falling edge line The line number that field FO begins on ModeN Valid N A Set to enable the mode after the configuration is complete ModeN Ancillary Line Ancillary line Embedded synchronization mode only The line to start inserting ancillary packets ModeN FO Ancillary Line FO ancillary line Embedded synchronization mode only The line in field FO to start inserting ancillary packets Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 51 Clocked Video Output The mode registers can only be written to if a mode is marked as invalid For example the following steps reconfigure mode 1 1 Write 0 to the Model Valid register 2 Write to the mode 1 configuration registers 3 Write 1 to the Model Valid register The mode is now valid and can be selected A currently selected mode can be configured in this way without affecting the video output of the MegaCore function When searching for a matching mode and there are multiple modes that match the resolution the function selects the lowest mode For examp
85. the Gamma Corrector control register map is always equal to the value of the Bits per pixel per color plane parameter selected in the MegaWizard interface Table 7 2 Gamma Corrector Control Register Map Interface 0 Address Register Name Description Bit 0 of this register is the co bit all other bits are unused Setting this bit to 0 causes the Gamma Corrector MegaCore function to stop the next time control 0 information is read Refer to Avalon MM Slave Interfaces page 4 17 for full details Bit 0 of this register is the status bit all other bits are unused Refer to Avalon 1 Status MM Slave Interfaces on page 4 17 for full details 2 to 2 1 where is the number of bits per color plane These registers contain a look up table that is used to apply gamma correction to video data An input intensity value of x is gamma corrected by replacing it with the contents of the x 1 th entry in the look up table Changing the values of these registers has an immediate effect on the behavior of the MegaCore function To ensure that gamma look up values do not change during processing of a video frame use the co bit to stop the MegaCore function while the table is changed Gamma Look Up Table Table 7 3 Gamma orrector Control Register Map Interface 1 Address Register Name Description 0 Unused This register is not used 1 Unused This register is not used 2 to 2 1 where is the
86. the memory space is sufficient Control packets are not stored in memory Input control packets are processed and discarded by the writer component and output control packets are regenerated by the reader component When a frame is dropped by the writer the non image data packets that preceded it are kept and sent with the next frame that is not dropped When a frame is repeated by the reader it is repeated without the packets that preceded it The behavior of the Frame Buffer MegaCore function is not determined by the field dimensions announced in Avalon ST Video control packets and relies exclusively on the startofpacket and endofpacket signals to delimit the frame boundaries The Frame Buffer can consequently handle and propagate mislabelled frames This feature can be used in a system where dropping frame is not an acceptable option The latency introduced during the buffering could provide enough time to correct the invalid control packet Buffering and propagation of image data packets incompatible with preceding control packets is an undesired behavior in most systems Dropping invalid frames is often a convenient and acceptable way of dealing with glitches from the video input and the Frame Buffer can be parameterized to drop all mislabelled fields or frames at compile time Enabling flow controlled frame repetition and turning on this option can guarantee that the reader component keeps on repeating the last valid received frame that is
87. the nearest neighbor method picks the value of the nearest input pixel to i 0 5 Win Wout j 0 5 hs hoy The 0 5 values in this equation come from considering the coordinates of an image array to be on the lines of a 2D grid but the pixels to be equally spaced between the grid lines that is at half values This equation gives an answer relative to the mid point of the input pixel and 0 5 should be subtracted to translate from pixel positions to grid positions However this 0 5 would then be added again so that later truncation performs rounding to the nearest integer Therefore no change is needed The calculation performed by the scaler is equivalent to the following integer calculation O i p F 2 X Win X i Win 2 x Wout 2 x hin x hin 2 x hu Bilinear Algorithm The bilinear algorithm that the scaler uses is higher quality and more expensive than the nearest neighbor algorithm The jaggedness of the nearest neighbor method is smoothed out but at the expense of losing some sharpness on edges July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 14 Chapter 5 Functional Descriptions Scaler Resource Usage The bilinear algorithm uses four multipliers per channel in parallel The size of each multiplier is either the sum of the horizontal and vertical fraction bits plus two or the input data bit width whichever is greater For example with four horizontal fraction bits three vertica
88. triggered state it stalls while it writes to the Avalon MM Slave ports of other MegaCore functions If the slaves do not provide a wait request signal the stall lasts for no more than 50 clock cycles Otherwise the stall is of unknown length La Clipper and scaler use the wait request signal Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 73 Latency Error Recovery The Control Synchronizer MegaCore function processes all packets until an endofpacket signal is received the image width height and interlaced fields of the control data packets are not compared against the following video data packet Any mismatch of the endofpacket signal and the frame size of a video data packet is propagated unchanged to the next MegaCore function Clocked Video Input The stall behavior of the Clocked Video Input MegaCore function is dictated by the incoming video If its output FIFO is empty during horizontal and vertical blanking periods the Clocked Video Input does not output any video data Error Recovery If an overflow is caused by a downstream core failing to receive data at the rate of the incoming video the Clocked Video Input MegaCore function sends an early end of packet and restart sending video data at the start of the next frame or field Clocked Video Output Switch Latency Once its input FIFO is full the stall behavior of the Clocked Video Output MegaCore
89. video streams for the physical properties of display devices For example the brightness displayed by a cathode ray tube monitor has a nonlinear response to the voltage of a video signal You can configure the Gamma Corrector with a look up table that models the nonlinear function to compensate for the non linearity The look up table can then transform the video data and give the best image on the display 2D FIR Filter The 2D FIR Filter MegaCore function performs 2D convolution using matrices of 3x3 5x5 or 7x7 coefficients The 2D FIR Filter retains full precision throughout the calculation while making efficient use of FPGA resources With suitable coefficients the 2D FIR Filter can perform operations such as sharpening smoothing and edge detection You can configure the 2D FIR Filter to change coefficient values at run time with an Avalon MM slave interface 2D Median Filter The 2D Median Filter MegaCore function applies 3x3 or 5x5 pixel median filters to video images Median filtering removes speckle noise and salt and pepper noise while preserving the sharpness of edges in video images Alpha Blending Mixer The Alpha Blending Mixer MegaCore function mixes together up to 12 image layers The Alpha Blending Mixer supports both picture in picture mixing and image blending Each foreground layer can be independently activated and moved at run time using an Avalon MM slave interface Video and Image Processing Suite User Guide July
90. when the output is in the Y CbCr color space the black borders at the left and right are two pixels wide Similarly the top and bottom borders are two pixels wide when the output is vertically subsampled The width and the horizontal subsampling might also have an effect on the width of each color bar When the output is horizontally subsampled the pixel width of each color bar is a multiple of two When the width of the image excluding the left and right borders cannot be exactly divided by eight then the last black bar is larger than the others For example when producing a 640x480 frame in the Y CbCr color space with 4 2 2 subsampling the left and right black borders are two pixels wide each the seven initial color bars 78 pixels wide 640 4 8 truncated down to the nearest multiple of 2 and the final black color bar is 90 pixels wide 640 7x78 4 Generation of Avalon ST Video Control Packets and Run Time Control The Test Pattern Generator MegaCore function outputs a valid Avalon ST Video control packet before each image data packet it generates whether it is a progressive frame or an interlaced field When the output is interlaced the Test Pattern Generator MegaCore function produces a sequence of pairs of field starting with FO if the output is F1 synchronized of with F1 if the output is F0 synchronized When the Avalon Slave run time controller is enabled the resolution of the output can be changed at run time at a f
91. 0 51 52 the output values on channels 0 1 and 2 denoted dout 0 dout 1 and dout_2 are calculated as follows dout 0 AO x din 0 BO x din 1 CO x din 2 50 dout 1 A1 x din 0 x din 1 x din 2 S1 dout 2 A2 x din 0 B2 x din 1 C2 x din 2 S2 where din 0 din 1 and din 2 are inputs read from channels 0 1 and 2 respectively July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 2 Chapter 5 Functional Descriptions Color Space Converter User specified custom constants and the following predefined conversions are supported Computer B G R to CbCrY SDTV CbCrY SDTV to Computer B G R Computer B G R to CbCrY HDTV CbCrY HDTV to Computer B G R Studio B G R to CbCrY SDTV CbCrY SDTV to Studio B G R Studio B G R to CbCrY HDTV CbCrY HDTV to Studio B G R IQY to Computer B G R Computer B G R to IOY UVY to Computer B G R Computer B G R to UVY The values are assigned in the order indicated by the conversion name For example if you select Computer B G R to CbCrY SDTV din 0 din 1 G din 2 dout 0 Cb dout 1 Cr and dout 2 Y If the channels are in sequence din 0 is first then din 1 and din 2 If the channels are in parallel din 0 occupies the least significant bits of the word din 1 the middle bits and din 2 the most significant bits For example if there a
92. 0 contains the aspect ratio code 5 Bar data flags Bits 0 3 contain the bar data flags to insert 6 Bar data value 1 Bits 0 15 contain the bar data value 1 to insert 7 Bar data value 2 Bits 0 15 contain the bar data value 2 to insert When bit 0 is 0 an AFD packet is not present for each image packet When bit 0 is 1 an AFD packet is present for each image packet 8 AFD valid Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 55 Color Plane Sequencer Color Plane Sequencer The Color Plane Sequencer MegaCore function rearranges the color pattern used to transmit Avalon ST Video data packets over an Avalon ST connection stream The Color Plane Sequencer can also split or duplicate a single Avalon ST Video stream into two or conversely combine two input streams into a single stream A color pattern is a matrix that defines a repeating pattern of color samples For full details of the Avalon ST Video protocol refer to Avalon ST Video Protocol on page 4 2 Rearranging Color Patterns The Color Plane Sequencer can rearrange the color pattern of a video data packet in any valid combination of channels in sequence and parallel The Color Plane Sequencer can also drop color planes Avalon ST Video packets of types other than video data packets are forwarded unchanged Figure 5 21 on page 5 55 shows an example that rearranges the color pattern of a video
93. 01 would have a width of 1920 and a height of 540 and a frame of 1920x1080 1080p would have a width of 1920 and a height of 1080 July 2010 Altera Corporation Video and Image Processing Suite User Guide 4 8 Chapter 4 Interfaces Avalon ST Video Protocol When a video data packet uses a subsampled color pattern the individual color planes of the video data packet have different dimensions For example 4 2 2 has one full width full height plane and two half width full height planes For 4 2 0 there are one full width full height plane and two half width half height planes In these cases the width and height fields of the control data packet should be configured for the fully sampled full width and full height plane The function codes the interlacing value to indicate progressive data or which field to expect next and how fields should reconstruct frames The most significant two bits of the interlacing nibble describe whether the next video data packet is either progressive interlaced field 0 f0 containing lines 0 2 4 or interlaced field 1 1 containing lines 1 3 5 00 means progressive 10 means interlaced f0 and 11 means interlaced f1 The meaning of the second two bits is dependent on the first two bits If the first two bits are set to f0 or f1 the second two bits describe the synchronization of interlaced data Use the synchronization bits for progressive segmented frame PsF content where progressive frames
94. 010 Altera Corporation Video and Image Processing Suite User Guide 7 14 Chapter 7 Control Register Maps Control Synchronizer Table 7 18 Test Pattern Generator Control Register Map Part 2 of 2 Address Register s Description 4 The value of the R or Y color sample when the test pattern is a uniform color R Y background 2 5 ales The value of the G or Cb color sample when the test pattern is a uniform color background 2 6 m The value of the B or Cr color sample when the test pattern is a uniform color background 2 Note to Table 7 18 1 Value can be from 32 to the maximum specified in the MegaWizard interface 2 These control registers are only available when the test pattern generator MegaCore function is configured to output a uniform color background and when the run time control interface has been enabled Control Synchronizer The width of each register of the frame reader is 32 bits The control data is read once at the start of each frame The registers may be safely updated during the processing of a frame Table 7 19 describes the Control Synchronizer MegaCore function control register map Table 7 19 Control Synchronizer Control Register Map Part 1 of 2 Address Register s Description Bit 0 of this register is the Go bit Setting this bit to 1 causes the Control Synchronizer 0 Control MegaCore function to start passing through data Bit 1 of the control registe
95. 10 Altera Corporation Chapter 7 Control Register Maps 7 11 Clocked Video Output Table 7 16 Clocked Video Input Control Register Map Part 2 of 2 Address Register Description 7 Total Sample Count The detected sample count of the video streams including blanking 8 FO Total Line Count The detected line count of the video streams FO field including blanking 9 F1 Total Line Count The detected line count of the video streams F1 field including blanking 10 Standard The contents of the vid_std signal Start of frame sample register The sample and sub sample upon which the SOF occurs and the sof signal triggers Sample m Bits 0 1 are the subsample value m Bits 2 15 are the sample value 12 Start of frame line register The line upon which the SOF occurs measured from the rising edge of the FO vertical sync 14 Refclk Divider Number of cycles of vid_clk refclk before refclk_div signal triggers Clocked Video Output Table 7 17 describes the Clocked Video Output MegaCore function control register map The width of each register is 16 bits Table 7 17 Clocked Video Output Control Register Map Part 1 of 3 Address Register Description Bit 0 of this register is the Go bit m Setting this bit to 1 causes the Clocked Video Output MegaCore function to start video data output Refer to Control Port on page 5 46 for full details Bits 3 2 and 1 of the control register ar
96. 2010 Altera Corporation Chapter 1 About This MegaCore Function Suite 1 5 General Description Scaler Clipper The Scaler MegaCore function resizes video streams The Scaler supports nearest neighbor bilinear bicubic and polyphase scaling algorithms You can configure the Scaler to change resolutions or filter coefficients or both at run time using an Avalon MM slave interface The Clipper MegaCore function clips video streams You can configure the Clipper at compile time or optionally at run time using an Avalon MM slave interface Deinterlacer The Deinterlacer MegaCore function converts interlaced video to progressive video using a bob weave or simple motion adaptive algorithm Interlaced video is commonly used in television standards such as phase alternation line PAL and national television system committee NTSC but progressive video is required by LCD displays and is often more useful for subsequent image processing functions Additionally the Deinterlacer can provide double buffering or triple buffering in external RAM Double buffering can help solve throughput problems burstiness in video systems Triple buffering can provide simple frame rate conversion Interlacer The Interlacer MegaCore function converts progressive video to interlaced video by dropping half the lines of incoming progressive frames You can configure the MegaCore function to discard or propagate already interlaced input You can also di
97. 3 Tahle 3 13 Deinterlacer Parameter Settings Part 3 of 3 Parameter Align read write bursts with burst boundaries 3 Value On or Off Description Turn on to avoid initiating read and write bursts at a position that would cause the crossing of a memory row boundary Notes to Table 3 13 1 Either double or triple buffering mode must be selected before you can select the weave or motion adaptive deinterlacing methods 2 These options are available only when you select Motion Adaptive as the deinterlacing method 3 The options to align read write bursts on burst boundaries specify the Avalon MM master ports width and the base address for the frame buffers are available only when you select double or triple buffering 4 5 4 5 6 7 Ni The option to synchronize input and output frame rates is only available when double buffering mode is selected The options to control the buffering of non image data packets are available when you select double or triple buffering You cannot enable both run time control interfaces at the same time This MegaCore function does not support interlaced streams where fields are not of the same size eg for NTSC FO has 244 lines and F1 has 243 lines Altera recommends that you use the clipper MegaCore function to crop the extra line in FO 8 The weave and motion adaptive algorithms stitch together F1 fields with the FO fields that precede rather than follow t
98. 3 The word to write to address 3 on trigger condition 13 Address 4e Address where word 4 should be written on trigger condition 14 Word 4 The word to write to address 4 on trigger condition 15 Address 5 Address where word 5 should be written on trigger condition Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 7 Control Register Maps Switch 1 15 Tahle 7 19 Control Synchronizer Control Register Map Part 2 of 2 Address Register s Description 16 Word 5 The word to write to address 5 on trigger condition 17 Address 6 Address where word 6 should be written on trigger condition 18 Word 6 The word to write to address 6 on trigger condition 19 Address 7 Address where word 7 should be written on trigger condition 20 Word 7 The word to write to address 7 on trigger condition 21 Address 8 Address where word 8 should be written on trigger condition 22 Word 8 The word to write to address 8 on trigger condition 23 Address 9 Address where word 9 should be written on trigger condition 24 Word 9 The word to write to address 9 on trigger condition Switch Table 7 20 Switch Control Register Map Table 7 20 describes the Switch MegaCore function control register map Address Register s Description 0 Control Writing a 1 to bit 0 starts the MegaCore function writing a 0 to bit 0 stops the ci MegaCore function 1 tat Readin
99. 56 58 19 264 Scaling NTSC standard definition 720x480 RGB to high definition 1080p using a bicubic algorithm Cyclone III 1 1 687 1 185 69 444 13 8 8 169 Stratix III 2 1 039 1 050 69 444 14 8 294 Notes to Table 1 10 1 EP3C10F256C6 devices 2 EP3SE50F780C2 devices 3 EP3C40F780C6 devices Clipper Table 1 11 shows the performance figures for the Clipper Table 1 11 Clipper Performance Device Family Combinational Logic Memory DSP Blocks fmax LUTS ALUTs Registers Bits M9K 9x9 18x18 MHz A 1080p60 compatible clipper with a clipping window that has fixed offsets from the size of the input frames Cyclone III 7 649 484 202 Stratix 1 2 475 484 332 A 100x100 pixel clipper with a clipping window that is a rectangle from the input frames Cyclone III 1 416 275 192 Stratix 1 2 323 276 333 A 1080p60 compatible clipper with a runtime interface which uses offsets to set the clipping window Cyclone 111 7 819 619 189 Stratix 1 2 597 620 327 A 100x100 pixel clipper with a run time interface which uses a rectangle to set the clipping window Cyclone 1 560 468 207 Stratix 1 2 449 468 326 Notes to Table 1 11 1 EP3C10F256C6 devic 2 EP3SE50F780C2 devi July 2010 Altera Corporati es ces on Video and Image Processing Suite User Guide 1 12 Chapter 1
100. 6 shows the Frame Buffer parameters Table 3 16 Frame Buffer Parameter Settings Part 1 of 2 Parameter Value Description 32 2600 Maximum image width Default 640 Specify the maximum frame width Specify the maximum frame height In general this value 32 2600 should be set to the full height of a progressive frame Maximum image height Default 480 However it can be set to the height of an interlaced field for double buffering on a field by field basis when the support for interlaced inputs has been turned off Bits per pixel per color plane 4 20 Default 8 Choose the number of bits per pixel per color plane conversion 1 2 Number of color planes in sequence 1 3 Choose the number of color planes in sequence Number of color planes in parallel 1 3 Choose the number of color planes in parallel Frame dropping On or Off Turn on to allow frame dropping Frame repetition On or Off Turn on to allow frame repetition Turn on to drop image data packets whose length is not Drop invalid fields frames On or Off compatible with the dimensions declared in the last control packet Run time control for the writer thread On or Off Turn on to enable run time control for the write interfaces a On or Off Turn on to enable run time control for the read interfaces Support for locked frame rate On or Off Turn on to synchronize the input and output frame rates th
101. 640x480 The frames that follow are progressive with a resolution of 640x480 The frames 15 Bm 480 0000 were deinterlaced using 0 as the last field The frames that follow are progressive with a resolution of 640x480 The frames 15 640 480 0001 were deinterlaced using f1 as the last field The fields that follow are 640 pixels wide and 240 pixels high The next field is 10 1s ony BU 1000 even lines and it is paired with the f1 field that precedes it The fields that follow are 1920 pixels wide and 540 pixels high The next field is f1 15 1920 540 1100 odd lines and it is paired with the fO field that follows it 15 1920 540 1101 The fields that follow are 1920 pixels wide and 540 pixels high The next field is f1 odd lines and it is paired with the fO field that precedes it Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 4 Interfaces 4 9 Avalon ST Video Protocol Table 4 4 Examples of Control Data Packet Parameters Parameters Description Type Width Height Interlacing The fields that follow are 1920 pixels wide and 540 pixels high The next field is 10 15 1920 540 1011 even lines and the stream should be handled as genuine interlaced video material where the fields are all temporally disjoint The fields that follow are 1920 pixels wide and 540 pixels high The next field is 10 15 1920 540 1010 even lines and the stream should be handled
102. 9 128 Setting up Tap 1 for Phase 0 10 0 Setting up Tap 2 for Phase 0 11 0 Setting up Tap 3 for Phase 0 12 0 Commit the writes to Phase 0 8 8 Setting up Tap 0 for Phase 1 9 124 Setting up Tap 1 for Phase 1 10 13 Setting up Tap 2 for Phase 1 11 1 Setting up Tap 3 for Phase 1 12 1 Commit the writes to Phase 1 8 1 Setting up Tap 0 for Phase 7 9 13 Setting up Tap 1 for Phase 7 10 124 Setting up Tap 2 for Phase 7 11 8 Setting up Tap 3 for Phase 7 12 7 Commit the writes to Phase 7 July 2010 Altera Corporation Video and Image Processing Suite User Guide 1 6 Clipper Chapter 7 Control Register Maps Clipper Table 7 9 on page 7 6 describes the Clipper MegaCore function control register map The control data is read once at the start of each frame and is buffered inside the MegaCore function so the registers can be safely updated during the processing of a frame Note that all Clipper registers are write only except at address 1 Table 7 9 Clipper Control Register Map Address Register Description Bit 0 of this register is the Go bit all other bits are unused Setting this bit to 0 causes the 0 Control Clipper MegaCore function to stop the next time control information is read Refer to Avalon MM Slave Interfaces on page 4 17 for full details Bit 0 of this register is the Status bit all other bits are unused The Clipper MegaCore 1 Stat function sets this address to 0 between frames I
103. About This MegaCore Function Suite Performance and Resource Utilization Deinterlacer Table 1 12 shows the performance figures for the Deinterlacer Table 1 12 Deinterlacer Performance Device Family combine oes Logic Memory DSP Blocks fmax UTs ALUTS Registers pur Bits 9 9 18x18 MHz Deinterlacing 64x64 pixel 8 bit R G B frames using the bob algorithm with scanline duplication Cyclone III 1 538 292 1 536 1 189 Stratix 11 2 386 293 1 536 1 325 Deinterlacing with scanline interpolation using the bob algorithm working on 352x288 pixel 12 bit Y CbCr 4 2 2 frames Cyclone Ill 1 673 395 8 448 2 184 Stratix 11 2 492 398 8 448 2 312 Deinterlacing PAL 720x576 with 8 bit Y CbCr 4 4 4 color using the motion adaptive algorithm Cyclone III 3 5 723 5 678 81 514 39 1 121 Stratix 4 4 803 5 772 5 73 292 41 1 243 Deinterlacing HDTV 10801 resolution with 12 bit Y CbCr 4 4 4 color using the weave algorithm Cyclone Ill 1 3 231 2 546 3 078 15 170 Stratix 2 3 539 2 540 3 078 19 280 Notes to Table 1 12 1 EP3C10F256C6 devices 2 EP3SE50F780C2 devices 3 EP3C40F780C6 devices 4 EP3SE110F1152C2 devices Interlacer Table 1 12 shows the performance figures for the Interlacer Table 1 13 Interlacer Performance
104. Avalon ST Video protocol specifies that there are seven packet types reserved for use by users and seven packet types reserved for future use by Altera The data content of all of these packets is undefined However the structure must follow the rule that the packets are split into symbols as defined by the number color plane samples sent in one cycle of the color pattern Unlike control data packets user packets are not restricted to four bits of data per symbol However when a core reduces the bits per pixel per color plane and thus the bit width of the symbols to less than the number of bits in use per symbol data is lost Packet Propagation The Avalon ST Video protocol is optimized for the transfer of video data while still providing a flexible way to transfer control data and other information To make the protocol flexible and extensible the Video and Image Processing MegaCore functions obey the following rules about propagating non video packets m User packets should be propagated until their end of packet signal is received Nevertheless MegaCore functions that buffer packets into external memory might introduce a maximum size due to limited storage space m MegaCore functions can propagate control packets or modify them on the fly MegaCore functions can also cancel a control packet by following it with a corrected packet m When the bits per color sample change from the input to the output side of a block the non video packet
105. Avalon ST endofpacket signal This signal marks the end of an dout endofpacket Out Avalon ST packet _ dout port Avalon ST ready signal This signal is asserted by the dout ready In downstream device when it is able to receive data dout port Avalon ST startofpacket signal This signal marks the start of dout startofpacket Out an Avalon ST packet _ dout port Avalon ST valia signal This signal is asserted when the cout valig Out MegaCore function outputs data Note to Table 6 16 1 These ports are present only if Runtime control of image size is on in the MegaWizard interface Control Synchronizer Table 6 17 shows the input and output signals for the Control Synchronizer MegaCore function Table 6 17 Control Synchronizer Signals Part 1 of 2 Signal Direction Description ise In The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is asserted high reset In The reset must be de asserted synchronously with respect to the rising edge of the clock signal din port Avalon ST data bus Pixel data is transferred into the din_data In MegaCore function over this bus din engofpack t din port Avalon ST endofpacket signal This signal marks the end of an Avalon ST packet din port Avalon ST ready signal This signal indicates when the d d Out fep Mud
106. C9 Color Plane Sequencer 00B3 2D FIR Filter 00DC Interlacer 00 Test Pattern Generator 00B4 2D Median Filter 00D1 Frame Reader 0000 Control Synchronizer 00B5 Alpha Blending Mixer 00C3 Frame Buffer 00 Switch Vendor ID s 6AF7 T For more information about this release refer to the MegaCore IP Library Release Notes and Errata Device Family Support MegaCore functions can provide the types of support for target Altera device families described in Table 1 2 Table 1 2 Altera IP Core Device Support Levels FPGA Device Families HardCopy Device Families Preliminary The core is verified with preliminary timing HardCopy Companion The core is verified with preliminary models for this device family The core meets all timing models for the HardCopy companion device The core functional requirements but might still be undergoing meets all functional requirements but might still be undergoing timing analysis for the device family It can be used in timing analysis for HardCopy device family It can be used in production designs with caution production designs with caution Final The core is verified with final timing models for HardCopy Compilation The core is verified with final timing this device family The core meets all functional and models for the HardCopy device family The core meets all timing requirements for the device family and can be used functional and timing requirements for th
107. Color Plane Sequencer Figure 5 22 shows an example of combining and rearranging two color patterns Figure 5 22 Example of Combining Color Patterns Color pattern of a video data packet on input stream 0 R xX 3 color plane samples in sequence i Color pattern of a video data packet on the output stream 2 color plane samples in parallel and sequence Color pattern of a video data packet on input stream 1 3 color plane samples in parallel Planes unused between the input and output are dropped Splitting Duplicating The Color Plane Sequencer also allows the splitting of a single Avalon ST Video input stream into two Avalon ST Video output streams In this mode of operation the color patterns of video data packets on the output streams can be arranged in a user defined way using any of the color planes of the input color pattern The color planes of the input color pattern are available for use on either both or neither of the outputs This allows for splitting of video data packets duplication of video data packets or a mix of splitting and duplication The output color patterns are independent of each other so the arrangement of one output stream s color pattern places no limitation on the arrangement of the other output stream s color pattern Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 57 Color Plane Sequencer Avalon ST Video packe
108. Color Plane Sequencer MegaCore function stalls for approximately 10 cycles after processing each line of a video frame Between frames the MegaCore function stalls for approximately 30 cycles Error Recovery The Color Plane Sequencer MegaCore function processes video packets per line until an endofpacket signal is received on din0 The line width is taken from the control packets on din0 When an endofpacket signal is received on either din0 or din1 the Color Plane Sequencer ceases output For the number of cycles left to finish the line the MegaCore function continues to drain the inputs that have not indicated end of packet The MegaCore function drains din0 until it receives an endofpacket signal on this port unless it has already indicated end of packet and stalls for up to one line after this endofpacket signal The MegaCore function then signals end of packet on its outputs and continue to drain its inputs that have not indicated end of packet Test Pattern Generator All modes of the Test Pattern Generator stall for a few cycles after a field after a control packet and between lines When producing a line of image data the Test Pattern Generator outputs one sample on every clock cycle but it can be stalled without consequences if other functions down the data path are not ready and exert backpressure Control Synchronizer The Control Synchronizer stalls for several cycles between packets When the Control Synchronizer enters a
109. Cyclone 111 1 574 818 9 238 Stratix III 2 469 665 9 394 Converting 720x576 8 bit Computer R G B to Y UV using 9 bit coefficients and 8 bit summands Cyclone III 1 394 427 3 238 Stratix III 2 337 376 3 395 Notes to Table 1 4 1 EP3C10F256C6 devices 2 EP3SE50F780C2 devices Chroma Resampler Table 1 5 shows the performance figures for the Chroma Resampler Table 1 5 Chroma Resampler Performance Part 1 of 2 Device Famil Combinational Logic Memory DSP Blocks fun Upsampling from 4 2 0 to 4 4 4 with a parallel data interface and run time control of resolutions up to extended graphics array format XGA 1024x768 This parameterization uses luma adaptive filtering on the horizontal resampling and nearest neighbor on the vertical resampling Cyclone III 1 2 262 1 771 16 384 4 158 Stratix 2 1 559 1 769 16 384 4 261 July 2010 Altera Corporation Video and Image Processing Suite User Guide Table 1 5 Chroma Resampler Performance Part 2 of 2 Chapter 1 About This MegaCore Function Suite Performance and Resource Utilization Device Family Combinational Logic Memory DSP Blocks fmax LUTs ALUTs Registers Bits M9K 9x9 18 18 2 Upsamping from 4 2 2 to 4 4 4 with a sequential data interface at quarter common intermediate format QCIF 176x144 using luma adaptive
110. Lear 5 72 Test Pattern Generator ses REA ER ache ERA eR CRECEN CERE ERAN p eae LAXE RETE 5 72 Control Synchronizer e t pea o ha 3 a ir ac ad 5 72 Error Recovery pii ex v UA oh dee bogota Ete vite baa irat be eer 5 73 Clocked Video Input eE nce EN LU Rape ee te 5 73 Error oen di res 5 73 Clocked Video Output iiis cits ket RE REI eee Eee chia eda 5 73 Etror REcovery e o ewe aede clt pe E Vg Ste 5 73 SWATCH 6 ccc oii etn kb hal bees nb Rae ag hae oa Dee Ht EE erp pac ge RS 5 73 Latency o ai E RC Aqu the E 5 73 Chapter 6 Signals Color Space Converter ccs ceca he a e E EE E MUTA Ee e E na e Rn 6 1 Chroma Resampl r i bep E eee EGER E P Pleno eae E piper bade Pe HE Rd etes 6 2 Gamma Corrector dee eed esed ree e desde S e pu ake lacked amp gun Se FO e Rd se pee 6 2 2D FUR Filter deb e d re E UE Vac up 6 3 2D Median FINEN 255 Sesto et 6 4 Alpha Blending Mixer Lope ee ete Hebe PEAT Bik CEE p DE bes Pide d bed teet 6 5 CUM E M RM P E 6 6 eI 6 7 Deinterlacet dee MM C E MN tee EE d ACE du aA m UR TEE 6 8 Interlac
111. Master to Slave Connection Clocked Video Deinterlacer Scaler Clocked Video Input MegaCore m MegaCore gt MegaCore m Output MegaCore Function Function Function Function Nios Il Processor The Clocked Video MegaCore functions in Figure 4 1 also have external interfaces that support clocked video standards These MegaCore functions can connect between the function s Avalon ST interfaces and functions using clocked video standards such as BT 656 July 2010 Altera Corporation Video and Image Processing Suite User Guide 4 2 Chapter 4 Interfaces Avalon ST Video Protocol Te For information about the supported clocked video interfaces refer to the functional description of the Clocked Video Input on page 5 35 and Clocked Video Output on page 5 43 Avalon ST Video Protocol The MegaCore functions in the Video and Image Processing Suite use the Avalon ST Video protocol The Avalon ST Video protocol is a packet oriented way to send video and control data over Avalon ST connections Using the Avalon ST Video protocol allows the construction of image processing data paths which automatically configure to changes in the format of the video being processed This minimizes the external control logic required to configure a video system Packets The packets of the Avalon ST Video protocol are split into symbols where each symbol represents a single piece of data see the Avalon Interface
112. Move binary point right 2 16 to 16 Default 0 Specify the number of places to move the binary point Remove fraction bits by Round values Half up Round values Half even Truncate values to integer Choose the method of discarding fraction bits resulting from the calculation Convert from signed to unsigned by Saturating to minimum value at stage 4 Replacing negative with absolute value Choose the method of signed to unsigned conversion for the results Notes to Table 3 1 1 When Guard bands are on the MegaCore function never receives or sends data outside of the range specified by Min and Max 2 You can specify a higher precision output by increasing Bits per pixel per color plane and Move binary point right Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 3 Parameter Settings Color Space Converter CSC 3 3 Table 3 2 Color Space Converter Parameter Settings Tab Operands Page Parameter Color model conversion 1 Value Computer B G R to CbCrY SDTV CbCrY SDTV to Computer B G R Computer B G R to CbCrY HDTV CbCrY HDTV to Computer B G R Studio B G R to CbCrY SDTV CbCrY SDTV to Studio B G R Studio B G R to CbCrY HDTV CbCrY HDTV to Studio B G R IQY to Computer B G R Computer B G R to IQY UVY to Computer B G R Computer B G R to UVY Description
113. P Blocks hu UTs ALUTs Registers Bits M9K 9x9 18 18 MHz 2 input 2 output switch with alpha channels disabled and doing three colors in sequence Cyclone III 122 127 0 0 0 0 306 Stratix IIl 79 128 0 0 0 0 538 12 input 12 output switch with alpha channels enabled and doing three colors in parallel Cyclone III 6151 2547 0 0 0 0 150 Stratix 111 5082 2657 0 0 0 0 274 Video and Image Processing Suite User Guide July 2010 Altera Corporation N DTE RYN 2 Getting Started with Altera IP Cores This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core The Altera IP library is installed as part of the Quartus II installation process You can select and parameterize any Altera IP core from the library Altera provides an integrated MegaWizard GUI that allows you to customize IP cores to support a wide variety of applications The MegaWizard interface guides you through the setting of parameter values and selection of optional ports The following sections describe the general installation design flow evaluation and production use of Altera IP cores Installation and Licensing The Altera IP Library is distributed with the Quartus II software and downloadable from the Altera website www altera com Figure 2 1 shows the directory structure after you install an Altera IP core where path is the installation directory The default installation directo
114. Plane Sequencer can process streams of pixel data of the types shown in Table 5 24 Table 5 24 Color Plane Sequencer Avalon ST Video Protocol Parameters Parameter Value Frame Width Read from control packets at run time Frame Height Read from control packets at run time Interlaced Progressive Either Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface Color Pattern The color pattern you select in the MegaWizard interface July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 58 Chapter 5 Functional Descriptions Test Pattern Generator Test Pattern Generator The Test Pattern Generator MegaCore function can be used to produce a video stream compliant with the Avalon ST Video protocol that feeds a video system during its design cycle The Test Pattern Generator MegaCore function produces data on request and consequently permits easier debugging of a video data path without the risks of overflow or misconfiguration associated with the use of the Clocked Video Input MegaCore function or of a custom component using a genuine video input Test Pattern The Test Pattern Generator MegaCore function can generate either a uniform image using a constant color specified by the user at compile time or a set of predefined color bars Both patterns are delimited by a black rectangular border The color bar pattern Figure 5 24 is a still image composed with a
115. SDC file you may see some warning messages in a format as follows m Warning At least one of the filters had some problems and could not be matched m Warning could not be matched with a keeper These warnings are expected because in certain configurations the Quartus II software optimizes unused registers and they no longer remain in your design Active Format Description Inserter The AFD Inserter is an example of how to write a core to handle ancillary packets It is available in the following directory install dir NipNclocked video outputMibNafd example When the output of the AFD Inserter is connected to the input of the Clocked Video Output MegaCore function the AFD Inserter inserts an Avalon ST Video ancillary data packet into the stream after each control packet The AFD Inserter sets the DID and SDID of the ancillary packet to make it an AFD packet DID 0x41 SDID 0x5 The contents of the ancillary packet are controlled by the AFD Inserter register map Refer to the SMPTE 2016 1 2007 standard for a more detailed description of the AFD codes Table 5 23 shows the AFD Inserter register map Table 5 23 AFD Inserter Register Map Address Register Description When bit 0 is 0 the core discards all packets 0 Control When bit 0 is 1 the core passes through all non ancillary packets 1 Reserved 2 Reserved 3 AFD Bits 0 3 contain the active format description code 4 AR Bit
116. SDI Clocked Clocked SDI RX Video Video gt TX Input Output Underflow Moving between flow controlled Avalon ST Video and clocked video can cause problems if the flow controlled video does not provide data at a rate fast enough to satisfy the demands of the outgoing clocked video The Clocked Video Output MegaCore function contains a FIFO that when set to a large enough value can accommodate any burstiness in the flow data as long as the output rate of the downstream Avalon ST Video components is equal to or higher than that of the outgoing clocked video If this is not the case the FIFO underflows If underflow occurs the MegaCore function continues to output video and re syncs the startofpacket for the next image packet from the Avalon ST Video interface with the start of the next frame The underflow can be detected by looking at bit 2 of the Status register This bit is sticky and if an underflow occurs stays at 1 until the bit is cleared by writing a 1 to it In addition to the underflow bit the current level of the FIFO can be read from the Used Words register July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 54 Chapter 5 Functional Descriptions Clocked Video Output Timing Constraints To constrain the Clocked Video Output MegaCore function correctly add the following file to your Quartus II project install dir NipNclocked video output MibNalt vip cvo sdc When you apply the
117. Specifications For all packet types on a particular Avalon ST interface the number of symbols sent in parallel that is on one clock cycle and the bit width of all symbols is fixed The symbol bit width and number of symbols sent in parallel defines the structure of the packets The functions predefine the following two types of packet m Video data packets containing only uncompressed video data m Control data packets containing the control data configure the cores for incoming video data packets There are also seven packet types reserved for users and seven packet types reserved for future definition by Altera The packet type is defined by a 4 bit packet type identifier This type identifier is the first value of any packet It is the symbol in the least significant bits of the interface Functions do not use any symbols in parallel with the type identifier assigned X Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 4 Interfaces 4 3 Avalon ST Video Protocol Table 4 1 lists the packet types and Figure 4 2 on page 4 3 shows the structure of a packet Table 4 1 Avalon ST Video Packet Types Type Identifier Description 0 Video data packet 1 8 User packet types 9 12 Reserved for future Altera use 13 Ancillary data packet 14 Reserved for future Altera use 15 Control data packet Figure 4 2 Packet Structure Data of the packet Split into symbols S
118. Specifies a predefined set of coefficients and summands to use for color model conversion at compile time Alternatively you can select Custom and create your own custom set by modifying the din 0 din 1 and din 2 coefficients for dout 0 dout 1 and dout 2 separately The values are assigned in the order indicated by the conversion name For example if you select Computer B G R to CbCrY SDTV then din 0 din 1 G din 2 dout 0 Cb dout 1 Cr and dout 2 Y Custom d On or Off Turn on to enable run time control of the conversion values Each coefficient or summand is represented by a white cell with a 2 purple cell underneath The value in the white cell is the desired value Coefficients and is editable The value in the purple cell is the actual value and determined by the fixed point type specified The purple cells are not gg 12 fixed point values editable You can create a custom coefficient and summand set by m Bi C1 1 specifying one fixed point value for each entry A2 B2 C2 S2 You can paste custom coefficients into the table from a spreadsheet such as Microsoft Excel Blank lines must be left in your input data for the non editable cells Coefficients On or Off Turn on to set the fixed point type used to store the constant Signed 2 coefficients as having a sign bit 0 16 Default 0 Specifies the number of integer bits for the fixed point type used to bit
119. Stall Behavior and Error Recovery Error Recovery On receiving an early endofpacket signal the Scaler stalls its input but continues writing data until it has sent an entire frame If it does not receive an endofpacket signal at the end of a frame the Scaler discards data until the end of packet is found Clipper The Clipper MegaCore function stalls for a few cycles between lines and between frames Its internal latency is less than 10 cycles During the processing of a line it reads continuously but the Clipper only writes when inside the active picture area as defined by the clipping window Error Recovery On receiving an early endofpacket signal the Clipper stalls its input but continues writing data until it has sent an entire frame If it does not receive an endofpacket signal at the end of a frame the Clipper discards data until the end of packet is found Deinterlacer While the bob algorithm with no buffering is producing an output frame it alternates between simultaneously receiving a row on the input port and producing a row of data on the output port and just producing a row of data on the output port without reading any data from the input port The delay from input to output is just a few clock cycles While a field is being discarded input is read at the maximum rate and no output is generated Select the weave algorithm so that the MegaCore function stalls for longer than the usual periods between each output ro
120. Synchronization signals On separate wires Piece Video in and out use the same clock On 2 Midee All modes with Video in and out use the same clock On 3 cycles 3 Not Applicable because the Test Pattern Generator is an Avalon ST Test Pattern Generator Video source only N A Frame Reader Not Applicable because the Frame Reader is a source only N A Switch All modes 2 cycles Control Synchronizer All modes O cycles Notes to Table 5 28 1 It is assumed that the MegaCore function is not being stalled by other functions on the data path the output ready signal is high 2 Add 1 cycle if Allow color planes in sequence input is turned on 3 Minimum latency case when video input and output rates are synchronized Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 15 Latency The latency associated with the initial buffering phase when a MegaCore function first receives video data is not included For example the Deinterlacer MegaCore function in motion adaptive mode initially buffers four fields of video in external memory without outputting data After the initial buffering phase the latency from field input to frame output assuming the output frame rate is the same as the input field rate is one field O lines July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 16 Chapter 5 Functional Descriptions Latency Video and Im
121. The counter is incremented if the frame is not repeated 3 Read only register updated at the end of each frame processed by the reader The counter peat vounter is incremented if the frame is about to be repeated July 2010 Altera Corporation Video and Image Processing Suite User Guide 7 10 Clocked Video Input Table 7 16 describes the Clocked Video Input MegaCore function control register map The width of each register is 16 bits Chapter 7 Control Register Maps Clocked Video Input Table 7 16 Clocked Video Input Control Register Map Part 1 of 2 Address Register Control Description Bit 0 of this register is the Go bit m Setting this bit to 1 causes the Clocked Video Input MegaCore function to start data output on the next video frame boundary Refer to Control Port on page 5 38 for full details Bits 3 2 and 1 of the control register are the interrupt enables m Setting bit 1 to 1 enables the status update interrupt m Setting bit 2 to 1 enables the stable video interrupt m Setting bit 3 to 1 enables the synchronization outputs sof sof_locked refclk div Status Bit 0 of this register is the Status bit m Data is being output by the Clocked Video Input MegaCore function when this bit is asserted Refer to Control Port on page 5 38 for full details Bits 2 and 1 of the status register are not used Bits 6 5 4 and 3 are the resolution valid bits m
122. Video and Image Processing Suite RYAN 101 Innovation Drive San Jose CA 95134 www altera com UG VIPSUITE 10 0 User Guide Document last updated for Altera Complete Design Suite version Document publication date 10 0 July 2010 cy Subscribe Copyright 2010 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo and specific device designations are trademarks and or service marks of Altera Corporation in the U S and other countries All other words and logos identified as trademarks and or service marks are the property of Altera Corporation or their respective owners Altera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the appfication or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services QUALITY 150 9001 2008 NSAI Certified Video and Image Processing
123. When bit 3 is asserted the SampleCount register is valid m When bit 4 is asserted the FOLineCount register is valid m When bit 5 is asserted the SampleCount register is valid m When bit 6 is asserted the F1LineCount register is valid Bit 7 is the interlaced bit m When asserted the input video stream is interlaced Bit 8 is the stable bit m When asserted the input video stream has had a consistent line length for two of the last three lines Bit 9 is the overflow sticky bit m When asserted the input FIFO has overflowed The overflow sticky bit stays asserted until a write of is performed to this bit Bit 10 is the resolution bit m When asserted indicates a valid resolution in the sample and line count registers Interrupt Bits 2 and 1 are the interrupt status bits m When bit 1 is asserted the status update interrupt has triggered m When bit 2 is asserted the stable video interrupt has triggered m The interrupts stay asserted until a write of 1 is performed to these bits Used Words The used words level of the input FIFO Active Sample Count The detected sample count of the video streams excluding blanking F0 Active Line Count The detected line count of the video streams FO field excluding blanking o oy By ow F1 Active Line Count The detected line count of the video streams F1 field excluding blanking Video and Image Processing Suite User Guide July 20
124. Write only master interface FIFO depth 16 1 024 Default 64 Choose the FIFO depth of the write only Avalon MM interface Write only master interface burst target 2 256 Default 32 Choose the burst target for the write only Avalon MM interface Read only master interface FIFO depth 16 1 024 Default 64 Choose the FIFO depth of the read only Avalon MM interface Read only master interface burst target 2 256 Default 32 Choose the burst target for the read only Avalon MM interface Base address of frame buffers 4 Any 32 bit value Default 0x00000000 Hexadecimal address of the frame buffers in external memory Align read write bursts with burst boundaries On or Off Turn on to avoid initiating read and write bursts at a position that would cause the crossing of a memory row boundary Notes to Table 3 16 1 Locked frame rate conversion cannot be turned on until dropping and repeating are allowed 2 4 July 2010 Altera Corporation 2 Locked frame rate conversion cannot be turned on if the run time control interface for the writer component has not been enabled 3 The Maximum packet length option is not available when the Number of packets buffered per frame is set to 0 4 The number of frame buffers and the total memory required at the specified base address is displayed under the base address Video and Image Processing Suite User Guide 3 16
125. a Corporation Chapter 3 Parameter Settings Clocked Video Output Clocked Video Output Table 3 18 shows the Clocked Video Output MegaCore function parameters 3 17 Table 3 18 Clocked Video Output Parameter Settings Part 1 of 2 lines Default 1 080 Parameter Value Description DVI 1080p60 You can choose from a list of preset conversions or use the other fields in Saleetoresetto lead SDI 1080p60 the dialog box to set up custom parameter values If you click Load values SDI 1080160 into controls the dialog box is initialized with values for the selected preset PAL NTSC conversion Image width Active 32 65 536 pixels Default 1 920 Specify the image width by choosing the number of active pixels Image height Active 32 65 536 Specify the image height by choosing the number of active lines Bits per pixel per color plane 4 20 Default 8 Choose the number of bits per pixel per color plane Number of color planes 1 4 Default 3 Choose the number of color planes Color plane transmission format Sequence Parallel Choose whether the color planes are transmitted in sequence or in parallel Allow output of color Choose whether run time switching is allowed between sequential formats such as NTSC and parallel color plane transmission formats such as 1080p The format is controlled by the ModeXControl registers planes in sequence Sor unt See the Avalo
126. a look up values do not change during processing of a video frame use the Go bit in Interface 0 to stop the MegaCore function while the table is changed 2D FIR Filter Table 7 5 describes the control register map for the 2D FIR Filter MegaCore function The width of each register in the 2D FIR Filter control register map is 32 bits The coefficient registers use integer signed 2 s complement numbers To convert from fractional values simply move the binary point right by the number of fractional bits specified in the user interface The control data is read once at the start of each frame and is buffered inside the MegaCore function so the registers can be safely updated during the processing of a frame Table 7 5 2D FIR Filter Control Register Map Address Register Name Description Bit 0 of this register is the Go bit all other bits are unused Setting this bit to 0 causes 0 Control the 2D FIR Filter MegaCore function to stop the next time control information is read Refer to Avalon MM Slave Interfaces on page 4 17 for full details 1 Bit 0 of this register is the Status bit all other bits are unused Refer to Avalon MM Status Slave Interfaces on page 4 17 for full details 2 Coefficient 0 The coefficient at the top left origin of the filter kernel 3 Coefficient 1 The coefficient at the origin across to the right by one 4 Coefficient 2 The coefficient at the origin across to the
127. a packets refer to Ancillary Data Packets on page 4 10 Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 37 Clocked Video Input Separate Synchronization Format The separate synchronization format uses separate signals to indicate the blanking sync and field information For this format the vid datavalid signal behaves slightly differently from in embedded synchronization format The Clocked Video Input MegaCore function only reads vid data when vid datavalidis high as in the embedded synchronization format but it treats each read sample as active picture data Table 5 15 describes the signals and Figure 5 13 shows the timing Table 5 15 Clocked Video Input Signals for Separate Synchronization Format Video Signal Name Description When asserted the video is in an active picture period not horizontal or vertical blanking vid h sync When 1 the video is in a horizontal synchronization period vid v sync When 1 the video is in a vertical synchronization period When 1 the video is interlaced and in field 1 When 0 the video is either progressive or interlaced and in field 0 vid_datavalid vid f Figure 5 13 Separate Synchronization Signals Timing vid data lt vid datavalid vid v sync vid h sync vid f
128. aWizard interface Interlaced Progressive interlaced data is either discarded or propagated without change as selected in the Progressive MegaWizard interface Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface Color Pattern One two or three channels in sequence or in parallel as selected in the MegaWizard interface For example for three channels in sequence where o 3 and y can be any color plane Frame Reader The Frame Reader reads video frames stored in external memory and outputs them using the Avalon ST Video protocol The Frame Reader has an Avalon Memory Mapped Read Master port that reads data from an external memory The Frame Reader has an Avalon ST source on which it streams video data using the Avalon ST Video protocol The Frame Reader also has an Avalon Slave port which provides the MegaCore function with configuration data July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 30 Chapter 5 Functional Descriptions Frame Reader Video frames are stored in external memory as raw video data pixel values only Immediately before the Frame Reader MegaCore function reads video data from external memory it generates a control packet and the header of a video data packet on its Avalon ST source The video data from external memory is then streamed as the payload of the video data packet The content of the control data pa
129. ace MegaWizard Plug In Manager FIR Filter 2D FIR Filter 2D Coefficients Image Format Result to Output Data Type Conversion Procedure 1 Result scaling The results are in the range 0 00 to 251 02 to 2 decimal places The results have B fraction bits Color Plane Configuration T Move binary point right 0 Places Number of color planes in sequence Maximum image width 640 Pixels rInput Data Type 2 Integer conversion The scaled results are in the range 0 00 to 251 02 to 2 decimal places seat The scaled results have 6 fraction bits Data type Unsigned Remove fraction bits by Round values Half up C Guard bands 3 Sign conversion The scaled integer results are in the range 0 to 251 The selected output data type is unsigned Output Data Type Convert from signed to unsigned Saturating to minimum value at stage 4 Bits per pixel per color plane z Data type 4 Range saturation The scaled integer sign handled results are in the range 0 to 251 The selected output data type has a range of Oto 255 The results are within the range of the output data type C Guard bands The following sections describe the parameters for each MegaCore function July 2010 Altera Corporation Video and Image Processing Suite User Guide 3 2 Color Space Converter CSC Table 3 1 and Table 3 2 show the Color Space Conver
130. addata variable Input Read only readdatavalid 1 Input Read only reset 1 Input Read Write optional waitrequest 1 Input Read write address 32 Output Read write burstcount variable Output Read write read 1 Output Read only write 1 Output Write only writedata variable Output Write only The clock and reset signal types are optional The Avalon MM master interfaces can operate on a different clock from the MegaCore function and its other interfaces by selecting the relevant option in the MegaWizard interface when and if it is available Some of the signals in Table 4 11 are read only and not required by a master interface which only performs write transactions Some other signals are write only and not required by a master interface which only performs read transactions To simplify the Avalon MM master interfaces and improve efficiency read only ports are not present in write only masters and write only ports are not present in read only masters July 2010 Altera Corporation Chapter 4 Interfaces 4 21 Buffering of Non Image Data Packets in Memory Read write ports are present in all Avalon MM master interfaces Refer to the description of each MegaCore function for information about whether the master interface is read only write only or read write The Avalon Interface Specifications define a set of transfer properties which may or may not be exhibited by any Avalon MM interface Together with the list of supported
131. addatavalid read master port Avalon MM readdatavalid signal This signal is asserted by the system interconnect fabric when the requested read data has arrived read master av reset read master port reset signal The interface is reset asynchronously when this signal is asserted high and must be de asserted synchronously with respect to the rising edge of the clock signal 1 read master av waitrequest read master port Avalon MM waitrequest signal Asserted by the system interconnect fabric to cause the master port to wait 2 reader control chipselect reader control Slave port Avalon MM chipselect signal The reader control port ignores all other signals unless this signal is asserted 2 reader control av readdata reader control Slave port Avalon MM readdata bus These output lines are used for read transfers 2 reader control av write reader control slave port Avalon MM write signal When this signal is asserted the xeader control port accepts new data from the writedata bus 2 reader control av writedata reader control Slave port Avalon MM writedata bus These input lines are used for write transfers 2 wri Le mas ter av address Out write master port Avalon MM address bus Specifies a byte address in the Avalon MM address space wri Le mas ter av burstcount Out write master port Avalon MM burstcount signal Specifies the number
132. age Processing Suite User Guide July 2010 Altera Corporation JA DTE RA 6 Signals Table 6 1 to Table 6 17 list the input and output signals for the Video and Image Processing Suite MegaCore functions Color Space Converter Table 6 1 shows the input and output signals for the Color Space Converter MegaCore function Table 6 1 Color Space Converter Signals Signal Direction Description The main system clock The MegaCore function operates on the rising edge of the clock In clock signal The MegaCore function is asynchronously reset when reset is asserted high reset In The reset must be de asserted synchronously with respect to the rising edge of the clock signal ETT In din port Avalon ST data bus Pixel data is transferred into the MegaCore mo eara function over this bus din port Avalon ST endofpacket signal This signal marks the end of an Avalon din_endofpacket In ST packet di d Out din port Avalon ST ready signal This signal indicates when the MegaCore PESE function is ready to receive data Mr up ce tot in din port Avalon ST startofpacket signal This signal marks the start of an Avalon ST packet din port Avalon ST valid signal This signal identifies the cycles when the port Seded e should input data dosi Out dout port Avalon ST data bus Pixel data is transferred out of the MegaCore function over this bus 2 dout port Avalon ST endofpacket signal Thi
133. al is asserted by the downstream device when it is able to receive data Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 6 Signals Deinterlacer Table 6 9 Deinterlacer Signals Part 2 of 3 Signal dout_startofpacket Direction Out Description dout port Avalon ST startofpacket signal This signal marks the start of an Avalon ST packet dout_valid Out dout port Avalon ST valid signal This signal is asserted when the MegaCore function outputs data ker writer control address ker writer control slave port Avalon MM address bus Specifies a word offset into the slave address space 6 ker writer control av chipselect ker writer control slave port Avalon MM chipselect signal The ker writer control port ignores all other signals unless this signal is asserted 6 ker writer control av readdata Out ker writer control slave port Avalon MM readdata bus These output lines are used for read transfers 6 ker writer control av waitrequest Out ker writer control slave port Avalon MM waitrequest signal 6 ker writer control av write ker writer control slave port Avalon MM write signal When asserted the ker writer control port accepts new data from the writedata bus 6 ker writer control av writedata ker writer control slave port Avalon MM writedata bus These input lines are u
134. aler Clipper Deinterlacer Interlacer Frame Reader Frame Buffer Clocked Video Input Clocked Video Output Color Plane Sequencer Test Pattern Generator Control Synchronizer Switch New Features This version has the following new features m The new Interlacer MegaCore function converts a stream of progressive video frames into a stream of interlaced video fields by dropping half the lines m TheClocked Video Output and Clocked Video Input MegaCore functions can now insert ancillary packets into and extract ancillary packet from the vertical blanking Active format description AFD ancillary packets contain aspect ratio and protected area information July 2010 Altera Corporation Video and Image Processing Suite User Guide 1 2 Chapter 1 About This MegaCore Function Suite Release Information Release Information Table 1 1 provides information about this release of the Altera Video and Image Processing Suite MegaCore functions Table 1 1 Video and Image Processing Suite Release Information Item Description Version 10 0 All MegaCore functions Release Date July 2010 Ordering Code IPS VIDEO Video and Image Processing Suite 0003 Color Space Converter 00B7 Scaler 00C4 Clocked Video Input 00B1 Chroma Resampler 00C8 Clipper 00C5 Clocked Video Output Product IDs 00B2 Gamma Corrector 00B6 Deinterlacer 00
135. all other signals unless this signal is asserted gamma_lut slave port Avalon MM readdata bus These output lines are gamma lut av readdata Qut used for read transfers In gamma lut slave port Avalon MM write signal When this signal is 3 asserted the gamma 10 port accepts new data from the writedata bus sama 90 n0 n in gamma_lut slave port Avalon MM writedata bus These input lines are used for write transfers 2D FIR Filter Table 6 4 shows the input and output signals for the 2D FIR Filter MegaCore function Table 6 4 2D FIR Filter Signals Part 1 of 2 Signal Direction Description in The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is asserted high reset In The reset must be de asserted synchronously with respect to the rising edge of the clock signal din port Avalon ST data bus Pixel data is transferred into the MegaCore din_data In i function over this bus dinsndotpacket In ao endofpacket signal This signal marks the end of an Avalon July 2010 Altera Corporation Video and Image Processing Suite User Guide Chapter 6 Signals 2D Median Filter Tahle 6 4 2D FIR Filter Signals Part 2 of 2 Signal Direction Description din port Avalon ST reaay signal This signal indicates when the MegaCore din ready
136. aluating an IP Core Evaluating an IP Core The Altera IP library contains both free and individually licenced IP cores With the Altera free OpenCore Plus evaluation feature you can evaluate separately licenced IP cores in the following ways prior to purchasing a production license m Simulate the behavior of an Altera IP core in your system using the Quartus II software and Altera supported VHDL and Verilog HDL simulators m Verify the functionality of your design and evaluate its size and speed quickly and easily m Generate device programming files for designs that include IP cores These files are time limited under the OpenCore Plus evaluation program m Program a device and verify your design in hardware OpenCore Plus Time Out Behavior Design Flows OpenCore Plus hardware evaluation supports the following two operation modes m Untethered the design runs for a limited time m Tethered requires a connection between your board and the host computer If tethered mode is supported by all Altera IP cores in a design the device can operate for a longer time or indefinitely All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one IP core in a design a specific IP core s time out behavior may be masked by the time out behavior of the other IP cores gt For IP cores the untethered time out is 1 hour the tethered time out value is indefinite Your de
137. ame Description Bit 0 of this register is the Go bit all other bits are unused Setting this bit to 0 causes 0 Control the Color Space Converter MegaCore function to stop the next time control information is read Refer to Avalon MM Slave Interfaces on page 4 17 for full details 1 Bit 0 of this register is the status bit all other bits are unused Refer to Avalon MM Slave Interfaces on page 4 17 for full details 2 Coefficient 0 3 Coefficient BO 4 Coefficient C0 5 Coefficient A1 6 Coefficient Bl 1 _ For details refer to Color Space Conversion on page 5 1 8 Coefficient A2 9 Coefficient B2 10 Coefficient C2 11 Summand S0 12 Summand S1 13 Summand S2 July 2010 Altera Corporation Video and Image Processing Suite User Guide 7 2 Chapter 7 Control Register Maps Gamma Corrector Gamma Corrector The Gamma Corrector can have up to three Avalon MM slave interfaces There is a separate slave interface for each channel in parallel Table 7 2 Table 7 3 and Table 7 4 on page 7 2 describe the control register maps for these interfaces The control registers are read continuously during the operation of the MegaCore function so making a change to part of the Gamma look up table during the processing of a frame always has immediate effect To synchronize changes to frame boundaries follow the procedure which is described in Avalon MM Slave Interfaces on page 4 17 The width of each register in
138. ane value within each pixel For example R G B data of eight bits per sample 24 bits per pixel would use eight bits per pixel per color plane La This parameter also defines the bit width of symbols for all packet types on a particular Avalon ST interface An Avalon ST interface must be at least four bits wide to fully support the Avalon ST Video protocol Color Pattern The organization of the color plane samples within a video data packet is referred to as the color pattern This color pattern cannot change within a video data packet A color pattern is represented as a matrix which defines a repeating pattern of color plane samples that make up a pixel or multiple pixels The height of the matrix indicates the number of color plane samples transmitted in parallel the width determines how many cycles of data are transmitted before the pattern repeats Each color plane sample in the color pattern maps to an Avalon ST symbol The mapping is such that color plane samples on the left of the color pattern matrix are the symbols transmitted first Color plane samples on the top are assigned to the symbols occupying the most significant bits of the Avalon ST data signal as shown in Figure 4 3 Figure 4 3 Symbol Transmission Order Symbol transmitted first Y Symbol in most significant bits Symbol transmitted last Symbol in least significant bits L gt The number of color plane samples transmitted in parallel that is
139. artofpacket signal This signal marks the start dout statrtofpacket Out of an Avalon ST packet _ dout port Avalon ST valid signal This signal is asserted when the RU MegaCore function outputs data Note to Table 6 6 1 These ports are present only if Alpha blending is on the MegaWizard interface Note that alpha channel ports are created for layer zero even though no alpha mixing is possible for layer zero the background layer These ports are ignored and can safely be left unconnected or tied to 0 Scaler Table 6 7 shows the input and output signals for the Scaler MegaCore function Table 6 7 Scaler Signals Part 1 of 2 Signal Direction Description a in The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is asserted reset In high The reset must be de asserted synchronously with respect to the rising edge of the clock signal pm 7 control slave port Avalon MM address bus Specifies a word offset into the slave address space 7 mw In control slave port Avalon MM chipselect signal The control port ignores all other signals unless this signal is asserted 7 Out control slave port Avalon MM readdata bus These output lines are used for read transfers 1 control av waitrequest Out control Slave port Avalon MM waitrequest
140. ata position equal to the phase variable described previously Consequently the bicubic coefficients are good for up scaling but not for down scaling If the coefficients are symmetric and provided at compile time then only half the number of phases are stored For N taps and P phases an array C P N of quantized coefficients is symmetric if for all p 1 P 1 and for all t 0 N 1 C p CIP p N 1 t That is phase 1 is phase P 1 with the taps in reverse order phase 2 is phase P 2 reversed and so on The predefined Lanczos and bicubic coefficient sets satisfy this property Selecting Symmetric for a coefficients set on the Coefficients page in the MegaWizard interface forces the coefficients to be symmetric Recommended Parameters In polyphase mode you must choose parameters for the Scaler MegaCore function carefully to get the best image quality Incorrect parameters can cause a decrease in image quality even as the resource usage increases The parameters which have the largest effect are the number of taps and the filter function chosen to provide the coefficients The number of phases and number of bits of precision are less important to the image quality July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 20 Chapter 5 Functional Descriptions Clipper Table 5 7 summarizes some recommended values for parameters when using the Scaler in polyphase mode Table 5 7
141. ation mode only The synchronization length of the Length Hs horizontal synchronization the high period of the sync ae H blanking The horizontal blanking period non active picture portion of a line ModeN Vertical Front V frontborch Separate synchronization mode only The front porch of the vertical Porch synchronization the low period before the synchronization starts ModeN Vertical Sync Separate synchronization mode only The synchronization length of the Length y vertical synchronization the high period of the sync ModeN Vertical Blanking V blank The vertical blanking period non active picture portion of a frame ModeN Active Picture Line Active picture line The line number that the active picture starts on For non SDI output this can be left at 0 ModeN Valid N A Set to enable the mode after the configuration is complete ModeN Ancillary Line Ancillary line Embedded synchronization mode only The line to start inserting ancillary packets Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions Clocked Video Output Figure 5 18 shows how the register values map to the interlaced frame format described in Video Formats on page 5 43 Figure 5 18 Interlaced Frame Parameters Active picture line FO V rising edge line F rising edge line FO ancillary line F falling edge line An
142. before changing output mode and then only enable it again when the status update interrupt has fired indicating that the mode change has occurred The vcoclk div signal can be compared to the refclk_div signal output by a Clocked Video Input MegaCore function using a phase frequency detector PFD that controls a voltage controlled oscillator VCXO By controlling the VCXO the PFD can align its output clock vcoc1k to the reference clock re c1k By tracking changes in the refclk div signal the PFD can then ensure that the output clock is locked to the incoming video clk July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 52 Chapter 5 Functional Descriptions Clocked Video Output The Clocked Video Output MegaCore function can take in the SOF signal from a Clocked Video Input MegaCore function and align its own SOF to this signal The Clocked Video Output SOF signal can be set to any position within the outgoing video frame The registers used to configure the SOF signal are measured from the rising edge of the FO vertical sync A start of frame is indicated by a rising edge on the SOF signal 0 to 1 Figure 5 16 on page 5 45 shows an example configuration Figure 5 19 shows how the Clocked Video Output MegaCore function compares the two SOF signals to determine how far apart they are Figure 5 19 Aligning the Output Video to the Incoming SOF sof vid sof remove lines repeat lines Repeat 3
143. c 0 The Avalon Interface Specifications state that sinks may set ready to logic 0 at any time for example because the sink is a FIFO and it has become full 5 The MegaCore function sets dout valid to logic 0 and stops putting data on the dout data port because the sink is not ready for data The MegaCore function also sets din ready to logic 0 because there is no way to output data and the MegaCore function must stop the source from sending more data before it uses all internal buffer space The sink holds din valid at logic 1 and transmits one more color sample G which is legal because the ready latency of the interface means that the change in the MegaCore function s readiness does not take effect for one clock cycle 6 Both the input and output interfaces transfer no data the MegaCore function is stalled waiting for the sink 7 The sink sets aout ready to logic 1 This could be because space has been cleared in a FIFO 8 The MegaCore function sets dout_valid to logic 1 and resumes transmitting data Now that the flow of data is again unimpeded it sets din ready to logic 1 9 The source responds to din ready by setting din valid to logic 1 and resuming data transfer Example 3 Control Data Transfer Figure 4 14 shows the transfer of a control packet for a field of 720x480i video with field height 240 It is transferred over an interface configured for 10 bit data with two color planes in parallel
144. ce where o P and y can be any color plane When the compatibility mode for subsampled 4 2 2 Y CbCr data is turned on EZET the motion adaptive deinterlacer expects the data as either 4 2 2 parallel data Cb Cr two channels in parallel or 4 2 2 sequential data two channels in sequence o c Interlacer The Interlacer MegaCore function converts progressive video to interlaced video The Interlacer generates an interlaced stream by dropping half the lines of each progressive input frame The Interlacer drops odd and even lines in successive order to produce an alternating sequence of F0 and F1 fields The output field rate is consequently equal to the input frame rate The Interlacer MegaCore function handles changing input resolutions by reading the content of Avalon ST Video control packets The Interlacer supports incoming streams where the height of the progressive input frames is an odd value In such a case the height of the output FO fields are one line higher than the height of the output F1 fields Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 29 Frame Reader S When the input stream is already interlaced the Interlacer either discards the incoming interlaced fields or propagates the fields without modification based on the compile time parameters you specify When Run time control is on you also can deactivate the Interlacer at ru
145. cesses and buffers incoming control packets in memory before propagating them Because both MegaCore functions generate a new updated control packet before outputting an image data packet this difference should be of little consequence as the last control packet always takes precedence L gt Altera recommends that you keep the default values for Number of packets buffered per frame and Maximum packet length unless you intend to extend the Avalon ST Video protocol with custom packets July 2010 Altera Corporation Video and Image Processing Suite User Guide 4 22 Chapter 4 Interfaces Buffering of Non Image Data Packets in Memory Video and Image Processing Suite User Guide July 2010 Altera Corporation AA OTE RYA 5 Functional Descriptions Each Video and Image Processing MegaCore function is implemented to generate hardware that performs its operations on multiple color planes typically three Color Space Converter The Color Space Converter MegaCore function provides a flexible and efficient means to convert image data from one color space to another A color space is a method for precisely specifying the display of color using a three dimensional coordinate system Different color spaces are best for different devices such as R G B red green blue for computer monitors or Y CbCr luminance chrominance for digital television Color space conversion is often necessary when transferring data between devices that use differ
146. chronously with respect to the rising edge of the clock signal bd de dee alpha in N port Avalon ST data bus Pixel data is transferred into M CE the MegaCore function over this bus 1 alpha in N port Avalon ST endofpacket signal This signal marks alpha in N endofpacket the end of an Avalon ST packet 1 alpha in Avalon ST ready signal This signal indicates when alpen Seu out the MegaCore function is ready to receive data 7 alpha in N port Avalon ST startofpacket signal This signal marks n the start of an Avalon ST packet 1 alpha in N port Avalon ST valid signal This signal identifies the alpha tn N valig n cycles when the port should input data 1 alpha out N port Avalon ST data bus Pixel data is transferred out of the MegaCore function over this bus 1 alpha_out_N_endofpacket Out alpha_out_N port Avalon ST endofpacket signal This signal marks the end of an Avalon ST packet 1 July 2010 Altera Corporation Video and Image Processing Suite User Guide 6 22 Table 6 18 Switch Signals Part 2 of 2 Chapter 6 Signals Switch Signal Direction Description alpha out port Avalon ST ready signal This signal is asserted by uc n the downstream device when it is able to receive data 7 alpha out N port Avalon ST startofpacket signal This signal able But N startofpac
147. cillary line FO active picture FO V front porch FO V sync FO V back porch F1 active picture V front porch V sync V back porch H front H back Active samples Porch sync porch H blanking FO active lines FO V blank gt F1 active lines V blanking 4 Active lines July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 50 Chapter 5 Functional Descriptions Clocked Video Output Table 5 22 shows how Figure 5 18 relates to the register map Table 5 22 Interlaced Frame Parameter Descriptions Register Name ModeN Control Parameter N A Description The zeroth bit of this register is the Interlaced bit m Setto 0 for interlaced m Bit 1 of this register is the sequential output control bit only if the Allow output of color planes in sequence compile time parameter is enabled m Setting bit 1 to 1 enables sequential output from the Clocked Video Output such as for NTSC Setting bit 1 to a 0 enables parallel output from the Clocked Video Output such as for 1080p ModeN Sample Count Active samples The width of the active picture region in samples pixels ModeN FO Line Count F0 active lines The height of the active picture region for field FO in lines ModeN F1 Line Count F1 active lines The height of the active picture region for field F1 in lines ModeN Horizontal Front Porch
148. cket is set via the Avalon Slave port This process is repeated for every video frame read from external memory The Frame Reader is configured during compilation to output a fixed number of color planes in parallel and a fixed number of bits per pixel per color plane In terms of Avalon ST Video these parameters describe the structure of one cycle of a color pattern also known as the single cycle color pattern The Frame Reader is also configured with the number of channels in sequence this parameter does not contribute to the definition of the single cycle color pattern To configure the Frame Reader to read a frame from memory the Frame Reader must know how many single cycle color patterns make up the frame If each single cycle color pattern represents a pixel then the quantity is simply the number of pixels in the frame Otherwise the quantity is the number of pixels in the frame multiplied by the number of single cycle color patterns required to represent a pixel You must also specify the number of words the Frame Reader must read from memory The width of the word is the same as the Avalon MM read Master port width parameter This width is configured during compilation Each word can only contain whole single cycle color patterns The words cannot contain partial single cycle color patterns Any bits of the word that cannot fit another whole single cycle color pattern are not used Also the Frame Reader must be configured with t
149. cket signal is received too early or too late for the compile time configured frame size In either case the 2D FIR Filter always creates output video packets of the configured size If an input video packet has a late endofpacket signal then the extra data is discarded If an input video packet has an early endofpacket signal the video frame is padded with an undefined combination of the last input pixels Alpha Blending Mixer All modes at the Alpha Blending Mixer stall for a few cycles after each output frame and between output lines Between frames the Alpha Blending Mixer is processing non image data packets from its input layers in sequential order and may exert backpressure during the process until the image data header has been received for all its input During the mixing of a frame the Alpha Blending Mixer reads from the background input for each non stalled cycle The Alpha Blending Mixer also reads from the input ports associated with layers that currently cover the background image Because of pipelining the foreground pixel of layer N is read approximately N active cycles after the corresponding background pixel has been read If the output is applying backpressure or if one input is stalling the pipeline stalls and the backpressure propagates to all active inputs When alpha blending is enabled one data sample is read from each alpha port once each time that a whole pixel of data is read from the corresponding input port
150. coming video is detected as stable has a consistent sample length in two of the last three lines or unstable if for example the video cable is removed The incoming video is always detected as unstable when the vid locked signal is low Both interrupts can be independently enabled using bits 2 1 of the Cont rol register Their values can be read using bits 2 1 of the Interrupt register and a write of 1 to either of those bits clears the respective interrupt Generator Lock Generator lock Genlock is the technique for locking the timing of video outputs to a reference source Sources that are locked to the same reference can be switched between cleanly on a frame boundary The Genlock functionality is enabled using the Control register The Clocked Video Input MegaCore function provides some functions to facilitate Genlock The MegaCore function can be configured to output via the refclk div signal a divided down version of its vid clk refclk aligned to the start of frame SOF By setting the divide down value to the length in samples of a video line the refclk div signal can be configured to output a horizontal reference which a phase locked loop PLL can align its output clock to By tracking changes in the refclk div signal the PLL can then ensure that its output clock is locked to the incoming video clock Figure 5 14 shows an example configuration Figure 5 14 Genlock Example Configuration
151. cs and field information via their own signals A sample is output for each clock cycle on the vid data bus The vid datavalid signal is used to indicate when the vid data video output is in an active picture period of the frame Table 5 20 describes five extra signals for separate synchronization formats Table 5 20 Clocked Video Output Signals for Separate Synchronization Format Video Signal Name Description vid h sync 1 during the horizontal synchronization period vid v sync 1 during the vertical synchronization period When interlaced data is output this is a 1 when F1 is being output and a 0 vid_t when FO is being output During progressive data it is always 0 vid_h 1 during the horizontal blanking period vid_v 1 during the vertical blanking period Control Port If you turn on Use control port in the MegaWizard interface for the Clocked Video Output it can be controlled using the Avalon MM slave control port Initially the MegaCore function is disabled and does not output any video However it still accepts data on the Avalon ST Video interface for as long as it has space in its input FIFO The sequence for starting the output of the MegaCore function is as follows 1 Write a 1 to Control register bit 0 2 Read Status register bit 0 When this is a 1 the function outputs video The sequence for stopping the output of the MegaCore function is as follows 1 Write a 0 to Control register bit 0
152. ctor register map Table 5 19 AFD Extractor Register Map Part 1 of 2 Address Register Description When bit 0 is 0 the core discards all packets 0 Control When bit 0 is 1 the core passes through all non ancillary packets 1 Reserved When bit 1 is 1 a change to the AFD data has been 2 Interrupt detected and the interrupt has been set Writing a 1 to bit 1 clears the interrupt 3 AFD Bits 0 3 contain the active format description code 4 AR Bit 0 contains the aspect ratio code When AFD is 0000 or 0100 bits 0 3 describe the contents of bar data value 1 and bar data value 2 When AFD is 0011 bar data value 1 is the pixel number end of the left bar and bar data value 2 is the pixel 3 Bar data flags number start of the right bar When AFD is 1100 bar data value 1 is the line number end of top bar and bar data value 2 is the line number start of bottom bar 6 Bar data value 1 Bits 0 15 contain bar data value 1 Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 43 Clocked Video Output Tahle 5 19 AFD Extractor Register Map Part 2 of 2 Address Register Description 7 Bar data value 2 Bits 0 15 contain bar data value 2 When bit 0 is 0 an AFD packet is not present for each image packet When bit 0 is 1 an AFD packet is present for each image packet 8 AFD valid Clocked Video Output The Clock
153. d order in the MegaWizard interface The sequence for stopping the output of the MegaCore function is as follows 1 Write a 0 to Control register bit 0 2 Read Status register bit 0 When this is a 0 the MegaCore function has stopped data output This occurs on the next end of frame or field that matches the setting of the Field order in the MegaWizard interface The starting and stopping of the MegaCore function is synchronized to a frame or field boundary Table 5 16 shows the output of the MegaCore function with the different Field order settings Table 5 16 Synchronization Settings Video Format Field Order Output Interlaced F1 first Start F1 FO F1 FO Stop Interlaced FO first Start FO F1 F1 Stop Interlaced Any field first Start FO or F1 FO or F1 Stop Progressive F1 first No output Progressive FO first Start FO FO FO Stop Progressive Any field first Start FO FO FO Stop Format Detection The Clocked Video Input MegaCore function detects the format of the incoming clocked video and uses it to create the Avalon ST Video control packet It also provides this information in a set of registers The MegaCore function can detect the following different aspects of the incoming video stream m Picture width in samples The MegaCore function counts the total number of samples per line and the number of samples in the active picture per
154. d to process the IP core in the Quartus II Compiler and a simulation directory which includes files for simulation 9 If you are working in a Quartus II project you are prompted to add the Quartus II IP File qip to the current Quartus II project You can also turn on Automatically add Quartus II IP Files to all projects You can now integrate your custom IP core instance in your design simulate and compile While integrating your IP core instance into your design you must make appropriate pin assignments You can create virtual pin to avoid making specific pin assignments for top level signals while you are simulating and not ready to map the design to hardware a For information about the Quartus II software including virtual pins and the MegaWizard Plug In Manager refer to Quartus II Help Simulate the Design You can simulate your IP core variation with the functional simulation model and the Verilog HDL or VHDL testbench or example design generated with your IP core if any The functional simulation model and testbench files are generated in your project directory or a designated directory The directory may also include scripts to compile and run the testbench For a complete list of models or libraries required to simulate your IP core refer to the scripts provided with the testbench Ta For more information about simulating Altera IP cores refer to Simulating Altera IP in Third Party Simulation Tools and Simulating Design
155. data Cyclone Ill 1 226 137 2 064 1 229 Stratix 111 2 160 137 2 064 1 383 Gamma correcting 64x64 three color 8 bit data Cyclone Ill 1 226 137 2 064 1 229 Stratix 111 2 160 137 2 064 1 383 Notes to Table 1 6 1 EP3C10F256C6 devices 2 EP3SE50F780C2 devices Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 1 About This MegaCore Function Suite 1 9 Performance and Resource Utilization 2D FIR Filter Table 1 7 on page 1 9 shows the performance figures for the 2D FIR Filter Table 1 7 2DFIR Filter Performance Device Family Combinational Logic Memory DSP Blocks hu LUTS ALUTs Registers Bits M9K 99 18 18 MHz Edge detecting 3x3 asymmetric filter working on 352x288 8 bit R G B using 3 bit coefficients Cyclone III 1 965 987 16 896 4 9 190 Stratix 2 750 830 16 896 4 9 349 Smoothing 3x3 symmetric filter working on 640x480 8 bit R G B using 9 bit coefficients Cyclone III 1 981 960 30 720 4 6 195 Stratix 2 761 909 30 720 4 4 354 Sharpening 5x5 symmetric filter working on 640x480 in 8 bit R G B using 9 bit coefficients Cyclone III 1 1 858 1 791 61 440 8 12 183 Stratix 2 1 398 1 598 61 440 8 8 295 Smoothing 7x7 symmetric filter working on 1 280x720 in 10
156. ddress 0 Control Register Description Bit 0 of this register is the co bit all other bits are unused Setting this bit to 0 causes the Deinterlacer MegaCore function to stop before control information is read and before outputting a frame While stopped the Deinterlacer may continue to receive and drop frames at its input if triple buffering is enabled Refer to Avalon MM Slave Interfaces on page 4 17 for full details 1 Status Bit 0 of this register is the Status bit all other bits are unused Refer to Avalon MM Slave Interfaces on page 4 17 for full details Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 7 Control Register Maps Interlacer Table 7 10 Deinterlacer Control Register Map for Run Time Control of the Motion Adaptive Algorithm Part 2 of 2 Address Register Description i Write only register Bit 0 of this register should be set to 1 to override the per pixel 2 i Wm motion value computed by the deinterlacing algorithm with a user specified value This i Rd register cannot be read dendi Write only register The 16 bit value that overrides the motion value computed by the 3 D deinterlacing algorithm This value can vary between 0 weaving to 65535 bobbing TM UE The register cannot be read Table 7 10 describes the control register map that synchronizes the input and output frame rates The control data is read
157. de for Progressive Frames 0 66 0c cee eee ee 5 25 Frame Buffermne codes deutet diseases le di Ms ee RR eoe ERROR tne Le ish 5 25 Frame Rate ConvetsiOn de Hi ne PH n HC HI Ee e d e ed 5 26 Behavior When Unexpected Fields are Received 00 00 5 27 Handling of Avalon ST Video Control Packets 00000 0000 5 27 NO m 5 28 Frame Reader reste EE eb e Lee terea e pet deca ddd lici enn lic ente e tr e ied 5 29 Frame Bultei erys terr m 5 32 Locked Frame Rate Conversion 000 nee ene eens 5 33 Interlaced Video Streams niepo aae eed tag a a lola ol E ees 5 34 Handling of Avalon ST Video Control Packets nunana nanan eee eens 5 34 Clocked Video IBDUE emus sett heut keee ner ee eE Hse e NE E a e E eats 5 35 July 2010 Altera Corporation Video and Image Processing Suite User Guide vi Contents Video ENG PUE E PER d eR dea dde VE e Trad 5 35 Embedded Synchronization Format 0000 5 35 Separate Synchronization Format 0 ees 5 37 Video locked Signal 5 37 Control e ao fee ortu b v ue yt Se eet dre ab le due tate Wk Msc a tank cosa tg 5 38 Format Detection iiu RR ER ReEx bi 0 See EG RA E RA Ce Re a Sew E 5 38 I nterrupts 352 vous pote uoo eet pate edd aves eau f
158. e O Y CbCr O For both upsampling and downsampling the vertical resampling algorithm is fixed at nearest neighbor Vertical resampling does not use any multipliers For upsampling it uses four line buffers each buffer being half the width of the image For downsampling it uses one line buffer which is half the width of the image 57 Allinput data samples must be in unsigned format If the number of bits per pixel per color plane is N this means that each sample consists of N bits of data which are interpreted as an unsigned binary number in the range 0 2 1 All output data samples are also in the same unsigned format For more information about how non video packets are transferred refer to Packet Propagation on page 4 11 Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions Gamma Corrector 5 7 The Chroma Resampler MegaCore function can process streams of pixel data of the types shown in Table 5 2 Table 5 2 Chroma Resampler Avalon ST Video Protocol Parameters Parameter Frame Width Value Maximum frame width is specified in the MegaWizard interface the actual value is read from control packets Frame Height Maximum frame height is specified in the MegaWizard interface the actual value is read from control packets Interlaced Progressive Progressive Bits per Color Sample Numb
159. e Deinterlacer MegaCore function also allows frame buffering in external RAM which you can configure at compile time When using either of the two bob algorithm subtypes you can select no buffering double buffering or triple buffering The weave and motion adaptive algorithms require some external frame buffering and in those cases only select double buffering or triple buffering When you chose no buffering input pixels flow into the Deinterlacer through its input port and after some delay calculated output pixels flow out through the output port When you select double buffering external RAM uses two frame buffers Input pixels flow through the input port and into one buffer while pixels are read from the other buffer processed and output When both the input and output sides have finished processing a frame the buffers swap roles so that the frame that the output can use the frame that you have just input You can overwrite the frame that the function uses to create the output with a fresh input The motion adaptive algorithm uses four fields to build a progressive output frame and the output side has to read pixels from two frame buffers rather than one Consequently the motion adaptive algorithm actually uses three frame buffers in external RAM when you select double buffering When the input and output sides finish processing a frame the output side exchanges its buffer containing the oldest frame frame n 2 with the frame it recei
160. e device family and in production designs can be used in production designs Table 1 3 shows the level of support offered by the Video and Image Processing Suite MegaCore functions to each Altera device family Table 1 3 Device Family Support Part 1 of 2 Device Family Support Arria GX Final Arria Il GX Preliminary Cyclone Final Cyclone III Final Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 1 About This MegaCore Function Suite Features Features Table 1 3 Device Family Support Part 2 of 2 Device Family Support Cyclone III LS Preliminary Cyclone IV Preliminary HardCopy II HardCopy Compilation HardCopy III HardCopy Companion HardCopy IV HardCopy Companion Stratix Final Stratix Il Final Stratix III Final Stratix IV Final Stratix IV GT Preliminary Stratix V Preliminary Other device families No support The following features are common to all of the Video and Image Processing Suite MegaCore functions m Common Avalon Streaming Avalon ST interface and Avalon ST Video protocol m Avalon Memory Mapped Avalon MM interfaces for run time control input and connections to external memory blocks m Easy to use MegaWizard interface for parameterization and hardware generation m IP functional simulation models for use in Altera supported VHDL and Verilog HDL simulators m Support for
161. e function converts interlaced video to progressive video using bob weave or motion adaptive methods In addition the Deinterlacer can provide double or triple buffering in external RAM Buffering is required by the motion adaptive and weave methods and can be selected if desired when using a bob method You can configure the Deinterlacer to produce one output frame for each input field or to produce one output frame for each input frame a pair of two fields For example if the input video stream is NTSC video with 60 interlaced fields per second the former configuration outputs 60 frames per second but the latter outputs 30 frames per second Producing one output frame for each input field should give smoother motion but may also introduce visual artefacts on scrolling text or slow moving objects when using the bob or motion adaptive algorithm When you select a frame buffering mode the Deinterlacer output is calculated in terms of the current field and possibly some preceding fields For example the bob algorithm uses the current field whereas the weave algorithm uses both the current field and the one which was received immediately before it When producing one output frame for every input field each field in the input frame takes a turn at being the current field However if one output frame is generated for each pair of interlaced fields then the current field moves two fields through the input stream for each output frame This m
162. e function does not use all other bits A few cycles after the function comes out of reset it writes a zero in the Go bit remember that all registers in Avalon MM control slaves power up in an undefined state Although there are a few exceptions most Video and Image Processing Suite MegaCore functions stop at the beginning of an image data packet if the Go bit is set to 0 This allows you to stop the MegaCore function and to program run time control data before the processing of the image data begins A few cycles after the Go bit is set by external logic connected to the control port the MegaCore function begins processing image data If the Go bit is unset while data is being processed then the MegaCore function stops processing data again at the beginning of the next image data packet and waits until the Go bit is set by external logic July 2010 Altera Corporation Video and Image Processing Suite User Guide 4 18 Chapter 4 Interfaces Avalon MM Slave Interfaces m Register 1 is the Status register Bit zero of this register is the Status bit the function does not use all other bits The function sets the Status bit to 1 when it is running and zero otherwise External logic attached to the control port should not attempt to write to the Status register The following pseudo code illustrates the design of functions that double buffer their control that is all MegaCore functions except the Gamma Corrector the Alpha Blending Mixer and s
163. e horizontal Blanking blanking period in samples 12 odel Vertical Front Video mode 1 vertical front porch Specifies the length of the vertical front porch Porch in lines 13 odel Vertical Sync Video mode 1 vertical synchronization length Specifies the length of the vertical Length synchronization length in lines 14 ae geet canton Video mode 1 vertical blanking period Specifies the length of the vertical e Meme cae o anxing blanking period in lines 15 odel F0 Vertical Front Video mode 1 field 0 vertical front porch interlaced video only Specifies the Porch length of the vertical front porch in lines 16 odel FO Vertical Sync Video mode 1 field 0 vertical synchronization length interlaced video only Length Specifies the length of the vertical synchronization length in lines 17 odel F0 Vertical Video mode 1 field O vertical blanking period interlaced video only Specifies Blanking the length of the vertical blanking period in lines 18 odel Active Picture Video mode 1 active picture line Specifies the line number given to the first line Line of active picture 19 odel F0 Vertical Video mode 1 field O vertical blanking rising edge Specifies the line number Rising given to the start of field 0 s vertical blanking I Video mode 1 field rising edge Specifies the line number given to the end of 9 gael Field Bising Field 0 and the start of Field 1 Video mode 1 field falling edge Specifies the line number given to the end of 2 D
164. e passed through without modification In all parameterizations the Deinterlacer MegaCore function generates a new and updated control packet just before the processed image data packet This packet contains the correct frame height and the proper interlace flag so that the following image data packet is interpreted correctly by following MegaCore functions The Deinterlacer uses 0010 and 0011 to encode interlacing values into the Avalon ST Video packets it generates These flags mark the output as being progressive and record information about the deinterlacing process Refer to Table 4 4 on page 4 8 The interlacing is encoded as 0000 when the Deinterlacer is passing a progressive frame through The Deinterlacer MegaCore function can process streams of pixel data of the types shown in Table 5 10 Table 5 10 Deinterlacer Avalon ST Video Protocol Parameters Parameter Value Frame Width Run time controlled Maximum value specified in the MegaWizard interface Frame Height Run time controlled Maximum value specified in the MegaWizard interface Interlaced E Progressive Interlaced input Progressive output plus optional passthrough mode for progressive input Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface Color Pattern One two or three channels in sequence or in parallel as selected in the MegaWizard interface For example for three channels in sequen
165. e specified in the MegaWizard interface Interlaced Progressive Consequently external logic is required to synchronize the input fields and prevent the mixing Progressive Interlaced input streams are accepted but they are treated as progressive inputs of FO fields with F1 fields Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface specified separately for image data and alpha blending Color Pattern din and dout One two or three channels in sequence or in parallel as selected in the MegaWizard interface For example if three channels in sequence is selected where B and y can be any color plane Color Pattern alpha in A single color plane representing the alpha value for each pixel Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 13 Scaler Scaler The Scaler MegaCore function provides a means to resize video streams It supports nearest neighbor bilinear bicubic and polyphase scaling algorithms The Scaler MegaCore function can be configured to change the input resolution using control packets It can also be configured to change the output resolution and or filter coefficients at run time using an Avalon MM Slave interface For information about using Avalon MM slave interfaces for run time control in the Video and Image Processing Suite refer to Avalon MM
166. e the interrupt enables m Setting bit 1 to 1 enables the status update interrupt m Setting bit 2 to 1 enables the locked interrupt m Setting bit 3 to 1 enables the synchronization outputs vid sof vid sof locked vcoclk div m When bit 3 is set to 1 setting bit 4 to 1 enables frame locking The Clock Video Output attempts to align its vid sof signal to the sof signal from the Clocked Video Input MegaCore function 0 Control Bit 0 of this register is the Status bit m Data is being output by the Clocked Video Output MegaCore function when this bit is asserted Refer to Control Port on page 5 46 for full details Bit 1 of the Status register is unused Bit 2 is the underflow sticky bit m When bit 2 is asserted the output FIFO has underflowed The underflow sticky bit stays asserted until a 1 is written to this bit Bit 3 is the frame locked bit m When bit 3 is asserted the Clocked Video Output has aligned its start of frame to the incoming sof signal 1 Status July 2010 Altera Corporation Video and Image Processing Suite User Guide 7 12 Chapter 7 Control Register Maps Clocked Video Output Table 7 17 Clocked Video Output Control Register Map Part 2 of 3 Address Register Description Bits 2 and 1 are the interrupt status bits m When bit 1 is asserted the status update interrupt has triggered
167. ead Address data processing 8 to 74N mos mon Specifies values for the horizontal coefficients at a particular phase Write dE these values first then the Horizontal Phase to commit the write Specifies which phase the Horizontal Tap Data applies to Writing to BiN oroe dn this location commits the writing of tap data This write must be made h D MALAE even if the phase value does not change between successive sets of tap data OMS fi ical coeffici icular phase Wri BM Vertical Tap Data Specifies values for the vertical coefficients at a particular phase rite ioo these values first then the vertical Phase to commit the write 2 V Specifies which phase the vertical Tap Data applies to Writing to this location commits the writing of tap data This write must be made 9 M Vertical Phase even if the phase value does not change between successive sets of tap data 2 Note to Table 7 7 1 Value can be from 32 to the maximum specified in the MegaWizard interface 2 If Share horizontal vertical coefficients is selected in the MegaWizard interface this location is not used Table 7 8 shows an example of the sequence of writes to the horizontal coefficient data for an instance of the Scaler MegaCore function with four taps and eight phases Table 7 8 Example of Using the Scaler Control Registers Address Value Purpose 8 0 Setting up Tap 0 for Phase 0
168. eans that the current field is either always a FO field defined as a field which contains the top line of the frame or always a F1 field The Deinterlacer MegaCore function does not currently use the two synchronization bits of the interlace nibble Refer to Control Data Packets on page 4 7 When input frame rate output frame rate the choice of FO or F1 to be the current field has to be made at compile time The deinterlacing algorithm does not adapt itself to handle PsF content July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 22 Chapter 5 Functional Descriptions Deinterlacer Figure 5 6 shows a simple block diagram of the Deinterlacer MegaCore function with frame buffering Figure 5 6 Deinterlacer Block Diagram with Buffering in External RAM Deinterlacing Writer Algorithm Avalon ST Output dout Avalon ST Input din Avalon MM Master Avalon MM Master write master read master Arbitration Logic Note to Figure 5 6 1 There can be one or two Avalon MM masters connected to the Memory Reader Deinterlacing Methods The Deinterlacer MegaCore function supports four deinterlacing methods m Bob with scanline duplication m Bob with scanline interpolation m Weave m Motion adaptive The Deinterlacer does not support interlaced streams where FO fields are one line higher than F1 fields in most of its parameterizations Bob with one output frame for
169. ed The other field is used to build a progressive frame unless it is dropped by the triple buffering algorithm When the bob algorithm is used and synchronization is done on both fields input field rate output frame rate the behavior is dependent on whether buffering is used If double or triple buffering is used the bob algorithm behaves like the weave and motion adaptive algorithms and a strict sequence of FO and F1 fields is expected If two or more fields of the same type are received successively the extra fields are dropped When buffering is not used the bob algorithm always builds an output frame for each interlaced input field received regardless of its type If passthrough mode for progressive frames has not been selected the Deinterlacer immediately discards progressive fields in all its parameterizations Handling of Avalon ST Video Control Packets When buffering is used the Deinterlacer MegaCore function stores non image data packets in memory as described in Buffering of Non Image Data Packets in Memory on page 4 21 July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 28 Ed Chapter 5 Functional Descriptions Interlacer Control packets and user packets are never repeated and they are not dropped or truncated as long as memory space is sufficient This behavior also applies for the parameterizations that do not use buffering in external memory incoming control and user packets ar
170. ed Video Output MegaCore function converts Avalon ST Video to clocked video formats such as BT656 BT1120 DVI It formats Avalon ST Video into clocked video by inserting horizontal and vertical blanking and generating horizontal and vertical synchronization information using the Avalon ST Video control and active picture packets No conversion is done to the active picture data the color plane information remains the same as in the Avalon ST Video format The Clocked Video Output MegaCore function converts data from the flow controlled Avalon ST Video protocol to clocked video It also provides clock crossing capabilities to allow video formats running at different frequencies to be output from the system In addition this MegaCore function provides a number of configuration registers that control the format of video leaving the system blanking period size synchronization length and interlaced or progressive mode and a status interrupt that can be used to determine when the video format changes Video Formats The Clocked Video Output MegaCore function creates the following clocked video formats m Video with synchronization information embedded in the data in BT656 or BT1120 format m Video with separate synchronization h sync v sync signals The Clocked Video Output MegaCore function creates a video frame consisting of horizontal and vertical blanking containing syncs and areas of active picture taken from the Avalo
171. ed to vid cik This signal is for information only and no action is required if it is asserted 1 refclk div Out A divided down version of vid_clk refclk Setting the Refclk Divider register to be the number of samples in a line produces a horizontal reference on this signal that a PLL can use to synchronize its output clock sof Out Start of frame signal A change of 0 to 1 indicates the start of the video frame as configured by the SOF registers Connecting this signal to a Clocked Video Output MegaCore function allows the function to synchronize its output video to this signal sof_locked Out Start of frame locked signal When high the sof signal is valid and can be used status_update_int Out control Slave port Avalon MM interrupt signal When asserted the status registers of the MegaCore function have been updated and the master should read them to determine what has occurred 7 vid_data Clocked video data bus Video data is transferred into the MegaCore function over this bus vid_datavalid Clocked video data valid signal This signal is asserted when a valid sample of video data is present on vid_data vid_f Separate Synchronization Mode Only Clocked video field signal For interlaced input this signal distinguishes between field 0 and field 1 For progressive video this signal should be deasserted vid h sync Separate Synchronization Mode Only Clocked video ho
172. el per color plane Output Data Type Choose whether output is unsigned or signed 2 s Data type Unsigned Signed complement Output Data Type Girard bands On or Off Turn on to enable a defined output range wt Data Type 1 048 575 to 524 288 Default 255 Set output range maximum value 2 ye Habe 1048575 to 524288 Default 0 Set output range minimum value 2 Move binary point right 3 16 to 16 Default 0 Specify the number of places to move the binary point This can be useful if you require a wider range output on an existing coefficient set Remove fraction bits by Round values Half up Round values Half even Truncate values to integer Choose the method for discarding fractional bits resulting from the FIR calculation Convert from signed to unsigned by Saturating to minimum value at stage 4 Replacing negative with absolute value Choose the method for signed to unsigned conversion of the FIR results Notes to Table 3 5 1 The maximum and minimum guard bands values specify a range in which the input should always fall The 2D FIR filter behaves unexpectedly for values outside th is range 2 The output is constrained to fall in the specified range of maximum and minimum guard band values 3 You can specify a higher precision output by increasing Bits per pixel per color plane and Move binary point right July 2010 Altera Corporation Vid
173. ent color space models For example to transfer a television image to a computer monitor you may need to convert the image from the Y CbCr color space to the R G B color space Conversely transferring an image from a computer display to a television may require a transformation from the R G B color space to Y CbCr Different conversions may be required for standard definition television SDTV and high definition television HDTV You may also want to convert to or from the Y IO luminance color color model for National Television System Committee NTSC systems or the Y UV luminance bandwidth chrominance color model for Phase Alternation Line PAL systems Input and Output Data Types The Color Space Converter MegaCore function inputs and outputs support signed or unsigned data and 4 to 20 bits per pixel per color plane Minimum and maximum guard bands are also supported The guard bands specify ranges of values that should never be received by or transmitted from the MegaCore function Using output guard bands allows the output to be constrained such that it does not enter the guard bands Color Space Conversion Conversions between color spaces are achieved by providing an array of nine coefficients and three summands that relate the color spaces These can be set at compile time or at run time using the Avalon MM slave interface Given a set of nine coefficients A0 A1 A2 BO B1 B2 CO C1 C2 and a set of three summands S
174. eo and Image Processing Suite User Guide 3 6 Chapter 3 Parameter Settings 2D Median Filter Table 3 6 2D FIR Filter Parameter Settings Tab Coefficients Page Parameter Value Description Filter size 7 3X3 5x5 7x7 Choose the size in pixels of the convolution kernel used in the filtering Runtime controlled On or Off Turn on to enable run time control of the coefficient values You can choose a predefined set of simple smoothing or simple sharpening coefficients which are used for color model convolution at compile time Alternatively you can create your own custom set of coefficients by modifying the coefficients in the matrix When on the 3x3 coefficient matrix must be symmetrical which enables optimization in the hardware reducing the number of multiplications required In this mode a limited number of matrix cells are editable and the remaining On or Off values are automatically inferred Symmetric mode is enabled for the predefined coefficient sets but can be disabled when setting custom coefficients If you turn off this option while one of the predefined coefficient sets is selected its values are used as the defaults for a new custom set Each coefficient is represented by a white box with a purple box underneath The value in the white box is the desired coefficient value and is editable The value in the purple box is the actual coefficient value as determined by the coefficient fixed point type specified The purp
175. er MegaCore function does not differentiate between interlaced and progressive fields When interlaced fields are received the MegaCore function buffers drops or repeats fields independently While this may be appropriate and perhaps even desired behavior when using a double buffer it is unlikely to provide the expected functionality when using a triple buffer because using a triple buffer would result in an output stream with consecutive F0 or F1 fields When Support for interlaced streams is on the Frame Buffer manages the two interlaced fields of a frame as a single unit to drop and repeat fields in pairs Using Support for interlaced streams does not prevent the Frame Buffer from handling progressive frames and run time switching between progressive and interlaced video is supported The Frame Buffer typically groups the first interlaced field it receives with the second one unless a synchronization is specified If synchronizing on F1 the algorithm groups each F1 field with the FO field that precedes it If a F1 field is received first the field is immediately discarded even if dropping is not allowed For more information refer to Control Data Packets on page 4 7 Handling of Avalon ST Video Control Packets The Frame Buffer MegaCore function stores non image data packets in memory as described in Buffering of Non Image Data Packets in Memory on page 4 21 User packets are never repeated and they are not dropped as long as
176. er of bits per color sample selected in the MegaWizard interface Color Pattern For 4 4 4 sequential data EET Cb Cr b Cr ET For 4 2 2 sequential data ES c 1 For 4 2 0 sequential data For 4 2 2 parallel data For 4 4 4 parallel data For 4 2 0 parallel data Gamma Corrector The Gamma Corrector MegaCore function provides a look up table LUT accessed through an Avalon MM slave port The gamma values can be entered in the LUT by external hardware using this interface For information about using Avalon MM slave interfaces for run time control in the Video and Image Processing Suite refer to Avalon MM Slave Interfaces on page 4 17 For details of the control register maps refer to Table 7 2 on page 7 2 Table 7 3 on page 7 2 and Table 7 4 on page 7 2 For information about the Avalon MM interface signals refer to Table 6 3 on page 6 2 When dealing with image data with N bits per pixel per color plane the address space of the Avalon MM slave port spans 2 2 registers where each register is N bits wide Registers 2 to 2N 1 are the look up values for the gamma correction function Image data with a value x will be mapped to whatever value is in the LUT at address x 2 The Gamma Corrector MegaCore function can process streams of pixel data of the types shown in Table 5 3 Table 5 3 Gamma Corrector Avalon ST Video Protocol Parameters Part 1 of 2
177. ere 1 represents full translucence and 0 represents fully opaque For n bit alpha values RGBAn coefficients range from 0 to 2 1 The model interprets 2 1 as 1 and all other values as Alpha value 2 For example 8 bit alpha value 255 gt 1 254 gt 254 256 253 gt 253 256 and so on The value of an output pixel Oy where N is the maximum number of layers is deduced from the following recursive formula On 1 Ay Pn dyOn 1 Oo where py is the input pixel for layer N and ay is the alpha pixel for layer N Consumed and disabled layers are skipped The function does not use alpha values for the background layer and you should tie the alphaO port off to 0 when the core is instantiated in SOPC Builder or the MegaWizard interface Allinput data samples must be in unsigned format If the number of bits per pixel per color plane is N then each sample consists of N bits of data which are interpreted as an unsigned binary number in the range 0 2 1 All output data samples produced by the Alpha Blending Mixer MegaCore function are also in the same unsigned format The Alpha Blending Mixer MegaCore function can process streams of pixel data of the types shown in Table 5 6 Table 5 6 Alpha Blending Mixer Avalon ST Video Protocol Parameters Parameter Frame Width Value Run time controlled Maximum value specified in the MegaWizard interface Frame Height Run time controlled Maximum valu
178. erfaces on page 4 17 For details of the control register maps refer to Table 7 6 on page 7 4 For information about the Avalon MM interface signals refer to Table 6 6 on page 6 5 Alpha Blending When Alpha blending is on the Avalon ST input ports for the alpha channels expect a video stream compliant with the Avalon ST Video protocol Alpha frames contain a single color plane and are transmitted in video data packets The first value in each packet transmitted while the startofpacket signal is high contains the packet type identifier 0 This condition holds true even when the width of the alpha channels data ports is less than 4 bits wide The last alpha value for the bottom right pixel is transmitted while the endofpacket signal is high July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 12 Chapter 5 Functional Descriptions Alpha Blending Mixer It is not necessary to send control packets to the ports of the alpha channels The width and height of each alpha layer are assumed to match with the dimensions of the corresponding foreground layer The Alpha Blending Mixer MegaCore function should recover cleanly if there is a mismatch although there may be throughput issues at the system level if erroneous pixels have to be discarded All non image data packets including control packets are ignored and discarded just before the processing of a frame starts The valid range of alpha coefficients is 0 to 1 wh
179. es Fides adi e ad ke riter 2 8 Chapter 3 Parameter Settings Color Space Conyerter CSC iiie sce EE E Renee i d tede decre 3 2 Chroma Resampler secre erg er pter le pen ce er d pend Peele e Pob ed adora 3 4 Gamma Corrector ciere direti esce Ree d WR NODI du EE T dee a deba duce ei eeu 3 4 2D EIR Filter uei e RS CREER I EET Ier 3 5 2D Median Filter 13 22 22 s I a Sad ea da eer vd aie de Ea Seed 3 6 Alpha Blending e pp ee dtr eese etie tov Ming Rede no de eek nies 3 7 url re Lc TN 3 8 CHIP Per 5 3 10 Deinterlacet Hae rbd de ee de a dee de Ee Petre ee 3 11 M LLL E LE 3 13 Fiame Readet 222 Ep kp de D e ei er d dea d da d cette oe D de ac det d ue 3 14 Frame Buero ou oth NOM 3 14 Clocked Video Input cede ee Let de HH EG eH pae Dp Peor de boue eu obe 3 16 Clocked Video Output eoe RE REN eer er RR rese er RE crie eruere eae tens 3 17 Color Plane Sequence eer ere ee cep Ie hea poeti be heey des 3 19 Test Pattern Generator 21 de LV eene ER edat en tede en diee es 3 19 Control Synchronizer cristenien eee he 3 20 ee UE t MM mE 3 21 Chapter 4 Interfaces Interlace Vy Pes esit ari eee e o deed ach PERE Gaede aie e Rd 4 1 Avalon ST Video Protocol 2
180. ese input lines are used for write transfers 1 f din port Avalon ST data bus Pixel data is transferred into the MegaCore function over this bus din port Avalon ST endofpacket signal This signal marks the end of an din endofpacket In Avalon ST packet din port Avalon ST ready signal This signal indicates when the MegaCore SEULS Be oni function is ready to receive data din port Avalon ST startofpacket signal This signal marks the start of din_startofpacket In an Avalon ST packet din Avalon ST valid signal This signal identifies the cycles when the din valid port should input data rem Out din port Avalon ST data bus Pixel data is transferred out of the MegaCore function over this bus _ dout port Avalon ST endofpacket signal This signal marks the end of an dout endofpacket Out Avalon ST packet dier cd m dout port Avalon ST reaay signal This signal is asserted by the downstream device when it is able to receive data dout port Avalon ST startofpacket signal This signal marks the start of dout startofpacket Out an Avalon ST packet EET Out dout port Avalon ST valid signal This signal is asserted when the MegaCore function outputs data Note to Table 6 8 1 These ports are present only if Pass through mode is on in the MegaWizard interface July 2010 Altera Corporation Video and Image Processing Suite User Guide 6 12 Frame Reader Table 6 11 shows the input and o
181. esto ete Mea pet a ate 5 39 Generator Lock reri e ee EYE EPPAEA YU EU VEA Y Ga RETE PIG GORGE 5 40 OVertlOW UE Uu EN wate egest er qe S ett te e ea reg 5 41 Timing Constraints 225 261 e tere o ERR CE ELE seeds opea qi edat es 5 41 Active Format Description nhe 5 42 Clocked Video Output LU EL CAM ASIE IE 5 43 Video Formats e ep Tuc ORAE AUI prd REOR e IE e 5 43 Embedded Synchronization Format 000 eee 5 45 Separate Synchronization Format ens 5 46 Control Potts crt OS Aas Bee RARE acc Bu EG ECC E Bd EG uc AS 5 46 Video Mod s oor OE Peru CPP nie ERE LAE EA Rc E Ad 5 46 Intertupte citi DEDUCI ete ete sei ees te ene 5 51 Generator Bock Se nies aa ek es he Us ie eee eye eee 5 51 Urndertlow 36 4 bia Pia Pk PES iE SS i RS 5 53 Timing Consttaints ss lt 0hagceeesaw eet dose Sandee ye dave quede ip big edendo op ee 5 54 Active Format Description Inserter sees nhe 5 54 Color Plane Sequencer esee ROMA RE YEN vea vag eta 5 55 Rearranging Color Patterns 22 0 sss cer eee es ena Oe ed eS 5 55 Combining Color Patterns sergio eran geet one repere e bale sean P op datis ag 5 55 Splhitting Duplicating i wet gei eco Baa iem cheek aoe aa eed as Mak da
182. et 2 ree Ete easier EO IH i e iHe aede e Ee dee dece deron dete deve iicet 6 11 Frame Reader od ott S E M CN TC uU LEE t 6 12 Fiame Fare ok icem E DR oe Rb Ee d ceu cet duc 6 13 Clocked Video epe sete estado nci 6 15 Clocked Video Output dna Etre ee HERE HER RR EA Pet bak hee eed A 6 17 Color Plane Sequencer scx ere e tepore Ne ertvelet He e tete bee ttes 6 18 Test Pattern Generator eR ER 6 19 Control SynchtODnlZetr tee pte RR Un paa ra ba en E RR PR 6 20 SWE CDi oer MT 6 21 Chapter 7 Control Register Maps Color Space Converter xxu pe eene eR Ren eet EE etes dile ARE 7 1 Gamma COrrector so doce Ee ER HE I eg geb a e ege dese a ie Pd d de deed 7 2 2D FIR Filter eoriou ERR TRE TRUE 7 3 Alpha Blending Mixer eer eae PROP pb eg a dee a dee RU eoe ee dente 7 3 Scaler sc cv T 7 4 GUpPper seina eee 7 6 Deinterlacer 7 6 Intetlacer E 7 7 Frame Reader eeu bcd pese ede 7 8 PFrame Buffer eH e eae Pa bee oe eden cede D Pe deed ae Da 7 8 Clocked Video teen tad dente ken E Edited pee dtu dee did 7 10 Clocked Video Output
183. etn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword sUBDESIGN and logic function names for example TRI An angled arrow instructs you to press the Enter key Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Hm Bullets indicate a list of items when the sequence of the items is not important 57 The hand points to information that requires special attention A question mark directs you to a software help system with related information ue The feet direct you to another document or website with related information CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work WARNING A warning calls attention to a condition or possible situation that can cause you injury Lj The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents Referenced Documents Altera application notes white papers and user guides available at the Altera web site www altera com provide more detail of how to effectively design with MegaCore functi
184. fficiency Frame Rate Conversion When you select triple buffering the decision to drop and repeat frames is based on the status of the spare buffer Because the input and output sides are not tightly synchronized the behavior of the Deinterlacer is not completely deterministic and can be affected by the burstiness of the data in the video system This may cause undesirable glitches or jerky motion in the video output By using a double buffer and controlling the dropping repeating behavior the input and output can be kept synchronized For example if the input has 60 interlaced fields per second but the output requires 50 progressive frames per second fps setting the input frame rate to 30 fps and the output frame rate at 50 fps guarantees that exactly one frame in six is dropped Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 27 Deinterlacer To control the dropping repeating behavior and to synchronize the input and output sides you must select double buffering mode and turn on Run time control for locked frame rate conversion in the Parameter Settings tab of the MegaWizard interface The input and output rates can be selected and changed at run time Table 7 10 on page 7 6 describes the control register map The rate conversion algorithm is fully compatible with a progressive input stream when the progressive passthrough mode is enabled but it cannot be enabled simul
185. filtering Cyclone III 1 998 787 212 Stratix 2 656 785 356 Downsampling from 4 4 4 to 4 2 0 with The parameterization uses anti aliasing a parallel data interface and ru n time contro of resolutions up to XGA 1024x768 filtering on the horizontal resampling and nearest neighbor on the vertical Cyclone III 1 1 848 1 236 4 096 1 149 Stratix Ill 2 1 115 1 240 4 096 1 296 Downsamping from 4 4 4 to 4 2 2 with a sequential data interface at quarter common intermediate format QCIF 176x144 using an anti aliasing filter Cyclone 111 1 848 531 194 Stratix 1 2 419 533 357 Notes to Table 1 5 1 Using EP3C10F256C6 devices 2 Using EP3SE50F780C2 devices Gamma Corrector Table 1 6 shows the performance figures for the Gamma Corrector Table 1 6 Gamma Corrector Performance Device Family Combinational Logic Memory DSP Blocks fux LUTs ALUTs Registers Bits M9K 9x9 18 18 MHz Gamma correcting 1 080 pixel one color 10 bit data Cyclone III 1 242 153 10 260 3 233 Stratix 111 2 172 153 10 260 3 393 Gamma correcting 720x576 one color 10 bit data Cyclone III 1 242 153 10 260 3 233 Stratix 111 2 172 153 10 260 3 393 Gamma correcting 128x128 three color 8 bit
186. fined coefficient spreadsheet edit the data with your third party tool delete the Phase column and store the data in the Coeff columns as a csv file Then in the MegaWizard interface select Custom from the Filter function list click Browse load the csv file and click Preview coefficients to verify the data July 2010 Altera Corporation Video and Image Processing Suite User Guide 3 10 Clipper Chapter 3 Parameter Settings Clipper 5 When editing the data each row of coefficients must sum to the same value Refer to Choosing and Loading Coefficients on page 5 17 Table 3 12 shows the Clipper MegaCore function parameters Table 3 12 Clipper Parameter Settings Parameter Maximum width Value 32 to input image width Default 1 024 Description Specify the maximum width of the clipping rectangle for the input field progressive or interlaced Maximum height 32 to input image height Default 768 Specify the maximum height of the clipping rectangle for the input field progressive or interlaced Bits per pixel per color plane 4 20 Default 8 Choose the number of bits per pixel per color plane Number of color Choose the number of color planes that are sent in sequence over one interface planes in sequence ins data connection For example a value of for R G B R G B R G B Number of color planes in parallel 1 3 Choose the number of color planes in para
187. frame size is propagated unchanged to the next MegaCore function 2D FIR Filter There is a delay of a little more than N 1 lines between data input and output in the case of a NxN 2D FIR Filter This is due to line buffering internal to the MegaCore function Error Recovery The 2D FIR Filter MegaCore function resolution is not configurable at runtime This MegaCore function does not read the control packets passed through it An error condition occurs if an endofpacket signal is received too early or too late for the compile time configured frame size In either case the 2D FIR Filter always creates output video packets of the configured size If an input video packet has a late endofpacket signal then the extra data is discarded If an input video packet has an early endofpacket signal then the video frame is padded with an undefined combination of the last input pixels 2D Median Filter There is a delay of a little more than N 1 lines between data input and output in the case of a NxN 2D Median Filter This is due to line buffering internal to the MegaCore function July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 68 Chapter 5 Functional Descriptions Stall Behavior and Error Recovery Error Recovery The 2D Median Filter MegaCore function resolution is not configurable at run time This MegaCore function does not read the control packets passed through it An error condition occurs if an endofpa
188. g Suite User Guide July 2010 Altera Corporation Contents Specification of the Type of Avalon MM Slave Interfaces 4 19 Avalon MM Master Interfaces en 4 20 Specification of the Type of Avalon MM Master Interfaces 4 20 Buffering of Non Image Data Packets in Memory ssssssssseeee eee eee 4 21 Chapter 5 Functional Descriptions Color Space Converter sr esri cnr tind lta in SA He ded ee ee eis ene ene etes 5 1 Inputand Output Data Types cete ca cues tun e eph ERI ehe re bm ed pared eee 5 1 Color Space Conversion cce co eee Ree RR RP he ERR dee Ie atte Ce Stat eor d itte th 5 1 Constant Precision 22 es iting tudes eder yer de ete ad Deep oce elles ace a ew e ee ent RR e boda 5 2 Calculation Precision eenid erie idei eee ee LO d ee dev e dio tec 5 2 Result of Output Data Type Conversion 2 066 nn 5 3 Chroma Resampler erdt Hoe E deett Hee P Ee Hee HE de P dee eot 5 4 Horizontal Resampling 4 2 2 2 nne 5 4 44 4 104 2 2 ase acetate ed e Ee e Eee UE RUE e Pau eoa dee Votes ee teet 5 4 DED NO IU P 5 5 Vertical Resampling 42 0 e eii ea E e a E a a 5 6 MM MD CR 5 7 2D FIR Filter 13 rete et tr eoe ne b Lb eR EEUU or rm a tete ded tested 5 8 Calculation Pr cision e n epe rhe tee piece d sce pb atn 5 8 Coefficient Precisi n
189. g a 0 from bit 0 indicates that the MegaCore function is running video ou is flowing through it reading a 1 indicates that it is stopped Writing a 1 to bit 0 indicates that the video output streams should be 2 Output Switch synchronized and then the new values in the output control registers should be loaded A one hot value that selects which video input stream should propagate to this output For example for a 3 input switch m 3 b000 no output 3 Dout0 Output Control 3 b001 din 0 m 3 b010 din 1 m 3100 din 2 4 Doutl Output Control AS Dout0 Output Control but for output dout 1 15 Doutl2 Output Control AS Dout0 Output Control but for output aout 12 July 2010 Altera Corporation Video and Image Processing Suite User Guide 7 16 Chapter 7 Control Register Maps Switch Video and Image Processing Suite User Guide July 2010 Altera Corporation JA DTE RA Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document Date Version Changes Added Stratix V device support July 2010 i00 Added Interlacer MegaCore function m Updated Clocked Video Output and Clocked Video Input MegaCore functions to insert and extract ancillary packets Added new Frame Reader Control Synchronizer and Switch MegaCore functions m he Frame Buffer MegaCore function supports contro
190. ge Processing Suite User Guide 5 32 Chapter 5 Functional Descriptions Frame Buffer Table 5 12 Avalon ST Video Parameters Part 2 of 2 Parameter Value Bits per Color Sample Specified in MegaWizard interface Up to four color planes in parallel with up to three color planes in sequence Color Pattern Frame Buffer The Frame Buffer MegaCore function buffers progressive or interlaced video fields in external RAM When frame dropping and frame repeating are not allowed the Frame Buffer provides a double buffering function that can be useful to solve throughput issues in the data path When frame dropping and or frame repeating are allowed the Frame Buffer provides a triple buffering function and can be used to perform simple frame rate conversion The Frame Buffer is built with two basic blocks a writer which stores input pixels in memory and a reader which retrieves video frames from the memory and outputs them Figure 5 10 shows a simple block diagram of the Frame Buffer MegaCore function Figure 5 10 Frame Buffer Block Diagram Memory Writer Memory Reader 1 Avalon ST Output Avalon ST Input i H 1 dout din Avalon MM Master Avalon MM Master write master read master Arbitration Logic When double buffering is in use two frame buffers are used in external RAM At any time one buffer is used by the writer component to store input pixels while the second buffer i
191. ge Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 9 2D Median Filter This is performed in four stages in the following order 1 Result Scaling You can choose to scale up the results increasing their range This is useful to quickly increase the color depth of the output The available options are a shift of the binary point right 16 to 16 places This is implemented as simple shift operation so it does not require multipliers Removal of Fractional Bits If any fractional bits exist you can choose to remove them There are three methods m Truncate to integer Fractional bits are removed from the data This is equivalent to rounding towards negative infinity Round Half up Round up to the nearest integer If the fractional bits equal 0 5 rounding is towards positive infinity m Round Half even Round to the nearest integer If the fractional bits equal 0 5 rounding is towards the nearest even integer Conversion from Signed to Unsigned If any negative numbers can exist in the results and the output type is unsigned you can choose how they are converted There are two methods m Saturate to the minimum output value constraining to range m Replace negative numbers with their absolute positive value Constrain to Range If any of the results are beyond the range specified by the output data type output guard bands or if unspecified the minimum and maxim
192. gures for the Test Pattern Generator Table 1 18 Test Pattern Generator Performance Device Family Combinational Logic Memory DSP Blocks fmax LUTs ALUTs Registers Bits M9K 9x9 18 18 MHz Producing a 400xx200 8 bit 4 2 0 Y Cb Cr stream with a parallel data interface Cyclone 111 1 164 112 192 2 332 Stratix 2 158 113 192 2 545 Producing a 640x480 8 bit R G B stream with a sequential data interface Cyclone 111 1 212 118 192 3 287 Stratix 2 181 119 192 3 485 Producing a 720x480 10 bit 4 2 2 Y Cb Cr interlaced stream with a sequential data interface Cyclone 111 1 258 138 240 3 245 Stratix 2 233 138 240 3 489 can be changed using Producing a 1920x1080 10 bit 4 2 2 Y the run time con Cb Cr interlaced trol interface stream with a parallel data interface The resolution of the pattern Cyclone III 7 365 208 304 263 Stratix Ill 2 248 208 304 481 Notes to Table 1 18 1 EP3C10F256C6 devices 2 EP3SE50F780C2 devices July 2010 Altera Corporation Video and Image Processing Suite User Guide 1 16 Chapter 1 About This MegaCore Function Suite Performance and Resource Utilization Switch Table 1 19 shows the performance figures for the Switch Table 1 19 Switch Performance Device Family Logic Memory DS
193. hase mode Figure 5 4 Polyphase Mode Scaler Block Diagram Line Buffer Line Buffer Delay Delay Bit Narrowing Register Delay Register Delay Ch Ch on OS LI Data from multiple lines of the input image are assembled into line buffers one for each vertical tap These data are then fed into parallel multipliers before summation and possible loss of precision The results are gathered into registers one for each horizontal tap These are again multiplied and summed before precision loss down to the output data bit width The progress of data through the taps line buffer and register delays and the coefficient values in the multiplication are controlled by logic that is not present in the diagram Refer to Algorithmic Description on page 5 17 July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 16 Chapter 5 Functional Descriptions Scaler Resource Usage Consider an instance of the polyphase scaler with N vertical taps and N horizontal taps B4ata is the bit width of the data samples B is the bit width of the vertical coefficients and is derived from the user parameters for the vertical coefficients It is equal to the sum of integer bits and fraction bits for the vertical coefficients plus one if coefficients are signed B is defined similarly for horizontal coefficient
194. hat are only used when connecting to the SDI MegaCore function They are vid trs which is high during the 3FF sample of the TRS and vid 1n which outputs the current SDI line number These are used by the SDI MegaCore function to insert line numbers and cyclical redundancy checks CRC into the SDI stream as specified in the 1 5 Gbps HD SDI and 3 Gbps SDI standards The Clocked Video Output MegaCore inserts any ancillary packets packets with a type of 13 or OxD into the output video during the vertical blanking For information about Avalon ST Video ancillary data packets refer to Ancillary Data Packets on page 4 10 The Clocked Video Output MegaCore begins inserting the packets on the lines specified in its parameters or mode registers ModeN Ancillary Line and ModeN F0 Ancillary Line The Clocked Video Output MegaCore stops inserting the packets at the end of the vertical blanking July 2010 Altera Corporation Video and Image Processing Suite User Guide Chapter 5 Functional Descriptions Clocked Video Output The Clocked Video Input MegaCore function extracts any ancillary packets from the Y channel during the vertical blanking Ancillary packets are not extracted from the horizontal blanking The extracted packets are output via the Clocked Video Input s Avalon ST output with a packet type of 13 0xD Separate Synchronization Format For the separate synchronization format the MegaCore function outputs horizontal and vertical syn
195. he starting address of the video frame in memory and the width height and interlaced values of the control data packet to output before each video data packet The raw data that comprises a video frame in external memory is stored as a set of single cycle color patterns In memory the single cycle color patterns must be organized into word sized sections Each of these word sized sections must contain as many whole samples as possible with no partial single cycle color patterns Unused bits are in the most significant portion of the word sized sections Single cycle color patterns in the least significant bits are output first The frame is read with words at the starting address first Figure 5 9 shows the output pattern and memory organization for a Frame Reader MegaCore which is configured for m 8 bits per pixel per color plane m 3color planes in parallel m Master port width 64 Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 31 Frame Reader Other Frame Reader parameters affect only resources and performance or both For more information refer to Table 5 12 Figure 5 9 Frame Reader Output Pattern and Memory Organization n2 A a n2 o n2 77 12 13 14 15 16 17 18 19 20 21 22 23 YW Start Address 1 ad bou 64 Bit Word Oo
196. he trigger is disabled and must be re enabled via the control port Maximum number of control data entries 1 10 Default 3 Maximum number of control data entries that can be written to other cores Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 3 Parameter Settings 3 21 Switch Switch Table 3 22 shows the Switch MegaCore function parameters Table 3 22 Switch Parameter Settings Parameter Value Description Bits per pixel per color plane 4 20 Default 8 Choose the number of bits per pixel per color plane Number of color planes 1 3 Default 3 Choose the number of color planes Color planes are in parallel On or Off Turn on to set colors planes in parallel turn off to set colors planes in sequence Number of input ports 1 12 Default 2 Number of input ports din and alpha in Number of output ports 1 12 Default 2 Number of output ports dout and alpha out Alpha enabled On or Off Turn on to enable the alpha ports Bits per pixel representing 2 4 or 8 Choose the number of bits used to represent the alpha coefficient the alpha coefficient July 2010 Altera Corporation Video and Image Processing Suite User Guide 3 22 Chapter 3 Parameter Settings Switch Video and Image Processing Suite User Guide July 2010 Altera Corporation RA 4 Interfaces Interface Types The MegaCore functio
197. hem 9 NTSC video transmits 60 interlaced fields per second 30 frames per second Selecting an Output frame rate of As input frame rate ensures that the output is 30 frames per second 10 The total memory required at the specified base address is displayed under the base address Interlacer Table 3 13 shows the Interlacer MegaCore function parameters Table 3 14 Interlacer Parameter Settings Parameter Maximum image width Value 32 2600 Default 640 Description Specifies the maximum frame width in pixels The maximum frame width is the default width at start up Maximum image height 32 2600 Default 480 Specifies the maximum progressive frame height in pixels The maximum frame height is the default progressive height at start up Bits per pixel per color plane 4 20 Default 8 Specifies the number of bits per color plane Number of color planes Specifies the number of color planes that are sent in sequence field selection 1 3 over one data connection For example a value of 3 for R G B in sequence R GB RGB Number of color planes in parallel 1 3 Specifies the number of color planes sent in parallel initial field FO F1 Specifies the type for the first field output after reset or after a resolution change Pass through mode On or Off Turn on to propagate interlaced fields unchanged Turn off to discard interlaced input Run time contr
198. hese output lines are used 1 ddat t DR EUST Ou for read transfers ieee T slave port Avalon MM write signal When this signal is asserted the gamma 1ut accepts new data from the writedata bus slave port Avalon MM writedata bus These input lines are used for write transfers slave port Avalon interrupt signal When asserted the status update int w Out interrupt registers of the MegaCore function have been updated and the master should read them to determine what has occurred TE Out master port Avalon MM address bus Specifies a byte address in the Avalon MM address space EDT Out master port Avalon MM writedata bus These output lines carry no data for write transfers Nias teeta Out master port Avalon MM write signal Asserted to indicate write AY ces requests from the master to the system interconnect fabric _ master port Avalon MM waitrequest signal Asserted by the system master av wailtrequest In interconnect fabric to cause th e master port to wait Switch Table 6 18 shows the input and output signals for the Switch MegaCore function Table 6 18 Switch Signals Part 1 of 2 Signal Direction Description T The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is reset In asserted high The reset must be de asserted syn
199. hree color planes but you can choose q whether they are transmitted in sequence in parallel format Progressive output Interlacing Interlaced output FO first Specifies whether to produce a progressive or an interlaced output stream Interlaced output F1 first Pattern Color bars Uniform Choose the standard color bar or a uniform background background _ When pattern is uniform background you can specify the individual R G B Unitoum values 05955 126 or Y Cb Cr values depending on the currently selected color space Control Synchronizer Table 3 21 shows the Control Synchronizer MegaCore function parameters Table 3 21 Control Synchronizer Parameter Settings Parameter Bits per pixel per color plane Value 4 16 Default 8 Description The number of bits used per pixel per color plane Number of color The number of color planes that are sent over one data via control port 1 4 Default 3 connection For example a value of 3 for R G B R G B R G B in planes serial ee mod On or Off Color planes are transmitted in parallel or in series Trigger on width On or Off Trigger compares control packet width values change Trigger on height On or Off Trigger compares control packet height values change Trigger on start of video data packet On or Off Trigger activates on each start of video data packet Require trigger reset On or Off Once triggered t
200. ideo Output MegaCore function correctly add the following file to your Quartus IT project lt install_dir gt ip clocked_video_input lib alt_vip_cvi sdc July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 42 Chapter 5 Functional Descriptions Clocked Video Input When you apply the SDC file you may see some warning messages in a format as follows m Warning At least one of the filters had some problems and could not be matched m Warning could not be matched with a keeper These warnings are expected because in certain configurations the Quartus II software optimizes unused registers and they no longer remain in your design Active Format Description Extractor The AFD Extractor is an example of how to write a core to handle ancillary packets It is available in the following directory install dir NipNclocked video outputMibNafd example When the output of the Clocked Video Input MegaCore function is connected to the input of the AFD Extractor the AFD Extractor removes any ancillary data packets from the stream and checks the DID and secondary DID SDID of the ancillary packets contained within each ancillary data packet If the packet is an AFD packet DID 0x41 SDID 0x5 the extractor places the contents of the ancillary packet into the AFD Extractor register map T Refer to the SMPTE 2016 1 2007 standard for a more detailed description of the AFD codes Table 5 19 shows the AFD Extra
201. ideo packets into RAM Cyclone Ill 1 3 796 2 495 11 168 6 145 Stratix 111 2 2 723 2 496 11 168 11 228 Triple buffering 720x576 8 bit RGB with sequential data interface and runtime control interface Cyclone III 1 2 177 1 763 8 504 7 162 Stratix 111 2 1 826 1 763 8 504 12 304 Notes to Table 1 14 1 EP3C10F256C6 devices 2 EP3SE50F780C2 devices Clocked Video Input Table 1 15 shows the performance figures for the Clocked Video Input Table 1 15 Clocked Video Input Performance Part 1 of 2 Combinational Logic Memory f Deviee Family ilUs Registers ALUTs M9K Bits MLAB Bits i Converts DVI 1080p60 clocked video to Avalon ST Video Cyclone III 1 411 414 7 51 200 187 Stratix 111 2 264 414 7 51 200 245 Converts PAL clocked video to Avalon ST Video Cyclone III 1 417 417 3 22 528 183 Stratix 111 2 301 417 3 22 528 228 Converts SDI 1080i60 clocked video to Avalon ST Video Cyclone III 1 417 439 7 43 028 169 Stratix 111 2 319 458 10 6 43 028 40 226 Converts SDI 1080p60 clocked video to Avalon ST Video Cyclone III 1 414 430 7 43 008 174 July 2010 Altera Corporation Video and Image Processing Suite User Guide 1 14 Chapter 1 About This MegaCore Function Suite Performance and Resource Utilization Table 1 15 Clocked Video Input Performance Part 2 of 2
202. in sequence 4 2 2 stream from Cb Y Cr Y to Y Cb Y Cr 8 bit data Cyclone III 1 291 243 261 Stratix 2 204 243 436 Joining a single channel luminance stream and a channels in sequence horizontally half subsampled chrominance stream to a single 4 2 2 channels in sequence output stream 8 bit data Cyclone III 1 374 313 261 Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 1 About This MegaCore Function Suite 1 15 Performance and Resource Utilization Table 1 17 Color Plane Sequencer Performance Part 2 of 2 Device Family Combinational Logic Memory DSP Blocks fux LUTs ALUTs Registers Bits M9K 9x9 18x18 MHz Stratix 2 262 313 391 Splitting a 4 2 2 stream from 2 channels in parallel to a single channel luminance output stream and a channels in sequence horizontally half subsampled chrominance output stream 8 bit data Cyclone 111 1 451 335 231 Stratix 111 2 305 336 369 Rearranging 3 channels in sequence to 3 channels in parallel 8 bit data Cyclone 111 1 242 249 258 Stratix 2 186 253 440 Notes to Table 1 17 1 EP3C10F256C6 devices 2 EP3SE50F780C2 devices Test Pattern Generator Table 1 18 shows the performance fi
203. included Extra samples are discarded if packets are larger than allowed 5 Turn on to add a separate clock signal for the Avalon MM master Use separate clocks for interfaces so that they can run at a different speed to the Avalon the Avalon MM master On or Off ST processing This decouples the memory speed from the speed interfaces of the data path and is sometimes necessary to reach performance target Avalon MM master ports width 3 16 32 64 128 256 Specifies the width of the Avalon MM ports used to access external memory when double buffering or triple buffering is used Read only master s interface FIFO depth 16 1 024 Default 64 Choose the FIFO depth of the read only Avalon MM interface Read only master s interface burst target 2 256 Default 32 Choose the burst target for the read only Avalon MM interface Write only master s interface FIFO depth 16 1 024 Default 64 Choose the FIFO depth of the write only Avalon MM interface Write only master s interface burst target 8 256 Default 32 Choose the burst target for the write only Avalon MM interface Base address of frame buffers 3 10 Any 32 bit value Default 0x00000000 Hexadecimal address of the frame buffers in external memory when buffering is used Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 3 Parameter Settings Interlacer 3 1
204. ines are used for read transfers slave port Avalon MM write Signal When this signal is slave write In asserted the gamma 1ut port accepts new data from the writedata Dus slave port Avalon MM writedata bus These input Slave av writedata In lines are used for write transfers slave port Avalon MM interrupt signal When Out asserted the interrupt registers of the MegaCore function have been updated and the master should read them to determine what has occurred Out master port Avalon MM address bus Specifies a byte address in the Avalon MM address space t Avalon ignal ifi Out master port Avalon burstcount Signal Specifies the number of transfers in each burst master port Avalon read signal Asserted to master av read Out indicate read requests from the master to the system interconnect fabric _ master port Avalon readdata bus These input master av readdata In lines carry data for read transfers master port Avalon readdatavalid signal This master av readdatavalid In signal is asserted by the system interconnect fabric when the requested read data has arrived Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 6 Signals Frame Buffer Table 6 11 Frame Reader Signals Part 2 of 2 6 13 Signal master av waitrequest Direction In Description master port Avalon MM waitrequest signal Asserted by the system i
205. input to output without using external memory This is possible only with the bob method Double buffering routes data via a pair of buffers in external memory This is required by the weave and motion adaptive methods and can ease throughput issues for the bob method Triple buffering uses three buffers in external memory and has the advantage over double buffering that the Deinterlacer can drop or repeat frames to perform simple frame rate conversion Output frame rate 9 As input frame rate FO synchronized As input frame rate F1 synchronized As input field rate Specifies whether to produce a frame out for every field which is input or a frame output for every frame pair of fields input Each deinterlacing method is defined in terms of its processing of the current field and some number of preceding fields In the case where a frame is produced only for every two input fields the current field is either always an F1 field or always an FO field Turn on to propagate progressive frames unchanged When off adaptive algorithm 2 Passthrough mode Onorat the progressive frames are discarded On or Off Turn on to add an Avalon MM slave interface that synchronizes the input and output frame rates conversion 2 6 Turn on to avoid color artefacts when processing 4 2 2 Y CbCr 4 2 2 support for motion On or Off data when the Motion Adaptive deinterlacing method is selected This option cann
206. iod One full line of video is required before the MegaCore function can determine the width Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 39 Clocked Video Input m Picture height in lines The MegaCore function counts the total number of lines per frame or field and the number of lines in the active picture period One full frame or field of video is required before the MegaCore function can determine the height m Interlaced Progressive The MegaCore function detects whether the incoming video is interlaced or progressive If it is interlaced separate height values are stored for both fields One full frame or field of video and a number of lines from a second frame or field are required before the MegaCore function can determine whether the source is interlaced or progressive m Standard The MegaCore function provides the contents of the vid std bus via the Standard register When connected to the rx std signal of a SDI MegaCore function for example these values can be used to report the standard SD HD or 3G of the incoming video If the MegaCore function has not yet determined the format of the incoming video it uses the values specified under the Avalon ST Video Initial Default Control Packet section in the MegaWizard interface After determining an aspect of the incoming videos format the MegaCore function enters the value in the respective register se
207. is signal marks the start of an REE Avalon ST packet i iia din port Avalon ST 11 signal This signal identifies the cycles when the port should input data T Out dout port Avalon ST data bus Pixel data is transferred out of the MegaCore a function over this bus dout port Avalon ST endofpacket signal This signal marks the end of an dout endofpacket Out Avalon ST packet Jout F dout port Avalon ST ready signal This signal is asserted by the downstream device when it is able to receive data dout port Avalon ST startofpacket signal This signal marks the start of an dout startofpacket Out Avalon ST packet does Out dout port Avalon ST valid signal This signal is asserted when the MegaCore PENES function outputs data Gamma Corrector Table 6 3 shows the input and output signals for the Gamma Corrector MegaCore function Table 6 3 Gamma Corrector Signals Part 1 of 2 Signal Direction Description The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is asserted reset In high The reset must be de asserted synchronously with respect to the rising edge of the clock signal din port Avalon ST data bus Pixel data is transferred into the MegaCore function over this bus clock In din data In Video and Image Processing Suite User Guide July 2010 Altera
208. its the function does not use the most significant bits of the symbol Table 4 5 shows the order of the nibbles and associated symbols Table 4 5 Order of Nibbles and Associated Symbols Order Symbol Order Symbol 1 width 15 12 6 height 11 8 2 width 11 8 7 height 7 4 3 width 7 4 8 height 3 0 4 width 3 0 9 interlacing 3 0 5 height 15 12 If the number of symbols transmitted in one cycle of the Avalon ST interface is more than one then the nibbles Table 4 5 are distributed such that the symbols occupying the least significant bits are populated first July 2010 Altera Corporation Video and Image Processing Suite User Guide 4 10 Chapter 4 Interfaces Avalon ST Video Protocol Figure 4 8 Figure 4 9 and Figure 4 10 on page 4 10 show examples of control data packets and how they are split into symbols Figure 4 8 Three Symbols in Parallel Control data reference numbers to Table 4 5 Start End 3 6 Symbols in most significant bits X 2 5 8 Symbols in middle significant bits 15 1 4 7 Symbols in least significant bits LH Control data packet type identifier 4 bits in least significant symbol X s for unused symbols Figure 4 9 Two Symbols in Parallel Control data reference numbers to Table 4 5 A Start B End A 618 x Symbols in most significant bits 15 1 3 DE Symbols in least sig
209. ker Out marks the start of an Avalon ST packet 7 alpha_out_N port Avalon ST valid signal This signal is asserted alpha put N valig Out when the MegaCore function outputs data 7 din_N port Avalon ST data bus Pixel data is transferred into the din_N_data In MegaCore function over this bus din N port Avalon ST endofpacket signal This signal marks the end Gap endofpacket of an Avalon ST packet din N port Avalon ST ready signal This signal indicates when the ready Out MegaCore function is ready to receive data din_N port Avalon ST startofpacket signal This signal marks the dci E DA start of an Avalon ST packet din N valid ii din N port Avalon ST valid signal This signal identifies the cycles when the port should input data Out dout_N port Avalon ST data bus Pixel data is transferred out of the MegaCore function over this bus 5 dout_N port Avalon ST endofpacket signal This signal marks the dout endofpacket Out end of an Avalon ST packet _ dout_N port Avalon ST ready signal This signal is asserted by the dout_N_ready In downstream device when it is able to receive data _ dout_N port Avalon ST startofpacket signal This signal marks the start of an Avalon ST packet dant N valid Out dout_N port Avalon ST valid signal This signal is asserted when the MegaCore function outputs data Note to Table 6 18 1 These ports are present only when Alpha Enabled is
210. kets with a change to the Scaler output size such that the Scaler maintains a scaling ratio of 1 1 no scaling The Frame Buffer is configured to drop and repeat this makes it impossible to calculate when packets streamed into the Frame Buffer are streamed out to the Scaler which means that the Scaler cannot be configured in advance of a certain video data packet The Control Synchronizer solves this problem as described in the following scenario July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 62 Chapter 5 Functional Descriptions Control Synchronizer 1 Set up the change of video width as shown in Figure 5 25 Figure 5 25 Change of Video Width Avalon MM Master Avalon MM Control Synchronizer Avalon MM Test Pattern Generator Avalon MM Scaler Nios CPU CPU Writes to CPU Writes to Control Test Pattern Synchronizer Configures it to Generator Change Scaler Output Size to 320 Width changing frame width to 320 When a Change in Width is Detected Red Line Indicates Control Data Packet and Video Data Packet Pair Number 4 Width 640 Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 0 Width 640 Control Data packet and Video Data Packet Pair Numbers 1 2 and 3 are Stored in the Frame Buffer 2 The Test Pattern Generator has changed the size of its Video Data Packet and Control Data Packet pairs to 320 width It is
211. l Lower Pixel Output Pixel 1 M Still Pixel Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 25 Deinterlacer Ls The motion adaptive algorithm requires the buffering of two frames of data before it can produce any output The Deinterlacer always consumes the three first fields it receives at start up and after a change of resolution without producing any output The weave and motion adaptive algorithms cannot handle fields of different sizes for example 244 lines for FO and 243 lines for F1 Both implementations discard input fields and do not produce an output frame until they receive a sufficient number of consecutive fields with matching sizes Pass Through Mode for Progressive Frames In its default configuration the Deinterlacer discards progressive frames Change this behavior if you want a datapath compatible with both progressive and interlaced inputs and where run time switching between the two types of input is allowed When the Deinterlacer lets progressive frames pass through the deinterlacing algorithm in use bob weave or motion adaptive propagates progressive frames unchanged The function maintains the double or triple buffering function while propagating progressive frames Enabling the propagation of progressive frames impacts memory usage in all the parameterizations of the bob algorithm that use buffering Frame Buffering Th
212. l fraction bits and eight bit input data the multipliers are nine bit With the same configuration but 10 bit input data the multipliers are 10 bit The function uses two line buffers As in nearest neighbor mode each of line buffers is the size of a clipped line from the input image The logic area is more than the nearest neighbor method Algorithmic Description This section describes how the algorithmic operations of the bilinear scaler can be modeled using a frame based method This does not reflect the implementation but allows the calculations to be presented concisely To find a value for an output pixel located at i j we first calculate the corresponding location on the input in x i x Win Wout inj j x The integer solutions Lina Linj to these equations provide the location of the top left corner of the four input pixels to be summed The differences between inj in and Linj are a measure of the error in how far the top left input pixel is from the real valued position that we want to read from Call these errors err and err The precision of each error variable is determined by the number of fraction bits chosen by the user By and respectively Their values can be calculated as B x2 fh TX U Wout X wi 7otw err out Bro OX Ain Mout x2 max h hou out where is the modulus operator and max a b is a function that returns the maximu
213. le When an endofpacket signal is received unexpectedly early or late the MegaCore function recovers from the error and prepares itself for the next valid packet control or data The time taken to do this is described in each of the following sections The exact behavior of the MegaCore functions may vary between releases or if any of the parameters are changed Color Space Converter In all parameterizations the Color Space Converter only stalls between frames and not between rows It has no internal buffering apart from the registers of its processing pipeline so there are only a few clock cycles of latency Error Recovery The Color Space Converter MegaCore function processes video packets until an endofpacket signal is received the control packets are not used For this MegaCore function there is no such condition as an early or late endofpacket any mismatch of the endofpacket signal and the frame size is propagated unchanged to the next MegaCore function Chroma Resampler All modes of the Chroma Resampler stall for a few cycles between frames and between lines Latency from input to output varies depending on the operation mode of the Chroma Resampler MegaCore function The only modes with latency of more than a few cycles are 4 2 0 to 4 2 2 and 4 2 0 to 4 4 4 These modes have a latency corresponding to one line of 4 2 0 data Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional De
214. le the function selects Model over Mode2 if they both match To allow the function to select Mode2 invalidate Model by writing a 0 to its mode valid register Invalidating a mode does not clear its configuration Interrupts The Clocked Video Output MegaCore function outputs a single interrupt line which is the OR of the following internal interrupts m Thestatus update interrupt Triggers when the Video Mode Match register is updated by a new video mode being selected m Locked interrupt Triggers when the outgoing video SOF is aligned to the incoming SOF Both interrupts can be independently enabled using bits 2 1 of the Control register The ir values can be read using bits 2 1 of the Interrupt register and a write of 1 to either of these bits clears the respective interrupt Generator Lock The Clocked Video Output MegaCore function provides some functions to facilitate Genlock The MegaCore function can be configured to output via the vcoclk_div signal a divided down version of its vid_clk vcoclk signal aligned to the SOF By setting the divided down value to be the length in samples of a video line the vcoclk div signal can be configured to output a horizontal reference The Genlock functionality is enabled using the Control register When Genlock functionality is enabled the Clocked Video Output MegaCore does not synchronize itself to the incoming Avalon ST Video Altera recommends that you disable Genlock functionality
215. le boxes are not editable You can create a custom set of coefficients by specifying one fixed point value for each entry in the convolution kernel The matrix size depends on the selected filter size Coefficient Precision On or Off Turn on if you want the fixed point type that stores the coefficients to have a Signed 3 sign bit Coefficient Precision Specifies the number of integer bits for the fixed point type used to store the Integer bits 3 coefficients Coefficient Precision Specifies the number of fractional bits for the fixed point type used to store Fraction bits 3 the coefficients Notes to Table 3 6 1 The size of the coefficient grid changes to match the filter size when this option is changed 2 The values in the coefficient grid change when you select a different coefficient set 3 Editing these values change the actual coefficients and summands and the results values on the General page Signed coefficients allow negative values increasing the integer bits increases the magnitude range and increasing the fraction bits increases the precision Simple Smoothing Coefficient set 2 Simple Sharpening Custom Enable symmetric mode 9 25 or 49 fixed Coefficients 2 point values 0 35 Default 0 0 35 Default 6 SYS a 2D Median Filter Table 3 7 shows the 2D Median Filter MegaCore function parameters Table 3 7 2D Median Filter Filter Parameter Settings
216. ll the inputs and is started once the output frame is completed A large number of samples may have to be discarded during the operation and backpressure can be applied for a long time on most input layers Consequently this error recovery mechanism could trigger an overflow at the input of the system In the Scaler MegaCore function the ratio of reads to writes is proportional to the scaling ratio and occurs on both a per pixel and a per line basis The frequency of lines where reads and writes occur is proportional to the vertical scaling ratio For example scaling up vertically by a factor of 2 results in the input being stalled every other line for the length of time it takes to write one line of output scaling down vertically by a factor of 2 results in the output being stalled every other line for the length of time it takes to read one line of input Ina line that has both input and output active the ratio of reads and writes is proportional to the horizontal scaling ratio For example scaling from 64x64 to 128x128 causes 128 lines of output where only 64 of these lines have any reads in them For each of these 64 lines there are two writes to every read The internal latency of the Scaler depends on the scaling algorithm and whether any run time control is enabled The scaling algorithm impacts stalling as follows m Innearest neighbor mode the delay from input to output is just a few clock cycles m Inbilinear mode a complete li
217. lled frame dropping or repeating to keep the input and output frame rates locked together The Frame Buffer also supports buffering of interlaced video streams The Clipper Frame Buffer and Color Plane Sequencer MegaCore functions now support November 2009 9 1 four channels in parallel The Deinterlacer MegaCore function supports a new 4 2 2 motion adaptive mode and an option to align read write bursts on burst boundaries The Line Buffer Compiler MegaCore function has been obsoleted m The Interfaces chapter has been re written m The Deinterlacer MegaCore function supports controlled frame dropping or repeating to keep the input and output frame rates locked together March 2009 8 0 The Test Pattern Generator MegaCore function can generate a user specified constant color that can be used as a uniform background Preliminary support for Arria GX devices How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact Note 1 Contact Method Address Technical support Website www altera com support 2 Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Non technical support General Email nacomp altera com Software Licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative
218. llel Include Avalon MM On or Off Turn on if you want to specify clipping offsets using the Avalon MM interface Clipping method Offsets Rectangle Choose whether to specify the clipping area as offsets from the edge of the input area or as a fixed rectangle Specify the x coordinate for the left edge of the clipping rectangle 0 is Left offset positive integer Default 10 the left edge of the input area 1 _ Specify the x coordinate for the right edge of the clipping rectangle 0 Right offset positive integer Default 10 is the right edge of the input area 1 Width positive integer Default 10 Specify the width of the clipping rectangle Top offset positive integer Default 10 Specify the y coordinate for the top edge of the clipping rectangle 0 is the top edge of the input area 2 Bottom offset positive integer Default 10 Specify the y coordinate for the bottom edge of the clipping rectangle 0 is the bottom edge of the input area 2 Height positive integer Default 10 Specify the height of the clipping rectangle Notes to Table 3 12 1 The left and right offset values must be less than or equal to the input image width 2 The top and bottom offset values must be less than or equal to the input image height Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 3 Parameter Settings Deinterlacer Deinterlacer
219. m of two values The sum is then weighted proportionally to these errors Note that because the values are measured from the top left pixel the weights for this pixel are one minus the error 2 Bg Bry That is in fixed point precision 2 err and 2 err The sum is then Brot Bg 1 Bg Bs Bry OJ 2 F in inj x 2 err x 2 F in 1 2 F in in 1 x 2 P err x err F in 1 in 1 X err X err Polyphase and Bicubic Algorithms The polyphase and bicubic algorithms offer the best image quality but use more resources than the other modes of the scaler They allow up scaling to be performed in such a way as to preserve sharp edges but without losing the smooth interpolation effect on graduated areas Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 15 Scaler For down scaling a long polyphase filter can reduce aliasing effects The bicubic and polyphase algorithms use different mathematics to derive their filter coefficients but the implementation of the bicubic algorithm is just the polyphase algorithm with four vertical and four horizontal taps In the following discussion all comments relating to the polyphase algorithm are applicable to the bicubic algorithm assuming 4x4 taps Figure 5 4 on page 5 15 shows the flow of data through an instance of the scaler in polyp
220. mbinational Logic Memory DSP Blocks fux LUTs ALUTs Registers Bits M9K 9x9 18x18 MHz Stratix 2 4 950 7 296 16 896 6 270 Notes to Table 1 8 1 EP3C10F256C6 devices 2 EP3SE50F780C2 devices 3 EP3C16F484C6 devices Alpha Blending Mixer Table 1 9 shows the performance figures for the Alpha Blending Mixer Table 1 9 Alpha Blending Mixer Performance Device Family Combinational Logic Memory DSP Blocks fmax LUTs ALUTs Registers Bits M9K 9x9 18x18 MHz Alpha blending an on screen display within a region of 1 024x768 pixel 10 bit Y CbCr 4 4 4 video Alpha blending is performed using 16 levels of opacity from fully opaque to fully translucent Cyclone III 1 1 103 764 752 1 4 178 Stratix 2 797 733 752 1 3 319 Drawing a picture in picture window over the top of a 128x128 pixel background image in 8 bit R G B color Cyclone III 7 735 492 752 1 211 Stratix 2 609 548 752 1 354 Rendering two images over 352x240 pixel background 8 bit R G B video Cyclone III 7 1 207 760 752 1 189 Stratix 2 853 758 752 1 325 Using alpha blending to composite three layers over the top of PAL resolution background video in 8 bit monochrome Alpha blending is performed using 256 levels of opacity from fully opaque to fully translucent Cyclone III 1 1 924 1 300 752 1 6 169 Stratix 2 1 428 1 205 752 1 6 276 Notes to Table 1 9 1 EP3C10F256C6 devices 2 EP3SE50F780C2
221. me based method This description shows how the filter kernel is applied and how coefficients are loaded but is not intended to indicate how the hardware of the scaler is designed The filtering part of the polyphase scaler works by passing a windowed sinc function over the input data For up scaling this function performs interpolation For down scaling it acts as a low pass filter to remove high frequency data that would cause aliasing in the smaller output image During the filtering process the mid point of the sinc function should be at the mid point of the pixel to output This is achieved be applying a phase shift to the filtering function If a polyphase filter has N vertical taps and horizontal taps the filter is x square filter Counting the coordinate space of the filter from the top left corner 0 0 the mid point of the filter lies at N 1 2 N 1 2 As in the bilinear case to produce an output pixel at i j the mid point of the kernel is placed at Lin Linj where in and in are calculated using the algorithmic description equations on page 5 14 The difference between the real and integer solutions to these equations determines the position of the filter function during scaling The filter function is positioned over the real solution by adjusting the function s phase vidis EX Wip Wout X Py max wi Wout phase Uti elo max h Aout The results of the
222. mends feeding Test Pattern Generator progressive video output into the Interlacer MegaCore function Table 5 26 Test Pattern Generator Avalon ST Video Protocol Parameters Parameter Frame Width Value Width selected in the MegaWizard interface Can be run time controlled in which case the value specified in the GUI is the maximum allowed value Frame Height Height selected in the MegaWizard interface Can be run time controlled in which case the value specified in the GUI is the maximum allowed value Interlaced i Progressive Mode selected in the MegaWizard interface Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface Color Space As selected in the MegaWizard interface RGB 4 4 4 subsampling only or YCbCr Color Pattern For RGB sequential data For RGB parallel data G For 4 4 4 sequential data For 4 2 2 sequential data E Cb For 4 2 0 sequential data H For 4 2 2 parallel data r For 4 4 4 parallel data For 4 2 0 parallel data Notes to Table 5 26 1 4 2 2 and 4 2 0 subsampling are not available for the RGB color space 2 Vertical subsampling and interlacing cannot be used when the height of the output is not even The GUI does not allow such a parameterization and the behavior of the MegaCore function is undefined if the height is subsequently set to an odd value through the run
223. n MM writedata bus These input lines are used bcm for write transfers 1 dnce If din port Avalon ST data bus Pixel data is transferred into the MegaCore function over this bus eter m din port Avalon ST endofpacket signal This signal marks the end of an Avalon ST packet din daddy Out din port Avalon ST ready signal This signal indicates when the MegaCore function is ready to receive data July 2010 Altera Corporation Video and Image Processing Suite User Guide 6 8 Table 6 8 Clipper Signals Part 2 of 2 Chapter 6 Signals Deinterlacer Signal Direction Description din port Avalon ST startofpacket signal This signal marks the start of din startofpacket In an Avalon ST packet din port Avalon ST valid signal This signal identifies the cycles when the In port should input data ER Out din port Avalon ST data bus Pixel data is transferred out of the MegaCore Berens function over this bus _ dout port Avalon ST endofpacket signal This signal marks the end of an dout endofpacket Out Avalon ST packet Re euis In dout port Avalon ST ready signal This signal is asserted by the downstream device when it is able to receive data _ dout port Avalon ST startofpacket signal This signal marks the start of dout startofpacket Out an Avalon ST packet dout valid Out dout port Avalon ST valid signal This signal is asserted when the MegaCore func
224. n ST Video Protocol section under Interfaces for a description of the difference between sequential and parallel color plane transmission formats inferianed viden On or Off Turn on if you want to use interlaced video If on you can set the additional Interlaced and Field 0 Parameters Sync signals Embedded in video On separate wires Choose whether the synchronization signal is embedded in the video stream or provided on a separate wire If you choose Embedded in video you can set the active picture line horizontal blanking and vertical blanking values If you choose On separate wires you can set horizontal and vertical values for sync front porch and back porch e 0 65 536 Active picture line Default 0 Choose the start of active picture line for Frame Frame Field 1 Ancillary 0 65 536 packet insertion line Default 0 Choose the line where ancillary packet insertion starts Frame Field 1 0 65 536 Choose the size of the horizontal blanking period in pixels for Frame Field Horizontal blanking Default 0 1 Frame Field 1 Vertical 0 65 536 mw blanking Default 0 Choose the size of the vertical blanking period in pixels for Frame Field 1 Frame Field 1 1 65 536 Choose the size of the horizontal synchronization period in pixels for Horizontal sync Default 60 Frame Field 1 Frame Field 1 1 65 536 Choose the size of the horizontal front porch period in
225. n ST Video input July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 44 Chapter 5 Functional Descriptions Clocked Video Output The format of the video frame is shown in Figure 5 15 for progressive and Figure 5 16 on page 5 45 for interlaced Figure 5 15 Progressive Frame Format Horizontal Sync FO Active Picture 2 GG j D S c wo GZ S S 5 a Width e 8 y gt Vertical Blanking Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 45 Clocked Video Output Figure 5 16 Interlaced Frame Format Horizontal Sync FO Active Picture Height Width Field F1 Active Picture Width Height eig Y Vertical Sync VAA Embedded Synchronization Format For the embedded synchronization format the MegaCore function inserts the horizontal and vertical syncs and field into the data stream during the horizontal blanking period Table 5 14 on page 5 36 A sample is output for each clock cycle on the vid data bus There are two extra signals t
226. n time to prevent the interlacing and propagate a progressive video stream without modification Table 7 12 on page 7 7 describes the control register map for the Interlacer MegaCore function At start up or after a change of input resolution the Interlacer begins the interlaced output stream by dropping odd lines to construct a FO field or by dropping even lines to construct a F1 field based on the compile time parameters you specify Alternatively when Control packets override field selection is on and the interlace nibble indicates that the progressive input previously went through a deinterlacer 0000 or 0001 the Interlacer produces a FO field if the interlace nibble is 0000 and a F1 field if the interlace nibble is 0001 For more information refer to Table 4 4 on page 4 8 For most systems turn off Control packets override field selection to guarantee the Interlacer function produces a valid interlaced video output stream where FO and F1 fields alternate in regular succession The Interlacer MegaCore function can process streams of pixel data of the types shown in Table 5 11 The Interlacer does not support vertically subsampled video streams For example 4 2 2 is supported but 4 2 0 is not Table 5 11 Interlacer Avalon ST Video Protocol Parameters Parameter Value Frame Width Run time controlled Maximum value specified in the MegaWizard interface Frame Height Run time controlled Maximum value specified in the Meg
227. nals Part 2 of 2 Signal Direction Description dinN port Avalon ST data bus Pixel data is transferred into the MegaCore dinN data In function over this bus dinN_endofpacket In dinN port Avalon ST endofpacket signal This signal marks the end of an Avalon ST packet ead Out din port Avalon ST ready signal This signal indicates when the MegaCore function is ready to receive data sn nnns dinN port Avalon ST startofpacket signal This signal marks the start of an Avalon ST packet dinN valid dinN port Avalon ST valid signal This signal identifies the cycles when the port should input data doutN port Avalon ST data bus Pixel data is transferred out of the MegaCore doutN data Out i function over this bus doutNendofpacket Out doutN port Avalon ST endofpacket signal This signal marks the end of an Avalon ST packet _ doutN port Avalon ST ready signal This signal is asserted by the downstream doutN ready In MSS device when it is able to receive data doutN port Avalon ST startofpacket signal This signal marks the start of an doutN startofpacket Out Avalon ST packet sul odd Out dout port Avalon ST valia signal This signal is asserted when the MegaCore function outputs data Test Pattern Generator Table 6 16 shows the input and output signals for the Test Pattern Generator MegaCore function Table 6 16 Test Pattern Generat
228. nction supports both 8 and 10 bit TRS and XYZ words When in 10 bit mode the bottom 2 bits of the TRS and XYZ words are ignored to allow easy transition from an 8 bit system The XYZ word contains the synchronization information and the relevant bits of it s format are shown in Table 5 14 Table 5 14 XYZ Word Format 10 bit 8 bit Description 5 0 3 0 These bits are not inspected by the Clocked Video Input MegaCore function H sync 6 4 When 1 the video is in a horizontal blanking period V sync 7 5 When 1 the video is in a vertical blanking period F field 8 6 When 1 the video is interlaced and in field 1 When 0 the video is either progressive or interlaced and in field O nused 9 7 These bits are not inspected by the Clocked Video Input MegaCore function For the embedded synchronization format the vid datavalid signal indicates a valid BT656 or BT1120 sample as shown in Figure 5 12 The Clocked Video Input MegaCore function only reads the vid data signal when vid datavalidis 1 Figure 5 12 vid datavalid Timing vid datavalid The Clocked Video Input MegaCore function extracts any ancillary packets from the Y channel during the vertical blanking Ancillary packets are not extracted from the horizontal blanking The extracted packets are output via the Clocked Video Input s Avalon ST output with a packet type of 13 0xD For information about Avalon ST Video ancillary dat
229. nction variation Use this file when using a third party EDA tool to synthesize your design variation name syn A timing and resource estimation netlist for use in some third party synthesis tools Note to Table 2 2 1 The variation name prefix is added automatically using the base output file name you specified in the MegaWizard interface Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 2 Getting Started with Altera IP Cores 2 9 Generated Files July 2010 Altera Corporation Video and Image Processing Suite User Guide 2 10 Chapter 2 Getting Started with Altera IP Cores Generated Files Video and Image Processing Suite User Guide July 2010 Altera Corporation 3 Parameter Settings This chapter describes the parameter settings for each Video and Image Processing Suite MegaCore function Throughout the chapter bold text in the tables indicates default parameter values Set the parameters in the MegaWizard interface as described in Chapter 2 Getting Started with Altera IP Cores The MegaWizard interface allows you to select only legal combinations of parameters and warns you of any invalid configurations Figure 3 1 shows an example of the MegaWizard Plug In Manager for the FIR Filter 2D MegaCore function The example shows the General page of the Parameter Settings tab Figure 3 1 General Page of the Parameter Settings Tab of the 2D FIR Filter MegaWizard Interf
230. ncy Summary Latency MegaCore Function Mode Latency Note 1 Color Space Converter All modes O cycles Input format 4 2 2 Output format 4 4 4 O cycles Chroma Resampler Input format 4 2 0 Output format 4 4 4 or 4 2 2 1 line O cycles Gamma Corrector All modes O cycles 2D FIR Filter Filter size M x V A 1 lines 0 cycles 2D Median Filter Filter size M x V A 1 lines 0 cycles Alpha Blending Mixer All modes O cycles Scaling algorithm Polyphase Deinterlacer Scaler N 1 lines 0 cycles Number of vertical taps M um HON Clipper All modes O cycles Method Bob cycles Frame buffering None Method Motion adaptive or Weave Frame buffering Double or triple buffering with rate conversion Output frame rate As input frame rate 1 frame 0 lines Method Motion adaptive or Weave Frame buffering Double or triple buffering with rate conversion Output frame rate As input field rate 1 field 0 lines Method All Frame buffering Double or triple buffering with rate conversion Passthrough mode propagate progressive frames unchanged On 1 frame 0 lines Interlacer All modes O cycles Frame Buffer All modes 1 frame 0 lines Color Plane Sequencer All modes O cycles Synchronization signals Embedded in video e 8 cycles Video in and out use the same clock On Clocked Video Input 2 T
231. ne of input is read into a buffer before any output is produced At the end of a frame there are no reads as this buffer is drained Exactly how many writes are possible during this time depends on the scaling ratio m Inbicubic mode three lines of input are read into line buffers before any output is ready As with linear interpolation there is a scaling ratio dependent time at the end of a frame where no reads are needed as the buffers are drained m In polyphase mode with N vertical taps N 1 lines of input are read into line buffers before any output is ready As with bilinear mode there is a scaling ratio dependent time at the end of a frame where no reads are needed as the buffers are drained Enabling run time control of coefficients and or resolutions affects stalling between frames m With no run time control there is only a few cycles of delay before the behavior described in the previous list begins m Enabling run time control of resolutions in nearest neighbor mode adds about 20 clock cycles of delay between frames In other modes it adds a maximum of 60 cycles delay m Enabling run time control of coefficients adds a constant delay of about 20 cycles plus the total number of coefficients to be read For example 16 taps and 32 phases in each direction would add a delay of 20 2 16 x 32 1024 cycles July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 70 Chapter 5 Functional Descriptions
232. nificant bits Control data packet type identifier 4 bits in least significant symbol X s for unused symbols Figure 4 10 One Symbol in Parallel Control data reference numbers to Table 4 5 Start g End 5 1 2 4 5 LAH Control data packet type identifier 4 bits in least significant symbol X s for unused symbols Ancillary Data Packets Ancillary data packets send ancillary packets between MegaCore functions Ancillary data packets are typically placed between a control data packet and a video data packet and contain information that describes the video data packet for example active format description codes An ancillary data packet can contain one or more ancillary packets each ancillary packet starts with the code 0 3FF 3FF Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 4 Interfaces 4 11 Avalon ST Video Protocol The format of ancillary packets is defined in the SMPTE S291M standard MegaCore functions are not required to understand or process ancillary data packets but must forward them on as is done with user defined and Altera reserved packets Figure 4 11 shows an example of an Avalon ST Video Ancillary Data Packet containing two ancillary packets Figure 4 11 Avalon ST Video Ancillary Data Packet PLO LL van os pen pr ie ps pe r eop a x don t care User Defined and Altera Reserved Packets The
233. not known when this change will propagate through the Frame Buffer to the Scaler Figure 5 26 Figure 5 26 Changing Video Width Avalon MM Master Avalon MM Control Synchronizer Avalon MM Frame Buffer Test Pattern Generator Avalon MM Nios Il CPU Red Line Indicates Control Data Packet and Video Data Packet Pair Number 5 Width 320 Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 1 Width 640 Control Data Packet and Video Data Packet Pair Numbers 2 3 and 4 are Stored in the Frame Buffer Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 63 Control Synchronizer 3 The Video Data Packet and Control Data Packet pair with changed width of 320 have propagated through the Frame Buffer The Control Synchronizer has detected the change and triggered a write to the Scaler The Control Synchronizer has stalled the video processing pipeline while it performs the write as shown in Figure 5 27 Figure 5 27 Test Pattern Generator Change Control Synchronizer Writes the Data to the Specified Addresses This Configures the Scaler to an Output Width of 320 Avalon MM Avalon MM Master Test Pattern Control Generator Synchronizer Avalon MM Avalon MM Nios Il CPU Red Line Indicates Control Data Packet and Video Data Packet Pair Number 14 Width 320
234. ns are not ready for a few clock cycles in between rows of image data or in between video frames For further details of each MegaCore function refer to the Functional Descriptions on page 5 1 The MegaCore function sets din ready to logic 1 indicating that the input port is ready to receive data one clock cycle later The number of clock cycles of delay which should be applied to a ready signal is referred to as ready latency in the Avalon Interface Specifications All of the Avalon ST interfaces that the Video and Image Processing Suite uses have a ready latency of one clock cycle The source feeding the input port sets din valid to logic 1 indicating that it is sending data on the data port and sets din startofpacket to logic 1 indicating that the data is the first value of a new packet The data is 0 indicating that the packet is video data The source feeding the input port holds din_valid at logic 1 and drops din_startofpacket indicating that it is now sending the body of the packet It puts all three color values of the top left pixel of the frame on to din_data No data is transmitted for a cycle even though din ready was logic 1 during the previous clock cycle and therefore the input port is still asserting that it is ready for data This could be because the source has no data to transfer For example if the source is a FIFO it could have become empty Data transmission resumes on the input port din_valid transitions to
235. ns in the Video and Image Processing Suite use standard interfaces for data input and output control input and access to external memory These standard interfaces ensure that video systems can be quickly and easily assembled by connecting MegaCore functions together The functions use the following types of interfaces m Avalon ST interface a streaming interface that supports backpressure The Avalon ST Video protocol transmits video and configuration data This interface type allows the simple creation of video processing data paths where MegaCore functions can be connected together to perform a series of video processing functions m Avalon MM slave interface provides a means to monitor and control the properties of the MegaCore functions m Avalon MM master interface when the MegaCore functions require access to a slave interface for example an external memory controller Specifications For more information about these interface types refer to the Avalon Interface Figure 4 1 shows an example of video processing data paths using the Avalon ST and Avalon MM interfaces This abstracted view is similar to that provided in the SOPC Builder tool where interface wires are grouped together as single connections Figure 4 1 Abstracted Block Diagram Showing Avalon ST and Avalon MM Connections High Performance DDR 2 Memory Controller MegaCore Function Avalon ST Connection lt gt Avalon MM
236. nterconnect fabric to cause the master port to wait master av reset master port reset signal The interface is reset asynchronously when this signal is asserted high and must be de asserted synchronously with respect to the rising edge of the clock signal master av clock master port The clock signal The interface operates on the rising edge of the clock signal Frame Buffer Table 6 12 shows the input and output signals for the Frame Buffer MegaCore function Table 6 12 Frame Buffer Signals Part 1 of 3 Signal Direction Description m In The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is reset In asserted high The reset must be de asserted synchronously with respect to the rising edge of the clock signal in din port Avalon ST data bus Pixel data is transferred into the MegaCore function over this bus din port Avalon ST endofpacket signal This signal marks the endotpacker i end of an Avalon ST packet din port Avalon ST ready signal This signal indicates when the om MegaCore function is ready to receive data din port Avalon ST startofpacket signal This signal marks the den ice start of an Avalon ST packet din Avalon ST valid signal This signal identifies the cycles when the port should inp
237. number of integer fraction and sign bits specified in the MegaWizard interface and have their fraction part multiplied out The sum of any two coefficients in the same phase must also be in the declared range For example if there is 1 integer bit 7 fraction bits and a sign bit each value and the sum of any two values should be in the range 256 255 representing the range 2 1 9921875 In summary you can generate a set of coefficients for an N tap P phase instance of the Scaler as follows 1 Define a function f x over the domain 0 N 1 under the assumption that N 1 2 is the mid point of the filter 2 For each tap t 0 1 N 1 and for each phase p 0 1 P P 1 P j sample f t p 3 Quantize each sample Ideally the sum of the quantized values for all phases should be equal 4 Either store these in a CSV file and copy them into the MegaWizard interface or load them at run time using the control interface Coefficients for the bicubic algorithm are calculated using Catmull Rom splines to interpolate between values in tap 1 and tap 2 Te For more information about the mathematics for Catmull Rom splines refer to E Catmull and R Rom A class of local interpolating splines Computer Aided Geometric Design pages 317 326 1974 The bicubic method does not use the preceding steps but instead obtains weights for each of the four taps to sample a cubic function that runs between tap 1 and tap 2
238. of transfers in each burst wri Le mas ter av clock write master port clock signal The interface operates on the rising edge of the clock signal 1 wri Le mas ter av reset write master port reset signal The interface is reset asynchronously when this signal is asserted high and must be de asserted synchronously with respect to the rising edge of the clock signal 1 wri Le mas ter av waitrequest write master port Avalon MM waitrequest signal Asserted by the system interconnect fabric to cause the master port to wait wri Le mas ter av write Out write master port Avalon MM write signal Asserted to indicate write requests from the master to the system interconnect fabric wri Le mas ter av writedata Out write master port Avalon MM writedata bus These output lines carry data for write transfers wri ter control av chipselect writer control slave port Avalon MM chipselect signal The writer_control port ignores all other signals unless this signal is asserted 3 Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 6 Signals Clocked Video Input 6 15 Table 6 12 Frame Buffer Signals Part 3 of 3 Signal writer control readdata Direction Description writer control slave port Avalon MM readdata bus These But output lines are used for read transfers 3 writer contr
239. ol On or Off Turn on to enable run time control Turn on when the content of the control packet specifies which Control packets override On or Off lines to drop when converting a progressive frame into an interlaced field July 2010 Altera Corporation Video and Image Processing Suite User Guide 3 14 Frame Reader Chapter 3 Parameter Settings Frame Reader Table 3 15 shows the Frame Reader parameters Table 3 15 Frame Reader Parameter Settings Parameter Value Description Bits per pixel per color plane 4 16 Default 8 The number of bits used per pixel per color plane Number of color planes in parallel 1 4 Default 3 The number color planes transmitted in parallel Number of color planes in sequence 1 3 Default 3 The maximum number of color planes transmitted in sequence Maximum image width 32 2600 Default 640 The maximum width of images video frames Maximum image height 32 2600 Default 480 The maximum height of images video frames Master port width 16 256 Default 256 The width in bits of the master port Read master FIFO depth 1 64 Default 64 The depth of the read master FIFO Read master FIFO burst target 2 256 Default 32 The target burst size of the read master Use separate clock for the Avalon MM master interface On or Off Use separate clock for the Avalon MM master interface Frame Buffer Table 3 1
240. ol av write writer control Slave port Avalon MM write signal When this In signal is asserted the writer control port accepts new data from the writedata bus 3 writer_control_av_writedata writer_control slave port Avalon MM writedata bus These input lines are used for write transfers 3 Notes to Table 6 12 1 Additional clock and reset signals are available when Use separate clocks for the Avalon MM master interfaces is on in the MegaWizard interface 2 These ports are present only if the control interface for the reader component has been enabled 3 These ports are present only if the control interface for the writer component has been enabled Clocked Video Input Table 6 13 shows the input and output signals for the Clocked Video Input MegaCore function Table 6 13 Clocked Video Input Signals Part 1 of 2 Signal Direction Description The MegaCore function is asynchronously reset when rst is asserted high The rst In reset must be de asserted synchronously with respect to the rising edge of the is clk signal vid clk In Clocked video clock All the video input signals are synchronous to this clock SE control slave port Avalon MM address bus Specifies a word offset into the slave address space 7 r lh control Slave port Avalon MM read signal When this signal is asserted the control port drives new data onto the read data bu
241. ome Scaler parameterizations go 0 while true read non image data packets status 0 while go 1 wait read control Copies control to internal registers status 1 send image data header process frame The Gamma Corrector does not double buffer its control data but the algorithm described in the previous paragraph is still largely applicable Most Video and Image Processing Suite MegaCore functions with a slave interface read and propagate non image data packets from the input stream until the image data header 0 of an image data packet has been received The status bit is then set to 0 and the MegaCore function waits until the Go bit is set to 1 if it is not already Once the Go bit is set to 1 the MegaCore function buffers control data sets its status bit back to 1 and starts processing image data 57 There is a small amount of buffering at the input of each Video and Image Processing Suite MegaCore function and you should expect that a few samples are read and stored past the image data header even if the function is stalled You can use the Go and Status registers in combination to synchronize changes in control data to the start and end of frames For example suppose you want to build a system with a Gamma Corrector MegaCore function where the gamma look up table is updated between each video frame You can build logic or program a Nios II processor to control the gamma corrector as foll
242. ond to changes of resolution in control packets Input image width 32 2600 Default 1 024 Choose the required input width in pixels Input image height 32 2600 Default 768 Choose the required input height in pixels Output image width 32 2600 Default 640 Choose the required output width in pixels Output image height 32 2600 Default 480 Choose the required output height in pixels Bits per pixel per color plane 4 20 Default 8 Choose the number of bits per pixel per color plane The number of color planes that are sent over one data Number of color planes 1 3 Default 3 connection For example a value of 3 for R G B R G B R G B in serial Color planes transmission The transmission mode used for the specified number of color forat Sequence Parallel planes Table 3 10 Scaler Parameter Settings Tab Algorithm and Precision Page Part 1 of 2 Parameter Scaling Algorithm Value Nearest Neighbor Bilinear Bicubic Polyphase Description Choose the scaling algorithm For more information about these options refer to pages 5 13 to 5 14 Number of vertical taps 1 3 16 Default 4 Specify the number of vertical taps Number of vertical phases 2 4 8 16 32 64 128 256 Specify the number of vertical phases Number of horizontal taps 1 3 16 Default 4 Specify the number of horizontal taps
243. onds to the mid point of the kernel If the kernel runs over the edge of an image the function uses zeros for the out of range pixels The 2D FIR Filter allows its input output and coefficient data types to be fully defined Constraints are 4 to 20 bits per pixel per color plane for input and output and up to 35 bits for coefficients The 2D FIR Filter supports symmetric coefficients This reduces the number of multipliers resulting in smaller hardware Coefficients can be set at compile time or changed at run time using an Avalon MM slave interface Calculation Precision The 2D FIR Filter does not lose calculation precision during the FIR calculation The calculation and result data types are derived from the range of input values as specified by the input data type or input guard bands if provided the coefficient fixed point type and the coefficient values If scaling is selected then the result data type is scaled up appropriately such that precision is not lost Coefficient Precision The 2D FIR Filter requires a fixed point type to be defined for the coefficients The user entered coefficients shown as white boxes in the MegaWizard interface are rounded to fit in the chosen coefficient fixed point type shown as purple boxes in the MegaWizard interface Result to Output Data Type Conversion After the calculation the fixed point type of the results must be converted to the integer data type of the output Video and Ima
244. ons and the Quartus II software Refer also to the following references Video and Image Processing Suite User Guide July 2010 Altera Corporation Additional Information Referenced Documents July 2010 Altera Corporation Info 3 International Telecommunications Union Geneva Recommendation ITU R BT 601 Encoding Parameters of Digital Television for Studios 1992 Ken Turkowski Graphics gems chapter Filters for common resampling tasks pages 147 165 Academic Press Professional Inc San Diego CA USA 1990 E Catmull and R Rom A class of local interpolating splines Computer Aided Geometric Design pages 317 326 1974 MegaCore IP Library Release Notes and Errata AN 320 OpenCore Plus Evaluation of Megafunctions AN427 Video and Image Processing Up Conversion Example Design Quartus II Installation amp Licensing for Windows and Linux Workstations Simulating Altera IP in Third Party Simulation Tools chapter in volume 3 of the Quartus II Handbook Volume 4 SOPC Builder of the Quartus II Handbook Avalon Interface Specifications Video and Image Processing Suite User Guide Info 4 Additional Information Referenced Documents Video and Image Processing Suite User Guide July 2010 Altera Corporation
245. ontrol over the routing of color plane samples Test Pattern Generator The Test Pattern Generator generates a video stream that displays either still color bars for use as a test pattern or a constant color for use as a uniform background You can use this MegaCore function during the design cycle to validate a video system without the possible throughput issues associated with a real video input Control Synchronizer Switch You can use the Control Synchronizer MegaCore function to synchronize the configuration change of MegaCores with an event in a video stream For example this MegaCore function could synchronize the changing of a position of a video layer with the changing of the size of the layer The Switch MegaCore function allows the connection of up to twelve input video streams to twelve output video streams and the run time reconfiguration of those connections via a control input Design Example A provided design example offers a starting point to quickly understand the Altera video design methodology enabling you to build full video processing systems on an FPGA For more information about this design example refer to AN427 Video and Image Processing Up Conversion Example Design MegaCore Verification Before releasing a version of each MegaCore function Altera runs comprehensive regression tests to verify quality and correctness Custom variations of the MegaCore functions exercise various parameter options The
246. or Signals Part 1 of 2 Signal Direction Description The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is asserted reset In high The reset must be de asserted synchronously with respect to the rising edge of the clock signal control Slave port Avalon MM address bus Specifies a word offset into clock In trol In control av address the slave address space 1 _ control slave port Avalon MM chipselect signal The control port control av chipselect In ipd ignores all other signals unless this signal is asserted 1 control slave port Avalon MM readdata bus These output lines are used control av readdata Out for read transfers 1 _ control Slave port Avalon MM write signal When this signal is asserted control av write In the control port accepts new data from the writedata bus 7 control Slave port Avalon MM writedata bus These input lines are used control writedata In for write transfers 1 _ dout port Avalon ST data bus Pixel data is transferred out of the MegaCore dout data Out function over this bus July 2010 Altera Corporation Video and Image Processing Suite User Guide 6 20 Chapter 6 Signals Control Synchronizer Table 6 16 Test Pattern Generator Signals Part 2 of 2 Signal Direction Description _ dout port
247. ot be turned on if you are not using either two channels in sequence or two channels in parallel July 2010 Altera Corporation Video and Image Processing Suite User Guide 3 12 Chapter 3 Parameter Settings Deinterlacer Table 3 13 Deinterlacer Parameter Settings Part 2 of 3 Parameter Value Description Turn on to compare the motion value with the corresponding motion value for the same location in the previous frame If it is Motion bleed On or Off greater the new value is kept but if the new value is less than the stored value the motion value used is the mean of the two values This reduces unpleasant flickering artefacts but increases the memory usage and memory bandwidth requirements 2 Turn on to add an Avalon MM slave interface that controls the Rundimecontrolof ithe behavior of the motion adaptive algorithm at run time The pixel motion adantiv bl ndin On or Off based motion value computed by the algorithm can be replaced p 0 by a user selected frame based motion value that varies between the two extremes of being entirely bob or entirely weave 4 6 Number of packets 1 32 Specify the number of packets that can be buffered with each buffered per field field Older packets are discarded first in case of an overflow 5 Choose the maximum packet length as a number of symbols The Maximum packet length 10 1024 minimum value is 10 because this is the size of an Avalon ST p 0 control packet header
248. ows 1 Set the Go bit to zero This causes the MegaCore function to stop processing at the end of the current frame 2 Poll the Status bit until the MegaCore function sets it to zero This occurs at the end of the current frame after the MegaCore function has stopped processing data 3 Update the gamma look up table 4 Setthe Go bit to one This causes the MegaCore function to start processing the next frame 5 Poll the Status bit until the MegaCore function sets it to one This occurs when the MegaCore function has started processing the next frame and therefore setting the Go bit to zero causes it to stop processing at the end of the next frame Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 4 Interfaces 4 19 Avalon MM Slave Interfaces 6 Repeat steps 1 to 5 until all frames are processed This procedure ensures that the update is performed exactly once per frame and that the MegaCore function is not processing data while the update is performed When using MegaCore functions which double buffer control data such as the Alpha Blending Mixer and Scaler a more simple process may be sufficient 1 Setthe Go bit to zero This causes the MegaCore function to stop if it gets to the end of a frame while the update is in progress 2 Update the control data 3 Setthe Go bit to one The next time a new frame is started after the Go bit is set to one the new control data is loaded into the
249. port Avalon MM write signal When this signal is nei es asserted the control port accepts new data from the writedata bus eee M control slave port Avalon MM writedata bus These input lines are Dum used for write transfers In din_N port Avalon ST data bus for port din for layer N Pixel data is transferred into the MegaCore function over this bus din N port Avalon ST endofpacket signal This signal marks the end of ain N endofpacker i an Avalon ST packet i din_N port Avalon ST ready signal This signal indicates when the Uin N acest Out MegaCore function is ready to receive data din N port Avalon ST startofpacket signal This signal marks the start of an Avalon ST packet July 2010 Altera Corporation Video and Image Processing Suite User Guide 6 6 Chapter 6 Signals Scaler Table 6 6 Alpha Blending Mixer Signals Part 2 of 2 Signal Direction Description din N valid In din_N port Avalon ST valid signal This signal identifies the cycles when the port should input data EE Out dout port Avalon ST data bus Pixel data is transferred out of the MegaCore function over this bus _ dout port Avalon ST endofpacket signal This signal marks the end of Out an Avalon ST packet _ dout port Avalon ST ready signal This signal is asserted by the dout ready In T downstream device when it is able to receive data _ dout port Avalon ST st
250. port Avalon ST startofpacket signal This signal is asserted when the SERE downstream device is starting a new frame dout port Avalon ST valid signal This signal is asserted when the downstream device outputs data Start of frame signal A rising edge 0 to 1 indicates the start of the video frame as sof In configured by the SOF registers Connecting this signal to a Clocked Video Input MegaCore function allows the output video to be synchronized to this signal sof_locked Out Start of frame locked signal When high the sof signal is valid and can be used control Slave port Avalon MM interrupt signal When asserted the status registers status update int Out of the MegaCore function have been updated and the master should read them to determine what has occurred 1 Clocked video underflow signal A signal corresponding to the underflow sticky bit underflow Out of the Status register synchronized to vid_clk This signal is for information only and no action is required if it is asserted 1 A divided down version of vid clk vcoclk Setting the Vcoclk Divider vcoclk div Out register to be the number of samples in a line produces a horizontal reference on this signal that a PLL can use to synchronize its output clock July 2010 Altera Corporation Video and Image Processing Suite User Guide 6 18 Chapter 6 Signals Color Plane Sequencer Table 6 14 Clocked Video Output Signals Part 2 of 2
251. r by providing a point to be the top left corner of the active region along with the region s width and height The Clipper can deal with changing input resolutions by reading Avalon ST Video control packets An optional Avalon MM interface allows the clipping settings to be changed at runtime The Clipper MegaCore function can process streams of pixel data of the types shown in Table 5 9 Table 5 9 Clipper Avalon ST Video Protocol Parameters Part 1 of 2 Parameter Frame Width Value Maximum frame width is specified in the MegaWizard interface the actual value is read from control packets Frame Height Maximum frame height is specified in the MegaWizard interface the actual value is read from control packets Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 21 Deinterlacer Table 5 9 Clipper Avalon ST Video Protocol Parameters Part 2 of 2 Parameter Interlaced Progressive Value Either Interlaced inputs are accepted but are treated as progressive inputs Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface Color Pattern Any combination of one two three or four channels in each of sequence or parallel For example if three channels in sequence is selected where and y can be any color plane Deinterlacer The Deinterlacer MegaCor
252. r av reset write master port reset signal The interface is asynchronously reset when reset is asserted high and must be de asserted synchronously with respect to the rising edge of the clock signal 1 3 4 write master av waitrequest write master port Avalon MM waitrequest signal Asserted by the system interconnect fabric to cause the master port to wait 1 3 write master av write Out write master port Avalon MM write signal Asserted to indicate write requests from the master to the system interconnect fabric 1 3 write master av writedata Out write master port Avalon MM writedata bus These output lines carry data for write transfers 7 3 Note to Table 6 9 1 The signals associated with the write master and read master ports are present only when buffering is used 2 When the motion adaptive algorithm is selected two read master interfaces are used 3 When the motion adaptive algorithm is selected and motion bleed is turned on one additional read master notion read master and one additional write master notion write master portare used to read and update motion values 4 Additional clock and reset signals are available when Use separate clocks for the Avalon MM master interfaces is on in the MegaWizard interface 5 The signals associated with the ma cont rol port are not present unless run time control of the motion adaptive blending is enabled
253. r determines whether dropping and repeating of frames or fields is ceased iat tightly controlled by the specified input and output frame rates Setting this bit to 0 4 Rale switches off the controlled rate conversion and returns the triple buffering algorithm to a free regime where dropping and repeating is only determined by the status of the spare buffer Write only register A 16 bit integer value for the input frame rate This register cannot 5 Input Frame Rate be read Write only register A 16 bit integer value for the output frame rate This register cannot 6 Output Frame Rate be read Table 7 15 describes the Frame Buffer MegaCore function control register map for the reader component Table 7 15 Frame Buffer Control Register Map for the Reader Component Address Register s Description Bit 0 of this register is the Go bit all other bits are unused Setting this bit to 0 causes the 0 reader component to stop the next time control information is updated While stopped CM the Frame Buffer may continue to receive and drop frame at its input if frame dropping is enabled Refer to Avalon MM Slave Interfaces on page 4 17 for full details 1 Bit 0 of this register is the Status bit all other bits are unused Refer to Avalon MM ore Slave Interfaces on page 4 17 for full details 2 c Read only register updated at the end of each frame processed by the reader
254. r is the interrupt enable Setting bit 1 to 1 enables the completion of writes interrupt 1 Bit 0 of this register is the Status bit All other bits are unused Refer to ini Slave Interfaces on page 4 17 for full details 2 c Bit 1 of this register is the completion of writes interrupt bit all other bits are unused E Writing a 1 to bit 1 resets the completion of writes interrupt Setting this register to 1 disables the trigger condition of the control synchronizer Setting this register to 0 enables the trigger condition of the control synchronizer When the 3 Disable Trigger compile time option Require trigger reset via control port is enabled this register value is automatically set to 1 every time the Control Synchronizer triggers This register sets how many write operations starting with address and word 0 are 1 Number of writes Written when the control synchronizer triggers 5 Address 0 Address where word 0 should be written on trigger condition 6 Word 0 The word to write to address 0 on trigger condition 7 Address 1 Address where word 1 should be written on trigger condition 8 Word 1 The word to write to address 1 on trigger condition 9 Address 2 Address where word 2 should be written on trigger condition 10 Word 2 The word to write to address 2 on trigger condition 11 Address 3 Address where word 3 should be written on trigger condition 12 Word
255. ra Corporation Chapter 5 Functional Descriptions 5 3 Color Space Converter Result of Output Data Type Conversion After the calculation the fixed point type of the results must be converted to the integer data type of the output This conversion is performed in four stages in the following order 1 Result Scaling You can choose to scale up the results increasing their range This is useful to quickly increase the color depth of the output The available options are a shift of the binary point right 16 to 16 places This is implemented as simple shift operation so it does not require multipliers Removal of Fractional Bits If any fractional bits exist you can choose to remove them There are three methods m Truncate to integer Fractional bits are removed from the data This is equivalent to rounding towards negative infinity Round Half up Round up to the nearest integer If the fractional bits equal 0 5 rounding is towards positive infinity m Round Half even Round to the nearest integer If the fractional bits equal 0 5 rounding is towards the nearest even integer Conversion from Signed to Unsigned If any negative numbers can exist in the results and the output type is unsigned you can choose how they are converted There are two methods m Saturate to the minimum output value constraining to range m Replace negative numbers with their absolute positive value Constrain to Range If any of
256. rame boundary that is before the first field of a pair when the output is interlaced For details of the control register map for the Test Pattern Generator refer to Table 7 18 on page 7 13 Because the Test Pattern Generator does not accept an input stream the pseudo code in Avalon MM Slave Interfaces on page 4 17 is slightly modified go 0 while true status 0 while go 1 wait read_control Copies control to internal register status 1 do once for progressive output or twice for interlaced output send control packet send image data header output test pattern Output Data Types The Test Pattern Generator MegaCore function supports a wide range of resolutions and color spaces with either a sequential or parallel data interface July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 60 Chapter 5 Functional Descriptions Test Pattern Generator In all combinations of color space and subsampling that are allowed the stream of pixel data is of a type consistent with the conventions adopted by the other MegaCore functions in the Video and Image Processing Suite The Test Pattern Generator MegaCore function can output streams of pixel data of the types shown in Table 5 26 The Test Pattern Generator cannot produce interlaced streams of pixel data with an odd frame height To create interlaced video streams where FO fields are one line higher than F1 fields Altera recom
257. ransferred in Parallel 1 2 3 4 5 6 7 n clock B din ready din valid din startofpacket din endofpacket 23 16 din data 15 8 7 0 dout_ready dout_valid dout_startofpacket dout_endofpacket 23 16 dout_data 15 8 7 0 This example has one Avalon ST port named din and one Avalon ST port named dout Data flows into the MegaCore function through din is processed and flows out of the MegaCore function through dout July 2010 Altera Corporation Video and Image Processing Suite User Guide 4 14 Chapter 4 Interfaces Avalon ST Video Protocol There are five signals types ready valid data startofpacket and endofpacket associated with each port The din ready signal is an output from the MegaCore function and indicates when the input port is ready to receive data The din valid and din data signals are both inputs The source connected to the input port sets din validto logic 1 when din data has useful information that should be sampled din startofpacket is an input signal that is raised to indicate the start of a packet with din endofpacket signaling the end of a packet The five output port signals have equivalent but opposite semantics The sequence of events shown in Figure 4 12 is 1 Initially din ready is logic 0 indicating that the MegaCore function is not ready to receive data on the next cycle Many of the Video and Image Processing Suite MegaCore functio
258. rate synchronously to this clock July 2010 Altera Corporation Video and Image Processing Suite User Guide 4 20 Chapter 4 Interfaces Avalon MM Master Interfaces The Avalon Interface Specifications define a set of transfer properties which may or may not be exhibited by any Avalon MM interface Together with the list of supported signals these properties fully define an interface type The control interfaces of the Video and Image Processing Suite MegaCore functions that do not use a waitrequest signal exhibit the following transfer properties m Zero wait states on write operations m Two wait states on read operations Avalon MM Master Interfaces The Video and Image Processing Suite MegaCore functions use a common type of Avalon MM master interface for access to external memory These master interfaces should be connected to external memory resources via arbitration logic such as that Specification of the Type of Avalon MM Master Interfaces IS Video and Image Processing Suite User Guide provided by the system interconnect fabric The Avalon Interface Specifications define many signal types many of which are optional Table 4 11 shows the signals for the Avalon MM master interfaces in the Video and Image Processing Suite Table 4 11 does not show unused signals Table 4 11 Avalon MM Master Interface Signal Types Signal Width Direction Usage clock 1 Input Read Write optional re
259. rce port s that are enabled for non image packets for from port dout0 and dint output port dout 0 Halve control packet width On or Off Turn on to halve the Avalon ST Video control packet width for output 90010 2 3 port dout 0 Color planes in parallel doutO 1 3 Choose the number of color planes in parallel for output port aout 0 ae in sequenge 1 4 Choose the number of color planes in sequence for output port aout 0 Port enabled dout1 On or Off Turn on to enable output port aout 1 Source non image packets dinO din dind Choose the source port used for non image packets for output port dout1 from port dout1 and din1 doutl Halve control packet width On or Off Turn on to halve the Avalon ST Video control packet width for output dout1 port dout1 7 Color planes in parallel dout1 1 3 Choose the number of color planes in parallel for output port dout1 Color planas in sequence 1 4 Choose the number of color planes in sequence for output port dout1 Note to Table 3 19 1 Turn on when treating Cb and Cr separately because two pixels worth of data is required Alternatively you can turn this parameter off and use channel names C Y instead of Cb Y Cr Y 2 This option can be useful if you want to split a subsampled color plane from a fully sampled color plane The subsampled color plane can then be processed by other functions as if fully sampled 3 Turn
260. re 8 bits per sample and one of the predefined conversions inputs B G R din 0 carries B in bits 0 7 din 1 carries G in bits 8 15 and din 2 carries in bits 16 23 Predefined conversions only support unsigned input and output data If signed input or output data is selected the predefined conversion produces incorrect results When using a predefined conversion the precision of the constants must still be defined Predefined conversions are based on the input bits per pixel per color plane If using different input and output bits per pixel per color plane the results should be scaled by the correct number of binary places to compensate Constant Precision The Color Space Converter MegaCore function requires fixed point types to be defined for the constant coefficients and constant summands The user entered constants in the white cells of the matrix in the MegaWizard interface are rounded to fit in the chosen fixed point type these are shown in the purple cells of the matrix Calculation Precision The Color Space Converter MegaCore function does not lose calculation precision during the conversion The calculation and result data types are derived from the range of the input data type the fixed point types of the constants and the values of the constants If scaling is selected the result data type is scaled up appropriately such that precision is not lost Video and Image Processing Suite User Guide July 2010 Alte
261. re pushing and pulling frames at different rates Locked Frame Rate Conversion With the triple buffering algorithm described previously the decision to drop and repeat frames is based on the status of the spare buffer Because the input and output sides are not tightly synchronized the behavior of the Frame Buffer is not completely deterministic and can be affected by the burstiness of the data in the video system This may cause undesirable glitches or jerky motion in the video output especially if the data path contains more than one triple buffer By controlling the dropping repeating behavior the input and output can be kept synchronized To control the dropping repeating behavior and to synchronize the input and output sides you must select triple buffering mode and turn on Run time control for locked frame rate conversion in the Parameter Settings tab of the MegaWizard interface The input and output rates can be selected and changed at run time Using the slave interface it is also possible to enable or disable synchronization atrun time to switch between the user controlled and flow controlled triple buffering algorithms as necessary Table 7 14 on page 7 9 describes the control register maps for the Frame Buffer writer component July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 34 Chapter 5 Functional Descriptions Frame Buffer Interlaced Video Streams In its default configuration the Frame Buff
262. ready been sent by the reader component When the writer has finished storing a frame in memory it swaps its buffer with the spare buffer if the spare buffer is dirty The buffer locked by the writer component becomes the new spare buffer and is clean because it contains a fresh frame If the spare buffer is already clean when the writer has finished writing the current input frame and if dropping frames is allowed then the writer drops the frame that has just been received and overwrites its buffer with the next incoming frame If dropping frames is not allowed the writer component stalls until the reader component has finished its frame and replaced the spare buffer with a dirty buffer Similarly when the reader has finished reading and has output a frame from memory it swaps its buffer with the spare buffer if the spare buffer is clean The buffer locked by the reader component becomes the new spare buffer and is dirty because it contains an old frame that has been sent previously If the spare buffer is already dirty when the reader has finished the current output frame and if repeating frames are allowed the reader immediately repeats the frame that has just been sent If repeating frames is not allowed the reader component stalls until the writer component has finished its frame and replaced the spare buffer with a clean buffer Triple buffering therefore allows simple frame rate conversion to be performed when the input and the output a
263. rizontal synchronization signal This signal is asserted during the horizontal synchronization period of the video stream vid hd sdn Clocked video color plane format selection signal in run time switching of color plane transmission formats mode only This signal distinguishes between sequential when low and parallel when high color plane formats vid locked Clocked video locked signal This signal is asserted when a stable video stream is present on the input This signal is de asserted when the video stream is removed vid std Video Standard bus Can be connected to the rx sta signal of the SDI MegaCore function or any other interface to read from the standard register vid v sync Separate Synchronization Mode Only Clocked video vertical synchronization signal This signal is asserted during the vertical synchronization period of the video stream Note to Table 6 13 1 These ports are present only if Use control port is on in the MegaWizard interface Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 6 Signals Clocked Video Output Clocked Video Output Table 6 14 shows the input and output signals for the Clocked Video Output MegaCore function 6 17 Table 6 14 Clocked Video Output Signals Part 1 of 2 Signal Direction Description The MegaCore function is asynchronously
264. rmation remains the same as in the clocked video format The Clocked Video Input converts clocked video to the flow controlled Avalon ST Video protocol It also provides clock crossing capabilities to allow video formats running at different frequencies to enter the system In addition the Clocked Video Input provides a number of status registers that provide feedback on the format of video entering the system resolution and interlaced or progressive mode and a status interrupt that can be used to determine when the video format changes or is disconnected Video Formats The Clocked Video Input MegaCore function accepts the following clocked video formats m Video with synchronization information embedded in the data in BT656 or BT1120 format m Video with separate synchronization H sync Vsync signals Embedded Synchronization Format The BT656 and BT1120 formats use time reference signal TRS codes in the video data to mark the places where synchronization information is inserted in the data July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 36 Chapter 5 Functional Descriptions Clocked Video Input These codes are made up of values that are not present in the video portion of the data and take the format shown in Figure 5 11 Figure 5 11 Time Reference Signal Format lt 3FFX 0 X TRS 10bit The Clocked Video Input MegaCore fu
265. rough an Avalon MM slave interface Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 3 Parameter Settings Frame Buffer Table 3 16 Frame Buffer Parameter Settings Part 2 of 2 3 15 Parameter Support for interlaced streams Value On or Off Description Turn on to support consistent dropping and repeating of fields in an interlaced video stream This option should not be turned on for double buffering of an interlaced input stream on a field by field basis Number of packets buffered per frame 3 0 32 Specify the maximum number of non image non control Avalon ST Video packets that can be buffered with each frame Older packets are discarded first in case of an overflow Maximum packet length 10 1 024 Specify the maximum packet length as a number of symbols The minimum value is 10 because this is the size of an Avalon ST control packet header included Extra samples are discarded if packets are larger than allowed Use separate clocks for the Avalon MM master interfaces On or Off Turn on to add a separate clock signal for the Avalon MM master interfaces so that they can run at a different speed to the Avalon ST processing This decouples the memory speed from the speed of the data path and is sometimes necessary to reach performance target External memory port width 16 32 64 128 256 Choose the width of the external memory port
266. round layer to the top edge of layer 1 7 Layer 1 is displayed if this control register is set to 1 Data in the input stream is consumed but 4 Layer 1 not displayed if this control register is set to 2 Avalon ST packets of type 2 to 14 are still Active propagated as usual Data from the input stream is not pulled out if this control register is set to 0 1 2 5 Layer 2 X Note to Table 7 6 1 The value of this register is checked at the start of each frame If the register is changed during the processing of a video frame the change does not take effect until the start of the next frame 2 For efficiency reasons the Video and Image Processing Suite MegaCore functions buffer a few samples from the input stream even if they are not immediately processed This implies that the Avalon ST inputs for foreground layers assert ready high and buffer a few samples even if the corresponding layer has been deactivated 3 The rows in the table are repeated in ascending order for each layer from 1 to the foreground layer Scaler Table 7 7 describes the Scaler MegaCore function control register map The control data is read once at the start of each frame and is buffered inside the MegaCore function so the registers may be safely updated during the processing of a frame Note that all Scaler registers are write only except at address 1 Table 7 7 Scaler Control Register Map Part 1 of 2
267. rts a E Default 0 insertion line Interlaced and Field 0 0 65 536 Choose the number of lines in the vertical front porch period for Interlaced Vertical blanking Default 0 and Field 0 Interlaced and Field 0 0 65 536 Choose the number of lines in the vertical back porch period for Interlaced Vertical sync Default 0 and Field 0 Interlaced and Field 0 0 65 536 Choose the number of lines in the vertical front porch period for Interlaced Vertical front porch Default 0 and Field 0 Interlaced and Field 0 0 65 536 Choose the number of lines in the vertical back porch period for Interlaced Vertical back porch Default 0 and Field 0 Pixel FIFO size 32 memory limit Default 1 920 Choose the required FIFO depth in pixels limited by the available on chip memory FIFO level at which to 0 memory limit Choose the fill level that the FIFO must have reached before the output start output Default 0 video starts Video in and out use the On or Off Turn on if you want to use the same signal for the input and output video same clock image stream clocks Use control port On or Off Turn on to use the optional Avalon MM control port Runtime configurable video modes 7 1 14 Default 1 Choose the number of runtime configurable video output modes that are required when you are using the Avalon MM control port Accept synchronization Specifies whether the synchronization outputs are used m
268. ry on Windows is C NalteraN version number on Linux it is opt altera lt version number Figure 2 1 IP core Directory Structure 3 path Installation directory ip Contains the Altera IP Library and third party IP cores altera Contains the Altera IP Library common Contains shared components IP core name or uniPHY Contains the IP core files and documentation You can evaluate an IP core in simulation and in hardware before you purchase a license For most Altera IP cores you can use Altera s free OpenCore Plus evaluation feature for this purpose Some Altera IP cores do not require use of this special feature for evaluation You can evaluate the IP core until you are satisfied with its functionality and performance You must purchase a license for the IP core when you want to take your design to production After you purchase a license for an Altera IP core you can request a license file from the Altera Licensing page of the Altera website and install the license on your computer When you request a license file Altera emails a license dat file to you If you do not have internet access contact your local Altera representative T For additional information about installation and licensing refer to Altera Software Installation and Licensing July 2010 Altera Corporation Video and Image Processing Suite User Guide 2 2 Chapter 2 Getting Started with Altera IP Cores Ev
269. s In din port Avalon ST endofpacket signal This signal marks the end of an Avalon ST packet din port Avalon ST reaay signal This signal indicates when the MegaCore din ready function is ready to receive data din port Avalon ST startofpacket signal This signal marks the start of an din startofpacket In Avalon ST packet din valid lf din port Avalon ST valid signal This signal identifies the cycles when the port should input data dout port Avalon ST data bus Pixel data is transferred out of the MegaCore ee Out function over this bus dout port Avalon ST endofpacket signal This signal marks the end of an dout endofpacket Out Avalon ST packet dout port Avalon ST ready signal This signal is asserted by the downstream dout ready device when it is able to receive data Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 6 Signals Alpha Blending Mixer Table 6 5 2D Median Filter Signals Part 2 of 2 6 5 Signal Direction Description dout port Avalon ST startofpacket signal This signal marks the start of an dout startofpacket Out Avalon ST packet Out dout port Avalon ST valid signal This signal is asserted when the MegaCore function outputs data Alpha Blending Mixer Table 6 6 shows the input and output signals for the Alpha Blending Mixer MegaCore function Table 6 6 Alpha Blending Mixer Signals Part 1 of 2
270. s 7 TEN Out control slave port Avalon MM read data bus These output lines are used for read CR i transfers 1 it if control slave port Avalon MM write signal When this signal is asserted the D control port accepts new data from the write data bus 7 TS In control slave port Avalon MM write data bus These input lines are used for write e S transfers 1 In Clock signal for Avalon ST ports dout and control The MegaCore function CEPS operates on the rising edge of the is cix signal TEN Out dout port Avalon ST data bus Pixel data is transferred out of the MegaCore function over this bus Out dout port Avalon ST endofpacket signal This signal is asserted when the RESUME MegaCore function is ending a frame d In dout port Avalon ST ready signal This signal is asserted by the downstream device when it is able to receive data Out dout port Avalon ST startofpacket signal This signal is asserted when the ics MegaCore function is starting a new frame ete Out dout port Avalon ST valid signal This signal is asserted when the MegaCore function outputs data July 2010 Altera Corporation Video and Image Processing Suite User Guide 6 16 Chapter 6 Signals Clocked Video Input Table 6 13 Clocked Video Input Signals Part 2 of 2 Signal overflow Direction Out Description Clocked video overflow signal A signal corresponding to the overflow sticky bit of the Status register synchroniz
271. s 2 7 store the constant coefficients Summands On or Off Turn on to set the fixed point type used to store the constant Signed 2 summands as having a sign bit 0 22 Default 8 Specifies the number of integer bits for the fixed point type used to bits 2 7 store the constant summands Coefficient and summand 0 34 Default 8 Specifies the number of fraction bits for the fixed point type used to fraction 7 store the coefficients and summands bits 2 Notes to Table 3 2 1 Editing the coefficient values automatically changes the Color model conversion value to Custom 2 Editing these values change the actual coefficients and summands and the results values on the General page Signed coefficients allow negative values increasing the integer bits increases the magnitude range and increasing the fraction bits increases the precision July 2010 Altera Corporation Video and Image Processing Suite User Guide 3 4 Chroma Resampler Table 3 3 shows the Chroma Resampler MegaCore function parameters Chapter 3 Parameter Settings Chroma Resampler Table 3 3 Chroma Resampler Parameter Settings Parameter Maximum width Value 32 2600 Default 256 Description Choose the maximum image width in pixels Maximum height 32 2600 Default 256 Choose the maximum image height in pixels Bits per pixel per 4 20 Default 8 Choose the number of bits per pixel per color plane
272. s Larger sizes have a stronger effect removing more noise but also potentially removing more detail Allinput data samples must be in unsigned format If the number of bits per pixel per color plane is N this means that each sample consists of N bits of data which are interpreted as an unsigned binary number in the range 0 2 1 All output data samples produced by the 2D Median Filter MegaCore function are also in the same unsigned format The 2D Median Filter MegaCore function can process streams of pixel data of the types shown in Table 5 5 Table 5 5 2D Median Filter Avalon ST Video Protocol Parameters Parameter Frame Width Value As selected in the MegaWizard interface Frame Height As selected in the MegaWizard interface Interlaced Progressive Progressive Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface Color Pattern One two or three channels in sequence For example if three channels in BH sequence is selected where and can be any color plane Alpha Blending Mixer The Alpha Blending Mixer MegaCore function provides an efficient means to mix together up to 12 image layers The Alpha Blending Mixer provides support for both picture in picture mixing and image blending with per pixel alpha support The location and size of each layer can be changed dynamically while the MegaCore function is running and individual la
273. s P and are the user defined number of vertical and horizontal phases for each coefficient set C is the number of vertical coefficient banks and the number of horizontal coefficient banks The total number of multipliers is N N per channel in parallel The width of each vertical multiplier is max Bgqig By The width of each horizontal multiplier is the maximum of the horizontal coefficient width B and the bit width of the horizontal kernel The bit width of the horizontal kernel determines the precision of the results of vertical filtering and is user configurable Refer to the Number of bits to preserve between vertical and horizontal filtering parameter in Table 3 9 on page 3 8 The memory requirement is N line buffers plus vertical and horizontal coefficient banks As in the nearest neighbor and bilinear methods each line buffer is the same size as one line from the clipped input image The vertical coefficient banks are stored in memory that is B bits wide and P xN xC words deep The horizontal coefficient banks are stored in memory that is BjxN bits wide and words deep For each coefficient type the Quartus II software maps these appropriately to physical on chip RAM or logic elements as constrained by the width and depth requirements s If the horizontal and vertical coefficients are identical they are stored in the horizontal memory as defined above If you turn on Share horizontal vertical
274. s are truncated or padded Otherwise the full bit width is transferred July 2010 Altera Corporation Video and Image Processing Suite User Guide 4 12 Chapter 4 Interfaces Avalon ST Video Protocol m When the color pattern changes from the input to the output side of a block in a way that changes the number of color planes sent in parallel then the end of non video data packets can be padded with extra data When defining a packet type where the length is variable and meaningful it is recommended to send the length at the start of the packet Transmission of Avalon ST Video Over Avalon ST Interfaces Avalon ST Video is a protocol transmitted over Avalon ST interfaces The Avalon Interface Specifications define parameters that you can use to specify the types of Avalon ST interface Table 4 6 on page 4 12 lists the values of these parameters that are defined for transmission of the Avalon ST Video protocol All parameters not explicitly listed in the table have undefined values Table 4 6 Avalon ST Interface Parameters Parameter Name Value Variable Always equal to the Bits per Color Sample parameter value of the stream of pixel data being transferred Variable Always equal to the number of color samples being transferred in SYMBOLS PER BEAT parallel This is equivalent to the number of rows in the color pattern parameter value of the stream of pixel data being transferred READY LATENCY 1 BITS PER SYMBOL
275. s locked by the reader component that reads the output pixels from the memory When both the writer and the reader components have finished processing a frame the buffers are exchanged The frame that has just been input can then be read back from the memory and sent to the output while the buffer that has just been used to create the output can be overwritten with fresh input A double buffer is typically used when the frame rate is the same both at the input and at the output sides but the pixel rate is highly irregular at one or both sides Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 33 Frame Buffer A double buffer is often used when a frame has to be received or sent in a short period of time compared with the overall frame rate For example after the Clipper MegaCore function or before one of the foreground layers of the Alpha Blending Mixer MegaCore function When triple buffering is in use three frame buffers are used in external RAM As was the case in double buffering the reader and the writer components are always locking one buffer to respectively store input pixels to memory and read output pixels from memory The third frame buffer is a spare buffer that allows the input and the output sides to swap buffers asynchronously The spare buffer is considered clean if it contains a fresh frame that has not been output or dirty if it contains an old frame that has al
276. s per pixel per color plane Number of color Choose the number of color planes that are sent in sequence over one planes in sequence 3 data connection For example a value of 3 for R G B R G B R G B Number of color planes in parallel 1 3 Choose the number of color planes in parallel Choose the number of image layers to overlay Higher number layers are Number of layers 2 12 mixed on top of lower layer numbers The background layer is always being mixed layer 0 When on alpha data sink ports are generated for each layer including an unused port 1 _1 _0 for the background layer This requires stream of alpha values value for each pixel When off alpha data sink ports are generated and the image layers are fully opaque Alpha bits per pixel 2 4 8 Choose the number of bits used to represent the alpha coefficient July 2010 Altera Corporation Video and Image Processing Suite User Guide 3 8 Scaler Chapter 3 Parameter Settings Scaler Table 3 9 Table 3 10 and Table 3 11 on page 3 9 show the Scaler MegaCore function parameters Table 3 9 Scaler Parameter Settings Tab Resolution Page Parameter Run time control of image size Value On or Off Description Turn on to enable run time control of the image size When on the input and output size parameters control the maximum values When off the Scaler does not resp
277. s signal marks the end of an dout endofpacket Out Avalon ST packet d F In dout port Avalon ST ready signal This signal is asserted by the downstream Miis dod device when it is able to receive data _ dout port Avalon ST startofpacket signal This signal marks the start of an dout startofpacket Out Avalon ST packet dout valid Out dout port Avalon ST valia signal This signal is asserted when the MegaCore function outputs data July 2010 Altera Corporation Video and Image Processing Suite User Guide 6 2 Chapter 6 Signals Chroma Resampler Chroma Resampler Table 6 2 shows the input and output signals for the Chroma Resampler MegaCore function Table 6 2 Chroma Resampler Signals Signal Direction Description The main system clock The MegaCore function operates on the rising edge of the clock In clock signal The MegaCore function is asynchronously reset when reset is asserted high reset In The reset must be de asserted synchronously with respect to the rising edge of the clock signal dina if din port Avalon ST data bus Pixel data is transferred into the MegaCore eee function over this bus din port Avalon ST endofpacket signal This signal marks the end of an Avalon din_endofpacket In ST packet di 5 Out din port Avalon ST reaay signal This signal indicates when the MegaCore function is ready to receive data in i LORI din port Avalon ST startofpacket signal Th
278. s signal marks the start of dout startofpacket Out an Avalon ST packet dout valid Out dout port Avalon ST valid signal This signal is asserted when the MegaCore function outputs data Note to Table 6 7 1 These ports are present only if Run time control of image size is on in the MegaWizard interface Clipper Table 6 8 shows the input and output signals for the Clipper MegaCore function Table 6 8 Clipper Signals Part 1 of 2 Signal Direction Description sd in The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is asserted reset In high The reset must be de asserted synchronously with respect to the rising edge of the clock signal m i control slave port Avalon MM address bus Specifies a word offset into the slave address space 7 in control Slave port Avalon MM chipselect signal The control port mese ignores all other signals unless this signal is asserted 1 id de Out control Slave port Avalon MM readdata bus These output lines are used CEDE for read transfers 1 control av waitrequest Out control Slave port Avalon MM waitrequest signal 1 RERUM In control slave port Avalon MM write signal When this signal is asserted Oe the control port accepts new data from the writedata bus 7 nae In control slave port Avalo
279. s with EDA Tools in volume 3 of the Quartus II Handbook July 2010 Altera Corporation Video and Image Processing Suite User Guide 2 8 Chapter 2 Getting Started with Altera IP Cores Generated Files Compile and Program After using SOPC Builder or the MegaWizard Plug In Manager to define and instantiate your IP core you must compile your design to create programming files to configure the FPGA Some Altera IP cores require that you apply constraints before compilation These constraint files make pin assignments and ensure that your IP core instance meets design timing requirements After applying constraint files if appropriate for your IP core you can use the Start Compilation command on the Processing menu in the Quartus II software to compile your design After successfully compiling your design program the targeted Altera device with the Programmer and verify the design in hardware Generated Files Table 2 2 describes the generated files and other files that may be in your project directory The names and types of files vary depending on the variation name and HDL type you specify during parameterization For example a different set of files are created based on whether you create your design in Verilog HDL or VHDL For a description of the signals that the MegaCore function variation supports refer to Chapter 6 Signals Table 2 2 Generated Files Note 1 File Name variation name hsf Description Quar
280. sable the interlacer at run time to propagate progressive frames unchanged Frame Reader The Frame Reader MegaCore function reads video frames stored in external memory and outputs them as a video stream You can configure the MegaCore function to read multiple video frames using an Avalon MM slave interface Frame Buffer The Frame Buffer MegaCore function buffers video frames into external RAM The Frame Buffer supports double or triple buffering with a range of options for frame dropping and repeating Clocked Video Input The Clocked Video Input MegaCore function converts clocked video formats such as BT656 BT1120 and DVI to Avalon ST Video You can configure the Clocked Video Input at run time using an Avalon MM slave interface July 2010 Altera Corporation Video and Image Processing Suite User Guide Chapter 1 About This MegaCore Function Suite MegaCore Verification Clocked Video Output The Clocked Video Output MegaCore function converts Avalon ST Video to clocked video formats such as BT656 BT1120 and DVI You can configure the Clocked Video Output at run time using an Avalon MM slave interface Color Plane Sequencer The Color Plane Sequencer MegaCore function changes how color plane samples are transmitted across the Avalon ST interface You can configure the channel order in sequence or in parallel In addition to reordering color plane samples the Color Plane Sequencer splits and joins video streams giving c
281. scriptions 5 67 Stall Behavior and Error Recovery Because this is a rate changing function the quantities of data input and output are not equal The Chroma Resampler MegaCore function always outputs the same number of lines that it inputs However the number of samples in each line varies according to the subsampling pattern used When not stalled the Chroma Resampler always processes one sample from the more fully sampled side on each clock cycle For example the subsampled side pauses for one third of the clock cycles in the 4 2 2 case or half of the clock cycles in the 4 2 0 case Error Recovery On receiving an early endofpacket signal the Chroma Resampler stalls its input but continues writing data until it has sent an entire frame If it does not receive an endofpacket signal at the end of a frame the Chroma Resampler discards data until the end of packet is found Gamma Corrector In all parameterizations the Gamma Corrector stalls only between frames and not between rows It has no internal buffering aside from the registers of its processing pipeline so there are only a few clock cycles of latency Error Recovery The Gamma Corrector MegaCore function processes video packets until an endofpacket signal is received Non image packets are propagated but the content of control packets is ignored For this MegaCore function there is no such condition as an early or late endofpacket Any mismatch of the endofpacket signal and the
282. sed for write transfers 6 ma control av address ma control Slave port Avalon MM address bus Specifies a word offset into the slave address space 5 ma control av chipselect ma control slave port Avalon MM chipselect signal The ma control port ignores all other signals unless this signal is asserted 5 ma control av readdata Out ma control slave port Avalon MM readdata bus These output lines are used for read transfers 5 ma control av waitrequest Out ma control slave port Avalon MM waitrequest signal 5 ma_control_av_write ma_control slave port Avalon MM write signal When asserted the ma_control port accepts new data from the writedata bus 5 ma_control_av_writedata ma control slave port Avalon MM writedata bus These input lines are used for write transfers 5 read master N av address Out read master N port Avalon MM address bus Specifies a byte address in the Avalon MM address space 1 2 3 read master av burstcount Out read master N port Avalon MM burstcount signal Specifies the number of transfers in each burst 1 2 3 read_master_N_av_clock read_master_N port clock signal The interface operates on the rising edge of the clock signal 7 2 3 4 read_master_N_av_read read_master_N port Avalon MM read signal Asserted to indicate read requests from the master to the system interconnect fabric
283. shows a block diagram of an example SOPC Builder system Figure 2 3 SOPC Builder System Altera IP Core Simulation Testbench Module y SOPC Builder System Altera IP Core Instance A Ni System Interconnect Fabric Peripheral 1 Peripheral 2 Peripheral 3 St For more information about system interconnect fabric refer to System Interconnect Fabric for Memory Mapped Interfaces and System Interconnect Fabric for Streaming Interfaces chapters in volume 4 of the Quartus II Handbook and Avalon Interface Specifications For more information about SOPC Builder and the Quartus II software refer to SOPC Builder Features and Building Systems with SOPC Builder sections in volume 4 of the Quartus II Handbook and Quartus II Help Specify Parameters To specify IP core parameters with the SOPC Builder flow follow these steps 1 Create a new Quartus II project using the New Project Wizard available from the File menu Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 2 Getting Started with Altera IP Cores 2 5 SOPC Builder Design Flow On the Tools menu click SOPC Builder For a new system specify the system name and language On the System Contents tab double click the name of your IP core to add it to your system The relevant MegaWizard interface appears La The System Contents tab lists Altera IP cores by category For example
284. sign stops working after the hardware evaluation time expires The Quartus II software uses OpenCore Plus Files ocp in your project directory to identify your use of the OpenCore Plus evaluation program After you activate the feature do not delete these files For information about the OpenCore Plus evaluation program refer to AN320 OpenCore Plus Evaluation of Megafunctions You can use either one of the following flows to parameterize Altera IP cores m SOPC Builder flow m MegaWizard Plug in Manager flow Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 2 Getting Started with Altera IP Cores Design Flows 2 3 Table 2 1 summarizes the advantages offered by the different parameterization flows Table 2 1 Select Design Flow SOPC Builder Flow m You want to use SOPC Builder to create complete system that includes an Altera core with other components available in External Memory Controllers DMA other IP cores m You want SOPC Builder to automatically and connect low level interfaces a IP SOPC Builder such as the Nios II processor controllers on chip memories FIFOs or implement standard interface connections between the various components in your design eliminating the requirement to design m You want to parameterize the IP core variant m You want to integrate an IP core variant that MegaWizard Plug in Manager Flow that you can instantiate manually in
285. signal 1 P in control Slave port Avalon MM write signal When this signal is asserted 6 the control port accepts new data from the writedata bus 7 if control slave port Avalon MM writedata bus These input lines are used pong for write transfers 1 m n din port Avalon ST data bus Pixel data is transferred into the MegaCore function over this bus din port Avalon ST endofpacket signal This signal marks the end of an din endofpacket In Avalon ST packet RT Out din port Avalon ST ready signal This signal indicates when the MegaCore function is ready to receive data Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 6 Signals Clipper Table 6 7 Scaler Signals Part 2 of 2 6 7 Signal Direction Description din port Avalon ST startofpacket signal This signal marks the start of din startofpacket In an Avalon ST packet din valid in din port Avalon ST valid Signal This signal identifies the cycles when the port should input data ee Out dout port Avalon ST data bus Pixel data is transferred out of the MegaCore function over this bus _ dout port Avalon ST endofpacket signal This signal marks the end of an dout endofpacket Out Avalon ST packet _ dout port Avalon ST ready signal This signal is asserted by the dout ready In ie downstream device when it is able to receive data _ dout port Avalon ST startofpacket signal Thi
286. signals these properties fully define an interface type The external memory access interfaces of the Video and Image Processing Suite MegaCore functions exhibit the following transfer property m Pipeline with variable latency Buffering of Non Image Data Packets in Memory The Frame Buffer and the Deinterlacer when buffering is enabled route the video stream through an external memory Non image data packets must be buffered and delayed along with the frame or field they relate to and extra memory space has to be allocated You must specify the maximum number of packets per field and the maximum size of each packet to cover this requirement The maximum size of a packet is given as a number of symbols header included For instance the size of an Avalon ST Video control packet is 10 This size does not depend on the number of channels transmitted in parallel Packets larger than this maximum limit may be truncated as extra data is discarded The maximum number of packets is the number of packets that can be stored with each field or frame Older packets are discarded first in case of overflow When frame dropping is enabled the packets associated with a field that has been dropped are automatically transferred to the next field and count towards this limit The Frame Buffer and the Deinterlacer handle Avalon ST Video control packets differently The Frame Buffer processes and discards incoming control packets whereas the Deinterlacer pro
287. ssociated with the frame 17 Frame 1 The interlace nibble to be used for the control packet associated with the frame Interlaced Frame Buffer Video and Image Processing Suite User Guide A run time control can be attached either to the writer component or to the reader component of the Frame Buffer MegaCore function but not to both The width of each register is 16 bits July 2010 Altera Corporation Chapter 7 Control Register Maps Frame Buffer Table 7 14 describes the Frame Buffer MegaCore function control register map for the writer component Table 7 14 Frame Buffer Control Register Map for the Writer Component Address Register s Description Bit 0 of this register is the Go bit Setting this bitto 1 causes the Frame Buffer MegaCore 0 Control function to stop the next time control information is read to start outputting data Refer to Avalon MM Slave Interfaces on page 4 17 for full details 1 T Bit 0 of this register is the Status bit all other bits are unused Refer to Avalon MM ra Slave Interfaces on page 4 17 for full details 2 Sount Read only register updated at the end of each frame processed by the writer The TOMS MSIE counter is incremented if the frame is not dropped and passed to the reader component 3 Cone Read only register updated at the end of each frame processed by the writer The ic ee counter is incremented if the frame is dropped Bit 0 of this registe
288. standard bus Can be connected to the tx sca signal of the SDI MegaCore function or any other interface to set the Standard register TA Out Embedded Synchronization Mode Only Clocked video time reference signal TRS ax signal Used with the SDI MegaCore function to indicate a TRS when asserted ee Out Separate Synchronization Mode Only Clocked video vertical blanking signal This m signal is asserted during the vertical blanking period of the video stream Separate Synchronization Mode Only Clocked video vertical synchronization vid v sync Out signal This signal is asserted during the vertical synchronization period of the video stream Note to Table 6 14 1 These ports are present only if Use control port is on in the MegaWizard interface Color Plane Sequencer Table 6 15 shows the input and output signals for the Color Plane Sequencer MegaCore function Table 6 15 Color Plane Sequencer Signals Part 1 of 2 Signal Direction Description The main system clock The MegaCore function operates on the rising edge of cus the clock signal The MegaCore function is asynchronously reset when reset is asserted high reset In The reset must be de asserted synchronously with respect to the rising edge of the clock signal Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 6 Signals 6 19 Test Pattern Generator Table 6 15 Color Plane Sequencer Sig
289. t 2 524 857 A Clocked Video Output MegaCore function can take in the locked PLL clock and the SOF signal and align the output video to these signals This produces an output video frame that is synchronized to the incoming video frame For more information refer to the description of the Clocked Video Output MegaCore function Overflow Moving between the domain of clocked video and the flow controlled world of Avalon ST Video can cause problems if the flow controlled world does not accept data at a rate fast enough to satisfy the demands of the incoming clocked video The Clocked Video Input MegaCore function contains a FIFO that when set to a large enough value can accommodate any bursts in the flow data as long as the input rate of the upstream Avalon ST Video components is equal to or higher than that of the incoming clocked video If this is not the case the FIFO overflows If overflow occurs the MegaCore function outputs an early endofpacket signal to complete the current frame It then waits for the next start of frame or field before re synchronizing to the incoming clocked video and beginning to output data again The overflow is recorded in bit 9 of the Status register This bit is sticky and if an overflow occurs stays at 1 until the bit is cleared by writing a 0 to it In addition to the overflow bit the current level of the FIFO can be read from the Used Words register Timing Constraints To constrain the Clocked V
290. t does use more logic area than the nearest neighbor algorithm 4 2 2 to 4 4 4 The nearest neighbor algorithm is the simplest way to up scale the chroma channels It works by simply duplicating each incoming Cb and Cr sample to fill in the missing data This algorithm is very fast and cheap but it tends to produce sharp jagged edges in the chroma channels The filtered algorithm uses the same method as the Scaler MegaCore function would use for upscaling that is a four tap filter with Lanczos 2 coefficients Use this filter with a phase offset of 0 for the odd output columns those with existing data and an offset of one half for the even columns those without direct input data A filter with phase offset 0 has no effect so the function implements it as a pass through filter A filter with phase offset of one half interpolates the missing values and has fixed coefficients that bit shifts and additions implement This algorithm performs suitable upsampling and uses no memory or multipliers It uses more logic elements than the nearest neighbor algorithm and is not the highest quality available The best image quality for upsampling is obtained by using the filtered algorithm with luma adaptive mode enabled This mode looks at the luma channel during interpolation and uses this to detect edges Edges in the luma channel make appropriate phase shifts in the interpolation coefficients for the chroma channels Figure 5 2 on page 5 6 shows 4 2 2
291. t is set to 1 while the MegaCore function ApS is processing data and cannot be stopped Refer to Avalon MM Slave Interfaces on page 4 17 for full details 2 Left Offset The left offset in pixels of the clipping window rectangle 1 3 Right Offset or clipping window mode the right offset of the window In clipping rectangle mode the Width width of the rectangle 1 4 Top Offset The top offset in pixels of the clipping window rectangle 2 5 Bottom Offset In clipping window mode the bottom offset of the window In clipping rectangle mode or Height the height of the rectangle 2 Notes to Table 7 9 1 The left and right offset values must be less than or equal to the input image width 2 The top and bottom offset values must be less than or equal to the input image height Deinterlacer An run time control interface can be attached to the Deinterlacer that you can use to override the default behavior of the motion adaptive algorithm or to synchronize the input and output frame rates However it is not possible to enable both interfaces simultaneously Table 7 10 describes the control register map that controls the motion adaptive algorithm at run time The control data is read once and registered before outputting a frame It can be safely updated during the processing of a frame Table 7 10 Deinterlacer Control Register Map for Run Time Control of the Motion Adaptive Algorithm Part 1 of 2 A
292. taneously with the run time override of the motion adaptive algorithm Behavior When Unexpected Fields are Received So far the behavior of the Deinterlacer has been described assuming an uninterrupted sequence of pairs of interlaced fields FO F1 FO each having the same height Some video streams might not follow this rule and the Deinterlacer adapts its behavior in such cases The dimensions and type of a field progressive interlaced FO or interlaced F1 are identified using information contained in Avalon ST Video control packets When a field is received without control packets its type is defined by the type of the previous field A field following a progressive field is assumed to be a progressive field and a field following an interlaced FO or F1 field is respectively assumed to be an interlaced F1 or FO field If the first field received after reset is not preceded by a control packet it is assumed to be an interlaced field and the default initial field FO or F1 specified in the MegaWizard interface is used When the weave or the motion adaptive algorithms are used a regular sequence of pairs of fields is expected Subsequent FO fields received after an initial FO field or subsequent F1 fields received after an initial F1 field are immediately discarded When the bob algorithm is used and synchronization is done on a specific field input frame rate output frame rate the field that is constantly unused is always discard
293. tatus bit All other bits are unused Refer to Avalon MM uds Slave Interfaces on page 4 17 for full details 9 in Bit 1 of this register is the end of frame interrupt bit All other bits are unused Writing a 1 ean to bit 1 resets the end of frame interrupt 3 This register selects between frame 0 and frame 1 for next output Frame 0 is selected by SEDE writing a 0 here frame is selected by writing a 1 here 4 erame 9 Base The 32 bit base address of the frame Address 5 Frame 0 Words The number of words reads from the master port to read from memory for the frame Frame 0 Single 6 Cycle Color The number of single cycle color patterns to read for the frame Patterns 7 erame 0 Reserved for future use Reserved 8 Frame 0 Width The Width to be used for the control packet associated with frame 0 9 Frame 0 Height The Height to be used for the control packet associated with frame 0 10 Frame The interlace nibble to be used for the control packet associated with frame 0 Interlaced 11 rame d BASE The 32 bit base address of the frame Address 12 Frame 1 Words The number of words reads from the master port to read from memory for the frame Frame 1 Single 13 Cycle Color The number of single cycle color patterns to read for the frame Patterns 14 pramet Reserved for future use Reserved 15 Frame 1 Width The Width to be used for the control packet associated with the frame 16 Frame 1 Height The Height to be used for the control packet a
294. ter MegaCore function parameters Chapter 3 Parameter Settings Color Space Converter CSC Table 3 1 Color Space Converter Parameter Settings Tab General Page Bits per pixel per color plane 2 Parameter Value Description Color Plane Three color planes in sequence or Specifies whether the three color planes are transmitted Configuration Three color planes in parallel in sequence or in parallel Input Data Type Bits per pixel per 4 20 Default 8 o the number of input bits per pixel per color color plane p Input Data Type Specifies whether the input is unsigned or signed 2 s Data type 2 Unsigned complement Input Data Type Guard bands 1 On or Off Enables using a defined input range M Type 524288 1048575 Default 255 Specifies the input range maximum value hey yee 524288 1048575 Default 0 Specifies the input range minimum value Output Data Type 4 20 Default 8 Choose the number of output bits per pixel per color plane Output Data Type Specify whether the output is unsigned or signed 2 Data type Unsigned Signed complement Output Data Type Guard bands 1 On or Off Turn on to enable a defined output range Output Data 5942881048575 Default 2 Specify th i l Max 1 5 575 Default 255 pecify the output range maximum value Y Type 524288 1048575 Default 0 Specify the output range minimum value
295. text RTL model is generated and you can simulate that model Te For more information about functional simulation models for Altera IP cores refer to Simulating Altera IP in Third Party Simulation Tools in volume 3 of the Quartus II Handbook Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 2 Getting Started with Altera IP Cores 2 1 MegaWizard Plug In Manager Design Flow A Use the simulation models only for simulation and not for synthesis or any other purposes Using these models for synthesis creates a nonfunctional design 6 Some third party synthesis tools can use a netlist that contains the structure of an IP core but no detailed logic to optimize timing and performance of the design containing it Many Altera IP cores support this feature To use this feature if your synthesis tool and IP core support it turn on Generate netlist 7 Onthe Summary tab if available select the files you want to generate A gray checkmark indicates a file that is automatically generated All other files are optional If file selection is supported for your IP core after you generate the core a generation report variation name gt html appears in your project directory This file contains information about the generated files 8 Click the Finish button the MegaWizard interface generates the top level HDL code for your IP core a qip file containing all of the necessary assignments and information require
296. the results are beyond the range specified by the output data type output guard bands or if unspecified the minimum and maximum values allowed by the output bits per pixel logic that saturates the results to the minimum and maximum output values is automatically added The Color Space Converter MegaCore function can process streams of pixel data of the types shown inTable 5 1 Table 5 1 Color Space Converter Avalon ST Video Protocol Parameters Parameter Value Frame Width Read from control packets at run time Frame Height Read from control packets at run time Interlaced Progressive Either Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface Color Pattern 1 For color planes in parallel For color planes in sequence 2 July 2010 Altera Corporation Notes to Table 5 1 For channels in parallel the top of the color pattern matrix represents the MSB of data and the bottom represents the LSB For details refer to Avalon ST Video Protocol on page 4 2 Video and Image Processing Suite User Guide 9 4 Chapter 5 Functional Descriptions Chroma Resampler Chroma Resampler The Chroma Resampler MegaCore function allows you to change between 4 4 4 4 2 2 and 4 2 0 sampling rates where 4 44 specifies full resolution in planes 1 2 and 3 m 4 22 specifies full resolution in plane 1 half width resolution in planes 2 and
297. till parts of an image but unpleasant artefacts in moving parts The weave algorithm requires external memory so either double or triple buffering must be selected This makes it significantly more expensive in logic elements and external RAM bandwidth than either of the bob algorithms if external buffering is not otherwise required The results of the weave algorithm can sometimes be perfect in the instance where pairs of interlaced fields have been created from original progressive frames Weave simply stitches the frames back together and the results are the same as the original as long as output frame rate equal to input frame rate is selected and the correct pairs of fields are put together Usually progressive sources split each frame into a pair consisting of an FO field followed by an F1 field so selecting F1 to be the current field often yields the best results Motion Adaptive The Deinterlacer MegaCore function provides a simple motion adaptive algorithm This is the most sophisticated of the algorithms provided but also the most expensive both in terms of logic area and external memory bandwidth requirement This algorithm avoids the weaknesses of bob and weave algorithms by using a form of bob deinterlacing for moving areas of the image and weave style deinterlacing for still areas 57 If the input is 42 2 Y CbCr subsampled data the compatibility mode for 4 2 2 data should be enabled to prevent the motion adaptive algorithm
298. time control 3 Vertical subsampling and interlacing are incompatible with each other and cannot be selected simultaneously in the GUI Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 61 Control Synchronizer Control Synchronizer You can use the Control Synchronizer MegaCore function to synchronize the configuration of other MegaCore functions with an event in the video stream The control synchronizer has an Avalon Video Streaming Input and Output port which passes through Avalon ST Video data and monitors the data for trigger events The events that can trigger the control synchronizer are the start of a video data packet or a change in the width or height field of a control data packet that describes the next video data packet The Control Synchronizer MegaCore function also has an Avalon Master port When the Control Synchronizer MegaCore function detects a trigger event the MegaCore writes data to the Avalon Slave control ports of other MegaCores The Control Synchronizer MegaCore function also has an Avalon Slave port that sets the data to be written and the addresses that the data should be written to when the MegaCore function detects a trigger event When the Control Synchronizer MegaCore function detects a trigger event it immediately stalls the Avalon ST video data flowing through the MegaCore which freezes the state of other MegaCore functions on the same video
299. tion outputs data Note to Table 6 8 1 These ports are present only if Include Avalon MM interface is on in the MegaWizard interface Deinterlacer Table 6 9 shows the input and output signals for the Deinterlacer MegaCore function Table 6 9 Deinterlacer Signals Part 1 of 3 Signal Direction Description e The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when senit In reset is asserted high The reset must be de asserted synchronously with respect to the rising edge of the clock signal In din port Avalon ST data bus Pixel data is transferred into the MegaCore function over this bus din port Avalon ST endofpacket signal This signal eae marks the end of an Avalon ST packet din port Avalon ST ready signal This signal indicates din ready Out when the MegaCore function is ready to receive data rmm in din port Avalon ST startofpacket signal This signal DE d marks the start of an Avalon ST packet Sieve adda In din port Avalon ST valid signal This signal identifies the E cycles when the port should input data m Out dout port Avalon ST data bus Pixel data is transferred cau de out of the MegaCore function over this bus dout port Avalon ST endofpacket signal This signal endo aes marks the end of an Avalon ST packet m A in dout port Avalon ST ready signal This sign
300. treated differently depending on their type Control packets of type 15 are processed by the core to extract the width and height of each layer and are discarded on the fly Other packets of type 1 to type 14 are propagated unchanged The second step corresponds to the usual behavior of other Video and Image Processing MegaCore functions that have an Avalon MM slave interface After the non image data packets from the background layer and the foreground layers have been processed and or propagated the MegaCore function waits for the Go bit to be set to 1 before reading the top left position of each layer Consequently the behavior of the Alpha Blending Mixer differs slightly from the other Video and Image Processing MegaCore functions This behavior is illustrated by the following pseudo code go 0 while true status 0 read non image data packet from background layer read control first pass Check layer status disable displayed consumed for each layer layer id process non image data packets for displayed or consumed layers if layer_id is not disabled handle non image packet from foreground layer layer while go 1 wait status 1 read_control_second_pass Copies top left coordinates to internal registers send image data header process frame For information about using Avalon MM Slave interfaces for run time control refer to Avalon MM Slave Int
301. ts other than video data packets are duplicated to both outputs Figure 5 23 shows an example of partially splitting and duplicating an input color pattern Figure 5 23 Example of Splitting and Duplicating Color Patterns R G Color pattern of a video data packet on output stream 0 R 2 color plane samples in parallel Color pattern of a video data packet on the input stream 3 color plane samples in sequence Color pattern of a video data packet on output stream 1 2 color plane samples in sequence Subsampled Data In addition to fully sampled color patterns the Color Plane Sequencer supports 4 2 2 subsampled data To facilitate this support you can configure the Color Plane Sequencer with two color patterns in sequence so that subsampled planes can be specified individually When splitting subsampled planes from fully sampled planes the Avalon ST Video control packet for the subsampled video data packet can have its width value halved so that the subsampled planes can be processed by other MegaCore functions as if fully sampled This halving can be applied to control packets on port dout0 and port dout1 or control packets on port dout 0 only Avalon ST Video Stream Requirements The only stream requirement imposed is that when two streams are being combined the video data packets must contain the same total number of pixels and to make a valid image the packets must have the same dimensions The Color
302. ts the registers valid bit in the Status register and triggers the respective interrupts Table 5 17 shows the sequence for a 1080i incoming video stream Table 5 17 Resolution Detection Sequence for a 1080i Incoming Video Stream Active Md m SES Total FOTotal FiTotal Status Interrupt Sample Line Line Sample Sample Sample Description Count Count Count Count Count Count 00000000000 000 0 0 0 0 0 0 Start of incoming video 00000101000 000 1 920 0 0 2 200 0 0 End of first line of video Stable bit set and interrupt fired 00100101000 100 1 920 0 0 2 200 0 0 Two of last three lines had the same sample count 00100111000 100 1 920 540 0 2 200 563 0 End of first field of video Interlaced bit set Start of 00110111000 100 1 920 540 0 2 200 563 0 second field of video 00111111000 100 1 920 540 540 2 200 563 562 End of second field of video 10111111000 110 1920 540 540 2200 563 562 Resolution valid bit set and interrupt fired Interrupts The Clocked Video Input MegaCore function outputs a single interrupt line which is the OR of the following internal interrupts The status update interrupt Triggers when a change of resolution in the incoming video is detected July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 40 Chapter 5 Functional Descriptions Clocked Video Input m Stable video interrupt Triggers when the in
303. turned on in the MegaWizard interface Video and Image Processing Suite User Guide July 2010 Altera Corporation RA 1 Control Register Maps The Color Space Converter Gamma Corrector 2D FIR Filter Alpha Blending Mixer Scaler Clipper Deinterlacer Interlacer Frame Buffer Clocked Video Input Clocked Video Output and Test Pattern Generator MegaCore functions support run time control for some of their behavior using a common type of Avalon MM slave interface This chapter describes the control register maps which can be accessed using these interfaces For information about the Control and Status registers which are common to these interfaces refer to Avalon MM Slave Interfaces on page 4 17 Color Space Converter Table 7 1 describes the control register map for the Color Space Converter MegaCore function The width of each register in the Color Space Converter control register map is 32 bits The coefficient and summand registers use integer signed 2 s complement numbers To convert from fractional values simply move the binary point right by the number of fractional bits specified in the user interface The control data is read once at the start of each frame and is buffered inside the MegaCore function so the registers can be safely updated during the processing of a frame Table 7 1 Color Space Converter Control Register Map Address Register N
304. tus II block symbol file for the MegaCore function variation You can use this file in the Quartus 11 block diagram editor variation name cmp A VHDL component declaration file for the MegaCore function variation Add the contents of this file to any VHDL architecture that instantiates the MegaCore function variation name qip A single Quartus IP file is generated that contains all of the assignments and other information required to process your MegaCore function variation in the Quartus Il compiler In the SOPC Builder flow this file is automatically included in your project In the MegaWizard Plug In Manager flow you are prompted to add the qip file to the current Quartus Il project when you exit from the wizard In SOPC Builder a gip file is generated for each MegaCore function and SOPC Builder component Each of these gip files are referenced by the system level gip file and together include all the information required to process the system variation name vhd A VHDL or Verilog HDL file that defines the top level description of the custom MegaCore or v function variation Instantiate the entity defined by this file inside your design Include this file when compiling your design in the Quartus II software variation name gt vho or vo VHDL or Verilog HDL output files that defines an IP functional simulation model lt variation name gt _bb v A Verilog HDL black box file for the MegaCore fu
305. um values allowed by the output bits per pixel logic to saturate the results to the minimum and maximum output values is automatically added The 2D FIR Filter MegaCore function can process streams of pixel data of the types shown in Table 5 4 Table 5 4 2D FIR Filter Avalon ST Video Protocol Parameters Parameter Frame Width Value As selected in the MegaWizard interface Frame Height As selected in the MegaWizard interface Interlaced Progressive Progressive Bits per Color Sample Number of bits per color sample selected in the MegaWizard interface Color Pattern One two or three channels in sequence For example if three channels in sequence is selected where B and y can be any color plane 2D Median Filter The 2D Median Filter MegaCore function provides a means to perform 2D median filtering operations using matrices of 3x3 or 5x5 kernels Each output pixel is the median of the input pixels found in a 3x3 5x5 or 7x7 kernel centered on the corresponding input pixel Where this kernel runs over the edge of the input image zeros are filled in July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 10 Chapter 5 Functional Descriptions Alpha Blending Mixer Larger kernel sizes require many more comparisons to perform the median filtering function and therefore require correspondingly large increases in the number of logic element
306. unction so that the registers can be safely updated during the processing of a frame or pair of interlaced fields After control data has been read the Test Pattern Generator MegaCore function outputs a control packet that describes the following image data packet When the output is interlaced the control data is processed only before the first field of a frame although a control packet is sent before each field Table 7 18 describes the Test Pattern Generator MegaCore function control register map Table 7 18 Test Pattern Generator Control Register Map Part 1 of 2 Address Register s Description Bit 0 of this register is the Go bit all other bits are unused Setting this bit to 0 causes the 0 Test Pattern Generator MegaCore function to stop before control information is read HLE TN Refer to Generation of Avalon ST Video Control Packets and Run Time Control on page 5 59 for full details Bit 0 of this register is the Status bit all other bits are unused The Test Pattern Generator MegaCore function sets this address to 0 between frames It is set to 1 while 1 Status the MegaCore function is producing data and cannot be stopped Refer to Generation of Avalon ST Video Control Packets and Run Time Control on page 5 59 for full details 2 Output Width The width of the output frames or fields in pixels 1 3 Output Height The progressive height of the output frames or fields in pixels 1 July 2
307. ure the Deinterlacer to output one frame for each input field it produces 60 frames of output per second If you enable triple buffering on average the function drops one frame in six so that it produces 50 frames per second If you chose one frame output for every pair of fields input the Deinterlacer produces 30 frames per second output and triple buffering leads to the function repeating two out of every three frames on average When you select double or triple buffering the Deinterlacer has two or more Avalon MM master ports These must be connected to an external memory with enough space for all of the frame buffers required The amount of space varies depending on the type of buffering and algorithm selected An estimate of the required memory is shown in the Deinterlacer MegaWizard interface If the external memory in your system runs at a different clock rate to the Deinterlacer MegaCore function you can turn on an option to use a separate clock for the Avalon MM master interfaces and use the memory clock to drive these interfaces To prevent memory read and write bursts from being spread across two adjacent memory rows you can turn on an option to align the initial address of each read and write burst to a multiple of the burst target used for the read and write masters or the maximum of the read and write burst targets if using different values Turning on this option may have a negative impact on memory usage but increases memory e
308. ures that the video streams entering the Switch MegaCore function are all on the same frame They can then be switched on the next image end of packet without causing a deadlock situation between the Switch and Alpha Blending Mixer The following sequence shows an example for layer switching 1 Switch MegaCore function Write to the DoutN Output Control registers setting up the outputs For example a Write 1 to address 3 b Write 2 to address 4 2 Switch MegaCore function Enable the function by writing 1 to address 0 3 Switch MegaCore function Write to the DoutN Output Control registers to switch the outputs For example a Write 2 to address 3 b Write 1 to address 4 4 Control Synchronizer MegaCore function Set up the Control Synchronizer to write a 1 to the Switch MegaCore function s Output Switch register on the next start of an image packet For information about the compile time parameters for the Switch MegaCore function refer to Table 3 22 on page 3 21 For information about the run time control register map refer to Table 7 20 on page 7 15 For information about the signals refer to Table 6 18 on page 6 21 July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 66 Chapter 5 Functional Descriptions Stall Behavior and Error Recovery Stall Behavior and Error Recovery The Video and Image Processing Suite MegaCore functions do not continuously process data Instead they use flow controlled
309. use them Table 4 2 Examples of Static Avalon ST Video Data Packet Parameters Parameters s Description Bits per Color Sample Color Pattern Three color planes B G and R are transmitted in alternating sequence and each 8 B G R H H H B G or R sample is represented using 8 bits of data R Three color planes are transmitted in parallel leading to higher throughput than 10 when transmitted in sequence usually at higher cost Each R G or B sample is represented using 10 bits of data so that in total 30 bits of data are transmitted B in parallel 4 2 2 video in the Y CbCr color space where there are twice as many Y samples 10 E as Cb or Cr samples One Y sample and one of either a Cb or a Cr sample is transmitted in parallel Each sample is represented using 10 bits of data The Avalon ST Video protocol does not force the use of specific color patterns however a few MegaCore functions of the Video and Image Processing Suite only process video data packets correctly if they use a certain set of color patterns Chapter 5 Functional Descriptions describes the set of color patterns that the MegaCore functions use July 2010 Altera Corporation Video and Image Processing Suite User Guide 4 6 Chapter 4 Interfaces Avalon ST Video Protocol Table 4 3 shows the recommended color patterns for common combinations of color spaces and color planes in parallel and sequence Table
310. ut data diti E Out dout port Avalon ST data bus Pixel data is transferred out of the MegaCore function over this bus dout port Avalon ST endofpacket signal This signal marks the Out end of an Avalon ST packet ANLE dout port Avalon ST ready signal This signal is asserted by the m Y downstream device when it is able to receive data _ dout port Avalon ST startofpacket signal This signal marks out the start of an Avalon ST packet _ dout port Avalon ST valid signal This signal is asserted when the MegaCore function is outputs data read master port Avalon MM address bus Specifies a byte read magter av address Out address in the Avalon MM address space m Out read master port Avalon MM burstcount signal Specifies the number of transfers in each burst July 2010 Altera Corporation Video and Image Processing Suite User Guide 6 14 Table 6 12 Frame Buffer Signals Part 2 of 3 Chapter 6 Signals Frame Buffer Signal read master av clock Direction In Description read master port The clock signal The interface operates on the rising edge of the clock signal 1 read master av read read master port Avalon MM read signal Asserted to indicate read requests from the master to the system interconnect fabric read master av readdata read master port Avalon MM readdata bus These input lines carry data for read transfers read master av re
311. utput signals for the Frame Reader MegaCore function Table 6 11 Frame Reader Signals Part 1 of 2 Chapter 6 Signals Frame Reader Signal Direction Description eS lh The main system clock The MegaCore function operates on the rising edge of the clock signal The MegaCore function is asynchronously reset when reset is reset In asserted high The reset must be de asserted synchronously with respect to the rising edge of the clock signal nm Out dout port Avalon ST data bus Pixel data is transferred out of the MegaCore function over this bus dout port Avalon ST endofpacket signal This signal dout_endofpack t Ou marks the end of an Avalon ST packet dout dezd In dout port Avalon ST ready signal This signal is AES Y asserted by the downstream device when it is able to receive data dout port Avalon ST startofpacket signal This dout_startofpacket t A ETES Ou signal marks the start of an Avalon ST packet dout port Avalon ST valid signal This signal is dout valid Out C asserted when the MegaCore function outputs data slave port Avalon MM address Specifies a word offset Slave av address In into the slave address space Morte ead slave port Avalon MM read signal When this signal is asserted the slave port drives new data onto the read data bus 1 t Avalon MM Th Syeda Out slave por valon readdata bus These output l
312. vertical filtering are then found by taking the set of coefficients from phase and applying them to each column in the square filter Each of these N results is then divided down to fit in the number of bits chosen for the horizontal kernel The horizontal kernel is applied to the coefficients from phase to produce a single value This value is then divided down to the output bit width before being written out as a result Choosing and Loading Coefficients The filter coefficients which the polyphase mode of the scaler uses may be specified at compile time or at run time At compile time the coefficients can be either selected from a set of Lanczos windowed sinc functions or loaded from a comma separated variable CSV file At run time they are specified by writing to the Avalon MM slave control port Table 7 7 on page 7 4 July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 18 Chapter 5 Functional Descriptions Scaler When the coefficients are read at run time they are checked once per frame and double buffered so that they can be updated as the MegaCore function processes active data without causing corruption Figure 5 5 on page 5 18 shows how a 2 lobe Lanczos windowed sinc function usually referred to as Lanczos 2 would be sampled for a 4 tap vertical filter gt The two lobes refer to the number of times the function changes direction on each side of the central maxima including the maxima itself
313. ves at the input side frame n It keeps frame n 1 for one extra iteration because it uses it with frame n to produce the next output When triple buffering is in use external RAM usually uses three frame buffers The function uses four frame buffers when you select the motion adaptive algorithm At any time one buffer is in use by the input and one two for the motion adaptive case is are in use by the output in the same way as the double buffering case The last frame buffer is spare July 2010 Altera Corporation Video and Image Processing Suite User Guide 5 26 Chapter 5 Functional Descriptions Deinterlacer This configuration allows the input and output sides to swap asynchronously When the input finishes it swaps with the spare frame if the spare frame contains data that the output frame uses Otherwise the function drops the frame which you have just wrote and the function writes a fresh frame over the dropped frame When the output finishes it also swaps with the spare frame and continues if the spare frame contains fresh data from the input side Otherwise it does not swap and just repeats the last frame Triple buffering allows simple frame rate conversion For example suppose you connect the Deinterlacer s input to a HDTV video stream in 1080160 format and connect its output i to a 1080p50 monitor The input has 60 interlaced fields per second but the output tries to pull 50 progressive frames per second If you config
314. w of the image Stalls of up to 45 clock cycles are possible due to the time taken for internal processing in between lines Select the motion adaptive algorithm so that stalls up to 90 clock cycles are possible Select double or triple buffering so that external memory decouples data input and output The MegaCore function writes non image data packets into memory by predeclaring transfers of fixed size The function cannot interrupt memory transactions immediately when it receives an endofpacket signal For each non image data packet received the number of words written into memory always corresponds to the maximum packet size defined in the MegaWizard interface Consequently the Deinterlacer MegaCore function does not handle control packets efficiently when large user defined packets are used This does not apply when reading non image packets back from the external memory because the size of each incoming packet is registered after it has been determined La When buffering is used with bob deinterlacing and fields are being discarded they are discarded at the input rather than being buffered through external RAM and then discarded This reduces the external RAM bandwidth requirement of the Deinterlacer in these modes Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 71 Stall Behavior and Error Recovery Error Recovery An error condition occurs if an endofpacket signal is
315. wever some more complex SOPC Builder components generate a separate qip file In that case the system qip file references the component qip file Simulate the System During system generation SOPC Builder generates a functional simulation model and testbench for supported cores or example design that includes a testbench which you can use to simulate your system easily in any Altera supported simulation tool SOPC Builder also generates a set of ModelSim Tcl scripts and macros that you can use to simulate the testbench and functional simulation models or clear text RTL design files that describe your system in the ModelSim simulation software July 2010 Altera Corporation Video and Image Processing Suite User Guide 2 6 Chapter 2 Getting Started with Altera Cores MegaWizard Plug In Manager Design Flow In the SOPC Builder design flow the sophistication of the testbench generated for your IP core varies by IP core The sophistication of the generated testbench also can depend on the HDL you specify for the system In most cases the testbench provides tasks that you can use to create a test sequence specific to your SOPC Builder system For information about the latest Altera supported simulation tools refer to the Quartus II Software Release Notes For information about simulating SOPC Builder systems refer to Volume 4 SOPC Builder of the Quartus II Handbook and AN 351 Simulating Nios II Embedded Processor
316. yers can be switched on and off This run time control is partly provided by an Avalon MM slave port with registers for the location and on or off status of each foreground layer The dimensions of each layer are then specified by Avalon ST Video control packets It is expected that each foreground layer fits in the boundaries of the background layer Control data is read in two steps at the start of each frame and is buffered inside the MegaCore function so that the control data can be updated during the frame processing without unexpected side effects The first step occurs after all the non image data packets of the background layer have been processed and transmitted and the core has received the header of an image data packet of type 0 for the background At this stage the on off status of each layer is read A layer can be disabled 0 active and displayed 1 or consumed but not displayed 2 The maximum number of image layers mixed cannot be changed dynamically and must be set in the MegaWizard interface for the Alpha Blending Mixer Video and Image Processing Suite User Guide July 2010 Altera Corporation Chapter 5 Functional Descriptions 5 11 Alpha Blending Mixer Non image data packets of each active foreground layer displayed or consumed are processed in a sequential order layer 1 first Non image data packets from the background layer are integrally transmitted whereas non image data packets from the foreground layers are
317. ymbols can be transmitted in parallel 2 in this example Start End cJ Packet type identifier 4 bits in least significant symbol X s for unused symbols The Avalon ST Video protocol is designed to be most efficient for transferring video data therefore the symbol bit width and the number of symbols transferred in parallel that is in one clock cycle are defined by the parameters of the video data packet types refer to Static Parameters of Video Data Packets on page 4 3 Video Data Packets Video data packets transmit video data between the MegaCore functions A video data packet contains the color plane values of the pixels for an entire progressive frame or an entire interlaced field The video data is sent per pixel in a raster scan order The pixel order is as follows 1 From the top left of the image right wards along the horizontal line 2 Atthe end of the current line jump to the left most pixel of the next horizontal line down 3 Goright wards along the horizontal line 4 Repeat 2 and 3 until the bottom right pixel is reached and the frame has been sent Static Parameters of Video Data Packets The following two static parameters specify the Avalon ST interface that video systems use July 2010 Altera Corporation Video and Image Processing Suite User Guide 4 4 Chapter 4 Interfaces Avalon ST Video Protocol Bits Per Pixel Per Color Plane The maximum number of bits that represent each color pl
318. your HDL or schematic design is not yet supported by SOPC Builder Figure 2 2 shows the stages for creating a system with an Altera IP core and the Quartus II software Figure 2 2 Altera IP Core Design Flow Select Design Flow SOPC Builder MegaWizard Flow Flow y y Specify Parameters Specify Parameters y Complete SOPC Builder System e Optional 4 y Perform gt Functional Simulation y Simulation Give Expected Results Debug Design Yes y Add Constraints and Compile Design y IP Complete The following sections describe the general steps for the use of each design flow July 2010 Altera Corporation Video and Image Processing Suite User Guide 2 4 Chapter 2 Getting Started with Altera IP Cores SOPC Builder Design Flow SOPC Builder Design Flow You can use SOPC Builder to build a system that includes your customized IP core You easily can add other components and quickly create an SOPC Builder system SOPC Builder automatically generates HDL files that include all of the specified components and interconnections The HDL files are ready to be compiled by the Quartus II software to produce output files for programming an Altera device SOPC Builder generates a simulation testbench module for supported cores that includes basic transactions to validate the HDL files Figure 2 3

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