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MC9S12DP256B Device User Guide V02.15 Covers also

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1. For More Information On This Product Go to www freescale com Bt7 BS Bit4 Bits Bt2 Biti Bit 0 1014 1013 1012 ID10 ID9 108 ID7 106 105 104 ID3 ID2 ID1 IDO RTR DB7 DB6 DB5 DB4 DB3 DB2 DBI DBO DLC3 DLC2 PRIO7 PRIO6 5 PRIO4 PRIO2 PRIO1 PRIOO TSR15 TSR14 TSR13 TSR12 TSR10 TSRO TSR8 TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSRO Motorola Scalable CAN MSCAN Bt7 BS 2 Biti Bit 0 RxrRM cswai time WUPE INITRO CLKSRC Loops Listen 9 WOPM LESER INTER SJWi SJWO BRP5 BRP4 BRP3 BRP2 1 BRPO SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 RSTATO TSTAT TSTATO aye WUPIE CSCIE RSTATE1 RSTATEO TSTATE1 TSTATEO OVRIE RXFIE 20 0 0 2 1 TXEO 0 0 2 0 TXEIE2 TXEIE1 TXEIEO p 0 0 ABTRG2 ABTRQ ABTRQO 0 0 0 0 ABTAK2 ABTAKO 0 0 0 0 TX2 TXO 0 0 NEN mm 0 IDHIT2 IDHIT1 IDHITO 0 0 0 0 0 0 0 0 41 MC9S12DP256B Device User dhkeeseale Semiconductor Inc
2. 01 0 01FF CAN Motorola Scalable CAN MSCAN Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit i Bit 0 50109 CAN2IDARS 7 AC6 5 2 AC1 ACO Read 01DA CANPIDARG AC6 5 2 ACI ACO Read 01DB CAN2IDAR7 AC6 5 2 ACI ACO 01DC 2 4 i AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO 01DD CAN2IDMR5 7 6 AM5 AM4 AM3 AM2 AM1 AMO 01DE CAN2IDMR6 e 7 AM6 AM5 AM4 AM3 AM2 AM1 AMO 01DF CAN2IDMR7 1 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO 01E0 paee Read FOREGROUND RECEIVE BUFFER see Table 1 2 01EF Write 01F0 C N2TXFG 1989 FOREGROUND TRANSMIT BUFFER see Table 1 2 01FF Write 0200 023F Motorola Scalable CAN MSCAN Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit i Bit 0 0200 us RxrRM EPXACT L9YNCH time WUPE INITRO 0201 1 CLKSRC Loops Listen 0202 SJWi SJWO BRP4 BRP3 BRP1 BRPO 0203 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0204 CANSRFLG ia wapi STATO TOTTI STATS RE aXe 0205 dns CSCIE RSTATE1 RSTATEO TSTATE1 TSTATEO OVRIE RXFIE 0206 dus 0
3. PTIH2 PTIHO 0262 DDRH DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 0263 RDRH ii RDRH7 RDRH6 RDRH5 2 RDRH1 RDRHO 0264 PERH PERH7 PERH6 5 PERH4 PERH2 0265 PPSH PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSHO 0266 PIEH Me PIEH7 PIEH6 PIEHS PIEH2 PIEH1 0267 PIFH PIFH7 PIFH6 PIFH4 PIFH3 PIFH2 PIFH1 PIFHO 0268 PTJ mc PTJ7 PTJ6 PTJ1 PTJO SES PTI7 PTIJ6 0 0 0 0 PTIJO 026A DDRJ ue DDRJ7 DDRJ7 DDRJ1 DDRJO 026B RDRJ iin RDRJ7 RDRJ6 0 0 RDRJO 026C PERJ PERJ7 PERJ6 PERJO 026D PPSJ ma PPSJ7 PPSJ6 PPSJ1 PPSJO 026E PIEJ PIEJ7 PIEJ6 PIEJ1 PIEJO 026F PIFJ ii PIFJ7 PIFJ6 2 0 PIFJO 2 Reserved Read 47 44 MOTOROLA For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 0280 02BF CANA Motorola Scalable CAN MSCAN Address m s Biz Bi 0280 bus LEXACT LSYNCH mE wUPE SLPRO INITRO 0281 e CLKSRC LOOPB LISTEN
4. Num Rating Symbol Min Max Unit 1 D External Oscillator Clock fNvMOSC 0 5 501 MHz 2 D Bus frequency for Programming or Erase Operations fyyvmBus 4 P Single Word Programming Time 5 D Flash Burst Programming consecutive word us 6 D Flash Burst Programming Time for 32 Words us 7 Sector Erase Time 9 D Blank Check Time Flash per block er 10 D Blank Check Time EEPROM per block tcheck 20587 lcyc NOTES 1 Restrictions for oscillator in crystal mode apply 2 Minimum Programming times are achieved under maximum NVM operating frequency and maximum bus frequency fous 102 For More Information On This Product Go to www freescale com 44 MOTOROLA Freescale Semicongusctemlnesevice User Guide 02 15 Maximum Erase and Programming times are achieved under particular combinations of fyymop and bus frequency fps Refer to formulae in Sections 3 1 1 A 3 1 4 for guidance urst Programming operations are not applicable to EEPROM Minimum Erase times are achieved under maximum NVM operating frequency fyymop Minimum time if first word in the array is not blank Maximum time to complete check on an erased block NOOR A 3 2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification constant process monitors and burn in to screen early life failures The failure rates for data retention and program era
5. 16 Table 1 1 Device Memory 22 Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout 41 Table 1 3 Assigned Part ID Numbers 51 Table 1 4 Memory size 5 51 Table 2 1 Signal PrObperlles o ev eS aw dered oleae ew ate eb 56 Table 2 2 MC9S12DP256 Power and Ground Connection 69 4 1 Mode Selection ee ARE ERA EF NERA ERE 73 Table 4 2 Clock Selection Based on 7 73 Table 4 3 Voltage Regulator 74 Table 5 1 Interrupt Vector Locations 77 Table 6 1 Configuration of HCS12 Core 81 Table A 1 Absolute Maximum Ralings s pean Eee ee eee ee 89 Table A 2 ESD and Latch up Test 90 Table A 3 ESD and Latch Up Protection 90 Table A 4 Operating Conditions ow ees 91 Table A 5 Thermal Package Characteristics 93 Table 6 5V I O Characteristics 94 Table
6. 60 2 3 3 TEST e IRE heb 60 2 3 4 VREGEN Voltage Regulator Enable 60 2 3 5 Loop Filter PIE uos iid o rette ER 60 2 3 6 BKGD TAGHI Background Debug Tag High and Mode Pin 60 2 3 7 PAD15 AN15 ETRIG1 Port AD Input Pin of ATD1 60 2 3 8 PAD 14 08 AN 14 08 Port AD Input Pins of ATD1 61 2 3 9 PAD ANO7 ETRIGO Port AD Input Pin of 61 2 3 10 PAD 06 00 AN 06 00 Port AD Input Pins of ATDO 61 2 3 11 PA 7 0 ADDR 15 8 DATA 15 8 Port Pins 61 2 3 12 PB 7 0 ADDR 7 0 DATA 7 0 Port Pins 61 2 3 13 PE7 NOACG XGLKS Port E I O ror RR m Re 61 2 3 14 PEO MODB IPIPE1 Port 61 2 39 15 PED ZMODA IPIPEO BPortE I PIT eee 62 2 3 16 PE4 ECLK Port E I O Pin 4 ERE 62 2 3 17 PE3 LSTRB TAGLO Port 62 2 3 18 2 2 62 23 19 PETZIRO Port 1 en 62 2 3 20 PEO XIRQ Port E Input Pin
7. 62 44 MOTOROLA 5 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc 2 3 21 2 3 22 2 3 23 2 3 24 2 3 25 2 3 26 2 3 27 2 3 28 2 3 29 2 3 30 2 3 31 2 3 32 2 3 33 2 3 34 2 3 35 2 3 36 2 3 37 2 3 38 2 3 39 2 3 40 2 3 41 2 3 42 2 3 43 2 3 44 2 3 45 2 3 46 2 3 47 2 3 48 2 3 49 2 3 50 2 3 51 2 3 52 2 3 53 2 3 54 2 3 55 2 3 56 PHY KWH7 79592 Port 1 7 62 PH6 KWH6 SCK2 Port 6 62 KWH5 MOSI2 Port 5 63 PHA KWH4 502 2 63 PH3 KWH3 SS1 Port 63 PH2 KWH2 SCK1 Port 1 2 63 KWH1 MOSI1 Port H VO Pin 1 63 PHO KWHO MISO1 Port 0 63 PJ7 KWJ7 TXCAN4 SCL 7 63 PJ6 KWJ6 SDA 6 64 PJ 1 0 KWJ 1 0 Port J 5 1 0 64 PK7 ECS ROMONE Port K l O Pin 7 nmn Rs 64 PK 5 0 XADDR 19 14 Port K I O Pins 5 0 64 PM
8. PERMO 0255 PPSM e 5 7 5 6 5 5 PPSM4 PPSM3 5 2 PPSM1 0256 WOMM 1 WOMM7 6 WOMMS WOMM4 WOMM3 WOMM 1 WOMMO 0257 MODRR MODRR6 MODRRS5 MODRR3 MODRR2 MODRR1 MODRRO Read 0258 PTP PTP6 PTPS PTP4 PTP2 1 PTPO 46 M For More Information On This Product Go to www freescale com 0240 027F Freescale Semicongucteomolnesevice User Guide 02 15 PIM Port Integration Module PIM 9DP256 Address Bt7 Bt5 2 Biti Bit 0 T WE PTIP7 PTIPe 5 PTIP2 025A DDRP e DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRPO 025B RDRP c RDRP7 RDRP6 RDRP5 RDRP3 RDRP2 RDRP1 RDRPO 025C PERP ew PERP7 PERP6 5 PERP4 PERP3 PERP2 PERPO 025D PPSP ae PPSP7 PPSP6 5 PPSP4 PPSP3 PPSP2 PPSP1 PPSSO 025E PIEP e PIEP7 6 PIEP3 PIEP2 025F PIFP Hoa PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFPO 0260 PTH 4 PTH7 PTH6 PTHS PTH4 PTH3 PTH2 PTH1 PTHO ii Bin ie PTIH7 6
9. 0 0 0 C 05 Se 0 0 2 20 0 gt 0 S A Z SOE ITTI TEE gt gt gt 7 x x x 5 9 lt 0 27 cC tco xg Ax 0 aQoooeo 6odxoo VRH VDDA PAD15 AN15 ETRIG1 PAD07 ANO7 ETRIGO PAD14 AN14 06 06 PAD13 AN13 05 05 PAD12 AN12 04 04 PAD11 AN11 PAD10 AN10 02 02 PAD09 ANO9 PADO1 ANO1 PAD08 AN08 PADOO ANOO VSS2 VDD2 PA7 ADDR15 DATA15 PA6 ADDR14 DATA14 PAS ADDR13 DATA13 PA4 ADDR12 DATA12 PA3 ADDR11 DATA11 PA2 ADDR10 DATA10 PA1 ADDR9 DATA9 PAO ADDR8 DATA8 Signals shown in Bold are not available on the 80 Pin Package Figure 2 1 Pin Assignments in 112 pin LQFP For More Information On This Product Go to www freescale com 44 MOTOROLA SS1 PWM3 KWP3 PP3 SCK1 PWM2 KWP2 PP2 MOSI1 PWM1 KWP1 PP1 MISO1 PWMO KWPO PPO M MOTOROLA OCO PTO 1 1 OC7 PT7 MODC TAGHI BKGD ADDRO DATAO PBO ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4 Freescale Semiconguctemolnenaevice User Guide 02 15 0014 Co PM4 RXCAN2 RXCANO RXCAN4 MOSIO PM5 TXCAN2 TXCANO TXCAN4 SCKO PJ6 KWJ6 RXCAN4 SDA PM2 RXCAN1 RXCANO MISOO PJ7 KWJ7 TXCAN4 SCL PP4 KWP4 PWM4 MISO2 PP5 KWP5 P
10. 0180 01BF Motorola Scalable CAN MSCAN Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit i Bit 0 Read 0 0 0 0 0 0 0 0 018D Reserved Write Read RXERR7 RXERR6 5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR 018E CANTRXERR e S 0 Read TXERR7 TXERR6 TXERRS TXERR4 TXERR3 TXERR2 TXERR 018F CANITXERR 1984 2 Write Read 0190 CANIIDARO 00 AC6 5 2 ACI ACO Read 0191 AC6 5 2 ACI ACO Read 0192 CANIIDAR2 00 AC6 5 2 ACI ACO Read 0193 CAN IDARS AC6 5 2 ACI ACO 0194 CAN1IDMRO 2 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO Read 0195 CANTIDMR1 282 AM7 AM6 AMS AM4 AM3 AM2 AMO 0196 CAN1IDMR2 E 6 AMS 4 AMO 0197 CAN1IDMR3 2 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO Read 0198 CANIIDAR4 AC6 5 AC2 ACI ACO Read 0199 CANIIDARS AC6 5 2 ACI ACO Read 019A CAN IDARG AC6 5 2 ACI ACO Read 50198 CANIIDAR7 AC6 5 2 ACI ACO 019C CANTIDMR4 AM7 6 5 4 2 AMI AMO 019D CAN1IDMR5 e AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO 019E CAN1IDMRG 7 AM6 AM5 AM4 AM3 AM2 AM1 AMO 019F CAN1
11. 0120 013F ATD1 Analog to Digital Converter 10 Bit 8 Channel Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O R 0 0 i D Write Read 0 0 0 0 0 0 0 0 0121 ATDICTL 0122 ATDICTL2 c ADPU AFFC ETRIGP ETRIG ASCE Read 0 0123 ATDICTL3 Wae SBC S4C S2C SiC FIFO FRZi FRZO 0124 ATDICTL4 i SRES8 SMP1 SMPO PRS4 PRS3 PRS2 PRS1 PRSO Read 0 0125 ATDICTLS Wae DIM DSGN SCAN MULT E CC CB CA Read F ETORF FIFOR 2 CCO GATOS EH LITER Eme Write Read 0 0 0 0 0 0 0 0 0127 Reserved Write EE R 0 0 dde Write R 0155 ol Write Read 0 0 0 0 0 0 0 0 012A Reserved WA S a RS Read F7 F F F4 E F2 Fi CCFO CCF6 CCF5 CC CCF3 CC CC Write Read 0 0 0 0 0 0 0 0 012C Reserved m l 012D ATDiDIEN 1929 gi 6 5 4 3 2 1 Bit 0 Write Read 0 0 0 0 0 0 0 0 012 Reserved Write m mms Read 4 2 1 BIT 0 smer Write Read 14 1 12 11 1 Bit8 01907 ORDA RO Write Read Bi 0 0 Write Bitt 14 1 12 11 1 Bit8 quida Write Bit
12. For More Information On This Product Go to www freescale com Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 RXERR7 RXERR6 RXERR5 RXERRS RXERR2 RXERR1 RXERRO TXERR7 TXERR6 TXERRS TXERR4 TXERRS TXERR2 TXERR1 TXERRO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 5 4 2 1 AM7 AM6 5 AM4 2 1 7 AM6 5 AM4 2 1 7 AM6 5 AM4 AM3 AM2 1 AC7 6 5 ACA 2 1 7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 5 AM4 2 1 7 AM6 5 AM4 2 1 7 AM6 5 AM4 2 1 7 AM6 5 AM4 AM3 AM2 1 FOREGROUND RECEIVE BUFFER see Table 1 2 FOREGROUND TRANSMIT BUFFER see Table 1 2 45 MC9S12DP256B Device User dhkeese ale Semiconductor Inc 0240 027F PIM Port Integration Module PIM 9DP256 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0240 im PTT7 PTT6 PTT5 4 PTT2 1 PTTO Read PTIT7 6 5 4 PTH2 1 0241 PTIT Write 0242 DDRT e DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2
13. Bits Bt2 Biti Bit 0 0100 FCLKDIV PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIVO Read KEYEN NV NV4 NV NV2 EC1 E 0101 FSEC pad 6 5 3 SEC SECO Write 0102 192 g 0 Write 0103 FCNFG e CBEIE KEYACC 2 0 BKSEL1 BKSELO 0104 FPROT 4 FPOPEN NV6 FPHDIS 1 FPHSO FPLDIS FPLS1 FPLSO 0105 FSTAT bin CBEIF BLANK 0106 FCMD eng CMDB6 5 00 0 0107 Reserved for Read 0 0 0 0 0 0 0 0 Factory Test Write 0108 FADDRH Peed 0 Bit 14 13 12 11 10 9 Bit 8 Write 0109 FADDRLO 192 6 5 4 3 2 1 Bit 0 Write 010A FDATAH 1930 Bit 15 14 13 12 11 10 9 Bit 8 Write 0108 FDATALO 1932 6 5 4 3 2 1 Bit 0 Write Read 0 0 0 0 0 0 0 0 010C Reserved Write 36 M MOTOROLA For More Information On This Product Go to www freescale com 0100 Address 010D 010E 010F 0110 Address 0110 0111 0112 0113 0114 0115 0116 0117 0118 0119 011A 011B 011C Address 011C 011D 011E 011F M MOTOROLA 010F Name Reserved Reserved Reserved 011B Name ECLKDIV Reserved Reserved for Factory Test ECNFG EPROT ESTAT ECMD Reserved for Factory Test EADDRHI EADDRLO EDATAHI EDATALO 011F Name Reserved Rese
14. is a general purpose input or output pin During MCU expanded modes of operation the NOACC signal when enabled is used to indicate that the current bus cycle is an unused or free cycle This signal will assert when the CPU is not using the bus The XCLKS input selects between an external clock or oscillator configuration The state of this pin is latched at the rising edge of RESET If the input is a logic low the EXTAL pin is configured for an external clock drive If input is a logic high an oscillator circuit is configured on EXTAL and XTAL Since this pin is an input with a pull up device if the pin is left floating the default configuration is an oscillator circuit on EXTAL and XTAL 2 3 14 PE6 IPIPE1 Port E I O Pin 6 is a general purpose input or output pin It is used as MCU operating mode select pin during reset The state of this pin is latched to the MODB bit at the rising edge of RESET This pin is shared with the instruction queue tracking signal IPIPE1 This pin is an input with a pull down device which is only active when RESET is low M MOTOROLA 61 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 2 3 15 MODA IPIPEO Port E I O Pin 5 15 a general purpose input or output pin It is used as MCU operating mode select pin during reset The state of this pin is latched to the MODA bit
15. EE E E 66 PS5 MOSIO Port 5 67 PS47MISOD Port S l O Pin oot E teh wheres SES EAE 67 Parm S VORN des E ESO SPP 67 PS2 RXD1 Port 5 2 67 PS1 TXDO Port 5 1 1 67 For More Information On This Product Go to www freescale com Freescale Semicongucteomolnesevice User Guide 02 15 2 3 57 PS0 ARXDO Port S V O Pin Oe to est vM eR SUE v 67 2 3 58 7 0 1 7 0 Port T I O 1 5 7 0 67 24 Power Supply IBS ved eor ihi dde dcs qox Das rios idv we oe eB eels ate ined 67 2 4 1 VDDX VSSX Power amp Ground Pins for I O 68 2 4 2 VDDR VSSR Power amp Ground Pins for I O Drivers amp for Internal Voltage Regulator 68 2 4 3 VDD1 VDD2 VSS1 VSS2 Core Power 68 2 4 4 VDDA VSSA Power Supply Pins for and VREG 68 2 4 5 VRH VRL Reference Voltage Input Pins 68 2 4 6 VDDPLL VSSPLL Power Supply Pins for _ 68 2 4 7 VREGEN On Chip Voltage Regulator 69 Section 3 System Clock Description 3 1 OVERVIEWS respecter Ea oe re d em e d ee t
16. 2 User Guide 02 15 Section 5 Resets and Interrupts 5 1 Overview Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and interrupts 5 2 Vectors 5 2 1 Vector Table Table 5 1 lists interrupt sources and vectors in default order of priority Table 5 1 Interrupt Vector Locations FFFC FFFD FFFA FFFB Clock Monitor fail reset COP failure reset Vector Address Interrupt Source ire Local Enable FFFE FFFF Reset None None PLLCTL CME SCME FFF8 FFF9 Unimplemented instruction trap None COP rate select None None FFFO FFF1 Real Time Interrupt SFFFT Sw FFF4 FFF5 XIRQ X Bit None FFF2 FFF3 IRQ I Bit IRQCR IRQEN F2 CRGINT RTIE FFDE FFDF Enhanced Capture Timer overflow FFEE FFEF Enhanced Capture Timer channel 0 I Bit TIE COI EE FFEC FFED Enhanced Capture Timer channel 1 TIE C11 EC FFEA FFEB Enhanced Capture Timer channel 2 FFE8 FFE9 Enhanced Capture Timer channel 3 I Bit TIE E8 FFE6 FFE7 Enhanced Capture Timer channel 4 I Bit TIE CAI E6 FFE4 FFE5 Enhanced Capture Timer channel 5 TIE E4 FFE2 Enhanced Capture Timer channel 6 I Bit TIE C61 E2 FFEO FFE1 Enhanced Capture Timer channel 7 I Bit TIE C71 TSRC2 TOF DE FFCA FFCB M MOTOROLA Modulus Down Counter
17. 2 3 43 PP6 KWP6 PWM6 552 Port P I O Pin 6 PP6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 6 output It can be configured as slave select pin SS of the Serial Peripheral Interface 2 SPI2 2 3 44 PP5 KWP5 PWM5 MOSI2 Port P I O Pin 5 PP5 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 5 output It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 2 SPI2 M MOTOROLA 65 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 2 3 45 PP4 KWP4 PWMA MISO2 Port P I O Pin 4 PP4 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 4 output It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 2 SPI2 2 3 46 PP3 KWP3 PWM3 551 Port P I O Pin PP3 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to
18. 5 XADDR19 EXTAL Module COP Watchdog Clock Monitor RESET Breakpoints PEO XIRQ PE1 ae System Enhanced Capture Integration Timer LSTRB Module ECLK SIM PES MODA PE6 MODB PE7 NOACC XCLKS PS3 PS4 Multiplexed Address Data Bus PS5 PS6 PS7 a E 71850 TXB PMO RXCAN 1 2 CANO _ o 5 2 92 95 MEBANE AN PXCAN FEM 4 RXCAN 5 2 o nanana oGoooooaoaoao XCAN PM6 S lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt RXCAN PM7 8 iuri TXOAN 1 i 8 Yer KNEE UP I Usu 5 1 7 Multiplexed z 2 222958 E Narrow Bus amp amp amp amp amp amp lt i Internal Logic 2 5V Driver 5V VDD1 2 lt VDDX VSS1 2 VSSX alls 1 A D Converter 5V amp PLL 2 5V Voltage Regulator Reference VDDPLL lt VDDA gt VSSPLL mex VSSA z Voltage Regulator 5V amp VDDR gt VSSR M MOTOROLA 21 For More Information On This Product Go to www freescale com MC9S12DP256B Device
19. PWMCNT4 0 0 0 0 0 0 0 0 Read 6 5 4 3 2 1 Bit 0 0081 5 0 0 0 0 0 0 0 0 Read 6 5 4 3 2 1 Bit 0 80082 PWMCNT6 Write 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 00B3 PWMCNT7 6070 0 0 0 0 0 0 0 0084 PwMPERo 198 pi 6 5 4 3 2 1 Bit 0 Write 0085 1980 6 5 4 3 2 1 Bit 0 Write 0086 PwMPER2 1 6 5 4 3 2 1 Bit 0 Write 0087 PwMPER3 1 6 5 4 3 2 1 Bit 0 Write 0088 PwMPER4 198 6 5 4 3 2 1 Bit 0 Write 32 44 MOTOROLA For More Information On This Product Go to www freescale com 00A0 00C7 Address 00B9 00BA 00BB 00BC 00BD 00BE 00BF 00 0 00 1 00C2 00C3 00C4 00C5 00C6 00C7 Name PWMPER5 PWMPER6 PWMPER7 PWMDTYO PWMDTY 1 PWMDTY2 PWMDTY3 PWMDTY4 PWMDTY5 PWMDTY6 PWMDTY7 PWMSDN Reserved Reserved Reserved 00C8 00CF Address 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF 44 MOTOROLA Name SCIOBDH SCIOBDL SCIOCR1 SCIOCR2 SCIOSR1 SCIOSR2 SCIODRH SCIODRL Freescale Semiconguceteomolnesevice User Guide 02 15 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write
20. 5 3 PemDmeema riw 68 L7 r esrmesaenmey 395 8 1 5 8 Bit Absolute Error 1 5 1 0 Counts NOTES 1 These values include the quantization error which is inherently 1 2 count for any A D converter ELI NETS 1 2 0 For the following definitions see also Figure 1 Differential Non Linearity DNL is defined as the difference between two adjacent switching steps nu DNL i 1 1LSB The Integral Non Linearity INL is defined as the sum of all DNLs n V V _ DR 0 INL n DNL rsg 99 M MOTOROLA For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc DNL 10 Bit Absolute Error Boundary A Vi da Vi RET 8 Bit Absolute Error Boundary 7 3FE 2 7 3FD 4 7 SFG SS SS 7 3FB 7 3FA y 2 3F9 7 FE 3F8 r 3F7 7 3F6 7 3F5 2 4 7 FD 10 3F3 7 9 7 deal Transfer Curve Z 2t 7 7 Z 7 IN10 Bit Transfer Curve 8 Bit Resolut N 10 Bit Resolution 1 N N x N 8 Bit Transfer Curve N 7 gt 50 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin T L iles tA tA N 9
21. 017F Motorola Scalable Can CANO 64 0180 01BF Motorola Scalable Can 64 01 0 01FF Motorola Scalable Can CAN2 64 0200 023F Motorola Scalable Can 64 0240 027F Port Integration Module PIM 64 0280 02BF Motorola Scalable Can 64 02 0 03FF Reserved 320 0000 0FFF EEPROM array 4096 1000 3FFF RAM array 12288 4000 7FFF Fixed Flash EEPROM 16384 58000 BFFF Flash EEPROM Page Window 16384 C000 FFFF Fixed Flash EEPROM 16384 For More Information On This Product Go to www freescale com 44 MOTOROLA Freescale Semicongucteom lnesevice User Guide 02 15 Figure 1 2 MC9S12DP256B Memory Map on REGISTERS 0400 Mappable to any 2k Block within the first 32K 4K Bytes EEPROM 1000 Mappable to any 4K Block 12K Bytes RAM Mappable to any 16K and alignable to top or 4000 bottom 16K Fixed Flash Page 3E 62 This is dependant on the state of the ROMHM bit 8000 16K Page Window 16 x 16K Flash EEPROM pages C000 16K Fixed Flash Page 3F 63 KRS M BDM 4 if active corre m emm FFFF 0292929292929 EXPANDED NORMAL SPECIAL SINGLE CHIP SINGLE CHIP Assuming that a 0 was driven onto port K bit 7 during MCU MOTOROLA 23 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 1 6 Detaile
22. 119 General Muxed Bus 119 Appendix B Package Information B 1 B 2 B 3 M MOTOROLA General mte nde enu See eee M MM 123 112 LQFP packager E t eed iicet 124 80 QFP Dac a ees rl 125 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 10 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguctemolnesevice User Guide 02 15 List of Figures Figure 0 1 Figure 1 1 Figure 1 2 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 3 1 Figure 20 1 Figure 20 2 Figure A 1 Figure A 2 Figure A 3 Figure A 4 Figure A 5 Figure A 6 Figure A 7 Figure A 8 Figure A 9 Figure B 1 Figure B 2 M MOTOROLA Order Part Number 16 MC9S12DP256B Block Diagram vaa see EP 21 MC9S12DP256B Memory 24 Pin Assignments 112 pin Pea var ERE SE a tee a Bhs Gok es 54 Pin Assignments in 80 pin QFP for 9512 9256 55 Pin Assignments 80 pin QFP for MC9812DJ256 56 PLL Loop Filler Connections ccc roh dex RR EUER E XY RENE eq 60 Glock CONMCCHONS 22 6 ised e REOS 71 Re
23. CSCIF CSCIE 0 0 0 RXERR6 TXERR6 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 AC6 Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 RSTATE1 0 0 RXERR5 TXERR5 AC5 AC5 AC5 AC5 5 5 5 5 AC5 Bit 4 SYNCH LISTEN BRP4 TSEG20 RSTATO RSTATEO 0 0 RXERR4 TXERR4 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 AC4 Bit 3 TIME 0 BRP3 TSEG13 TSTAT1 TSTATE1 0 0 0 RXERR3 TXERR3 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 AC3 For More Information On This Product Go to www freescale com Bit 2 WUPE WUPM BRP2 TSEG12 TSTATO TSTATEO TXE2 TXEIE2 ABTRQ2 ABTAK2 TX2 IDHIT2 0 0 RXERR2 TXERR2 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 AC2 Bit 1 SLPRQ SLPAK BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1 TX1 IDHIT1 0 0 TXERR1 AC1 AC1 AC1 AC1 1 1 1 1 1 Bit 0 INITRQ INITAK BRPO TSEG10 RXF RXFIE TXEO TXEIEO ABTRQO ABTAKO TXO IDHITO 0 0 RXERRO TXERRO ACO ACO ACO ACO AMO AMO AMO AMO ACO 43 MC9S12DP256B Device User dhkeese ale Semiconductor Inc
24. M MOTOROLA For More Information On This Product Go to www freescale com 105 MC9S12DP256B Device User dhkeese ale Semiconductor Inc 106 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicongusctemolnesevice User Guide 02 15 A 5 Reset Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase Locked Loop PLL A 5 1 Startup Table A 14 summarizes several startup characteristics explained in this section Detailed description of the startup behavior can be found in the Clock and Reset Generator CRG Block User Guide Table A 14 Startup Characteristics Conditions are shown in Table A 4 unless otherwise noted NNNM T POR assert level 0 97 D Reset input pulse width minimum input time losc ERU IIT EN NNNM NES D Interrupt pulse width IRQ edge sensitive mode 6 D Wait recovery startup time twrs 14 lcyc A 5 1 1 POR The release level and the assert level are derived from the VDD supply They are also valid if the device is powered externally After releasing the POR reset the oscillator and the clock quality check are started If after time valid oscillation is detected MCU will start using the internal self clock The fastest startup ti
25. 10 The stabilization delays shown in Table A 16 are dependant on PLL operational settings and external component selection e g crystal XFC filter A 5 3 2 Jitter Information The basic functionality of the PLL is shown in Figure A 2 With each transition of the clock femp the deviation from the reference clock is measured and input voltage to the VCO is adjusted accordingly The adjustment is done continuously with no abrupt changes in the clock output frequency Noise voltage temperature and other factors cause slight variations in the control loop resulting in a clock jitter This jitter affects the real minimum and maximum clock periods as illustrated in Figure A 3 110 44 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguctemolnesevice User Guide 02 15 Figure A 3 Jitter Definitions The relative deviation of thom number of clock periods N is at its maximum for one clock period and decreases towards zero for larger Defining the jitter as N t nom N t nom J N mad tmin N For N lt 100 the following equation is a good fit for the maximum jitter 1 5 10 20 Figure 4 Maximum bus clock jitter approximation M MOTOROLA 111 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc This is very important to notice with respect to time
26. 2 3 21 PH7 KWH7 SS2 Port H Pin 7 PH7 is a general purpose input or output pin It can be configured to generate an interrupt causing the to exit STOP or WAIT mode It can be configured as slave select pin SS of the Serial Peripheral Interface 2 SPD 2 3 22 PH6 KWH6 SCK2 Port H I O Pin 6 PH6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 SPD 62 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicongauctenm Inesevice User Guide V02 15 2 3 23 KWH5 MOSI2 Port H I O Pin 5 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 2 SPI2 2 3 24 PHA MISO2 Port I O Pin 2 PH4 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 2 SPI2 2 3 25 PH3 KWH3 SS1 Port H I O Pin PH3 is a general purpose input or output pin It can be co
27. Consult the BDLC Block User Guide for information about the J1850 module Section 14 Pulse Width Modulator PWM Block Description Consult the 8B8C Block User Guide for information about the Pulse Width Modulator module Section 15 Flash EEPROM 256K Block Description Consult the FTS256K Block User Guide for information about the flash module Section 16 EEPROM 4K Block Description Consult the EETS4K Block User Guide for information about the EEPROM module Section 17 RAM Block Description 82 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicongucteomlnesevice User Guide 02 15 This module supports single cycle misaligned word accesses Section 18 MSCAN Block Description There are five MSCAN modules CAN3 CAN2 CANI and CANO implemented on the MC9S12DP256B Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module Section 19 Port Integration Module PIM Block Description Consult the 9DP256 Block User Guide for information about the Port Integration Module Section 20 Voltage Regulator Block Description Consult the VREG Block User Guide for information about the dual output linear voltage regulator Component Purpose Type Value C1 VDD 1 filter cap VDD2 filter cap ceramic X7R 100 220nF ceramic X7R 100 220nF VDDA filter cap ceramic X7R 100nF VDDR filter cap VDDPLL fil
28. Core Power Pins Power is supplied to the MCU through VDD and VSS Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible This 2 5V supply is derived from the internal voltage regulator There is no static load on those pins allowed The internal voltage regulator is turned off if VREGEN is tied to ground NOTE No load allowed except for bypass capacitors 2 4 4 VDDA VSSA Power Supply Pins for ATD and VREG VDDA VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter It also provides the reference for the internal voltage regulator This allows the supply voltage to the ATD and the reference voltage to be bypassed independently 2 4 5 VRH VRL Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter 2 4 6 VDDPLL VSSPLL Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased Locked Loop This allows the supply voltage to the Oscillator and PLL to be bypassed independently This 2 5V voltage is generated by the internal voltage regulator NOTE No load allowed except for bypass capacitors 68 M MOTOROLA For More Information On This Product Go to www freescale com Table 2 2 MC9S12DP256 Power and Ground Connection Su
29. DOCUMENT NUMBER Freescale Semiconductor Inc 9S12DP256BDGV2 D MC9S12DP256B Device User Guide V02 15 Covers also MC9S12DT256C 9 1204256 95120 256 MC9S12DT256B 95120 256 MC9S12DG256B MC9S12A256B Original Release Date 29 Mar 2001 Revised Jan 11 2005 Motorola Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding t
30. MOTOROLA 2 For More Information On This Product Go to www freescale com Freesqase SemicaneuctotwidAc 9s12pPp256BDGV2 D 02 15 Version Revision Effective Number Date Date 24 August 2001 V02 08 Author Description of Changes Corrected local enable bits in interrupt vector table Corrected 33 36 in table A 20 A 4 Voltage Regulator characteristics was removed A 1 to A 7 major rework according to feedback from PE V02 09 V02 10 Changed document name and title to MC9 Added table containing other devices covered by this document Added NVM Blank check specificaiton Added external ADC trigger to pin description Updated A 7 Supply Current Characteristics Updated TableO 1 Derivative Differences Added Item8 to Table 8 IOL IOH reduced to 10mA 2mA for full reduced drive Changed ATD characteristic Cins max to 22pF Changed VDD min VDDPLL min to 2 35V Removed Oscillator startup time from POR or STOP changed input capacitance for standard i o pin to 6pF V02 11 V02 12 Corrected NVM reliability spec added derivative differences for part number 95120256 added partlD and maskset number for MC9S12D256D added table with fixed defects on 2K79X added table for HCS12 core configuration Added detailed register map Added pull device description to signal table V02 13 corrected tables 0 1 and 0 2 Derivative Differences added 80QFP DG256 pin assignment diagram V02 14 added A256B pa
31. Read Write Read Write PWM Pulse Width Modulator 8 Bit 8 Channel Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 PWMIF PWMIE pa PWMLVL PWM7IN dida 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCIO Asynchronous Serial Interface Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 i SBR12 SBR11 SBR10 5889 SBR8 SBR7 SBR6 SBR5 5884 5883 5882 5881 SBRO LOOPS SCISWAI RSRC M WAKE ILT PE PT TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PF 8 9 BRK13 TXDIR BAE R8 0 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 RO 7 6 5 T4 T3 T2 1 TO 33 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc 00DO 00D7 SCH Asynchronous Serial Interface Address Bis 2 Read 0 0 0 50000 SCHBDH p SBRI2 SBR11 8810 SBR9 SBRE 00D1 SCHBDL ue
32. SBR7 SBR6 SBR5 SBR4 SBR3 SBR SBRi SBRO 00D2 SCHCR1 e LOOPS SCISWAI RSRC M WAKE PE PT Read 0003 SCHCR2 TCIE RIE ILIE RWU SBK 00D4 scHsmi Read TC RDRF IDLE OR NF BE PF Write 0005 SCHSR2 BRK13 80005 Sapra LLL s Write Read R7 R6 R5 R4 R3 R2 R1 RO 00D7 SCIHDRL Write Te l ts 00D8 00DF SPIO Serial Peripheral Interface Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit i Bit O 0008 SPIOCR1 4 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0009 SPIOCR2 MODFEN BIDIROE sPISWAI sPCO 00DA SPIOBR eng SPPR2 SPPR1 1 0 spre spri SPRO Read SPIF PTEF MODF 0008 SPIOSR Ui UN Write Read 0 0 0 0 0 0 0 0 00DC Reserved Write DER 00DD splooR 19 6 5 4 3 2 1 Write Read 0 0 0 0 0 0 0 0 00DE Reserved Write DD a a Read 0 0 0 0 0 0 0 0 00DF Reserved Write _ 00 0 00E7 Inter IC Bus Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit i Bit O 00 0 IBAD d ADR7 ADR6 ADRS ADR4 ADR2 ADRI 0 Read 00E1 IBFD 18 7 Bce IBCS IBC4 IBC3 IBC2 IBCO Read 0 0 00E2 IBCR Ware BEN IBIE MS SL TX RX TXAK sy pe IBSWAI gue
33. added PCB layout proposal for power and ground connections 11 July 2001 V02 05 V02 06 Added Document Names Variable definitions and Names have been hidden Added Maskset 1K79X Modified description in chapter A 5 2 Oscillator V02 07 Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part M
34. 0 12 11 10 0 0 SMRST DLOOP NBFS TEOD TSIFR TMIFR1 TMIFRO D7 D6 D5 D4 D3 D2 D1 Do RXPOL 0 BO2 BO1 BOO R5 R4 R3 R2 R1 RO 0 0 0 SERE 0 0 0 0 0 0 0 0 0 0 0 IDLE SPI1 Serial Peripheral Interface Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 MODFEN BIDIROE 0 SPISWAI SPCO SPPR2 SPPR1 SPPRO SPR2 SPR1 SPRO SPIF 0 SPTEF MODF 0 0 0 0 0 0 0 0 0 0 0 0 Bit7 6 5 4 3 2 1 Bito 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 00F8 00FF SPI2 Serial Peripheral Interface Address Name Bt7 Bt5 Bits Bt2 Bit Bit 0 00F8 SPI2CRI1 im SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 00F9 2 VODFEN BIDIROE 2 sPISWAI sPCO 00FA SPI2BR eng eee 2 8 sPPRo 0 4 spre 1 sPRO eves ssa Pead 0 SPTEF MODF 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 00FC Reserved Write SS Sa O Se aa ee 00FD sppr 1984 6 5 4 3 2 1 Bito Write Read 0 0 0 0 0 0 0 0 00 Reserved Write Read 0 0 0 0 0 0 0 0 00FF Reserved Write De SS SS M 0100 010F Flash Control Register fts512k4 Address Name Bt7 Bt5
35. 0 0 TXE2 1 TXEO 0207 CAN3TIER 0 0 TXEIE2 TXEIE1 TXEIEO 0208 e 0 0 0 ABTRG2 ABTRQ ABTRQO EL m 0 0 0 ABTAK ABTAKO Write 020A CANSTBSEL e 0 0 TX2 TXi 020B E 0 IDAM1 IDAMO 9 LUE A Read 0 0 0 0 0 0 0 0 020C Reserved Write 44 M MOTOROLA For More Information On This Product Go to www freescale com 0200 Address 020D 020E 020F 0210 0211 0212 0213 0214 0215 0216 0217 0218 0219 021A 021B 021C 021D 021E 021F 0220 022F 0230 023F M MOTOROLA 023F Name Reserved CAN3RXERR CAN3TXERR CAN3IDAR2 CAN3IDMR2 5 CAN3IDAR6 CAN3IDAR7 CAN3IDMR4 CAN3IDMR5 CAN3IDMR6 CAN3IDMR7 CAN3RXFG CAN3TXFG Freescale Semicongucteomolnensevice User Guide 02 15 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write CAN3 Motorola Scalable CAN MSCAN
36. 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 31 MC9S12DP256B Device User dhkeese ale Semiconductor Inc 0040 00C7 PWM Pulse Width Modulator 8 Bit 8 Channel Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O 00A0 PWME iu PWME7 PWME6 PWMES PWME4 PWME3 PWME2 PWME1 PWMEO 00A1 PWMPOL PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOLO 00A2 PWMCLK e PCLK7 PCLK6 5 PCLK4 PCLK3 PCLK2 PCLK1 PCLKO Read 0 0 0043 PWMPRCLK e PCKB2 1 py PCKA2 1 00A4 PWMCAE e CAE7 CAE6 CAES CAE4 CAE 1 CAEO Read 0 0 00A5 PWMCTL CON45 CON23 CONO1 PSWAI PFRZ ir PWMTST 0 0 0 0 0 0 0 0 Test Only Write R 007 PwMPRsc 19844 0 8 2 0 0 0 0 0 Write 008 PWMSCLA 10 6 5 4 3 2 1 Bit 0 Write 009 PwMscLB 198 6 5 4 3 2 1 Bit 0 Write R 00 PWMscNTA 1984 0 0 0 0 9 i Write R 2 00 1984 0 0 0 0 0 0 0 0 Write Read Bit7 6 5 4 3 2 1 Bit 0 00AC PWMCNTO Write 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 00AD PWMCNT1 0 0 0 0 0 0 0 0 Read 6 5 4 3 2 1 Bit 0 00 PWMCNT2 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 00AF PWMCNT3 0 0 0 0 0 0 0 0 Read 6 5 4 3 2 1 Bit 0 0080
37. Block Description 7 1 Device specific Intofffialloh berto Ce ote galee prs e gb tbe pad ms 81 7 1 1 EL 81 Section 8 Enhanced Capture Timer ECT Block Description Section 9 Analog to Digital Converter ATD Block Description Section 10 Inter IC Bus Block Description Section 11 Serial Communications Interface SCI Block Description Section 12 Serial Peripheral Interface SPI Block Description Section 13 J1850 BDLC Block Description Section 14 Pulse Width Modulator PWM Block Description Section 15 Flash EEPROM 256K Block Description Section 16 EEPROM 4K Block Description Section 17 RAM Block Description Section 18 MSCAN Block Description Section 19 Port Integration Module PIM Block Description Section 20 Voltage Regulator VREG Block Description Appendix A Electrical Characteristics Ad General E LC CTI 87 1 1 Parameter Classification RE BRE ee peed ees 87 A 1 2 Power Supply vocem ttd eor SESS EU uo p deo cd 87 A 1 3 RU RT RR e N RU EI NE M NP 88 A 1 4 ss uos 2644 5 bep ERE EE e EE RR b Weit dites 89 A 1 5 Absolute Maximum a wows enter pido RE VR V eere 89 A 1 6 ESD Protection and Latch up 90 8 44 MOTOROLA For More Information On This Product Go to www freescale com A 1 7 A 1 8 A 1 9 A 1 10 A 2 A 2 1 A 2 2 A 2 3 A 3 A 3 1 A 3 2 A 4 A 5 A 5 1 A 5 2 A 5 3 A
38. FFA7 wake up CAN2RIER WUPIE FFA4 FFA5 FFA2 FFA3 CAN errors receive CAN2RIER CSCIE OVRIE CAN2RIER RXFIE FFA1 transmit CAN2TIER TXEIE2 TXEIEO FF9E FF9F FF9C FF9D CAN3 wake up CANS errors WUPIE TXEIE2 TXEIEO FF9A FF9B CANS receive RXFIE FF98 FF99 CANG transmit TXEIE2 TXEIEO FF96 FF97 wake up CANARIER WUPIE FF94 FF95 CANA errors CSCIE OVRIE FF92 FF93 CAN4 receive RXFIE FF90 FF91 CANA transmit CANATIER TXEIE2 TXEIEO FF8F Port P Interrupt PTPIF PTPIE FF8C FF8D FF80 to FF8B PWM Emergency Shutdown PWMSDN PWMIE Reserved 5 3 Effects of Reset When a reset occurs MCU registers and control bits are changed to known start up states Refer to the respective module Block User Guides for register reset states 5 3 1 pins Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A B E and K out of reset Refer to the PIM Block User Guide for reset configurations of all peripheral module ports 78 44 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguetem lieaevice User Guide vo2 15 NOTE For devices assembled 80 QFP packages all non bonded o
39. Loop The oscillator provides the reference clock for the PLL The PLL s Voltage Controlled Oscillator is also the system clock source in self clock mode A 5 3 1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics VDDPLL fosc 1 fret refdv 1 Detector femp Loop Divider Figure A 2 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for f and iy from Table 16 The VCO Gain at the desired VCO output frequency is approximated by f pu Tuo K 1V The phase detector relationship is given by lich ich 15 the current in tracking mode 109 M MOTOROLA For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc The loop bandwidth should be chosen to fulfill the Gardner s stability criteria by at least a factor of 10 typical values are 50 G 0 9 ensures a good transient response 2 6 fier 1 fref And finally the frequency relationship is defined as fvco ref 2 1 With the above inputs the resistance can be calculated as 2 iz COE o The capacitance C can now be calculated as 2 2 0 516 Qm o EOE S nio Ri The capacitance C should be chosen in the range of 20 C C
40. Read TAAS IBB 0 SRW up Write 34 M MOTOROLA For More Information On This Product Go to www freescale com 00E0 00E7 Address 00E4 00E5 00E6 00E7 Name IBDR Reserved Reserved Reserved 00E8 00EF Address 00E8 00E9 00EA 00EB 00EC 00ED 00EE 00EF Name DLCBCR1 DLCBSVR DLCBCR2 DLCBDR DLCBARD DLCBRSR DLCSCR DLCBSTAT 00F0 00F7 Address 0070 0021 00 2 00F3 00F4 00F5 00F6 00F7 M MOTOROLA Name SPI1CR2 SPI1BR SPI1SR Reserved SPHDR Reserved Reserved Freescale Semiconguetemolnesevice User Guide 02 15 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Inter IC Bus Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 06 05 D4 D3 D2 D1 DO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BDLC Bytelevel Data Link Controller J1850 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IMSG CLKS 0 IE WCM 0
41. The device contains an internal voltage regulator to generate the logic PLL supply out of the I O supply The absolute maximum ratings apply when the device is powered from an external source 3 All digital I O pins are internally clamped to Vssx and Vppx and Vppr Vssa and 4 Those pins are internally clamped to Vgsp and 5 This pin is clamped low to Vssp but not clamped high This pin must be tied low in applications A 1 6 ESD Protection and Latch up Immunity All ESD testing is in conformity with CDF AEC Q100 Stress test qualification for Automotive Grade Integrated Circuits During the device qualification ESD stresses were performed for the Human Body Model HBM the Machine Model MM and the Charge Device Model A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature unless specified otherwise in the device specification Table A 2 ESD and Latch up Test Conditions Model Description Symbol Value Unit Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF Puman Rody Number of Pulse per pin positive 3 negative 3 Series Resistance R1 0 Ohm Storage Capacitance C 200 pF Machine Number of Pulse per pin positive 3 negative 3 Mi
42. exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 3 output It can be configured as slave select pin SS of the Serial Peripheral Interface 1 SPI1 2 3 47 PP2 KWP2 PWM2 SCK1 Port P I O Pin 2 PP2 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 2 output It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 5 2 3 48 PP1 KWP1 PWM1 MOSI Port P I O Pin 1 is general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 1 output It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 1 SPI1 2 3 49 KWPO PWMO MISO1 Port P I O Pin 0 PPO is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 0 output It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 1 SPI1 2 3 50 PS7 550 Port I O Pin 7 PS6 is a general purpose input or output pin It can be configured as the sla
43. of the secured part Everything will appear the same as if the part was not secured with the exception of BDM operation The BDM operation will be blocked 4 3 2 2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller This is accomplished by resetting directly into expanded mode The internal FLASH and EEPROM will be disabled BDM operations will be blocked 74 44 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconduetosrp 6 device User Guide V02 15 4 3 3 Unsecuring the Microcontroller In order to unsecure the microcontroller the internal FLASH and EEPROM must be erased This can be done through an external program in expanded mode Once the user has erased the FLASH and EEPROM the part can be reset into special single chip mode This invokes a program that verifies the erasure of the internal FLASH and EEPROM Once this program completes the user can erase and program the FLASH security bits to the unsecured state This is generally done through the BDM but the user could also change to expanded mode by writing the mode bits through the BDM and jumping to an external program again through BDM commands Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state the part will be secured again 4 4 Low Power Modes The microcontroller features three main low power modes Consult th
44. process variations Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted values shown in the typical column are within this category Those parameters are derived mainly from simulations A 1 2 Power Supply The MC9S12DP256B utilizes several pins to supply power to the ports A D converter oscillator and PLL as well as the digital core The VDDA VSSA pair supplies the A D converter and the resistor ladder of the internal voltage regulator MOTOROLA 87 For More Information On This Product to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc The VDDX VSSX VDDR and VSSR pairs supply the I O pins VDDR supplies also the internal voltage regulator VDDI 551 VDD2 and VSS2 are the supply pins for the digital logic VDDPLL VSSPLL supply the oscillator and the PLL 551 and VSS2 are internally connected by metal VDDX VDDR as well as VSSA VSSX VSSR are connected by anti parallel diodes for ESD protection NOTE the following context VDDS is used for either VDDA VDDR VDDX 555 is used for either VSSA VSSR and VSSX unless otherwise noted 205 denotes the sum of the currents flowing into VDDX and pins VDD is used for VDDI VDD2 and VDDPLL VSS is used for VSS1 VSS2 and VSSPLL IDD is used for the sum of the currents flowing into VDDI
45. scale full range results VssA lt lt Vin lt lt Vppa This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to If the input level goes outside of this range it will effectively be clipped Table A 8 ATD Operating Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating Symbol Min Typ Max Unit Reference Potential 1 Low Vssa VppA 2 V High VppA 2 VpDA V 2 Differential Reference Voltage Vni Vn 4 50 5 00 5 25 V 3 ATD Clock Frequency ATDCLK 0 5 2 0 MHz ATD 10 Bit Conversion Period 4 D Clock Cycles 10 14 28 Cycles Conv Time at 2 0MHz ATD Clock fATDCLK Tconv1 0 7 14 us ATD 8 Bit Conversion Period 5 Clock Cycles Conv Time at 2 0MHz ATD Clock farpcik 6 D Recovery Time VppA 5 0 Volts 7 Reference Supply current 2 ATD blocks on 8 Reference Supply current 1 ATD block on NOTES 1 Full accuracy is not guaranteed when differential voltage is less than 4 50V 2 The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks A 2 2 Factors influencing accuracy Three factors source resistance source capacitance and current injection have an influence on the accuracy of the ATD 2 2 1 Source Resistance Due to the in
46. underflow FFDC FFDD Pulse accumulator A overflow I Bit PACTL PAOVI DC FFDA FFDB Pulse accumulator input edge I Bit PACTL PAI DA FFD8 FFD9 SPIO SPIE SPTIE D8 SCOCR2 310 TIE TCIE RIE ILIE SC1CR2 SEEDS SPEDS Sel TIE TCIE RIE ILIE FFD2 FFD3 ATDO ATDOCTL2 ASCIE FFDO FFD1 ATD1 ATD1CTL2 ASCIE DO FFCE FFCF Port J I Bit PTJIF PTJIE CE FFCC FFCD Port H I Bit PTHIF PTHIE CC MCCTL MCZI CA For More Information On This Product Go to www freescale com 77 MC9S12DP256B Device User dhkeeseale Semiconductor Inc FFC8 FFC9 Pulse Accumulator B Overflow I Bit PBCTL PBOVI C8 FFC6 FFC7 CRG PLL lock CRGINT LOCKIE FFC4 FFC5 CRG Self Clock Mode CRGINT SCMIE FFC2 FFC3 BDLC DLCBCR IE FFCO FFC1 Bus IBCR IBIE FFBE FFBF SPI1 SP1CR1 SPIE SPTIE FFBC FFBD SPI2 SP2CR1 SPIE SPTIE FFBA FFBB EEPROM EECTL CCIE CBEIE FFB8 FFB9 FLASH FCTL CCIE CBEIE FFB6 FFB7 FFB4 FFB5 CANO wake up CANO errors CANORIER WUPIE CANORIER CSCIE OVRIE FFB2 FFB3 CANO receive CANORIER RXFIE FFBO FFB1 FFAE FFAF CANO transmit CAN1 wake up CANOTIER TXEIE2 TXEIEO CAN1RIER WUPIE FFAC FFAD errors CAN1RIER CSCIE OVRIE FFAA FFAB FFA8 FFA9 receive transmit CAN1RIER RXFIE TXEIE2 TXEIEO FFA6
47. w v a mV Figure A 1 ATD Accuracy Definitions NOTE Figure A 1 shows only definitions for specification values refer to Table A 10 100 MOTOROLA For More Information On This Product Go to www freescale com Freescale 9 2 User Guide V02 15 A 3 NVM Flash and EEPROM NOTE Unless otherwise noted the abbreviation NVM Non Volatile Memory is used for both Flash and EEPROM A 3 1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator A minimum oscillator frequency fyymosc is required for performing program or erase operations The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively The frequency of this clock must be set within the limits specified as The minimum program and erase times shown in Table A 11 are calculated for maximum fyypop and maximum fp The maximum times are calculated for minimum fyyyop and a fy of 2MHz A 3 1 1 Single Word Programming The programming time for single word programming is dependant on the bus frequenc
48. xxxF CANxRTSRL TE TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSRO Extended ID Read aos CANxTIDRO Write 1028 1027 1026 1025 1024 1023 1022 1021 Standard ID Read ID10 ID9 108 107 106 105 IDA 103 Write Extended ID Read ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 ID1 IDo RTR IDE O Write 40 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicongucteomolnesevice User Guide 02 15 Table 1 2 Detailed MSCAN Foreground Receive Transmit Buffer Layout Address xx12 xx13 xx14 xx1B xx1C xx1D xx1E xx1F 0180 Address 0180 0181 0182 0183 0184 0185 0186 0187 0188 0189 018A 018B 018C Name Extended ID CANxTIDR2 Standard ID Extended ID CANxTIDR3 Standard ID CANxTDSR7 CANxTDLR CONxTTBPR CANxTTSRH CANxTTSRL 01 BF Name CAN1CTLO CAN1CTL1 CAN1BTRO CAN1RFLG CAN1TFLG CAN1TIER CAN1TARQ CAN1TAAK CAN1TBSEL CAN1IDAC Reserved M MOTOROLA Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write
49. 0 Bit 7 6 5 4 3 2 1 Bit 0 Miscellaneous Peripherals Device User Guide Table 1 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 IDO MMC map 3 of 4 Core and Device User Guide Table 1 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 reg swO 0 5 1 eep_sw0 0 ram 5 2 sw1 ram swO rom sw swO 0 0 0 0 sw1 pag swO MEBI map 2 of 3 Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRQE IRQEN 0 0 0 0 0 2 25 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 001F 001F INT map 2 of 2 Core User Guide Address Read 001F HPRIO Wre PSEL7 PSEL6 PSELS PSEL4 PSEL3 PSEL2 mmm 0020 0027 Reserved Address Bit7 Bite Bts Bt4 2 Bit 0 Read 0 0 0 0 0 0 0 0 0020 Reserved Write Read 0 0 0 0 0 0 0 0 0021 Reserved Write RE EM Read 0 0 0 0 0 0 0 0 0022 Reserved Write SSS LE Se Read 0 0 0 0 0 0 0 0 0023 Reserved Write M Read
50. 0 0 0 0 0 0 0 0 0024 Reserved Write SE Read 0 0 0 0 0 0 0 0 0025 Reserved Write Read 0 0 0 0 0 0 0 0 0026 Reserved Write lt SSS SS Read 0 0 0 0 0 0 0 0 0027 Reserved Write 0 3 0028 002F BKP Core User Guide Address Bt7 Bite Bts 2 Bii Bit 0 0028 BKPCTO Pan BKEN BKFULL L_2 0 0029 BKOMBH BKOMBL BK1MBH BK1MBL BKORWE BKORW BK1RWE BKTRW 002A BKPOX BKOV5 BKOV4 002B 162 pirig 14 13 12 11 10 9 Bit 8 Write 002C BkPol 1889 6 5 4 3 2 1 Bit 0 Write 002D BKP1X BK1V5 BKiv4 BK1VO 002E 162 15 14 13 12 11 10 9 Bit 8 Write 002F Bkpip 16989 gi 6 5 4 3 2 1 Bit 0 Write 26 MOTOROLA For More Information On This Product Go to www freescale com Freescale 2 User Guide 02 15 0030 0031 MMC map 4 of 4 Core User Guide Address 0030 PPAGE PIX5 PIX4 PIX3 PIX2 PIX1 PIXO 0031 Reserved 0032 0033 MEBI map 3 of 3 Core User Guide Address Name Bt7 Bt5 2 Bit Bit 0 0032 198
51. 0 wuPM LSLPAK INITAK 0282 e SJWi SJWO 5 BRP4 BRP3 1 BRPO 0283 jer SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0284 CANA4RFLG jun wupiF csc ESTAN RSTATO 5 1 TSTATO oyRIF RXF 0285 CAN4RIER e WUPIE CSCIE RSTATE1 RSTATEO TSTATE1 TSTATEO OVRIE RXFIE 0286 CAN4TFLG tt D 2 0 2 1 TXEO 0287 TXEIE2 TXEIE1 TXEIEO 0288 2 ABTRQ1 2 ABTAK1 ABTAK 00286 Write 028A CANATBSEL tt t 2 0 TX2 TX1 TXO 028B 0 i DANO TE TO Read 0 0 0 0 0 0 0 0 028C Reserved Write Read 0 0 0 0 0 0 0 0 028D Reserved Write SSS Read RXERR7 RXERR6 5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR 028E CANARXERR Read TXERR7 6 TXERR4 TXERR3 TXERR2 1 TXERR 0386 D DEL EE Write Read 0290 CANAIDARO 6 5 2 ACI ACO Read 0291 AC6 5 2 ACI ACO Read 0292 CANAIDAR2 00 AC6 5 4 2 1 Read 0293 CANAIDARS AC6 5 2 ACI ACO 0294 CAN4IDMRO iun AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO 0295 CAN4IDMR1 e AM7 AM6 AM5 A
52. 2DP256B MC9S 12DT256 MC9S 12DJ256 9 1200256 is available in a 112 pin low profile quad flat pack LQFP and MC9S12DJ256 is also available in a 80 pin quad flat pack Most pins perform two or more functions as described in the Signal Descriptions Figure 2 1 and Figure 2 3 show the pin assignments M MOTOROLA 53 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc 54 SS1 PWM3 KWP3 PP3 SCK1 PWM2 KWP2 PP2 MOSI1 PWM1 KWP1 PP1 MISO1 PWMO KWPO PPO XADDR17 PK3 XADDR16 PK2 XADDR15 PK1 XADDR14 PKO IOC2 PT2 10C3 PT3 VDD1 VSS1 5 5 IOC6 PT6 IOC7 PT7 XADDR19 PK5 XADDR18 PK4 KWJ1 PJ1 KWJ0 PJ0 MODC TAGHI BKGD ADDRO DATAO PBO ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4 96 PS7 SS0 00 i PMS TXCAN2 TXCANO TXCANA4 SCKO 95 I PS6 SCKO 99 PU6 KWJ6 RXCAN4 SDA 98 PJ7 KWJ7 TXCANA SCL 97 88 1 PM6 RXCAN3 RXCAN4 87 7 94 PS5 MOSIO 93 54 500 92 2 PS3 TXD1 91 2 PS2 RXD1 90 3 PS1 TXDO 89 3 PSO RXDO qum uu um qua am qum uem que MC9S12DP256B MC9S12DT256 95120 256 95120 256 dU ES CES en c t 09 03 09 03 OD 603 290 wo ite E I TL T Lb LE LH LH C3 Ld qj LL nj mE mE 0 WOW OLD QD LL
53. 3 2 1 Bit 0 Read 0056 hi Bit15 14 13 12 11 10 9 Bit 8 Read 0057 yngl BU 6 5 4 3 2 1 Bit 0 Read 0058 TC4 hi BiL15 14 13 12 11 10 9 Bit 8 28 44 MOTOROLA For More Information On This Product Go to www freescale com 0040 007F Address 0059 005A 005B 005C 005D 005E 005F 0060 0061 0062 0063 0064 0065 0066 0067 0068 0069 006A 006B 006C 006D 006E 006F 0070 0071 M MOTOROLA Name TC4 lo TC5 hi TC5 lo TC6 hi TC6 lo TC7 hi TC7 lo PACTL PAFLG PACNG hi PACN lo hi PACNO lo MCCTL MCFLG ICPAR DLYCT ICOVW ICSYS Reserved TIMTST Test Only Reserved Reserved PBCTL PBFLG Freescale Semicongucteomolnesevice User Guide 02 15 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write ECT Enhanced Capture Timer 16 Bit 8 Channels For More Information On This Product Go to www freescale com Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit
54. 4 6 5 4 3 2 1 Bit 0 Write 0033 89 6 5 4 3 2 1 Bit 0 Write 0034 003F CRG Clock and Reset Generator Address Name Bt7 Bt5 2 Biti Bit 0 0034 SYNR a 0 0 SYN5 SYN4 SYN3 SYN2 SYN SYNO 0035 REFDV e D 0 0 0 REFDV3 REFDV2 REFDV1 REFDVO CTFLG TOUT7 TOUT6 TOUTS TOUT4 TOUT3 TOUT TOUTI TOUTO TESTONLY Write 0037 CRGFLG PHOF DIS 0038 CRGINT in BEES HM ERES UO QT 0039 CLKSEL iin PLLSEL PSTP SYSWAI PLLWAI CWAI RTIWAI COPWAI Read 0 003A Wie CME PLLON AUTO PRE SCME Read 0 003B RTICTL RTR6 RTRS RTR4 RTR3 RTR2 RTRO 008C dnm wcoP 00 CRI CRO FORBYP Read 0 0 0 0 003D RTIBYP COPBYP PLLBYP TESTONLY Write CTCTL Read TCTL7 TCTL6 TCTL5 TCTL4 TCLT3 TCTL2 TCTL1 TCTLO 0098 rESTONLY Write Read 0 0 0 0 0 0 0 0 SOUSP Write 6 5 4 3 2 1 Bit 0 M MOTOROLA For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc 0040 007F ECT Enhanced Capture Timer 16 Bit 8 Channels Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit i Bit 0 00
55. 40 TIOS in IOS7 1056 1055 1054 1053 1052 1081 1050 Read 0 0 0 0 0 0 0 0 80041 CFORC Write 6 5 FOC2 Foci FOCO 0042 OC7M e OC7M7 OC7M6 7 5 OC7M4 OC7M3 7 2 OC7M1 OC7MO 0043 OC7D i OC7D7 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 Read 15 14 13 12 11 10 9 Bit 8 0044 TONT h Read 6 5 4 3 2 1 Bit 0 40045 TONT o m 0046 TSCR1 un TEN TSFRZ TFFCA 00 0047 TTOV jc TOV7 Tove tovs TOV Read 0048 OL7 ome OL6 OMS 015 OM4 OL4 Read 0049 TCTL2 OL3 OM2 OL2 OM1 OL1 OMO OLO 004A TCTL3 2 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 004B TCTL4 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDGOB EDGOA 004C TIE E 7 C11 Col 004D TSCR2 e 0 0 PR1 PRO Read 004E TFLG1 CF C6F C5F 2 1 004 Write Read 0050 TCO h Bit15 14 13 12 11 10 9 Bit 8 Read 0051 TCO lo was Bit 6 5 4 3 2 1 Bit 0 Read 0052 TCi h Bit15 14 13 12 11 10 9 Bit 8 Read 0053 1 BU 6 5 4 3 2 1 Bit 0 i Read 0054 TC2 hi Bit 15 14 13 12 11 10 9 Bit 8 Read 0055 TC2 o Bit 6 5 4
56. 6 A 7 A 7 1 A 7 2 A 8 A 8 1 Freescale Semicondeetai2batpevice User Guide 02 15 Operating eei 91 Power Dissipation and Thermal Characteristics 91 I O Characteristics TTC 93 Supply C rrentS cm 95 ATD Characteristics dr RU Ep dE ded dri IE pq at digi ih 97 ATD Operating Characteristics 97 Factors influencing 97 nap edo Seg Sd eR EES CSO aw 99 NVM Flash EEPROM ee er ke hot tle dint ee Motes Mo eh e ps 101 NVM E Satis es 101 NVM Reliability uide ROC 103 Voltage aay tee core soe dro Rheno CET P oe eee eod suas B Erud rape 105 Oscillator ang PEL 125242 CR EO cR d aca 107 lt lt e bias e ate eee EDIT LIUM LL EE 107 erri TELE 108 Phase Locked LOO saecu eis ias ee amc PNEU WI do hs 109 MSGAN emeret e eso trio oA side 113 EPIS eiua YR E INS Ea ida d a 115 Master Mode 115 Slave MOUS sod tx 117 External Bus NU RE
57. 7 TXCAN3 7 64 PM6 RXCAN4 Port M I O Pin 6 64 PM5 2 TXCANO SCK0 Port M I O Pin 5 64 RXCAN2 RXCAN4 MOSIO Port I O Pin 4 64 TXCAN1 550 Port M I O 65 2 1 MISO0 M 2 65 1 TXB Port Pin 1 65 RXB Port N O Pin 0 65 PP7 KWP7 PWM7 SCK2 Port P I O Pin 7 65 PP6 KWP6 PWM6 552 Port P 6 65 5 PWM5 MOSI2 Port 5 65 KWP4 PWM4 MISO2 Port P I O Pin 4 66 PP3 KWP3 PWM3 SS1 Port 1 66 PP2 KWP2 PWM2 SCK1 Port 2 66 PP1 KWP1 PWM1 MOSI1 Port P I O Pin 1 66 KWPO MISO1 Port P 0 66 577550 rers irer 66 PS6 SOKO PiN
58. 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 PAMOD PEDGE 1 CLKO PAOVI PAIF Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 MCZI MODMC RDMCL m m MCEN MCPRO em 0 0 0 POLF3 POLF2 POLF1 POLFO 2 PAOEN 2 DLY1 DLYO NOVW7 NOVW6 NOVW5 Novw4 NOVW3 NOVW2 NOVW1 NOVWO SH37 SH26 5 15 SH04 TFMOD PACMX BUFEN LATQ 0 0 0 0 0 0 0 PBEN 9 9 0 0 0 0 0 0 BEONE 0 29 MC9S12DP256B Device User dhkeeseale Semiconductor Inc 0040 007F ECT Enhanced Capture Timer 16 Bit 8 Channels Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0072 PASH Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0073 PA2H Bit 7 6 5 4 3 2 1 Bit 0 Write Read Bit7 6 5 4 3 2 1 Bit 0 0074 PA1H Wine 0075 PAOH poan Bit 7 6 5 4 3 2 1 Bit 0 Write 0076 hi Bit 15 14 13 12 11 10 9 Bit 8 Read 0077 MCCNT 0 Bit 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 00
59. 7 Bi 0133 ATDIDRIL npag it it6 0 0 0 0 0 0 Write Read 14 1 12 11 1 Bit8 Write Bit7 Bi 0135 ATD1DR2L npag it it6 0 0 0 0 0 0 Write Read 14 1 12 11 1 Bit8 E a Write Read Bit Bi 0 60192 esl Write Read 14 1 12 11 1 Bit8 i sd Write 38 M For More Information On This Product Go to www freescale com 0120 013F Address 0139 013A 013B 013C 013D 013E 013F Name ATD1DR4L ATD1DR5H ATD1DR5L ATD1DR6H ATD1DR6L ATD1DR7H ATD1DR7L 0140 017F Address 0140 0141 0142 0143 0144 0145 0146 0147 0148 0149 014A 014B 014C 014D 014E 014F Name CANOCTLO CANOCTL1 CANOBTRO CANORFLG CANORIER CANOTFLG CANOTIER CANOTARQ CANOTAAK CANOTBSEL CANOIDAC Reserved Reserved CANORXERR CANOTXERR 44 MOTOROLA Freescale Semicongusetemolnesevice User Guide 02 15 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write ATD1 Analog to Digital Converter 10 Bit 8 Chann
60. 78 TCOH h Read Bit7 6 5 4 3 2 1 Bit 0 0079 Read 15 14 13 12 11 10 9 Bit 8 007A TCIH h Read Bit7 6 5 4 3 2 1 Bit 0 0078 TCIH o Read Bit 15 14 13 12 11 10 9 Bit 8 5007 TC2H h Read Bit7 6 5 4 3 2 1 Bit 0 0070 TC2H o Read Bit 15 14 13 12 11 10 9 Bit 8 007E Read Bit7 6 5 4 3 2 1 Bit 0 007F 0 0080 009F ATDO Analog to Digital Converter 10 Bit 8 Channel Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0080 ArDocrio 1884 0 0 9 0 0 Write 0081 16844 0 0 2 0 0 0 0 Write 0082 ATDOCTL2 ida ADPU AFFC ETRIGP ETRIG LASOE Read 0 0083 ATDOCTL3 qr S8C S4C S2C S1C FIFO FRZi FRZO 0084 4 ies SRES8 1 SMPO PRS4 PRS3 PRS2 PRS1 PRSO Read 0 0085 ATDOCTLS Wire DJM DSGN SCAN MULT 0 ETORF FIFOR 0 CCO Write Read 0 0 0 0 0 0 0 0 008B Reserved Write 30 M MOTOROLA For More Information On This Product Go to www freescale com 0080 Address 0088 0089 008A 008B 008C 008D 008E 008F 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F M MOTOROLA 009F Name ATDOTESTO ATDOTEST1 Reserved ATDOSTAT1 Reserved ATDODIEN Reserved PORTADO ATDODROH ATDOD
61. 9S12DP256B Device User dhkeese ale Semiconductor Inc Table A 19 SPI Slave Mode Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted CLOAD 200pF on all outputs Me Unt p e 5 Period tgck 14 2048 tous 2 Enable Lead Time lcyc 3 Enable Lag Time lcyc 4 Clock SCK High or Low Time twsck 5 Data Setup Time Inputs Data Hold Time Inputs III BUE EIE EINE i Slave MISO Disable Time ldis Data Valid after SCK Edge ty 25 ns 10 Data Hold Time Outputs tho ns D Rise Time Inputs and Outputs tr 25 ns 12 Time Inputs and Outputs tf 25 ns 1 18 M MOTOROLA For More Information On This Product Go to www freescale com Freescale 9 gt User Guide V02 15 A 8 External Bus Timing A timing diagram of the external multiplexed bus is illustrated in Figure A 9 with the actual timing values shown on table Table A 20 AII major bus signals are included in the diagram While both a data write and data read cycle are shown only one or the other would occur on a particular bus cycle A 8 1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions The timing parameters shown assume a balanced load across all outputs M MOTOROLA 119 For More Information On This Product Go to www freescale com MC
62. 9S12DP256B Device User dhkeeseale Semiconductor Inc 1 2 gt lt 3 lt 4 ECLK 4 Addr Data read PA PB Addr Data write PA PB Non Multiplexed Addresses PK5 0 ECS PK7 R W PE2 Figure A 9 General External Bus Timing 120 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicondeetam2batpevice User Guide 02 15 Table A 20 Expanded Bus Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted Cj 50pF Rating Symbol Min Typ Max Unit P Frequency of operation E clock fo 0 25 0 MHz GT cain Pulse width E low 4 Pulse width E high 5 Address delay time 6 Address valid time to E rise PWg 7 Muxed address hold time ER Address hold to data valid 10 Read data setup time 11 Read data hold time 12 Write data delay time 14 Write data setup time PWgp tppw ipsw 15 Address access time tcyc tap tpsg tacca pr Non multiplexed address delay time Non muxed address valid to E rise PWg tNAp Non multiplexed address hold time Chip select delay time Chip select access time teye tesp tosr Chip select hold time Read write hold time Low strobe delay time Low strobe valid time to E rise PWg sp L
63. A 7 Supply Current Characteristics 96 Table A 8 Operating Characteristics 97 Table A 9 ATD Electrical Characteristics s px uu Anse 98 Table 10 Conversion Performance 99 Table 11 NVM Timing 102 Table A 12 NVM Reliability 5 103 Table A 13 Voltage Regulator Recommended Load Capacitances 105 Table A 14 Startup 107 Table A 15 Oscillator Characteristics 0 04 voce ee ed sean peewee 108 Table 16 PLL Characteristics uar Sead dex Ge ad alk ees 112 Table A 17 MSCAN Wake up Pulse 5 113 Table A 18 SPI Master Mode Timing 116 44 MOTOROLA 13 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc Table 19 SPI Slave Mode Timing 118 Table A 20 Expanded Bus Timing Characteristics 121 14 M MOTOROLA For More Information On This Product Go to www freesc
64. C Operating Junction Temperature Range Tj 40 100 Operating Ambient Temperature Range 2 40 27 85 C MC9S12DP256BV Operating Junction Temperature Range 40 120 Operating Ambient Temperature Range 2 40 27 105 C MC9S12DP256BM Operating Junction Temperature Range 40 140 Operating Ambient Temperature Range 2 40 27 125 C NOTES 1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source 2 Please refer to Section A 1 8 Power Dissipation and Thermal Characteristics for more details about the rela tion between ambient temperature T4 and device junction temperature A 1 8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related The user must assure that the maximum operating junction temperature is not exceeded The average chip junction temperature Ty in can be obtained from M MOTOROLA 91 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc Tj Junction Temperature T Ambient Temperature P D Total Chip Power Dissipation W Oja Package Thermal Resistance C W The total power dissipation can be calcula
65. DDR Disabled Port H I O Interrupt MOSI of SPI2 VDDR Disabled Port H I O Interrupt MISO of SPI2 VDDR Disabled Port I O Interrupt SS of SPI1 PH2 KWH2 VDDR Disabled Port H I O Interrupt SCK of SPI1 PH1 KWH1 VDDR Disabled Port H I O Interrupt MOSI of SPI PHO KWHO VDDR Disabled Port H I O Interrupt MISO of SPI PERJ Port J I O Interrupt TX of PJ7 KWJ7 SCL TXCANO VDDX U P Int t of PJ6 KWJ6 RXCAN4 RXCANO VDDX DH CU PITCH SDA of IIC RX of CANO 1 0 KWUJ 1 0 VDDX Port J I O Interrupts Port I O Emulation Chip Select PK7 ECS UP ROM On Enable PK 5 0 Up Port I O Extended Addresses Port M I O TX of CAN3 TX of 7 TXCAN3 TXCAN4 Disabled CAN4 Port of of PM6 RXCAN3 RXCAN4 Disabled CAN4 PM5 TXCAN2 TXCANO TXCAN4 Disabled Pot M VO CANE CANG 58900 of SPIO PERM Port M I O RX CAN2 CANO 4 RXCAN2 RXCANO MOSIO VDDX Disabled 84994 MOSI of SPIO DUM PERM Port M I O TX of CANO SS TXCAN1 TXCANO SS0 VDDX PPSM Disabled of SPIO Port M I O CANO MISO of SPIO TXCANO RXCANO TXB VDDX VDDX Disabled Disabled Port M I O TX of CANO TX of BDLC Port M I O RX of RX of BDLC 58 KWP7 VDDX VDDX Disabled For More Information On This Prod
66. DDRT1 DDRTO 0243 RDRT ii RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRTO 0244 PERT iis PERT7 PERT6 PERT5 PERT2 PERTO 0245 PPST e PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 1 PPSTO Read 0 0 0 0 0 0 0 0 0246 Reserved Write p Read 0 0 0 0 0 0 0 0 0247 Reserved Write e 0248 PTS 2 PTS7 56 55 PTS4 PTS3 52 81 50 Read PTIS7 PTISe 5 PTIS4 PTIS3 PTIS2 PTIS1 50 oe ae ead S S6 S5 S S3 S S 50 Write 024A DDRS e DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRSO 024B RDRS i RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRSO 024C PERS is PERS7 PERS6 PERSS PERS4 PERS3 PERS2 PERS1 PERSO 024D PPSS e PPSS7 556 555 PPSS4 PPSS3 552 551 550 024E WOMS 1 WOMS7 WOMS6 womss WOMS4 woms3 WOMS WOMS1 WOMSO Read 0 0 0 0 0 0 0 0 024F Reserved Write SSS eee I 0250 PTM 2 PTM7 6 5 4 PTM2 1 PTMO Read PTIM7 6 5 PTIM4 2 PTIMO 0251 PTIM pi sa o Write 0252 DDRM jan DDRM7 DDRM7 DDRMS DDRM4 DDRM3 DDRM2 DDRM1 DDRMO 0253 RDRM e RDRM7 RDRM6 5 RDRM4 RDRM3 RDRM2 1 RDRMO 0254 PERM iim PERM7 6 5 PERM2
67. ENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC C 215 245 BODY AT THE BOTTOM OF THE PARTING LINE D 022 038 4 DATUMS A B D TO BE E 2 00 240 DETERMINED AT DATUM PLANE H Elco loa 5 DIMENSIONS S AND V TO BE DETERMINED 5 DATUM 6 DIMENSIONS A AND B DO NOT INCLUDE E H 0 25 PLANE LH MOLD PROTRUSION ALLOWABLE J 918 023 PROTRUSION IS 0 25 PER SIDE DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH K 065 0 95 AND ARE DETERMINED AT DATUM PLANE H L 12 35 REF 7 DIMENSION D DOES NOT INCLUDE DAMBAR M 109 PROTRUSION ALLOWABLE DAMBAR N 17 PROTRUSION SHALL 0 08 TOTAL IN 013 0 EXCESS OF THE D DIMENSION A MAXIMUM P 0 325 BSC Q MATERIAL CONDITION DAMBAR CANNOT a oe 75 BE LOCATED ON THE LOWER RADIUS OR Rl vns om THE FOOT S 1695 1745 T 013 m DETAIL C Wl sl 1695 1745 W 035 045 X 1 6 REF Figure B 2 80 pin QFP Mechanical Dimensions case no 841B M MOTOROLA 125 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 126 M MOTOROLA For More Information On This Product Go to www freescale com Freescale 2 User Guide 02 15 User Guide End Sheet M MOTOROLA 127 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc FINAL PAGE OF 128 PAGES 128 M MOTOROLA For
68. ETERMINED AT EATING PLANE DATUM T MENSIONS A AND B DO NOT INCLUDE OLD PROTRUSION ALLOWABLE ROTRUSION IS 0 25 PER SIDE DIMENSIONS AND B INCLUDE MOLD MISMATCH MENSION D DOES NOT INCLUDE DAMBAR ROTRUSION ALLOWABLE DAMBAR ROTRUSION SHALL NOT CAUSE THE D MENSION TO EXCEED 0 46 2 gt 3 4 Q OOUCOAU 5 UVVOYFrVESV SEATING PLANE 0 25 22 000 BSC GAGE PLANE 11 000 BS 22 000BSC 0 250 LA LB B1 LE L6 LK LP LS LS1 Lz 61 82 11 VIEW AB Figure B 1 112 pin LQFP mechanical dimensions case 987 124 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicongusctemolneaevice User Guide 02 15 B 3 80 pin QFP package DETAIL A 0 20 OIDO 5 D DETAIL C 0 20 AB 9 DO SECTION B B BIB DATUM VIEW ROTATED 90 mt SEATING 5010 PLANE EE NOTES MILLIMETERS DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 MIN 2 CONTROLLING DIMENSION MILLIMETER A 1390 14 10 3 DATUM PLANE H IS LOCATED AT BOTTOM OF 1290 1410 LEAD AND IS COINCID
69. IDMR7 e AM7 6 5 4 2 AMI AMO 01A0 Read FOREGROUND RECEIVE BUFFER see Table 1 2 goiAF Write 01B0 cANITXEG 19 FOREGROUND TRANSMIT BUFFER see Table 1 2 01BF Write 42 M MOTOROLA For More Information On This Product Go to www freescale com 01C0 Address 01C0 01C1 01C2 01C3 01C4 01C5 01C6 01C7 01C8 01C9 01CA 01CB 01CC 01CD 01CE 01CF 0100 0101 0102 0103 0104 0105 0106 0107 0108 MOTOROLA 01FF Name CAN2CTLO CAN2CTL1 CAN2BTRO CAN2BTR1 CAN2RFLG CAN2RIER CAN2TFLG CAN2TIER CAN2TARQ CAN2TAAK CAN2TBSEL CAN2IDAC Reserved Reserved CAN2RXERR CAN2TXERR CAN2IDARO CAN2IDAR1 CAN2IDAR2 CAN2IDAR3 CAN2IDMRO CAN2IDMR1 CAN2IDMR2 CAN2IDMR3 CANZ2IDAR4 Freescale Semicongucteomlnesevice User Guide 02 15 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write CAN2 Motorola Scalable CAN MSCAN Bit 7 RXFRM CANE SJW1 SAMP WUPIF WUPIE 0 0 0 RXERR7 TXERR7 AC7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 AC7 Bit 6 RXACT CLKSRC SJWO TSEG22
70. M4 AM3 AM2 AM1 AMO 0296 CAN4IDMR2 E 7 6 5 4 2 AMI AMO 0297 CAN4IDMR3 jr AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO Read 0298 CANAIDARA 6 5 2 ACI ACO 48 M For More Information On This Product Go to www freescale com Freescale Semicongucteomlnesevice User Guide 02 15 0280 02BF CANA Motorola Scalable CAN MSCAN Address Name Bt7 Bt6 Bt5 2 Biti Bit 0 0299 CAN4IDARS 7 AC6 5 4 2 1 029A CANAIDAR6 e AC7 AC6 5 4 2 1 90298 7 i AC7 AC6 5 4 2 1 029C CANA4IDMR4 i AM7 6 5 4 2 AMI AMO 90290 CAN4IDMR5 6 AMS AM4 AM2 AMO 029E CAN4IDMR6 e 6 AMS 4 AM2 AMI AMO 029F CAN4IDMR7 2 AM7 6 5 4 2 AMI AMO 02A0 Read FOREGROUND RECEIVE BUFFER see Table 1 2 ogar CANARXFG Write 02B0 CANA4TXEQG 1939 FOREGROUND TRANSMIT BUFFER see Table 1 2 02BF Write 02 0 03FF Reserved space Address eee o o o o o o p 03FF 1 7 Part ID Assignments The part ID is located in two 8 bit registers PARTIDH and PARTIDL addresses 001A and 001B after reset The read
71. MODC bit at the rising edge of RESET 2 3 7 PAD15 AN15 ETRIG1 Port AD Input Pin of ATD1 15 is a general purpose input pin and analog input of the analog to digital converter It can act as an external trigger input for the ATDI 60 44 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicon actai2batpevice User Guide V02 15 2 3 8 PAD 14 08 AN 14 08 Port AD Input Pins of ATD1 PAD14 PADOS are general purpose input pins and analog inputs AN 6 0 of the analog to digital converter ATDI 2 3 9 PAD7 07 ETRIGO Port AD Input Pin of ATDO PAD7 is a general purpose input pin and analog input AN7 of the analog to digital converter ATDO It can act as an external trigger input for the ATDO 2 3 10 PAD 06 00 AN 06 00 Port AD Input Pins of ATDO PADO6 PADOO are general purpose input pins and analog inputs AN 6 0 of the analog to digital converter ATDO 2 3 11 PA 7 0 ADDR 15 8 DATA 15 8 Port A I O Pins 7 are general purpose input or output pins In MCU expanded modes of operation these pins are used for the multiplexed external address and data bus 2 3 12 PB 7 0 ADDR 7 0 DATA 7 0 Port Pins PB7 PBO are general purpose input or output pins In MCU expanded modes of operation these pins are used for the multiplexed external address and data bus 2 3 13 PE7 XCLKS Port E I O Pin 7
72. More Information On This Product Go to www freescale com
73. R W PE2 IRQ PE1 XIRQ PEO ECLK PE4 ADDRBS DATA5 PB5 ADDR6 DATA6 PB6 ADDR7 DATA7 PB7 XCLKS NOACC PE7 MODB IPIPE1 PE6 MODA IPIPEO PE5 LSTRB TAGLO PE3 VRH VDDA PADO7 ANO7 ETRIGO PADO06 AN06 5 PADO4 ANO4 PADOS ANOS PADO02 AN02 PADO1 ANO1 PADOO ANOO VSS2 VDD2 PA7 ADDR15 DATA15 PA6 ADDR14 DATA14 PAS ADDR13 DATA13 PA4 ADDR12 DATA12 PA3 ADDR11 DATA1 1 PA2 ADDR10 DATA10 PA1 ADDR9 DATA9 PAO ADDRB8 DATA8 Figure 2 3 Pin Assignments in 80 pin for MC9S12DJ256 2 2 Signal Properties Summary Table 2 1summarizes the pin functionality Signals shown in bold are not available in the 80 pin package 56 Table 2 1 Signal Properties For More Information On This Product Go to www freescale com M MOTOROLA Freescale Semicongucetemolnesevice User Guide 02 15 Pin Name Funct 1 Pin Name Pin Name 2 Funct 3 Internal Pull Pin Name Pin Name Power Resistor Funct 4 Funct 5 Suppl pply CTRL Reset State Description Oscillator Pins External Reset VREGEN Test Input Voltage Regulator Enable Input XFC PLL Loop Filter Background Debug Tag High Mode BKGD TAGHI 2 Input Port AD Input Analog Input AN7 PAD 15 AN1 7 ETRIG1 of ATD1 External Trigger Input of ATD1 Port AD Inputs Analog Inputs PAD 14 8 AN1 6 0 None AN 6 0 of ATD1 1 Port AD Inpu
74. ROL ATDODR1H ATDODR1L ATDODR2H ATDODR2L ATDODR3H ATDODR3L ATDODR4H ATDODR4L ATDODR5H ATDODR5L ATDODR6H ATDODR6L ATDODR7H ATDODR7L Freescale Semicongusetemlnesevice User Guide 02 15 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write ATDO Analog to Digital Converter 10 Bit 8 Channel For More Information On This Product Go to www freescale com Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC 0 0 0 0 0 0 0 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCFO 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit7 6 5 4 3 2 1 BIT O Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10
75. User dhkeese ale Semiconductor Inc 1 5 Device Memory Map Table 1 1 and Figure 1 2 show the device memory map of the MC9S12DP256B after reset Note that after reset the bottom 1k of the EEPROM 0000 03FF are hidden by the register space 22 Table 1 1 Device Memory Map Address Module Bytes 0000 0017 CORE Ports A B E Modes Inits Test 24 0018 0019 Reserved 2 001A 001B Device ID register PARTID 2 001C 001F CORE MEMSIZ IRQ HPRIO 4 0020 0027 Reserved 8 0028 002F CORE Background Debug Mode 8 0030 0033 CORE PPAGE Port K 4 0034 003F Clock and Reset Generator PLL RTI COP 12 0040 007F Enhanced Capture Timer 16 bit 8 channels 64 0080 009F Analog to Digital Converter 10 bit 8 channels ATDO 32 00A0 00C7 Pulse Width Modulator 8 bit 8 channels PWM 40 00C8 00CF Serial Communications Interface 0 SCIO 8 0000 0007 Serial Communications Interface 0 SCI1 8 00D8 00DF Serial Peripheral Interface SPIO 8 00E0 00E7 Inter IC Bus 8 00E8 00EF Byte Data Link Controller BDLC 8 00FO 00F7 Serial Peripheral Interface SP11 8 00F8 00FF Serial Peripheral Interface SP12 8 0100 010F Flash Control Register 16 0110 011B EEPROM Control Register 12 011C 011F Reserved 4 0120 013F Analog to Digital Converter 10 bit 8 channels ATD1 32 0140
76. V Code Notes An errata exists An errata exists An errata exists An errata exists conntact Sales office conntact Sales office conntact Sales office conntact Sales office 44 MOTOROLA For More Information On This Product Go to www freescale com 15 MC9S12DP256B Device User dhkeese ale Semiconductor Inc Table 0 3 shows the defects fixed on maskset 2K79X MC9S12DP256C Table 0 3 Defects fixed on Maskset 2K79X Defect Headline MUCts00510 SCI interrupt asserts only if odd number of interrupts active MUCts00604 Security in Normal Single Chip mode MUCts00603 Security in Normal Single Chip mode This document is part of the customer documentation A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block User Guides of the implemented modules In a effort to reduce redundancy all module specific information is located only in the respective Block User Guide If applicable special implementation details of the module are given in the block description sections of this document MC9S12 DP256C C FU fene Package Option Temperature Option Device Title gt Controller Family Temperature Options 40 to 85 40 to 105 40 to 125 V Package Options FU 800 PV 112 LQFP Figure 0 1 Order Part Number Example See Table 0 4 for names and versions of the referenced documents throughout the Device User Guide Table 0 4 D
77. WM5 MOSI2 PP7 KWP7 PWM7 SCK2 PM3 TXCAN1 TXCANO SSO VDDX VSSX PMO RXCANO PM1 TXCANO PS2 RXD1 PS1 TXDO PSO RXDO VSSA VRL MC9S12DG256 80 QFP VSSR VDDR TEST ECLK PE4 XIRQ PEO ADDR5 DATA5 PB5 ADDR6 DATA6 PB6 ADDR7 DATA7 PB7 MODB IPIPE1 PE6 XCLKS NOACC PE7 VRH VDDA PADO7 ANO7 ETRIGO 06 06 5 04 04 0 03 02 02 PADO1 ANO1 00 00 VSS2 VDD2 PA7 ADDR15 DATA15 PA6 ADDR14 DATA14 PA5 ADDR13 DATA13 PA4 ADDR12 DATA12 PA3 ADDR11 DATA11 PA2 ADDR10 DATA10 PA1 ADDR9 DATA9 PA0 ADDR8 DATA8 Figure 2 2 Pin Assignments in 80 pin QFP for MC9S12DG256 For More Information On This Product Go to www freescale com 55 MC9S12DP256B Device User dhkeeseale Semiconductor Inc SS1 PWM3 KWP3 PP3 SCK1 PWM2 KWP2 PP2 MOSI1 PWM1 KWP1 PP1 MISO1 PWMO KWPO PPO IOCO PTO 1 1 IOC2 PT2 IOCS PT3 MODC TAGHI BKGD ADDRO DATAO PBO ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4 goto PP4 KWP4 PWM4 MISO2 73 PM2 RXCAN1 RXCANO MISOO 72 5 PM3 TXCAN1 TXCANO SSO 71 ES PM4 RXCAN2 RXCANO RXCAN4 MOSIO PMS TXCAN2 TXCANO TXCAN4 SCKO PJe KWJe RXCANA SDA 79 PPSIKWPS PWMS MOSI2 78 PP7 KWP7 PWM7 SCK2 VDDX 7615 VSSX 754 PMO RXCANO RXB 74 3 PM1 TXCANO TXB 67 VREGEN MC9S12DJ256 80 QFP VSSR VDDR RESET
78. ad 0 0 0 0 0011 is reset expanded widerormarowmade EG 1 4 REG13 REG12 REG11 24 44 MOTOROLA For More Information On This Product Go to www freescale com 0010 0014 Address 0012 0013 0014 Name INITEE MISC MTSTO 0015 0016 Address 0015 0016 Name ITCR ITEST 0017 0017 Address 0017 Name MTST1 0018 001B Address 0018 0019 001A 001B Name Reserved Reserved PARTIDH PARTIDL 001C 001D Address 001C 001D Name MEMSIZO MEMSIZ1 001E 001E Address 001E 44 MOTOROLA Name INTCR Freescale Semiconguceteomolnesevice User Guide 02 15 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MMC map 1 of 4 Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EE15 EE14 EE13 EE12 EEON EXSTR1 EXSTRO ROMHM ROMON Bit 7 6 5 4 3 2 1 Bit 0 INT map 1 of 2 Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 WRINT ADR3 ADR2 ADRO INTE INTC INTA INT8 INT6 4 2 INTO MMC map 2 of 4 Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
79. ale com Preface Freescale 2 User Guide 02 15 The Device User Guide provides information about the MC9S12DP256B device made up of standard HCS12 blocks and the HCS12 processor core Table 0 1 and Table 0 2 show the availability of peripheral modules on the various derivatives For details about the compatibility within the MC9S12D Family refer also to engineering bulletin EB386 Table 0 1 Drivative Differences MC9S12D256B Generic device MC9S12DP256B MC9S12DT256B MC9S12DJ256B MC9S12DG256B MC9S12A256B of CANS 5 3 2 2 0 CANO V V V CAN2 V CANS3 V V V V V J1850 BDLC V V Package 112 LQFP 112 112 LQFP 80 QFP 112 LQFP 80 112 LQFP 80 Mask set 0AK79X 0 1 79 0 1 79 0 1 79 0 1 79 Temp Options C PV PV PV FU PV PV FU Code Notes An errata exists An errata exists An errata exists An errata exists An errata exists conntact Sales office conntact Sales office conntact Sales office conntact Sales office conntact Sales office Table 0 2 Derivative Differences 95120256 Tamea MC9St20P2560 of CANs 3 2 2 J1850 BDLC V Package 112 112 LQFP 80 112 LQFP 80 Mask set 2K79X 2K79X 2K79X Temp Options package PV PV PV FU P
80. and VDD2 A 1 3 Pins There are four groups of functional pins A 1 3 1 5V I O pins Those I O pins have a nominal level of 5V This class of pins is comprised of all port I O pins the analog inputs BKGD and the RESET pins The internal structure of all those pins is identical however some of the functionality may be disabled E g for the analog inputs the output drivers pull up and pull down resistors are disabled permanently A 1 3 2 Analog Reference This group is made up by the VRH and VRL pins A 1 3 3 Oscillator The pins XFC EXTAL XTAL dedicated to the oscillator have a nominal 2 5V level They are supplied by VDDPLL A 1 3 4 TEST This pin is used for production testing only A 1 3 5 VREGEN This pin is used to enable the on chip voltage regulator 88 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguctemlnesevice User Guide 02 15 A 1 4 Current Injection Power supply must maintain regulation within operating Vpps or range during instantaneous and operating maximum current conditions If positive injection current Vi gt Vpps is greater than Ipps the injection current may flow out of VDDS5 and could result in external power supply going out of regulation Ensure external VDD5 load will shunt current greater than maximum injection current This will be the greatest risk when the MCU is not consuming power e g if no system clock is present or if clock rat
81. at the rising edge of RESET This pin is shared with the instruction queue tracking signal IPIPEO This pin is an input with a pull down device which is only active when RESET is low 2 3 16 4 Port E I O Pin 4 is a general purpose input or output pin It can be configured to drive the internal bus clock ECLK ECLK can be used as a timing reference 2 3 17 LSTRB TAGLO Port E I O Pin PE3 is a general purpose input or output pin In MCU expanded modes of operation LSTRB can be used for the low byte strobe function to indicate the type of bus access and when instruction tagging is on TAGLO is used to tag the low half of the instruction word being read into the instruction queue 2 3 18 R W Port E I O Pin 2 PE2 is a general purpose input or output pin In MCU expanded modes of operations this pin drives the read write output signal for the external bus It indicates the direction of data on the external bus 2 3 19 PE1 IRQ Port E Input Pin 1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests This will wake up the MCU from STOP or WAIT mode 2 3 20 PEO XIRQ Port E Input Pin 0 PEO is a general purpose input pin and the non maskable interrupt request input that provides a means of applying asynchronous interrupt requests This will wake up the MCU from STOP or WAIT mode
82. ax Unit P Operating Frequency fous Csr Enable Lead Time lleag lsck Enable Lag Time Ec Data Setup Time Inputs Data Hold Time Inputs Data Valid after Enable Edge Data Hold Time Outputs Rise Time Inputs and Outputs Fall Time Inputs and Outputs NOTES 1 The numbers 7 8 in the column labeled Num are missing This has been done on purpose to be consistent between the Master and the Slave timing shown in Table A 19 116 44 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguctemolnesevice User Guide 02 15 A 7 2 Slave Mode Figure A 7 and Figure A 8 illustrate the slave mode timing Timing values are shown in Table A 19 SS INPUT SCK 0 INPUT SCK CPOL 1 INPUT gt lt 9 OUTPUT MSB OUT an M SLAVE LSB OUT INPUT MSB IN LSB IN Figure A 7 SPI Slave Timing 0 SS INPUT N D gt 3 2 2 gt ja 1 SCK CPOL 20 INPUT _ SCK 4 1 gt lt 12 CPOL 1 INPUT 9 lt 0 8 usos C 7 HC MOSI Figure A 8 SPI Slave Timing CPHA 1 M MOTOROLA 117 For More Information On This Product Go to www freescale com MC
83. commended PCB Layout 1121 85 Recommended PCB Layout for 80QFP 86 ATD Accuracy Definitions 100 Basic PLL functional diagram 109 Sears RR 111 Maximum bus clock jitter approximation 111 SPI Master Timing GPHA 0 115 SPIMaster Timing 5 1 vue RE eT 116 SPI Slave Timing CPHA 0 117 SPI Slave Timing CPHA 1 117 General External Bus Timings ceeded ed Moke Maa oad etek 120 112 pin LQFP mechanical dimensions case no 987 124 80 pin Mechanical Dimensions case no 841 125 11 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 12 M MOTOROLA For More Information On This Product Go to www freescale com Freescale 2 User Guide 02 15 List of Tables Table 0 1 Drivative Differences 95120256 15 Table 0 2 Derivative Differences 95120256 15 Table 0 4 Document 16 Table 0 3 Defects fixed Maskset 2 79
84. d Register Map The following tables show the detailed register map of the MC9S12DP256B 0000 000F MEBI map 1 of 3 Core User Guide Address Bt7 5 Bt2 Bii Bit 0 0000 PORTA 198 6 5 4 3 2 1 Bit 0 Write 0001 192 6 5 4 3 2 1 Bit 0 Write 0002 DDRA 1944 pi 6 5 4 3 2 1 Bit 0 Write 0003 1929 6 5 4 3 2 1 Bit 0 Write Read 0 0 0 0 0 0 0 0 0004 Reserved Write Read 0 0 0 0 0 0 0 0 0005 Reserved Write Read 0 0 0 0 0 0 0 0 0006 Reserved Write Ee EEE EE a a Read 0 0 0 0 0 0 0 0 0007 Reserved Write 0008 porte 192 gi 6 5 4 3 ae ae BITO Write 0009 19344 6 5 4 3 Write 000A PEAR NOACCE 0 4 LsTRE Rowe he 0 000B MODE MODB MODA 0 4 ms 10 EMK 000C PUCR PUPKE LLL pupee h2 O PUPBE PUPAE 000D RDRIV e S Rope LO O 000E ar Write Read 0 0 0 0 0 0 0 0 000F Reserved Write R a 0010 0014 MMC map 1 of 4 Core User Guide Address Bt7 5 Bt2 Bilt Bit 0 0010 INITRM dan RAM15 14 RAM13 RAM12 11 0 Re
85. digital I O lines with interrupt and wakeup capability five CAN 2 0 A B software compatible modules MSCAN12 and an Inter IC Bus The MC9S12DP256 has full 16 bit data paths throughout However the external bus can operate in an 8 bit narrow mode so single 8 bit wide memory can be interfaced for lower cost systems The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements 1 2 Features e HCS12 Core 16 bit HCS12 CPU i Upward compatible with M68HC11 instruction set ii Interrupt stacking and programmer s model identical to M68HC11 iii Instruction queue iv Enhanced indexed addressing Multiplexed External Bus Interface MMC Module Mapping Control INT Interrupt control Breakpoints BDM Background Debug Mode e CRG low current oscillator PLL reset clocks COP watchdog real time interrupt clock monitor e 8 bit and 4 bit ports with interrupt functionality Digital filtering Programmable rising or falling edge trigger Memory 256K Flash EEPROM 4K byte EEPROM 12K byte RAM M MOTOROLA 17 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc e Two 8 channel Analog to Digital Converters 10 bit resolution External conversion trigger capability Five IM bit per second CAN 2 0 A B software compatible modules Five receive and
86. e is very low which would reduce overall power consumption A 1 5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only A functional operation under or outside those maxima is not guaranteed Stress beyond those limits may affect the reliability or cause permanent damage of the device This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either or Table A 1 Absolute Maximum Ratings 1 Regulator and Analog Supply Voltage E NE ME MES 2 Logic Supply Voltage 2 V 3 Supply Voltage 2 VDDPLL V 4 Voltage difference VDDX to VDDR and VDDA V 5 Voltage difference VSSX to VSSR and VSSA 6 Digital I O Input Voltage 6 0 V 7 Analog Reference 6 0 V 8 XFC EXTAL XTAL inputs 3 0 V 9 TEST input 10 0 V 19 nao pn littoral dallo pins 22 4 M AN 13 Storage Temperature Range Tas 65 155 1 Beyond absolute maximum ratings device might be damaged M MOTOROLA 89 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 2
87. e respective Block User Guide for information on the module behavior in Stop Pseudo Stop and Wait Mode An important source of information about the clock system is the Clock and Reset Generator User Guide CRG 4 4 1 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode Wake up from this mode can be done via reset or external interrupts 4 4 2 Pseudo Stop This mode is entered by executing the CPU STOP instruction In this mode the oscillator is still running and the Real Time Interrupt RTI or Watchdog COP sub module can stay active Other peripherals are turned off This mode consumes more current than the full STOP mode but the wake up time from this mode is significantly shorter 4 4 3 Wait This mode is entered by executing the CPU WAI instruction In this mode the CPU will not execute instructions The internal CPU signals address and databus will be fully static All peripherals stay active For further power consumption the peripherals can individually turn off their local clocks 4 4 4 Run Although this is not a low power mode unused peripheral modules should not be enabled in order to save power M MOTOROLA 75 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc 76 M MOTOROLA For More Information On This Product Go to www freescale com Freescale
88. eescale com MC9S12DP256B Device User Gakeesgale Semiconductor Inc Figure 20 2 Recommended PCB Layout for 80 86 M MOTOROLA For More Information On This Product Go to www freescale com Freescale 2 User Guide 02 15 Appendix A Electrical Characteristics A 1 General NOTE The electrical characteristics given in this section are preliminary and should be used as a guide only Values cannot be guaranteed by Motorola and are subject to change without notice This supplement contains the most accurate electrical information for the MC9S12DP256B microcontroller available at the time of publication The information should be considered PRELIMINARY and is subject to change This introduction is intended to give an overview on several common topics like power supply current injection etc A 1 1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This classification is shown in the column labeled in the parameter tables where appropriate Those parameters are guaranteed during production testing on each individual device Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across
89. el Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 CANO Motorola Scalable CAN MSCAN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXACT cswai SYNCH time wupe SLPRQ INITRO CANE CLKSRC LOOPB LISTEN 9 WOKE SEPA SJw1 SJWO BRP5 BRP4 BRP3 BRP1 BRPO TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 WuPie escor LESIATT RSTATO TSTATI TSTATO aye WUPIE CSCIE RSTATE1 RSTATEO TSTATE1 TSTATEO OVRIE RXFIE TXE2 1 TXEO 0 TXEIE2 TXEIE1 TXEIEO 0 ABTRQ1 ABTRQO 0 0 0 0 0 2 ABTAK1 ABTAKO TX2 TX1 TXO 0 0 mpm 0 IDHIT2 IDHIT1 IDHITO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXERR7 RXERR6 RXERRS5 RXERR4 RXERR3 RXERR2 RXERRO TXERR7 TXERR6 TXERRS TXERR4 TXERR2 TXERR1 TXERRO 39 For More Information On This Product Go to www freescale com MC9S12DP256B Device User Gakeesgale Semiconductor Inc 0140 017F CANO Motorola Scalable CAN MSCAN Address Na
90. for information about the Clock and Reset Generator module 7 1 Device specific information 7 1 1 XCLKS The XCLKS input signal is active low see 2 3 13 PE7 NOACC XCLKS Port E I O Pin 7 Section 8 Enhanced Capture Timer ECT Block Description Consult the ECT 16B8C Block User Guide for information about the Enhanced Capture Timer module Section 9 Analog to Digital Converter ATD Block Description There two Analog to Digital Converters ATD1 and ATDO implemented on the MC9S12DP256B Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter module M MOTOROLA 81 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc Section 10 Inter IC Bus Block Description Consult the Block User Guide for information about the Inter IC Bus module Section 11 Serial Communications Interface SCI Block Description There are two Serial Communications Interfaces 5 and SCIO implemented on the MC9S12DP256B device Consult the SCI Block User Guide for information about each Serial Communications Interface module Section 12 Serial Peripheral Interface SPI Block Description There are three Serial Peripheral Interfaces SPI2 SPIL and SPIO implemented on MC9S12DP256B Consult the SPI Block User Guide for information about each Serial Peripheral Interface module Section 13 J1850 BDLC Block Description
91. he design or manufacture of the part M MOTOROLA For More Information On This Product Go to www freescale com DOCUMENT NUMBER Freescale Semiconductor Inc 9S12DP256BDGV2 D Revision History Version Revision Effective nti Number Date Date Author Description of Changes 29 MAR 29 MAR V01 00 2001 2001 Initial version VDD5 spec change 4 5 5 25V V01 01 8 MAY 8 MAY Current Injection on single pin 2 5mA 2001 2001 added DC bias level on EXTAL pin minor cosmetics and corrected typos changed ATD Electrical Characteristics seperate coupling ratio for V02 00 16 May 16 May positive and negative bulk current injection 2001 2001 added pinout for 80QFP corrected SPI timing 5 June m E V02 01 2001 corrected Expanded Bus Timing Characteristics 14 June V02 02 2001 Some corrections on pin usage after review V02 03 18 June Minor corrections with respect to format and wording 2001 Added SRAM data retention disclaimer Changed Oscillator Characteristics max 2 55 and replaced V02 04 26 June Clock Monitor Time out by Clock Monitor Failure Assert Frequency 2001 Changed Self Clock Mode Frequency 1MHz and max 5 5MHz Changed Ippps RTI and COP disabled to 400uA Corrected fref and REFDV SYNR Settings for PLL Stabilization Delay Measurements added and to Oscillator Characteristics Corrected text and tex 7 values Added thermal resistance for LQFP 80
92. ice User Guide 02 15 A D converter inputs Operation at 50MHz equivalent to 25MHz Bus Speed Development support Single wire background debug mode BDM On chip hardware breakpoints 1 3 Modes of Operation User modes e Normal and Emulation Operating Modes Normal Single Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Operating Modes Special Single Chip Mode with active Background Debug Mode Special Test Mode Motorola use only Special Peripheral Mode Motorola use only Low power modes Stop Mode Pseudo Stop Mode Wait Mode M MOTOROLA For More Information On This Product Go to www freescale com 19 MC9S12DP256B Device User dhkeese ale Semiconductor Inc 1 4 Block Diagram Figure 1 1 shows a block diagram of the MC9S12DP256B device 20 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicongucetemlnenaevice User Guide 02 15 Figure 1 1 MC9S12DP256B Block Diagram 256K Byte Flash EEPROM ATDO Men MTS mn VDDA VDDA 12K Byte RAM VSSA VSSA 4K Byte EEPROM Voltage Regulator XADDR14 15 2 XADDRI16 Single wire Background Debug Module XFC VDDPLL Clock and PK3 XADDR17 VSSPLL pij Reset Periodic Interrupt PK4 XADDR18 Generation p
93. ice clocks are derived from the EXTAL input frequency XTAL is the crystal output M MOTOROLA For More Information On This Product Go to www freescale com 59 MC9S12DP256B Device User dhkeese ale Semiconductor Inc 2 3 2 RESET External Reset Pin An active low bidirectional control signal it acts as an input to initialize the MCU to a known start up state and an output when an internal MCU function causes a reset 2 3 3 TEST Test Pin This input only pin is reserved for test NOTE The TEST pin must be tied to VSS in all applications 2 3 4 VREGEN Voltage Regulator Enable Pin This input only pin enables or disables the on chip voltage regulator 2 3 5 XFC PLL Loop Filter Pin PLL loop filter Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements Any current leakage on this pin must be avoided XFC R 0 Cp MCU see VDDPLL VDDPLL Figure 2 4 PLL Loop Filter Connections 2 3 06 BKGD TAGHI MODC Background Debug Tag High and Mode Pin The BKGD TAGHI MODC pin is used as a pseudo open drain pin for the background debug communication In MCU expanded modes of operation when instruction tagging is on an input low on this pin during the falling edge of E clock tags the high half of the instruction word being read into the instruction queue It is used as a MCU operating mode select pin during reset The state of this pin is latched to the
94. igured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 3 or 4 CAN3 2 3 35 PM6 RXCANA Port M I O Pin 6 PM6 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 3 4 CAN3 or 2 3 36 5 TXCAN2 TXCANO TXCANA SCKO Port M I O Pin 5 is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 2 0 or 4 CAN2 or It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 SPIO 2 3 37 4 RXCAN RXCAN4 MOSIO Port M I O Pin 4 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 2 0 or 4 CAN2 or It can be configured as the master output during master mode or slave input pin during slave mode MOSI for the Serial Peripheral Interface 0 SPIO 64 44 MOTOROLA For More Information On This Product Go to www freescale com Freescale 9 2 User Guide V02 15 2 3 38 TXCANO SSO Port M I O Pin is a general purpose input or output pin It can be configured as the transmit pin TXCAN of
95. me Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0150 CANOIDARO Read 0153 CANOIDARS3 Write 0154 CANOIDMRO Read 0157 CANOIDMRS3 Write 0158 CANOIDAR4 Read 015B CANOIDAR7 Write 015C CANOIDMR4 Read 015F CANOIDMR 7 Write AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 5 AM4 2 1 AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 5 AM4 2 1 FOREGROUND RECEIVE BUFFER see Table 1 2 SIE CANORXFG OREGROU C U see Table Write SUE CANOTXFG e FOREGROUND TRANSMIT BUFFER see Table 1 2 Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Extended ID Read 1028 ID27 ID26 ID25 ID24 ID23 ID22 ID21 xxx0 Standard ID 1010 ID9 ID8 ID7 ID6 ID5 104 103 Write Extended ID Read 1020 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 xxx1 Standard ID Read ID2 ID1 IDO RTR IDE 0 Write Extended ID Read 1014 1013 1012 1011 1010 109 108 107 xxx2 Standard ID Read CANxRIDR2 Write Extended ID Read ID6 ID5 104 103 102 101 IDO RTR xxx3 Standard ID Read Write 4 CANxRDSRO Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO xxxB CANXxRDSHR7 Write xxxC CANRxDLR Read DLC3 DLC2 DLC1 DLCO Write Read xxxD Reserved Write xxxE CANxRTSRH ee TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
96. me possible is given by Nypose 5 1 2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU preventing the CPU from executing code when VDDS is out of specification limits the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set A 5 1 3 External Reset When external reset is asserted for a time greater than the CRG module generates an internal reset and the CPU starts fetching the reset vector without doing a clock quality check if there was an oscillation before reset M MOTOROLA 107 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc A 5 1 4 Stop Recovery Out of STOP the controller can be woken up by an external interrupt A clock quality check as after POR is performed before releasing the clocks to the system A 5 1 5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes The controller can be woken up by internal or external interrupts After the CPU starts fetching the interrupt vector A 5 2 Oscillator The device features an internal Colpitts oscillator By asserting the XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave Before asserting the oscillator to the internal system clocks the quality of the
97. mmary Mnemonic Description 112 pin Voltage R Vpp1 2 13 65 2 5 Internal power and ground generated by internal regulator Vss1 2 14 66 OV 41 5 0 V External power and ground supply to pin drivers and internal Vssp 40 OV voltage regulator Vppx 107 5 0 V E External power and ground supply to pin drivers Vssx 106 OV VDDA 83 5 0 V Operating voltage and ground for the analog to digital converters and the reference for the internal voltage regulator Vssa 86 OV allows the supply voltage to the A D to be bypassed independently 85 OV Reference voltages for the analog to digital converter 84 5 0 VDDPLL 43 2 5 Provides operating voltage and ground for the Phased Locked Loop This allows the supply voltage to the PLL to be VssPLL 45 OV bypassed independently Internal power and ground generated by internal regulator VREGEN 97 5V Internal Voltage Regulator enable disable 2 4 7 VREGEN On Chip Voltage Regulator Enable Freescale Semiconguctomolnesevice User Guide 02 15 Enables the internal 5V to 2 5V voltage regulator If this pin is tied low VDD1 2 and VDDPLL must be supplied externally M MOTOROLA For More Information On This Product Go to www freescale com 69 MC9S12DP256B Device User dhkeese ale Semiconductor Inc 70 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semico
98. nfigured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as slave select pin SS of the Serial Peripheral Interface 1 SPIL 2 3 26 PH2 KWH2 SCK1 Port H I O Pin 2 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 SPIL 2 3 27 1 KWH1 MOSI1 Port H I O Pin 1 PH 1 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 1 SPI1 2 3 28 PHO MISO1 H I O Pin 0 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 1 SPIL 2 3 29 PJ7 KWJ7 SCL PORT J I O Pin 7 PJ7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller 4 CANA or the serial clock pin SCL of the IIC mod
99. ngucteomlneaevice User Guide 02 15 Section 3 System Clock Description 3 1 Overview The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules Figure 3 1 shows the clock connections from the CRG to all modules Consult the CRG Block User Guide for details on clock generation 8512 CORE core clock LE sna oscillator clock 5 0 1 2 CANO 1 2 3 4 XTAL Figure 3 1 Clock Connections M MOTOROLA 71 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 72 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconduetosrp 6 device User Guide V02 15 Section 4 Modes of Operation 4 1 Overview Eight possible modes determine the operating configuration of the MC9S12DP256B Each mode has an associated default memory map and external bus configuration controlled by a further pin Three low power modes exist for the device 4 2 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC MODB and MODA pins during reset Table 4 1 The MODC MODB and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation The states of the MODC MODB and MODA pins are latched into these bits on the rising edge of the re
100. nimum input voltage limit 2 5 V Latch up Maximum input voltage limit 7 5 V Table A 3 ESD and Latch Up Protection Characteristics EE Rating Symbol Min Max Unit EE Human Body Model HBM 2000 C Machine Model MM VMM 200 V C Charge Device Model CDM 500 V Latch up Current at T4 125 C 4 positive 100 5 mA negative 100 Latch up Current at T 27 5 C positive 4200 mA negative 200 90 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semicongeetame2bicpevice User Guide 02 15 A 1 7 Operating Conditions This chapter describes the operating conditions of the device Unless otherwise noted those conditions apply to all the following data NOTE Please refer to the temperature rating of the device C V M with regards to the ambient temperature T4 and the junction temperature For power dissipation calculations refer to Section A 1 8 Power Dissipation and Thermal Characteristics Table 4 Operating Conditions Rating Symbol Min Typ Max Unit Regulator and Analog Supply Voltage 5 4 5 5 5 25 V Digital Logic Supply Voltage Vpp 2 35 2 5 2 75 V PLL Supply Voltage VDDPLL 2 35 2 5 2 75 V Voltage Difference VDDX to VDDR and VDDA 0 1 0 0 1 V Voltage Difference VSSX to VSSR VSSA Avssx 0 1 0 0 1 V Oscillator fosc 0 5 16 MHz Bus Frequency fous 0 5 25 MHz MC9S12DP256B
101. ocument References User Guide Version Document Order Number HCS12 V1 5 Core User Guide 1 2 HCS12COREUG CRG Block User Guide V02 S12CRGV2 D ECT 16 8 Block User Guide V01 S12ECT16B8CV1 D 10B8C Block User Guide V02 S12ATD10B8CV2 D Block User Guide V02 S121ICV2 D SCI Block User Guide V02 S12SCIV2 D SPI Block User Guide V02 S12SPIV2 D PWM 8 8 Block User Guide V01 S12PWM8B8CV1 D FTS256K Block User Guide V02 S12FTS256KV2 D EETS4K Block User Guide V02 S12EETS4KV2 D BDLC Block User Guide V01 S12BDLCV1 D MSCAN Block User Guide V02 S12MSCANV2 D VREG Block User Guide V01 S12VREGV1 D PIM 9DP256 Block User Guide V02 S12PIM9DP256V2 D 16 44 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicongucteomlnensevice User Guide 02 15 Section 1 Introduction 1 1 Overview The MC9S12DP256 microcontroller unit MCU is a 16 bit device composed of standard on chip peripherals including a 16 bit central processing unit HCS12 CPU 256K bytes of Flash EEPROM 12K bytes of RAM 4K bytes of EEPROM two asynchronous serial communications interfaces SCI three serial peripheral interfaces SPI an 8 channel IC OC enhanced capture timer two 8 channel 10 bit analog to digital converters ADC an 8 channel pulse width modulator PWM a digital Byte Data Link Controller BDLC 29 discrete digital I O channels Port A Port B Port K and Port E 20 discrete
102. only value is a unique part ID for each revision of the chip Table 1 3 shows the assigned part ID number Table 1 3 Assigned Part ID Numbers Device Mask Set Number Part 101 MC9S12DP256 0K79X 0010 MC9S12DP256 1K79X 0011 MC9S12DP256 2K79X 0012 NOTES 1 The coding is as follows Bit 15 12 Major family identifier Bit 11 8 Minor family identifier Bit 7 4 Major mask set revision number including FAB transfers Bit 3 0 Minor non full mask set revision M MOTOROLA 49 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc The device memory sizes are located in two 8 bit registers MEMSIZO and MEMSIZI addresses 001C and 001D after reset Table 1 4 shows the read only values of these registers Refer to section Module Mapping and Control MMC of HCS12 Core User Guide for further details Table 1 4 Memory size registers Register name Value MEMSIZO MEMSIZ1 50 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguscteomlnensevice User Guide 02 15 Section 2 Signal Description This section describes signals that connect off chip It includes a pinout diagram a table of signal properties and detailed discussion of signals It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device 2 1 Device Pinout The MC9S1
103. oscillation is checked for each start from either power on STOP or oscillator fail tco our specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected The quality check also determines the minimum oscillator start up time tuposc The device also features a clock monitor A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency Table A 15 Oscillator Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating Symbol Min Typ Max Unit 1 C Crystal oscillator range fosc 0 5 16 MHz Startup Current iosc m Clock Quality check time out tcaouT 0 45 2 5 Clock Monitor Failure Assert Frequency 7 p eral soar wave puse wet ow External square wave pulse width high tExTH 9 5 External square wave rise time tExTR D Input Capacitance EXTAL XTAL pins pF DC Operating Bias in Colpitts Configuration on 12 C EXTAL Pin VDCBIAS v NOTES 1 fosc 2 22pF 2 Maximum value is for extreme cases using high Q low frequency crystals 3 XCLKS 0 during reset 108 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguctemlnenaevice User Guide 02 15 A 5 3 Phase Locked
104. ow strobe hold time D NOACC valid time to E rise tNov ns M MOTOROLA 121 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc Table A 20 Expanded Bus Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted Cj 50pF Rating Symbol Min Typ Max Unit IPIPO 1 0 valid time to E rise PWg tpop IPIPO 1 0 delay time PWg tp vy IPIPO 1 0 valid time to E fall NOTES 1 Affected by clock stretch add N x tyyc where N 0 1 2 or 3 depending on the number of clock stretches 122 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguscteomlnesevice User Guide 02 15 Appendix B Package Information B 1 General This section provides the physical dimensions of the MC9S12DP256B packages M MOTOROLA 123 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc B 2 112 pin LQFP package X L MORN F r 0 13 LM N SECTION 91 91 1A1 ROTATED 90 COUNTERCLOCKWISE x s1 NOTES 1 MENSIONING AND TOLERANCING PER SME Y14 5M 1994 MENSIONS IN MILLIMETERS ATUMS L M AND N TO BE DETERMINED AT EATING PLANE DATUM T MENSIONS S AND V TO BE D
105. pass twup 5 us M MOTOROLA 113 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 114 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicongucteomolnesevice User Guide 02 15 A 7 SPI A 7 1 Master Mode Figure A 5 and Figure A 6 illustrate the master mode timing Timing values are shown in Table A 18 551 OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT MISO INPUT MOSI OUTPUT MSB OUT2 BIT6 1 X LSB OUT K 1 If configured as output 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB Figure A 5 SPI Master Timing CPHA 0 115 M MOTOROLA For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 1 SS OUTPUT SCK 0 OUTPUT SCK CPOL 1 OUTPUT MISO 2 me pL Can 10 MASTER MSB OUT MASTER LSB OUT PORT DATA 1 If configured as output OUTPUT PORT DATA 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB Figure A 6 SPI Master Timing CPHA 1 Table A 18 SPI Master Mode Timing Characteristics Conditions are shown Table A 4 unless otherwise noted 200pF on all outputs Rating Min Typ M
106. pending on the source resistance The additional input voltage error on the converted channel can be calculated as Vggg K Rg With being the sum of the currents injected into the two pins adjacent to the converted channel Table A 9 ATD Electrical Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 C Max input Source Resistance Rs 1 Total Input Capacitance 2 Non Sampling Sampling 3 Disruptive Analog Input Current 4 Coupling Ratio positive current injection 5 Coupling Ratio negative current injection 98 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguctemlnenaevice User Guide 02 15 A 2 3 ATD accuracy Table A 10 specifies the ATD conversion performance excluding any errors due to current injection input capacitance and source resistance Table 10 Conversion Performance Conditions are shown in Table A 4 unless otherwise noted Vner Vay 5 12V Resulting to one 8 bit count 20mV and one 10 bit count 5mV ATDCLK 2 0MHz L D L D Ws e 5 2 10 Bit Differential Nonlinearity 3 P 10 Bit Integral Nonlinearity 4 10 Bit Absolute Error 5 8 Resolution E SB NL INL AE SB NL INL AE Counts Counts Counts mV
107. put pin leakage current as specified in Table A 6 in conjunction with the source resistance there will be a voltage drop from the signal source to the input The maximum source resistance Rg 44 MOTOROLA 97 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc specifies results in an error of less than 1 2 LSB 2 5mV at the maximum leakage current If device or operating conditions are less than worst case or leakage induced error is acceptable larger values of source resistance is allowed A 2 2 2 Source Capacitance When sampling an additional internal capacitor is switched to the input This can cause a voltage drop due to charge sharing with the external and the pin capacitance For a maximum sampling error of the input voltage ILSB then the external filter capacitor 2 1024 Ciyns A 2 2 3 Current Injection There are two cases to consider 1 Acurrent is injected into the channel being converted The channel being stressed has conversion values of 3FF FF 8 bit mode for analog inputs greater than and 000 for values less than unless the current is higher than specified as disruptive condition 2 Current is injected into pins in the neighborhood of the channel being converted A portion of this current is picked up by the channel coupling ratio K This additional current impacts the accuracy of the conversion de
108. r eere ud OB on 71 Section 4 Modes of Operation Aly 4S obtentu A o uie ated esa Poo aq S tubus dx laudans 73 4 2 Chip Configuration Summary i bon pee Pete E E Eee ete 73 23v oec vu tour Tre teda Edu 74 4 3 1 Securing the Microcontroller 74 4 3 2 Operation of the Secured Microcontroller 74 4 3 3 Unsecuring the Microcontroller 75 4 4 Low Power Modes 75 4 4 1 SIOD A E It cue E a A E e 75 4 4 2 Pseudo aeea aae TT 75 4 4 3 ge nep MR E 75 4 4 4 E cae icu Re haat ET ERN DR RE DAS nud Ue Dd 75 Section 5 Resets and Interrupts 5 1 qui K P EU ate 77 527 MECOS RI ANE Pe tod Bok ERREUR ne d 77 5 2 1 Vector Tablet 2 actu IER 77 222 Effects ORES an da te thee nne 1 78 5 3 1 VO DING CT EE 78 5 3 2 Memo DENEN a DN he ba els tes TL SUL 79 Section 6 HCS12 Core Block Description 44 MOTOROLA 7 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc Section 7 Clock and Reset Generator CRG
109. r enabled Internal Voltage Regulator disabled VDD1 2 and 5 VDDPLL must be supplied externally with 2 5V 4 3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents This feature allows Protection of the contents of FLASH e Protection of the contents of EEPROM Operation in single chip mode Operation from external memory with internal FLASH and EEPROM disabled The user must be reminded that part of the security must lie with the user s code An extreme example would be user s code that dumps the contents of the internal program This code would defeat the purpose of security At the same time the user may also wish to put a back door in the user s program An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM 4 3 1 Securing the Microcontroller Once the user has programmed the FLASH and EEPROM if desired the part can be secured by programming the security bits located in the FLASH module These non volatile bits will keep the part secured through resetting the part and through powering down the part The security byte resides in a portion of the Flash array Check the Flash Block User Guide for more details on the security configuration 4 3 2 Operation of the Secured Microcontroller 4 3 2 1 Normal Single Chip Mode This will be the most common usage
110. rs serial modules where a pre scaler will eliminate the effect of the jitter to a large extent Table A 16 PLL Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating Self Clock Mode frequency VCO locking range Lock Detector transition from Acquisition to Tracking Avid mode vi Lock Detection IALockl Un Lock Detection I unil Lock Detector transition from Tracking to Acquisition Aunt mode E PLLON Total Stabilization delay Auto Mode td PLLON Acquisition mode stabilization delay lacq 9 PLLON Tracking mode stabilization delay 10 Fitting parameter VCO loop gain 120 Fitting parameter VCO loop frequency D Charge pump current acquisition mode ich 5 D Charge pump current tracking mode ien C Jitter fit parameter 1 1 1 NOTES 1 96 deviation from target frequency 2 2 25 2 equivalent fyco 50MHz REFDV 03 018 Cs 4 7nF 470pF Rs 10KQ 112 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguctemolnenaevice User Guide 02 15 A 6 MSCAN Table 17 MSCAN Wake up Pulse Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 MSCAN Wake up dominant pulse filtered 2 us 2 MSCAN Wake up dominant pulse
111. rts to table 0 1 Derivative Differences V02 15 M MOTOROLA removed protected sector definition from table 1 1 For More Information On This Product Go to www freescale com MC9S12DP256B Device User amp Semioonductor Inc 4 M MOTOROLA For More Information On This Product Go to www freescale com Freescale 2 User Guide 02 15 Table of Contents Section 1 Introduction MEC 17 oe Gee TIT ROS ode teer 17 1 39 Modos ol OpDOFallOlk ur eiiis iioii al ee Mee Ke Maso 19 TA Block DIGOEAITI asta dicted CER REESE MERE Nu Pd Ioas id 20 15 Device Memory 22 1 6 Detailed Register Map vente eo ere whe th Pte Ws eee ete eae Re RE DT Reese ed 25 Ta Pat WO us ticdu dA IE 51 Section 2 Signal Description 2 1 Device PIDE ot Pi uu eos rh rS aestas uie AE 53 22 Signal Properties Summa s ssa t aceto d RE RE BAIE Ea EUN a 56 2 3 Detailed Signal 59 2 3 1 EXTAL XT AL Oscillator Pins ras nee Roe dee en 59 2 3 2 RESET External Reset
112. rved Reserved Reserved Freescale Semicongucteomolnesevice User Guide 02 15 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Flash Control Register fts512k4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EEPROM Control Register eets4k Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EDIVLD PRpiva 5 EDIV4 EDIV8 EDIV2 EDIVO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CBEIE CCIE NV6 NV5 NV4 EPDIS EP2 EP1 EPO SSF 0 BLANK CMDB6 5 2 CMDB2 CMDBO o o o o 0 10 9 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Reserved for RAM Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc
113. s 14 PortH J P Interrupt Input Pulse passed us NOTES 1 Maximum leakage current occurs at maximum operating temperature Current decreases by approximately one half for each 8 C to 12 C in the temperature range from 50 C to 125 C 2 Refer to Section A 1 4 Current Injection for more details 3 Parameter only applies in STOP or Pseudo STOP mode 94 44 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicongucteomlnesevice User Guide 02 15 A 1 10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements 1 10 1 Measurement Conditions measurements are without output loads Unless otherwise noted the currents are measured in single chip mode internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode Production testing is performed using a square wave signal at the EXTAL input A 1 10 2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address data and control signals as well as on the duty cycle of those signals No generally applicable numbers can be 95 M MOTOROLA For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc given A very good estimate is to take the single chip currents and add the currents due to
114. se cycling are specified at the operating conditions noted The program erase cycle count on the sector is incremented every time a sector or mass erase event is executed NOTE All values shown in Table A 12 are target values and subject to further extensive characterization Table 12 NVM Reliability Characteristics Conditions are shown in Table A 4 unless otherwise noted Data Rating Retention Lifetime 15 C EEPROM 40C to 125C NOTE Flash cycling performance is 10 cycles at 40C to 125C Data retention is specified for 15 years NOTE EEPROM cycling performance is 10K cycles at 40C to 125 Data retention is specified for 5 years on words after cycling 10K times However if only 10 cycles are executed on a word the data retention is specified for 15 years M MOTOROLA 103 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 104 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguctemlncesevice User Guide 02 15 A 4 Voltage Regulator The on chip voltage regulator is intended to supply the internal logic and oscillator circuits No external DC load is allowed Table A 13 Voltage Regulator Recommended Load Capacitances Rating Symbol Min Typ Max Unit Load Capacitance on VDD1 2 220 nF Load Capacitance on VDDPLL Ci ypDfcPLL 220 nF
115. set signal The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map ROMON 1 mean the Flash is visible in the memory map The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal Table 4 1 Mode Selection BKGD 7 ROMON MODB MODA Bit Mode Description Special Single Chip BDM allowed and ACTIVE BDM is 0 0 0 X 1 allowed in all other modes but a serial command is required to make BDM active 0 0 1 X 0 Emulation Expanded Narrow BDM allowed 0 1 0 X 0 Special Test Expanded Wide BDM allowed 0 1 1 X 0 Emulation Expanded Wide BDM allowed 1 0 0 X 1 Normal Single Chip BDM allowed 0 0 1 0 1 1 1 Normal Expanded Narrow BDM allowed Peripheral BDM allowed but bus operations would cause 1 1 0 X 1 bus conflicts must not be used 0 0 1 1 1 SLOT Normal Expanded Wide BDM allowed For further explanation on the modes refer to the Core User Guide Table 4 2 Clock Selection Based on PE7 PE7 XCLKS Description Colpitts Oscillator selected 0 External clock selected M MOTOROLA 73 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc Table 4 3 Voltage Regulator VREGEN VREGEN Description 1 Internal Voltage Regulato
116. t Analog Input AN7 of PAD 7 7 ETRIGO None ATDO External Trigger Input of ATDO Port AD Inputs Analog Inputs PAD 6 0 ANO 6 0 None i AN 6 0 of ATDO ADDR 15 8 PA 7 0 DATA 15 8 Disabled Port A I O Multiplexed Address Data 1 ADDR T7 0 PB 7 0 DATA 7 0 EREJET VDDR PUCR Disabled Port B I O Multiplexed Address Data PE7 NOACC XCLKS VDDR PUCR Up Port E I O Access Clock Select While RESET PE6 IPIPE1 VDDR pin is low Port E I O Pipe Status Mode Input Down While RESET IPIPEO VDDR pin is low Port E I O Pipe Status Mode Input Down 4 PUCR Up Port E I O Bus Clock Output PUCR Up Port E Byte Strobe Tag Low PE2 PUCR Up Port E in expanded modes PE1 Port E Input Maskable Interrupt Always up PEO Port E Input Non Maskable Interrupt PERH 22 KWH7 552 VDDR PPSH Disabled Port I O Interrupt SS of SPI2 PERH PH6 KWH6 SCK2 VDDR PPSH Disabled Port H I O Interrupt SCK of SPI2 MOTOROLA For More Information On This Product Go to www freescale com 57 MC9S12DP256B Device User dhkeeseale Semiconductor Inc 1 Disabled Internal Pull Pin Pin Name Pin Name Pin Pin Power Resistor Description Funct 1 Funct 2 Funct Funct 4 Funct 5 Supply Reset CTRL State V
117. t or output pin It can be configured as the receive pin RXD of Serial Communication Interface 0 SCIO 2 3 58 PT 7 0 IOC 7 0 Port T I O Pins 7 0 PT7 PTO are general purpose input or output pins They can be configured as input capture or output compare pins IOC7 IOCO of the Enhanced Capture Timer ECT 2 4 Power Supply Pins MC9S12DP256B power and ground pins are described below NOTE All VSS pins must be connected together in the application M MOTOROLA 67 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc 2 4 1 VDDX VSSX Power amp Ground Pins for I O Drivers External power and ground for I O drivers Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded 2 4 2 VDDR VSSR Power amp Ground Pins for I O Drivers amp for Internal Voltage Regulator External power and ground for I O drivers and input to the internal voltage regulator Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded 2 4 3 VDD1 VDD2 VSS1 VSS2
118. ted from PINT Chip Internal Power Dissipation W Two cases with internal voltage regulator enabled and disabled must be considered 1 Internal Voltage Regulator disabled Pint VbDA 2 Roson lio is the sum of all output currents on I O ports associated with VDDX and VDDR For Rpson is valid R OL sor outputs driven low DSON P respectively V V RDSON en for outputs driven high 2 Internal voltage regulator enabled Pint Ippg is the current shown in Table A 7 not the overall current flowing into VDDR which additionally contains the current flowing into the external loads with output high 2 Pio Roson lio is the sum of all output currents on I O ports associated with VDDX and VDDR 92 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicongusctemlnesevice User Guide 02 15 Table A 5 Thermal Package Characteristics Rating Unit C W C W Thermal Resistance LQFP 80 double sided PCB _ _ 7 Neat with 2 internal planes JA 41 NOTES 1 The values for thermal resistance are achieved by package simulations 2 PC Board according to EIA JEDEC Standard 51 2 3 PC Board according to EIA JEDEC Standard 51 7 A 1 9 I O Characteristics This sec
119. ter cap X7R tantalum gt 100nF ceramic X7R VDDX filter cap X7R tantalum OSC load cap OSC load cap PLL loop filter cap PLL loop filter cap DC cutoff cap PLL loop filter res See PLL specification chapter Quartz The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself The following rules must be observed M MOTOROLA 83 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc e Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins C1 C6 Central point of the ground star should be the VSSR pin Use low ohmic low inductance connections between VSS1 VSS2 and VSSR e VSSPLL must be directly connected to VSSR e Keep traces of VSSPLL EXTAL and XTAL as short as possible and occupied board area for C7 C8 C11 and Q1 as small as possible Donot place other signals or supplies underneath area occupied by C7 C8 C10 and Q1 and the connection area to the MCU Central power input should be fed in at the VDDA VSSA pins 84 MOTOROLA For More Information On This Product Go to www freescale com M MOTOROLA Freescale Semicongusetemlnesevice User Guide 02 15 Figure 20 1 Recommended PCB Layout 112 LQFP 85 For More Information On This Product Go to www fr
120. the Motorola Scalable Controller Area Network controllers 1 or 0 CANO It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 SPIO 2 3 39 2 RXCAN1 RXCANO MISOO Port I O Pin 2 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 CANO It can be configured as the master input during master mode or slave output pin during slave mode MISO for the Serial Peripheral Interface 0 SPIO 2 3 40 PM1 TXCANO TXB Port I O Pin 1 is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 CANO It can be configured as the transmit pin TXB of the BDLC 2 3 41 RXCANO RXB Port M I O Pin 0 PMO is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 CANO It can be configured as the receive pin RXB of the BDLC 2 3 42 PP7 KWP7 PWM7 SCK2 Port P I O Pin 7 PP7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 7 output It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 SPI2
121. the external loads Table A 7 Supply Current Characteristics Conditions are shown in Table A 4 unless otherwise noted 1 P Run supply currents mA Single Chip Internal regulator enabled Ipps 65 Wait Supply current 2 P All modules enabled PLL on Ippw 40 mA P only RTI enabled 5 Pseudo Stop Current RTI and COP disabled 2 40 C 370 P 27 C 400 500 C 70 450 3 85 550 C Temp Option 1002 DDPS 600 1600 105 650 V Temp Option 120 800 2100 125 850 M Temp Option 140 1200 5000 Pseudo Stop Current RTI COP enabled 2 C 40 570 27 600 70 650 4 85 C DDPS 750 C 105 850 C 125 1200 140 1500 Stop Current C 40 12 27 25 100 70 100 85 130 C Temp Option 100 C PPS 160 1200 C 105 200 V Temp Option 120 350 1700 C 125 400 M Temp Option 140 600 5000 NOTES 1 PLL off 2 At those low power dissipation levels T4 can be assumed 96 44 MOTOROLA For More Information On This Product Go to www freescale com Freescale 912 User Guide V02 15 A 2 ATD Characteristics This section describes the characteristics of the analog to digital converter A 2 1 ATD Operating Characteristics The Table A 8 shows conditions under which the ATD operates The following constraints exist to obtain full
122. three transmit buffers Flexible identifier filter programmable as 2 x 32 bit 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx Tx error and wake up Low pass filter wake up function for self test operation Enhanced Capture Timer 16 bit main counter with 7 bit prescaler 8 programmable input capture or output compare channels Two 8 bit one 16 bit pulse accumulators 8PWM channels Programmable period and duty cycle 8 61 8 channel or 16 bit 4 channel Separate control for each pulse width and duty cycle Center aligned or left aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs e Serial interfaces Two asynchronous Serial Communications Interfaces SCI Three Synchronous Serial Peripheral Interface SPI e Byte Data Link Controller BDLC SAE J1850 Class Data Communications Network Interface Compatible and ISO Compatible for Low Speed lt 125 Kbps Serial Data Communications in Automotive Applications e Inter IC Bus Compatible with I2C Bus standard Multi master operation Software programmable for one of 256 different serial clock frequencies e 112 LQFP package JO lines with 5V input and drive capability 18 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguctemolnensev
123. tion describes the characteristics of all 5V I O pins All parameters are not always applicable e g not all pins feature pull up down resistances M MOTOROLA 93 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc Table A 6 5V Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Input High Voltage 0 65 Vpps V T Input High Voltage VDD5 0 3 V 2 Low Voltage VL 0 35 Vppg V T Input Low Voltage Vit VSS5 0 3 3 Input Hysteresis mV Input Leakage Current pins in high impedance input 4 Vin Vpps OF V gt 555 Output High Voltage pins in output mode 5 Partial Drive C2mA Full Drive 10mA Output Low Voltage pins in output mode 6 p Drive loj 2 Full Drive 10 Internal Pull Up Device Current 7 tested at VL Max uA Internal Pull Up Device Current 8 P tested at uA Internal Pull Down Device Current 9 tested at uA Internal Pull Down Device Current 10 tested at V Max 11 D Input Capacitance pF Injection current 12 Single Pin limit mA Total Device Limit Sum of all injected currents 13 P Port H J P Interrupt Input Pulse filtered u
124. uct Go to www freescale com Port P Interrupt Channel 7 of PWM SCK of SPI2 44 MOTOROLA Freescale Semicongucteomolnesevice User Guide 02 15 Internal Pull Pin Pin Name Pin Name Pin Pin Power Resistor Description Funct 1 Funct 2 Funct Funct 4 Funct 5 Supply Reset CTRL State PERP Port P I O Interrupt Channel 6 of PP6 KWP6 VDDX Disabled SA PP5 KWP5 Disabled Port P Interrupt Channel 5 of i iss PWM MOSI of SPI2 Port P Interrupt Channel 4 of KWP4 Disabled PWM MISO of SPI2 PP3 KWP3 Disabled Port P Interrupt Channel of PWM SS of SPI1 PP2 KWP2 Disabled Port P I O Interrupt Channel 2 of i E PWM of SPI1 PP1 KWP1 Disabled Port P I O Interrupt Channel 1 of i THUS PWM MOSI of PPO KWPO Disabled Port P Interrupt Channel 0 i PAS PWM MISO of SPI1 PS6 SCKO Port S SCK of SPIO PS5 MOSIO Port S I O MOSI of SPIO misoo ERE vox PERS up Port S vo MISO of SPIO PS3 TXD1 Port S I O TXD of SCI1 PS2 RXD1 Port S I O RXD of SCI1 es TXDO i vox PERS Up Ports vo TxD of SCIO PSO RXDO VDDX Port S I O RXD of SCIO PT 7 0 IOC 7 0 VDDX Disabled Port T I O Timer channels 2 3 Detailed Signal Descriptions 2 3 1 EXTAL XTAL Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins On reset all the dev
125. ule M MOTOROLA 63 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeeseale Semiconductor Inc 2 3 30 PJ6 KWJ6 RXCAN4 SDA PORT J I O Pin 6 PJ6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as the receive pin RXCAN for the Motorola Scalable Controller Area Network controller 4 CANA or the serial data pin SDA of the IIC module 2 3 31 PJ 1 0 KWJ 1 0 Port J Pins 1 0 and PJO are general purpose input or output pins They can be configured to generate an interrupt causing MCU to exit STOP or WAIT mode 2 3 32 PK7 ECS ROMONE Port I O Pin 7 PK7 is a general purpose input or output pin During MCU expanded modes of operation this pin is used as the emulation chip select output ECS During MCU normal expanded wide and narrow modes of operation this pin is used to enable the Flash EEPROM memory in the memory map ROMONE At the rising edge of RESET the state of this pin is latched to the ROMON bit 2 3 33 PK 5 0 XADDR 19 14 Port I O Pins 5 0 5 are general purpose input or output pins In MCU expanded modes of operation these pins provide the expanded address XADDR 19 14 for the external bus 2 3 34 PM7 Port M I O Pin 7 PM7 is a general purpose input or output pin It can be conf
126. ut pins should be configured as outputs after reset in order to avoid current drawn from floating inputs Refer to Table 2 1 for affected pins 5 3 2 Memory Refer to Table 1 1 for locations of the memories depending on the operating mode after reset The RAM array is not automatically initialized out of reset M MOTOROLA 79 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc 80 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semicongucteomolnesevice User Guide 02 15 Section 6 HCS12 Core Block Description Consult the HCS12 Core User Guide for information about the HCS12 core modules i e central processing unit CPU interrupt module INT module mapping control module MMC multiplexed external bus interface breakpoint module BKP and background debug mode module Table 6 1 Configuration of HCS12 Core Name Description MC9S12DP256B Configuration PUCR RESET PUCR reset state 90 NUM INT Interrupt Request Bus Width 56 INITEE RST INITEE reset state 01 INITEE register is writeable once in normal modes PPAGE register is writable in all PPAGE SMOD ONLY PPAGE Write only in special mode modes reset state of the PPAGE register is 00 INITEE WOK INITEE Write anytime in normal mode Section 7 Clock and Reset Generator CRG Block Description Consult the CRG Block User Guide
127. ve select pin SS of the Serial Peripheral Interface 0 SPIO 2 3 51 PS6 SCKO Port I O Pin 6 PS6 is a general purpose input or output pin It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 SPIO 66 44 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconguctemlnenaevice User Guide 02 15 2 3 52 PS5 MOSIO Port S 1 0 Pin 5 PS5 is a general purpose input or output pin It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 0 SPIO 2 3 53 PS4 500 Port I O Pin 4 PS4 is a general purpose input or output pin It can be configured as master input during master mode or slave output pin during slave mode MOSI of the Serial Peripheral Interface 0 SPIO 2 3 54 PS3 TXD1 Port S I O Pin PS3 is a general purpose input or output pin It can be configured as the transmit pin TXD of Serial Communication Interface 1 SCIL 2 3 55 PS2 RXD1 Port S I O Pin 2 PS2 is a general purpose input or output pin It can be configured as the receive pin RXD of Serial Communication Interface 1 SCI1 2 3 56 PS1 00 Port I O Pin 1 PS1 is a general purpose input or output pin It can be configured as the transmit pin TXD of Serial Communication Interface 0 SCIO 2 3 57 PSO RXDO0 Port S I O Pin 0 PSO is a general purpose inpu
128. y as a well as on the frequency and can be calculated according to the following formula t HC NM 25 snp fous A 3 1 2 Burst Programming This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled The time to program a consecutive word can be calculated as 1 1 an NVMOP bus tbwpgm The time to program a whole row is torpgm swpgm 31 tbwpgm Burst programming is more than 2 times faster than single word programming M MOTOROLA 101 For More Information On This Product Go to www freescale com MC9S12DP256B Device User dhkeese ale Semiconductor Inc A 3 1 3 Sector Erase Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes 1 a 4000 NVMOP The setup time can be ignored for this operation A 3 1 4 Mass Erase Erasing a NVM block takes 1 20000 NVMOP The setup time can be ignored for this operation A 3 1 5 Blank Check The time it takes to perform a blank check on the Flash EEPROM 15 dependant on the location of the first non blank word starting at relative address zero It takes one bus cycle per word to verify plus a setup of the command t check location 10 Table A 11 NVM Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted

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