MSI-P900 USER MANUAL
Contents
1. cc O m CS0 CS4 Chip 2 oe gt Select W W Pins O un gt A8 A15 Address 74HCT688 gt Select Jumper Pins o 5 W W Select Pins for a IOR IOW SAO SA3 IRQ3 IRQ7 IRQ9 5V 5V 12V 12V and GND Figure 1 Block diagram of the MSI P900 Prototyping Card Page 1 MSI P900 User Manual TOP VIEW EEEEREFFEEE HH Hm ibe RE BRR RRR Ree eee 2 LILIL ONIS ooo E a hm LE a i MJ y l W OO ED DREIER ERRIIELZERSE TE DJ ojm m MSI P900 Figure 2 MSI P900 Layout BOTTOM VIEW MSI P900 User Manual Page 2 ll HARDWARE DESCRIPTION A Card Configuration The bus interface for the card provides wire wrap jumpers for the various functions as shown in Figure 2 The connections for DO D7 IOR IOW CSO CS4 IRQ2 IRQ7 IRQ9 SAO SA3 5V 5V 12V 12V and GND are provided by wire wrap headers which are positioned on the bottom of the card This provides easy access to wire wrap DIP sockets and other components positioned in the prototyping area see Fig 2 TOP VIEW Other signals that are required can be wire wrapped directly from the PC 104 bus connector pin The prototyping area will accommodate various combinations of 0 3 and 0 6 width DIP sockets SIPs and 0 1 gri2. 1 and AO 1 A1 1 A2 0 and A3 0 The input device also uses IOR during a read cycle 3 An output device at address 70B1H base 31H which activates CS3 and AO 1 Al 0 A2 0 and A3 0 The output device also uses IOW during a write cycle A program sequence to read the input device store the value at input_data and write the result to the output device is define base_address 0x7080 define input_device_addr 0x13 define output_device_addr 0x31 int input_data storage for input data input data inp base_address input device addr outp base address output device addr input data Page 4 MSI P900 User Manual APPENDIX Page 5 MSI P900 User Manual
3. MSI P900 PC 104 PROTOTYPING CARD USER MANUAL OED PC 4 ul PC 104 Embedded Industrial Series Microcomputer Systems Inc 1814 Ryder Drive Baton Rouge LA 70808 Ph 504 769 2154 Fax 504 769 2155 CONTENTS I INTRODUCTION II HARDWARE DESCRIPTION A Card Configuration B Card Addressing C Example C Program Sequence APPENDIX Circuit Diagrams MSI P900 I INTRODUCTION The MSI P900 is an 8 bit PC 104 stackthrough prototyping card for simple rapid hardware implementation of user designs The card is I O mapped using 16 bit addressing and provides a fully decoded bi directional 8 bit data bus DO D7 five low enable chip selects CSO CS4 decoded from jumper selectable addresses A8 A15 Note an asterisk following the pin assignment denotes low level active state e g CS1 means CS1 is active lo 0 Also provided are jumper selectable IOR IOW SAO SA3 IRQ3 IRQ7 amp IRQ9 5V 5V 12V 12V and ground as shown in the block diagram of Figure 1 Sixty percent of the card area accommodates user supplied 8 pin thru 40 pin wire wrap DIPs SIPs resistors capacitors transistors etc as well as standard I O connectors up to 40 pin with 0 1 grid spacings Solder pad connections are provided on the bottom surface for easy connections of devices to 5V and ground Top and bottom views of the card are shown in Figure 2 74HCT245 gt D0 D7 W W Pins
4. d connectors at sites Pl and P2 The bottom surface of the card has numerous solder pads 0 062 square to accommodate connections for GND and 5V B Card Addressing The card address is set by installing appropriate jumpers for A7 thru A15 An uninstalled jumper for a given address bit sets the bit to 1 true and an installed jumper sets the bit to O false Addresses A7 thru A15 define the base address of the card from OOOOH to FF80H on integral 80H boundaries where H denotes a hexadecimal number To assign a base address of 3080H for example install jumpers A8 A9 A10 All Al4 and A15 When assigning a base address be sure that 80H contiguous addresses are available in which there are no I O address conflicts Since 64 536 addresses are available in the address space this normally should not be a problem The 80H space is required in order to accommodate the five chip selects CSO thru CS4 Page 3 MSI P900 User Manual The chip select addresses for CSO CS3 are the following Chip Select Address CSO base addr 0 CS1 base addr 10H CS2 base addr 20H CS3 base addr 30H CS4 base addr 40H C Example C Program Sequence For a simple C program illustration consider a case in which the prototype devices are configured for the following parameters 1 Abase address for the card of 7080H insert jumpers for A8 A9 A10 All and A15 2 An input device at address 7093H base 13H which activates CS
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