Home

Ultimate User Manual - IPHC

1. rstpix cklatch lt 200 ns gt Figure 4 Synchronization signals for SDS timing diagram January 2011 Ultimate User Manual V 1 1 10 IPHC ne 1 5 4 Algorithm sparse data scan SDS description By Co Cc Colum ojolojojo ojojojojojojojojo ojojo nO a m Sttel State2 State3 Pone 64 Discriminators ni ms dd 1 bit at bottom of bank Enable bit is set to 1 for first hit Read row by row Y Code 2 bits Pixel in group Rd 63 0 Coding ojojojojo ojojojojojojojojo ojojo o Dat i Data compression IS Inst ll gt 2 Inst A 3 Inst Selection of column o 6 Inst address of first hit pixel in group Sparse Data Scan algorithm This is the sequence used to decode column address of first hit pixel in group it s corresponding to read enable bit which is set to 1 The number of instruction is limited at 6 Each state is composed of 6 bits Column address plus 2 bits code Column Address decoder 64 to 6 i gt Maximum 6 States registers of 8 bits gt Bank address register of 5 bits gt Status register of 3 bits number of states by bank UJ D 5 A gt oa T Storing of N states by bank and generating status register STATUS 2 0 January 2011 Ultimate User Manual V 1 1 11 1 5 5 Synoptic 1 1 1 64 col BO gt Control signals 3J9 First 3 col B 1 2 0 7
2. Header2 Framecpt Data Data Framecpt length0 lengtht StatusLine D E gt 1 word 16 successive bits 0 J datalengtho datalength Figure 21 Format of the output Data of Ultimate Mono Channel and 80 MHz Mode 80 MHz Dua channel clkrate O and dualchannel 1 The maximum number of data generated by the suppression of zeros is 918 x 16 bits for each output This overflow implies the truncation of the data frame A EEE Dualchannel 1 ir ES ciko 80 MHz clkrate 0 O lt n 9 CLKD o MKD n 15 0 SE bo Data E datalength DOO HeaderO Framecpt lengthO StatusLine State x State Der y gt lt Trailer 1 gt Data datalength DO1 Header 1 Framecpt State StatusLine gt cons eae Trailer 2 length1 31 16 A word 16 successive bits Figure 22 Format of the output Data of Ultimate Dual Channel and 80 MHz January 2011 Ultimate User Manual V 1 1 46 Ultimate Mode 160 MHz Mono channel clkrate 1 and dualchannel 0 The maximum number of data generated by the suppression of zeros is 922 x 2 x 16 bits for the output This overflow implies the truncation of the data frame 012345 67 8 9 10111213 14 15 Frequency ciko 160 MHz
3. From Mux test Output Test output p P PADS Delay p syncout e 16 times clock gt 79 gt o gt clkout From Configuration Registers Headers trailers format clk160MHz A e 22920 004 3 5 Dood Bm From frame counter frame number o e From memory writing Words written in frame E gt gt gt 32322 Dot From RAM reading output D K B Address E 346 reading ad clk160MHz ml f 8 f 16 clkrate Clock divider dualchannel p gt 1 16 January 2011 Ultimate User Manual V I 1 23 Ultimate 2 Control Interface 2 1 Introduction The JTAG controller works independently of the main external clock and asynchronously AT the end of the JTAG communication the user can access to the initialization of the sequencer by the start sequence The control interface of Ultimate complies with Boundary Scan JTAG IEEE 1149 1 Rev1999 standard It allows the access to the internal registers of the chip like the bias Register and the different registers control 2 2 JTAG Instruction Set After the main reset sequence the user must load into the Instruction Register of the JTAG controller the code of the desired operation to perform or with the code of the desired data register to access Notes JTAG mandatory instruction JTAG mandatory instruction JTAG mandatory instruction JTAG mandatory instruction JTAG mandatory instruction User instruction datareg0 datareg datareg2 datar
4. The multiplexer And the memory management BlocO From Analog he 1 status t 6 stat Memory matrix em D o cs Management x 0 960 bits N 0 UJ Sparse Data M Fai 9 states 8 status Memory gt RAM Scan 0 ultiplexer Bloc 14 ze nise Tests PADS Control 1 status 6 states c Control t signals 1 3Jd ral 5 Kpa gt Frame Serializer counter Dat discriminator Test Serial test result Output Figure 3 SUZE block diagram 1 5 SPARSE DATA SCAN SDS 1 5 1 Introduction Based on a sparse data scan algorithm to find hit pixels discriminator output 1 this module Sparse Data Scan SDS receives a line constituted of 960 pixels 959 to 0 divided in 15 blocks of 64 pixels Up to 4 contiguous pixel signals above Vihreshoia Of the discriminator will be encoded in a 2 bits state word following the address of the Ist pixel Block 14 13 12 11 10 9 8 7 6 15 4 13 2 1 0 O E un o lt D e Each block extracts of the 64 pixels bus status group 6 states column addresses encoded state 1 overlapping These 15 blocks works 1n parallel and give 6 x 15 states to the next stage January 2011 Ultimate User Manual V I 1 Ultimate 1 5 2 One block description The next figure shows the different steps of the sparse data scan for one block RstLine Enable s dic
5. Ultimate User Manual v 1 1 56 Design Revievv Digital Core documentation Preliminary version G Doziere A Himmi 3 54 Chronograms for a the first frame readout 393 4us 359 BUS 095 PUS 333 Tus 333 Bus 388 Sus 400us 400 145 400 Us DO 3us 400 4u5 07 545 400 6u8 ADU fus 400 6us 400 9us 401us 401 1us 401 215 clk160 II LA LU ULL start Syncs seqrstb a seqrstb d clk80 WUT UU MIUT MAN LANTA ckload load h start s cikrovv a ER 4 clkrowevod clka lastgr e lastrow 5 5 D oo Line 6 Line 5 Line 4 Line 2 Line 1 LineO mk linemarker pwr on 1 927 sel gr 57 sel row int 1927 clp 92 7 cip rd calib latch sync mxpwITOW sync mxrow Figure 33 readout start initial phase a After 2 rising edge of the clkl when start 1 the internal seqrstb a and seqrstb d are generated b After the falling edge of START signal when the first falling edge of clkrow the sequence of sequencer pix reg is actived for state machine Readout Controller when load his staying at the high level c The data sequencer suze reg is loaded to a state machine Readout Controller during line 5 phase d At the falling edge of load h
6. the sequencer fsm for pixel generates all useful signals for pixel and discriminators e The readout of the matrix starts January 2011 Ultimate User Manual V 1 1 od starts 133 Acus 194415 333 bus J33 595 Ultimate SEERIATE 233 921 333 DUS REER 333 bus did DIS 333 bus 439 045 cik160 cik80 start syncs seqrstb a seqrstb d ckload load h start s clkrow clk80 start syncs seqrstb d seqrstb a ckload load h start s clkrow clkrowevod clka Figure 34 zoom 1 on the readout synchronization of the internal reset L ma e OO p 15 1413 121110 9 8 7 6 5 4 3 2 1 0 LUL i i i i i H i L i i i i i i i i y i i i i i i i b i i i i i i i L i i 1 i i i i i i i i i i i i i i i i i i i ji i b Line 4 L 200 lastgr lastrow mk linemarker pwr on I9271 sel gr 57 sel row int I 927 clp 927 clp January 2011 Figure 35 zoom on the readout clock row and latency before read out Ultimate User Manual V I 58 clk80 start syncs seqrstb d seqrstb a ckload 1 load h start s cikrovv cikrovvevod cika mk Design Revievv
7. 500 ns min time 1 US max ckrow DEL Start of the main status Idle sequencer Signal markers allow the readout monitoring and the data outputs analogue and digital sampling K clka and clka mk are running when the main sequencer starts January 2011 Ultimate User Manual V I 1 55 Ultimate ab D ane K When speak signal is active marker of synchronization for analogue outputs is generated on clka mk pad K Marker of synchronization for digital outputs is generated on pad syncout this signal is shifted clk80 independently of the signal speak 000 of 2 times clock clk80 from startframe signal pad syncout is set during 4 times ine rstirame Last Frame i 1 Current Frame i one o oo ooo o startline o ckrdpixons M s XE scan load Testsynchronization Scan KE output pad 110 clk80 An E 13 2 11 10 PLU UU UU UU UU UU UU UU UU U U 1 Turi UU LUUU UU UU UU UU U ULU l pad clkout pad do0 pad doi e TH 4 imes clock ck80 a 3 5 3 Synchronization for stop and re start readout Successive pixel frames are read until the readout clock 1s stopped A frame resynchronization can be performed at any time by setting up the start token again January 2011
8. So E cm P IXel o 959 ALT 0 959 sel row int 0 Soo row0 oM I E QI sel_gr 0 E on Y S 0 959 row15 Pixel 15 0 m Pixels 959 S 15 1959 MEC B row15 E E ES Iu NC t EL sel_row_int 15 Matrix 928 rows x 960 columns ColO O LO e o O Pixel o12 0 Pixel o12 959 Si e e ant row912 RRON A ES eae row S un Sel S 57 959 NW o EE sel gr b7 IT E KT Pixeli7 o 0 mi Pixel 7 927959 S row927 A eno vicis C QE Hee L sel row int 927 rd E rd E calib calib h Lo Diseri h Tr Discri ss aten ____ atch Dis latch ___ Dis latch ___ Column 0 Column959 Figure 41 matrix of pixels and discriminators for switching The following picture shows the initialization phase of the synchronizations signal applied to the discriminator January 2011 Ultimate User Manual V 1 1 63 Ultimate 400us QOL5 60045 73045 rstb cikl telk start 0 5 IV e calib 0 5 0 5 V latch 0 5 a 1 FT E lastrow Reset Jtag access Init 1rst frame readout Successive frame readouts cika Figure 42 matrix of pixels and discriminators The following pictures show the synchronization signal for the readout of the matrix note the generation of the different clock like clkrow frequency line clkrowevod frequency
9. Ultimate User Manual A Himmi G Doziere G Bertolone W Dulinski C Colledani A Dorokhov Ch Hu F Morel H Pham I Valin J Wang Institut Pluridisciplinaire Hubert Curien IN2P3 CNRS UdS Strasbourg France Y Degerli F Guilloux CEA Saclay DAPNIA SEDI January 2011 Ultimate User Manual V I 1 Document history December 2010 Based on Mimosa 26 Version January 2011 OJ I Ultimate chip Submitted January 11 AMS 035 Opto Version 928 x 960 pixels Fa January 2011 Ultimate User Manual V I 1 2 Ultimate ze SUN RE ne gs 5 1 1 General description of STAR CMOS pixel sensor esse 5 1 2 Architecture description esse eee 5 ES RET T SO ica 7 1 4 SA AUTO 910 620 ire OVA E iria eee er 8 1 5 RSS DATA SCAN JO 8 1 5 1 TOMO QUA NN u m 8 15 2 One block desc PON eo DIU mI MONIS DM a SIUS 9 1 5 3 Timing dlast ani Tor control Signals rss tet YU PEE Isa duree uen yx sen Ue ova tu ee bees ead aeos de 10 1 5 4 Algorithm sparse data scan SDS description 11 1 5 5 A A O A 12 1 5 6 og e e o 13 1 6 States AD ICC odii ottimi teu ee eT ae ee eee ee ee 14 1 6 1 NO ea 14 1 6 2 Gon E e e 15 1 6 3 Module 6 x 8 Y 9 and module 6 x 7 9 15 1 6 4 NO E G Mu REIR 18 1 7 Menor mad MD 19 1 7 1 Memory control multiplexer test RAM 19 TO 19 PO DEN A e aera einen see eee 19 e Wondno Modo enero ere Tene ee ene se mere 21 I PC AIS COUDECE T 27 1 7 3 Gaz ro 23 2 OTO B Sn e 24 2
10. Column i Column Figure 32 Format of the MUX word Test 141 143 157 159 are undefined January 2011 Ultimate User Manual V 1 1 54 Ultimate 3 5 Main sequencer 3 51 Introduction After the power external reset and after the configuration of the JTAG registers the external user sends a start sequence The unit first generates an internal low active reset seqrstb a or seqrstb d and starts all the internal finite states machines fsm for the schedule and the synchronization of ultimate chip All internal functions are set to the initial states and the internals registers receives the values from JTAG If the desired operating mode does not correspond to the default one set all configuration registers following to the appropriate settings cf configuration registers in annex JTAG Register Set For main synchronization signals we use the following process At the reset mode the value of each parameter is latched on a shift register At the working mode this shift register works as a circular shift register looped on itself For a signal synchronized Ona line the cycle takes 16 times clock Ona frame the cycle takes 928 x one line time 3 5 2 Main phases for ultimate After the loading of the JTAG registers the readout of Ultimate can initiated with the following sequence 30V Vdd 500 ns min time 1 us max Power supply UN 80 MHz Power reset rstb D Do start
11. Figure 1 Schematic view of sparse data scan for one block I Adr 6 bite The algorithm proceeds through four consecutive steps summarized below e In the first step the data inputs for the process are extracted from 64 discriminators e The second step consists in encoding groups of hit pixels This logic provides Enable bits and Code bits for each column composing a bank The Enable bit 1s set to 1 for the first hit pixel in a group The number of Enable bits set to 1 characterizes the state January 2011 Ultimate User Manual V I 1 9 Ultimate e The third step selects the states each state 1s selected successively by a sparse data scan It uses a chain of alternated NAND and NOR gates for the priority management during the sparse scan The generation of states requires several instructions The number of states N in a bank is related to M states in a row The algorithm manages up to N 6 instructions or states in a bank e At each instruction the column address of the state is decoded The last digital step stores the N states and generates status information indicating the number of states per bank Each bank has its own address encoded in 5 bits 15 3 Timing diagram for control signals These inputs signal are given by the main sequencer Synchronization signals used for sds s i rstline 4 aes pe lng ckrdpix ckmemlatch
12. en disc autoscan 1 January 2011 Ultimate User Manual V I 1 32 Ultimate 34 5 SUZE multiplexer test 3 4 5 1 Introduction The SDS results are combined by a multiplexer This test allows validating the multiplexer To realize this test we emulate inside the chip a matrix of 960 rows For this purpose the patt lineO and patt_linel must be used as exSDSined on paragraphs 2 3 5 and 2 3 9 We select one address row defined into jtg sel rovyscan 0 to 23F of the suze seq register During each frame the selected row is processed and the data outputs after multiplexer data frame is 160 bits wide are serialized with falling edge of CLKD CLKL 8 and transmit off chip via DOO pad DOI pad is not used The synchronisation marker for digital outputs 1s generated on MKD pad and corresponds to first bit serialized 3 4 5 2 Configuration test Register Bit Name Value configuration En scan E suze seq En auto scan discri O S E U ro modeO En patt only patt_line0 959 0 patt linel 959 0 User defined same as patt_lineO to simplify the checking of this test 3 4 5 3 Synoptic Gress Test structure MU XClkscanout CLKD DFF Scansync_out M KD Loadscan En_scan En_scanout Shift Register y d Test aftermux i test Speed po SFR d DOO PLA douts1 PLA dataout1_test A DO1 Figure 31 MUX test structure block diagram January 20
13. m 200 ns Adline 9 0 0 1 Figure 38 synchronization periodic signals for suze part January 2011 Ultimate User Manual U 60 Ultimate 3 5 7 Pipeline of the readout chain Each stage of the chip is complex from analogical acquisition pixel to the storage of the pixel data and requires time for achievement of all function The operation of each block lasts one line time given by the following equation linetime 16x l 200ns S0MHz The schematic below shows very simplified the pipeline given by the main operations EN x 960 x 960 x 720 x 112 i gt generation E NI ea pixel T Diseri data f 2 sds f mux6x15to9 f o 2 memory f e ol eo Line Line i 1 Line i 2 Line i 3 Line i 4 synchro line 4 e We introduce a margin of minimum 10 ns between the end of the achievement of the functions and the rising edge of the synchronization line of each stage to increase the reliability of the readout The chip switches 2752 latch boxes 960 960 720 112 at the same time With the experience on Mimosa26 and the separation of the analog and digital supply voltages the experiment shows that these switches present low influence and do not disturb the pixel stage 3 6 Pixel and analog core sequencer 3 6 1 Pixel and discriminator read out sequence synchronization The digital core realizes the switch
14. 0 State0 63 0 6 States BO BlocO 7 0 State5 0 Status BO al Control signala 64 col B1 First 3 col B2 gt 7 0 State0 2 0 0 6 States B1 63 0 i Bloc 1 7 0 State5 D Status B1 2 0 64col B2 Control signals First 3 col B3 gt gt 63 0 Bloc2 7 0 2 0 2 0 0 State0 6 States B2 0 0 State5 Overlapping Bo B Overlapping B Bo gt Status B2 Overlapping B2 Bs gt Overlapping Bi 1 B ami 2 0 7 01 State0 Suze 0 Multiplexer 64 co Bi eme 163 0 Bloci 9 StatesB L Control signals D 7 0 States Status Fi Bi 2 0 irst 3 co i 2 0 B ua Overlapping B B 0 0 0 0 0 OverlappingB B 7 2 0 7 0 State0 L 0 Bloc 14 Control signals us States 0 0 0 j 2 01 2 0 9 Not connected Figure 5 SDS block diagram January 2011 Ultimate User Manual V I 1 12 Ultimate 1 5 6 Coding The following table shows the format of the result for one block LO aT et se oT oT 7 8 9 10 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 o 1 e o 1 Status block coding Column address coding Column address coding Column address nevv bit210j OJ d Op d ESA e LT o ij 2 coding Column address coding Column address coding
15. 20 7 um set of 64 pixels Set of 15 successive jointed bank 960 pixels The frame is a set of 928 lines In default mode 200 ns 1 e 16 times the period of the main internal clock 80 MHz 12 5 ns Frame duration duration line x the content of the cycle Max register Ultimate User Manual v 1 1 78
16. Column address Overlapping Figure 6 format of the SDS results For the whole line we have 15 x 1 status blocks and 6 states January 2011 Ultimate User Manual V 1 1 13 Ultimate 1 6 States multiplexer 1 6 1 Introduction The states multiplexer reads out the outcomes of the 15 banks x 6 states and keep up maximum 9 states from the previous stage SDS Three objects constitute this block 2 identical modules Mux 6x8 9 which extract each one 9 states and 1 status for an half line module Mux 2 x 9 9 which retains 9 states and a status from these 2 modules Bloc 0 1 status 6 states ED 0 00 x 0 1 status 9 states FromPLA 4 0 x 8 Bloc 7 O 1 status 6 states D A 1 status 9 states E N Mux control gt lt signals O gt lt Bloc 8 1 status 6 states o 0 D From PLA x lt 1 status 9 states 0 CO 0 Dat _ Bloc 14 1 status 6 states B MULTIPLEXER Figure 7 Multiplexor top view Sample signals This synchronous module uses 3 signals The first one initiate the process rstline The second one samples the selection of the hit kept ckrdpix The third one en fsm mux signal latches the record states 12 5 ns 0 5 10 15 cik i rstline I LI ckrdpix Ei en fsm mux lt i line ME Figure 8 Synchronization signals for MUX 6 x 8 gt 9 MUX 6 x 7 9top view January 2011 Ultimate User Manual V 1 1 14 Ultimate Figure 9 Module
17. Digital Core documentation Preliminary version G Doziere A Himmi a Line 5 Line 4 Line 3 Line 2 Line 1 cika lastgr lastrow mk_linemarker pwr on 19271 sel gr 57 sel row int 11927 cipl9271 cip rd calib latch sync_MxXPWITOW sync_mxrow rstpix ckrdpix ckmemlatch cklatchmem rstline ckrdpixmux cklatch adline 9 0 rstframe startframe startline ckrdpix5ns scan load scan cik pad syncout pad cikout pad_do0 pad_do1 January 2011 EEE Latency of 4 limee st LineO Pd Not done on sequencer but after e only for highlight the last line PIXEL eS HAE L LI L L LI LJ L SDS hana AAA UL TULIO MAT LULL rn TULL U UW jn rr ni A TUA MUX r ane A e et eet ee ee MEMORY 3 o ET i e0 Figure 36 Pipeline of the readout processing from analog to memory part simulation timing diagram Ultimate User Manual V 1 1 59 meses Design Review Digital Core documentation Preliminary version G Doziere A Himni 3 5 5 Line synchronization for pixel and discriminator The sequencer generates the signals for all
18. ProbePadLI40_ GND3ALLPI40 Power GND3ALLPI40 Power GND3ALLPI40 Power GND3ALLPI40 Power VDD3ALLPI40 Power NDDSALLPIS0 Power Li icem ada AVDDSALLPIA0 Power AvppsaLLPIA0 Power AGNDSALLPIA0 Power AGNDsALLPIA0 Power GNDSALLPI40 Power GNDSALEPI40 Power Gnpsaripiso Power VDD3ALLPI40 Power VDD3ALLPI40 Power Lo Power AGND3ALLPI40 Power AGNDJALLPI40 Power AGND3ALLPISO Power AGNDGALLPI40 Power AGND3ALLPI40 Power 74 Ultimate Pad x y Name Description Part VO Cell Type Analogue power AVDDSALLPI40 Power Analogue power AVDD3ALLP140 Power Analogue power AVDD3ALLP140 Power Analogue power AVDD3ALLP140 Power Analogue power _ AVDD3ALLPI40 Power Analogue power AVDD3ALLPI40 Power DirectPadi4o 7 Ouput voltage of VDDA DirectPadi4o EE optional __ DirectPadldO DirctPadld disable the regulator ICUPMO ground GND3ALLPI40 Power input digital power VDDSALLPI40 input digital power VDD3ALLP140 o input digital power VDDSALLPI40 o input digital power VDD3ALLPMO 19014 35 PLL digital power VDD3ALLP140 PLL disable pll veo af ICDP 140 select pll output af ISUPIMO PLL digital
19. every 2 lines and the clp one per line clamping of the pixel frequency January 2011 Ultimate User Manual v 1 1 64 TRES Design Review Digital Core documentation Preliminary version G Doziere A Himmi m Baseline Y s 404 90530834 Fus Cursor Baselne 54 2325 1313 Name INPLITS S clkrow 400us 407us clkrowewod cip en linemarker segrstb a sync nmopwrrnow poll sync GOV Line 2 gt pwr on 12 sel row int I 2 cip 12 Line 1 pwr on I 1 i sel row int I 1 ES lp It l clp I sel row int Io pwr on oj A Line 0 i pwr on I 327 M sel rom int 927 T cip 1 927 0 o Line 927 M Mi Line 325 pwr on I 826 0 Fe sel row int 11326 0 clp 826 E Line 325 ran pwr on I 825 0 gt sel row int 1925 cip I 325 0 Line 927 Line 926 e Line 925 c Figure 43 timing diagram after the start matrix of pixels and discriminators frame 0 January 2011 Ultimate User Manual V I 1 65 haora Flan c Design Review Digital Core documentation Preliminary version G Doziere A Himmi El Baseline 587 85023150243 f Cursor Bassline 2 0567965 085us Name Cursor J585 Bus dB Bus SBB ZUS 506 415 D06 Au 906 615 587us 587 Zus a INPUTS s clkrow 1 LT clkrowevod i clo 1 ie Line 2 EE pur on ie 0 Je sel row int I 2 0 e clp_ 2 Line 1 E pur on I 1 i E sel_row_int_1 1 gt elp I 1 E cip IO i se
20. instruction register 5 bits long On reset it 1s set with the ID CODE instruction During its reading the 2 last significant bits are set with the markers specified by the standard the remaining bits contain the current instruction X IX IX j1 0 QJ 24 1 DEV ID Register The Device Identification register 32 bits long allows the reading of the fixed hardware value into the chip The selection of the ID CODE instruction causes the shifting of this fixed value to TDO the JTAG serial output of the chip Ultimate ID CODE register value for ULTIMATE is UT1 0x55543101 31 0 ID CODE Device Identification register 55543101 HET i lt SOH gt 242 Boundary Scan Register BSR The Boundary Scan Register according to the JTAG instructions tests and set the IO pads The Ultimate BSR 11 bits long allows the test of the following input and outputs pads Corresponding Pad 10 ext disc line Input ext disc line Hit emulation during one line ext pwr pulse Input ext pwr pulse oS O qa 9 C 2 IN NE 6 speak T input T speak Initial control for JTAG communication Clock output O pad dol Output pad dol Data output padi January 2011 Ultimate User Manual V 1 1 26 Ultimate 2 5 THE BIAS GEN Register The BIAS GEN register 148 bits wide sets simultaneously the 19 DAC registers After reset the register is set to 0 a value which fixes the minimum power consumption of the circuit The current values of
21. pernime 50 Dd e cas 50 AAA O NI a 50 3 4 4 5 Transfer function of discriminator and pixel digital readout calibration 51 SAO e INN TTT 51 3 4 5 SUZE MD le e a a se a oui 53 SAS A A IA 53 K COMBO MON OS a m 53 puo VOP E E ae dE ME ee eee RA 53 3454 MUX scanning word description eese sie kn riain bani EI Ehe Abd 54 3 5 GE otras 55 3 5 1 IpntodUc OI ia 55 2092 Ma phases TOR Umata 55 3 5 3 Synchronization for stop and re start readout eee 56 3 5 4 Chronograms for a the first frame readouts 57 3 5 5 Line synchronization for pixel and discriminator aaa aaa nana sese eee 60 3 5 6 Line synchronization Tor SAR none nn NE ete ee ee a 60 39 7 TS E E E E a ESI E easiapa 6l 3 6 Pixel and analog core sequencer ss 61 3 6 1 Pixel and discriminator read out sequence synchronization sss 61 3 6 2 Disable discriminator output sequence iii aaa ahahah aaa aaa Yaa vana yaara aaya eee eee nnne nnne 67 3 6 3 Analog discriminators SEQUENCE L SE gg and ed t n n U buk do 67 Jl Mamwstenal SC C1 IC ALON e e Runa tn 68 SR E nan aaa 69 TT OA o RU I Ne 70 Glossary abbreviations and acronyms tables ee TI January 2011 Ultimate User Manual V 1 1 4 Ultimate 1 Suze and main sequencer 1 1 General description of STAR CMOS pixel sensor Ultimate is the final sensor chip for the upgrade of STAR inner layer of the vertex detector Its architecture integrates main function of Mimosa26 Monolithic Active Pixel Sensor MAPS
22. registers 8 bits large allow the user to select specific digital mode of the chip Bit Register name Purpose Rst Working mode range status 7 en v disc digtst Enable the internal injection of VTEST 0 0 the matrix for the analog outputs Ta L E active clock CMOS 4 en linemarker Add two rows at the end of matrix for the chip readout The LINEPAT REG register is selected to emulate discriminators outputs For analogue outputs the 2 Test Levels VTESTI and VTEST2 are selected which emulate a pixel output in RD and CALIB phases 3 en mode speak Select Marker signal or Readout Clock for digital and analogue data MK CLK A and MK CLKD pads ES emulate discriminators outputs re EL synchronization 1 pee Rem ros synchronization 2 1 The minimum wide of asynchronous external START signal is 500 ns the maximum us and this signal is active at high level 2 When en extstart 1s disabled it s possible to generate internal START by accessing JTAG Start bit JTAG Start signal is realized by three JTAG access First step this bit is set to 0 second step it is set to 1 and at last it is set to 0 2 19 BYPASS Register The Bypass register consists of a single bit scan register Its selection loads the code in the Instruction register during this load the instruction register contains an undefined instruction January 2011 Ultimate User Manual V I 1 38 Ultimate 3 Running Ultimate The fo
23. rst rst n rx SDS sel January 2011 Address Analog to converter analog buffer Chip enable clock clamp Chip select counter control current Data Digital to converter digital disable discriminateur enable Elementary Time Unit digital analog First in first out jtag load Low voltage differential signaling marker Multiplexer pattern pixel power Power save read reference reset reset reception Sparse data scan selection Ultimate User Manual disable the internal signal high level active Notation for internal signal high level active l l ETU 1timeclock 2 main chip frequency S0MHz 12 5ns Memory First In first Out Cf JTAG interface IEEE 1149 Structure that catches only nine groups of pixels among 6 x 15 groups The first 9 states are kept Here pattern of image Reset high level active Reset low level active Asynchronous way to access from a hit to another hit The next one has the priority V ll ki seq suze sync tek tdi tdo tms Ultimate sequencer Suppression of zeroes synchronization Test clock Cf JTAG interface IEEE 1149 Test Data Input Cf JTAG interface IEEE 1149 Test Data Output Cf JTAG interface IEEE 1149 Test Management Cf JTAG interface IEEE 1149 System test transmission write Word or locution Line duration January 2011 Sensor unit element surface 20 7 x
24. stage of the memory manager January 2011 Ultimate User Manual V I 20 Ultimate 1 7 1 3 Working mode rstframe pro im j ckrdpix TE Initialisation of the Se ey Lu al Lud eai ses ece Jas suis Mux output latch d pjeter Listes peme Liste i D LineO q C O E Line 1 Line 2 e2 so EN RAMO 0 15 state RAM1 16 31 Line 927 Reverse writing memory input words Figure 15 Odd even swapping working mode procedure The memory space includes four single access RAM 2048 words of 16 bits IP from AMS to ensure the continuous read out The writing and reading mode represent two independent blocks The process fills up the memory only when the data appears The memory stops to fill up when no new hit is detected the memory is full or at the end of the frame According to the data received the completion rate of the memory can change from a frame to another one e During the current frame the writing mode uses 2 SRAM s while the reading mode works with 2 others SRAM s e The writing process is realized by the writing of word of 2x16 bits In order to reduce the useful memory space see Figure 13 if the last word of 16 bits 1s not written in case of even number of hit states in the current row next row processing status is written in that location e At the end of the frame a state mac
25. stripes of 8 columns is fully scanned at each frame and then swapped with the next block of 8 columns at right and so on until the complete analyze of all the columns January 2011 Ultimate User Manual V I 1 48 31 2598 EF Cursor Bas Name v z E gt Last Col EP CLK_A A pron Ky Entest nalogMk El Sel naDriver 0 119 i E MK CLK A Bs Out naDriver 7 0 gt Out naDriver 7 Qut naDriver 5 Out naDriver 5 Dut amp naDriver 4 OutAnaDriver 3 Dut amp naDriver 2 Out naDriver 1 Out naDrivet 0 January 2011 Cursor v h 8000 00 gt 0 8 values 38334 38334h 99334 L2 38334 E 38334 I 38334 98334 Ultimate 17 136 400ns 0000 00000000 00000000 00000000 00000001 Data Ana Row 927 8 values gt c 17 137 600ns 8000 00000000 00000000 00000000 00000000 Data Ana Row 0 First Row add becond Row add 2 04692V Vtest1 Vtest2 Vtesti Vtest2 04692V 4 Figure 26 Ultimate User Manual Mode scan for analog output v 1 1 49 Ultimate 344 Transfer function of discriminator and pixel digital readout calibration 3 4 4 1 Introduction This test readout mode allows obtaining the transfer function of discriminator and calibrating the digital readout Pixel discriminator 3 4 4 2 Transfer function of discriminator During the test mode en_disc_tst bit set to 1 in the RO MODEZ2 r
26. the DACs are read while the new values are downloaded during the access to the register An image of the value of some DAC can be measured on its corresponding test pad range Name Test Pad 143 136 DACI7 i pix Pixel source follower bias _ _ _ o 135 128 DACI6 Ji disc Discriminator bias2 127 120 DACIS li disel f Discriminatorbias 79 12 DAC9 i ana buf Analogue Buffer bias 3 3 o 71 64 DAC8 v tst2 Test Level emulates a pixel output v tstl IDEM S S 55 48 DAC6G ilvdsrx LVDSPAD bias 47 40 DACS _ilvdstx LVDSPAD bis illl b caval L iae ERR consp pe emm consp 23 16 DAC2 Ref amp Tst Buffer bias DACI Discriminator Povver Pulse bias DACO Discriminator Clamping bias E 3 1 The clamping voltage in pixel can be provided either by the 4 bit DAC in the range of 1 9 2 275 V or in an external way v clp pads In this case the regulator has to be disabled by JT AG access disvclp 2 The voltage v disc ref2 are bufferized four times and applied to each group of discriminators A B C and D These four voltages are multiplexed and output on one pad named v disc ref2 In the same way the four voltages v disc reflA B C and D are bufferized and applied to each group of discriminators These four voltages are multiplexed and output on one pad named v disc refl The group can be selected by JTAG access en anamux sel 1 en anamux sel 0 In normal mode the analog m
27. with fast binary readout and including a zero suppression logic The sensor consists of a matrix composed by 928 rows x 960 columns pixels of 20 7 um pitch for a size of the chip of 20 22 mm x 22 71 mm The design process Austria Micro System AMS C35B4 OPTO uses 4 metal and 2 poly layers The thickness of the epitaxial layer stretches out up to 15 um in Hi Resistivity substrate 400 Ohm cm The design tools follow the CADENCE DFII 5 1 with DIVA ASSURA CALIBRE rules The chip has been submitted in an Engineering Run via CMP on 20 January 2011 In the STAR vertex detector the hit rate is evaluated at 2 4 x 10 hits s cm The design of the sensor is driven by the high readout frequency in order to keep the track multiplicity per frame at a low level It is done by read out pixel columns in parallel row by row The chip readout time is 185 6 us Each pixel includes an amplification and Correlated Double Sampling CDS and each end of column is equipped with a discriminator The threshold of the discriminator is programmable by slow control After analogue to digital conversion digital signals pass through the zero suppression block The digital signals are processed in parallel on 15 banks then arranged and stored in a memory row by row Two memories banks have been implemented in the sensor to perform read and write operations simultaneously see Memory management At each frame the circuit sends a specific marker to initialize the format
28. 011 Ultimate User Manual V 1 1 71 Ultimate Pad x ly Name Description so 80099 Master clock LVDS compatible n Cell 8189 35 clkl n probe ProbePadL140 8289 35 digital power INE VDD3ALLP140 8389 35 digital power ee VDD3ALLP140 8489 35 754 gnd ground GND3ALLP140 8589 35 75 4 gnd ground GND3ALLP140 86 8689 35 clkd n probe m ProbePadL 140 Readout clock for digital data 8889 35 cikd p O LVDS TX 89 8989 35 cikd p prope l ProbePadL 140 90 9089 35 digital power VDD3ALLP140 9189 35 do0_n probe o ProbePadL_ 140 nice Pata ain 92 9289 35 754 do0 n Domum hende O 9489 35 do0_p_ probe NN ProbePadL 140 9589 35 GND3ALLP140 96 9689 35 dol n prove NN ProbePadL140 fas fal nr en 97 9789 35 754 dol n soda O 99 9989 35 dol p prove NN ProbePadL140 10089 35 digital power VDD3ALLP140 10189 35 75 4 mkd n probe L ProbePadL 140 pam n sata E 102 10289 35 75 4 mkd n Marker for digital data O 10489 35 75 4 mkd p probe 0000000000000 ProbePadL 140 10589 35 754 gnd ground GND3ALLP140 10689 35 75 4 gnd ground GND3ALLP140 10789 35 digital power NE VDD3ALLP140 10889 35 digital power EN VDD3ALLP140 11014 35 ground Memory GND3ALLP140 11114 35 ground Memory GND3ALLP140 January 2011 Ultimate User Manual V I 1 PAD LVDS Rev140 Ji Y J lt J VI lt O Jj lt Y OD OQ OTTO lele OD O Type LVDS RX
29. 1 RO Ae 24 22 TODI 24 2 3 VISOOSeBISIST Elba 25 Z2 OT AMM A HEN E 26 2 4 DI MED Cu r emer 26 205 2 Boundary scam Be NI B SRI oes eO UM eI UND UN IU D 26 2 9 THE BLOS GEN IR C2 1S I UU UU em 27 20 pal II E 29 2 GS SC E NA 29 28 AENA tn 30 2 Mono ne ICO sans DO NTE 30 e e 31 iz icu lcd 32 2 12 header alero reset reviens VR Erin arm EE ete E eres eee aetna DUANE TUUS 33 TO 34 ZOI EO ee ne eee een AEE ME 36 Zo RO NDI ROCCO aii ies 36 2 16 RO MODE2 Register sss 25 S I RO MODEL 4 T a 37 Zo TO MODEO etnias 38 2 19 BASS RO IS E E ME EUN 38 RGD I uos ndm ERUIT UEM MEM UMEN MEE EUM 39 3 Reset md ZOT dr 39 January 2011 Ultimate User Manual V 1 1 3 4 Ultimate 3 1 1 Spes eee A PU E A 39 DL I RERO e eE RR RR CCD 39 e sd NT TTE 39 3 3 iens Tie DIAS OMe AA A 40 3 4 Analogue and digital Data Format sese sss sees eee eee 42 3 4 Tau A OO I UEM mM DUDEN MUN I UEM MM MEM TE 42 3 4 2 Normal mode data Tornos 42 E A OO DDR CR PDR O Ute detis Id SUM MM UEM MM UE 42 EA RR 43 AS NRE OS RARE RCE RO ERREI 43 E Em 43 Zo ramo e PN NNI NN 43 3 4 2 6 Data L ndimi int nin dini 43 I S ates LIne SIAE aa 43 3 4 3 TE 48 43 1 Analogue outputs Normal pixel SION nin n se nenin shah pic lentas 48 3 4 4 Transfer function of discriminator and pixel digital readout calibration 50 SUM o ya ieee e 50 544 2 Transfer function of discriminator
30. 11 Ultimate User Manual V I 1 53 Ultimate 3 4 5 4 MUX scanning word description The first bit outputting from the shift register is the LSB of the word 160 bits analyzed as following Caution The following range of bits unused 29 31 45 47 61 63 77 79 93 95 109 111 125 127 State 1 rot 3 5 6 7 9 1 13 A 18 10 00 AZ SIA 25 26 27 25 25 35 5 roT 2 3 4 516 7 8 9 A 5 cC gt e F 0 1 2 3 4 516 7 8 9 A B ClDIE FI rr tasty S 7 sesi CCC Coding Column 32 33 54 35 36 37138 39740 41 42 43744 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59760 61 Lojtjaj3s ja Ss ToT 7 BP ITAL BCI DUEL FPO 1 2 3 4 5 6 7 8 9 A B C D E F Lol 1 2 3 4 5 e 7 ee Lol 11 21 S 4 5 el vj ef S Column i Column e465 66 er 68 63 88 89 50 91 2 93 0 11 2 3 4 5 e 7 S MES 0 11 2 3 4 5 e 7 el MES Coding Column Coding Column State 7 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111112 113 114 115 116 117 118 119 120 121 122 123 124 125 COT IRISIADSISIALSISIADISISIPIELTISDOIRISIADSISLALSISIADBISIPIEIE CLIC CLSC Coding Column Coding Column State 8 Sateo 125 129 130 131 192 135 154 135 136 137 138 199 140 141 142 145 144 145 146 147 148 149 150 151 152 155 154 155 156 157 155 159 FOIT I2 8 4T5 6T7 8T9 A 8S C P ETF LO L1 L2 3 4 19 T7185 T9 LA T8 C E TET Lo T 2L 3L 2L 5L SL 7L 8L o 2 3 4 5 el
31. 11 Ultimate User Manual v 1 1 31 Ultimate 2 11 suze_seq register The suze seq registers 160 bits large contains all parameters to generate readout zero suppression suze sequence range name configuration Name value Code 144 128 SDS mae 12 memory management SDS nai 80 dckrdpixSns Synchronization signal 6 times every 82aa ckrdpix5ns line for memory management shifted of 5 ns compared with Ckrdpix line for memory management memory management SUZE part 31 16 Reset signal 6 times every line for SDS 0555 15 0 drstframe Reset frame signal for memory 2000 rstframe management e Related timing with fxz80 MHz Theses signals are used by zero suppression circuit January 2011 Ultimate User Manual V 1 1 32 Ultimate 2 12 header trailer register The register called header trailer includes 4 registers of 16 bits as shown below Basic configuration value 63 48 Synchronization header for serial outputo 5555 1 47 32 Synchronization header for serial output1 5555 pC 31 16 Synchronization trailer serial outputo AAAA Synchronization trailer serial outputl AAAA For both modes according to the register DUALCHANNEL the header and the trailer of each data frame can be different The following table shows the possible Header and the Trailer which ensure the unicity in the data frame The unicity is guaranteed without the Frame counter l Possible Header or Trailer T vem Table 1
32. 2011 Ultimate User Manual V 1 1 Inat Phri amp ariphnaire Huber Era Sr s Design Review Digital Core documentation Preliminary version G Doziere A Himmi 3 4 3 Test mode 3 4 3 1 Analogue outputs Normal pixel signal The en ana tst bit set to 1 in the RO MODEI register implies the connection of the rightmost 8 columns of pixels to the 8 voltage buffers the outcoming signals are available on output pads at the top of the matrix The en anadriver scan set to 1 starts the analog test in the RO MODEL The scanning of the matrix now starts and stripes of 8 pixels are connected to the analog outputs The analog test is performed considering a reduced size of the array about 928 rows x 8 columns it requires therefore acquisitions of 120 frames to analyze the full matrix The next figure shows how to realize the analog characterization and which parts of the matrix are under test for each frame The MKA is the synchronization marker for the analog outputs When en ana tst bit set to 1 it appears at the end of each frame sampling the analog channel of the new frame on the next rising edge of CLKA Further with en anadriver scan set to 1 this marker appears at the end of the frame for each sub matrix Oo co E AI gt gt Pad Z D D E E ia LL LL Frame N t2 Frame N 1 Frame N L927 Figure 25 Analog characterization of the pixel The matrix of pixels divided in
33. 411435 75 4 gnd ground GND3ALLPI40 Power Regulator DirectPad 140 Power DirectPad 140 Power optional __ DirectPad_140 Power DirectPad 140 Power 1CDP140 ICUPIA0 VDD3ALLPI Power VDDSALLP140 Power VDDSALLP140 Power Regulator vopsarrpia Power GwpALLPHAo Power optiona DiretPad 140 Dirceu n o Css ssw3s 154 me mm GNDALLPIao Powe 56 semas rsa ext punue extemal power puise cnan 1Cppiao pee LE Des vopsAuPao Power Ls sowas rsa ew dise ine extemalline discriminator 1cDpia0_ Leosweas ra mer aimimigromd GNDSaLLPI40 Powe 6116189351754 gnd ground GNDGALLPI40 Power 621628935 754 speak p probe UN ProbePadL 140 analog Main PAD LVDS Rev140 65 16589 35 175 4 speak n probe NN ProbePadLi40 661668935 75 4 vdd digitalpower _ VDD3ALLPI40 Power Inputs VDD3ALLPI40 Power 681688935 75 4 end prob ground GND3ALLPI40 Power 69 6989 35 GND3ALLP140_ Power 7089 35 75 4 start p probe ProbePadL 140 B SS amn DI Synchronize the outputs PAD LVDS Rcv140 pulldown DI PAD LVDS Rev140 73 738935 754 start n probe Power Power Power Power 78 v88935 754 ciki p probe I ProbePadL 140 LVDS 79 7989 35 75 4 cikl p Master clock LVDS compatible PAD LVDS Rcv140 RX January 2
34. 6 x 9 9 top view 1 6 2 Coding The following table shows the format of the result for the line given to the memory management ESA SLajsj 171819 JAJPBIOJDJEJPFJojiI21 3s 4 5 je 171819 JAJBICIDJEJ Ene of 11 2 si 4 5 e 7 el IM AAA OOOO SJ4 s5 6 7 8 9 JALBICID EjFIOJi 2 8 4 5 6 7 8 9 AJB CI D EJF i 2 3 4 SL GENE HO HO Lo 11 21 S 4 SL Gj 71 s o j j Column i Column State 6 State 7 Lo 11 21 S Asp Gj 71 el S j Column Coding Column Figure 10 format of the multiplexer results 1 6 3 Module 6 x 8 gt 9 and module 6 x 7 gt 9 8 Banks 9 Status 6 states Bank Bank Token 1 Bank ext1 Next2 V SELECTION STATES OF MULTIPLEXER BANKS TOKEN Z X9N sajejs L LIXON sajejs Z Quen sejejs MAIN STATES MACHINE Calculation of next Banks to read and selection states to output enable ckrdpixmux Figure 11 Module 6x 8 or 6 x 7 Y 9 top view January 2011 Ultimate User Manual V I 1 Ultimate Construction of the address column of the hit state Each block of 64 pixels gives an address on 6 bits 0 5 added with the address of a group on 4 bits 0 3 The total of the line address includes 10 bits 0 9 Given the critical timing constraints we subdivide the line 960pixels in 2 block of 8 banks x 64 pixels working in parallel with the same constraints in the layout 1 bank 1s inactive To respect this
35. Power Power Power Power LVDS LVDS Power LVDS LVDS Power LVDS LVDS Power LVDS LVDS Power Power Power Power Power Power 72 Pad x y Name 121 12264 35 75 4 end gnd 13564 35 13764 35 JTAG mode state ICUP 140 138 13964 35 75 4 tms I January 2011 Ultimate User Manual Ultimate Description Analogue power ground Readout clock for analogue data digital power Analog marker digital power digital power digital power digital power ground ground Cell _ GND3ALLP140_ VDD3ALLP140_ _ VDD3ALLP140_ _ VDD3ALLP140_ _ AGND3ALLP140 _ AGND3ALLP140 _ AGND3ALLP140 _ AVDD3ALLP140 _ AVDD3ALLP140 _ AVDD3ALLP140 GND3ALLP 140 BT4P140 VDD3ALLP140 GND3ALLP140 GND3ALLP140 Type Power Power Power Power Power Power Power Power Power Power Power 3 state 4 mA Power Power Power Power Power JTAG data output 3 state 4 mA O BT4P140 JTAG data input I ICUP 140 JTAG clock V I ProbePadL 140 ProbePadL 140 ProbePadL 140 ICCK2P140 clockin 73 Pad x y Name Ultimate Description 1167 16939 35 75 4 gnda gnda analogue ground 17039 35 analogue ground 17139 35 Clamping voltage for pixels 17239 35 Clamping voltage for pixels January 2011 Ultimate User Manual V 1 1 Cell Type ProbePadL140 VDD3ALLPI40 Power VDD3ALLPI40 Power
36. SUZE into Ultimate Core analoa l Rowl0 Matrix of Pixels Pixel 0 scanned line pixel 959 Discriminators Synchro matrix Line Cfg registers others controls Cfg registers Synchro Line others controls Synchro test RSTB Sequencer for Analog part Cfg registers others controls Synchro Line Cfg registers 2 E 38 E D Eu 5 Vo c JTAG bus JTAG gt Cfg registers 3 a controller is Test Structure Cfg registers Line address S UZE Synchro Line Synchro frame RSTB gt others controls CLKL __ gt Line address gt Synchro Line gt Synchro frame gt others controls START Cfg registers Synchro frame Figure 2 top view implementation of SUZE in ULTIMATE Output mux This digital part manages sequentially each line for the whole frame composed of 928 lines x 960 columns The main sequencer gives to the structure the address of lines and all synchronizations and controls signals A JTAG controller brings the configuration information Table of configurations registers A test structure simulates a matrix of pixel in order to check the functions of SUZE January 2011 Ultimate User Manual V 1 1 7 Ultimate 1 4 Synoptic of SUZE This digital part includes 3 main parts The Sparse Data Scan SDS
37. Ultimate the patt line0 lt 0 gt is on the left hand side while patt lineO lt 959 gt is on the right hand side 2 7 dis disc register The dis disc register 960 bits large disables the discriminator on a specific column by gating Latch signal and setting the output discriminator at 0 The default value 0 of the dis disc register activates all discriminators Setting a bit to 1 disables the corresponding discriminator In Ultimate the reading of the discriminator is given from left dis disc lt 0 gt to the right dis disc lt 959 gt 0 Lsb 959 Msb dis disc lt 0 gt dis disc lt 959 gt January 2011 Ultimate User Manual V 1 1 29 Ultimate 2 8 pix seq Register The pix seq register 112 bits large contains all parameters to generate readout pixel and discriminator sequence Bits register Purpose Basic configuration value Signal range name Codes name diode clamping 79 64 Sample after clamping 3C00 63 48 Sample before clamping 001C rd 47 32 dlatch Latch state of the 6000 1 latch discriminator pixel After the load of the parameters into the rotate shift register clocked at 80 MHz each result signal from the table outputs from the last D fliflop The cycle lasts 16 times clock excepted for the pwr on 2 9 Monitoringl register The monitoring register 30 bits large gives the setting parameters of the readout controller Basic configuration value Code 29 20 jtg sel rowscan Row to scan fo
38. ate Discriminator test structure Loadscan kscanout_di Scansyncout_disc En_tstdata Ds En Loadscan En Loadscan Clkscan Line bit 959 Shift Register Line bit 512 dataouti disc En Loadscan Cikscan Line bit 511 Shift Register y Figure 27 discriminator test block diagram 3 4 4 6 Timing diagram dataouto disc MKD PADS DO1 Last Frame i 1 po rstframe startframe stariline pao M1 3 ckrdpix5ns scan_load 8 2 1 1 clk80 January 2011 100 ns f 10 MHz Figure 28 Start of scan load and scan clk Ultimate User Manual v 1 1 Current Frame i 51 Ultimate 5 10 15 16 CLKL l I Ti Yaa ma 7 rstline U i Lo 4 INPUT cklatch Epp scan cik CLKL 8 scan_load RE ME 5 10 15 16 rH OUTPUT Of The chip pad clkout pad syncout pad doo lt mo mt sd dm pad doi lt me gt ms gt Scanning timing location Figure 29 Sequence of the line reading The jtg sel rowscan of the monitori Register gives the row address into the frame For both modes the table below shows the following bits of the ro mode2 registers Bit Name Value configuration en scan en aftermuxtst 0 en disc d tst Two modes are defined When en disc autoscan is set to O we select one row defined into jtg sel rowscan 0 to 927 When this mode is s
39. atus half line A 9 states 1 status half line B 9 states S Overflow status For the 9 states group A state 12 8 1000 state 7 0 unchanged Process Keeping of the 9 first hit states January 2011 Figure 13 Module 6 x 9 9 top view Ultimate User Manual V I 1 status line 9 states 18 Ultimate 1 7 Memory management 171 Memory control multiplexer test RAM 1 7 1 1 Introduction This stage bufferizes the data coming from the previous stage before their transmission to outside The management of the memory is a classic one using single access RAM The writing and reading are totally separated The minimum writing cycle time is 25 ns and the reading 100 ns The worst specification of these RAM IP AMS is 5 ns for both read write mode cycle The paths with the worst constraints 75 C 3V amp 2 7V are controlled The relative complexity of the writing mode is dictated by the optimization of the memory depth and the stored data flow variable according to the number of hits by row No possible crash of the reading by the writing operation Only one frame top start information toggles the writing from the reading mode The pipeline of the writing mode minimizes the consumption as lower as possible 160 bits in 200 ns The writing time of the whole matrix is extended at maximum 1 e a frame time operation 185 us minimizing the delay constra
40. clkrate 1 Dualchannel 0 T U Data length0 922 U Data length 922 CLKD Eu C UN Nr SH O IE UE RU UM Ded ze DOO 15 0 31 16 a DO Header Header DELE Diis StatusLine State A Trailer Trailer2 length length J datalengtho 1 word 16 successive bits i datalength1 Figure 23 Format of the output Data of Ultimate Mono Channel and 160 MHz Mode 160 MHz dualchannel clkrate 1 and dualchannel 1 The maximum number of data generated by the suppression of zeros 1s 1850 x 16 bits for each output This overflow implies the truncation of the data frame 0123456789 T E E Frequency ciko 160 MHz cikrate 1 T gt Dualchannel 1 0 lt Data lengtho 1850 0 lt Data length1 1850 Fe 2 ON 1 i CLKD MKD 15 0 Data datalength DOO Headero gt lt Framecpt length Sage gt lt State D State M gg gt lt Trailer 1 gt Data datalength DO1 Header Framecpt State StatusLine lt lt lt E Trailer 2 length 31 16 0 1 j A word 16 successive bits Figure 24 Format of the output data Mode 160 MHz dual channel 47 January
41. e token 2 if this hit state belongs to the same bank as token 2 On the last hit state if no hit exists anymore This process allows the management and recording of three ready states for the next rising edge of the signal enable mux done on next module January 2011 Ultimate User Manual V 1 1 16 Ultimate The picture below illustrates the token s processing according to the synchronization signals rstline ckrdpix Enable_mux January 2011 0 L ee eee ek eee eee Nb states line Y Nb _ states lt 9 e s token 1 i token 2 current irsthit next 1 4th hit state state 2nd hit 5th hit state state token 3 I 3rd hit next 2 6th hit state state 7th hit state 8th hit state 9th hit state Figure 12 token s processing according to the synchronization signal Ultimate User Manual V I 17 1 6 4 Module2x9 gt 9 This component collects the first 9 states from the two module Mux 6x89 Ultimate A state machine fsm initiated by the synchronization line event signal rstline low level active records the 9 states in 3 times latched by the signal enable mux 3 states each rising edge of enable mux signal rst n rstline 3 Enable mux R 1 st
42. eg3 datarega dataregs datareg datareg7 datareg8 o datarego NUZ I19 dataregl0 datareg datareg12 datareg13 datareg14 dataregl5 JTAG mandatory instruction 1 Instruction codes implemented but not the corresponding registers To be fixed in the next version January 2011 Ultimate User Manual V 1 1 24 Ultimate 2 3 JTAG Register Set JTAG registers are implemented with a Capture Shift register and an Update register JTAG standard imposes that the last significant bit of a register 1s downloaded shifted first bits INSTRUCTONREG 2 sus Reger E it a qe patt line0 960 R W Previous value shifted out during write dis disc 1960 R W Previous value shifted out during write patt linel 1960 R W Previous value shifted out during write monitoring 8 R W Previous value shifted out during write NUI NUZ 0 Not implemented For future use ro mode4 8 RW Previous value shifted out during write ro mode3 8 RW l Previous value shifted out during write ro mode 8 RAY Previous value shifted out during write ro model 8 R W Previous value shifted out during write ro mode 8 R W Previous value shifted out during write BYPASS ROnl PO January 2011 Ultimate User Manual V I 1 25 Ultimate 2 4 Instruction Register The test Access Port Controller defined by the IEEE 1149 1 standard includes the
43. egister the pixel matrix is not connected to the discriminators Only one test level Vtest2 is applied to the discriminator input to emulate pixel base line The DAC offers the possibility of adjustment of this voltage The Vtest2 voltage is chosen closed to the VDISREF2 voltage The VDISREFI voltage scan allows performing the transfer function of the discriminator There are 4 DACs corresponding to the four banks of discriminators A B C and D 3 4 4 3 Pixel digital readout calibration During the test mode en disc d tst bit set to 0 in the RO MODE I register the pixels are connected to the discriminators This mode allows obtaining pixel digital readout calibration During one frame one row is processed and the outputs of discriminators are serialized with falling edge of CLKD CLKL 8 and send off chip via DOO and DOI pads The synchronisation marker for digital data outputs on MKD pad and corresponds to first bit serialized The pixel array calibration can be realized in automatic mode when En_disc_autoscan is set to 1 SRO MODE2 Register In this mode the scanning of the pixel array takes 928 frames long One frame per line 3 4 4 4 Synoptic According to the synoptic the scanning of the whole line 960 bits outputs from one shift register of 512 bits and one of 448 wide January 2011 Ultimate User Manual V I 1 50 3 4 4 5 Transfer function of discriminator and pixel digital readout calibration Clkscan Ultim
44. f SUZE are serialized on two output pads and two other signals are provided for the DAQ A clock clkd Two data lines pad doO and pad dol and A marker mkd The serial output has four configuration modes according to 2 registers clkrate and dualchannel see 2 3 12 as shown later All the words 16 bits are read from the LSB to the MSB The different part of the data frame is the Header Frame counter Data Length States Line State and Trailer The 2 words elements ie Header Frame counter Data Length and Trailer are divided into two parts For instance the header includes Header0 corresponds to the 16 bits LSB and header corresponds to the 16 bits MSB The Header the Trailer and the Marker signal could be used together to detect loss of synchronization January 2011 Ultimate User Manual V 1 1 42 Ultimate 3 4 2 2 The Clock The clock is always present even if the data transmission is finished Its rate depends on the cikrate register 160 MHz or 80 MHz 3 4 2 5 Marker The marker mkd is available in all modes The Marker signal set to one during 4 clock s rising edges can also be used to detect the beginning of a data transmission 3 4 2 4 Header trailer The Header and the Trailer composed of 2 x 16 bits headerO headerl trailerO trailerl allow the detection of the beginning and the end of a data transmission respectively The Header and the Trailer are totally configurable by JTAG the header and t
45. ground LVDS ground supply pll clock pll clock LVDS power supply PLL analogue ground pll test voltage test pad pll voltage control test pad PLL Analogue power GND3ALLP140 E AGNDSALLP140 Power LO pad Ivds transmitter140 g padi40 o Ja padiso AVDDSALLP140 Power AGND3ALLPI40 Power APRIOPI40 APRIOPMO AVDDSALLP140 Power January 2011 Ultimate User Manual V I 1 75 Ultimate Pad x Name Description Part UU Cell Type g padt40 analogue ground gpadiso gpadiso analogue test power gpadiso gpadiso analogue driver test out 0 O gpadid0 gpadid analogue driver test out 1 analogue O gpadi40 gpadid analogue driver test out 2 O gpadi4o gpadiso O gpadid0 8588 75 22657 205b 8443 75 22657 analogue driver test out 3 L gpadido analogue driver test out 4 g padi40 gpadi4o analogue driver test out 5 TO a padiao L gpadido analogue driver test out 6 g pad140 Py gpadi4o analogue driver test out 7 LO gpadido January 2011 Ultimate User Manual V I 1 76 Ultimate 4 Glossary abbreviations and acronyms tables Abbreviation f Meaning Description or acronym ad adc ana buf ce clk clp CS ci ctrl cur d dac dig dis disc en etu fifo jtg ld Ivds mk mux pwrs rd ref
46. gth Number trailer Total iss channel of words useful data words of 16 bits TrailerO 924 4 amp Trailerl 922 TrailerO 1852 4 922 amp Headerl Cptframel Datalengthl Trailer D00 HeaderO Cptframe0 DatalengthO 1850 Trailer 1854 2 EP D00 HeaderO Cptframe0 DatalengthO 918 Trailerd 926 2 The figure below describes the format of data send by Ultimate in the one data line mode 0 1 2 3 4 5 6 718 9 10 11 12 13 14 15 CLKD AT gt bo bis HeaderO Figure 20 Detail of the beginning of a data frame January 2011 Ultimate User Manual V I 1 45 Ultimate Mode 80 MHz Mono channel clkrate 0 and dualchannel 0 The maximum number of data generated by the suppression of zeros 1s 459 x 2 x 16 bits for the output This overflow implies the truncation of the data frame This mode 0 giving too little information thus irrelevant can be used as test only 0123456789 44 Frequency cko 80 MHz clkrate 0 T gt IA SEU Dualchannel 0 0 lt Data length0 459 CLKD 0 lt Data length1 459 mo vR RRR 9353 99 HER T RR 6 9 M po tit titi ttt T oe 15 0 31 16 DO1 Header
47. he trailer can be different The Table 1 see 82 3 11 shows the possible Header and Trailer values 3 4 2 5 Frame counter Frame counter is the number of frames since the chip was reset This counter 32 bits is reset to 0 when the maximum is reached FFFFFFFF in hexadecimal and continues to work The JTAG register startframe receives successively to 1 and 0 reinitializing the counter to 0 The Frame counter when separated into 2 words is given in the Data line 0 Frame counter 0 with the LSB s and in the Data line 1 Frame counter 1 the MSB s 3 4 2 6 Data Length Data Length 1s the number of word of 16 bits of the useful data Data Length 1s written on 32 bits In the case of one data line the number of words is repeated 2 times The sum determines the real value of the useful data In the case of no hit during a frame Data Length 0 and Data Length 1 are set to zero 3 4 2 7 Useful data States Line State The useful data is the daisy chain of States Line and States The maximum number of the useful data bits sent during one frame 1s 1850 words of 32 bits 59200 bits In some rare case the number of data generated by the suppression of zeros exceeds the maximum bits capable to be sent thus the data frame will be truncated The data are periodically sent at the beginning of each new frame The number of bits sent between two headers is variable and depends on the numbers of the words recorded during the last frame Each data li
48. hine memorizes the number of written words given by the address writing counter January 2011 Ultimate User Manual V 1 1 21 at each frame Ultimate During the next frame the 2 operations reading writing are swapped and this process is repeated The format of the row states is composed of Status line and State words States Line contains the address of the hit line the number of state for this line 1 e a number between one and nine and an overflow flag State contains the address of the first hit pixel and the number of successive hit pixels 172 Frame counter This frame counter initialized at the reset works from 0 to FFFF_FFFF and restarts from 0 Each occurrence of the falling edge of rstframe increments the counter 32 bits rstframe Counter eu S RESET startframe DL gt 0 hFFFF FFFF 32 LR framecpt The re initialization of the counter is done by setting the register en startframe to 1 and to 0 ro model register January 2011 Ultimate User Manual V I 22 Ultimate 17 3 Serializer and data format This stage formats the data to the output ports and selects the normal working or test mode If en scan 0 please refer to the normal mode data format paragraph 3 5 1 please refer to the test mode paragraph 3 5 3 en Scan x
49. ing sequence for the matrix of pixels and the discriminators The following succinct synoptic illustrates where the signals act during the line in each pixel of the row and one discriminator per column in the matrix The pwr on is activated when the start signal high level is sent to the chip and stays at the high level Pixel i j Discriminator i p aloline j Dis_latch 0 i 927 0 j 959 Figure 39 pixel and discriminator synchronization structure January 2011 Ultimate User Manual V 1 1 61 Ultimate The following picture represents the cycle of one row of 960 pixels That means that 960 pixels are sampled at the same time then 960 discriminators works in parallel at the same time BER UU UYU JU UU U 1 L 1 L 1 IULUUUUUUUUUI Pwr_on 575 Times ck 15 14 13 12 1 10 918 7 161514131211 lol sel_row_int 575 Ll lal al rstline 575 mi MEE Clp 575 m Pwr_on 574 E sel row int 574 Rstline 574 Clp 574 rd je latch calib Line 927 Line 926 200 n Figure 40 the cycle of one row of 960 pixels and discriminators For the whole matrix the schematic below shows the switching applied to the pixel into the row and into the lines January 2011 Ultimate User Manual v 1 1 62 Ultimate GU RES C S 1 OG Pixel o 0 rowO
50. ints technology and layout and the consumption Only the final block shift registers less than 50 flipflops is sampled with 160 MHz frequency 1 7 1 2 Top view diagram The top view diagram or synoptic represents how the architecture is structured around the memory A latch receives the data from the multiplexer stage 9 states status line The memory writing module manages the writing into the memory according to the contents of the data A special sequence is done to optimize the space into the memory critical part of this design for the implementation timing constraints January 2011 Ultimate User Manual V 1 1 19 From MUX 1 status 9 states Test control signals Ultimate Address Data Controls selmempimp Odd S L o OW O 0 Latch Ma pon a Even High 5 g O Initialization Sequence togglemem gt Multiplexer gt Mux test output Test Address Control Memory Reading Address Data In Controls Frame OR RANK swapp 1 2 togglemem Data OUT RANK 0 2048 words x 16 bits RAMT low 2048 words x 16 bits RAM1 high RANK 1 Figure 14 Memory management top view Frame OR RANK swapp 2 2 Reading Data 32 bits togglemem NB The multiplexer test explained later in the test part uses the first
51. l_row_int_ 0 Et pur on I 0 LRA mk_g_linemarker Line 1 G O C 6 86 O E lastrow Line 0 ES pwr on 927 Es sel row in i27 fe ee EE E clp I 827 ai Line 927 if Line 326 E pwt on 1 926 0 Fe se row int see Po 0 pem Es clp 1926 M Line 925 Lo ES pur on 1925 0 Line 925 fe sel row int I 825 gt cip I 825 Figure 44 timing diagram after the start matrix of pixels and discriminators others successive frames January 2011 Ultimate User Manual V I 1 66 Ultimate 3 6 2 Disable discriminator output sequence The ASIC offers the possibility to disable one or several discriminators outputs by a configurable register of 960 bits Cf 2 7 dis_disc register The change can be done each new JTAG and start sequence 3 6 3 Analog discriminators sequence test This block is only used for test and calibration Cf annex 2 18 RO MODEO Register January 2011 Ultimate User Manual V I 1 67 Ultimate 3 7 Main Signal Specifications Parameter Typical Notes Value RSTB Pulse Active Low Asynchronous Power on Reset Width TCK Frequency 10 MHz Boundary Scan Clock JTAG TMS Setup Hold 10 ns Boundary Scan Control Signal Time TDI Setup Hold 10 ns Boundary Scan Serial Data In Time READOUT CKRD Frequency Up to 160 Readout Clock LVDS signal MHz CKRD Duty Cycle SYNC Setup Hold 5 ns DS O initialisation CMOS signal Starts after fa
52. lines A block below will distribute them for each line independently Cf Pixel and discriminator read out sequence synchronization For the configuration registers see Spix seq Register e ICE CY GP PC 8 NE KE ox BOK 4K EBD E Fi o Mense p latch AA H Q D o 200 ns Figure 37 Simulation timing diagram for the pixel part Related timing with f 1x 80 MHz rd calib latch signals are used by the column readout circuitry 3 5 6 Line synchronization for suze The picture below resumes the synchronization signals used for all suze part output of the discriminator sds mux and memory management for each line clk 80MHz E EE APS LERI CEEI ERES CELS EF GG EFE atm Latch for output of the discriminator latch rstline ckrdpix ckmemlatch rstpix cklatch AIJE L rstline ckrdpixmux l l l l l l l l Synchronization signals used for Memory management ckrdpix5ns L re L cklatch E ST LA Au o mm remem eee E mm HI rstframe startframe startline
53. lling edge on Irst CKRD sampling January 2011 Ultimate User Manual V I 1 68 Ultimate 3 8 Pad Ring The pad ring of Ultimate is built with Pads full custom designed with analogue signals and power supplies Pads from the AMS library for the digital signals and power supplies Analog Outputs it M 2m SE Es P C84 Cx EM cc Ua ici iol 960 Discriminators N i ES DACS JA MTT didnt TT NN E TIM Mani TT fe He iai mt rpm mu S YOT gg i mu Fail A a mej p p Saa o gg January 2011 Ultimate User Manual V I 1 69 Ultimate 3 9 Pad List UO UO UO UO 6 56435 75 4 gnda probe analogue ground 8 76435 754 vada probe Analoguepower 9 s6435 754 vdda Analoguepower _ VO APRIOPI40 ProbePadLI4O vo APRIOPI ProbePadLI4O O APRIOP140 VO APRIOPI40 1964 35 Analogue power AVDD3ALLP140 2064 35 Analogue power AVDD3ALLP140 2164 35 Analogue power AVDD3ALLP140 2264 35 analogue ground AGND3ALLP140 2364 35 analogue ground AGND3ALLP140 2464 35 Clamping voltage for pixels DirectPad 140 2564 35 Clamping voltage for pixels DirectPad 140 2664 35 Analogue power AVDD3ALLP140 2764 35 Analogue power AVDD3ALLP140 2864 35 Analogue power AVDD3ALLP140 2964 35 analogue ground AGND3ALLP140 January 2011 Ultimate User Manual V I 1 70 Ultimate Pad x ly Name Description Part VO Cel Type 41
54. llowing steps describe how to operate Ultimate 3 1 Reset initialization 31 1 Introduction The asynchronous reset rstb power reset controls all the parts of chip including the configuration slow control by JTAG A start signal independently of this signal generates an internal synchronous reset without modifying the configuration No slow control reset 3 1 2 Sequence The sequence is the following one a Power supply switch on Vdd b power reset signal coming asynchronous reset c supply of the clock clk cmos or clk Ivds g internal synchronous reset generation 90 Vdd tus min n Vdd Power reset rstb AN internal_rst A start clocks Il Figure 18 timing diagram of the reset sequence 3 2 After reset On RSTB active low signal e All BIAS registers are set to the default value 1 e O dis disc is set to 0 i e all columns are selected ro mode0 ro model ro mode2 ro mode3 ro mode4 are set to O pix seq is set to 0 pix seq is set to 0 seq suze 1s set to 0 header trailer is set to 0 patt lineO is set to O patt linel is set to O monitoringl and monitoring2 are set to 0 JTAG state machine is in the Test Logic Reset state JTAGID CODE instruction is selected January 2011 Ultimate User Manual V I 1 39 Ultimate Then the initial sequence controls the load of the bias register and all the previously quoted registers are set in the running conditions According to the settings the readout can be
55. nes have the same number of bits Consequently Data Length O and Data Length 1 are the same States Line and State have exactly the same meaning whatever the selected mode The number of words sent in a data frame depends of the number of hits If the number of words for the two data lines is even the last Status of Data line 1 is false This operating way allows having the same number of bits Data length in the both DOO and DOI in every case This false Status can be detect by the last Status Line because the number of State sent 1s one more than the Status Line expected January 2011 Ultimate User Manual V I 1 43 Ultimate States Line contains the address of the hit line and the number of State for this line between one and nine and an overflow flag The following table describes the signification of the bits in Status Line word Status line Statusi line II 0 1 2 3 4 15161718 9101213 14 15 BO Bit 0 9 Not The address of the line used Table 2 Description of States line word State contains the address of the first hit pixel and the number of successive hit pixels as shown on the table below 0 8 AMA 15 of hit pixels the address of the column not used Table 3 Description of State word January 2011 Ultimate User Manual V I 1 44 Ultimate The table below resumes the maximum length of the output frame according to the selected mode Clk Dual Config Out Header Cptframe Datalen
56. performed either in normal mode or in test mode 3 3 Setting the bias gen register The BIAS GEN register must be loaded before operating Ultimate For biasing the Ultimate chip there are 18 DACS building vvith the same current mode 8 bits DAC 1 uA of resolution and 1 specific 4 bits DAC for setting the pixel clamping voltage Interfaces as current mirrors for current sourcing or sinking resistors or current voltage converter circuit customize each bias output The following table shows the downloaded codes which set the nominal bias Internal DAC IVDISREF1D s From 32 up to 32 mV 1 IAnaBUF From 0 up to 255 LA IVTEST2 From 1 up to 1 5 V From 0 up to 255 LA From 0 up to 255 LA From 0 up to 255 LA 1 Referenced with respect to IVDREF2 The threshold voltage of the discriminators AVth is defined as Vrefl Vref2 Vrefl Vref2 AVth January 2011 Ultimate User Manual V I 1 40 January 2011 v_disc_refiD VDiscriRef1 Ultimate v tst 5 v_tst2 V disc ref1A v disc rei B v disc refIC VDiscriRef1 lt l lt DIO 0 IN og DJ 2 0 ololwm gt v disc rei vDiscriRef2A VDiscriRef2B VDiscriRef2C VDiscriRef2D v_disc_clp VDiscriClp i pwrs bias LL TTT i Ivds rx Figure 19 Bias synthetic bank diagram Ultimate User Manual V 1 41 Ultimate 3 4 Analogue and digital Data Format 34 1 Main Introduction The analogue outputs dedicated fo
57. possible Header and Trailer for mode 0 and 1 to ensure unicity or mode 2 with 32 bits January 2011 Ultimate User Manual V I 1 33 Ultimate 2 13 Monitor 2 Register The Monitor2 register 8 bits large allows setting parameters of the test pads Basic configuration value Codes 7 4 sel tstpadl Selection of the synchronization signal on test pad Pl Sel tstpad2 Selection of the synchronization signal on test pad2 The internal follovving signals can be selected vvith SelPadl and SelPad2 4 bits Cig multiplexors configuration This configuration register selects the output signals on the external pads The follovving tables describe the different capabilities SelPadl TstiPad Purpose MK Test D Digital marker corresponding to last serialized digital data It depends of RowMkd selection parameter Same signal as PwOn but shifted of 16 main clock Activate power supply for pixel Connect pixel output to common column Analogue marker is shifted of 80 ns to MK A signal This signal rises up at the beginning of the reading phase and falls down at the end of Calib phase It depends of RowMka selection parameter depends of RowMka selection parameter depends of RowMka selection parameter ckdivx2 Clock divided by 2 mk a Analogue marker corresponding to readout pixel sequence It depends of RowMka selection parameter latch Latch state of the discriminator vdd January 2011 Ultimate User Manual V I 1 34 Ultima
58. r test 928 Normal mode the number of row decimal matrix is 928 for digital marker matrix during the readout for analogue marker matrix during the readout January 2011 Ultimate User Manual V I 1 30 Ultimate 2 10 patt_linel Register The patt_linel register 960 bits large emulates discriminators outputs rows in en_linemarker and en patt only modes When en patt only is active the values stored in the pixel matrix are ignored and the value of patt linel is sent to the discriminators outputs This is a test mode vyhich emulates the digital pixel response with the contents programmed into the patt_lineO register in order to verify the digital processing The pattern is alternated vvith the contents of the patt linel In the en linemarker mode it adds two rows at the end of matrix for a readout chip and the patt linel register is read to emulate the discriminators outputs of these two supplementary rows Bit register Purpose Basic configuration value Codejs range name 0 959 patt linel Emulate 5555 555555 discriminators rows 1 Example of pattern used in simulation In Ultimate the patt linel lt 0 gt is on the left hand side while patt linel lt 959 gt is on the right hand side With patt linel together these two signals will form the elements of the simulated frame given to SUZE part 0 1151 k H Row 0 Row 1 x times Row 927 Figure 16 Generation of the test frame pattern January 20
59. r test purpose offer two kinds of output signals e pixel signals e synchronization signals For digital outputs the IC generates two types of signals e digital pixel signal after zero suppression processing e test discriminator and test zero suppression logic K Digital pixel signal by discriminator K Test pattern used by zero suppression logic reading the LINEPAT REG register Ultimate uses the pads at the bottom edge for all its operations whatever is collecting data from the pixels using the pixels and the discriminators or in test mode reproducing at the outputs the pre programmed patterns All the digital signals to synchronize and programming the chip are necessary to operate successfully Analog outputs located on the top edge of the chip are not used for the normal operations The main purpose is to characterize the pixels or to check the dead pixels Therefore measurements on these pads deal with normal pixel signals as well as test signals but they still require the synchronization and the markers and it is activated on demand by setting to 1 the en ana tst bit in the RO MODE I register 34 2 Normal mode data format 3 4 2 1 Introduction This chip includes the main features of Mimosa 26 The inputs are the main clock the reset and an input synchronization signal START for initializing the readout control The sparsified output data of the previous frame are sent during the acquisition of the current frame The data o
60. rations inside the line and for the whole frame It produces also the line address counter In running mode it reaches maximum 928 lines the boundary scan chain for testing the main input and output pads the memory management sequencing the writing and reading operation the ram 4 memories of 2048 x 16 bits additional test structure acting as a probe for each block Digital Supplies Analog Supplies Logical scan pix array Columns Imi Bankl4 AnaDriver lt 7 0 gt R Banko SO S14 Column 63 c E 2 O Column 63 Column 0 K c E 2 O O Pixel Array 928x960 Multiplexer Row Pix 927 Rows Rows Address Register lt 0 927 gt Column 63 A V discri ref v tests Sparse Data Scan algorithm SDS SDS 0 SDS 1 N states N states Current Reference Bias Generators 19 registers ro modeO pix seq monitoring1 Regulator ro mode1 idcoge suze_seq monitoring2 ro mode2 SRAM SRAM ro mode3 Header trailer 2048x16 2048x16 Temp JTAG Controller ro_mode4 Bus PLL temp probe ReadOut Controller JTAG Bus Clocksin x Test pads Digital outputs PLL in out s spea Ctrl Pixel t Discri Figure Ultimate functional view January 2011 Ultimate User Manual V 1 1 6 Ultimate 1 3 Ultimate main synoptic The following synoptic shows the implementation of
61. ream is output on both data line 0 and 1 The data are sampled by the The data stream is output on frequency output clock 160 data line 1 only Data line 0 stay to low level The data stream is output on both data line 0 and 1 January 2011 Ultimate User Manual V I 1 36 Ultimate 2 16 RO_MODE2 Register Bit Register name Purpose Rst Basic configuration range status value T en tstpad Enable the pad test To Jo _________ 6 en disc line enable the line discriminator O0 0 Gating clock mode ON Off o Jo 4 j Neued o do 3 en aftermuxtst Enable mode scan test for multiplexer of suze en disc d tst Enable mode scan test discriminators JO 0 Enable mode scan test o jo S en disc autoscan Enable mode scan test discriminators all matrix 2 17 RO MODEI Register The RO MODE registers 8 bits large allow selecting specific analogue mode of the chip Bit Bit Name Purpose Rst Basic configuration range Status value Reinitializes the frame counterto0 0 0 en ana tst Enable the 8 columns at right of the matrix for the analog outputs en anadriver scan Enable scan pixel mode dis bufref Disable the reference buffers Oo Jo Use the PLL clock as main clock o Jo J Enable the power pulse amplifier o O0 mode O len disc tst Enable the discriminator test mode 10 0 January 2011 Ultimate User Manual V I 1 37 Ultimate 2 18 RO MODEO Register The RO MODE
62. symmetry little craftiness consists of adding the value 512 8 x 64 to the column address for each state inside the module states multiplexer 6x8 9 Systematically the next module mux 9 x 2 to 9 will correct the address column of each calculated state coming from the first bank Mux 6x8 9 by the removal of 512 Column address pixel address into the block address of the block Calculation of the number of states hit per half line A function totals up all the number of state per bank given by the previous stage SDS If the total exceeds 9 the result will keep this value and the overflow flag will print 1 The equation below resumes the calculation Selection of the 9 states inside the module Mux 6x8 9 First between each rising edge of ckrdpix signal three successive token identifies each one asynchronously the position of the next hit state according to a pyramidal structure from the left significant position of the pixel position 0 of the column to the most significant position position 512 Token 1 it points at the first state hit not taken in account before whatever the location inner and inter bank from column 0 to 959 Token 2 it locates the fourth hit state following the token 1 if this state 1s included into the same bank of the cursor 1 The third or second hit state if the state belongs to another bank of the token 1 On the last hit state if no hit happens Token 3 it points at the third hit state following th
63. tarted at each frame the selected row 1s scanned the readout process 1s continuous To change the row address we define other scan line into jtg sel rowscan and generate a new START signal When en disc autoscan is set to 1 we select the row automatic scanning from line O to 927 and the process stops when last row is scanned see the Figure below but line O and line 511 are not START Frame frame 7 Frame i i i duration NE Frame927 duration O duration 1 i i rame rame i rame 927 i i i pad eel poe T T I U DatadiscriRow0 DatadiscriRow1 l Data discri Row 511 DatadiscriRowO Data discri Row 1 Data discri Row 511 Qi gt A eaa i l 512 l 512 i i 512 y 512 512 512 i jedge of CLKD j edge of CLKD i j j edge of CLKD edge of CLKD edge of CLKD edge of CLKD i Q gt K yK lt _ _ gt I pad_do0 1 SERRA SRR PS T T T I I i I 960 edge of CLKD l 960 edge of CLKD i 960 edge of QLKD b 960 edge of CLKD 960 edge of CLKD 1 960 edge of QLKD i kie A I i i I I n I 1 I Data discri Row 512 Data discri Rbw 513 I 1 y Data discri Row 512 Data discri Row 513 pad clkout E Wl LET TU Figure 30 scanning automatic test of the Data discriminator
64. te SelPad2 Tst2Pad Purpose 0 cklatch jcfsuzeseq o cf suze seq 6 latch GT suze seg 7 clkdiv8 Man Clock devidedbyl 8 seine fer suze_seq 000000000 rstline i suze seg 13 sti SO 14 jsynmx jj IS ESS S Figure 17 Cfg multiplexors configuration January 2011 Ultimate User Manual V I 1 35 Ultimate 2 14 RO MODE4 Register Bit range register Name Purpose Rst status configuration value I Not used 6 dis pstart 1 Disable the start pad o 0 5 dis pspeak disable the speak pad 0 10 4 dis ppll Disable the pllpad jo TO dis pdol Disable the DI pad 10 10 2 dispdoo DisabletheDlpad 0 1 dis mkd Disable the markerpad 0 0 0 dis pelkd Disable the clkd pad jo 70 2 15 RO MODE Register Bit range Register name Purpose Rst configuration status value 7 en anamux sel 0 Select the group of discriminators for the reference voltages A B C or D IDEM 3 Enable the analog multiplexor 4 en rd delay Enable the delay for reading 6 1 o To S LS 0 jl S EE GEN 0 Jl S 3 dis vclppix Disable the internal clamping voltage RN DO E e 0 RAV ie ES configuration AR Lu outputs channel or in one channel dualchannelout Determines the data stream on the l CE To Data stream output The data are sampled by the The data stream is output on frequency output clock 80 data line 1 only Data line 0 stay to low level The data st
65. ted readout and inside the data some specifics words give also synchronization markers to begin and start the readout The chip offers the choice of the output bit rate of the communication 160 or 80 Mbits second The configuration by JTAG protocol allows the programming of the test the masking and the control of the discriminator A self in built test 1s included in the chip for debug of all main digital parts see Figure 1 Ultimate functional view 1 2 Architecture description The core digital includes two main parts called ult manager and suze The first part ult manager contains the jtag controller treating the configuration registers for the matrix readout both analog and digital part for testability the command of the possibility to disable the discriminators the pixel sequence read out block managing the sampling of the pixel the matrix analog readout sequence the mode selection for suze input the user choices the readout of the analog matrix the virtual matrix generated by the repetition of 2 lines pattern given or the synchronization test frame The second part suze contains the sparse data scan sds extracting by block up to 6 hits for the line up to 6 x15 the second stage the mux6x15 to 9 retains 9 states from the previous one January 2011 Ultimate User Manual V 1 1 5 Ultimate the main sequencer a key component of the chip generates all the synchronization signals for the line the ope
66. ultiplex is disabled en anamux 0 January 2011 Ultimate User Manual V 1 1 2 Ultimate en anamux sel 1 en anamux sel Oj group en anamux sel 1 en anamux sel 0 en anamux v disc refla bu v disc ref2a bu IPAD v disc refi v disc _reflb buf v disc ref2b bu v disc ref2 v disc refic bu v disc ref2c buf v disc refid buf v disc ref2d bu 3 The voltage v disc clp is bufferized and output on the pad named v disc clp January 2011 Ultimate User Manual V 1 1 28 Ultimate 2 6 patt_lineO register This register patt line0 960 bits large emulates discriminators outputs Two registers control the using of the content of this register en patt only and en_linemarker Mithen patt only active high level the pixel matrix is ignored and replaced by a virtual matrix constituted only of patt line0 and patt_linel This test mode emulates the digital pixel response with the contents of the patt lineO register in order to verify the digital processing The pattern alternates the contents of the patt line0 and patt linel In the en linemarker mode it adds two rows at the end of matrix for a readout chip The patt lineO register 1s read to emulate the discriminators outputs of these two supplementary rows The initialisation phase reset presets this register to 0 Bits register Purpose Basic configuration value Codes range name 0 959 AAA 1 Example of pattern used in simulation In

Ultimate User Manual - IPHC

Contents

Download Pdf Manuals

Related Search

Related Contents