User Manual for Virtex-6 XMC card
Contents
1. A connected to the front panel 3V daughter card front Panel UO daughter card 5V 1A Front Panel IO daughter card 3V3 3A Front Panel IO daughter card 12V 1A Front Panel IO daughter card 12V 1A MGT power supply 1 0V 1 2V 2 5V 2 0A 2 5A 0 01A respectively Table 13 Power supply Optionally the FM680 can be used as a stand alone module and is powered via the external power connector 5v to 1vO 12v to 5v0 EN5396QI LTC3605 El ve 5A p gt lout 6A V5 1A 1v0 gt 5v to 1vO EN5396QI I T FET SVO XMC L V6 9 5A VPWR V 1A 5V 12V 5 BLAST voltage 5 m e124 ENABLE 1v5 1v8 O 5A e CONTROL 5v to 1v8 EN5395QI MGT 2 5A BLAST 5A 1v8 to 1v5 TPS74401 5V to 0v9 TPS54972 0v9 ddr term 97A 5V 3v3 to 2v5 TPS74401 MGT Q 1 VADJ 3A 3v3 XMC 3v3 Q8A 3v3 to 1v2 EN5395QI 1V2 MGT 2A 1v2 to 1v0 ivo TPS74401 XMC 12v Figure 12 Power supply An ADT7411 device is used to monitor the power on the different voltage rails as well as the temperature The ADT7411 data are constantly passed to the Virtex 6 device Measurements can be accessed from the host computer via the PCI bus A software utility delivered with the board allows the monitoring of the voltage on the 2 5V 1 8V2. 1 2V 1 0V and 0 9V rails It also displays both FPGAs junction temperature 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 21 FM680 User Manual S r va 4 1 External power connector for stand alone mode An external power connector J2 is available on side 2 of the PMC next to the PMC connectors It is used to power the board when it is in stand alone mode This is a right angled connector and it will be mounted on board only if the card is ordered as a stand alone version FM680 SA The height and placement of this connector on the PCB breaches the PMC specifications and the module should not be used in an enclosed chassis compliant to PMC specifications if the external power connector is present on board Do not connect an external power source to J2 if the board is powered via the PMC connectors Doing so will result in damaging the board The external power connector is of type Molex 43045 1021 Each circuit can carry a maximum current of 5A The connector pin assignment is as follows Pin Signal Signal Pin 1 3 8V 3 3V 2 3 5V 5V 4 5 GND GND 6 7 9 GND GND 8 12V 12V 10 Table 14 External power connector pin assignment WARNING UNREGULATED UNPROTECTED EXTERNAL POWER SUPPLY CONNECTION This board is designed with an UNSUPPORTED feature for an external power connector labe
3. 3 7 External E PENES SET 11 3 7 1 Front Panel daughter a 11 3 7 2 Power connection to the front panel I O daughter card 15 3 7 8 Front Panel optical transceivers renn 15 3 7 4 8channels rocket IO on QTE connectors ANEN 15 Ob Cu eet 15 20 IR discat ctetu rod ee eM dtu 16 3 9 FPGA configuration UE 17 SO e GE EE 17 de GEES 17 399 JTAG 19 3 10 Pla EM 19 4 Power requirements rennen rnnt tnn rna cesses resen enesenn BARRE asi sacadas 20 4 1 External power connector for stand alone mode 22 Xuan 1 23 EMI y s lt 1 P T em 23 5 2 Convection Cooling Meet 23 5 3 Conduction un ai oo 23 6 Safety ee ee E eege ee 23 7 EMC 23 8 K lt 0 Te 1 E IT T m 24 MEE e AE 24 DER C lCcnufme e ees eens cies ene 24 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 3 FM680 User Manual S r va Acronyms and related documents 1 1 Acronyms ADC DAC DCI DSP EPROM FBGA FPDP FPGA JTAG LED LVTTL LVDS LSB LVDS MGT MSB PCB PCI PCl e PLL PMC SDRAM Analog to Digital Converter Digital to Analog Converter Digitally Controlled Impedance Double Data Rate Digital Signal Processing Erasable Programmable Read Only Memory Fine
4. Board Level Advanced Scalable Technology is a small PCB module that allows customization of the FM680 in memory extensions processing units and communication interfaces For more information about the available BLASTs on the FM680 please consult the following page BLAST modules http www 4dsp com BLAST htm 2 Installation 2 1 Requirements and handling instructions e he FM680 must be installed on a motherboard compliant to the VITA 42 3 standard e Do not flex the board e Observe ESD precautions when handling the board to prevent electrostatic discharges e Do not install the FM680 while the motherboard is powered up 2 2 Firmware and software Drivers API libraries and a program example working in combination with a pre programmed firmware for both FPGAs are provided The FM680 is delivered with an interface to the Xilinx PCl e endpoint core in the Virtex 5 device as well as an example VHDL design in the Virtex 6 device so users can start performing high bandwidth data transfers over the PCI bus right out of the box For more information about software installation and FPGA firmware please refer the 4FM Get Started Guide 3 Design 3 4 FPGA devices The Virtex 5 and Virtex 6 FPGA devices interface to the various resources on the FM680 as shown on Figure 1 They also interconnect to each other via 58 general purpose pins including 4 clock pins 2 pairs one in each direction 1000 terminated A 16 bits single ended bus is also av
5. amo faso rexes Le Nas LJ Loes juo fm rensa Pss LA Jee Le Lu mx Ds EM eo Lee os Lus rep em nes Jam us Le Leg 7000 Blus Lem Jm Le rae e em aco Joe le Table 7 Front Panel IO daughter card pin assignment Bank C 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 14 FM680 User Manual S r va 3 7 2 Power connection to the front panel UO daughter card The Front Panel I O daughter card on side 1 of the PCB is powered via a 7 pin connector of type BKS Samtec Each pin can carry up to 1 5A The power connectors pin assignment is as follows Pin Signal Signal Pin 1 3 3V 3 3V 2 3 5V GND 4 5 12V GND 6 7 12V Table 8 Daughter card power connector pin assignment on PMC side 1 3 7 3 Front Panel optical transceivers Special build option and not in combination with the front panel daughter card or EMCORE Four 2 5 GB s optical transceivers LTP ST11M are available on the FM680 in the front panel area They are connected to the MGT l Os of the Virtex 6 Infiniband protocols as well as Gigabit Ethernet and Fibre channel SFPDP can be implemented over the transceivers Lower rate optical transceivers 2 125 GB s and 1 0625 GB s are available in the same form factor 3 7 4 8channels rocket IO on QTE connectors This is a special build option and not in combination with the optical
6. est distribue par AY www techway ir into otechway tr 3 1 64 53 3 90 FM680 User Manual August 2010 www 4dsp com 11 FM680 User Manual DET V1 4 FP va N13 FP N3 10 Exerc umma ieee ome Ca pem ma CPT Ls ew o ss rons ve e pen e Wale oe o en 52 MENOS Ja e mw ee os me ls Eet EE a Gs rere o PTR fy rw o des rene eo Jee o Backes s rere we ads reps ss reve we ve re oe DEE E far pers po js oen oe fo reus Ier Mo s oo pee pe eee pem Le rera o WI Trees ow Ls reve en por roms os EE CO il fo renes ve fio rep on ER ESSA Pe umd EG O rss freee GH reps oe sr reve o on rows pec ee pem Table 5 Front Panel IO daughter card pin assignment Bank A Connected to a global clock pin on the FPGA LVDS output not supported Connected to a regional clock pin on the FPGA LVDS output not supported 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 August 2010 FM680 User Manual www 4dsp com 12 FM680 User Manual S r va Connector FPGA FPGA Connector pin Signal Name pin pin Signal name pin f men oo Eire eem Jo e mm rs Bee ene e ER COME fer ferem eo MEN Lo Jo e ms ov eee Joie la c e Tee e m eea re en rens Ds mee er CHECA Cette E E o irem o o rem Jo a ms Dm ee rem en A CM EA es reece 82 e e Jo e mw m es enm oo
7. Pis LP so Pn jose quis NT Jegen e1 Ligen ne fns femi co png tose ns N Ion Table 2 Pn4 pin assignment R16 TT R16 P18 Pn4 1055 15 E mo Pn jo4o Jr T4 Leo Ju joo 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 9 FM680 User Manual S r va 3 5 Serial FLASH A 128 Mbits serial flash device S25FL128P will be available to the Virtex 6 device This flash allows the storage of vital data like processor boot code and settings into a non volatile memory The flash is operated using a standard SPI interface that can run up to 104 MHz allowing for a page programming speed up to 208 KB s Reading data from the flash can be done at speeds up to 13 MB s The SPI programming pins will be connected to a bank that supports 1V8 whereas the serial flash will be operating at 3V3 This will not cause problems for the signals from the Virtex 6 to the flash device but the signal from the flash device to the Virtex 6 will have to pass through a level translator SN74AVCAT245 3 6 BLAST sites Thanks to the availability of 5 BLAST sites a wide variety of memory and processing modules can be connected to the Virtex 6 device For each BLAST site it is possible to choose from the list of available BLAST modules For more information about the available BLASTs on the FM680 please consult the following page BLAST
8. achieved via the JTAG chain 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 17 FM680 User Manual S r va 3 9 2 1 DIP Switch A switch J1 is located next to the JTAG programming connector J6 see Figure 8 The switch positions are defined as follows Figure 8 switch J1 location Sw1 OFF Default setting The Virtex 5 device configuration is loaded from the flash at power up ON Virtex 5 device safety configuration loaded from the flash at power up To be used only if the Virtex 5 device cannot be configured or does not perform properly with the switch in the OFF position Sw2 Reserved Sw3 Reserved Sw4 Reserved Table 10 Switch description 3 9 2 2 LED and board status Four LEDs connect to the CPLD and give information about the board status LED 0 Flashing FPGA A or B bit stream or user ROM register is currently being written to the flash ON FPGA A not configured OFF FPGA A configured LED 1 Flashing FPGA A or B bit stream or user ROM register is currently being written to the flash ON FPGA B not configured OFF FPGA B configured LED 2 Flashing The Virtex 5 device has been configured with the safety configuration bit stream programmed in the flash at factory Please write a valid Virtex 5 device bit stream to the flash ON Flash is busy writin
9. device is partly used to store the configuration for both FPGAs In the default CPLD firmware configuration the Virtex 5 device and the Virtex 6 device are directly configured from flash if a valid bit stream is stored in the flash for each FPGA The flash is pre programmed in factory with the default firmware example for both FPGAs JTAG Header Virtex 6 S29GL512M 512Mbit Flash 8 bit parallel configuration CoolRunner ll CPLD XC2C256 CP132 Virtex 5 DIP switch Figure 7 Configuration circuit 3 9 2 CPLD device As shown on Figure 7 a Cool Runner ll CPLD is present on board to interface between the flash device and the FPGA devices The CPLD is used to program and read the flash The data stored in the flash is transferred from the host motherboard via the PCl express bus to the Virtex 5 device and then to the CPLD that writes the required bit stream to the storage device A 31 25 MHz clock connects to the CPLD and is used to generate the configuration clock sent to the FPGA devices At power up if the CPLD detects that an FPGA configuration bit stream is stored in the flash for both FPGA devices it will start programming the devices in SelecMap mode Do NOT reprogram the CPLD without 4DSP s approval The CPLD configuration is achieved by loading with a Xilinx download cable a bit stream from a host computer via the JTAG connector The FPGA devices configuration can also be
10. modules http www 4dsp com BLAST htm Table 3 BLAST Configuration Options BLAST 3 SITE 1 2 3 4 5 es YES YES YES YES YES Single Extended YES YES YES YES YES BLAST Double BLAST Double Extended YES YES YES YES BLAST 1 Single and double extended BLAST placed in BLAST sites 4 and 5 will protrude 3mm from edge of the board 2 BLAST SITES 1 and 2 4 and 5 are paired when using double BLAST 3 Only available on XC6VLX550T and SX475T FPGA devices YES YES YES YES 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 10 FM680 User Manual S r va Table 4 BLAST Memory Processing Options BLAST 1 SITE 1 2 3 4 5 DDR3 YES YES YES YES NO DDR2 YES YES YES YES NO QDR YES YES YES YES YES ADV212 JPEG2000 YES YES YES YES YES 32GB NAND YES YES YES YES YES FLASH 1 Only available on XC6VLX550T and SX475T FPGA devices Due to its small form factor and ease of design the BLAST modules enable a rapid solution for custom memory or processing requirements 3 7 External IO interfaces The Virtex 6 device interfaces to the front panel daughter card on the FM680 via a high speed connector 174 I Os are available from the FPGA to from the daughter card that can be mounted in the IO area defined by the XMC standard Figure depicts the mechanical set up
11. pomme ED e em IS Bas res je a eo e oe eee oe hs xe c pe MON Tee e e mem m CHEM e Jee uo Ml n ne Je Ge ee Le fere om ls Lo Je Le Je Le e Iwer Je be xw pe Beste be oo reps uz EN ansa ENS Iess Lr pm cem Em nm e sme O Jos m pco a Lu exe JS O Table 6 Front Panel IO daughter card pin assignment Bank B Connected to a global clock pin on the FPGA LVDS output not supported Connected to a regional clock pin on the FPGA LVDS output not supported 9 Vbatt is connected to both Virtex 5 devices Vbatt pin 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 18 FM680 User Manual wp C V1 4 Connector Signal Signal Connector pin Name FPGA pin FPGA pin name pin La ree t Bil mm no Lm mw ose Biz rem e La rx 59 CTT Le mee 555 Biz fere us Lm remo 9 Blo fio La exe es CET Lm ee Seat Les mme o Biz low s Ds mx EMBAER 139 repas t9 Jes Leem no ir renas Im Le Ten i us Lea LP Lee ia ws repas ase Le Ion is wr reas B36 LA ep as us us rexe Ke Le reouo iso as reper H30 es repe le ass re 30 Le remo iso 155 Jrpxso Lamm LJ rexer Le asz mem lm Le reso iss aso rene 097 F9 Lee wo fet rex Juizo Ewe Love tee ws reps T9 Jasse reps Le ws eens Im La Low ie e Le
12. the FPGA The endpoint will support a 4 lane PCl express bus The following performances have been recorded with the FM680 transferring data on the bus gt PCle 1 lane 180Mbytes s sustained gt PCle 4 lanes 600Mbytes s sustained A PCI express switch will be used to optionally route the 4 lanes from the P15 connector to the Virtex 6 device The remaining 4 transceiver lanes on the P15 connector will be routed to the Virtex 6 device as well Furthermore the VITA 42 3 standard defines an optional P16 connector which can carry an additional 8 lanes of PCl express All these lanes are routed to the Virtex 6 device directly An overview of the PCl express subsystem is shown in Figure 3 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 7 FM680 User Manual DE V1 4 Virtex 5 PCle Mux FPGA A pa gt pa XMC Pn5 Le gt PEROp 0 gt ra PETOpO La PEROp 1 gt PETOp1 la PEROp 2 PETOp2 pet LL Virtex 6 PEROp 3 lt FPGA B PETOp3 la po l j RefCLK CLK buffer l j eg pi l PEROp 4 gt PETOp4 La PEROp 5 PETOp5 la PERO
13. FM680 User Manual S r va FM680 User Manual for Virtex 6 XMC card Contact www techway fr 4DSP LLC 955 S Virginia Street Suite 214 Reno NV 89502 USA 4DSP BV Ondernemingsweg 66f 2404 HN Alphen a d Rijn Netherlands Email support 4dsp com This document is the property of 4DSP and may not be copied nor communicated to a third party without the written permission of 4DSP 4DSP 2010 FM680 User Manual S r va Revision History ie in rn December First release 1 0 15 2009 January 20 Minor modifications 1 1 2010 April 23 Corrected typos 1 2 2010 August 16 Corrected typos 1 3 2010 August 17 Added image 10 for the JTAG connector location 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 2 FM680 User Manual a r va Table of Contents ti ACIONYME T 4 1 2 Related DOW sa a SSI ead a Sa 4 1 3 General courier die eia densidade as Ud ada e ag ia ni B MEM SC cou Ee 6 2 1 Requirements and handling instructions EEN 6 2 2 Firmware and software AN 6 ek s e a A 6 gt DR a E lt lt e 6 3 1 1 Virtex 5 device family and package serenas 6 3 1 2 Virtex 6 device family and package rrenan 6 PGA A TT 6 3 3 PCl express architecture ek 7 34 Prn4userl O connector sese 9 5 f FLASH Er EE 10 WEE ip c P 10
14. TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 24
15. ailable between the two FPGA devices for communication with the Pn4 bus or general purpose communication 3 1 1 Virtex 5 device family and package The Virtex 5 device is from the Virtex 5 LX family It can be either an XC5VLX2OT or XC5VLX30T in a Fineline Ball Grid array with 323 balls FF323 3 1 2 Virtex 6 device family and package The Virtex 6 device is dedicated to Digital Signal Processing video processing or communication applications and can be chosen from the SXT or LXT family devices Its package is based on Fineline Ball Grid array with 1759 balls In terms of logic and dedicated DSP resources the FPGA B can be chosen from the following types LX240T LX550T SX315T and the SX475T FF1759 3 2 Inter FPGA interface The Virtex 5 device is connected to the Virtex 6 device using a 54 pin bus plus 2 differential clock signals Also there are 16 single ended pins available that can be used as general 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 6 FM680 User Manual S r va purpose IO or as a connection to the Pn4 bus Please be aware that 8 of those extra bits are available only on the SX475T and the LX550T FPGA types Only on LX550T and SX475T Figure 2 Inter FPGA Interface 3 3 PCl express architecture The Virtex 5 device is connected to the XMC connector P15 and offers a PCI Express Endpoint block integrated in
16. chway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 15 FM680 User Manual S r va Part of the Emcore connector will protrude outside of front panel because the Emcore package dimensions are in breach of the XMC specifications in terms of height Figure 4 Emcore connectors protruding from front panel 125 MHz gt Clk buffer Emcore RX Virtex 6 FPGA B RXO gt RX1 Le RX2 RX3 RX4 RX5 RX6 RX7 RX8 gt RX9 RX10 RX11 Emcore TX Ten TX1 TX2 TX3 TX4 TX5 TX6 TX7 TX8 TX9 TX10 TX11 K K K K K K K K K K K A Figure 5 Emcore GTP connections 3 8 FPGALED Four LEDs are connected to the Virtex 5 device In the default FPGA firmware the LEDs are driven by the Virtex 6 device via the inter FPGA interface The LEDs are located on side 2 of the PCB in the front panel area Figure 6 FPGA LED locations 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 16 FM680 User Manual S r va 3 9 FPGA configuration 3 9 1 Flash storage The FPGA firmware is stored on board in a flash device The 512Mbit
17. ess endpoint or Serial Rapid IO and one Virtex 6 device It can be utilized for example to accelerate frequency domain algorithms with off the shelf Intellectual Property cores for applications that require the highest level of performances The FM680 is mechanically and electrically compliant to the standard and specifications listed in section 1 2 of this document A top level diagram is depicted in Figure 1 Front Panel 180 pin QTH connector on side 1 and on side 2 facing inward 12 lane EMCORE Tx Rx or 8 lanes rocket IO on 2 QTE connectors or 4 optical tranceivers 2 5 Gb s PCI express Optional battery for IP encryption key Ud Wou pepue ojbuis g snq e201 Papua ejBuis gg Configuration circuit and JTAG Flash 512Mbit LED x4 PCI express End point X C sdafg 0 dn xg sdag 0 dn xg sdabsz xy j saed SQA ZE JO 49MO 10 ILLAT papua ejBuis 79 User I O PCI Express Rocket IO VITA 42 3 VITA 42 2 42 3 1 Only available on XC6VLX550T and SX475T FPGA devices Figure 1 FM680 block diagram Build on the success of its predecessor boards of the FM48x series the FM680 also uses the BLAST technology A total of 5 BLAST sites connect directly to the Virtex 6 FPGA 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 5 FM680 User Manual ae r va BLAST
18. for the IO area daughter card option 3 7 1 Front Panel daughter card Only available with front panel daughter card purchase and not in combination with the optical transceivers or EMCORE The Virtex 6 device interfaces to a 180 pin connector placed in the Front panel I O area on both side 1 of the PCB It serves as a base for a daughter card and offers I O diversity to the FM680 PMC The FPGA I O banks are powered either by 1 8V or 2 5V via a large O ohms resistor 2 5V is the default if not specified otherwise at the time of order Using the Xilinx DCI termination options to match the signals impedance allows many electrical standards to be supported by this interface The VRN and VRP pins on the I O banks connected to the daughter card connector are respectively pulled up and pulled down with 500 resistors in order to ensure optimal performances when using the Xilinx DCI options The VREF pins are connected to 0 9V for DDR2 DCI terminations Please contact 4DSP Inc for more information about available daughter card types The 180 pin Samtec connector pin assignment is as follows All signals shown as LVDS pairs in the table can also be used for any standard that does not breach the electrical rules of the Xilinx I O pad The FP Xi signals in the table below are routed as single ended Connector Signal Signal Connector Dp PIA FE pin rre pin E FP Ire po resp P1 Sa oe s Lea Jos oe lex jo E ESI MEO us ls TSP
19. g e et lI lI Figure 10 JTAG connector J6 location The JTAG connector pinout is as follows Pin Signal Signal Pin 1 1 8V TMS 4 2 GND TDI 5 3 TCK TDO 6 Table 12 JTAG pin assignment 3 10 Clock tree The FM680 clock architecture offers an efficient distribution of low jitter clocks Both FPGA devices receive a low jitter 125MHz clock A low jitter programmable clock able to generate frequencies from 62 5MHz to 255 5MHz in steps of 0 5MHz is also available This clock management approach ensures maximum flexibility to efficiently implement multi clock domains algorithms and use the memory devices at different frequencies Both clock 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 19 FM680 User Manual S r va buffer devices CDCV1804 and the frequency synthesizer CDCE925 are controlled by the Virtex 5 device 125MHz gt gj Virtex 5 CDCM1804 FPGA A WE i ei 16 MHz Virtex 6 CDCE925 a FPGA B wi CPLD Figure 11 Clock tree 4 Power requirements The Power is supplied to the FM680 via the XMC Pn5 connector Several DC DC converters generate the appropriate voltage rails for the different devices and interfaces present on board The FM680 power cons
20. g or erasing OFF Flash device is not busy LED 3 ON CRC error Presumably a wrong or corrupted FPGA bit stream has been written to the flash Once on this LED remains on OFF No CRC error detected Table 11 LED board status Figure 9 CPLD LED locations 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 18 FM680 User Manual S r va 3 9 3 JTAG A JTAG connector is available on the FM680 for configuration purposes The JTAG can also be used to debug the FPGA design with the Xilinx Chipscope A press fit connector is delivered with the board that can be plugged into the connector holes The JTAG connector can be placed on both sides of the PCB The connector location seen from the bottom of the PCB is shown in Figure 10 VCC O TMS GND OO TDI TCK O TDO Je ee dng El 9 eec 2 5 E Dia 222 TOU E SS n ANE CG c 9 7 E N 5 pure 8 B Seng za ssa L i ps e B TO Z E ab Bn 9 e gabe H LE e nH um 4 E DI ka m ps m Rs uc m2 BS E MP T o To ez TE a e On B EE MO e de E i HE m on Bas HE R s ka a EB mama O hj at 8 n gre z a ue oe pi E a i EE BU Hr H m o Em ii e m a H T H z u o WER BB mim zu HI aa B B om z E E mmi H 88 27 585 58 o m S 2 e e Co nmi iii L R E o TE E e o E El e u
21. led as J2 Mounting a connector on the PCB breaches the PMC electrical and mechanical specifications of the PMC standard This is a FACTORY ONLY feature that is used in the manufacturing process when powering the board is required in an UN MOUNTED PCI bus mode thus in stand alone mode DO NOT connect an external power source to J2 doing so may result in damaging the board and will automatically VOID WARRANTY Consult factory for further information 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 22 FM680 User Manual LE gt 5 Environment 5 1 Temperature Operating temperature e 0C to 60 C Commercial e 40 to 85 C Industrial Storage temperature e 40C to 120C 5 2 Convection cooling 600LFM minimum 5 3 Conduction cooling V1 4 The FM680 can optionally be delivered as conduction cooled PMC The FM680 is compliant to ANSI VITA 20 2001 standard for conduction cooled PMC 6 Safety This module presents no hazard to the user 7 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system 4DSP est distribu
22. line Ball Grid Arra Front Panel Data Port Field Programmable Gate Array Joint Test Action Group Light Emitting Diode Low Voltage Transistor Logic level Low Differential Data Signaling Least Significant Bit s Low Voltage Differential Signaling Multi Gigabit Transceiver Most Significant Bit s Printed Circuit Board Peripheral Component Interconnect PCI Express Phase Locked Loop PCI Mezzanine Card Quadruple Data rate Synchronous Dynamic Random Access memory SRAM Synchronous Random Access memory Table 1 Glossary 1 2 Related Documents IEEE Std 1386 1 2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC ANSI VITA 20 2001 Conduction Cooled PMC ANSI VITA 42 0 2005 XMC Switched Mezzanine Card Auxiliary Standard ANSI VITA 42 3 2006 XMC PCI Express Protocol Layer Standard IEEE Std 1386 2001 IEEE Standard for a Common Mezzanine Card CMC Family Xilinx Virtex 5 Documentation Xilinx Virtex 6 Documentation 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 August 2010 FM680 User Manual www 4dsp com 4 FM680 User Manual S r va 1 3 General description The FM680 is a high performance XMC optionally conduction cooled dedicated to digital signal processing applications with high bandwidth and complex algorithms requirements It offers various interfaces fast on board memory resources one Virtex 5 FPGA with embedded PCl expr
23. p 6 gt PETOp6 La PEROp 7 gt PETOp7 la gt RefCLK CLK buffer XMC Pn6 PER1p0 PETipO La PER1p 1 gt PETip1 La PER1p2 gt PETIp2 La PEROp 3 gt PETOp3 la RefCLK H gt CLK buffer le PEROp 4 PETip4 La PERIp 5 PETip5 La PER1p 6 gt PETip6 La PER1p7 PETip7 la RefCLK CLK buffer Figure 3 PCl express subsystem diagram 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 August 2010 FM680 User Manual www 4dsp com FM680 User Manual LJE gt V1 4 3 4 Pn4 user I O connector The Pn4 connector is connected to the Virtex 5 device Connectorpin Signalname FPGA pin FPGApin Signalname Connector pin a Po jm Pn o 3 m V jm Leo Ju s Pmi P P Lem Jo Inge V Leg Jo 5 o Lamm R T Io fio 5 mo pnt Jm IL Leon ue a3 Pamio Ing LI png tora ua fis L m K6 nator Jie az Lpngpe Jm Lmm Lea is 9 Lens mo ms Png ms 21 na tozo mio LIm Jens 23 pes r7 ms Jeune 25 Jnage Im Lin Jeune 27 nations Ti8 Lu Jeune feof png 1028 PIO mo Jeune nm Pmioso ue Lu Png tot 33 Pn4io32 Im VI7 Jeng 35 Jeng R0 37 L mg LJ Jeng 39 Jeng m Jum Ten Pn4 1035 Ut ena tows In ena toas az pm oss P fes Lego 49 Pm fus V3 ng toto st Jpmioso ve yn Leger ss Prats ur ss Jpmios quis 1 Pmiose ka
24. par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 23 FM680 User Manual S r va 8 Technical support Technical support for all 4DSP Product hardware software and firmware is available under 4DSP Terms and Conditions of Sales ONLY in its original condition AS SHIPPED unless agreed to by 4DSP and documented in writing prior to any modifications Terms and Conditions are available from http www 4dsp com TOs txt Technical support requests should be sent to support 4dsp com Any electrical connections made to the board or other components shall be made only with approved connectors as specifically identified in the products official documentation Any modification to hardware including but not limited to removing of components soldering or other material changes to in part or in whole to the PCM and or its components will immediately invalidate and make void any warranty or extended support if any Further and changes or modifications to software and or firmware supplied with the Product unless provided for in the Products official documentation shall immediately invalidate and make void any warranty or extended support if any 9 PCB revisions 10 Warranty Basic Warranty included 1 Year from Date of Shipment 90 Days from Date of Shipment Extended Warranty optional 2 Years from Date of Shipment 1 Year from Date of Shipment 4DSP est distribu par
25. transceivers or EMCORE Eight Rx Tx Multi Gigabit Transceivers connected to the Virtex 6 are available in the front panel area on two connectors of type QTE These connectors provide a base for a daughter card dedicated to high bandwidth communication via optical transceivers or copper please refer to the FM489 web page for more details about available daughter cards Infiniband protocols as well as Gigabit Ethernet OC48 and Fibre channel sFPDP can be implemented over the transceivers Eight LVTTL signals four per connector are also available for daughter card control Pin Signal Signal Pin Pin Signal Signal Pin 1 Rx p3 7 3 3V 2 15 Tx n2 6 CTRL3 7 16 3 Rx n3 7 3 3V 4 17 Rx p1 5 GND 18 5 Tx p3 7 3 3V 6 19 Rx n1 5 GND 20 7 Tx n3 7 3 3V 8 21 Tx p1 5 GND 22 9 Rx p2 6 CTRLO 4 10 23 Tx n1 5 GND 24 11 Rx n2 6 CTRL1 5 12 25 Rx n0 4 Tx n0 4 26 13 Tx p2 6 CTRL2 6 14 27 Rx p0 4 Tx p0 4 28 Table 9 QTE connector pinout 3 7 5 Emcore connector This is a special build option and not in combination with the optical transceivers or front panel daughter card Another front panel possibility is the 12 lanes Emcore connector FM680V2 This connector comes with a TX and an RX version FM680 will come with one TX and one RX connector All the high speed serial connections will connect directly to the Virtex 6 FPGA 4DSP est distribu par TECHWAY www techway fr info te
26. umption depends mainly on the FPGA devices work load By using high efficiency power converters all care has been taken to ensure that power consumption will remain as low as possible for any given algorithm After power up the FM680 typically consumes 6 Watts of power For precise power measurements it is recommended to use the Xilinx power estimation tools for both the Virtex 5 and Virtex 6 FPGA devices The maximum current rating given in the table below is the maximum current that can be drawn from each voltage rail in the case resources are used to their maximum level Special precautions need to be taken to support the XMC VPOWER input since the XMC standard dictates that this power supply can either be 12V or 5V To overcome this a voltage detection circuit detects whether VPOWER is 12V or 5V and enables a switching regulator or a Field Effect Transistor FET If VPOWER is 12V the switching regulator converts down to 5V otherwise the FET allows 5V to pass through Device Interface Voltage Maximum current rating DCI and memory reference 0 9V 6A voltage Virtex 6 device core 1 0V 10A Virtex 5 device core 1 0V 2A BLAST core and IO Virtex 6 I O 1 8V 6A banks 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FM680 User Manual August 2010 www 4dsp com 20 FM680 User Manual S r va Virtex 5 device I O bank 0 9 1 0 1 8 2 5 3
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