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X3-SDF User's Manual

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1. Feature Description Inputs 4 independent Input Range 10V to 10V differential Input Impedance 2K ohm 15 pF excludes cable A D Devices Analog Devices AD7760 Output Format 2 s complement 32 bit Number of A D Devices 4 simultaneously sampling Sample Rate 5MSPS 24 bit maximum 20 MSPS 16 bit modulator data accessible only for custom logic work Clock Rate 6 144 to 20 MHz Calibration Factory calibrated Gain and offset errors are digitally corrected in the A D Non volatile EEPROM coefficient memory Table 15 X3 SDF A D Features Conversion clocking is provided through separate special circuitry that minimizes jitter on the clocks The clock circuitry allows for a variety of clock sources including two external sources to be used as conversion timebases See the clock discussion for more details The following block diagram shows the general arrangement of the A D The differential inputs from the front panel connector are adjusted for range through a differential amplifier and input to the A D The A D output data rate is determined by the sample clock rate and the A D filter decimation rates The A D has three internal filters that are used to filter the data to the desired data rate and resolution At rates below 2 5 MSPS fully filtered data provides the best resolution and dynamic range At 5 MSPS the data is not as well filtered so the dynamic
2. The main focus of the module is the X3 s computing core which connects the IO peripherals host communications and support features Each IO device directly connects to the application FPGA on the X3 module providing tight coupling for high performance Real time IO The FPGA logic implements an interface to each device that connects them to the X3 SDF User s Manual 37 Linux Directory Structure X3 SDF User s Manual controls and data communications features on the module Support features such as sample triggering and data analysis are implemented in the logic to provide precise real time control over the data acquisition process X3 Computing Core Block Diagram The X3 module architecture 1s really defined by the features in the logic that connect the IO devices to the Velocia packet system For data from IO devices such as A Ds the data flows from the IO interface and is then enqueued in the multi queue buffer The packetizer then creates data packets from the data stream that are moved across the data link to the PCIe interface Packets to output devices travel in the opposite direction from the link to the deframer and into the multi queue data buffer The output IO such as a DAC then consumes the data from the queue as required The Alert Log monitors error conditions and important events for management of the data acquisition process The host interacts with the X3 computing core using the packet system for high
3. Figure 9 Digital IO Port Addresses Data may be written to read from the digital I O port using the digital I O port data registers Data written to ports bits which are set for output mode will be latched and driven to the corresponding port pins while data written to input bits will be ignored The input DIO may be clocked externally by enabling the external digital clock bit in the appropriate configuration register If the internal clock is used the data is latched at the beginning of any read from the port Data read from output bits is equal to the last latched bit values i e the last data written to the port by the host Digital 1 O port pins are pulled down to digital ground within the logic device Consequently the state of the DIO pins do not change as power is applied to the PC during system start up The pulldown resistor is about 8K ohms External signals connected to the digital I O port bits or timer input pins should be limited to a voltage range between 0 and 3 3V referenced to ground on the digital I O port connector Exceeding these limits will cause damage to the X3 module Front Panel DIO Some modules in the X3 family notably the A4D4 25M Servo SD16 and 2M provide additional banks of digital I O accessible via the front panel MDR68 connector The number of available bits is shown in the table below These bits are direction programmable in banks of eight bits The FrontPanelPortConfig property is used to progra
4. sse nennen nnne nennen nnne 12 Oona Help tetas E HUE EE 12 Innovative Integration Technical Support cecesceeseesceeseesceeseeseceseesecnsecseeeseceeeseceeesescesseseaesseeeaeeseeeseeeeeaeeeeeeessaeeeeaeeees 12 Innovative Integration Web Site enne enne enne nennen entente nter enne inerenti nne 13 Typographic COonven ls oO Installation oH LNUs en oio ri A cad Package File Names deese a 14 Prerequisites for Installation incita c E The Redistribution Package Group MalibuRed omooonononnnonoonncononcconananonananonanononanononanononcnconacccnonac ono 14 A A EO Other SOICWAEO ie thnc tpe ceen e tixtd dud is LS Baseboard Package Installation Procedure omomommmss 19 Board PACK AB OS er c O Unpacking the Package DC LO Creating Symbolic Links un eth ete Ba Se a ede ce et eR eet es 16 Completing the Board li ici eec L7 Linux Directory SITU Em d ur i cum CE 17 Hari Watt A A UU m 17 Mem Driver Installation LInUx eeecoe e eee e eode eso eto nere ea aoo se oon eoe ead re eso caseus esa o eese Vae eoe ee Loose da ro sacacinicaci ss LS X3 SDF User s Manual Table of Contents X3 SDF User s Manual Windows Enis Call a e REID Host Hardware Requirenbents 5o diei soot oe eee eo Sek e Noo ee save eiie PNIS E BR a cacon seisis lnea oU eese qe Ze Software Iistallation is
5. int64 samples FBlockCount Settings PacketSize int triggers static cast int samples Settings FrameCount if triggers FTriggered SoftwareTrigger In the event that were operating in framed trigger mode the example code re asserts a software trigger each time a frames worth of data packets have been received If we re in continuous mode no action need be performed to sustain data flow EEProm Access Each PMC module contains an IDROM region that can be used to write information associated with the module In the next line of code we make a call to Malibu method IdRom which returns an object that acts as interface to that region The following methods illustrate how to write and read information from IDROM StoreToRom and ReadRom are the two IdRom methods used to save and retrieve data to from memory void ApplicationIo WriteRom Module IdRom Name Settings ModuleName Module IdRom Revision Settings ModuleRevision Module Clock ReferenceCalibrationFactor Settings PllCorrection for int ch 0 ch lt Channels ch Module Input Gain ch Settings AdcGain ch X3 SDF User s Manual 69 Linux Directory Structure X3 SDF User s Manual Module Input Offset ch Settings AdcOffset ch Module Input Calibrated Settings Calibrated Module IdRom StoreToRom void ApplicationIo ReadRom Module IdRom LoadFromRom Settings ModuleName
6. Span 100 Analyze Cho cho X X3 SDF User s Manual 5amples 4096 73 Linux Directory Structure X3 SDF User s Manual Applets for the X3 SDF Baseboard EEProm X3 SDF has two logic devices on it One controls the analog hardware This logic can be modified by the user and must be loaded by the user with an image on each session The second device performs the baseboard enumeration and PCI interface and has a ROM so that it can function at power up The EEProm applet is designed to allow field upgrades of this PCI logic firmware on the X3 SDF The utility permits an embedded firmware logic update file to reprogrammed into the module Flash ROM which stores the personality of the board Complete functionality 1s supplied in the application s help file nc Eeprom Programmer DOS J Target Xsvf File Load Event Log No devices detected Revision Family Pcb Type Status Elapsed X3 SDF User s Manual 74 Linux Directory Structure X3 SDF User s Manual Finder The Finder is designed to help correlate board target numbers against PCI slot numbers in systems employing multiple boards Target Number Select the Target number of the board you wish to identify using the Target Number combo box Blink Click the Blink button to blink the LED on the board for the specified target It will continue blinking until you click Stop On OFF Use the On a
7. The Alert Log creates an alert packet whenever an enabled alert 1s active The packet includes information on the alert when it occurred in system time and other status information The system time is kept in the logic using a 32 bit counter running at the sample clock rate Each alert packet is transmitted in the packet stream to the host marked with a Peripheral Device Number corresponding to the Alert Log The Alter Log allows X3 modules to provide the host system with time critical information about the data acquisition to allow better system performance System events such as over ranges can be acted on in real time to improve the data acquisition quality Monitoring functions can be created in custom logic that triggers only when the digitized data shows that something interesting happened Alerts make this type of application easier for the host to implement since they don t require host activity until the event occurs Types of Alerts Alerts can be broadly categorized into system IO and software alerts System alerts include monitoring functions such as temperature time stamp rollover and PLL lost These alerts just help keep the system working properly The temperature warning should be used increase temperature monitor and to prepare to shut down 1f necessary because thermal overload may be coming Better to shut down than crash in most cases The temperature failure alert tells the system that the module actually shut itself down
8. When the alert system is enabled the module logic continuously monitors the status of the peripheral usually analog hardware present on the baseboard and generates an alert whenever an alert condition is detected It s also possible for application software to generate custom alert messages to tag the data stream with system information The Malibu software provides support for alert configuration and alert packet processing See the software manual for usage Tagging the Data Stream The Alert Log can be used to tag the data stream with system information by using software alerts This helps to provide system level correlation of events by creating alert packets in the data stream created by the host software Alert packets are then created by the X3 module and are in the stream of data packets from the module For example it is often interesting when something happens to the unit under test such as a change in engine speed or completion of test stimulus Using the X3 SDF Where to start The best place to start with the X3 SDF module is to install the module and use the SNAP example to acquire some data This program lets you log data from the module and use all the features like triggering clocks alerts and calibration ROM You can use this program to acquire some data and log it to disk This should let you verify that the module can acquire the data you want and give you a quick start on deciding what sample rates to use how to trig
9. 117 Linux Directory Structure X3 SDF User s Manual Table 33 X3 SDF XMC Secondary Connector P16 Pinout Column Row A B C D E F 1 i DIOO0 PXI TRIGO E DIO19 2 DGND DGND DIO1 PXI TRIGI DGND DGND DIO20 3 z DIO2 PXI TRIG2 2 DIO21 4 DGND DGND DIO3 PXI TRIG3 DGND DGND DIO22 5 DIO4 PXI_TRIG4 DIO23 6 DGND DGND DIOS PXI_TRIG5 DGND DGND DIO24 7 z DIO6 PXI TRIG6 f DIO25 8 DGND DGND DIO7 PXI TRIG7 DGND DGND DIO26 9 DIO38 DIO39 DIO8 PXI_ STAR DIO40 DIO41 DIO27 PXI DSTARA PXI DSTARA PXIE_100M PXIE 100M 10 DGND DGND DIO9 DGND DGND DIO28 PXIE SYNC100 11 B DIO10 DIO29 PXIE_SYNC100 12 DGND DGND DIO11 DGND DGND DIO30 13 2 DIO12 E DIO31 14 DGND DGND DIO13 DGND DGND DIO32 15 2 DIO14 DIO33 16 DGND DGND DIO15 DGND DGND DIO34 17 z DIO16 DIO35 PXI 10M 18 DGND DGND DIO17 DGND DGND DIO36 PXI LBL6 19 DIO42 DIO43 DIO18 DIO_CLK DIO CLK PXI DIO37 PXIE DSTARB PXIE DSTARB PXI DSTARC DSTARC PXI LBR_6 Note all unused pins are not labeled X3 SDF User s Manual 118 Linux Directory Structure X3 SDF User s Manual Table 34 P16 Signal Descriptions Signal Description P16 Pin DIO0 PXI TRIGO Digital IO 0 PXIE trigger 0 Cl DIO PXI TRIGI
10. Start counter Clock Start std stringstream msg msg lt lt Packet size lt lt Packet Size lt lt samples UI Log msg str If enabled log the data stream if Settings LoggerEnable Settings PlotEnable if FBlockCount BlocksToLog Logger LogWithHeader Packet Count the blocks gone by on each Channel FBlockCount X3 SDF User s Manual Linux Directory Structure X3 SDF User s Manual In this example each received packet is logged to a disk file The packet header and the body are written into the file which implies that a post analysis tool such as BinView will be used to parse channelized data from the file Alternately custom applications may use the Innovative PacketDeviceMap object to conveniently extract channelized data from a packet data source Stop streaming when both Channels have passed their limit if Settings AutoStop amp amp IsDataLoggingCompleted amp amp Stopped Stop counter and display it double elapsed Clock Stop StopStreaming UI gt AfterStreamAutoStop UI gt Log Stream Mode Stopped automatically Ul gt Log std string Elasped S FloatToString elapsed Packets are processed until a specified amount of data is logged or the GUI Stop button is pressed Auto analyze and retrigger in framed mode if Settings Framed return if Settings ExternalTrigger 0 amp amp Settings AutoTrigger
11. 140 160 180 LP HH 0 5 10 15 20 25 KHz Max S N dB S N 05 SINAD 48 ENOB SFOR 45 THD e dB 146 2 114 0 104 8 17 1 109 9 0 000510 105 8dB X3 SDF User s Manual 107 Linux Directory Structure X3 SDF User s Manual Figure 27 Signal Quality 1 01 kHz 19 8Vp p input 50 ksps X3 SDF User s Manual 108 Linux Directory Structure X3 SDF User s Manual 0 X3 SDF 20 40 60 80 co Lo 100 120 140 160 n L 180 0 5 10 15 20 25 30 35 40 45 50 KHz Max S N dB S N 05 SINAD 48 ENOB SFOR 25 THD d8 146 2 114 1 1042 17 0 110 0 0 000509 105 9dB Figure 28 Signal Quality 1 01 kHz 19 8Vp p input 100 ksps 0 x2 SDF 20 40 60 80 re Lo 100 120 140 160 180 102 10 1 100 101 102 KHz Max S N dB S N dB SINAD dB ENOB SFOR dB THD d8 146 2 102 5 974 15 9 107 5 0 000604 104 448 Figure 29 Signal Quality 1 01 kHz 19 8Vp p 1000 ksps X3 SDF User s Manual 109 Linux Directory Structure X3 SDF User s Manual X3 SDF 20 40 60 100 B 420 140 160 180 200 220 0 50 100 150 200 250 KHz Max S N dB S N dB SINAD dB ENOB SFDR dB THD 9 dB 146 2 68 4 67 9 11 0 96 0 002289 92 8dB Figure 30 Signal Quality 101 kHz 9 8Vp p 500 ksps 160 180 200 0 50 100 150 200 250 300 350 400 450 500 KHz Max S N dB S N dB SINAD dB ENOB SFDR dB THD 96 dB 148 2 93 1 84 4 13 7 92 6 0 003811 88 4dB Figu
12. 66 MHz lt gt SelectMAP interface to Connector P15 app logic The major interfaces to the application logic are the data link command channel and SelectMAP interface The data link provides a high performance channel for the application logic to communicate with the host computer while the Command Channel is a command and control interface from the host computer to the application logic The SelectMAP interface is the application FPGA configuration port for loading the logic image The data link is the primary data path for the data communications between the application FPGA and host computer When data packets are created by the application logic such as A D samples or required by the application logic for output devices such as DAC channels the data flows over the data link as packets The maximum transfer rate over the data link is 264 MB s with a 220 MB s sustained rate The data packets contain a Peripheral Device Number PDN that identifies the peripheral associated with the this data packet In this way the packet system is extensible to other devices that may be added to the logic For example an FFT analysis can be added to the logic and its result sent to the host as a new PDN for display and further analysis while maintaining other data streams from A D channels Table 5 Interfaces from PCI Express to Application Logic Application Logic Max Data Rate Typical Use Interface Data Link 264 MB s bu
13. Linux Directory Structure X3 SDF User s Manual AGND AIDO IN AGND AGND AID1 IN AGND AGND A D2 IN AGND AGND A D3 IN AGND AGND EXT CLK TRIGGER1 AGND AIDO IN AGND AGND EXT CLK TRIGGERO Note No Connect P Power I Input O Output relative to X3 module X3 SDF User s Manual 113 Linux Directory Structure X3 SDF User s Manual XMC P15 Connector P15 is the XMC PCI Express connector to the host Connector Types XMC pin header 0 05 in pin spacing vertical mount Number of Connections 114 arranged as 6 rows of 19 pins each Connector Part Number Samtec ASP 105885 01 Mating Connector Samtec ASP 105884 01 L1 je a O a a a O a O a je a a a O a a LH Figure 34 P15 XMC Connector Orientation X3 SDF User s Manual 114 Linux Directory Structure X3 SDF User s Manual Column Row A B C D I F 1 PETOpO PETOn0 3 3V VPWR 2 GND GND GND GND MRSTI 3 3 3V VPWR 4 GND GND GND GND MRSTO 5 3 3V VPWR 6 GND GND GND GND 12V 7 3 3V VPWR 8 GND GND GND GND 12V 9 10 GND GND GND GND GAO 11 EROpO PEROnO MBIST VPWR 12 GND GND GAI GND GND MPRESENT 13 3 3VAUX VPWR 14 GND GND GA2 GND GND MSDA 15 VPWR 16 GND GND MVMRO GND GND MSCL 17 18 GND GND GND GND 19 PEX REFCLK PEX
14. X3 SDF Module s tite ee eg ur tete E Hte dra ep qui as tette URGE EE 77 Figure 14 X3 SDP Block Diagram eet into Lp e dee ed 78 Figure 15 X3 SDF A D Channel Diagram eene teenretee trennen rennen rete tne tenent ennt enne nnne 80 Figure 16 X3 SDF Clock Generation and Controls Block Diagram eese nennen 82 Figure 17 X3 S8DF External Clock Path cui dt nog aep i oe geo p atti tuet 83 Figure l PLE Reference Prescalo 2e ines dete tete te ta m BU E 85 Figure 2 Examples of PLL Output FrequencieS oocoocncnncncononcnnnnnnononnnnnoncnncnncnacnn coccion non non non non none nn nana anna treten ener eene nnne 85 Figure 18 Analog Triggering Timing sss nnne nnne RR nn RR nr innen ran rra nnne inneren 89 Figure 19 X3 SDF FrameWork Logic Data Flow eese nennen netten ennt rete tetetetrr rca 9 Figure 20 X3 SDF Ground Noise Input Grounded Fs 100 ksps sseessssssseeseeeneennenne nennen 101 Figure 21 X3 SDF Noise Floor 0 to 50 kHz Grounded Input Fs 100 ksps sssssseeeeeeeenenne nne 102 Figure 22 X3 SDF Frequency Response for 10 to 200K Hz span 20Vp p input essen emen 102 Figure 23 X3 SDF A D Signal Quality vs Sample Rate eese nente nnne ener 104 Figure 24 X3 SDF A D Signal Quality vs Input Amplitude ooooonccicnnnnnccnnononononnconcnoncnnconncnnoonncnno no nennen 105 Figure 25 Signal Quality vs Input Fregene y vsere eere EEEE entere
15. 0 16 8 103 4 100 kHz 113 1 108 3 16 7 103 5 500 kHz 107 5 107 1 16 3 104 2 1000 kHz 101 6 107 0 15 8 104 9 5000 kHz 87 6 78 8 11 9 75 2 X3 SDF User s Manual 100 Linux Directory Structure X3 SDF User s Manual Noise Floor grounded input Amplitude vs Time Q 5 o X3 SDF A105 0 08 0 06 0 04 0 02 ANN UU A N UN wi DD 0 00 0 02 Hil UL ill Il Il WU UN IM MAUI ll Ht HIV Hill Il UM 0 04 0 06 0 08 0 10 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 mS Min mV Max mV Delta mV Mean mV Std Dev mV Range dB 3 8399e 02 3 6703e 02 7 5102e 02 1 6653e 03 8 1885e 03 854 Figure 20 X3 SDF Ground Noise Input Grounded Fs 100 ksps Magnitude vs Frequency X3 SDF A105 cho 120 140 160 180 0 5 10 15 20 25 30 35 40 45 50 KHz X3 SDF User s Manual 101 Linux Directory Structure X3 SDF User s Manual Figure 21 X3 SDF Noise Floor 0 to 50 kHz Grounded Input Fs 100 ksps Frequency Response Test method Input sine from 10 to 2 5 MHz at 19 8Vp p Figure 22 qud dB T o o AR 0 05 0 08 100 os S CHO T LH ooo IN 1000 Analog Bandwidth la Y 4 400 Horaro E AJ N ES 10000 100000 Freq Hz 1000000 Column I X3 SDF User s Manual 102 Linux Directory Structure X3 SDF User s Manual X3 SDF User s Manual 103 Linux D
16. 16383 integers B 3 to 8191 integers 1 bypass A 0 to 63 integers used only in dual modulus mode X3 SDF User s Manual 84 Linux Directory Structure X3 SDF User s Manual P reference prescaling shown in the following table for the two modes and 100 MHz Fvco 140 MHz Mode FD Fixed Divide DM Dual Modulus Value in 0Ah lt 4 2 gt Divide By FD 000 l FD 001 2 P 2 DM 010 P P 1 2 3 P 4DM 011 P P 4 1 2 4 5 P 8DM 100 P P 1 2 8 9 P 16DM 101 P P 1 16 17 P 32DM 110 P P 1 32 33 FD 111 3 Figure 1 PLL Reference Prescaling The following table shows a sampling of the PLL output frequencies for a a desired frequency This table does not show all possible combinations of values and there may be settings closer to a particular frequency of interest The table is a good just illustrates the frequency range required by the A D and the tuning resolution In use the Malibu software drivers compute the required PLL configuration to come as close as possible to the desired sample rate considering the constraints of the devices Fyeq FyogR x PB A Fs Mhz D FVCO Fref Mhz R PB A P A B FS ACTUAL Mhz Error ppm 20 000 6 120 24 576 16383 79995 32 27 2499 19 999971 1 5 19 999 6 119 99 24 576 16383 79991 32 23 2499 19 998971 1 5 19 000 6 114 24 576 16383 75995 32 27 2374 18 999910 48 18 000 6 108 24 576 16382 71991 32 23 2249 17 999947 2 9 17 000 6 102 24 576 16378 67975 32 7 2124 16 999976 1
17. 2 A summary of the analog performance follows for the X3 SDF module All tests performed at room temperature with no forced air cooling unless noted Test environment was PCIe adapter card in PC running testbed software using FrameWork Logic Table 30 X3 SDF Analog Performance Summary Test Group Parameter Measured Units Test Conditions Analog Input Bandwidth 0 01 dB 0 to 1 MHz 19 8Vp p sine 24 85 dB 2 5 MHz 1 dBm sine Impedance 2 05k Ohms nominal Input Range Max 10 02 Vp p Standard on X3 SDF calibration results may limit input Min 9 98V differential range to 0 99 of full scale nominal Accuracy Offset lt 100 uV Factory calibration average of 64K samples Gain lt 0 2 Factory calibration average of 64K samples Analog Input Ground Noise 70 uVp p Input Grounded Fs 100 ksps 250k samples Ground Noise 147 dB Input Grounded Fs 100 ksps 64K sample FFT non averaged X3 SDF User s Manual 99 Linux Directory Structure X3 SDF User s Manual Test Group Parameter Measured Units Test Conditions Analog Input Crosstalk 110 dB 1 MHz 20Vp p input cable included all channels Analog Input Amplitude 0 03 dB 10 Hz to 200K Hz input range 20 Vp p Variation Test Group Parameter Analog Sample Rate S N dB SFDR dB ENOB bits THD dB Input 10 kHz 105 4 121 7 17 1 119 4 50 kHz 113 1 108
18. 4 16 000 8 128 24 576 16383 85328 32 16 2666 15 999977 1 5 15 000 8 120 24 576 16383 79995 32 27 2499 14 999978 1 5 14 000 8 112 24 576 16383 74662 32 6 2333 13 999979 1 5 13 000 8 104 24 576 16383 69329 32 17 2166 12 999981 1 5 12 000 10 120 24 576 16383 79995 32 27 2499 11 999982 1 5 11 000 12 132 24 576 16382 87989 32 21 2749 10 999968 2 9 10 000 12 120 24 576 16383 79995 32 27 2499 9 999985 1 5 9 000 14 126 24 576 16378 83969 32 1 2624 8 999974 2 8 8 000 16 128 24 576 16383 85328 32 16 2666 7 999988 1 5 7 000 16 112 24 576 16383 74662 32 6 2333 6 999990 1 5 6 000 22 132 24 576 16380 87978 32 10 2749 5 999965 5 9 5 000 28 140 24 576 16380 93310 32 30 2915 4 999971 5 9 4 050 30 121 5 24 576 16383 80995 32 3 2531 4 049997 0 7 _ 4 001 30 120 03 24 576 16383 80015 32 15 2500 4 000994 1 4 4 000 30 120 24 576 16383 79995 32 27 2499 3 999994 1 5 3 200 32 102 4 24 576 16381 68254 32 30 2132 3 199992 2 4 Figure 2 Examples of PLL Output Frequencies Linux Directory Structure X3 SDF User s Manual PLL Status The PLL has a status pin that can be programmed to show when the PLL is locked or other status information The software in the SNAP example configures this pin to be digital lock detect It indicates when the PLL is locked and ready for use If the PLL lock is false the PLL is not working properly and may give poor results or inaccurate frequencies Even when the PLL is unable to lock it will produce an output so the m
19. AlertEnable array This code fragment applies the state of each bit in that array to the Alerts sub object within the module During streaming an alert message will be sent to the Host tagged with a special alert packet ID PID to signify the alert condition Start Streaming Stream Start UI gt Log Stream Mode started UI gt Status Stream Mode started The Stream Start command applies all of the above configuration settings to the module then enables PCI data flow However samples will not be acquired until the module is triggered ActualSampleRate static cast float Module Clock FrequencyActual std stringstream msg msg precision 6 msg Actual sampling rate ActualSampleRate 1 e3 KHz Ul gt Log msg str FTicks 0 Timer Enabled true Handle Data Required Once streaming is enabled and the module is triggered data flow will commence Samples will be accumulated into the onboard FIFO then they are bus mastered to the Host PC into page locked driver allocated memory following a two word header data packets Upon receipt of a data packet Malibu signals the Stream OnDataAvailable even By hooking this event your application can perform processing on each acquired packet Note however that this event is signaled from X3 SDF User s Manual 67 Linux Directory Structure X3 SDF User s Manual within a background thread So you must not perform non reentrant
20. Digital IO 1 PXIE trigger 1 C2 DIO2 PXI TRIG2 Digital IO 2 PXIE trigger 2 C3 DIO3 PXI TRIG3 Digital IO 3 PXIE trigger 3 C4 DIO4 PXI TRIG4 Digital IO 4 PXIE trigger 4 C5 DIO5 PXI TRIGS Digital IO 5 PXIE trigger 5 C6 DIO6 PXI TRIG6 Digital IO 6 PXIE trigger 6 C7 DIO7 PXI TRIG7 Digital IO 7 PXIE trigger 7 C8 DIOS PXI STAR Digital IO 8 PXIE star trigger C9 DIO9 PXIE_SYNC100 Digital IO 9 PXIE sync 100 C10 DIO10 PXIE_SYNC100 Digital IO 10 PXIE sync 100 C11 DIO11 Digital IO 11 C2 DIO12 Digital IO 12 C13 DIO13 Digital IO 13 C14 DIO14 Digital IO 14 C15 DIO15 Digital IO 15 C16 DIO16 Digital IO 16 C17 DIO17 Digital IO 17 C18 DIO18 Digital IO 18 C19 DIO19 Digital IO 19 Fl DIO20 Digital IO 20 F2 DIO21 Digital IO 21 F3 DIO22 Digital IO 22 F4 DIO23 Digital IO 23 F5 DIO24 Digital IO 24 F6 DIO25 Digital IO 25 F7 X3 SDF User s Manual 119 Linux Directory Structure X3 SDF User s Manual Signal Description P16 Pin DIO26 Digital IO 26 F8 DIO27 Digital IO 27 F9 DIO28 Digital IO 28 F10 DIO29 Digital IO 29 F11 DIO30 Digital IO 30 F12 DIO31 Digital IO 31 F13 DIO32 Digital IO 32 F14 DIO33 Digital IO 33 F15 DIO34 Digital IO 34 F16 DIO35 PXI 10M Digital IO 35 PXI 10M Ref CIk F17 DIO36 PXI LBL6 Digital IO 36 PXI local bus left 6 F18 DIO37 PXI LBR_6 Digital IO 37 PXI local bus right 6 F19 DIO38 PXI DSTARA Digital IO 38 PXIE Differential STAR A A9 DIO39 PXI DSTARA D
21. REFCLK WAKE ROOT Table 31 X3 SDF XMC Connector P15 Pinout Note All unlabeled pins are not used by X3 modules but may defined in VITA42 and VITA42 3 specifications X3 SDF User s Manual 115 Linux Directory Structure X3 SDF User s Manual Table 32 P15 Signal Descriptions Signal Description P15 Pin PETOpO PETOnO PCI Express Tx A1 B1 PEROp0 PEROn0 PCI Express Rx A11 B11 PEX REFCLK PCI Express reference clock 100 MHz A19 B19 MRSTI Master Reset Input active low F2 MRSTOF Master Reset Output active low F4 GAO Geographic Address 0 F9 GA1 Geographic Address 1 C12 GA2 Geographic Address 2 C14 MBIST Built in Self Test active low Cll MPRESENT Present active low F11 MSDA PCI Express Serial ROM data F13 MSCL PCI Express Serial ROM clock F15 MVMRO PCI Express Serial ROM write enable C16 WAKE Wake indicator to upstream device active low D19 ROOT Root device active low E19 X3 SDF User s Manual 116 Linux Directory Structure X3 SDF User s Manual XMC P16 Connector P16 is the XMC secondary connector to the host and is used for digital IO data link and triggering functions Connector Types XMC pin header 0 05 in pin spacing vertical mount Number of Connections 114 arranged as 6 rows of 19 pins each Connector Part Number Samtec ASP 105885 01 Mating Connector Samtec ASP 105884 01 Figure 35 fion X3 SDF User s Manual
22. Updating the Calibration Coefficients A software applet for writing the calibration coefficients to the EEPROM is provided EEPROM exe New coefficients are simply typed into the offset and gain field for each channel Calibration coefficients for gain should not be greater than 1 1 and offset 0x8000 If the calculated coefficients are larger than this they are either wrong or the channel is damaged X3 SDF User s Manual 97 Linux Directory Structure X3 SDF User s Manual Performance Data Power Consumption The X3 SDF requires the following power for typical operation with when using the FrameWork Logic This typical number assumes a 67 MHz system clock rate and 5 MSPS A D data rates for the application logic Table 28 X3 SDF Power Consumption Voltage Maximum Allowed Typical Current Typical Derived from Supplies these Devices Current A Required A Power W 3 3V 5A 2 4 7 92 Direct connect to the FPGA IO clock controls and recommended PCIe host analog power supplies 12 0 1A 0 005 0 06 Direct connect to the A D voltage references recommended PCIe host Total 7 98 Power Surge currents occur initially at power on and after application logic initialization The power on surge current lasts for about 10 ms 5A on both 3 3V and 5V This surge 1s due primarily to charging the on card capacitors and the startup current of the FPGAs After initial power up the logic configuratio
23. checked and loaded into option object Ul gt GetSettings loads the settings information from the UI controls into the Settings structure in the Applicationlo class if SampleRate Module Input Info MaxRate UI gt Log Sample rate too high StopStreaming UI AfterStreamAutoStop return We insure that the sample rate specified by the GUI is within the capabilities of the module if Settings Framed if Settings FrameCount lt Settings PacketSize UI gt Log Error Frame count must exceed packet size UI gt AfterStreamAutoStop return The module supports both framed and continuous triggering In framed mode each trigger event whether external or software initiated results in the acquisition of a fixed number of samples In continuous mode data flow continues whenever the trigger is active and pauses while the trigger is inactive The code above issues a warning if the trigger mode is framed and ill formed FBlockCount 0 FBlockRate 0 FTriggered 1 The class variables above are used to maintain counts of blocks received reception rate and whether the module is currently triggered These values are initialized prior to each streaming run Channel Enables for int i 0 i lt Channels i Module Input Info Channels Enabled i Settings ActiveChannels i true false int ActiveChannels Module Input Info Channels ActiveChann
24. clock rate of the A D 1 MHz We recommend using decimation if the data rate falls below 5 ksps that decimation be used because the A D performance begins to degrade below this output data rate The decimation simply discards M points for every point kept no averaging or filtering is used When decimation is true the number of points captured in the framed mode is the number of decimated points in other words the discarded points do not count Maximum decimation rate is 1 4095 When decimation is used in the framed trigger mode the number of points captured is after decimation The frame count is always the actual number of points inserted into the FIFO FrameWork Logic Functionality The FrameWork Logic implements a data flow for the X3 SDF that supports standard data acquisition functionality This data flow when used with the supporting software allows the X3 SDF to act as a data acquisition card with 2MB of data buffering and high speed data streaming to the host PCI Express The example software for the X3 SDF demonstrates data flow control logic loading and data logging X3 SDF User s Manual 90 Linux Directory Structure X3 SDF User s Manual Host Card 4 total f Ne C80 interface Data Buffer Packetizer nf PCle Figure 19 X3 SDF FrameWork Logic Data Flow The data flow is driven by the data acquisition process Data flows from the A D devices into the A D interface component in the FPGA as controlled by t
25. connectors and physical locations The bottom view of the XMC is shown which is the side against the host card when mounted The XMC conforms to IEEE 1386 form factor 75mm x 150mm The spacing to the host card is 10 mm and consumes a single slot in desktop and Compact PCI PXI chassis The following views of the X3 SDF show the connector placements The bottom view of the board is faces the carrier card when installed An EMI shield over the analog section is normally installed Detailed drawings for mechanical design work are available through technical support Note that the bottom of the card is the side with the XMC and front panel connector P16 XMC DIO m Uy Zi ge E 5 9 p lt jn MT e STITT x72 e9e 4 7 x ES 3 ete B s tfe Si e 1 E e e gg e e e v e 090 e z e e v ee z ee ee O So gt t BS e p zz e uii mm a e l EZ a s 3 L 2 d Ea o Una G A fiset dt JP2 Power Test X3 SDF User s Manual JP3 JTAG 122 Linux Directory Structure X3 SDF User s Manual Figure 38 X3 SDF Mechanicals Bottom View Rev A z O 51305 Rev Bj o EN e D4 PCI D5 LED Application LED Figure 39 X3 S
26. correction Module Clock Reference reference Module Clock Frequency SampleRate X3 SDF User s Manual 66 Linux Directory Structure X3 SDF User s Manual The module may accept an external sample clock but also features a programmable PLL clock source which may be used as a sample clock for the A D input channels If the All channels trigger together Module Input ExternalTrigger Settings ExternalTrigger 1 Frame count in units of packet elements if Settings Framed Module Input Framed Settings FrameCount else Module Input Unframed Samples will not be acquired until the channels are triggered Triggering may be initiated by a software command or via an external input signal to the Trigger SMA connector The code fragment above selects the trigger mode enum IUsesX3Alerts AlertType Alert IUsesX3Alerts alertTimeStampRollover IUsesX3Alerts alertSoftware IUsesX3Alerts alertWarningTemperature IUsesX3Alerts alertPllLost IUsesX3Alerts alertInputFifoOverrun IUsesX3Alerts alertInputTrigger IUsesX3Alerts alertInputOverrange for unsigned int i 0 i lt Settings AlertEnable size 1 Module Alerts AlertEnable Alert i Settings AlertEnable i true false The fragment above enables alert generation by the module The GUI control includes check boxes for each of the types of alerts of which the module is capable The enabled state of the check boxes is copied into the Settings
27. forwards the call to the UI form class to perform the action Applicationlo only has to know how to deal with a pointer to a class that implements the interface and all UI dependencies are hidden X3 SDF User s Manual 59 Linux Directory Structure X3 SDF User s Manual The predefined UserInterface interface class is defined in Applicationlo h The constructor of Applicationlo requires a pointer to the interface which is saved and used to perform the actual updates to the UI inside of Applicationlo s methods Applicationlo Initialization The main form creates an Applicationlo object in its constructor The object creates a number of Malibu objects at once as can be seen from this detail from the header Applicationlo h Innovative X3SDF Module IUserInterface Ul Innovative PacketStream Stream IntArray _Rx unsigned int Cursor 1164 BlocksToLog bool Opened bool Stopped bool StreamConnected Innovative StopWatch Clock Innovative DataLogger Logger IntArray DataRead Innovative BinView Graph Innovative Scripter Soript float ActualSampleRate std string Root Innovative AveragedRate Time double FBlockRate std string FVersion Innovative SoftwareTimer Timer In Malibu objects are defined to represent units of hardware as well as software units The X3 SDF object represent the board The PacketStream object encapsulates supported board specific operations Scripter object can be used to add a simpl
28. libraries Installing MemDriver And Controller Both MemDriver and controller are automatically installed by the Innovative software installation program setup bat Should the installation or driver failed please follow instructions under the Troubleshoot section below Running The Controller This applet displays MemDriver statuses and provide various control functions Please note any change to the MemDriver registry settings will require a system reboot Running the Applet 1 Go to folder C Innovative MemDriver Release utils MemDrvControl Vc9 Release or Release x64 2 Execute application MemDrvControl exe Following window will appear X3 SDF User s Manual 31 Linux Directory Structure X3 SDF User s Manual EUM OOOO TEES Registry Requested Memory Size MB Driver Memory Pool MB Max Used Free LFB Status Ready Version 142 Test Unknown Build Date Nov 21 2011 Refresh Applet Features and Notes l 4 de 6 If MemDriver failed to reserve desired amount of memory it will attempt to reserve the largest amount poosible However if it failed to reserve any memory at all the Status field will show Not Ready In this case set the Memory To Reserve value to a smaller value 50 of previous and reboot Valid values are between 1 and 4095 To reset memory driver and clear all allocated memory 1 Close all applications 2 Click Reset button To verify driv
29. loaded onto the target machine by the the Malibu LinuxRed RPM These procedures need to be completed for every target machine Malibu To develop software for a baseboard the Malibu packages also must be installed Malibu LinuxPeriphLib ver rel 1586 rpm Installs Malibu Source Libraries and Examples Other Software Our examples use the DialogBlocks designer software and wxWidgets GUI library package for user interface code If you wish to rebuild the example programs you will have to install this software as well wxWidgets wxWidgets http www wxwidgets org DialogBlocks Anthemion http www anthemion co uk org dialogblocks Baseboard Package Installation Procedure Each baseboard installation for Linux consists of one or more package files containing self extracting packages of compressed files as listed in the table below Note that package version codes may vary from those listed in the table Each of these packages automatically extract files into the usr Innovative folder herein referred to as the Innovative root folder in the text that follows For example the X5 400 RPM extracts into usr Innovative X5 400 ver A symbolic link named x5 400 is then created pointing to the version directory to allow a single name to apply to any version that is in use X3 SDF User s Manual 15 Board Packages X3 SDF User s Manual Board Packages EE eee X5 400M Malib
30. log if software alerts are enabled for display Host Side Program Organization The Malibu library is designed to be re buildable in each of three different host environments Borland C Builder Microsoft Visual Studio 2003 and Microsoft Visual Studio 2005 using the NET UI Because the library has a common interface in all environments the code that interacts with Malibu is separated out into a class Applicationlo in the files Applicationlo cpp and h This class acts identically in all the platforms The Main form of the application creates an Applicationlo to perform the work of the example The UI can call the methods of the Applicationlo to perform the work when for example a button is pressed or a control changed Sometimes however the Applicationlo object needs to call back into the UI But since the code here is common it can t use a pointer to the main window or form as this would make Applicationlo have to know details of Borland or the VC environment in use The standard solution to decouple the Applicationlo from the form is to use an Interface class to hide the implementation An interface class is an abstract class that defines a set of methods that can be called by a client class here Applicationlo The other class produces an implementation of the Interface by either multiple inheriting from the interface or by creating a separate helper class object that derives from the interface In either case the implementing class
31. na Storen to logic register address a la a n Fetch n from logic register address a p na Storen to port register address a p a n Fetch n from oort register address a ms n Delay n milliseconds All commands use postfix notation so parameters go before the command For instance 0x01 0x02 1 causes the value 0x01 to be stored to logic address 0x02 The Stream Data Fil es Log check box controls whether received packets are logged in real time If checked data will be accumulated until the limit specified in the Data Logging Samples edit box is reached The Stream streaming termin The Stream Data Fil ates to allow perusal of the acquired data stored in the disk file Data Fil es es Plot check box controls whether the BinView file viewer applet is invoked when Overwrite BDD check box controls whether a new BinView binary data descriptor file should be created as streaming terminates Normally this should be enabled so that a valid BDD is available for use by BinView when it 1s opened to view acquired data But under some circumstances such as when comments are added to the BDD file it may be desirable to avoid re creating the file each run During data flow the number of received data packets data transfer rate board temperature and current DIO pin state is shown in real time on the statistics status bar located at the bottom of the Streaming tab X3 SDF User s Manua
32. offset and scale factor are corrected by the logic This is a first order error correction where y mx b wherein x the input sample m gain correction and b offset correction The resultant samples are the error corrected output samples Trim range is about 1 25 for gain and 0 78 for offset Production Calibration Each X3 SDF is calibrated as part of the production tests performed The calibration results are provided on the production test report with each module The results of the calibration are stored in the on board EEPROM memory These calibration X3 SDF User s Manual 96 Linux Directory Structure X3 SDF User s Manual values are used by the logic to correct the analog errors and are loaded into the A D as part of the initialization by the software The calibration technique used determines the A D errors by first measuring the output with ground connected then a 9 8V source and a 9 8V source The measurements are the average of 64K samples at each test voltage From these three points across the input range the gain and offset errors are calculated All test voltages are measured as part of the procedure with NIST traceable equipment Production calibration is performed at room temperature 26C with the module operating temperature at about 50C Under normal circumstances calibration is accurate for one year For recalibration the module can be sent to Innovative or recalibrated using a similar test procedure
33. programming of Innovative hardware products under Windows and Linux Malibu supports both high speed data streaming plus asynchronous mailbox communications between the DSP and the Host PC plus a wealth of Host functions to visualize and post process data received from or to be sent to the target DSP What is C Builder C Builder is a general purpose code authoring environment suitable for development of Windows applications of any type Armada extends the Builder IDE through the addition of functional blocks VCL components specifically tailored to perform real time data streaming functions What is Microsoft MSVC MSVC is a general purpose code authoring environment suitable for development of Windows applications of any type Armada extends the MSVC IDE through the addition of dynamically created MSVC compatible C classes specifically tailored to perform real time data streaming functions X3 SDF User s Manual 11 Table of Contents X3 SDF User s Manual What kinds of applications are possible with Innovative Integration hardware Data acquisition data logging stimulus response and signal processing jobs are easily solved with Innovative Integration baseboards using the Malibu software There are a wide selection of peripheral devices available in the Matador DSP product family for all types of signals from DC to RF frequency applications video or audio processing Additionally multiple Innovative Integration baseboards can be us
34. right are non visual components in Builder Timer controls timer ticks and pop up menu facilitate user to select channels on right click where the folder controls the posting of a File Open Dialog box They will not appear in the running application User Interface This application has four tabs Each tab has its own significance and usage though few could be inter related All these tabs share a common area which displays messages and feedback throughout the operation of the program Logic Tab Capture Example DER Configure Setup Stream Zbt Ram EEProm Debug El E Eb Driver As soon as the application is launched device driver Target tt is opened and hardware is attached to target number a Bee Exo Logic File zero In this tab we configure user interface logic m The target board number is set to zero The order of the targets is determined by the location in the PCI bus so it will remain unchanged from run to run While application is being launched device driver is Event Log automatically opened for the baseboard and internal resources are allocated for use At this point stream is simply connected to the board and board has been reset to be in known good state Also if ID ROM is properly initialized module name and revision in addition to the Device Opened message is displayed in the message box Next we load the desired user interface logic The user logic for the module must be
35. speed data and over the command channel The packet system is the main data channel to the card and delivers the high performance real time data capability of moving data to and from the module Since it uses an efficient DMA system it is very efficient at moving data which leaves the host system unburdened by the data flow The command channel provides the PCIe host direct access to the computing core logic for status control and initialization Since it is outside the packet system it is less complex to use and provides unimpeded access to the logic The application FPGA image is loaded by the host computer as part of the module initialization The image is loaded over the SelectMAP interface to the FPGA which is a byte wide configuration port on the FPGA from the host PCI Express X3 SDF User s Manual 38 Linux Directory Structure X3 SDF User s Manual interface The configuration port for the FPGA 1s independent of the packet interface to the host and does not involve the use of the Velocia packet system The image can be loaded at any time over the SelectMAP interface allowing dynamic configuration of the FPGA for advanced applications Note There is no on card storage for this image and it must be loaded each time the host computer is powered down or reset Adding New Features to the FPGA The functionality of the computing core can be modified using the FrameWork Logic tools for the X3 module family The tools support development in ei
36. the Components to Install box checked If you do not wish to install a particular item simply uncheck it The Installer will alert you and automatically uncheck any item that requires a development environment that is not detected on your system 4 Click the Install button to begin the installation Note The default Product Filter setting for the installer interface is Current Only as indicated by the combo box located at the top right of the screen If the install that you require does not appear in the Product Selection Box 1 Change the Product Filter to Current plus Legacy X3 SDF User s Manual 24 Linux Directory Structure X3 SDF User s Manual Each item of the checklist in the screen shown above has a sub install associated with it and will open a sub install screen if checked For example the first sub install for Quadia Applets Examples Docs and Pismo libraries is shown below The installation will display a progress window similar to the one shown below for each item checked Quadia Documentation Thank you for choosing Quadia Installing Documentation Figure 3 Progress is shown for each section X3 SDF User s Manual 25 Linux Directory Structure X3 SDF User s Manual Tools Registration Registration Information User Name First Email Address Telephone Country Code Area Code Number Extension Fax Area Code
37. the machine back on to make certain everything is plugged in correctly Thank you from Innovative Integration 1 805 578 4250 www innovative dsp com Shutdown Now Shutdown Later Figure 6 Installation complete Click the Shutdown Now button to shut down your computer Once the shutdown process is complete unplug the system power cord from the power outlet and proceed to the next section Hardware Installation Hardware Installation Now that the software components of the Development Package have been installed the next step is to configure and install your hardware Detailed instructions on board installation are given in the Hardware Installation chapter following this chapter IMPORTANT Many of our high speed cards especially the PMC and XMC Families require forced air from a fan on the board for cooling Operating the board without proper airflow may lead to improper functioning poor results and even permanent physical damage to the board These boards also have temperature monitoring features to check the operating temperature The board may also be designed to intentionally fail on over temperature to avoid permanent damage See the specific hardware information for airflow requirements X3 SDF User s Manual 27 Linux Directory Structure X3 SDF User s Manual After Power up After completing the installation boot your system into Windows Innovative Integration boards are plug and play compli
38. variable resolution speed Xilinx Spartan3 1M Vibration measurement A D up to 24 bit 5 MSPS or 16 bit 20 2M option acoustics wide dynamic MSPS gt 100 dB below 2 5 MSPS range applications X3 25M Two channels of 25 MSPS 16 bit A D and Xilinx Spartan3A DSP 1 8M Ultrasound pulse digitizing two channels of 16 bit 50 MSPS DAC 16 waveform generation and bits front panel DIO stimulus response X3 A4D4 4 channels of 16 bit 4 MSPS A D and 4 Xilinx Spartan3A DSP 1 8M Servo controls process channels 16 bit 2 MHz DAC with low instrumentation latency 8 bits front panel DIO X3 Servo 12 channels 16 bit 250 ksps A D and 12 Xilinx Spartan3A DSP 1 8M Electromechanical controls channels 16 bit 250 ksps DAC low 3 4M option process instrumentation latency 16 bits front panel DIO X3 DIO 64 bits 32 pairs digital IO to FPGA Xilinx Spartan3A DSP 1 8M Test pattern generation LVCMOS or LVDS with streaming 3 4M option remote IO interfaces digital playback and capture features controls X3 10M 8 channels of 16 bit 25 MSPS A D with Xilinx Spartan3A DSP 1 8M Measurement for high speed programmable gain and instrumentation vibration ultrasound fault front end Xilinx Spartan3A DSP FPGA detection systems neurophysical applications X3 2M 12 channels of 16 bit 10 MSPS A D with Xilinx Spartan3A DSP 1 8M Multi channel applications in programmable gain and instrumentation ultrasound video sensors and front end Xilinx Spartan3A DSP FPGA optical
39. 000 Set up a read from PLL address X 40 BARI 0xA X x01303xx See format below Table 21 PLL Read Sequence X3 SDF User s Manual 86 Linux Directory Structure X3 SDF User s Manual The PLL readback word has the following format The PLL read must be performed before any additional writes are performed 30 24 0000000 Data byte don t care for reads Table 22 PLL Read Word Notes About Programming the PLL The PLL an Analog Devices AD9510 device must be initialized prior to use This device has many configurations that require programming of a large number of registers prior to use The X3 SDF support software provides PLL configurations that satisfy most applications and should be used if possible For custom configurations the AD9510 data sheet should be consulted The X3 SDF uses the AD9510 for five output clocks one for each A D channel plus one for the FPGA These clocks are connected as shown in the following table The FrameWork Logic is predicated on the all of the channels operating synchronously therefore the AD9510 is programmed so that all channels have the same clock output with the same phase The PLL should be programmed to use these outputs with the signal type noted AD9510 Output Signal Type FPGA Channel 0 LVPECL AID 3 Tt CMOS Table 23 PLL Output Assignments The VCO used with the AD9510 has a tuning range of 100 to 140 MHz and is connected to the CLK2 input to the PLL The s
40. 3 SDF User s Manual 60 Linux Directory Structure X3 SDF User s Manual certain events detected Events allow a tight integration between an application and the library These events are informational messages issued by the scripting and logic loader feature of the module They display feedback during the loading of the user logic and when script 1s used del Alerts Module Alerts OnTimeStampRolloverAlert SetEvent this amp ApplicationIlo HandleTimestampRolloverAlert Module Alerts OnSoftwareAlert SetEvent this amp ApplicationIo HandleSoftwareAlert Module Alerts OnWarningTemperature SetEvent this amp Applicationlo HandleWarningTempAlert Module Alerts OnPllLost SetEvent this amp ApplicationIlo HandlePllLostAlert Module Alerts OnInputFifoOverrun SetEvent this amp ApplicationIo HandleInputFifoOverrunAlert Module Alerts OnInputTrigger SetEvent this amp ApplicationIo HandleInputTriggerAlert Module Alerts OnInputOverrange SetEvent this amp ApplicationIlo HandleInputFifoOverrangeAlert This code attaches alert processing event handlers to their corresponding events Alerts are packets that the module generates and sends to the Host as packets containing out of band information concerning the state of the module For instance if the analog inputs were subjected to an input over range an alert packet would be sent to the Host interspersed into the data stream indicating the condition This informat
41. B making it ideal for acoustic and vibration measurement applications A high performance computing core for signal processing data buffering and system IO is built around a Spartan3 1M gate FPGA Supporting peripherals include 2MB of SRAM conversion timebase and triggering circuitry 44 bits digital IO and a PCI Express interface The module format is a single slot XMC and is compatible with XMC 3 host sites Figure 13 X3 SDF Module Custom application logic development for the X3 SDF is supported by the FrameWork Logic system from Innovative using VHDL and or MATLAB Simulink Signal processing data analysis and application specific algorithms may be developed for use in the X3 SDF logic and integrated with the hardware using the FrameWork Logic Software support for the module includes host integration support including device drivers XMC control and data flow and support applets X3 SDF User s Manual 77 Linux Directory Structure X3 SDF User s Manual X3 SDF Block Diagram Ext Clk Triggers 1 0 Figure 14 X3 SDF Block Diagram Hardware Features A D Converters The X3 SDF has four channels of 24 bit A D sampling at up to 5 MSPS using a four of Analog Devices AD7760 The AD7760 is a sigma delta converter that has programmable filters and decimation allowing trade offs in resolution and output data rates over a range of 1 ksps to 5 MSPS X3 SDF User s Manual 78 Linux Directory Structure X3 SDF User s Manual
42. DF Mechanicals Top View Rev A X3 SDF User s Manual 123 Linux Directory Structure X3 SDF User s Manual X3 SDF User s Manual 124
43. Es you plan to use for Host development If you are planning on using these environments it is imperative that they are tested and known operational before proceeding with the library installation If these items are not installed prior to running the Innovative Integration install the installation program will not permit installation of the associated development libraries However drivers and DLLs may be installed to facilitate field deployment You must have Administrator Privileges to install and run the software hardware onto your system refer to the Windows documentation for details on how to get these privileges X3 SDF User s Manual 22 Linux Directory Structure X3 SDF User s Manual Starting the Installation To begin the installation start Windows Shut down all running programs and disable anti virus software Insert the installation DVD If Autostart is enabled on your system the install program will launch If the DVD does not Autostart click on Start Run Enter the path to the Setup bat program located at the root of your DVD ROM drive 1 e E Setup bat and click OK to launch the setup program SETUP BAT detects if the OS is 64 bit or 32 bit and runs the appropriate installation for each environment It is important that this script be run to launch an install When installing on a Vista OS the dialog below may pop up In each case select Install this driver software anyway to continue Don t install th
44. Hz fixed 0 24 576 MHz oscillator as the PLL reference 1 2 PXI 100M PLL CLKA SEL External Clock Mux Selects either Ext CIk or PXI DSTARA as 0 Ext Clk input to the clock distribution 1 PXI DSTARA Table 17 X3 SDF External and Reference Clock Selection To use an external clock the external clock multiplexer must be configured to select either the front panel external clock or the PXI DSTARA input on P16 The control signal PLL CLKA SEL is from the application logic FPGA and is set by the host software when the standard logic image is used The external clock multiplexer output is the CLK1 input to the AD9510 so the AD9510 must be configured to use CLK1 as the source to the output distribution section of the device The following diagram shows the clock path when an external clock is used PLL REF SEL PXI 100MHz J P16 ae Ext Clock Input P1 PXI DSTARA P16 PLL CLKA SEL FPGA FPGA Figure 17 X3 SDF External Clock Path The reference clock to the PLL is also software programmable The external reference clock multiplexer must be configured to select the reference clock to the PLL as either the 24 576 MHz oscillator or the PXI_100M input on P16 The control X3 SDF User s Manual 83 Linux Directory Structure X3 SDF User s Manual signal PLL REF SEL is from the application logic FPGA and is set by the host software when the standard logic image is used All external clock and reference
45. Innovative Integration X3 SDF User s Manual X3 SDF User s Manual The X3 SDF User s Manual was prepared by the technical staff of Innovative Integration on November 29 2011 For further assistance contact Innovative Integration 2390 A Ward Ave Simi Valley California 93065 PH 805 578 4260 FAX 805 578 4225 email techsprt innovative dsp com Website www innovative dsp com This document is copyright 2011 by Innovative Integration All rights are reserved VSS Distributions SDF Y Documentation Manual 1 SDFMaster odm HZXXXXXX Rev 1 0 Table of Contents X3 SDF User s Manual Table of Contents Last of Tables entente UU EH 8 TASH OF FI Ure ssc zov eie REO ET REIN seid 9 TCO DU CON e LO Real Time Solutions ieeeecce e eere oe ka eae Vete So ka eee e so sve cua ao Paca ee sebo sab Sese cdsconenssssdeascecsevencesadesasdecooauodseese LO A om ET What is XIS DET enra a i e EEA eR IINE REG T ATE UHR ER ERU BO EROTR UGG NUT TE R 11 What 1s Malibu uu aue ne ert t vecino I RE HE aad RERO ERR UE CE PR UON GEI eR 11 Whatis C tt Builder eee aeta tear e UR EEUU pete ee Ge re EE UPPER 11 What is Microsoft MSW 2 0 eis eia A een RN ap E ENERO ERR 11 What kinds of applications are possible with Innovative Integration hardware esee 12 Why do I need to use Malibu with my Baseboard sese nennen enn 12 Finding detailed information on Malibu
46. Module IdRom Name Settings ModuleRevision Module IdRom Revision Settings PllCorrection static cast float Module Clock ReferenceCalibrationFactor for int ch 0 ch Channels ch Settings AdcGain ch Module Input Gain ch Settings AdcOffset ch Module Input Offset ch Settings Calibrated Module Input Calibrated X3 SDF User s Manual 70 Linux Directory Structure X3 SDF User s Manual Developing Host Applications Developing an application will more than likely involve using an integrated development environment IDE also known as an integrated design environment or an integrated debugging environment This is a type of computer software that assists computer programmers in developing software Refer to Chapter 3 Creating Applications using an IDE within the Malibu Library Users Manual for specific instructions for each of the supported compilers X3 SDF User s Manual 71 Linux Directory Structure X3 SDF User s Manual Applets The software release for a baseboard contains programs in addition to the example projects These are collectively called applets They provide a variety of services ranging from post analysis of acquired data to loading programs and logic to a full replacement host user interface The applets provided with this release are described in this chapter Shortcuts to these utilities are installed in Windows by the installation To inv
47. Number Company Name Address City State Country Postal Code Product Boarg M6713 E 2 Help E Register Now Register Later Figure 4 ToolSet registration form Bus Master Memory Reservation Applet Reserve Memory for Dsp Combined DSP Board Usage Rsv Region Size MB Configuration Total physical memory MB 2047 Non paged pool size MB 256 Status Ok Update Help Exit Ready Figure 5 BusMaster configuration X3 SDF User s Manual At the end of the installation process you will be prompted to register If you decide that you would like to register at a later time click Register Later When you are ready to register click Start All Programs Innovative Board Name Applets Open the New User folder and launch NewUser exe to start the registration application The registration form to the left will be displayed Before beginning DSP and Host software development you must register your installation with Innovative Integration Technical support will not be provided until registration is successfully completed Additionally some development applets will not operate until unlocked with a passcode provided during the registration process It is recommend that you completely fill out this form and return it to Innovative Integration via email or fax Upon receipt Innovative Integration will provide access codes to enable technical support and unres
48. O port bits or timer input pins should be limited to a voltage range between 0 and 3 3V referenced to ground on the digital I O port connector Exceeding these limits will cause damage to the X3 module Digital I O Timing The following diagram gives timing information for the digital I O port when used in external readback clock mode see above for details This data is derived from device specifications and is not factory tested Extemal Readback Clock Input data V Data Valid V Figure 12 Digital I O Port Timing Table 9 Digital I O Port Timing Parameters Ho p X3 SDF User s Manual 45 Linux Directory Structure X3 SDF User s Manual Digital IO Electrical Characteristics The digital IO pins are LVTTL compatible pins driven by 3 3V logic The DIO port connects directly to the application FPGA The DIO input clock is LVDS a differential input Warning the DIO pins are NOT 5V compatible Input voltage must not exceed 3 6V Parameter Value Notes Input Voltage Max 3 6V Exceeding these will damage Min 0 3V the application FPGA Output Voltage 3 0V For load lt 12mA 0 lt 0 8V Output Current 12mA FPGA can be reconfigured for custom designs for other drive currents Input Logic 1 gt 2VDC Thresholds 0 lt 0 8VDC Input Impedance 21M ohm 15 pF Excludes cabling Pulldown 8K ohms Pulldown is in the logic Table 10 Digital IO Bits Elec
49. OS system calls such as GUI updates from within your handler unless you marshal said processing into the foreground thread context void ApplicationIo HandleDataAvailable PacketStreamDataEvent amp Event if Stopped return static PmcBuffer Packet Extract the packet from the Incoming Queue Event Sender gt Recv Packet When the event is signaled the data buffer must be copied from the system bus master pool into an application buffer The preceding code copies the packet into the local PmcBuffer called Packet Process the data packet int Channel Packet Header gt PeripherallId Discard packets from sources other than analog devices if Channel gt Channels return Each PmcBuffer consists of a header and a body of data The header may be interrogated to determine the data source In the fragment above packets containing peripheral IDs greater than the number of enabled channels are discarded Consequently alert packets are not retained or processed Calculate transfer rate in KB s double KBytes Packet Size sizeof int 0x400 double Period Time Differential if Period FBlockRate KBytes Period The code fragment above calculates the nominal block processing rate The AveragedRate object Time maintains a moving averaged filtered rate This rate is stored in FBlockRate for use by display method of the GUI if Settings LoggerEnable amp amp Logger Logged
50. ROM device is an Atmel AT24C16 or equivalent Caution the serial EEPROM contains the calibration coefficients for the analog and is preprogrammed at factory test Do not erase these coefficients or calibration will be lost Thermal Protection and Monitoring X3 modules have an on card temperature sensor that monitors the module and protects it from thermal damage The application software can monitor the module temperature and receive a warning if the temperature is above 70 C If the temperature exceeds 85C the module will shut down devices to prevent damage The temperature sensor is accurate to about 2 deg C with a resolution of 0 0625C Since it is mounted near the center of the card it indicates an average temperature not the maximum on the module Local hot spots may be 5 to 10 C hotter than the indicated reading The temperature sensor can be read by the host at address PCI BARO 0x3 The temperature is computed as Temperature C reading 0 0625 where the reading is a 12 bit signed number This table summarizes the relationship C BINARY 10 onoomooxo 65 o a07 e000 0000 8S 25 9010109 19 os 0X03x0090 Q4 0 9000p00x0 X9 Table 5 Temperature Data Format X3 SDF User s Manual Linux Directory Structure X3 SDF User s Manual The logic component provides a programmable temperature warning BARO 0x4 and failure BARO 0x5 The warning and fail may crea
51. This usually requires that the module be restarted when conditions permit The data acquisition alerts including over ranges overflows and triggering tell the system that important events occurred in the data acquisition process Overflow is particularly bad data was lost and the system should try to alleviate the system by unclogging the data pipe or just start over If you get an overrange alert then the data may just be bad for a while but acquisiton can continue Modules with programmable input ranges can use this to trigger software range changes Software alerts are used to tag the data Any message can be made into an alert packet so that the data stream logged includes system information that is time correlated to the data X3 SDF User s Manual 93 Linux Directory Structure X3 SDF User s Manual Table 26 Alert Types Alert Purpose Timestamp rollover The 32 bit timestamp counter rolled over This can be used to extend the timestamp counter in software Software Alert The host software can create alerts to tag the data stream Over Temperature Alarm Sensor Failure The module temperature exceeded 85C Temperature Warning The module temperature exceeded 70C PLL Lost The sample clock PLL lost lock The PLL must be reconfigured ADC Queue Overflow The ADC data queue overflowed indicating the the host did not consume the data quickly enough ADC Trigger The ADC trigger wen
52. additional queues for new devices EEPROM A serial EEPROM on the X3 modules is used to store configuration and calibration information The interface to the serial EEPROM is an I2C bus that is controlled by the PCI logic device The device is an Atmel AT24C16 10SI a 16K bit device The I2C bus is slow and the calibration is read out of the EEPROM at initialization time by the application software and written into registers in the application logic for real time error correction The EEPROM also has a write cycle limit of 100K cycles so it should only be written to when calibration is performed or configuration information changes Once the write cycle duration limit 1s exceeded the device will not reliably store data any more X3 SDF User s Manual 41 Linux Directory Structure X3 SDF User s Manual Digital I O The X3 modules have a digital IO port and is accessible over P16 that provides basic bit IO The port provides 44 bits of IO that may be used as inputs or outputs and a differential clock input The port is configured and accesses directly from the PCI Express host For more advance applications digital IO port may be reconfigured in custom logic applications for a variety purposes since it provides direct connections to the applicant FPGA The DIO port is presented on P16 See the connectors section of this chapter the connector pin out and information about the connector Software Support The digital I O hardware is cont
53. ains files associated with programming the board Logic and any logic images provided X3 SDF User s Manual 17 Linux Directory Structure X3 SDF User s Manual Mem Driver Installation Linux This document provide instructions to install and use the Innovative Integration memory driver MemDriver and controller applet for Linux Releases See the README txt file Tested System Configuration 4 GB Core2 openSUSE 11 1 x32 and x64 Linux Kernel 2 6 27 45 Malibu Applications In order to utilize MemDriver all Malibu based applications must be linked against the latest release of Malibu libraries Installing MemDriver The MemDriver for Linux is a boot start driver In such this driver must be linked into the Linux kernel and executed during system boot up Perform the following steps to build and link the driver into the kernel Obtain the source for the Linux kernel listed in section Minimum System Requirement 2 Copy the folder usr Innovative MemDriver memdrv to your kernel source gt drivers 3 Edit the file lt your kernel source gt drivers Kconfig Add the line source drivers memdrv Kconfig quotes included before the line endmenu Save the changes 4 Edit the file lt your kernel source gt drivers Makeflie Add the line obj y memdrv to the end of this file Save 5 Go to the kernel root folder Perform the steps listed under the section Adjusting Memory Pool Size Be sure a check mark appears beside th
54. ant allowing Windows to detect them and auto configure at start up Under rare circumstances Windows will fail to auto install the device drivers for the JTAG and baseboards If this happens please refer to the TroubleShooting section Installation on a Deployed System The above instructions install the complete development platform onto a system for the development of application software Often however a developed application needs to be installed on a system that will only be used to run the program In this instance installing the complete library is overkill To support this situation Innovative has a minimal installation program called MalibuRED This is short for Malibu Redistributable This install will install the driver software and support DLLs required to run a Malibu application Note Specific applications may have their own additional requirements that are not covered by MalibuRED For example NET applications require the NET libraries to be installed as well Installation programs for NET can be obtained from Microsoft over the Internet Running MalibuRed MalibuRED can be found on the installation CD in the Windows 32 Malibu subdirectory The name of the installation file is MalibuRED exe Running the program displays the setup screen for the installer Select your baseboard i pan Using the combo box select the appropriate baseboard to install support for In this case we are insta
55. anything discolored or do any ICs show evidence of damage This may be due to device failure system power problems or from overheating If damage is noticed the module is suspect and should be sent for repair If not test the module outside the system in a benign environment such as on an adapter card in a desktop PC with a small fan It should not overheat If it does this module is now bad Now consider what may have caused the failure A bad module could be the cause but it could have went bad due to system failure or overheating The system power supply could cause a failure by not providing proper power to the module This could be too little power resulting in the module failing or power glitches causing the temp sensor to drop out Did other cards in the system fail If so this may indicate that a system problem must be solved If the module did overheat you should review the thermal design of the system What was the ambient temperature when failure occurred Is the air flow adequate Is air flow blocked to the card Did a fan fail If conduction cooling is being used what is the temperature of the surrounding components The heat must be dissipated either through conduction or convection for the module to keep from overheating You should also review application and be sure that you have taken advantage of any power saving features on the module Many of the X3 modules have power saving features that allow you to turn off unused channels
56. are or rising edge of Software or falling edge of external trigger external trigger Framed N sample points for each of Software or rising edge of Stops when N samples are the enabled channel pairs external trigger collected back Decimation M points are discarded for every point kept May be used with either trigger mode Table 2 Trigger Modes On the X3 SDF module the sample rate is a fraction of the A D clock rate because the A D uses multiple clocks for its conversion process The effective sample rate Fs is a sub multiple of the A D clock rate The trigger component operates at the sample rate for its data collection process So even though a 100 ksps data from the A D may use a 24 576 MHz A D clock the trigger components collects the data based upon the 100 ksps data rate DRDY Trigger Analog Input Samples are acquired when trigger is true on rising edges of Fs when trigger is true Figure 18 Analog Triggering Timing As shown in the diagram samples are captured when the sample is ready DRDY and the trigger are true For the X3 SDF the sample clock to the A D is a multiple of the sample rate as determined by the decimation setting in the A D The trigger is true in continuous mode after a rising edge on the trigger input software or external until a falling edge is found The trigger is synchronized to the sample ready and has a 0 to 1 A D c
57. bugging iniri aee eee dd ER 59 Host Side Program Organization cete ad dea 59 Applicati nIo i agn pte t e pere a e pq eto T ERR GR e HP RE RN REA 60 Initialization dete n RHODE Rede e ode n ER MT et ect 60 Logic Loading arce e HE aa 63 Starting Data flow sec EA 64 Handle Data Required Re Ree ed d e e SER e A Ete ERA 67 EEBProinACCeSS d e odor oem er e o RD E e ER ER 69 Developing Host Application dee eite L FOU arar ts TZ COMMON quee ici TZ Registration Utility NewUSser exe cccccscesscsssessessecsscesecseeeseesecsesesecseeesesseessecseeesecaeeaeesecsesesecsecesesaeesseceeesaeseneceeeenenteesaes 72 Reserve Memory Applet ReserveMemDSp CXO coooococonoonoonnonooonoonconnonnonnncn nooo non non nn nennen neret enr nnne nnne nne nennen nnne 73 Data AMIALY SISZA QUIC PORRO MERERI Binary File Viewer Utility BinView eX6 oooncnnncccnnoncocnonnconconncnnnnnnonnnon nono nennen nennen enne A eter e nere enne nnne erret 73 Applets for the X3 SDF BasebOaEd eerte cenare nter suse ob io nen e tao ano so ea caen i6 nE asp en s aoa sas I nano ee zRasE i oi ch aba ea 14 Logic Loaders x32 o de ea Me odo el SHINE 75 PCI Configuration Utility Config CXO ooconccoionnnonnononnnoonconnconcnnncnnrnn non ron ron non n nan nn RR nn RR e nenne nene nn nnne ennt innen nnn nnns 76 MSDN Collection Integration Utility ono rnnn non n ran r nn nr nn rn nn nnne nn enne enirn enne enne 76 X3 SDE Hard Ware 3iseeesaeee te eab eee
58. c cisssocsesssassccossensacsesnndcsasssesncsshoasseaseanseccsisvsnssstonsastetesseoassseossadense D D System Thermal Desi EUR 92 Temperature Sensor and Over Temperature Protection ener enne nrn nennen 92 Reducing Power Cons mptlori ct De Ue n M DN TAM 92 PICU etr X E E dmt E Nl xta 93 Types of Alerts c eet tede te e i pe e ee e I EG ER EHE EH Eee e I id 93 Alert Packet Format 4 eS ee ee CU eee rtp teet et Qe tete e EE T eS eie e ee de 94 Software SUpDOTo d Adeste tO eet ae e ra 95 Tagging the Datars trea o eee aepo e nt mE 95 Using tlie X3 SD E iode eto renovare ado Where to Start iae au A tdi E 95 Getting Good An log Performance nim eet onde ini te drea ie pie ROS U QU EDEN e ets 95 Application Logic ns ERG A idet dee ORT QS d Pete rete ded 96 erii citoim TL ET Production Calibration RR 96 Updating the Calibration Coefficients ssesssssssssssseseseeeeeeene nennen erinnere nere innen enr nne nn nennen innen 97 Performance Datacivcsciccicciciscccccssccscasaisediedescsscedciectevdessescedaisccesesedsoodciacecvdesedsoodadacdendesedsoodcdaccuassssetessasensss UN Power Cons mption tacto 98 IA RN 99 Duran ee ts A O eE REN EEE 99 O O RO NA Input Connector JP dias e dans Per ER CARERE ee dee ios 112 XMC PIS Connector as nre Ree d e ae e p t er e e He dat i ep HH Alias 114 XMC PI6 Connectot c otro ete etae ig ri PO EHE a PERDE ORE E e 117 Note PXI Express signals are only availabl
59. control 0 input default 2 DIO bits 23 16 direction control 0 input default 3 DIO bits 31 24 direction control 0 input default 4 DIO bits 39 32 output enable 0 input default 5 DIO bits 43 40 output enable 0 input default 30 6 31 Sample DIO inputs when DIO EXT CLK is true otherwise always sample 0 sample always default X3 SDF User s Manual 44 Linux Directory Structure X3 SDF User s Manual Figure 10 DIO Control Register BAR1 0x14 Port Address DIO L BAR1 0x13 DIO H BARI 0x16 Figure 11 Digital IO Port Addresses Data may be written to read from the digital I O port using the digital I O port data registers Data written to ports bits which are set for output mode will be latched and driven to the corresponding port pins while data written to input bits will be ignored The input DIO may be clocked externally by enabling the external digital clock bit in the appropriate configuration register If the internal clock is used the data is latched at the beginning of any read from the port Data read from output bits is equal to the last latched bit values i e the last data written to the port by the host Digital I O port pins are pulled down to digital ground within the logic device Consequently the state of the DIO pins do not change as power is applied to the PC during system start up The pulldown resistor is about 8K ohms External signals connected to the digital I
60. cw epaa eo Deoa sesoses raana base eee Poo dose eb sedosccnecscdeoscsdosccasscodeossscedessyeaosesseavea T T Intr ductnis TN 17 Hardware F atUEes 52 2 2 2 eee o oo n eoo e eee eub ob TR oo a eere ee apos Da abo ee ideesse b san a eese ee aiee oaie ee usabog vas eae cass ue bo aos ae 78 AD COBVettetsa dien em rem oe P EI eti tte P eed e dati abe eoi nde o else b ENG 78 Input Range and Conversion Codes cci indagado deidad 80 X3 SDF User s Manual Table of Contents X3 SDF User s Manual Driving the A D Inputs ou eR e E SR RERO IU UU NN ERE eS IU UE RENTA TR 81 Overrange Detection rest D DEOS REU VAR A ERE SR ERU SEED FG UHR E RR EXE VERE de 81 Sample Rate Generation and Clocking Controls eee e eene eee e eere neenon nee eneseessssseeees O L External Clock and Reference InputS oooncnnncicnnonnnonconcnononnconnonncon non ron nn nr nn nennen nne enne entren innen ran rra rennen enne 82 Generating a Sample Clock with the PEL ooooooconcnnncniccnnnnocnconcoononncnnncnnonnnonncnn non ron ron nnnnn rn ron rro n non n rn nne nr eren nnne nennen 84 A repe ee eo pet ce e eget ON 86 PLL teta EM 86 Notes About Programming the SA 87 Tirng Analysi eee eere eh ie qp aen dott me ait e desse et E E Ad E ERE IRR e eet 88 A MU Trigger SOULCE EP 89 Framed Trigger Mode iie teat e asi d bsc stand ol dst tu ON 90 DECIMO M DRE 90 FrameWork Logic Funcional o rs D Power Controls and Thermal Desiginsis
61. designed to include conduction cooling to improve heat dissipation from the module These features can make the module more reliable in operation and also reduce power consumption X3 SDF User s Manual 91 Linux Directory Structure X3 SDF User s Manual System Thermal Design The X3 SDF dissipates about 8 watts typically for all A D channels running at full rate When operating in a room temperature environment at about 27C module temperatures do not exceed 60C even without forced air flow If the environment is more demanding you will need to carefully consider how to cool the module Forced air cooling is used in may compact PCI installations and this is very effective If forced air cooling is not used conduction cooling is another method of dissipating the module heat A thermal plane in the card is attached to the center stripe on the card The card can then be cooled by mounting the card on host card that supports conduction cooling per VITA specification 20 The conduction cooling method allows the module heat to be flowed out to the chassis The thermal plane has NO electrical connection in the module and cannot be used as a ground Temperature Sensor and Over Temperature Protection The temperature sensor is described in detail in the Board Basics chapter of this manual The temperature sensor is used to monitor the module temperature and protect it from overheating Temperature readings from the module are provided for system monitori
62. e Use the normal power mode for the A D if possible It gives 6 dB better noise performance e Reference input signals to the module ground Be sure not to introduce ground loops e Provide sufficient signal strength to drive the input The X3 SDF has about 2K input impedance Be sure you can drive this without distorting your signals If you decide to test the X3 SDF to verify its performance be aware that most signal sources are not good enough without additional filtering and careful use Most single ended lab instruments are limited by their distortion to about 90 dB Post filter is necessary to clean them up if you want to test the X3 SDF Application Logic The application logic must be loaded after every system boot up or reset There is no on card storage for the logic image The logic can be loaded using the LogicLoad software applet or 1s loaded as part of the application itself such as SNAP If you write your own application you will need to either use LogicLoad or incorporate a logic loader in the application The code in SNAP is a good example of how to do this Calibration Every A D sample is error corrected on the X3 SDF module in real time by the A D converter AD7760 This error correction is done before the samples are in the FPGA and is done digitally This results in improved performance and reliability for the module because the error correction does not change over time or temperature The basic error terms for
63. e MemDriver module i e it is set to Y See image below 6 Continue to Adjusting Memory Pool Size section Adjusting Memory Pool Size In order to adjust the memory pool size a rebuild of the Linux kernel is required 1 Ina terminal sheel login as root 2 Goto the root folder of the new kernel source and type make gconfig 3 This window will appear X3 SDF User s Manual 18 Linux Directory Structure X3 SDF User s Manual Linux Kernel v2 6 27 45 Configuration gt Ne e File Options Help m E Load 1 Single Split Full Collapse Expand Options Name IN m fy value 4 Multimedia devices Graphics support Sound card support NEW SOUND _M_M IY HID Devices NEW HID SUPPORT E Y Y Y USB support NEW USB SUPPORT YY MMC SD card support NEW MMC _M_m Sony MemoryStick card support EXPERIMENTAL NEW MEMSTICK _M_m Y LED Support NEW NEW LEDS Y O Accessibility support NEW ACCESSIBILITY N LN InfiniBand support NEW INFINIBAND M_M V EDAC error detection and reporting EXPERIMENTAL NEW EDAC NUN Real Time Clock NEW RTC CLASS _M_M Y Auxiliary Display support NEW AUXDISPLAY _ Y Y Userspace I O drivers NEW Ulo _M_M V Staging drivers NEW STAGING _ YY Innovative Memory Driver support NEW INNOVATIVE_MEMDRV __YY Memory Pool Size megabyte NEW INNOVATIVE_MEMDRV_POOL_SIZE 500 Firmware Drivers File systems Kernel hacking Security opt
64. e next trigger edge is detected If Trigger Frame Auto Retrigis checked and the Trigger Source is software the application automatically re triggers upon completion of processing of the previous packet This mode is ideal for application such as spectral analysis using fixed input buffers submitted to FFTs Digital I O Group These controls govern the configuration of the DIO port on the module The DIO port can be configured for input or output on a byte wise basis as a function of the configuration code in Digital I O Config Mask See the DIO Control Register description user logic offset 0x14 for details Data Logging Group These controls govern the size of data files created by the application containing packet data received from the module during real time streaming The value of Data Logging Samples sets the upper bound on the number of stored events samples from each channel If the Data Logging Auto Stop checkbox is checked streaming will automatically terminate once the specified number of events has been collected and logged to disk Test Counter Group Use this control to enable a logic specific test mode if you are developing custom FPGA logic If you are using the stock factory supplied logic bit zero of the Test Register user logic offset 0x02 is controlled by Test Counter Enable which forces an incremental ramp to replace A D data from each channel Low Power Group This puts all A Ds into a low power mode The perfor
65. e scripting language to the application for the purposes of performing hardware initialization during FPGA firmware development PmcBuffer class object can be used to access buffer contents In addition under this constructor we hook up event handlers to various events Hook script event handlers Script OnCommand SetEvent this amp ApplicationIo HandleScriptCommand Script OnMessage SetEvent this amp ApplicationIo HandleScriptMessage Configure Module Event Handlers Module Logic OnFpgaFileReadProgress SetEvent this amp ApplicationIo HandleProgress Module Logic OnFpgaFileReadComplete SetEvent this amp ApplicationlIo HandleParseComplete Module Logic OnFpgaParseProgress SetEvent this amp ApplicationIo HandleProgress Module Logic OnFpgaParseComplete SetEvent this amp ApplicationIo HandleParseComplete Module Logic OnFpgaParseMessage SetEvent this Applicationlo HandleLoadError Module Logic OnFpgaLoadProgress SetEvent this amp Applicationlo HandleProgress Module Logic OnFpgaLoadComplete SetEvent this amp Applicationlo HandleLoadComplete Module Logic OnFpgaLoadMessage SetEvent this amp ApplicationIlo HandleLoadError This code attaches script event handlers and X3 SDF logic loader s informational event handlers to their corresponding events Malibu has a method where functions can be plugged into the library to be called at certain times or in response to X
66. e software and hardware installation procedure for the Windows platform WindowsXP Vista and Windows 7 Do NOT install the hardware card into your system at this time This will follow the software installation Host Hardware Requirements The software development tools require an IBM or 100 compatible Pentium IV class or higher machine for proper operation An Intel brand processor CPU is strongly recommended since AMD and other clone processors are not guaranteed to be compatible with the Intel MMX and SIMD instruction set extensions which the Armada and Malibu Host libraries utilize extensively to improve processing performance within a number of its components The host system must have at least 1 GB of memory 2 GB recommended 1 GB available hard disk space and a DVD ROM drive Most versions of Windows released after Win2000 including XP Vista or Windows 7 referred to herein simply as Windows or later 1s required to run the developer s package software and are the target operating systems for which host software development is supported Software Installation The development package installation program will guide you through the installation process Note Before installing the host development libraries VCL components or MFC classes you must have Microsoft MSVC Studio version 9 or later CodeGear RAD Studio 2007 2009 Embarcadero Rad Studio 2010 or QtCreator installed on your system depending on which of these ID
67. e to multiple outputs either the PLL or one of two external clock inputs The PLL reference is also selectable from either fixed 24 576 MHz clock oscillator or an external input allowing the sample clock to be phase locked to an external reference signal The PLL can generate many sample rates that suit most applications The advantage of using the PLL is that the sample clock is very clean and provides the highest signal quality The output frequency of the PLL is programmable and is determined by the reference clock rate and the VCO tuning range The discussion in the following PLL section gives details of its programming and use Software functions for PLL configuration monitoring and clock distribution are provided in Innovative s Malibu software toolkit that configure the operating mode and sample rate required for the desired A D data rate This takes into consideration the A D frequency limits decimation factor in the A D and adjusts the PLL when in use to within its specified operating range X3 SDF User s Manual 81 Linux Directory Structure X3 SDF User s Manual PLL REF SEL PXI 100MHz P16 L Pig Ext Clock Input P1 PXI DSTARA P16 PLL CLKA SEL FPGA FPGA Figure 16 X3 SDF Clock Generation and Controls Block Diagram The PLL is software programmable and uses either fixed 24 576 MHz reference clock or an external reference clock The standard configuration for th PLL has a tuning range fr
68. e when PXIE adapter card is used see 120 Xilinx JE AG Connector ee eee E ON 121 X3 SDF User s Manual Table of Contents X3 SDF User s Manual lU CIEIMMVIENEOT RU I E X3 SDF User s Manual Table of Contents X3 SDF User s Manual List of Tables Fable 1 X3 X MG Family s sace tete EU E RO 36 T ble 2 X3 XMG Family Peripherals ee adas 37 T ble 3X3 Computng Core Devices aue ee a rete e dut c ndun redd 37 T ble 4 PCT Express Standards Compliance EE ER 39 Table 5 Interfaces from PCI Express to Application LOgic c cceccccscessesseesseeseceeeeseeceeseeaeeseceeeeaecnaesaeenseseeenseseeeeseeeneseeeaes 40 Table 6 IUsesExtendedDioPort Class Operations essent nnn nennen 42 Table 7 Table 1 Front Panel DIO on X3 Modules nennen enne 44 Table 8 IUsesExtendedDioPort Class Operations esses eene nnne nennen enne n eren 44 Table 9 Digital VO Port Timing Parameters enata m sn e eie ed te HER Ce eR s 45 Table 10 Digital IO Bits Electrical Characteristics nennen enne nnne nnne nre rennen 46 Table 11 Digital IO Clock Input Electrical Characteristics essere 47 Table 12 Temperature Alarmas ee ERE ERG A ENERO GER ERE ERU a aco eed 49 Table 13 X3 Modules FPGA JTAG Scan Path sess enne nnne eren enne E R E nnne 51 Table 14 Development Tools for the X3 SDF Example ccccccceccessesssesseeseceseeseeceeseeeeeeseseseeseeeaeeseenseseeeeaeeeeeeesen
69. ed for a large channel or mixed requirement systems and data acquisition cards from Innovative can be integrated with Innovative s other DSP or data acquisition baseboards for high performance signal processing Why do I need to use Malibu with my Baseboard One of the biggest issues in using the personal computer for data collection control and communications applications is the relatively poor real time performance associated with the system Despite the high computational power of the PC it cannot reliably respond to real time events at rates much faster than a few hundred hertz The PC is really best at processing data not collecting it In fact most modern operating systems like Windows are simply not focused on real time performance but rather on ease of use and convenience Word processing and spreadsheets are simply not high performance real time tasks The solution to this problem is to provide specialized hardware assistance responsible solely for real time tasks Much the same as a dedicated video subsystem is required for adequate display performance dedicated hardware for real time data collection and signal processing is needed This is precisely the focus of our baseboards a high performance state of the art dedicated digital signal processor coupled with real time data 1 O capable of flowing data via a 64 bit PCI bus interface The hardware is really only half the story The other half is the Malibu software tool set which u
70. eeesaeeees 54 Tablets X3 SDE A D Ecce s 79 Table 16 A D Conversion Coding ccceccesccesssseceseeseceseeseeesecsecesecsecesecseeesecseeesecsaesseesaeeseceaeeaecaeseenseceeeseseeesaeesaeeneaeeesaeeens 80 Table 17 X3 SDF External and Reference Clock Selection sess 83 Table 18 X3 SDF External Clock and Reference Input Requirements essere 84 Table 19 External Clock and Reference Signal Pinouts sess 84 Table 20 PLL Interface Word ForMat oooooonccnncninononononooncnononncnnnonncnn non nnnn non non non nnne enne i ener ener enne enne 86 Table 21 PEL Read Sequence Roe HR RS I ERREUR dee io edes RH e eee ad 86 Table 22 PEE Read Word i c octetos pies once 87 Table 23 PLIE Output ASSIM cr RR RE RN UU UNE nl tati 87 Table 24 X3 SDF Conversion Clock Timing esses ennemi nne nennen 88 Table 25 Reduced Power Options coser e Rte e ee a eed terc ies eei idein E ie ive ge IER 92 Table 26 Alert Lypes 2cie testet teo aea eee peto e ee a HE SEN I EAE ede batte elite 94 Table27 Alert Packet Formats m exito eO ened tla etait dr e ter b ERR REP m tete ese 94 Table 28 X3 SDF Power Consumption 3 e tty er e E PRSE CREE UA REA TD NI D e DET 98 Table 29 X3 SDF Environmental aci NER US 99 Table 30 X3 SDF Analog Performance Summary sess nennen nn rn nr nnne nennen 99 Table 31 X3 SDF XMC Connector P15 Pimout cccccssssscsssesseseseessessecssesscessecssesseco
71. egasas megasas cAwindowsis Kernel Driver No Manual Stopped OK Normal No No Components megasr MegasR cAwind Kernel Driver No Manual Stopped OK Normal No No 5 Software Environment Kernel Driver OK Normal No modem Modem ES Kernel Driver No Manual Stopped oK Ignore No No Environment Variables E 4 E a a PLE monitor Microsoft Monitor Class Functi c windows s Kernel Driver Yes Manual Running ok Normal No Yes mouclass Mouse Class Driver cAwindowsis Kernel Driver Yes Manual Running oK Normal No Yes Network Connections is 5 z Running Tasks mouhid Mouse HID Driver cAwindowsis Kernel Driver Yes Manual Running oK Ignore No Yes pp caes mountmgr Mount Point Manager c windows s Kernel Driver Yes Boot Running ok Critical No Yes para mpio Microsoft Multi Path Bus Driver c windows s Kernel Driver No Manual Stopped oK Normal No No roam Grips mpsdrv Windows Firewall Authorizatio c windows s Kernel Driver Yes Manual Running ok Normal No Yes Startup Programs mrxdav WebDav Client Redirector Driv c windows s File System D No Manual Stopped ok Normal No No OLE Registration mrxsmb SMB MiniRedirector Wrapper cAwindowss File System D Yes Manual Running oK Normal No Yes Windows Error Reporting mrxsmb10 SMB 1 x MiniRedirector c windows s File System D Yes Manual Running ok Normal No Yes mnismb20 SMB 20 MiniRedirector Cwindowsis File System D Yes Manual Running oK Normal No Yes msahci msahci c windows s Kernel Drive
72. electrical Host Type Bus Mechanical Form factor Adapter Example card Required XMC 3 module PCI Express 1 0a XMC single width None Kontron CP6012 slot www kontron com Diversified Technology CPB4712 http www diversifiedtechnology com p roducts cpci cpb4712 html Desktop PC PCI Express 1 0a PCI Express Plug in card PCle XMC 3 Innovative 80172 adapter Desktop PC PCI 2 2 PCI Plug in card PCI XMC 3 Innovative 80167 adapter Compact PCI PCI Express 1 0a 3U or 6U CPCle XMC 3 TBD Express adapter Cabled PCI PCI Express 1 0a Cabled PCI Express to Cable PCIe Innovative 90181 0 Express remote IO Adapter and XMC 3 carrier PXI Express Compact PCI 3U 3U PXIe Innovative 80207 Express Adapter X3 SDF User s Manual 52 Linux Directory Structure X3 SDF User s Manual Air cooled or conduction cooled Embedded PC Stand alone PC Enclosure is Innovative 90201 90199 with dual XMC sites 195 x 252 x 75 mm OpenVPX PCI 3U 3U VPX XMC Innovative 80260 X3 SDF User s Manual 53 Linux Directory Structure X3 SDF User s Manual Writing Custom Applications Most scientific and engineering applications require the acquisition and storage of data for analysis after the fact Even in cases where most data analysis is done in place there is usually a requirement that some data be saved to monitor the system In many cases a pure data that does no immediate
73. els if ActiveChannels UI gt Log Error Must enable at least one channel UI gt AfterStreamAutoStop return The module supports up to four channels of simultaneous data flow The previous call to GetSettings populated the Settings object with the number of channels to be enabled on this run That information is used to enable the required channels via the Channels object within the Module Input Info object Packets scaled in units of events samples per each enabled channel int SamplesPerWord 1 X3 SDF User s Manual 65 Linux Directory Structure X3 SDF User s Manual Module ReturnPacketSize Settings PacketSize ActiveChannels SamplesPerWord 2 The size of the data packets sent from the module to the Host during streaming is programmable This is helpful during framed acquisition since the packet size can be tailored to match a multiple of the frame size providing application notification on each acquired frame In other applications such as when an FFT is embedded within the FPGA the packet size can be programmed to match the processing block size from the algorithm within the FPGA Start Loggers on active channels if Settings PlotEnable Graph Quit if Settings LoggerEnable Settings PlotEnable Logger Start BlocksToLog Settings SamplesToLog Settings PacketSize Settings SamplesToLog Settings PacketSize 1 0 Stopped false The example illustrates lo
74. er is operational 1 Close all applications 2 Click Test button 3 The Test field will show the test result This field shows Unknown if no test has been run Click Refresh to update displayed values Any change to registry setting requires a system reboot to take effect If driver status failed to start up properly the Test and Reset buttons will be deactivated greyed out Definition of Terms Memory Pool area of physical RAM reserved by MemDriver Max total size of the memory pool Used portion of memory pool assigned to applications Free total memory pool area not yet assigned to applications LFB Largest Free Block of contiguous area in the memory pool X3 SDF User s Manual 32 Linux Directory Structure X3 SDF User s Manual Troubleshoot Before performing any troubleshooting procedure it is recommended that the user backup all existing data and system files Please contact technical support for more detail Additional Driver Status The user can also determine the status of MemDriver with Msinfo32 exe 1 Click Start and run application Msinfo32 exe 2 Goto System Summary gt Software Enviornment gt System Drivers 3 Look for the memdrv entry It should be in the Running state Ka System Information Fe fat File Edit View Help System Summary Name Description File Type Started Start Mode State Status Error Control Accept Pause Accept Stop Hardware Resources m
75. ere presence of data does not indicate that the PLL is operating at the correct frequency or is stable PLL Interface The AD9510 is mapped into the PCI Express memory space for its control port at BAR1 0xA so that the host can perform configuration Writes to the PLL interface port generate a serial data stream to the PLL that is used to configure the PLL Writes to the PLL are performed when the PLL interface port is written to Reads from the PLL require a two step process consisting of first a write to the PLL register specifying a read at an address followed by a read from the PLL register that returns the value of the PLL register specified by the address in the PLL word The PLL is read is a single byte This interface is only for configuration accesses should be spaced by the host computer to be at least 2 ms apart The Malibu library handles this restriction as part of the function The PLL interface uses a 24 bit word to communicate with the PLL that specifies a read or write access the PLL register address and the data byte to transfer For reads the data byte is a don t care The 24 bit word is as follows 0 PLL register address 7 Table 20 PLL Interface Word Format Data byte don t care for reads For reads the PLL must be written to with a bit 23 as 1 and the address that is to be read then read from the PLL register For example a read to PLL register X 40 would be performed as BARI 0xA X 00804
76. ger the data acquisition best for your application and just get familiar with using the module The program also shows how to use BinView a data analysis and viewing program by Innovative that will let you see what you acquired in detail Both time domain and frequency domain data can be viewed and analyzed Data can also be exported to programs like Excel and MATLAB for further analysis Before you begin to write software taking a look at SNAP will allow you see everything working You can then look at the code for SNAP and modify it for your application or grab code from it that is useful Getting Good Analog Performance The X3 SDF has a dynamic range exceeding 100 dB To take advantage of this it is important to use do the following e Use differential signals to eliminate system noise Single ended signals give typically 10 to 20 dB worse results because of noise pickup X3 SDF User s Manual 95 Linux Directory Structure X3 SDF User s Manual e Band limit input signals Even though the A D has filtering and rejects most out of band noise it is a good idea to filter the incoming signal just to get rid of as much noise as possible e Scale your input signals to be 10V full scale Make the signal as big as possible so that the noise is a not as much a factor Custom ranges can be ordered if necessary e Usea high quality shielded cable The MDR68 cable was selected because it has a foil shield and delivers near coax performanc
77. gging data to a disk file with post viewing of the acquired data using BinView The code fragment above closes any pending instance of BinView and logger data files Module Dio DioPortConfig Settings DioConfig The module supports programmable bit I O available on connector JP16 The code fragment above programs the direction of these DIO bits in accordance with the settings from the GUI Set test mode Module TestCounterEnable Settings TestCounterEnable For test purposes the FPGA firmware supports replacement of analog input samples with ascending ramp data If the test counter is enabled in the GUL it is applied to the hardware using the preceeding code fragment Set power mode Module LowPowerEnable Settings LowPower The module supports a lower power consumption mode enabled via the LowPowerEnable method of the module object Route clock to active analog devices Set reference based on clock source to obtain correct FrequencyActual double reference if Settings SampleClockSource 0 reference SampleRate Module DecimationFactor SampleRate Module Clock OutputClock Ad9511 oExternal else reference Module Input Info ReferenceClock Module Clock OutputClock Ad9511 0Vco Apply timebase correction factor if available double correction Settings PllCorrection if correction correction correction 1 0 NaN so fix it Module Clock ReferenceCalibrationFactor
78. he settings X3 SDF User s Manual Linux Directory Structure X3 SDF User s Manual J monitor gt mouclass gt mouhid b mountmgr mpio gt mpsdrv bo MpsSvc b J MRxDAV l Computer HKEY_LOCAL_MACHINE SYSTEM CurrentControlSet services memdry it 3 Reboot the system and retest the driver 4 If test failed contact technical support X3 SDF User s Manual IN z 3 3 oe 3 34 Linux Directory Structure X3 SDF User s Manual About the X3 XMC Modules In this chapter we will discuss the common features of the X3 module family Specifics on each module are covered in later chapters X3 XMC Architecture The X3 XMC modules share a common architecture as well as many features such as the PCI Express interface data buffering features the Application Logic and other system integration features This allows the X3 XMC modules to utilize common software and logic firmware while providing unique analog and digital features Figure 7 X3 XMC Family Block Diagram The X3 XMCs have a variety of analog and digital IO front ends suited to many applications X3 SDF User s Manual 35 Linux Directory Structure X3 SDF User s Manual X3 XMC Features FPGA Applications X3 SD 16 channels of 24 bit 216 ksps A D 7100 Xilinx Spartan3 1M Vibration measurement dB 2M option acoustics wide dynamic range applications X3 SDF 4 channels of
79. he temperature as illustrated below Open the module Innovative X3 SD Module Module Target 0 Module Open Create reference to thermal management object on module const LogicTemperatureIntf amp Temp Module Thermal Read current temperature float t Module LogicTemperature Read write current warning temperature float t Module LogicWarningTemperature Module LogicWarningTemperature 70 0 Read current failure temperature float t Module LogicFailureTemperature See if the module is in thermal shutdown bool state Module Failed X3 SDF User s Manual 49 Linux Directory Structure X3 SDF User s Manual Thermal Failures The X3 modules will shut down if the module temperature exceeds 85C This means that something is seriously wrong either with the module or with the system design Damage may occur if the module temperature exceeds this limit The Application LED will blink when the a temperature failure has occurred If your software was monitoring the alert packets you will also receive a temperature warning alert prior to failure The module temperature can always be read by the application software so this can also provide information pointing to overheating The most important thing to do is to determine the root cause of the failure The module could have failed the system power is bad or the environment is too harsh The first thing to do is inspect the module Is
80. he triggering The data is then error corrected and the enabled channels flow to the data buffer The data buffer implements a data queue in the SRAM The packetizer pulls data from the queue creates data packets of the programmed size and sends those to the PCIe interface logic or out the host link From here the Velocia packet system controls the flow of data to the host Data packets flow into host memory for consumption by the host program The Board Basics and Host Communications chapters of this manual discuss the use of the packet data system used on the X3 module family The X3 SDF module FrameWork Logic connects the data from A D interface to the packet system by forming the data into 32 bit words of consecutive enabled channels Status indicators for the A Ds are integrated with the alert log to provide host notifications of important events for monitoring the data acquisition process some of which are unique to the X3 SDF The complete description of the FrameWork Logic is provided in the FrameWork Logic User Guide including the memory mapping register definitions and functional behavior This logic is about 3596 of the available logic in the application FPGA 1M gate device In many custom applications unused logic functions can be deleted to free up gates for the new application Power Controls and Thermal Design The X3 SDF module has temperature monitoring and power controls to aid in system integration Also the module has been
81. ification calibration coefficients and other data that needs to be stored permanently on the card This memory is 16K bits in size Functions for using the Serial EEPROM are included in the Malibu Toolset and example programs that allow the software application programmer to easily write and read from the memory without having to program the low level interface Use the baseboard IdRom method to obtain a reference to the internally managed IusesPmcEeprom object as shown below Open the module Innovative X3 SD Module Module Target 0 Module Open Create a 50 32 bit word section at offset zero in ROM user space PmcIdromSection Sectionl Module IdRom Rom PmcIdrom waUser 0 50 Create a 50 32 bit word section at offset 50 in ROM user space PmcIdromSection Section2 Module IdRom Rom PmcIdrom waUser 50 50 Write to ROM for int i 0 i lt 50 i Sectionl AsInt i i 2 Sectionl StoreToRom for int i 50 i lt 100 i Section2 AsFloat i static cast float i 2 Section2 StoreToRom Read from ROM Sectionl LoadFromRom for int i 0 i lt 50 i int x Sectionl AsInt i Section2 LoadFromRom X3 SDF User s Manual 47 Linux Directory Structure X3 SDF User s Manual for int i 50 i lt 100 i float x Section2 AsFloat i As delivered from the factory this EEPROM contains the calibration coefficients used for the A D error correction The serial EEP
82. igital IO 39 PXIE Differential STAR A B9 DIO40 PXIE_100M Digital IO 40 PXIE 100M ref clk D9 DIO4 PXIE_100M Digital IO 41 PXIE 100M ref clk E9 DIO42 PXIE_DSTARB Digital IO 42 PXIE Differential STAR B A19 DIO43 PXIE DSTARB Digital IO 43 PXIE Differential STAR B B19 DIO_CLK PXI_DSTARC Digital IO Clk PXIE Differential STAR C D19 DIO CLK PXI DSTARC Digital IO Clk PXIE Differential STAR C E19 Note PXI Express signals are only available when PXIE adapter card is used X3 SDF User s Manual 120 Linux Directory Structure X3 SDF User s Manual Xilinx JTAG Connector JP3 is used for the Xilinx JTAG chain It connects directly with Xilinx JTAG cables such as Parallel Cable IV or Platform USB Connector Types Number of Connections Connector Part Number Mating Connector JP3 Figure 36 X3 SDF J3 Orientation 14 pin dual row male header 2mm pin spacing right angle 14 arranged as 2 rows of 7 pins each Samtec TMM 107 01 L D RA or equivalent AMP 111623 3 or equivalent Pin Pin 1 13 Pin 14 Figure 37 X3 SDF J3 Side View Table 35 X3 SDF JP3 Xilinx JTAG Connector Pinout Pin Signal Direction 1 3 5 7 9 11 13 Digital Ground Power 2 3 3V Power 4 TMS I 6 TCK I 8 TDO O 10 TDI I 12 14 No Connect X3 SDF User s Manual 121 Linux Directory Structure X3 SDF User s Manual Mechanicals The following diagram shows the X3 SDF
83. in this region Since packets main contain data from up to four channels of twentyfour bit data on an X3 SDF packets should be sized less than 0x200000 In practice packets at least 0x40000 in size tend to provide good performance while fitting into available bus master memory Active Channels Group The X3 10M support simultaneous acquisition from up to eight analog input channels simultaneously Trigger Group Acquisition may be triggered using an external signal or via software The Trigger Source radio control provides the means of selection Triggers act as a gate on data flow no data flows until a trigger has been received Triggers may be initiated via software or hardware depending on the Trigger Source control If software the application program must issue a command to initiate data flow If hardware a signal applied to the external trigger connector controls data flow X3 SDF User s Manual 56 Linux Directory Structure X3 SDF User s Manual Triggers are modal depending on the Trigger Mode control In Unframed mode triggers are level sensitive and data flow proceeds while the trigger is in the high active state and stops while the trigger is in the low inactive state This mode is ideal for conventional data acquisition applications In Framed mode triggers are rising edge sensitive Upon detection of each edge Trigger Frame Count samples are acquired from all active channels then acquisition terminates until th
84. ing of the program outside of the User Interface portion of the program is therefore common code Each project uses the same file to interact with the hardware and acquire data Program Design The Snap example is designed to allow repeated data reception operations on command from the host As mentioned earlier received data can be saved as Host disk files When using modest samples rates data can be logged to standard disk files X3 SDF User s Manual 54 Linux Directory Structure X3 SDF User s Manual However full bandwidth storage of multiple A D channels can require up to 80 MB s capacity to a dedicated RAIDO drive array partitioned as NTFS for data storage may be required The example application software is written to perform minimal processing of received data and is a suitable template for high bandwidth applications The example uses various configuration commands to prepare the module for data flow Parametric information is obtained from a Host GUI application but the code is written to be GUl agnostic All board specific 1 O is performed within the Applicationlo cpp h unit Data is transferred from the module to the Host as packets of PmcBuffers The Host Application The picture to the right shows the main window of X3 SDF example This form is from the designer of the Borland Turbo C version of the example It shows the layout of the controls of the User Interface The timer pop up menu and folder icons to the upper
85. inputs are LVDS and must be driven as a differential pair Each differential pair is 100 ohm terminated The LVDS inputs cannot be driven single ended both inputs must be actively driven Electrical characteristics of the inputs are shown in the following table Input Amplitude a fo 1Vp p Larger inputs may cause damage CN A Ww o CO Table 18 X3 SDF External Clock and Reference Input Requirements The external clock and reference inputs are from either the front panel connector JP1 or XMC secondary connector P16 To use the P16 connector inputs it is necessary to have a carrier card that supports the P16 pinout shown later in this chapter Here is where the external clock inputs are connected External Clock Ext clk m uc MDR6S front panel connector Table 19 External Clock and Reference mal Pinouts Generating a Sample Clock with the PLL The PLL is configured to provide clock rates as shown in the following table This table is based upon a 24 576 MHz reference clock to the PLL and a VCO operating range of 100 to 140 Mhz Custom configurations with a different reference clock can be ordered to meet exact requirements The PLL can be tuning range is limited to 100 to 140 MHz when using the VCO standard on the X3 SDF The PLL has two modes fixed divider FD and dual modulus DM The FD mode does not use the A counter The tuning equation is Fo F R x PB A where Fref 24 576 MHz or external reference frequency R to
86. ion can be acted upon immediately or simply logged along with analog data for subsequent post analysis Module OnBeforeStreamStart SetEvent this Applicationlo HandleBeforeStreamStart Module OnBeforeStreamStart Synchronize Module OnAfterStreamStart SetEvent this Applicationlo HandleAfterStreamStart Module OnAfterStreamStart Synchronize Module OnAfterStreamStop SetEvent this amp ApplicationIo HandleAfterStreamStop Module OnAfterStreamStop Synchronize Similarly HandleBeforeStreamStart HandleA fterStreamStart and HandleAfterStreamStop handle events issued on before stream start after stream start and after stream stop respectively These handlers could be designed to perform multiple tasks as event occurs including displaying messages for user These events are tagged as Synchronized so Malibu will marshall the execution of the handlers for these events into the main thread context allowing the handlers to perform user interface operations The Stream object manages communication between the application and a piece of hardware Separating the I O into a separate class clarifies the distinction between an I O protocol and the implementing hardware In Malibu high rate data flow is controlled by one of a number of streaming classes In this example we use the events of the PacketStream class to alert us when a packet arrives from the target When a data packet is delivered by the data streaming system OnDataAvailable e
87. ions Cryptographic API NEW CRYPTO YY Y Virtualization NEW VIRTUALIZATION _ YY Library routines Sorry no help available for this option yet 4 Goto section Device Drivers gt Innovative Memory Driver support gt Memory Pool Size 5 Change the value click save and exit This value must be 1 4095 for x64 and 1 1000 for x32 Addition information in section Applet Features and Notes 1 below 6 Rebuild the kernel and reboot 7 After boot up login as root and change the permission chmod 666 dev memdrv Aadd this command to the file etc rc d boot local Using Controller Applet This applet displays MemDriver statuses and provide control functions to interact with the driver Running the Applet 1 Open folder usr Innovative MemDriver controller mdControl 2 Run executable mdControl 3 If this file is missing or does not execute properly you may recompile it using Qt project mdControl pro 4 Normally the following window will appear X3 SDF User s Manual 19 Linux Directory Structure X3 SDF User s Manual gt MainWindow MS Requested Pool Size MB 500 Memory Pool Info MB Max 500 o 500 500 Memory Driver Status Ready Version 0 0 24 INED Passed Build Date Nov 9 2011 Refresh Applet Features and Notes 1 Ifthe memory driver failed to reserve desired amount of memory it will attempt to reserve the largest amount poosible However if it failed to reserve any memory at a
88. irectory Structure X3 SDF User s Manual Signal Quality vs Sample Rate 1 01 KHz 19 8V p p sine differential input Signal Quality Summary Sample Rate S N SFDR ENOB THD 10 105 4 121 7 17 1 119 4 50 113 1 108 0 16 8 103 4 100 113 1 108 3 16 7 103 5 500 107 5 107 1 16 3 104 2 1000 101 6 107 0 15 8 104 9 5000 87 6 78 8 11 9 75 2 Signal Quality vs Sample Rate 130 120 x 110 dB 100 90 80 70 Sample Freq KS s 10000 Figure 23 X3 SDF A D Signal Quality vs Sample Rate X3 SDF User s Manual 104 Linux Directory Structure X3 SDF User s Manual 140 120 100 80 dB 60 40 20 Signal Quality vs Input Amplitude S N m SFDR I I I I 0 5 10 15 20 25 Input Amplitude Vp p Figure 24 X3 SDF A D Signal Quality vs Input Amplitude X3 SDF User s Manual 105 Linux Directory Structure X3 SDF User s Manual Signal Quality vs Input Frequency He TL ILE Not ENOB bits 1000 10000 Input Frequency kHz X3 SDF User s Manual 106 Linux Directory Structure X3 SDF User s Manual X3 SDF 60 80 dB 100 120 140 160 180 0 0 0 5 1 0 15 2 0 2 5 3 0 3 5 4 0 45 5 0 KHz Max S N dB S N 05 SINAD dB ENOS SFDR 05 THD dB 146 2 111 1 103 1 16 6 109 5 0 000419 107 608 Figure 26 Signal Quality 1 01 kHz 19 8Vp p 10 ksps I X2 SDF 80 dB 100 120
89. is driver software You should check your manufacturer s website for updated driver software for your device Install this driver software anyway Only install driver software obtained from your manufacturer s website or disc Unsigned software from other sources may harm your computer or steal information v See details Figure 1 Vista Verification Dialog X3 SDF User s Manual 23 Linux Directory Structure X3 SDF User s Manual The Installer Program After launching Setup you will be presented with the following screen Please select a product to install DAELE C Innovative O Change Components to Install for Quadia Quadia Applets examples Docs and Pismo libraries Malibu Host libraries utilites Docs drivers amp DLLs Bin View Data graphing and analysis tool CodeHammer JTAG support for Code Composer Studio Innovative Components C Builder Support Product Registration ONE TENE Using this interface specify which product to install and where on your system to install it Figure 2 Innovative Install Program 1 Select the appropriate product from the Product Menu 2 Specify the path where the development package files are to be installed You may type a path or click Change to browse for or create a directory If left unchanged the install will use the default location of C Innovative 3 Typically most users will perform a Full Install by leaving all items in
90. is used to program the PLL to generate the specified sample rate during acquisition However if the clock source is external then the Output KHz control is used to inform the program of your intended external sample rate In that case you are expected to supply a clock running at the rate listed in the Clock Source MHz control to the external clock input connector on the module Event log Communications Group All X3 modules support data transfer between Host memory and the on board FPGA via a dedicated PCI Express bus interface Data is transferred in packets which consist of a two word header followed by a fixed length data buffer Header word zero contains the buffer length in bits 0 23 and a peripheral ID in bits 24 31 The Communications Pkt Size edit control specifies the size of the packets transferred between the target and the Host Each packet transferred results in a Host interrupt handled by the Malibu libraries Consequently larger packets amortize the Host interrupt processing more efficiently However packets are transferred using a contiguous page locked memory region of Host memory known as bus master memory which is allocated during installation via the ReserveMemDsp exe applet Since bus master memory is Host memory it is limited in size by the amount of physical memory installed in the PC By default 32 MBytes are allocated as bus master memory which implies that the Pkt Size must be restricted to fit with
91. l 58 Linux Directory Structure X3 SDF User s Manual Ram Test Select the ZbtRam tab The control on this tab allows the onboard ZBT ram to be tested In practice the ZbtRam is directly addressed by custom FPGA firmware However the stock logic provides means of accessing this RAM using methods in the module control object to verify proper electrical operation EEPROM Access Select the EEPprom tab The controls on this tab allow the contents of the onboard EEPROM to be queried or changed The onboard EEPROM is used for non volatile storage of module identification strings digital calibration coefficients for each of the A D channels and for a calibration coefficient for the reference clock for the onboard PLL These values are determined during factory calibration and need not normally be changed by the user Debugging Select the Debug tab The controls on this tab support a few low level debug operations to be performed A debug script may be executed at any time to perform low level register fetches or stores to exercise custom FPGA firmware or determine the current hardware state Unlike the stream scripts described earlier this script executes manually via the button so you need not be streaming to put it to use A software alert may be generated by pressing the Software button The value in the edit control to the right of this button is supplied as the code for the alert which is returned and displayed in the
92. l DIO e ctetu Sep ta ro ere tito eet te bet 43 Hardware Implementation s d eee fate ee o etl dut bee are au e tbe ui evita eda 44 Digital VO T Hingd e te tae ttu an oa ta eta e atv eis 45 Digital TO Electrical Characteristics su nce dd 46 Notes on Digital IO US6 e Arce ree e ORE tute nta ev et nae a reote el a tog e 47 Serial EEPRODM InterfaCQ zs idee dro ed Ee ena csessdeacscaccsscscsddasessacses duucddusestacessclucd esassaconseaceceuedesGesseseccasecoo4ey Thermal Protection and Monitoring eere scere ee eren eene enne eene eno see ens sesso se snssesssseesssseessosssece FO Thermal Fail res eire eese e a Coe eror ta ane a ostia ede a doesnt pese p eae nano sa eden oed eed ae sa Con osebe ssos isese siss du sao Ges osa ice DO IO EET DO EIL EET JTAG Scan Pa h 5 2 ordeo cet ot eo eo oon a eo seo beue tota c doo ave ea eoo baee eo esp see a suo e eee soos usce suspe adeo sea Vboee doeet esses s ce DL X3 SDF User s Manual Table of Contents X3 SDF User s Manual FRAME dd dur L Integrating with Host Cards and Systems eee eee ee eee seen nets seins senses essen sees sees en esses D2 Writing Custoni A Sgt M X3 SDE Snap Example ad ANN A ete eO eC One a he e RES 54 NA cene Oe AES e e RO D E RR Re aD edis 54 ES The Host Application Me OS EEPROM ACCESS 2 e ge etat m e AA pere E ia 59 De
93. l mode was about 10C cooler than 4 channel mode for no forced air flow at room temperature The 33 MHz system clock feature requires that the card reconfigured by installing a 0 ohm jumper for R228 This jumper is located near the PCIe interface device XIO2000A and is on the back of the card The factory can pre configure this if you X3 SDF User s Manual 92 Linux Directory Structure X3 SDF User s Manual decide to use this option in production As shipped the system clock is 66 MHz because this allows the system logic to support more custom logic developers more easily Tests have shown that this reduces operating temperature by 3 C for room temperature testing with no forced air Total data rate from the module must be limited to 50MB s when a 33 MHz clock is used Alert Log Overview X3 modules have an Alert Log that can be used to monitor the data acquisition process and other significant events Using alerts the application can create a time history of the data acquisition process that shows when important events occurred and mark the data stream to correlate system events to the data This provides a precision timed log of all of the important events that occurred during the acquisition and playback for interpretation and correlation to other system level events Alerts for critical system events such as triggering data overruns analog overranges and thermal warnings provide the host system with information to manage the module
94. ll the Status field will show Not Ready In this case set the Memory To Reserve value to a smaller value say 50 of previous and reboot Valid values are between and 4095 MB For 32 bit machines it is highly recommended to stay below 1000 2 To reset memory driver and clear all allocated memory 1 Close all applications 2 Click Reset button 3 To verify driver is operational 1 Close all applications 2 Click Test button 3 The Test field will show the test result Pass or Failed This field shows Unknown if the test has not yet been executed 4 Click Refresh to update displayed values Definition of Terms Memory Pool a section of physical RAM reserved by MemDriver Max total size of the memory pool Used amount of memory pool allocated to applications X3 SDF User s Manual 20 Linux Directory Structure X3 SDF User s Manual Free total memory pool area not yet allocated to applications LFB Largest Free Block of contiguous memory in the pool Alternative Driver Status Alternatively the user may obtain the status of MemDriver with the following 1 Open bash terminal 2 Scat proc driver memdrv 3 Ifthe driver is functional you should see an output with the driver name version and build date For example II Memory Driver v0 0 24 Nov 9 2011 12 35 43 X3 SDF User s Manual 21 Linux Directory Structure X3 SDF User s Manual Windows Installation This chapter describes th
95. lling an X3 A4D4 board If support for multiple cards is needed the program must be run to completion once for each type of board This is required because parts of the installation such as baseboard device drivers may be different for different board types After selecting the board press Go to begin installation The window changes to display the progress of the install X3 SDF User s Manual 28 Linux Directory Structure X3 SDF User s Manual X3 SDF User s Manual 29 Linux Directory Structure X3 SDF User s Manual MalibuRED Libraries Thank you for choosing X3 A4D4 Installing Malibu Redistributable Libraries After completing the installation reboot the system to allow Windows to recognize the new drivers Then proceed with the Hardware Installation as in the development system installation above X3 SDF User s Manual 30 Linux Directory Structure X3 SDF User s Manual Mem Driver Installation Windows Introduction This document provide instructions to install and use the Innovative Integration memory allocation driver MemDriver and controller applet MemDrvControl Releases Release notes are found in the file README txt Peroidic updates can be downloaded from http www innovative dsp com ftp MemDriver System Requirement Windows 7 32 or 64 bits Malibu Applications In order to utilize MemDriver all Malibu based applications must be linked against the current release of Malibu
96. loaded at least once per session it remains valid until power is removed from the board Use Configure button is to load the logic from an EXO file X3 SDF User s Manual 55 Linux Directory Structure X3 SDF User s Manual Setup Tab Capture Example This tab has a set of controls that hold the parameters for Configure Setup Stream Zbt Ram EEProm Debug BRB rne A Clock Ci iicali data acquisition These settings are delivered to the target E ER poA and configure the target when streaming is initiated via Extemal MHz Tine Stamp e iae controls on the Stream tab described in the next section C intemal Terp Waring Input verange Active Channels r Trigger The setup tab contains a large number of controls used to Sola Pars Bos Software Count Unframed configure the on board timebase alert notifications C Enema T Auto Retioger c aed analog channel selection range and triggering etc Each Digital 1 0 Data Logging Test Counter Low Power r Decimation 1 1 Config Mask Samples Enable of these controls is described below ee een r mose Ee T Ente Clock Group The module features an on board AD9510 PLL which may be used as a sample clock during analog acquisition Alternately an external sample clock may be used The Clock Source radio control governs which timebase is used as the analog sample clock If the internal PLL is selected the sample rate entered in the Output Khz edit control
97. m which are an excellent source of FAQs and information submitted by Innovative employees and customers Innovative Integration Web Site Additional information on Innovative Integration hardware and the Malibu Toolset is available via the Innovative Integration website at www innovative dsp com Typographic Conventions This manual uses the typefaces described below to indicate special text Typeface Source Listing Boldface Emphasis Cpp Variable Cpp Symbol KEYCAPS Menu Command X3 SDF User s Manual Meaning Text in this style represents text as it appears onscreen or in code It also represents anything you must type Text in this style is used to strongly emphasize certain words Text in this style is used to emphasize certain words such as new terms Text in this style represents C variables Text in this style represents C identifiers such as class function or type names Text in this style indicates a key on your keyboard For example Press ESC to exit a menu Text in this style represents menu commands For example Click View Tools Customize 13 Table of Contents X3 SDF User s Manual Installation on Linux This chapter contains instruction on the installation of the baseboard software for Linux operating systems Software installation on Linux is performed by loading a number of packages A Package is a special kind of archive file that contains not o
98. m applications XMC P16 Provides digital IO or a private link to host cards capable of gt 200 MB s sustained operation Timing and triggering Flexible clocking and synchronization features for IO Data buffering and Computational Memory Two 2MB SRAM devices are used provide data buffering processor memory and computation memory for the Application FPGA Alert Log Monitors system events and error conditions to help manage the data acqusiton process Temperature Sensor Monitors the module temperature and provides thermal protection for the module X3 Computing Core The X3 XMC module family has an FPGA based computing core that controls the data acquisition process providing data buffing and host communications The computing core consists of a Xilinx Spartan3 or 3A DSP FPGA and two banks of 2MB SRAM memory The FPGA uses the memories for data buffering and computational workspace Table 3 X3 Computing Core Devices Feature X3 Module Device Part Number Application Logic SD SDF Xilinx Spartan 3 1M XC351000 4FGG456C FPGA 10M Servo 25M DIO Xilinx Spartan 3A DSP 1 8M XC3SD1800 4FGG676C 2M SD16 A4D4 Buffer Memory SD SDF Synchronous Burst ZBT 1Mx16 100 MHz SRAM SRAM 10M Servo 25M DIO 512Kx32 133 MHz 2M SD16 A4D4 Computational SD SDF Synchronous Burst ZBT 1Mx16 100 MHz Memory SRAM SRAM 10M Servo 25M DIO 512Kx32 133 MHz 2M SD16 A4D4
99. m and typical timing The external clocks go through one or two multiplexers accounting for the differences in propagation delay to the various devices Jitter to the A D converters is of primary interest since that limits the A D conversion accuracy Jitter is summed as the root sum of squares for random jitter Table 24 X3 SDF Conversion Clock Timing Clock Source Clock Destination Propagation Delay ns Additive Jitter ps RMS External clock or A D conversion clock 1 8 typical 0 05 PXI_DSTARA 2 5 maximum 24 576 MHz or PLL Reference clock 1 2 typical 0 05 PXIE 100M 1 5 maximum Triggering The X3 SDF has a trigger control component in the FPGA that controls the data acquisition process The sample clock specifies the instant in time when data is sampled whereas triggering specifies when data 1s kept This allows the application to collect data at the desired rate and keep only the data that is required On the X3 SDF module all A D channels operate synchronously using the same clock and trigger The trigger controls allows data to be acquired continuously or during a specified time as triggered by either a software or external trigger Data can also be decimated to reduce data rates X3 SDF User s Manual 88 Linux Directory Structure X3 SDF User s Manual Trigger Mode Data Collected Played Back Start Trigger Stop Trigger Continuous All enabled channel pairs Softw
100. m the bank directions This low order two bits in the parameter sent to this method corresponds to up to two bytes of direction control where bit 0 corresponds to front panel DIO bits 0 7 bit 1 corresponds to front panel DIO bits 8 15 Subsequently use of the FrontPanelPortData property allows accessing the state of all bits Using the setter property updates all bits configured for output whereas using the getter property fetches the current state of all bits regardless of configuration X3 SDF User s Manual 43 Linux Directory Structure X3 SDF User s Manual Table 7 Table 1 Front Panel DIO on X3 Modules This digital I O hardware 1s controlled by the IUsesFrontPanelPort class Its properties Table 8 IUsesExtendedDioPort Class Operations FrontPanelPortConfig Configures banks of bits for input or output FrontPanelPortData Broadside Read Write to low order 32 bits of DIO Typical use of the digital IO port involves first configuring the port using the FrontPanelPortConfig operator This sets the byte direction and the clock mode The port is then ready for read write operations via FrontPanelPortData Hardware Implementation Digital I O port activity is controlled by the digital I O configuration control and data register Port direction is controlled by the configuration control register Bit Function 0 DIO bits 7 0 direction control 0 input default 1 DIO bits 15 8 direction
101. mance of the A Ds will be affected Decimation Group These controls govern the behavior enable the decimation logic When enabled only one of every Nth sample of acquired data is retained within the internal on board FIFOs and sent to the Host PC via bus mastering X3 SDF User s Manual 57 Linux Directory Structure X3 SDF User s Manual Data Streaming Capture Example DER Configure Setup Stream Zbt Ram EEProm Debug Sl Eh E Select the Stream tab The controls on this tab control data Biel flow The meaning of each of the fields on this tab are Bde r explained below mo ale Data collection is initiated when the VCR Start button is Data Fies f pressed and terminates when the VCR Stop button is pressed I Log Plot Overwrite Bdd or when the amount of data specified in the Data Logging configuration controls is accumulated To accommodate custom logic development the application Block Count Rate KB s Temp C Dig In Event Log supports execution of simple user authored scripts before and after the commencement of data flow The Start Scripts Before edit box specifies the full path spec to a text file containing valid script commands described below which will be executed prior to data flow Similarly the Start Scripts After edit box specifies the file containing commands to be executed after data flow is underway The following script commands are supported 1
102. n box If logic file is selected then we will move on to the loading it void _ fastcall TMainForm LogicLoadConfigBtnClick TObject Sender To gt LoadLogic In UI LogicLoadConfigBtnClick shown above is executed in response to the Configure button click It immediately checks whether the device is opened and stream is connected If the condition is true we exit the routine after logging the message in the message log We can also do some more UI tricks here such as setting up the progress bar limits and disabling the configure button etc We further extract the file name from the Textbox and pass it to the Applicationlo method LoadLogic shown below ApplicationIo LoadLogic Initiate Logic Load Process void ApplicationIo LoadLogic if Opened UI gt Log No module on specified target return X3 SDF User s Manual 63 Linux Directory Structure X3 SDF User s Manual UE AO Nomen enano A esie edad ortae e lante e cols A AS ed UI gt Log Parsing Module logic file UI gt GetSettings Module Logic ConfigureFpga Settings ExoFile In this method we make a call to the Malibu function ConfigureFpga which allows new logic image to be loaded This method takes name of the image file as an argument which will be read and loaded into the interface logic Logic loading triggers a series of events which are managed by the background thread void Applicationlo HandleProgress Proce
103. n will also result in a step change to the current consumption because the logic will begin to operate In our testing and measurements this has not been a surge current as much as a just a step change in the power consumption Power consumption varies and is primarily as a function ofthe logic design Logic designs with high utilization and fast clock rates require higher power Since calculating power consumption in the logic requires many details to be considered Xilinx tools such as XPower are used to get the best estimates It is important that any custom logic design have a substantial safety margin for the power consumption Dynamic loads should be considered so that peak power is adequate In many cases a factor of 2 for derating is recommended especially when the operating temperature is above 40C X3 SDF User s Manual 98 Linux Directory Structure X3 SDF User s Manual Environmental Table 29 X3 SDF Environmental Limits Analog Input Condition Limits Operating Temperature 0to 55 C 65C as measured by the on card temp sensor Humidity 5 to 95 non condensing Storage Temperature 30 to 85 C Forced Air Cooling None for ambient to 40C Forced air required above 40C Vibration operating ETS 300 019 1 3 R3 class 3 3 Vibration storage ETS 300 019 1 1 R1 class 1 2 Vibration transportation ETS 300 019 1 2 R2 class 2 3 except for free fall class 2
104. nd Off buttons to activate or deactivate respectively the LED on the baseboard for the specified target When you exit the application the board s LED will remain in the state programmed by this applet Dax fm X3 Pmc Finder Target Number Set LED Logic Loader The logic loader applet is used to deliver known operational logic images to the user logic device installed on a X3 SDF The user logic must be loaded once per session as the logic part is cleared on bus reset or power up The utility may be used to configure the firmware either through its command line interface or from its GUI Windows user interface The former is often convenient during PC boot up to install a standard logic file Place a short cut with the command line option set into the Windows Startup folder to execute the program when the system is started This application supports configuration of the onboard Spartan 3 logic device from a bit file produced by popular logic design tools including Xilinx s It is essential that the Spartan 3 be programmed before using related applications since some of the baseboard peripherals are dependent on the personality of the configured logic X3 Pme Logic Loader Target Exo File c NinnovatieevX3 SDSHardwaresmages 3 sd v3 bk m Event Log No baseboards enumerated HW Variant X3 SDF User s Manual 75 Linux Directory Structure X3 SDF User s Manual inf
105. ng and are also reported in each alert packet During system development it is a good idea to have a look at the temperature and verify that everything is OK inside the system during actual use When the module exceeds 85C the analog power supplies shut down reducing the power consumption to about 3W The module can continue to communicate but no valid data will be collected A temperature warning is provided via the Alert Log when the temperature is above 70C If a warning occurs it is best to do something either to reduce power consumption such as tunning off the A D channels turning on a system fan or turning off other things in the system Reducing Power Consumption The X3 SDF has power controls that allow the application software to power down unused channels and run in reduced power mode for the A Ds If you incorporate these into your application you may be able to avoid problems later in hot installations Feature Power Saved Comments A D low power mode 0 3W channel 6 dB loss in S N performance A D power down 0 9W channel A D is in lowest power mode PLL power down 0 3W PLL off must use external clock 33MHz system clock 0 5 33 MHz FPGA system clock Data rate to host is limited to 100 MB s typically Table 25 Reduced Power Options The A D power controls are under software control In the example software only the enabled A D channels are turned on to save power In lab tests single channe
106. nly the files that are to be installed but also installation scripts and dependency information to allow a smooth fit into the system This information allows the package to be removed or patched Innovative uses RPM packages in its installs Package File Names A package file name such as Malibu LinuxPeriphLib 1 1 3 1586 rpm encodes a lot of information Malibu Linux PeriphLib 1 1 3 1586 rpm Prerequisites for Installation In order to properly use the baseboard example programs and to develop software using the baseboard some packages need to be installed before the actual baseboard package The Redistribution Package Group MalibuRed This set of packages contain the libraries and drivers needed to run a program using Malibu This group is called MalibuRed because it contains the packages needed to allow running Malibu based programs on a target non development machine Red is short for redistributable WinDriver 9 2 1 1586 rpm Installs WinDriver 9 2 release MalibuLinux Red ver rel i586 rpm Installs Baseboard Driver Kernel Plugin intel ipp_rti 5 3p x32 rpm Installs Intel IPP library redistributable files X3 SDF User s Manual 14 The Redistribution Package Group MalibuRed X3 SDF User s Manual The installation CD or the web site contains a file called LinuxNotes pdf giving instructions on how to load these packages and how to install the drivers onto your Linux machine This file is also
107. nnne enne nn 106 Figure 26 Signal Quality 1 01 kHz 19 8Vp p 10 ksps ssessssssseseeseeeeeneeneneeenenn nennen nnne nennen nnne nnne 107 Figure 27 Signal Quality 1 01 kHz 19 8Vp p input 50 ksps essere nnne 108 Figure 28 Signal Quality 1 01 kHz 19 8Vp p input 100 ksps essssssseseeseeneeneenennennenn enne nennen 109 Figure 29 Signal Quality 1 01 kHz 19 8Vp p 1000 kSpS ooooocoinonicnionooonoonconnonnconnonnonnnon nono non nono non enne enne nennen nnne 109 Figure 30 Signal Quality 101 kHz 9 8Vp p 500 ksps nennen nennen nennen nennen nnne nnne 110 Figure 31 Signal Quality 101 kHz 9 8Vp p 1000 ksps enne nnne nnne nennen 110 Figure 32 Signal Quality 101 kHz 9 8Vp p 4375 ksps nnne nnne 111 Figure 33 Intermodulation Distortion 990 and 1100 dual tone 50 ksps sse 111 Figure 34 P15 XMC Connector Orientation ede aS ERE IR dle Be aes 114 Figure 35 P16 XMC Connector Orientation eeesssecsscssesessesseesesseseceeccceeceeceeesecsecseesessessessessesseeaesaeeeseeseceeseeeeeaeees 117 Figure 36 X3 SDF J3 Orientation csi ec ee e me er re ede ee et e Reda 121 Figure 37 X3 SDF J3 Side View ite e EUR aa 121 Figure 38 X3 SDF Mechanicals Bottom View Rev A sese nennen nennen 123 Figure 39 X3 SDF Mechanicals Top View Rev A cceccccccessessesseesseesecseeesecceeseceeeesecaeeseeeseeaeseseeaeenaesaeenaeserenaeessaeeenaeeee 123 X3 SDF User s Manual Table of Content
108. nputs The usual effect of inadequate signal drive is increased distortion or in the extreme case loss of input range This input impedance was chosen as the best compromise between noise and input impedance As the impedance goes up the noise increases Overrange Detection The A D devices indicate when an overrange occurs on the input Overrange occurs when the input signal is above the 10V differential range is exceeded For small overrange conditions of less than 5 overrange the A D will recover in a few samples to proper readings For larger overrange conditions the A D may require longer to recover The overrange indicator bit from each A D can be used to trigger an alert in the logic to notify the application when this error condition has occurred The alert message shows when the overrange occurred in system time and which channels overranged Custom logic has access to the overrange bits in the A D interface component Each data sample indicates when an overrange occurs as part of its status byte appended to the data This allows implementation of automatic gain controls for auto ranging external front end signal conditioning Sample Rate Generation and Clocking Controls The X3 SDF can either generate a sample clock using its on board PLL or it can use an external clock for conversion For clock generation the PLL provides low noise sample clocks for the A D converters For clock distribution the X3 SDF is able to distribut
109. oke any of these utilities go to the Start Menu Programs Baseboard Name and double click the shortcut for the program you are interested in running Common Applets Registration Utility NewUser exe Some of the Host applets provided in the Developers Package are keyed to allow Innovative to obtain end user contact information These utilities allow a User unrestricted use during a 20 day trial period after which you are required to Pr oo register your package with Innovative After the trial period operation will be Enel disallowed until the unlock code provided as part of the registration is entered Len into the applet After using the NewUser exe applet to provide Innovative Eu MMMM Integration with your registration information you will receive acid i poer The unlock code necessary for unrestricted use of the Host applets Name Innovative Integration A WSC tech support service code enabling free software maintenance IM aur downloads of development kit software and telephone technical hot line conyl support for a one year period as es Vista T Access Code 995846148 2 Help E Register Now Ok X3 SDF User s Manual 72 Linux Directory Structure X3 SDF User s Manual Reserve Memory Applet ReserveMemDsp exe Each Innovative PCI based DSP baseboard requires 2 to 8 MB of memory to be reserved for its use depending on the
110. om 3 2 MHz to 20 MHz with 100 Hz resolution The external reference input further allows the PLL to generate a wide range of frequencies that can be synchronous to an external input External clock inputs allow other external clocks to be used for sample clocks for unique system integration requirements The sample clocks for the A D devices are clocked directly from the clock distribution circuitry and are NOT derived from the application logic clocks or PCI Express bus clock This is because these clocks have too much jitter phase noise to use for high speed A D conversion The FPGA also receives a copy of the sample clock that is used for data capture and triggering Note Conversion clocking is separate from triggering sample clock is the time when samples are digitized but trigger determines when those samples are kept External Clock and Reference Inputs The X3 SDF has two external clocks that may be used for conversion timing plus two external inputs that can be used as a reference to the PLL The two external input clocks Ext Clk and PXI DSTARA can be used to directly clock the converters X3 SDF User s Manual 82 Linux Directory Structure X3 SDF User s Manual The 24 575MHz clock oscillator and PXI 100M clock can be used as references to the PLL The following table shows the clock mux controls for the X3 SDF Control Signal Device Function Result PLL REF SEL PLL Reference Mux Selects either PXI 100M or 24 576M
111. onversion uncertainty for an asynchronous trigger input Trigger Source A software trigger or external trigger can be used by the trigger controls Software trigger can always be used but external triggering must be selected The trigger source is level sensitive for the continuous mode or edge triggered for the framed mode triggering The Malibu software tools provide trigger source configuration and methods for software triggering retriggering in framed mode and trigger mode controls X3 SDF User s Manual 89 Linux Directory Structure X3 SDF User s Manual Framed Trigger Mode Framed trigger mode is useful for collecting data sets of a fixed size each time the input trigger is fired In framed mode the trigger goes false once the programmed number of points N have been collected Start triggers that occur during a frame trigger are ignored The maximum number of points per frame is 16 777 214 2 24 2 points while the minimum number of points is 2 Data flow to the host is independent of the framed triggering mode In most cases packet sizes to the host are selected to be integer sub multiples of the frame size to allow the entire data set to flow to the host That way the entire data frame can be moved immediately to the host without waiting for the next trigger frame Decimation The data may be decimated by a programmed ratio to reduce the data rate This mode is usually used when the data rate 1s less than the minimum master
112. ormation PCI Configuration Utility Config exe The Config exe applet is used to view all of the PCI configuration space variable data for any of Innovative Integration s PCI baseboards This tool is generally used as a low level diagnostic to troubleshoot installation problems But it is also capable of restoring previously memorized PCI Heer ede ere n 00060000 config space enumeration settings in the instance of target Irealthe ran ura urdet et application crash which inadvertently disrupts PCI config edo T Cache line Size z 2 2 8 3 8 eo z E 2 E gt 0004 1202 Peste toe SESE 1441 E HMM d ls E Sh 3 js an dr 13 sl t a E Kort server operational on sot POCONG MSDN Collection Integration Utility X3 SDF User s Manual EQ MSDN Collection Integration Utility Select chm File Select chi File Title String Version a Unique Ident er Gen GUID r Static MSDN Colection Language ID Colection Number MSDN Colection path hhcokeg dat path C l i Help Remove Integrate with MSDN Done 76 Linux Directory Structure X3 SDF User s Manual X3 SDF Hardware Introduction The X3 SDF is a member of the X3 XMC family that has four channels of 24 bit 5 MSPS A D conversion The A D converter is a delta sigma converter that has a usable dynamic range of over 105d
113. ows how to open the device for streaming Each baseboard has a unique code given in a PC For instance 1f there are three boards in a system they will be targets 0 1 and 2 The order of the targets is determined by the location in the PCI bus so it will remain unchanged from run to run Moving the board to a different PCI slot may change the target identification The Led property can be use to associate a target number with a physical board in a configuration Malibu method Open is called to open the device driver for the baseboard and allocate internal resources for use The next step is to call Reset method which performs a board reset to put the board into a known good state Note that reset will stop all data streaming through the busmaster interface and it should be called when data taking has been halted Connect Stream Stream ConnectTo amp Module StreamConnected true UI gt Status Stream Connected FHwPciClk Module Debug PciClockRate FHwBusWidth Module Debug PciBusWidth DisplayLogicVersion FChannels Module Input Info Channels Channels Once the object is attached to actual physical device the streaming controller associates with a baseboard by the ConnectTo method Once connected the object is able to call into the baseboard for board specific operations during data streaming If an objects supports a stream type this call will be implemented Unsupported stream types will no
114. performance is degraded X3 SDF User s Manual 79 Linux Directory Structure X3 SDF User s Manual 4 Input _ 10V 2 05K differential Figure 15 X3 SDF A D Channel Diagram Input Range and Conversion Codes The input has a 10 to 10 V differential full scale input 2K ohm input impedance Other input ranges may be custom ordered The output codes are 2 s complement 24 bit numbers Differential Input voltage V V Conversion Code hex 10 Ox7FFFFF 5 0x400000 OV 0x000000 5 0xA00000 10 0x800000 Table 16 A D Conversion Coding X3 SDF User s Manual 80 Linux Directory Structure X3 SDF User s Manual Driving the A D Inputs The X3 SDF has fully differential inputs with 2K input impedance The input range is specified as a differential voltage or 10V from V to V inputs with a common mode voltage of OV for full range The input signals should be driven differentially to realize the full performance of the A D The differential inputs reject common mode noise from the system and the card itself to improve the conversion results If you drive the inputs single ended the results will be worse by at least 6dB in most cases worse if the system noise is high For signal ended use the unused input must be grounded Input voltage range is limited to 5V to 5V for single ended use The 2K input impedance requires that the signal source be capable of driving 2 5 mA for full scale i
115. processing is the most common application The X3 SDF PMC card is high bandwidth analog capture module with an advanced architecture that provides ultimate flexibility and speed for the most advanced hardware assisted signal processing and ultrasonic signal capture The X3 SDF module streams in analog data and it 1s possible to log relevant data to host for post data analysis Because the maximum data rate from the X3 SDF module is under 80 MB s a logger that saves all of the data to the host disk is feasible X3 SDF Snap Example The X3 SDF Snap example in the software distribution demonstrates such functionality It consists of a host program in Windows which simultaneously works with user defined interface logic It uses the Innovative Malibu software libraries to accomplish the tasks Tools Required In general writing applications for the X3 SDF requires the development of host program This requires a development environment a debugger and a set of support libraries from Innovative Table 14 Development Tools for the X3 SDF Example Processor Development Environment Innovative Project Directory Toolset Host PC Borland Developers Studio C Malibu Examples Snap Bcb Examples Snap VC8 Microsoft Visual Studio 2005 Examples Snap Common Common Host Code On the host side the Malibu library is source code compatible with both environments The code that performs much of the actual function
116. r No Manual Stopped ok Critical No No msdsm Microsoft Multi Path Device S c windows s Kernel Driver No Manual Stopped oK Normal No No msfs Msfs cAwindowss File System D Yes System Running oK Normal No Yes mshidkmdf Pass through HID to KMDF Fil c windows s Kernel Driver No Manual Stopped ok Ignore No No msisadry msisadrv c windows s Kernel Driver Yes Boot Running ok Critical No Yes Maually Up grade MemDriver Perform the following steps to manually up grade MemDriver to the latest released version without reinstalling other Innovative Integration software 1 Obtain latest MemDriver release from Innovative Integration 2 Extract the content into folder C Innovative MemDriver Release 3 Open folder C Windows NSystem32 drivers and delete file memdrv sys 4 Copy the driver executable from C Innovative MemDriver Release driver 5 Copy the file memdrv sys to folder C Windows WSystem32 rivers 6 Reboot the system 7 Run the controller app according to instruction in section Running The Controller above 8 Verify the latest version of MemDriver is installed See file README txt Registry Settings MemDriver requires the certain values be set in the system registry If the driver is not operating properly perform the following steps to manually verify the registry setting and correct them 1 At Start menu type regedit 2 Navigate to the MemDriver registry key as shown and compare t
117. rates of bus master transfer traffic which each baseboard will generate Applications operating at transfer rates in excess of 20 MB sec should reserve additional contiguous busmaster memory to ensure gap free data acquisition To reserve this memory the registry must be updated using the ReserveMemDsp applet If at any time you change the number of or rearrange the baseboards in your system then you must invoke this applet to reserve the proper space for the busmaster region See the Help file ReserveMemDsp hlp for operational details Data Analysis Applets Reserve Memory for Dsp Baseboards j f si Number Installed Matador family Type System 2048 y BM Region Size KB 2048 y Rsv Region Size KB Configuration Total physical memory MB 255 Non paged pool size MB 4 Status k Update Help Exit Ready Binary File Viewer Utility BinView exe BinView is a data display tool specifically designed to 3 BinView c vista vistat 1 dump bin allow simplified viewing of binary data stored in data ac marh TBROG Q files or a resident in shared DSP memory Please see the Time Frequency Tes Summa Server on line BinView help file in your Binview installation X ZoomOut Zoomin gt gt directory olio Amplitude vs Offset Counts e9 e e D 10 20 30 40 50 Offset xL Sample Leap 10 60 70 80 90 100
118. re the state of user logic LED D5 can be controlled using the Innovative X3 SD Led property JTAG Scan Path The X3 modules have a JTAG scan path for the Xilinx devices on the module This is used for logic development tools such as Xilinx ChipScope and System Generator and for initial programming of the PCI FPGA configuration FLASH ROM There are three devices in the scan chain the Xilinx FLASH ROM Spartan 3E 250K used for PCI control and the Spartan 3 3A application logic When the devices are identified in the scan chain you will see these devices in this order Table 13 X3 Modules FPGA JTAG Scan Path JTAG Device Module Device Function Number 0 All X3 Xilinx XCF028 FLASH ROM PCI FPGA Spartan3E logic configuration ROM 1 All X3 Xilinx Spartan3E 250 FPGA Control FPGA for PCI XC3S250E 4FTG256C Interface 2 X3 SD X3 SDF Xilinx Spartan3 1000 FPGA Application Logic XC3S1000 4FGG456C optional 2M device could be installed here All others Xilinx Spartan3A DSP 1800 FPGA XC3SD1800 4FGG676C optional 3 4M device could be installed here FrameWork Logic Many of the standard X3 XMC features are implemented in the application logic This feature set includes a data flow triggering features and application specific features In many cases this logic provides the features needed for a standard data acquisition function and is supported by software tools for data analysis and logging In
119. re 31 Signal Quality 101 kHz 9 8Vp p 1000 ksps X3 SDF User s Manual 110 Linux Directory Structure X3 SDF User s Manual 0 X3 SDF 20 40 60 80 dB 100 120 140 160 180 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 KHz Max S N dB S N dB SINAD dB ENOB SFDR dB THD 9 dB 146 2 74 73 0 11 8 907 0 003982 88 0dB Figure 32 Signal Quality 101 kHz 9 8Vp p 4375 ksps 0 x3 sdf imod 990 and 1100 Hz dB do 100 120 140 160 10 3 10 2 10 1 100 101 KHz Max S N dB S N dB SINAD dB ENOS bits SFDR dB M amp dB 146 2 93 5 91 2 140 108 0 0 000642 103 8dB Figure 33 Intermodulation Distortion 990 and 1100 dual tone 50 ksps X3 SDF User s Manual 111 Linux Directory Structure X3 SDF User s Manual Connectors Input Connector JP1 JP 1connector is the front panel connector for the analog inputs external clock and external trigger inputs Connector Type MDR Number of Connections 68 Connector Part Number 3M part number 10268 55H3VC Mating Connector 3M part number 10168 6000EC IDC Digikey www digikey com P N MPB68A ND Cable Innovative part number 65057 MDR 68 male to male 36 inches 0 91meters This is the MDR68 as viewed from the front panel Pin 35 Pin 68 lt gt Pin 1 Pin 34 X3 XMC Front Panel View X3 XMC X3 SDF JP1 Front Panel Connector Pin Assignments X3 SDF User s Manual 112
120. reduce clock rates or stop data when the module is not in use The chapter discussing module specifics has information on both the power consumption and the power saving features that can be used LED Indicators The X3 modules have two LEDs one that is used for PCI Express interface and one from the application logic Both LEDs are on the back side of the card These LEDs are not visible from the front panel in most installations They are used primarily for debug The LED from the PCI Express interface FPGA D4 is usually used to find the target number of the module The Finder applet blinks the LED when the target module is addressed This allows systems with multiple modules to find out the software target number for each module Another use for the PCI LED is to indicate that the PCI interface logic loaded This LED should ALWAYS be on after the host computer boots If it is not on that means the PCI control logic did not load The possible causes for this are bad power defective module or missing PCI logic image In any case if this LED is off the card will not communicate to the host system The second LED D5 is from the application logic The purpose of this LED is to indicate that the application logic has been configured and to blink when an over temperature condition occurs Custom logic designs can use it for any purpose When X3 SDF User s Manual 50 Linux Directory Structure X3 SDF User s Manual using the stock firmwa
121. rolled by the UsesExtendedDioPort class Its properties Table 6 IUsesExtendedDioPort Class Operations DioPortConfig Configures banks of bits for input or output DioPortData Broadside Read Write to low order 32 bits of DIO DioPortDataHigh Property Broadside Read Write to high order 12 bits of DIO Only Typical use of the digital IO port involves first configuring the port using the DioPortConfig operator This sets the byte direction and the clock mode The port is then ready for read write operations via DioPortData or DioPortDataHigh Hardware Implementation Digital I O port activity is controlled by the digital I O configuration control and data register Port direction is controlled by the configuration control register Bit Function 0 DIO bits 7 0 direction control 0 input default 1 DIO bits 15 8 direction control 0 input default 2 DIO bits 23 16 direction control 0 input default 3 DIO bits 31 24 direction control 0 input default 4 DIO bits 39 32 output enable 0 input default 5 DIO bits 43 40 output enable 0 input default X3 SDF User s Manual 42 Linux Directory Structure X3 SDF User s Manual Bit Function 30 6 31 Sample DIO inputs when DIO EXT CLK is true otherwise always sample 0 sample always default Figure 8 DIO Control Register BAR1 0x14 Port Address DIO L BAR1 0x13 DIO H BARI 0x16
122. rst 240 MB s sustained Velocia packet system interface main path for data communications Command Channel 5 MB s sustained Command control and status SelectMAP 5 MB s Application logic configuration Data Buffering and Memory Use There are two 2MB SBSRAM devices attached to the application FPGA that provide data buffering and computational RAM for FPGA applications X3 SDF User s Manual 40 Linux Directory Structure X3 SDF User s Manual Computational SRAM The SRAM on the X3 family is a 2MB memory dedicated as FPGA local memory Applications in the FPGA may use the SRAM as a local buffer memory if the data buffer is too large to fit in FPGA block RAMs or as memory for an embedded processor in the FPGA The SRAM device connected to each Application FPGA is 2 MB total size organized as 1M by 16 bits X3 SD and X3 SDF or 512K by 32 bits all others This device is a synchronous ZBT SRAM and supports clock rates up to 100 MHz on X3 SD and X3 SDF 133 MHz on all other modules All SRAM control and data lines pins are directly connected to the FPGA allowing the SRAM memory control to be customized to the application The Framework Logic provides a simple SRAM interface that can be readily modified for many types of applications Detailed explanation of the interface control logic is described in the FrameWork Logic User Guide The Framework Logic provides a simple register interface to the SBSRAM control logic that is u
123. s X3 SDF User s Manual Introduction Real Time Solutions Thank you for choosing Innovative Integration we appreciate your business Since 1988 Innovative Integration has grown to become one of the world s leading suppliers of DSP and data acquisition solutions Innovative offers a product portfolio unrivaled in its depth and its range of performance and I O capabilities Whether you are seeking a simple DSP development platform or a complex multiprocessor multichannel data acquisition system Innovative Integration has the solution To enhance your productivity our hardware products are supported by comprehensive software libraries and device drivers providing optimal performance and maximum portability Innovative Integration s products employ the latest digital signal processor technology thereby providing you the competitive edge so critical in today s global markets Using our powerful data acquisition and DSP products allows you to incorporate leading edge technology into your system without the risk normally associated with advanced product development Your efforts are channeled into the area you know best your application Vocabulary X3 SDF User s Manual 10 Table of Contents X3 SDF User s Manual What is X3 SDF The X3 module Family are XMC VITA 42 3 modules with a variety of IO capabilities and a PCI Express interface Each modules has a Spartan 3 application FPGA buffer memory and clocking features
124. scesesnecesseacessesaeestesrsesenseennsesenersrees 115 T ble 32 P15 Signal Descriptions 5 an e e EO E ad seis eet E tigna 116 Table 33 X3 SDF XMC Secondary Connector P16 Pinout essen eene 118 Table 34 PT6 Sipnal Descriptions et e eto tiet d eO e bec t re eee OR E 119 Table 35 X3 SDF JP3 Xilinx JTAG Connector Pinout eessssssesseseeeeeee nennen enne ennt 121 X3 SDF User s Manual Table of Contents X3 SDF User s Manual List of Figures Figure T Vista Verification Dialog aes eee epe ias 23 Figure 2 Innovative Install Pr eR LR ese Te ete ec eld ei Renee oues E pta bags eine 24 Figure 3 Progress is shown for each section eren iei i nnne nnne 25 Figure 4 Toolset registration fom te ea estere eere aee dine nde aba Eo c Pede qu a denote dirias 26 Figure 5 BusMaster configuration e ais 26 Figure 6 Installation cotiplete iE edes rado 27 Figure 7 X3 XMC Family Block Diagr in ee dera a eMe ees 35 X3 Computing Core Block Di gram siepe nce dada a aihe 38 Figure 8 DIO Control Register BAR 40x14 enne nennen neret nnne nennen nne nnne nens 43 Figure 9 Digital IO Port Addresses nace no eren Hera vero d hanna eeiam e aa 43 Figure 10 DIO Control Register BAR 1 0x14 seesessssesseseseeeeeeeenenne neret nnn rennen 45 Figure 11 Digital IO Port Addresses aen here e ero dite erp qn ied e ee 45 Figure 12 Digital VO Port Litring ii A ia 45 Figure 13
125. sed for test and demonstration FPGA logic developers can easily replace the simple register interface logic to build on top of the high performance logic core when integrating the SRAM into their logic design MATLAB developers frequently use the SRAM as the real time data buffer during development Since the MATLAB Simulink tools operate over the FPGA JTAG during development at a low rate it is necessary to use the SRAM for real time high speed data buffering The MATLAB Simulink library for the X3 modules demonstrate the use of the SRAM as a data capture buffer The SRAM captures real time high speed data that can then be read out into MATLAB for analysis or display as a snapshot This allows high speed real time to be captured and brought into MATLAB Simulink over the slow 10Mb sec JTAG link See the X3 FrameWork Logic User Guide for more details and examples Data Buffer SRAM The second SRAM is provides a 2MB memory pool local to the FPGA The Framework Logic implements a data buffer with one or more queues for the A D and D A streams as appropriate for the particular X3 module In the Framework logic the SRAM use is demonstrated as a multiple queue FIFO memory that divides the 2 MB memory buffer into separate queues virtual FIFOs for input and output The logic component referred to as Multi Queue SRAM controls the SRAM to create the FIFO queue functionality Custom logic applications can use the Multi Queue SRAM buffer component to add
126. sensors X3 SD16 16 channels of 24 bit 144 kHz A D and Xilinx Spartan3A DSP 1 8M Vibration monitoring 192 kHz D A with programmable gain and recording control Acoustic instrumentation front end Xilinx monitoring Geophysical Spartan3A DSP FPGA sensor interfaces Table 1 X3 XMC Family The X3 XMCs feature a Xilinx Spartan3 or Spartan3A DSP FPGA core for signal processing and control In addition to the features in the Spartan3 3A logic such as embedded multipliers and memory blocks the FPGA computing core has two local SRAMs for data buffering and computing memory There are also a number of support peripherals for IO control and system integration Each XMC may have additional application specific support peripherals X3 SDF User s Manual Linux Directory Structure X3 SDF User s Manual Table 2 X3 XMC Family Peripherals Peripheral Features XMC 3 PCI Express interface The XMC 3 host interface Integrates with PCI Express systems using one lane operating at 2 5 Gbps that provides up to 180 MB s sustained data rates This interface complies with VITA standard 42 3 which specifies PCI Express interface for the XMC module format The Velocia packet system provides fast and flexible communications with the host using a credit based flow control supporting packet transfers with the host A secondary command channel provides independent interface for control and status outside of the data channel that is extensible to custo
127. ses state of the art software techniques to bring our baseboards to life in the Windows environment These software tools allow you to create applications for your baseboard that encompass the whole job from high speed data acquisition to the user interface Finding detailed information on Malibu Information on Malibu is available in a variety of forms e Data Sheet http www innovative dsp com products malibu htm e On line Help Innovative Integration Technical Support nnovative Integration Web Site www innovative dsp com Online Help Help for Malibu is provided in a single file Malibu chm which is installed in the Innovative Documentation folder during the default installation It provides detailed information about the components contained in Malibu their Properties Methods Events and usage examples An equivalent version of this help file in HTML help format is also available online at http www innovative dsp com support onlinehelp Malibu Innovative Integration Technical Support Innovative includes a variety of technical support facilities as part of the Malibu toolset Telephone hotline supported is available via X3 SDF User s Manual 12 Table of Contents X3 SDF User s Manual Hotline 805 578 4260 8 00AM 5 00 PM PST Alternately you may e mail your technical questions at any time to techsprt innovative dsp com Also feel free to register and browse our product forums at http forum iidsp co
128. si osecceex ect eee eupuec teneo deo eo Rue e eus essa OE NNU Ce Tetra eu Uie Nu e denne Foto queo pue va ea ee Cote ud rea Resa sdes le Starting the Installation a ERR ae 23 The Installer Progr m onera eee e EGRE een es 24 Tools curi pui er H 20 Bus Master Memory Reservation Applet essere nnne nete enne n nenne nnne nnne 26 Hardware Installation daniel eo esae naso o caue ied sosse seoan usa eel t incaico O eee eps HTC Installation on a Deployed System ooi ehoe tein teas dusk eod seen iR oseo dod ieu ea ep ia epor o ebbe ee kpP a ede ko ee PERO Ra canes 2O Runnng Malib Red 3 ree TR De dp ie 28 Mem Driver Installation Windows ee eee eee ee eee eee eee enne esee eese sese senos sese ee eee eee essseseeeeeeeeeeessseeeeee se D L About the X3 XMC Modules 5 5 6 ose eiie eo eae ee ee eoe ta oae eei no ei ra Fa ee on eee Cen sa ee da cosa oe eee vene Poo eoe oe eae aeo sesers OD KS YE Tdi RENE NL III ELI NI EXeousiid nigde c S XIJ PCI Express teria ds Data Buffering and Memory USE voii fl Computational ss RAM n sene aem 41 Data Buffer SRAM iii abad hice 41 EEPROM iinn taina E A REEE 41 DADO add A A OR ED debe e em e Bn P CP UE 42 Hardware Impletnentati n s tee fade RR tret dut tbu t et aee ete 42 Front Pane
129. ssProgressEvent amp event UI gt UpdateLogicLoadProgress event Percent Process progress events are issued to give a percentage progress of the entire operation These event are handled by HandleProgress This handler calls a UI method UpdateLogicLoadProgress where a Progress bar control is updated to give a visual effect of the loading progress void ApplicationIo HandleLoadComplete ProcessCompletionEvent amp event UI gt Log Load completed ok DisplayLogicVersion Finally the logic loader issues a process completion event when the load is complete This event is handled by HandleLoadComplete as shown above In this case all we do is update the UI so the user can see that the logic configuration is complete and application status is idle In other cases this could trigger the application to automatically perform additional tasks Starting Data flow After downloading interface logic user can setup clocking and triggering options The stream button then can be used to start streaming and thus data flow void ApplicationlIo StartStreaming if StreamConnected UI gt Log Stream not connected Open the boards return Set up Parameters for Data Streaming X3 SDF User s Manual 64 Linux Directory Structure X3 SDF User s Manual First have UI get settings into our settings store UI GetSettings Before we start streaming all necessary parameters must be
130. t active ADC Overrange An ADC channel was overranged Alert Packet Format Alert data packets have a fixed format in the system The Peripheral Device Number PDN is programmable in the software and is included in the packet header thus identifying the alert data packets in the data stream The packet shows the timestamp in system time what alerts were signaled and a status word for each alert Dword Description Header 1 PDN amp Total N of Dwords in packet e g Headers data payload Header 2 0x00000000 Alerts Signaled Timestamp 0 Software Word temp sensor error amp temp error amp 00 amp X 000 amp temp data YIN APRIL WLNIR oO temp_warning amp 000 amp X 000 amp temp_data d oo 0 12 X 1303000 amp 000 amp mq overflow 0 35 13 unused Table 27 Alert Packet Format Since alert packets contain status words such as temperature for each packet a software alert can essentially be used to read temperature of the module and so that 1t can be recorded X3 SDF User s Manual 94 Linux Directory Structure X3 SDF User s Manual Software Support Applications have different needs for alert processing Aside from the bulk movement of data most applications require some means of handling special conditions such as post processing upon receipt of a stop trigger or closing a driver when an acquisition is completed
131. t compile void Applicationlo Close Stream gt Disconnect Board Close FOpened false X3 SDF User s Manual 62 Linux Directory Structure X3 SDF User s Manual Similarly the Close method closes the hardware Inside this method first we logically detach the streaming subsystem from its associated baseboard using Disconnect method Malibu method Close is then used to detach the module from the hardware and release its resources Logic Loading The user interface logic for the module must be loaded at least once per session it remains valid until power is removed from the board In the following code we show how to browse and configure the desired logic In the UI when the logic browse button is pressed LogicLoadBrowseBtnClick method gets called as shown below void fastcall TMainForm LogicLoadBrowseBtnClick TObject Sender std auto ptr TOpenDialog Dialog new TOpenDialog NULL Dialog gt Filter Logic File exo exo All Files Dialog gt Title Select FPGA Logic File if LogicFilenameEdit gt Text Length Dialog gt InitialDir ExtractFilePath LogicFilenameEdit gt Text if Dialog Execute LogicFilenameEdit gt Text Dialog gt FileName The code above opens a dialog allowing the user to browse for logic file The filter property of this dialog masks out all the files in a folder other than exo file If the user cancels out no change will occur in the selectio
132. tandard reference clock is 24 576 MHz to the PLL although an external reference may be used The output of the PLL section of the AD9510 can therefore be programmed to many numbers in the range of 100 to 140 MEZ that may be subsequently divided in the PLL outputs The dividers in the clock distribution section of the AD9510can be used to further divide the clock by 1 to 32 with the restriction only even numbers are used to make the clock a 5096 duty cycle The external clock and optional fixed oscillator are connected to the CLK1 input The PLL must be programmed to use one of these two clock sources for the outputs The clock dividers on the outputs should be programmed to the same divisor to work with the standard logic X3 SDF User s Manual 87 Linux Directory Structure X3 SDF User s Manual The AD9510 is programmed during initialization of the card All configuration registers are written then an update command is sent to the PLL that makes the outputs update simultaneously After an update the clock is stable when the PLL status bit indicates a lock but the A Ds require additional time to stabilize so a 1 ms period should be allowed for stabilizing the clock Timing Analysis There are several timing parameters associated with the clock control circuitry that affect the measurement process The following table summarizes two important effects Timing propagation delay through the logic for external clocks are shown for the maximu
133. te alert packets when enabled Both temperature warning and failure are latched when they occur and must be cleared by a read their respective registers Table 12 Temperature Alarms Alarm Setting Temperature Celsius Set Register to Warning 70 X 460 Fail 85 X 550 A temperature failure results in a power down signal to the analog electronics signaling to shut down The FPGA and host interface remain active and the module should continue to communicate unless a catastrophe has occurred The thermal shutdown behavior of each X3 module is detailed in the specific discussion of that t module The power down can be cleared by reading from the temperature fail register The temperature sensor must be present and responding for the module to operate If the temp sensor fails this is treated as a temperature failure The logic continues to attempt to communicate with the temperature sensor If multiple failure conditions are found the logic should be reloaded Note that the control logic for the temperature sensor is in the application logic so the logic must be configured to provide thermal protection It is unlikely except in cases of catastrophic failure that the module will overheat when the logic is not loaded since it is central to module operation Software support tools provide convenient access to the temperature and thermal controls These should be used in application programming configure and monitor t
134. ther VHDL or MATLAB Signal processing data analysis and unique functions can be added to the X3 modules to suit application specific requirements See the X3 FrameWork Logic User Guide for further information X3 PCI Express Interface The X3 module family has a PCI Express interface that provides a lane 2 5 Gbps full duplex link to the host computer The interface is compatible with industry standard PCI Express systems and may be used in a variety of host computers The following standards govern the PCI Express interface on the X3 XMC modules Table 4 PCI Express Standards Compliance Standard Describes Standards Group PCI Express 1 0a PCI Express electrical and protocol standards PCI SIG http www picmg com 2 5 Gbps data rate ANSI VITA 42 XMC module mechanicals and connectors VITA www vita org ANSI VITA 42 3 XMC module with PCI Express Interface VITA www vita org The X3 module family uses a Texas Instruments bridge chip to go from PCI Express to a local PCI bus on the module The PCI Express bridge works with the PCI FGPA to implement the Velocia packet system for data communications and also provides the module configuration and control features X3 SDF User s Manual 39 Linux Directory Structure X3 SDF User s Manual a P Data link to App Logic 32 bit 66 MHz PCI Express rigg i Ec a ww Serial Link aid PCI Express Local PCI Bus Sue X1 or x4 lane 32 bit
135. this manual the FrameWork Logic features for each card are described in in general to explain the standard hardware functionality The X3 FrameWork Logic User Guide provides developers with the tools and know how for developing custom logic applications See this manual and the supporting source code for more information The X3 XMC modules are supported by the FrameWork Logic Development tools that allow designs to be developed in HDL or MATLAB Simulink Standard features are provided as components that may be included in custom applications or further modified to meet specific design requirements X3 SDF User s Manual Linux Directory Structure X3 SDF User s Manual Integrating with Host Cards and Systems The X3 XMCs may be directly integrated PCI Express systems that support VITA 42 3 XMC modules The host card must be both mechanically and electrically compatible or an adapter card must be used The XMC modules conform to IEEE 1386 specification for single width mezzanine cards This specification is common to both PMC and XMC modules and specifies the size mounting mating card requirements for spacing and clearances There are several adapter cards that are used to integrate the XMC modules into other form factor PCI Express systems such as desktop systems There are also adapter cards to electrically adapter the PCI Express XMC modules in older PCI systems that use a bridge device between the two buses PCI is not
136. ting the Board Install The normal board install is complete with the installation of the files The board driver install is already complete with the loading of the Malibu Red package If there are any board specific steps they will be listed at the end of this chapter Linux Directory Structure When a board package is installed its files are placed under the usr Innovative folder The base directory is named after the board with a version number attached for example the version 2 0 X5 400 RPM extracts into usr Innovative X5 400 2 0 This allows multiple version of installs to coexist by using a symbolic link to point to a particular version Changing the symbolic link changes with version will be used Under the main directory there are a number of subdirectories Applets The applets subdirectory contains small application programs that aid in the use of the board For example there is a Finder program that allows the user to flash an LED on the board to determine which board is associated with a target number See the Applets chapter for a fuller description of the applets for a board Documentation This directory contains any documentation files for the project Open the index html file in the directory with a web browser to see the available files and a description of the contents Examples This directory and its subdirectories contain the projects source and example programs for the board Hardware This directory cont
137. to support the IO functions Two SRAMs are used one each for buffer memory and application memory Then XMC has a 32 66 PCI interface to a single lane PCIe bridge chip DIO using P16 connection to the baseboard For sample rate generation the X3 SDF has a precision low noise PLL or external clocks Trigger modes including software framed and external triggering provide precise control over sample acquisition and synchronization with other devices Timestamped alerts also provide the ability to monitor the acquisition process and correlate system events to the data Data acquisition control signal processing buffering and system interface functions are implemented in a Xilinx Spartan3 FPGA 1M gate device Two 1Mx16 memory devices are used for data buffering and FPGA computing memory The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset The MATLAB BSP supports real time hardware in the loop development using the graphical block diagram Simulink environment with Xilinx System Generator The PCI Express interface supports continuous data rates up to 180 MB s between the module and the host A flexible data packet system implemented over the PCIe interface provides both high data rates to the host that is readily expandable for custom applications What is Malibu Malibu is the Innovative Integration authored component suite which combines with the Borland Microsoft or GNU C compilers and IDEs to support
138. trical Characteristics Parameter Value Notes Input Voltage Max 3 6V Exceeding these will damage Min 0 3V the application FPGA Signaling LVDS 2 5V EIA 644 Standard Input common Min 0 30V mode voltage Typ 1 25V Max 2 20V Input Logic Min 0 10V Differential voltage Vin Vin Thresholds Typ 0 30V Max 0 60V Termination 100 ohms X3 SDF User s Manual 46 Linux Directory Structure X3 SDF User s Manual Table 11 Digital IO Clock Input Electrical Characteristics Notes on Digital IO Use The digital IO on X3 family as supported using the standard FrameWork Logic is intended for low speed bit IO controls and status The interface is capable of data rates exceeding 75MHz and custom logic developers can implement much higher speed and sophisticated interfaces by modifying the logic The digital IO clock input and LVDS signal pair is a capable of rates exceeding 200 MHz Since the bit IO is connected to the command channel interface in the standard logic this limits the effective update or read rate to about 200 kHz The limitation on this rate is the slow speed of the command channel itself Again custom logic implementations can achieve much higher data rates The X3 FrameWork Logic user Guide details logic supporting the digital IO port and gives the pin information for customization Serial EEPROM Interface X3 modules have a serial EEPROM for storing data such as board ident
139. tricted access to applets At the conclusion of the installation process ReserveMem exe will run except for SBC products This will allow you to set the memory size needed for the busmastering to occur properly This applet may be run from the start menu later if you need to change the parameters For optimum performance reserve at least 64 MB of memory for each Innovative board to be used simultaneously within the PC plus 32 MB for other system use For example if using two X5 400M modules reserve 2 64 32 MB 160 MB To reserve this memory the registry must be updated using the ReserveMem applet Simply type the desired size into the Rsv Region Size MB field click Update and the applet will update the registry for you If at any time you change the number of boards in your system then you must invoke this applet found in Start All Programs Innovative target board Applets Reserve Memory After updating the system exit the applet by clicking the exit button to resume the installation process 26 Linux Directory Structure X3 SDF User s Manual At the end of the install process the following screen will appear Installation The installation is complete Shut down your computer and install your board s then reboot your computer The drivers should load automatically and your board will become available Please referto your Hardware Software Manual for instructions on hardware installation priorto powering
140. u LinuxPeriphLib ver rel 1586 rpm Board files and examples X5 210M X5 210M LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 10M X3 10M LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 25M X3 25M LinuxPeriphLib ver rel i586 rpm Board files and examples X3 A4D4 X3 A4D4 LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 SD X3 SD LinuxPeriphL ib ver rel 1586 rpm Board files and examples X3 SDF X3 SDF LinuxPeriphLib ver rel i586 rpm Board files and examples X3 Servo X3 Servo LinuxPeriphLib ver rel i586 rpm Board files and examples SBC ComEx Sbc ComEx LinuxPeriphLib ver rel 1586 rpm Board files and examples Unpacking the Package As root type rpm i h X5 400 LinuxPeriphLib 1 1 4 i1586 rpm This extracts the X5 400 board files into the Innovative root directory Use the package for the particular board you are installing Creating Symbolic Links The example programs assume that the user has created symbolic links for the installed board packages A script file is provided to simplify this operation by the Malibu Red package In the MalibuRed KerPlug directory there is a script called quicklink quicklink X5 400 1 1 These commands will create a symbolic link x5 400 pointing to X5 400 1 1 This script can be moved to the user s bin directory to allow it to be run from any directory X3 SDF User s Manual 16 Completing the Board Install X3 SDF User s Manual Comple
141. vent will be issued to process the incoming data This event is set to be handled by HandleDataAvailable After processing the data will be discarded unless saved in the handler Similarly OnDataRequired event is handled by HandleDataRequired Configure Stream Event Handlers Stream OnDataAvailable SetEvent this amp ApplicationIo HandleDataAvailable Stream OnDataAvailable Synchronize In this example a Malibu SoftwareTimer object has been added to the Applicationlo class to provide periodic status updates to the user interface The handler below serves this purpose X3 SDF User s Manual 61 Linux Directory Structure X3 SDF User s Manual Timer OnElapsed SetEvent this amp ApplicationIo HandleTimer Timer OnElapsed Thunk An event is not necessarily called in the same thread as the UI If it is not and if you want to call a UI function in the handler you have to have the event synchronized with the UI thread The call to Synchronize directs the event to call the event handler in the main UI thread context This results in a slight performance penalty but allows us to call UI methods in the event handler freely Creating a hardware object does not attach it to the hardware The object has to be explicitly opened The Open method open hardware Open Devices Module Target Settings Target Module Open Module Reset UI gt Status Module Device Opened Opened true This code sh

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