SoCWire User Manual
Contents
1. 1 1 Software License This license governs the use of this software and your use of this software constitutes acceptance of this license Agreement with all points is required to use this software 1 These source files may be used and distributed without restriction provided that the software license statement is not removed from the file and that any derivative work contains the original software license notice and the associated disclaimer 2 The source files are free software you can redistribute 1t and or modify 1t under the restriction that UNDER NO CIRCUMTANCES this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE This implies modification and or derivative work of this Software 3 This source is distributed in the hope that it will be useful but WITHOUT ANY WARRANTY without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE Y our rights under this license are terminated immediately if you breach it in any way 1 2 Software package content This software package comprises CODEC SoC Wire CODEC source files SoCWire Switch source files Testbench lt CWire CODEC Testbench 1 SoCWire CODEC configured in loopback mode packets with different length are send over the link SoCWire network testbench 1 Switch and 4 nodes communication example e Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04 09 User Manual ie i 7 30 2 SoCWire SoCWire is based2. End 1 End 2 After 6 4 ys Exchange of Slicence After 6 4 us After 12 8 ys After 12 8 ps NULL received Ls q NULL received FCT Received FCT Received Figure 6 SoCWire link connection adapted from 1 The timeouts After 6 4 us and After 12 8 us follow the SpaceWire standard Since SoCWire is in a complete synchronized on chip environment these timeouts can be decreased Additional detection of disconnection timeout has a window of 850 ns in the Space Wire standard and can also be decreased Range 1 ns after64 1 to 6400 after128 1 to 12800 1 to 850 Table 2 SoCWire timeout generics In simulation after64 64 after128 128 and disconnect detection 85 has been successfully tested This has to be verified in hardware Reference SoCWire SoC Wire Draft 1 Issue Rev Date 22 04 09 User Manual a e 9 30 3 3 Packet Level The packet level describes the format to support routing of packets over a SoCWire network A SoCWire packet comprises Destination Address plus Cargo plus EOP EEP as depicted in Figure 7 Figure 7 SoCWire packet The Destination Address 1s required to send packets over a SoCWire network to a certain target Depended on the network topology multiple destination addresses can follow before the Cargo begins For point to point communication the destination address is not required The Cargo contains the user data Regular packets are completed
3. 0 The parity bit is set to 1 to cover the odd parity In run state the transmitter sends NULL character to sustain the link connection e Reference SoCWire SoCWire pai Issue Rev Date 22 04 09 User Manual TU Bau Page 17 of 4 2 Configuration options range datawidth data word width 8 8192 8 speed 1 100 after64 7 us timeout unit ns 1 6400 ui after128 12 8 us timeout unit ns 1 12800 12800 disconnect detection disconnect detetction timeout 1 850 4 3 Signal description 30 Signal name Range Type Function Active st input Reset sigh dk put Clock S S o RR input Link Enable When assert CODEC can High move to Ready state and socw_dis Input Link Disable When assert and in Run state CODEC moves immediately to Error Reset state Io A r mvaid aan co wvaid Output When assert current blink data is valid High dat full Output Input Data Interface Indicates the input Hiah Fifo is full write is rejected 9 PRE nwrite Lul ere Data Interface Write data to a din datawidth ee Input Input Data Interface User data datawidth 1 0 Data control flag datawidth Gares ft Rec data fon CODES dat_empty Output Indicates fifo empty no data available dat_dout datawidth EE Output User data datawidth 1 0 Data control Flag active Output When active link is connected and High running transmission can start 9 Wi R
4. e Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04 09 User Manual Baa e di 30 4 7 Resource utilization and timing The SoCWire CODEC has been implemented and tested in Xilinx Virtex 4 LX60 10 Figure 13 shows the occupied area absolute values and maximum clock frequency Appendix A shows detailed information of the SoCWire CODEC implementation 230 228 228 V 225 V i 221 Lut 290 4 v E e_ FF A BRAM y N N al 215 210 Resource Utilization N Core Clock Frequency MHz 200 Data Word Width Bit Figure 13 SoCWire CODEC synthesis report Xilinx Virtex 4 LX60 10 5 SoCWire Switch The SoCWire Switch enables the transfer of packets arriving at one link interface to another link interface on the switch The SoCWire Switch provides a configurable number of ports realized by internal SOCWire CODECS Entrance Matrix SoCWire Switch Figure 14 SoCWire Switch e Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04 09 User Manual Pago 21 7 30 5 1 Structure The SoCWire Switch comprises at least 5 modules The number of SoC Wire CODECS are equivalent to the number of ports Each cell module represents an inter connection between two ports and therefore a switch with 4 ports comprises 16 cells or with 32 ports 1024 cells SoCWire Switch socwire switch SoC Wire CODEC socw_codec Equivalent to th
5. gt S oCWir e Reference SoCWire Issue Draft Rev Sh A Za Date 22 04 09 User Manual TU Braunschweig Page 1 of 30 SYStem on Chip Wire SoCWire User Manual Issue Draft Revision 1 SoCWire V1 0 22 04 09 Prepared by Bj rn Osterloh SoCWire User Manual Reference SoCWire Issue Draft Date 22 04 09 Page 2 Page left free intentionally Rev of 30 o Reference SoCWire R SoCWire Draft 4 Issue Rev j Date 22 04 09 uu E User Manual TU Braunschweig Page 3 of 30 DOCUMENTATION CHANGE RECORD Llssue Rev Pages Date Changes Author Dra Pr fan 220409 Drafilssue BO a D o Reference SoCWire Issue Rev Date 22 04 09 renti User Manual p 4 og 30 TABLE OF CONTENTS Genera OSN fid 5 1 1 Sacile 6 1 2 SOL Ware COME atardecer leelo lolas ita riot 6 gt plico 7 BA OOM i cb J 3 1 Aa A E E A bb 7 3 1 1 Data Charcas adela YC J 3 12 Control Marac lei detal ici 8 31 3 bilia 8 3 1 4 TSOP AIG Ts sondeo iaia 9 32 Txchancse Level KK TO 9 32 4 FION OOO y ilaele 9 3 22 Sail 10 3 233 Ns OT 11 A ili A ili al ie 11 3 3 1542 16 o A O A A 12 3 4 Nilla 12 4 SOON IS CODE CC a el ascos isa 13 4 1 SUC ROC aaron aera AAN ERAT T AE AA AN IR TRE RIT VIT E OTT TT TT 14 4 1 1 Sluc agenti iii i 14 4 1 2 LA IN 14 4 1 3 in 15 4 1 4 Ironia 15 4 1 5 LERNIA ER ION O 15 4 2 Contour ton OP OMS nia 17 4 3 Signal descripta
6. 09 User Manual a aA ei 30 Figure 16 shows a SoCWire network with 4 nodes in a star topology The simulation shows the nodes A B C and D from top to bottom For each node the transmit tx dat in and receive rx dat dout signals are shown The signals dat nread dat nwrite dat empty and dat full are represented by bit vectors The MSB left 1s therefore node D and LSB right node A In the first operation all nodes are set in read mode with dat_read 0 Concurrently node A and B start a write cycle Node A sends data to its own port loopback and sets the header to 000 orange marked Node Bs destination is node D and therefore sets the header to 003 green marked One clock cycle later node C sends data to node D purple marked and node D sends data to C blue marked The following transmissions make clear that the packets are received in the order they have sent The packet from C to D blue has to wait until the packet from B green is completely received by D Between the 2 packets the receiver of node D receives a NULL character grey this is caused by the round robin scheduling of the switch 5 5 Data Rates The SoCWire Switch basically consists of a number of SoCWire CODECS according to the number of ports and additional fully pipelined control machines The maximum data rate 1s therefore equivalent to the SoCWire CODEC 5 6 Resource utilization and timing The SoCWire Switch is a fully scalable design su
7. 09 User Manual ns a 30 Data Word Width 16 Bit LX 60 Total number of SoCWire Switch Resource SLICEs 26624 53248 Utilization 53248 BRAMs 160 Core CLK L BRAM Slice Lut FF MHz ut 90 5 2 1 1 404 1629 404 324 1782 3 7 2226 4161 O 262 O 817 4 1 2 3 6 7 0 O O O OO N 12 13 3566 14 3935 L 3 4 2 6 1 15 4 3 0 5 4 4 1 2 2 6 Ei il 1 16 14 3 19 6 8 16 4716 17 5056 1 22 35 27 0 14495 2 27 9985 6 18443 33590 11050 60 69 18892 8 32 19423 12271 11 4 1 3 9 1 1 8 8 5 E NENE a Le Led a LA _ 14 NE 16 ia am Cae EA e Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04 09 User Manual Pas 30 a 30 Data Word Width 32 Bit LX 60 Total number of SoCWire Switch Resource SLICEs 26624 53248 Utilization 53248 BRAMs 160 Core CLK BRAM Frequency Lut BRAM Slice Lut FF MHz 094 568 95 78 6 150 1 1831 NID INTO WIN OIA IO 00 28 N N oO LS 15 34 OO N Xx dh dh OI N Co 2 00 00 N al N N OO O O N 00 N al al N O al N O N N md O 00 00 4928 55 19 23 99 334 7 1 62 00 10304 11365 13255 14704 92 1573
8. OR CreditError OR Link Disabled RxErr OR gotFCT OR gotN Char RxErr OR gotN Char OR after 12 8 us RxErr OR RxErr OR gotFCT OR gotFCT OR gotN Char OR gotN Char after 12 8 us after 12 8 us gotFCT gotNull Link Enabled Figure 5 SoCWire CODEC state machine adapted from 1 The ErrorReset is the initial state after an external reset a link operation is terminated or if an error occurs during link initialization In ErrorReset state both transmitter and receiver are in reset If reset is de asserted this state will be move after 6 4 us into ErrorWait In ErrorWait the receiver 1s enabled and wait for 12 8 us This time period make sure that both ends of the link are ready to receive data before either ends begins transmission The Ready state checks if the interface has permission Link Enable to buildup a link If Link Enable is true the state machine moves on into Started and waits 12 8 us for NULL characters If during this time period NULL characters are received the state machine moves into Connecting and waits 12 8 for us FCTs If an FCT 1s received the state machine moves into Run The Run state 1s the state of normal operation e Reference SoCWire SoC Wire Draft 1 Issue Rev Date 22 04 09 User Manual TU eE Page 11 of 30 3 2 3 Link Connection Figure 6 shows the SoCWire link connection flow
9. code 8 bit length NULL ESC FCT Odd parity is assigned to data and control characters to support the detection of transmission errors The parity bit covers the previous eight bits of a data character or two bits of a control character Figure 3 shows the different characters Control Characters E 1 0 i FCT Flow Control Token EOP Normal End of Packet EEP Exceptional End of Packet j 1 ESC Escape Control Code NULL ESC FCT Figure 3 Control Characters amp Control Code 3 1 3 Parity Odd parity 1s assigned to data and control characters to support the detection of transmission errors The parity bit covers the previous eight bits of a data character or two bits of a control character the parity bit and the data control flag lt lt Data Character EOP e FCT _ gt ena nen Parity Coverage Parity Coverage Figure 4 SoCWire Parity Coverage Figure 4 shows the parity coverage for a data character followed by EOP followed by FCT The parity bit of the EOP covers the previous eight bit of the data character and the data control flag of the EOP The FCT parity bit is calculated with both control bits of EOP and data control flag of FCT In this case the parity bit is 1 and therefore an odd number of 1 s for the parity coverage e Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04 09 User Manual TU eE Page 9 Of 30 3 1 4 EOP and EEP The hos
10. dat_dout datawidth 0 e Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04 09 User Manual Page AA g 30 4 1 Structure The SoCWire CODEC consists of 6 modules SoCWire CODEC socwire_codec State machine state_machine This module controls the operation of the SoCWire CODEC It response to errors and user requests Rx receiver This module decodes the link data and sends the decoded user data to RX Fifo All read operations are operated by this module Link errors are detect and forward to the state machine Rx Fifo receive_fifo The Rx Fifo receives the user data from the receiver and transfer it to the host interface It checks the outstanding counter and controls the FCT handling Dual Port Ram dp_ram Cascadable dual port ram to store received data Tx transmitter The transmitter module operates all write operation on the SoCWire link The module codes the user data calculates the parity and includes FCTs in the data flow of the link It permanent sends data to prevent a disconnection error Tx Fifo tx_fifo The TX Fifo transmits the user data from the host interface to the transmitter It controls the credit flow and checks the credit counter to send the appropriate amount of user data 4 1 1 State Machine The state machine describes the SoCWire CODEC finite state machine Its states are analog to Figure 5 and response to the external signals socw_en and socw dis socw
11. on the SpaceWire standard 1 The SpaceWire interface is a well established standard providing a layered protocol physical signal character exchange packet network and proven interface for space applications It is an asynchronous communication serial link b1 directional full duplex interface including flow control error detection and recovery in hardware hot plug ability and automatic reconnection after a link disconnection Space Wire is a serial link interface and performance of the interface depends on skew jitter and the implemented technology SoC Wire is a NoC approach in a complete on chip environment Therefore Space Wire interface has been modified to a parallel data interface The advantage of this approach is that significantly higher data rates can be achieved as compared to the SpaceWire standard Additionally a scalable data word width to support medium to very high data rates has been implemented On the other hand the advantageous features of the SpaceWire standard including flow control hot plug ability error detection and link re initialization are still fully support 3 Background The following sections describe the SoC Wire interface The chapter briefly describes the SoC Wire relevant sections from the SpaceWire standard and the differences For more detailed information please refer to 1 The SoC Wire character level exchange level packet level and network level is derived from the SpaceWire standard and refer
12. with an EOP marker EEP marker 1s exclusively send by the user to indicate an erroneous packet To this the target can react accordingly and reject the packet In summary the SpaceWire packet level is highly flexible and permits to implement a wide range of protocols 3 4 Network SoCWire network nodes can be either connected by links or connected by routing switches The network operates exclusively with the objects of the packet level All lower levels are completely masked from the network The network topology can be configured as e g tree cloud or cube The SoCWire Switch supports wormhole routing packets arriving at one port are routed immediately to the output port if the port is free which reduces buffer space and latency The SoC Wire network level supports the simple and effective header deletion technique to transfer packets across an arbitrary sized network When a packet is received at a routing switch the destination port is determined from the header The destination header 1s then deleted and the remaining packet content 1s transferred through the output port If a second identifier exists it can be used for any subsequent routing Therefore at each stage of the network a packet can be regarded as a packet comprising a single destination identifier header cargo and end of packet The SoCWire network level comprises patch dressing With path addressing a sequence of destination identifier within a packet is used to guide the packet a
13. 5 O Q 2 1 5 6 5 10 48 4 9 4 2 0 2 5 6 3 O 0 NNO O O ININ O O ee dE 036 16127 602 9636 16582 640 _ 60 _ 66 69 o O O G O1 O71 amp NI 00 gt Co r amp 11351 20163 7346 11951 21212 13405 23308 14418 25135 15282 2 349 16498 29680 17970 31628 18882 33230 19397 35201 20811 38166 O 40856 23556 42052 13391 24768 45530 14185 25593 46720 14851 95 23 05 961 10129 10661 11312 11847 12327 12885 0 4 9 1 4 6 00 N 6 0 4 1 5 8 4 32 10507 18156 680 39 5 34 1 12 8 33 8 134 533 42 6 37 9 13 8 35 6 132 036 LI J 1 LI 54 7 1 41 55 7 126 592 70 2 48 J di J N N 00 3 N Led Foe Led 19 EA N N x N
14. _en is necessary to move from the state ready into started The socw dis signal forces the state machine to move from run into ErrorReset Additional the signal active indicates the run state where link connection 1s established Time conditions for time dependent state transitions are triggered by watchdog timer which are adapted to the system clock period The watchdog clock cycles are calculated with watchdog hi _ 1 clk ty is the number of watchdog clock cycles and tis the clock period in ns The current state of the state machine is distributed to all other modules 4 1 2 Rx Fifo The rx fifo can be access from the host interface with the low active dat_nread signal The fill state of the fifo is indicated with the high active dat empty signal If dat empty is 0 data can be read from the fifo The dat_dout signal vector provides the user data It is 1 n bit width n is the data word width and the MSB is the Data Control Flag The fifo 1s currently realized with 16 Kbyte BlockRAM dp_ram The fifo depth is 1024 which is the default depth of the Virtex 4 architecture The fifo is cascadable to adapt it to data word width from 8 to 8192 bit This is automatically generated and the resource utilization of BlockRam increase with the data word width LI Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04 09 User Manual Pages ai 30 The fifo i
15. cross the network SoCWire User Manual Issue Date Page SoCWire Error Recovery Schemes Reference SoCWire Draft Rev 22 04 09 13 of 30 The SoC Wire error recovery scheme covers the exchange and network level In the exchange level the following errors can be detected e Disconnect error e Parity error e Escape error e Character sequence error invalid token at invalid time e Credit error The response to any of these errors 1s 1 Detect error 2 Disconnect link 3 Report error to network level 4 Attempt to reconnect the link if the link 1s still enabled In the network level the following errors can be detected e Link error exchange level error e EEP received e Invalid destination address If a link error is detected the network level response as follows 1 Error is received by the network level 2 Current received packet is terminated with EEP 3 Ifthe error occurred in destination or source node the error shall reported to the host system 4 SoCWire CODEC The SoCWire CODEC connects a node or host system to a SoC Wire network SoC Wire CODECS are the atomic components of the network and are source and destination of a SoC Wire link tx datawidth 1 0 tx_valid dat_full dat_nwrite dat_din datawidth 0 clk rst socw_en socw_dis active rx datawidth 1 0 rx_valid Figure 8 SoCWire CODEC dat_empty dat_nread
16. d with the fct empty signal The rx fifo signalize its internal fifo fill state to the receiver If the fifo is full and still a N Char is received a character error is triggered The receiver is fully pipelined to provide at every clock cycle a full SoCWire data word 4 1 4 Tx Fifo The transmit fifo can be access with the low active dat write signal As soon as the fifo is full the dat_full signal is 1 FCTs received by the receiver are forwarded with the fct nwrite signal to the transmitter The fct nwrite increments the credit counter If the credit counter receives 7 FCTs the fct full signal is set For a bi directional full duplex transfer the FCTs have to be included in the data transfer The tx fifo does not require a dedicated ram because it just has to store 1 data word 4 1 5 Tx The tx module codes and transfers the user data and operates the handshake mechanisms Additional it calculates the parity bit in a 2 stage pipeline The tx valid signal indicates the validity of the data and is connect with rx valid of the receiver Figure 9 shows the state diagram Reference SoCWire SoC Wire Draft 1 Issue Rev Date 22 04 09 User Manual Page e of 30 rst 0 AND state Started OR Connecting OR Run rst 1 OR state ErrorReset OR ErrorWait OR Ready Figure 9 Control of tx_valid In idle mode the transmitter sets all bits except the parity bit to
17. e 26 receive fifo SoCWire CODEC schematic Rev of 30 VI 7e Reference SoCWire SoC Ire Issue Draft Rev 1 Date 22 04 09 User Manual Page 27 of 30 SoCWire Codec resource utilization synthesize report Xilinx Virtex 4 LX60 10 T LuxeoTotalnumberof SoCWire CODEC SLICEs 26624 53248 Resource Utilization 53248 BRAMs 160 Frequency Data Rate L 1 401 220 510 e Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04 09 User Manual Page os a 30 SoCWire Switch resource utilization synthesize report Xilinx Virtex 4 LX60 10 Data Word Width 8 Bit LX 60 Total number of SoCWire Switch Resource SLICEs 26624 53248 Utilization 53248 BRAMs 160 Core CLK BRAM Frequency BRAM Slice Lut FF MHz HE 855 i DE 410 778 699 5 1194 2250 855 6 1481 2784 1062 Lut 778 489 3 4 2250 2784 ME G 3523 6 6 4 5324 9 6058 6 T 8 9 9 660 4 39 37 12 25 188 237 3 1 8 2204 4139 1512 8 83 78 9 2825 5324 1756 _ 10 0 10 3225 6058 2014 _ 11 4 12 6 14 7 16 4 8 1 1 1 9 1 1 5 5 9 5 4 17 7 4 2 0 9 5 4 _ 18 4 20 3 6 T 22 2 24 5 9 26 8 29 4 0 1 2 3 5 6 1 20 1 8 9 1 0 1 2 12 33 2 35 5 1 16 3 l 5 46 1 e Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04
18. e number of ports Switch switch Top Level module Entrance entrance Analyze Incoming packets The module verifies the validation of the header processes header deletion and passes the packet to the matrix Matrix matrix Matrix crossbar manages the cargo transfer to the destination port by cell modules Cell cell Each cell module represents an inter connection between two ports 5 1 1 Entrance The entrance module analyzes the header of incoming packets If the packet destination port is valid the module deletes the header and forwards the cargo to the matrix with the destination port information For each port a entrance module is instantiated therefore a 4 port switch has 4 entrance modules This is necessary to provide an independent communication of each port Additional the entrance module markes a port as full 1f a cargo is transferred The entrance module itself does not receive information if the port is busy The requested port of the current packet is therefore transferred to the matrix with the wanted signal This signal tests autonomously if the connection to the destination port can be established This information 1s provided to the entrance module with the nwrite signal If it 1s 0 the transfer can be started If the entrance receives an EOP or EPP the header deletion is enabled and destination address is determined for the incoming next packet 5 1 2 Matrix The matrix crossbar manages
19. eference SoCWire SoC ire Issue Draft Rev 1 Date 22 04 09 User Manual Bada e 30 4 4 Write Figure 10 shows a SoCWire CODEC write transfer completed with an EOP clk dat full dat_nwrite dat_din Figure 10 SoCWire CODEC write cycle 8 bit data word width 4 5 Read Figure 11 shows a SOCWire CODEC read transfer completed with an EOP clk dat_empty dat_nread dat_dout 8 7 6 5 4 3 2 1 0 Figure 11 SoCWire CODEC read cycle 8 bit data word width LI Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04 09 User Manual a AS i 30 4 6 Data Rates For bi directional full duplex data transfer the FCTs need to be included in the transfer After initialization phase every eight data characters are followed by one FCT The maximum data rate for a bi directional full duplex transfer can therefore be calculated to DRate y core uua X DWord Width x lt S For a unidirectional data transfer the FCTs are processed in parallel and the maximum data rate can be calculated to M DRate E ey X DWord Width Figure 12 shows data rates for different data word width unidirectional and bi directional full duplex data transfer at a core clock frequency of 200 MHz 30 28 26 24 22 20 18 16 14 12 10 Gbit s O N A 0 8 16 32 64 128 Data Word Width Bit Figure 12 SoCWire CODEC data rates at core clock frequency 200 MHz
20. ignal description Signal cb I emma O ETT ETE RETE R _ _ Hon Input i Clock SoCWire Switch receive link 1 0 nports 1 DOWNTO 0 When active current rx link data is valid oai Output SoCWire Switch transmit link MN nports 1 EA 0 Output When active current tx link data is valid active Output When active link is connected and High running transmission can start 9 e Reference SoCWire SoC Wire Draft 1 Issue Rev Date 22 04 09 User Manual TU Braunschweig Page 23 of 30 5 4 Switch example clk dat_nread 1111 0000 dat_nwrite 1111 11100 10000 10011 1111 dat_empty 1111 0110 0010 1011 0111 1111 dat_full 0000 Atx 02F 000 005 008 00C 004 02F Arx O2F 1004 008 00C 004 f02F dat_dout Btx 02F JO0C 025 029 02D 00B O2F Brx 02F B dat_din 000 003 009 004 00B 100 000 B dat_dout 000 Ctx 02F OOC 085 089 08D 0OB_x02F Crx 02F 104 109 10D IOOB 02F C dat_din 000 1003 021 022 023 100 000 C dat_dout 000 1041 042 043 100 Dtx 02F 008 1104 109 110D 00B 102F 003 02E YOZF Dr 02F 1024 1029 02D 00B 02F 084 089 108D 00B 102F D dat_din 000 002 041 042 043 100 000 D dat_dout 000 009 00A 00B 100 3021 022 023 100 Figure 16 SoCWire Switch example with 4 nodes LI Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04
21. pporting many data word widths 8 128bit and 2 to 32 ports It 1s a totally symmetrical input and output interface with direct port addressing including header deletion The SoCWire Switch has been implemented and tested in a Xilinx Virtex 4 LX60 10 Figure 17 shows the occupied area and maximum clock frequency for an 8 bit data word width switch For detailed resource utilization and timing see Appendix A 70 220 65 60 200 55 DS N 30 CoreClkF I gt gt D 180 a5 i O 5 40 C S g N 35 160 O 30 E 2 25 140 O 20 X 15 3 i 120 5 0 100 Number of Ports Figure 17 SoCWire Switch 8 bit data word width synthesis report W Ts Reference SoCWire Y SoC ire Draft Rev EA Issue Date 22 04 09 uu User Manual TU Braunschweig Page 25 of 30 6 Reference 1 ECSS Space Engineering SpaceWire Links nodes routers and networks ESA ESTEC Noordwijk Netherlands January 2003 ECSS E 50 12A 2 B Osterloh H Michalik and B Fiethe SoC Wire A Robust and Fault Tolerant Network on Chip Approach for a Dynamic Reconfigurable System on Chip in FPGAs in Architecture of Computing Systems ARCS 2009 vol 5455 Delft Netherlands Springer Berlin Heidelberg 2009 pp 50 59 7 Appendix d D a gt sl SoCWire User Manual state machine receiver Reference SoCWire Issue Draft Date 22 04 09 Pag
22. s 17 4 4 WISIN de one Pn Oe TROT ae Oe 18 4 5 REIU ACC SS Sissi vee a dba 18 4 6 DAS AA iii 19 ET Resoureeutlizanoni Nd NE 20 5 OV Ms DO il ir li 20 5 1 SUC urca DI 5 1 1 Entran usd 21 35 12 IN LN BPR 21 Did CONSULTORI PHON ERR 22 5 3 SUNaANUSSCE PHON Liar ciclici 22 5 4 SE EOR OS em e E O O OO O 23 5 5 bikini 24 56 ResoUree Utihzation and eo 24 O Li AAA RE EI iii iii 25 JE APPO i i 26 3 SoCWire User Manual TU Braunschweig 1 General Overview Reference SoCWire Issue Draft Rev 1 Date 22 04 09 Page 5 Of 30 SoCWire is a Network on Chip NoC approach based on the ESA SpaceWire interface standard 1 to support dynamic reconfigurable System on Chip SoC SoCWire has been developed to provide a robust communication architecture for the harsh space environment and to support dynamic partial reconfiguration in future space applications SoCWire provides High speed data rate Scalable data word width 8 8192 Configurable Switch with 2 to 32 ports Reconfigurable point to point communication Hot plug ability to support dynamic reconfigurable modules Link error detection and recovery in hardware Easy implementation in dynamic partial reconfigurable systems For more background information about the SoCWire motivation see 2 Figure 1 SoCWire architecture network example VI Te Reference SoCWire SoC ire Draft Rev 1 Issue Date 22 04 09 User Manual o 4 7 30
23. s currently implemented for the Xilinx Virtex 4 architecture but it can be simply implemented in any architecture with the replacement of the BlockRam primitive in the dp_ram module Additonal the rx fifo controls the FCTs transfer This is done by the fct empty signal With fct nread the transmitter can indicate that its credit counter is full and no more FCTs have to be sent 4 1 3 Rx The receiver module receives the parallel data of the link Since SoCWire is a synchronous implementation it requires a additional signal to indicate the validation of the data This is implemented with the high active rx_valid signal The receiver is responsible to detect link errors The errors are pass to the state machine with the signals err_par parity error err_esc escape error err_dsc disconnection error err nchar character error and err_fct fct error A disconnection error is triggered if the link is inactive for disconnect detection generic in the vhdl model after the first link connection was established Inactive 1s related to the rx_valid low period This state is implemented with a counter dsc_count The clock cycles can be calculated with disconnect _ detection watchdog 1 l oik The receiver communicates with the rx _ fifo to transfer data with the dat dout signal A valid received N Char is displayed with the dat empty signal Additional valid received FCTs are displaye
24. s to it In Contrast to SpaceWire the SoC Wire architecture does not require the physical layer Furthermore Time Code characters and logical addressing has not been implemented to safe resources 3 1 Character Level The character level describes data and control characters used to manage the flow of data across the link It follows the SpaceWire standard without Time Code distribution SpaceWire does not provide a global time base nodes are synchronized through a system time distribution with Time Codes which have a high priority in the network Time Code characters are not necessarily required because a global time base distribution can be easily implemented in a complete on chip environment through dedicated signals which saves resources 3 1 1 Data Character A data character is formed by 1 parity bit 1 data control flag and 8 data bits to be transmitted Data Control Flag Pl ol DE DE DE DE DE DE DE D 0 1 2 3 4 5 6 7 Parity Bit LSB MSB Figure 2 Data Character The data control flag indicates if the current character is a data 0 or control character 1 e Reference SoCWire SoC Wire Draft 1 Issue Rev Date 22 04 09 User Manual o ve 7 30 3 1 2 Control Character Control characters 4 bit length are used for flow control Flow Control Token FCT End of Packet EOP Error End of Packet EEP and an Escape Character ESC which 1s used to form the higher level control
25. t data interface can be source or destination for the transferred data To distinguish between user data and packet marker EOP and EEP the following coding 1s used Data Control ARAS DAA Data bits MSB LSB XXXXXXXX a amen ion Table 1 Coding of EOP and EEP for 8 bit data word width The data control flag is the MSB of the dat din datawidth or dat dout datawidth vector All lower bits shall be set to 0 s EOP or 0 s 1 for the LSB EEP 3 2 Exchange Level The exchange level manages the connection and flow across the link The exchange level 1s separated into two types Link Characters L Char and Normal Characters N Char N Char comprises data character EOP and EEP and are passed to the network level L Char are used in the exchange level and are not passed to the network level They comprise FCT and ESC characters and are responsible for link connection and flow control 3 2 1 Flow Control To avoid buffer overflows and therefore data loss a credit based flow control is implemented After link connection is established FCTs are transmitted over the link Each FCT signify that one end of the link is ready to receive 8 N Chars Wi Reference SoCWire SoC ire Draft Rev 1 Issue Date 22 04 09 User Manual ua e 30 3 2 2 State Machine The SoCWire CODEC is based on a finite state machine derived from the SpaceWire standard as depicted in Figure 5 Reset after 6 4 us RxErr
26. the cargo transfer to the destination port by cell modules Each cell module represents an inter connection between two ports and therefore a switch with 4 ports comprises 16 cells or with 32 ports 1024 cells To provide parallel data transfer between different ports the matrix conceives data transfers of all ports as bit vector Therefore the bit width of the matrix is datawordwidth 1 data control flag number of ports As depicted in Figure 15 e Reference SoCWire SoCWire Draft 1 Issue Rev Date 22 04 09 User Manual TU eE Page 22 of 30 Y 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 port 3 port 2 port 1 port O ALA MP er ETA PO Figure 15 Matrix bit vector Data word width is in this case 8 bit and the switch comprises 4 ports The matrix can manipulate bits in this vector within 1 clock cycle to provide write access to ports To prevent the concurrent access from 2 ports writing to 1 port the round robin scheduling mechanism 1s implemented The access to ports is divided in time slots Each time slot represents write access of 1 port Therefore the maximum latency of the Switch is number of ports 1 for a 4 port Switch 3 clock cycles If 2 ports access 1 destination port one data transfer will be blocked until the first received packet is fully transmitted 5 2 Configuration options Es range datawidth datawordwidth 88192 8 5 3 S
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