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TE0320 Series User Manual

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1. JM5 FPGA y singal ball p TE in Vb2b 1 2 Vb2b in TE TE in Vb2b 3 4 Vb2b in TE 3 3V 1 VO 12C IO_L13P_1 Y22 SCL 5 6 MR in 3 3V 3 3V 1 VO 12C IO L13N_1 Y23 SDA T 8 9 10 VO IO_L22N_2 IO_L30N_2 SPI in 3 3V 2 DUAL DOUT AE15 DOUT 11 12 SPILD AB15 MOSICSI B DUAL 2 KSC VO IO_LO1N_2 lO_L34P_2 VO 33V 2 DUAL MO AD4 MO 13 14 INT_B AA15 INT B DUAL 2 3 3V VO lO_LO1P_2 3 3V 2 DUAL m AC M1 15 16 Vsup out TE VO lO_LO2P_2 lO_L52P_2 SPlout 3 3V 2 DUAL M2 YT M2 17 18 SPLQ AF24 DO DIN MISO DUAL 2 3 3V VO lO_LO7P_2 IO LO2N 2 SPlout 39V 2 DUAL RDWR B Y12 RDWR _B 19 20 SPL S AA7 CSO B DUAL 2 3 3V IO L52N_2 SPlout 21 22 SPL C AR24 CCLK DUAL 2 3 3V lO_L24N_2 VO 23 24 D4 AE12 D4 DUAL 2 3 3V IO_L24P 2 VO 25 26 D5 AF12 D5 DUAL 2 3 3V lO_L22N 2 VO 27 28 D6 AF10 DG DUAL 2 3 3V VO IO_L36N_2 33V 2 DUAL D1 AE18 D1 29 30 D D D D VO lO_L36P_2 OL 22P 2 VO 33V 2 DUAL D2 AF18 D2 31 32 D7 AE10 D7 DUAL 2 3 3V VO IO_L34N_2 Sn 2 DUAL D3 Y15 D3 33 34 J5 lIO20 AA18 IO_L47N 2 VO 2 3 3V IO _L27P_2 GCLKO J5 1001 35 36 J5 1021 AB18 lO L47P 2 VO 2 3 3V CN 37 38 J5 I022 AP3 IO L48N 2 VO 2 3 3V 2 O_L28F_2 J5 1002
2. Table 11 user LEDs signal details 6 7 Push Buttons S 3 4 TE0320 is provided with 2 user buttons A signal listed in Table 12 is set low logical 0 when a push button is pressed and vice versa default pui switch signal FPGA ball FPGA pin bank when input pressed S3 PBI U23 I0 L23P1 1 logical 1 logical 0 S4 PB2 R22 IO L25N_1 1 logicali logical O Table 12 user push buttons signal details S4 PB2 S3 PB1 Figure 31 push buttons PB1 and PB2 24 82 www trenz electronic de TE0320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 Warning on some boards PB1 and PB2 labels might be exchanged Please take Figure 31 as reference 6 8 Switches TE0320 is provided with the following slide switches 51 4 x DIP slide switches system 52 1 x slide switch system 55 8 x DIP slide switches user 6 8 1 DIP Slide Switches S1 A D 25 82 TEO320 is provided with 4 system DIP slide switches as shown in Figure 32 S1A S1B S1C SID Figure 32 DIP slide switches S1 A D Please note the 4 switch labels are on one side and the lt ON gt label is on the opposite side DIP slide switches S1 A D condition the value of some system signals as described in Table 13 switch S1 label signal name the USB microcontroller the USB microcontroller S1A 1 EEPROM serial data CANNOT read write the can read write the serial EEPROM serial EEPRO
3. Configuration Pin Done Float Table 33 Xilinx ISE Project Navigator settings for having DONE actively driving its line Consult ISE Help about the Process Properties of the Generate Programming File process in the Processes pane for additional information on these properties 56 82 www trenz electronic de TEO320 Series User Manual 11 Recommended Design Tools Settings UM TEO320 v2 08 22 February 2012 11 2 Unused IOB Pins All signals entering and exiting a Xilinx Spartan 3 generation FPGA must pass through the I O resources known as I O blocks or IOBs Users can specify the configuration for any unused IOB pins This is the serial data outputs for all JTAG instruction and data registers This options are set graphically in Xilinx ISE Software Project Navigator by selecting the following Generate Programming File gt Process Properties gt Configuration Options gt Unused IOB Pins Select an option from the drop down list a Pull Down Default All unused I O pins and input only pins have a pull down resistor to GND b Pull Up All unused I O pins and input only pins have a pull up resistor to the VCCO supply for its associated I O bank c Float also Pullnone All unused l O pins and input only pins are left floating Hi Z high impedance three state Use external pull up or pulldown resistors or logic to apply a valid signal level 11 3 CCLK Frequency In SPI Flash mode the FPGA s interna
4. 2 03 2010 01 20 FDR Added legal notices 2 04 2010 05 17 FDR Added reference design summaries Added SPI pin out summary Improved assembly options overview 2 05 2010 05 18 FDR Added indirect SPI configuration mode 2 06 2010 05 19 FDR Improved JM5 pin out configuration and power management pins 2 08 2012 02 22 FDR Improved push buttons description Corrected slide switch positions 2 08 2011 10 03 AIK Modified block diagram Added power supply diagram Little fixes 2 09 2011 10 05 AIK Modified B2B section Changed DDR and SPI specification 2 10 2011 11 30 AIK Clarification of SPI Flash options 2 11 2011 12 01 AIK Board revision and assembly options chapter 2 12 2012 02 16 AIK Module options chapter 2 13 2012 02 22 AIK Dimensions image and description modifications 2 14 2012 02 22 AIK Updated S1 switch description 82 82 www trenz electronic de TEO320 Series User Manual
5. configuration mode is irrelevant for this step S1D OFF master reset disabled switch S1 label signal name SIA 1 EEPROM serial data OFF S1B 2 M2 x SIC 3 Mi x SID 4 MR master reset OFF Table 25 S1 Settings for installing generic USB device driver Figure 45 S1 Settings for installing generic USB device driver Connect the TE0320 to a USB port on your computer using a USB cable Follow the Found New Hardware wizard to install the driver if necessary as shown in the following example You need to look for the step1_factory CyUSB inf device driver information file in the TE0320 software package 39 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 Assistent f r das Suchen neuer Hardware Assistent f r das Suchen neuer Hardware Willkommen Wahlen Ste die Such und Installationsoptionen Mit diesem Assistenten konnen Sie Software f r de folgende Hardwarekomponente installieren Digilent USB Device Diese Quellen nach dem zutreffendsten Treiber durchsuchen versenden Sie die Kontrollk stchen um de Standardsuche zu enveitern oder einzuschr nken Lokale Pfade und Wechselmedien sind in der Standardsuche mit einbegriffen Der zutreffendste Treiber wird installiert A Falls die Hardwarekomponente mit einer CD 71 oder Diskette geliefert wurde legen Sie diese Wechselmedien durchsuchen Diskette CD jetzt ein
6. 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 6 3 2 JTAG lines at B2B connector JM4 6 4 I2C bus 20 82 JTAG signal lines are also available at B2B connector JM4 See Table 40 for additional information on these signals TEO320 has a flexible I2C bus on board as outlined in Figure 28 USB MCU EZ USB FX2LP I2C CMOS serial EEPROM B2B JM5 Figure 28 I2C bus topology The I2C signals on the TE0320 are listed and described in Table 5 name definition description SDA serial data This is a bidirectional pin used to transfer addresses and data into and out of a device SCL serial clock This signal is used to synchronize the data transfer to and from a device Table 5 I2C signals summary The I2C bus is typically used by the USB microcontroller to write USB firmware to the serial EEPROM In this case the 12C port of the FPGA must be set in slave mode SCL pin as input the device attached to the I2C port of B2B JM5 connector must be set to slave mode The USB microcontroller can operate just in I2C master mode default operation If the user wants to set another device attached to the 12C bus as master device the USB microcontroller shall three state Z high impedance its SCL and SDA pins lf the FPGA is set to I2C master mode it can write to or read from serial EEPROM always slave mode and B2B connector JM5 attached device set to slave mode lf the device attached to
7. Aw trenz TE0320 Series User Manual J electronic Xilinx Spartan 3A DSP Industrial Grade FPGA Micromodule Bud UM TE0320 v2 08 22 February 2012 Trenz Electronic GmbH Overview Rapid prototyping The TE0320 is an industrial grade FPGA Reconfigurable computing micromodule integrating a leading edge Xilinx System on Chip SoC development Spartan 3A DSP FPGA a USB 2 0 microcontroller 32 bit wide 128 MByte DDR RAM 4 MByte Flash memory for configuration and operation and powerful switch mode power supplies for all on board voltages A large number of configurable I Os is provided via robust board to board B2B connectors All this on a tiny footprint smaller than a credit card at the most competitive price Hardware and software development environment as well as reference designs are available at www trenz electronic de Sample Applications Cryptographic hardware module Digital signal processing Embedded educational platform Embedded industrial OEM platform Embedded system design Emulation platforms FPGA graphics Image processing P intellectual property cores Low power design Parallel processing SES AAAAAAAAAAAAAAAAARA AAAAAAAARAAAAAAAAAA o aa min E JE itd m a gt ei E HAHN HU UN NU UU uu H IHH Hii 0 ke po RN Wa ae Ss Read D d d ma bn z m eh a er P 2 at P CC gt um y a a ap ote Ree oo mg e 4 4 E 5555
8. Bitstream 1 Start Address 675840 Add Non Configuration Data Files Yes Number of Data File Auto Select PROM Description The PROM File Formatter will guide you through the steps to format bitstream BIT files into a PROM file that is compatible with Xilinx and third party PROM programmers The programmed PROM device can then be used to configure the target FPGA Additional capabilities of the PROM File Formatter include Select step 2 add storage device s auto select PROMof the middle panel and press the right green arrow E PROM File Formatter Step 1 Select Storage Target Step 2 Add Storage Device s Step 3 Enter Data Storage Device Type Xilinx Flash PROM Non Volatile FPGA Spartan3an p SPI Flash Add Storage Device Remove Storage Device Seele Untied Configure Single FPGA Output File Configure MultiBoot FPGA Location BPI Flash Configure Single FPGA Configure MultiBoot FPGA FlashPROM File Property Configure from Paralleled PROMs File Format Generic Parallel PROM PROM Family Platform Flash 1 General File Detail value s 5 gt Checksum Fill Device bits IxcFD1s 1 m Value FF Cain Enable Revisioning Number Of Revisions Enable Compression Description In this step you will enter information to assist in setting up and generating a PROM file for the targeted storage dev
9. Folgende Quelle ebenfalls durchsuchen Durchsuchen Wie mochten Sie vorgehen Software automatisch installieren empfohlen Software von einer Liste oder bestimmten Quelle Verwenden Sie diese Option um einen Ger tetreiber aus einer Liste zu w hlen Es wird installieren fur fortgeschrittene Benutzer nicht garantiert dass der von Ihnen gew hlte Treiber der Hardware am besten entspricht Klicken Ste auf Weiter um den Worgang fortzusetzen ZurLick I weiter gt Abbrechen Assistent f r das Suchen neuer Hardware Datei suchen ey Suchen in O driver A DEWELISE inf a O LUSB inf Wahlen Sie den Hersteller und das Modell der Hardwarekomponente und klicken Sie auf er E d E SO S SS DO Scripts Wetter Klicken Sie auf Datentr ger wenn Sie uber einen Datentr ger verf gen der der erforderlichen Treiber enthalt CH Inc Wahlen Sie den fur diese Hardware zu installierenden Geratetreiber Kompatible Hardware anzeigen Modell Cypress Genenc USB Device Dateiname CyUSB inf Dateityp Setup Informatianen inf Abbrechen Dieser Treiber ist nicht digital signiert l Datentr ger Warum ist Treibersignierung wichtig Installation von Datentr ger Assistent f r das Suchen neuer Hardware Fi Legen Sie den Installationsdatentrager des Herstellers ein und stellen Sie sicher dass weiter unten das nchtige Wahlen Sie den fur diese Hardware zu installieren
10. 22 February 2012 Initializing temperature to 85 000 Celsius default Range 0 000 to 85 000 Celsius Initializing voltage to 1 140 Volts default Range 1 140 to 1 260 Volts Device speed data version PRODUCTION 1 33 2010 02 13 Design Summary Report Number of External IOBs 119 cue of 519 22 Number of External Input IOBs 30 Number of External Input IBUFs 30 Number of LOCed External Input IBUFs 30 out of 30 100 Number of External Output IOBs 43 Number of External Output DIFFMs 2 Number of LOCed External Output DIFFMs 2 out of 2 100 Number of External Output DIFFSs 2 Number of LOCed External Output DIFFSs 2 out of 2 100 Number of External Output IOBs 39 Number of LOCed External Output IOBs 39 out of 39 100 Number of External Bidir IOBs 46 Number of External Bidir IOBs 46 Number of LOCed External Bidir IOBs 46 out of 46 100 Number of BSCANs 1 out of 1 100 Number of BUFGMUXs 5 out of 24 20 Number of DCMs 1 out of 8 12 Number of DSP48As 3 out of 84 Number of RAMB16BWERS 30 out of 84 355 Number of Slices 7304 out of 16640 43 Number of SLICEMs 1156 out of 8320 13 Number of LOCed Slices 125 out of 7304 1 Number of LOCed SLICEMs 83 put of 1156 7 Overall effort level ol High Router effort level rl High 59 82 www trenz electronic de TEO320 Series User Manual 12 Reference Design Summaries ISE 11 5 UM TEO320 v2 08 22 February 2012 12 2 Reference Design Summary for Xilinx Spartan 3A DSP 340
11. S1 0 A 3 3V SES 3 0 Vsup gt DC DC module JM5 1 0 A 2 5V 25 3 0 Vsup gt DC DC DDR SDRAM JM5 lt 1 0 A 1 2V 1 2 3 0 Vsup gt DC DC VCCINT JM5 lt 1 0 A 2 5 0 3 3 3V gt LDO VCCAUX VCCAUX JM4 lt 1 0 A 33 lt 3 0 3 3V 25 lt 3 0 2 5V JM4 lt 1 0 A VCCCIOO 3 3 lt 3 0 3 3V VCCO JM4 lt 1 0 A bank 0 seo 2 0 JM4 JM4 2 pin x 1 0 A pin 30 44 30 44 Table 1 On board power rails summary 5 4 Power Supervision 5 4 1 Power on Reset During power on the RESET line is first asserted Thereafter the supply voltage supervisor monitors the power supply rail 3 3V and keeps the RESET line active low as long as the rail remains below the threshold voltage 2 93 V An internal timer delays the return of the RESET line to the inactive state high to ensure proper system reset The delay time of 200 ms starts after the rail has risen above the threshold voltage Figure 13 Power on reset with fixed delay time of 200 ms After this delay the RESET line is reset high and the FPGA configuration can 12 82 www trenz electronic de TEO320 Series User Manual 5 Power Supply UM TE0320 v2 08 22 February 2012 start When the rail voltage drops below the threshold voltage the RESET line becomes active low again Figure 14 Reset assertion on power drop with fixed delay time of 200 ms 5 4 2 Power Fail TEO320 integrates a power fail comparator whi
12. video archive TrenzElectronic s Channel at YouTube www trenz electronic de TEO320 Series User Manual 17 Related Materials and References UM TEO320 v2 08 22 February 2012 17 Related Materials and References The following documents provide supplementary information useful with this user manual 17 1 Data Sheets Xilinx DS485 Digital Clock Manager DCM Module Data Sheet This is the data sheet for the Digital Clock Manager DCM Module core www xilinx com support documentation ip_documentation dem_module pdf Xilinx DS610 Spartan 3A DSP FPGA Family Complete Data Sheet The Spartan 3A DSP family of Field Programmable Gate Arrays FPGAs solves the design challenges in most high volume cost sensitive high performance DSP applications www xilinx com support documentation data_sheets ds61 0 pdf 17 2 User Guides Xilinx UG331 Spartan 3 Generation FPGA User Guide Functional description of the Spartan 3 generation FPGA architecture and how to use it Includes the Spartan 3A Spartan 3AN Spartan 3A DSP Spartan 3E and Spartan 3 platforms www xilinx com support documentation user_guides ug331 pdf Xilinx UG332 Spartan 3 Generation Configuration User Guide Describes the configuration features of the Spartan 3 Generation FPGAs Includes the Spartan 3A Spartan 3AN Spartan 3A DSP Spartan 3E and Spartan 3 FPGA families www xilinx com support documentation user_guides ug332 pdf EZ USB Technical Referen
13. 1 x 32 bit data bus DDR SDRAM Microchip Technology 24LC1281 ST 128 kbit DC CMOS serial EEPROM 3 x STMicroelectronics ST1S10 3 A 900 kHz monolithic synchronous step down regulator 3 A for each power rail 1 2 V 2 5 V 3 3 V Texas Instruments TPS3705 33DGN processor supervisory circuits with power fail and watchdog 100 MHz oscillator system user 24 MHz oscillator system user 2 x CviLux CBC1 80 2 M110 2P 1 27 mm 50 mil 050 pitch 80 pin double row socket female header board to board B2B connectors with key and pegs 109 FPGA IO Pins routed to the B2B connector 6 pin JTAG header 1 x USB mini B receptacle device 1 x LED system 4 x LED user 2 x push button user 4 x DIP switches system 1 x slide switch system 8 x DIP switch user 1 Default module configuration contain 32 MBit Flash 6 82 www trenz electronic de TEO320 Series User Manual A Board Dimensions UM TEO320 v2 08 22 February 2012 4 Board Dimensions 48 00mm 7 82 18 40mm TEO320 measures 68 0 x 48 0 mm 10 50mm 3 00mm Top View Figure 4 dimensional drawing TEO320 can reach a minimum vertical height of about 6 mm if push buttons and USB receptacle are not assembled Two mated standard TEO320 connectors have a nominal mated height of 6 0 mm Processing conditions and solder paste thickness affects such height resulting in an effective mating heights of 7 0 mm Therefore the
14. 46 JM4 IO50 H9 lO_L47N_0 VO 0 VecciO0 VccclOO 0 VO IO L30ON_ O C12 JM4 IO20 47 48 JNA I051 G9 lO_L47P_0 VO 0 VecciO0 VccclOO 0 VO IO L30PO D13 JM4 I021 49 50 JM4 I052 E7 lO_L48N_0 VO 0 VecciO0 E D D D 51 52 JM4 1053 F7 lO_L48P_0 VO 0 VccclOo VccclOO 0 VO IO L33N O B10 JM4 I022 53 54 JM4 1054 B3 lO_L51N_0 VO 0 VccclOO VccclOO 0 VO IO L33P 0 A10 JM4 I023 55 56 JM4 IO55 A3 lO_L51P_0 VO 0 Vcccloo VccclO0 0 VO IO LAN O D10 JM4 1024 57 58 GND OGND GND GND VccclOO 0 VO lO_L34P_0 C10 JM4 025 59 60 JM4 lIO56 C23 IO LOGN O VO 0 Vcccloo VccclOO 0 VO IO_L35N_O H12 JM4 IO26 oi 62 JM4 1057 D23 IO_LO6P_0 VO 0 VecciO0 VccclOO 0 VO O_L35P_O G12 JM4 I027 63 64 JM4 IO58 A22 IO LO7N_O VO 0 VecciO0 65 66 JM4 I059 B23 IO LO7P0 VO 0 VccclO0 VccclOO 0 VO lO_L36N_0 B9 JM4 I028 67 68 JM4 lIO60 G17 IO_LO8N_0 VO 0 Vcccloo Vcccloo 0 VO lO_L36P_0 A9 JM4 I029 69 70 JM4 1061 H17 IO_LO8P_O VO 0 VecciO0 Vcccloo 0 VO lO_L37N_0 D9 JM4 1030 71 72 VccAux out VccAux VccAux VccclOO 0 VO lO_L37P_0 E10 JM4 I031 73 VccAux VccAux VccclO0 0 VO lO_L38N_0 B8 JM4 I032 75 VccAux VccAux VccclO0 0 VO lO_L38P_0 A8 JM4 I033 77 VccAux VccAux GND OND CIND GND 79 VccAux VccAux Table 40 pin out of B2B connector JM4 www trenz electronic de 75 82 TEO320 Series User Manual 18 B2B Connectors Pin Descriptions 18 3 2 JM5 Pin Out UM TEO320 v2 08 22 February 2012
15. He PIFO CS 0x04 EPA PIFO Cs 0x04 BEP6 FIFO CS 0 04 EPS FIFO Cs 0 04 BEP I TO OOO BPA FIFO BCH 0x00 EP6 FIFO BCH 0x00 EPS FIFO BCH 0x00 TEO320 DLL Example 1 0 Oh WO J On U GA N Pp www trenz electronic de Get number of modules Connect module No 0 Connect module No 1 Disconnect Get FX2 status Get FX2 version Get FPGA firmware version Get FX2 FIFO Status Reset FX2 FIFO Status Write high speed data FPGA RX Read high speed data FPGA TX Exit TEO320 Series User Manual 13 Verification Resetting all FIFOs TEO320 DLL Example 1 0 Get number of modules Connect module No 0 Connect module No 1 Disconnect Get FX2 status Get FX2 version Get FPGA firmware version Get FX2 FIFO Status Reset FX2 FIFO Status Write high speed data Read high speed data Exit Resetting all FIFOs host gt memory data verification PASSED Transferred 120000 kB in 4 048 s 282953 MB s FPGA RX FPGA TX OR g vw OO M0 LU Gs GA b i EH TEO320 DLL Example 1 0 1 Get number of modules 2 Connect module No 0 3 Connect module No 1 4 Disconnect 5 Get FX2 status 63 82 www trenz electronic de UM TEO320 v2 08 22 February 2012 6 Get FX2 version 7 Get FPGA firmware version 8 Get FX2 FIFO Status 9 Reset FX2 FIFO Status w Write high speed data FPGA RX r Read high s
16. L20N 2 44 Table 43 trace length of signal pins of B2B connector JM5 www trenz electronic de TEO320 Series User Manual 19 Glossary of Abbreviations and Acronyms UM TE0320 v2 08 22 February 2012 19 Glossary of Abbreviations and Acronyms A WARNING notice denotes a hazard It calls attention to an operating procedure practice or the like that if not correctly performed or adhered to could result in damage to the product or loss of important data Do not proceed beyond aWARNING notice until the indicated conditions are fully understood and met A CAUTION notice denotes a risk It calls attention to an operating procedure practice or the like that if not correctly performed or adhered to could result in a fault undesired condition that can lead to an error Do not proceed beyond a CAUTION notice until the indicated conditions are fully understood and met API application programming interface B2B board to board DSP digital signal processing digital signal processor EDK Embedded Development Kit FUT Firmware Upgrade Tool FWU Firmware Upgrade file IOB input output blocks UO blocks IP intellectual property ISP In System Programmability PB push button SDK Software Development Kit TE Trenz Electronic XPS Xilinx Platform Studio 80 82 www trenz electronic de TEO320 Series User Manual 20 Legal Notices UM TE0320 v2 08 22 February 2012 20 Legal Notices 20 1 Document Warranty The
17. Pins 30 and 44 of JM4 are power supply outputs in this case c if resistor R131 is populated and R132 is not populated VCCCIOO power rail is set to power rail 3 3V nominal voltage 3 3 V This is the default HUY ae Figure 12 assembly option for VCCCIOO 3 3 V bottom view Pins 30 and 44 of JM4 are power supply outputs in this case Assembly option where both R131 and R132 are populated is not allowed 1 2 V 2 5 V and 3 3 V voltage rails are provided by corresponding step down regulator DC DC converters each one capable of providing up to 3 A of output current These three regulators are synchronized to switch with 120 phase lag to improve EMC and to reduce input ripple The synchronization circuit can be omitted in cost sensitive applications please contact Trenz Electronic 11 82 www trenz electronic de TEO320 Series User Manual 5 Power Supply UM TE0320 v2 08 22 February 2012 Power supply inputs and outputs are made available at B2B connectors JM4 and JM5 for user applications Each pin of B2B connectors JM4 and JM5 is capable of a maximum current of 1 0 A nominal power rail maximum power system user voltage name V current A source supply supply Vb2b 4 0 to 7 0 a JM5 module l l 4 pin x 1 0 Han Vusb 5 0 0 5 J1 module lt 0 5 Vusb 3 x DC DC Vsup 4 0 to 7 0 DC DC sync JM5 lt 1 0 A S Vb2b power fail JM4
18. driven by the FPGA and made them available to the EZ USB FX2LP USB microcontroller allow the EZ USB FX2LP USB microcontroller to program the SPI Flash memory 10 2 5 4 FUT upgrade procedure Open USB Firmware Upgrade Tool double click step5 user USBFirmwareUpgradeTool exe USB Firmware Upgrade Tool Device USE Device Version 4 1 nenne EI Upload Press the button corresponding to the Iw USB EEPROM Iw FPGA FLASH File name 53 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 Suchen in 3 Trenz Electronic de v E TE0320 00 fwu Zuletzt verwendete D Desktop Select a suitable wu firmware upload file Press the open button Eigene Dateien Arbeitsplatz Netzwerkumgeb Dateiname TE0320 00 fwu v ung Dateityp Fw Update Files fwu M Abbrechen _ Check the USB EEPROM box if you want the EP ENER td usb bin file compressed into the wu file to Device Jeu gt Version 4 1 be written into the large EEPROM of the EZ File name E Trenz Electronic de TE0320 00 Fwu Upload USB FX2LP USB microcontroller ee nen Check the FPGA FLASH box if you want the foga bin file compressed into the fwu file to be written into the SPI Flash memory Press the upload button USB Firmware Upgrade Tool Version 4 1 i The tool will first attempt to write the large A a EEPROM if the c
19. of SPI_ C This input signal is used to transfer data serially into the device It receives SPI_D serial data input instructions addresses and the data to be programmed Values are latched on the rising edge of SPI_ C This input signal provides the timing of the serial interface Instructions addresses or SPI_ C serial clock data present at SPI_D are latched on the rising edge of SPI_ C Data on SPI_Q changes after the falling edge of SPI_ C When this input signal is high the device is disabled and SPI_Q is at high impedance Z SPIS chip select When this input signal is low the device is enabled After power up a falling edge on SPI_ S is required prior to the start of any instruction to the Flash memory Table 7 SPI signals summary SPI signal pin out of the TEO320 is summarized in Table 8 name FPGA ball JM5 pin SPI_Q AF24 18 SPI_D AB15 12 SPI_ C AE24 22 SPI_ S AA7 20 Table 8 SPI pin out summary SPI pins on B2B connector JM5 cannot be used as GPIOs general purpose I Os The SPI bus can be used during configuration and operation in a plurality of ways as summarized respectively in Table 9 and Table 10 Any other usage of the SPI bus is neither supported nor recommended 6 5 1 SPI bus for configuration The SPI bus is used for configuration in two ways by default d EZ USB Flash the USB microcontroller master writes the PROM file contai
20. set low logical 0 when a slide switch is set to lt ON gt and vice versa 6 9 Voltage Reference VREFO The user can freely set voltage VREFO through pin 37 of B2B connector JM4 VREFO is the reference voltage for setting the input switching threshold for certain I O standards of FPGA bank 0 For more information on reference voltages please consult Xilinx DS610 Spartan 3A DSP FPGA Family Complete Data Sheet Recommended operating voltage for VREFO is 0 75 to 1 5 V Absolute maximum voltage range for VREFO is 0 5 to VCCCIO 0 5 V 29 82 www trenz electronic de TEO320 Series User Manual 7 Timing UM TE0320 v2 08 22 February 2012 7 Timing 7 1 Main Clock Oscillator The module has a main SMD clock oscillator providing a clock source for the FPGA as detailed in Table 3 signal FPGA pin FPGA ball FPGA bank IO_L27N 2 MAINCLK GCLKI AA14 2 Table 16 Main clock signal details Standard frequency is 100 MHz Should you wish or need another main clock oscillator frequency please contact Trenz Electronic The lower the main clock frequency the lower the module power consumption Moreover as the main clock is preferably used as DDR SDRAM clock a lower clock frequency makes easier for the development tools to meet the timing requirements particularly for DDR SDRAM 7 2 24 MHz Clock Oscillator The module has a 24 MHz SMD clock oscillator providing a clock source for both the EZ USB FX2LP USB microcon
21. the 12C port of B2B JM5 connector is set to master mode it can write to or read from serial EEPROM always slave mode and FPGA DC port set to slave mode Possible I2C operation modes are summarized in Table 6 www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TEO320 v2 08 22 February 2012 FPGA core EZ USB FX2LP SDA 1 0 B2B JM5 serial EEPROM slave default master SCL slave slave inactive master custom slave slave SCL SDA Z SCL O custom inactive slave master slave SCL SDA Z SCL I Table 6 I2C bus modes summary TE0320 reference design includes an HDL core managing the fast mode 400 kHz DC communication between the Xilinx MicroBlaze embedded soft processor and the EZ USB FX2LP USB microcontroller I2C pins on B2B connector JM5 cannot be used as GPIOs general purpose I Os as these bus signals are pulled up to 3 3V 6 5 SPI bus 21 82 TE0320 has a flexible SPI bus on board as outlined in Figure 29 USB MCU EZ USB FX2LP SPI serial Flash B2B JM5 Figure 29 SPI bus topology SPI signals on the TE0320 are listed and described in Table 7 www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 definition description serial data This output signal is used to transfer data serially out of the device Data is shifted out SPI_Q output on the falling edge
22. there are different procedures to follow according to module status and purpose of use For instance a full quality control test already performed at Trenz Electronic laboratory premises requires all the following steps to be performed a generic USB device driver installation b USB microcontroller large EEPROM programming c specific USB device driver installation d e e Firmware Upgrade Tool utilization FWU file generation first following step development development OA quality control cycle cycles KH lab test a b e c e d e e e e Table 24 configuration steps via USB bus according to module status and purpose of use 38 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 10 2 1 generic USB device driver installation TEO320 users are normally not required to perform this step This step has to be performed when a Trenz Electronic module with EZ USB technology is connected to a computer on which the Cypress generic USB device driver is not yet installed Disconnect the TEO320 from the USB bus or leave it unconnected if it already IS Ensure that DIP switch S1 is set as follows S1A OFF this disconnect the serial data line between the USB microcontroller and the large EEPROM in so doing the USB microcontroller enumerates as a Cypress generic USB device S1B and S1C do not care
23. to the path you chose as the output file location you should find the fpga bin PROM file 10 2 4 3 FWU file from the PROM file Once you have got your fpga bin PROM file you can proceed and generate your FWU FirmWare Upgrade file The FWU file is a ZIP archive containing 3 files Bootload ini TE0320 booting settings see paragraph 10 2 4 3 1 Bootload ini file fpga bin FPGA configuration PROM file 51 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 usb bin EZ USB FX2LP USB microcontroller firmware To create your FWU file you shall replace the existing step4 user fpga bin with the latest fpga bin once per design zip the 3 files rename the zip file extension to fwu upload the file as explained in paragraph 10 2 5 Firmware Upgrade Tool utilization Warning file and path names are given and must not be changed 10 2 4 3 1 Bootload ini file The step4 user Bootload ini file defines some module start up options Version 1 0 of Bootload ini has the following structure Info information section do not edit this section Version Bootload ini file format version DeviceType 3 stands for current device type Settings settings section FPGABitSwap see Xilinx UG332 Spartan 3 Generation Configuration User Guide chapter SelectMAP Data Ordering default 1 do bit swapping FPGAPowerON value of FX2_PS_E
24. xilinx com products design_resources config_sol isp standards _specs ht m 72 82 www trenz electronic de TEO320 Series User Manual 18 B2B Connectors Pin Descriptions UM TEO320 v2 08 22 February 2012 18 B2B Connectors Pin Descriptions This section describes how the various pins on B2B connectors JM4 and JM5 connect with TE0320 on board components In this chapter most of naming conventions and colour coding scheme are taken from the official Xilinx Spartan 3A DSP documentation 18 1 Pin Labelling The pin label is abbreviated but descriptive for each pin All I O pins begin with lO If a pin can be used as a differential signal the name includes an _Lxxy_b suffix where indicates that the pin is part of a differential pair xx is a two digit integer unique for each bank that identifies a differential pin pair y is the signal polarity and is replaced by P for the positive signal or N for the negative These two pins form one differential pin pair bis an integer O through 2 for TE0320 indicating the associated I O bank Dual or multi purpose pins have a name composed of the signal names referring to each possible pin function e g IO_L52P_2 DO DIN MISO B is used as the active Low designator as in CSI_B A differential clock input requires two global clock inputs The P and N inputs follow the same configuration as for standard inputs on those pins The clock inputs that get paired together are consecutive p
25. 0 platgen p xc3sd3400afg676 4 lang vhdl lp x xxx projects EDK Release 11 5 platgen Xilinx EDK 11 5 Build EDK 155 70 Copyright c 1995 2009 Xilinx Inc All rights reserved nt system mhs Command Line platgen p xc3sd3400afg676 4 lang vhdl lp Running post placement packing Design Summary Number of errors 0 Number of warnings 1272 Logic Utilization Number of Slice Flip Flops 6 442 out of Number of 4 input LUTs 8 290 out of Logic Distribution Number of occupied Slices 7 889 out of Number of Slices containing only related logic Number of Slices containing unrelated logic t T44 47 744 23 872 7 88 13 17 335 9 out of O out of 7 889 100 7 889 0 See NOTES below for an explanation of the effects of unrelated logic 47 744 Total Number of 4 input LUTs 8 662 out of Number used as logic 6 212 Number used as a route thru 372 Number used for Dual Port RAMs 1 892 Two LUTs used per Dual Port RAM Number used as Shift registers 186 185 The Slice Logic Distribution report is not meaningful if the design is over mapped for a non slice resource or if Placement fails Number of bonded IOBs 119 out of IOB Flip Flops 39 IOB Master Pads 2 IOB Slave Pads 2 Number of ODDR2s used 44 Number of DDR ALIGNMENT NONE 44 Number of DDR ALIGNMENT co 0 Number of DDR ALIGNMENT C1 0 Number of BUFGMUXs 5 out of Number of DCMs 1 out of Number of BSCANs 1 out of Num
26. 0 02 13 out of out of out of out of out of of of of of of of of Of or 24 126 126 23872 11936 7889 1156 30 39 46 100 20 12 23 o oe oe www trenz electronic de 25 100 100 100 100 100 TEO320 Series User Manual 13 Verification 13 Verification UM TEO320 v2 08 22 February 2012 The quickest way to test most module functions is to execute the sample DMA test available in the TEO320 API Example Release folder of the TE0320 software package Hereunder is reported a sample trace of a successful execution TEO320 DLL Example 1 0 Get number of modules Connect module No 0 Connect module No 1 Disconnect Get FX2 status Get FX2 version Get FPGA firmware version Get FX2 FIFO Status Reset FX2 FIFO Status Write high speed data FPGA RX Read high speed data FPGA TX Exit On Si WO J On 1 VG GA b i kA TEO320 DLL Example 1 0 Get number of modules Connect module No 0 Connect module No 1 Disconnect Get FX2 status Get FX2 version Get FPGA firmware version Get FX2 FIFO Status Reset FX2 FIFO Status Write high speed data FPGA RX Read high speed data FPGA TX Exit OK F OO OO J On U GA A ki TEO320 DLL Example 1 0 Get number of modules Connect module No 0 Connect module No 1 Disconnect Get FX2 status Get FX2 version Get FPG
27. 0 2 Configuration via USB DUS une een 38 10 2 1 generic USB device driver msiallaton 39 10 2 2 USB microcontroller large EEPROM programming 41 10 2 3 specific USB device driver mstallatnon nennen en nennnnn nennen 44 ZN ME T N ae anti 46 10 2 5 Firmware Upgrade Tool utltzaton nennen nennen nennen nnnnne nen 52 10 3 Configuration Using Indirect SPI Configuration Mode 55 11 Recommended Design Tools SelliNnd8 u un ennnsnnenen nennen 56 VIA DONE LEO scams 56 Ile Ina E Eege 57 Et Ao A E E enn nina era 57 12 Reference Design Summaries GEIB 58 12 1 Reference Design Summary for Xilinx Spartan 3A DSP 1800 58 12 2 Reference Design Summary for Xilinx Spartan 3A DSP 2400 60 TI Vo EE 62 AO BR De On te 64 o re o 5 e O TEE 65 Y ee 66 14 3 Angle View 6 oa 68 15 1 Product Identification A 68 15 2 Assembly Options Cverview nn 68 APA A 69 1124 me A GE 70 17 Related Materials and References 0022240002200000020nn0onnnnnn nennen nnnnnnnnnnnnennnnnnn nennen nenn 71 Ao o A E E E 71 17 2 User o e 71 120 Kure EE 71 RADICA OE nan prieta 71 18 B2B Connectors Pin RR date S ne seine 73 A ee 73 UR lag Ate 73 18 3 BE BT Or Te ernennen he A EE 75 18 3 2 JM5 in e nee een 76 184 Signal Integrity CONSIST ANOS eege eege od 17 184 1JM4 Signal Verena aa 78 18 4 2 JM5 Signals I ee ae 79 19 Glossary of Abbreviations and FAC OI ee 80 A A A 81 201 Document Waa praia 81 AA ac ao A E A AE e A ere en ea 81 20 3 Copyrigh
28. 012 Table of Contents Es ee AE Tine ee ee ee nee ee 5 OG ae te E 5 Tale o E 6 4 Board DIMENSIONS nenn nenn nenn nnnnnnnnnnnnne nenne nnnne nenne nnnnennnnenennennnne nenn ennnennnnnn 7 OT Se ee ee een 8 IF DW Ua ee re ee 8 5 2 Power o ee ea ee 8 DEDOS FINE een 9 SANT U ee 12 5 4 1 Power on ESO nennen nee ee 12 A E 13 6 Inputs and COutputs cece ccccceeeeeeeeceeeeeeeceeeeeceeeseeeeeeeseeeeeeesseeeeeeessaaeceesseesseeesssageeeeseegeeeeeeaas 14 0 1 BIO 10 Baard DIET enter 14 BI EN EEN 16 AR A 16 aiii 17 SE E BEER An Ce IHR RE E E 18 BI UU T T a aE S T 18 6 3 2 JTAG lines at B2B connector ee 20 A 20 A 21 leal A a 22 GO OFLDUS 10r Oner de E 23 A ee einer 23 POLY LEI EM nee ee ei 23 Sog E E RRE E 24 RZ FEN EEN ke EE 24 A 25 0 0 1 DIF e Wiener VA IN aaa 25 A Pe nee eee ee eens 26 6 8 3 DIP Side Switches 0 H EE 28 SE VOO ele eee VRE EE 29 A a 30 e MAIN CIO OS CNO te 30 ZZ 22 AT e Be E E A N AE E E E A AENT AN EA 30 7 3 Interface Clock ECK 30 2A Digital Glock Manager DOM een een 30 E IO iaa 30 O MENOS iia 33 A EE 33 age al ge EE 33 BEE A er nee 33 De Sle ip ee En See e io EE AE E rrr 34 9 1 Power Supply Heouremente nennen nnnnnnnnn nenn 34 9 2 Hardware Design RI una 34 Ee ME E ee a een 34 gA JTAG Regule E 34 SA SNE REUE MENO sita 34 9 5 Operahng System o ODO een 35 3 82 www trenz electronic de TEO320 Series User Manual UM TEO320 v2 08 22 February 2012 Eeselen EE 36 10 1 Mode SE Pre E EE 37 1
29. 0320 for both configuration and operation The USB cable provides for Power supply Configuration by means of the Firmware Upgrade Tool FUT recommended for field upgrades Please use a dedicated JTAG Adapter during development Data communication channel during operation Figure 21 sample USB connection TE0320 side In order to minimize the stub on USB lines and improve communication quality the connection to both USB pins of B2B connector JM4 can be interrupted by removing resistors R3 and R4 le Figure 22 resistors R3 and R4 removed for lower stub on USB lines Should you require a module version without connector J1 please contact Trenz Electronic 6 2 2 USB Pins USB communication can be performed over 2 pins of B2B connector JM4 as 17 82 www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 detailed in Table 3 Ensure resistors R3 and R4 are populated to connect USB B2B pins B2B D P and B2B D Pto USB lines D P and D_P respectively pin number pin name signal name description 4 B2B D P D P USB data D 6 BBBDN DN USB data D Table 3 USB pins at B2B connector JM4 Figure 23 Resistors R3 and R4 required for USB communication over B2B connector JM4 6 3 JTAG Interface 6 3 1 JTAG connector J2 18 82 JTAG signals are available on the gender inverted standard 6 pin JTAG header connector J2 as shown in Figu
30. 22 February 2012 in Table 2 gender W P Trenz Electronic B2B connector JM4 JM5 female 6060 080 46 00 10 10 PPTR 23758 B2B mating connector male 6110 080 00 10 PPTR 23749 Table 2 Ordering codes of recommended B2B connectors The mating height of connectors 6060 080 46 00 10 10 PPTR and 6110 080 00 10 PPTR is 6mm Connectors JM4 and JM5 can mate also with any 1 27 mm 50 mil 050 pitch male header connectors with up to 2 x 40 pins Figure 17 em H dai H Um 7 fr e ep geg vals a a Aa fa ka Aah AAANAK e em bg ba dn eben ge IK ure 1 San ple Matcnina neader Connector Connectors JM4 and JM5 and are placed on the bottom side of the module as shown in Figure 18 15 82 www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 6 2 USB Interface USB communication can be performed in one of the following two ways through a USB connector through USB lines at one B2B connector Only one connection type at one time is allowed 6 2 1 USB Connector TEO320 is provided with a USB mini B receptacle device connector J1 on the top side Figure 19 USB connector top view x Kae Figure 20 USB mini B receptacle device connector 16 82 www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TEO320 v2 08 22 February 2012 Figure 21 shows a sample USB connection between computer and TE
31. 320 software package E z 1st_program CyConsole CyConsole exe The device must have the status Cypress Generic USB Device in the select device display Device Properties Control Endpt Xfers Other Endpt Xfers Misc This indicates that the Cypress USB Console u recognizes the EZ USB microcontroller Device LLL A IN Value Attributes Max Power Power 0x01 0x80 0x32 100 m Configuration Interfaces 4 LIntic_ Alt Setting Class Subclass Protocol 0 O E OxFF Vendor OxFF OxFF Interface Endpoints 0 Max Pkt Size gege 2503 Click Options from the top menu of the E SE CyConsole window and then choose the EZ USB oo Interface E E Device Properties Control Endpt Xfers Other Endpt Xters Misc Device Configurations 1 AA Meer oo 0x01 0x80 0x32 AA 00 m Configuration Interfaces 4 Inte m Setting A OxFF Vendor OxFF Interface Endpoints 0 Max Pkt Size Interval A new application window opens EZ USB 7 EZ USB Interface Interface S EEPROM button refers to Device USE Device gt D ae en s EEPROM seen the small EEPROM 256 bytes whereas _s sus curse ou snos per the Lg EEPROM one refers to the large _ Mend Req Req 0x00 Value 0x0000 Index 0x0000 Length 0 er Hex Bytes CO B4 04 81 00 01 00 y EEPROM 64 kbit Press the A Petes B Lg EEPROM button u we _ Set IFace Interface 0
32. 320 to a USB port on your computer using a USB cable Follow the Found New Hardware wizard to install the driver if necessary as shown in the following example You need to look for the steo3_user DEWESOFT inf device driver information file in the TEO320 software package Assistent fiir das Suchen never Hardware Assistent fiir das Suchen never Hardware Willkommen Wahlen Sie die Such und Installationsoptionen Sa Mit diesem Assistenten konnen Sie Software f r die folgende Hardwarekomponente installieren Vernvenden Sie de Kontrollkastchen um die Standardsuche zu erweitern oder ones einzuschr nken Lokale Pfade und Wechselmedien sind m der Standardsuche mit einbegriffen Der zutreffendste Treiber wird installiert Ty Falls die Hardwarekomponente mit einer CD d oder Diskette geliefert wurde legen Sie diese Wechselmedien durchsuchen Diskette CD jetzt ein Folgende Quelle ebenfalls durchsuchen CATEO3DO driver v Software automatisch installieren empfohlen Nicht suchen sonder den zu installlerenden Treiber selbst w hlen Wie mochten Sie vorgehen s oftware von einer Liste oder bestimmter Quelle verwenden Sie diese Option um einen Ger tetreiber aus einer Liste zu w hlen Es wird installieren fur fortgeschrittene Benutzer E nicht garantiert dass der von Ihnen gew hlte Treiber der Hardware am besten entspricht Klicken Sie auf weiter um den Yorgang fortzusetzen Zurtick Abbrechen Abbr
33. 39 40 J5 1023 AF23 lO L48P 2 VO 2 3 3V GCLK2 S 2 E 3 3V 2 VO IO L29N 2 AC14 J5 1003 41 42 J5 1024 AE25 lO L51P 2 VO 2 3 3V 3 3V 2 VO IO L39N_ 2 AR20 J5 1004 43 44 ANE out 1 2 V 3 3V 2 VO CO L39P_2 AF20 J5 1005 45 46 J5 1025 AF25 IO_L51P 2 VO 2 3 3V 3 3V 2 VO IO_L40N 2 AC19 J5 1006 47 48 J5 1026 YQ IO_LOSN_2 VO 2 3 3V 3 3V 2 VO IO L40P 2 AD19 J5 1007 49 50 J5 1027 W9 IO_LO5P_2 VO 2 3 3V E B D 51 52 J5 I028 AF3 IO_LO6N 2 VO 2 3 3V 3 3V 2 VO IO_L41N_ 2 AC20 J5 1008 53 54 J5 IO29 AB3 IO_LO6P_2 VO 2 3 3V 3 3V 2 VO IO L41P_2 AD20 J5 1009 55 56 J5 IO30 AF4 lO_LO7N 2 VO 2 3 3V 3 3V 2 VO IO LAN 2 U16 J5 1010 57 58 END END END GN A AN 2 VO O L42P 2 V16 J5 1011 59 60 J5 I031 AE4 IO_LO7P_2 VO 2 3 3V 3 3V 2 VO IO L43N 2 Y17 J5 1012 61 62 J5 I032 AD6 IO LO8N_2 VO 2 3 3V 3 3V 2 VO IO L43P_2 AA17 J5 1013 63 64 J5 IO33 AC6 IO_LO8P_2 VO 2 3 3V 2 5 V out 2 5V 65 66 J5 034 W10 lIO_LOON 2 VO 2 3 3V 3 3V 2 VO IO_L44N 2 AD21 J5 1014 67 68 J5 1035 V10 IO_LO9P_2 VO 2 3 3V IO_L25N_2 3 3V 2 VO IO L44P 2 AR21 J5 1015 69 70 onor Gk GCLK13 2 3 3V 2 VO IO LAN 2 AC21 J5 1016 71 72 END END E 3 3V 2 VO IO L45P_2 AD22 J5 1017 73 74 MONTE E GCLK12 2 lO_L26N_2 3 3V 2 VO IO L46N 2 V17 J5 1018 75 76 HON E GCLK15 lO_L26P_2 3 3V 2 VO IO L46P 2 W17 J5 1019 77 78 MORON E GCLK14 GND GND END GND 79 80 J5 I040 W13 IO_L20N_2 VO 2 3 3V 76 82 T
34. 5 r r 21010 D O TEC 886 Lei KOR WE WR tg 330 e WER AER pg Oo 6 om o TK g 20 EL 7370 Bee Ate 411 O 5 i o o 3 a ows D 90 1010 0 8 re g D e e Gi O wf 0600 2 9 MEMO 0 10 Dy pw a e U nx D 900 lla IK 0 f al A A n wur de SD DE POPPA PPP Pree Py 2329 2399 2229 Main miss shies situs AAA SU PLAY RT PY PY AAA AAA A A A ULUUUUUUUULULUNUHLUUUD r po S d VS A ZEIT ae e df 9 N A A O Le e e Ei A gt Le ef IE WHK O Og gp gt a Ki BP er el me 5 o tot DOOM MN MU A r HNRHNRHRRRRRNRHNNNNNNHN LC y kd 0004 E 37 Figure 54 TE0320 high resolution bottom view j DUT A e AR o TEO320 Series User Manual www trenz electronic de 66 82 14 High Resolution Pictures UM TEO320 v2 08 22 February 2012 14 3 Angle View Figure 55 TE0320 angle view 67 82 www trenz electronic de TEO320 Series User Manual 15 Ordering Information UM TE0320 v2 08 22 February 2012 15 Ordering Information Boards with other configurations or equipped with industrial temperature grade parts are available on request 15 1 Product Identification System Trenz Electronic TE0320 series modules have the following ordering numbers TEO320 XX Vest module PCB assembly series revision option 15 2 Assembly Options Overview ower module FPGA device oe Vcc
35. 8 gt e u mu i mn au vn Leen een m om ms o m oe eid mev ET x 47 6 31111 A A LE w AN O A LA LA LA LA HA FA hal sa Figure 2 TE0320 top view Figure 1 TE0320 bottom view 1 82 www trenz electronic de TE0320 Series User Manual UM TEO320 v2 08 22 February 2012 Key Features Industrial grade Xilinx Spartan 3A DSP FPGA module 1800 k gates or 3400 k gates USB 2 0 Hi Speed USB interface with a signalling bit rate of up to 480 Mbit s 32 bit wide 1 Gbit DDR SDRAM FPGA configuration through B2B connector JTAG port SPI Flash memory Large SPI Flash memory for configuration and operation accessible through B2B connector SPI direct FPGA JTAG port SPI indirect USB bus Firmware Upgrade Tool On board 100 MHz oscillator for high performance On board 24 MHz oscillator available to user 3 on board high power high efficiency switch mode DC DC converters capable of 3 A each Power supply range 4 0 7 0 V Power supply via USB or B2B carrier board 4 LEDs 2 push buttons 8 DIP switches Plug on module with 2 female 1 27 mm pitch header connectors 109 FPGA I O pins 10 dual purpose pins available on B2B connectors Evenly spread supply pins for good signal integrity Assembly options for cost or performance optimization available on request 2 82 www trenz electronic de TEO320 Series User Manual UM TEO320 v2 08 22 February 2
36. 9 FS 82 ES 83 3A FS 83 ES FO 22 50 06 E9 25 82 C8 F6 22 BB FE 05 E9 25 82 CS FZ 22 EB SF FS FO EA 9E 42 FO ES 9D 42 FO ES 9C 45 FO 22 Toggle 8051 Reset 00 Downloading file C TEOSOO usb iic Downloading 4096 bytes to addr 0 Downloading 1331 bytes to addr 1000 Download Successful 5427 bytes downloaded 10 2 3 specific USB device driver installation TE0320 users are normally required to perform this step when a Trenz Electronic module with DEWESoft technology is connected to a computer on which the DEWESoft specific USB device driver is not yet installed Disconnect the TE0320 from the USB bus or leave it unconnected if it already IS Ensure that DIP switch S1 is set as follows S1A ON this connect the serial data line between the USB microcontroller and the large EEPROM in so doing the USB microcontroller is able to read the large EEPROM and enumerate as a DEWESoft specific USB device S1B and S1C do not care configuration mode is irrelevant for this step S1D OFF master reset disabled 44 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 switch S1 label signal name status S1A 1 EEPROM serial data ON S1B 2 M2 A SIC 3 M1 X S1D 4 MR master reset OFF Table 28 S1 settings for installing specific USB device driver pmm Figure 49 S1 settings for installing pecific USB device driver Connect the TEO
37. A firmware version Get FX2 FIFO Status Reset FX2 FIFO Status Write high speed data FPGA RX Read high speed data FPGA TX Exit OR SZ VO OO J On 1 VG GA b i kA Pio een 0 Current modes 1 flasn bDusy 0 Fog prog 1 0 bootings 1 TE0320 DLL Example 1 0 Get number of modules Connect module No 0 Connect module No 1 Disconnect Get FX2 status Get FX2 version Get FPGA firmware version Get FX2 FIFO Status Reset FX2 FIFO Status Write high speed data FPGA RX Read high speed data FPGA TX EXIT OR Si WO J 004 GA NP 62 82 Major version 1 Minor version 7 Device hi 1 Device lo 1 TEO320 DLL Example 1 0 OR Si WO 004 GA NP Get number of modules Connect module No 0 Connect module No 1 Disconnect Get FX2 status Get FX2 version Get FPGA firmware version Get FX2 FIFO Status Reset FX2 FIFO Status Write high speed data FPGA RX Read high speed data FPGA TX Exit INT o 1 Major version Y Minor version 1 Release version 2 Buile versions 24 TE0320 DLL Example 1 0 1 Get number of modules 2 Connect module No O 3 Connect module No 1 4 Disconnect 5 Get FX2 status 6 Get FX2 version 7 Get FPGA firmware version 8 Get FX2 FIFO Status 9 Reset FX2 FIFO Status w Write high speed data FPGA RX r Read high speed data FPGA TX O Exit
38. A is powered and regardless of the mode pin settings However when the FPGA mode pins are set for JTAG mode M 2 0 lt 1 0 1 gt the FPGA waits to be configured via the JTAG port after a power on event or after PROG_B is pulsed Low Selecting the JTAG mode simply disables the other configuration modes No other pins are required as part of the configuration interface MO M2 have Pull ups in FPGA If S1B S1C is off then signals from B2B should be left float If S1B C1C is on then mode can be set from B2B Stop condition Never set Mx from B2B directly to one Table 21 shows some options about setting mode pin M2 high or low M2 value M2 S1B M2 O JM5 37 82 0 ON any 0 any 0 1 OFF floating 1 OFF 1 Table 21 mode pin M2 settings Table 22 shows some options about setting mode pin M1 high or low Mivalue M1 S1C M1 JM5 0 ON any 0 any 0 1 OFF floating 1 OFF 1 Table 22 mode pin M1 settings Table 23 shows some options about setting mode pin MO high or low www trenz electronic de TEO320 Series User Manual 10 Configuration UM TEO320 v2 08 22 February 2012 MO value MO JM5 0 0 1 floating 1 1 Table 23 mode pin MO settings S1B M2 FPGA 2 7 cp M2 JM5 S1C M1 FPGA 3 lan M1 0 JM5 MO FPGA MO JM5 Figure 44 configuration modes schematic 10 2 Configuration via USB bus To configure a 1E0320 module via USB bus
39. AftSetting jo 43 82 www trenz electronic de TEO320 Series User Manual 10 Configuration Large 512 64K byte EEPROM Download Suchen in IS 1st_program D IH E driver Zuletzt O CyConsole verwendete D Desktop O e ES Eigene Dateien y Arbeitsplatz Dateiname Abbrechen fusb iic v ES EEPROM Files D wl v Schreibgeschiitzt ffnen DD Netzwerkumgeb Dateityp ung The display window shows the process of IIC file being programmed into the EEPROM and displays Downloaded Successful when completed UM TEO320 v2 08 22 February 2012 Select the step2_factory USB iic file in the TE0320 software package and press the Open button to start writing to EEPROM 7 EZ USB Interface Device USB Device zl D Clear _Load Mon EEPROM Select Mon Get Dew Get Conf Get Pipes Get Strings Download EEPROK URB Stat HOLD RUN vend Req Req 0x00 Value 0x084E Index 0x0000 Length 0 Dir 0 OUT Hex Bytes CO B4 04 81 00 01 00 Pipe fo Length 128 Packet Size Packets Pipe D Length 64 Hex Bytes E D Reset Pipe bort Pipe File Trans Pipe D Set IFace Interface fo AltSetting jo 0000 02 OD 91 Download 12 bytes addr d91 0000 78 7F E4 F6 DS FD 75 81 3E 02 OS Ee Download 96 bytes addr Sde BB 01 OC ES 82 29 F5 82 ES 83 34 FS 83 EO 22 50 06 E9 25 82 FS E6 22 BB FE 06 E9 25 82 FS EZ 22 ES 82 29 FS 82 ES 83 3A FS 83 E4 93 22 FS BB Ol OD ES 82 2
40. D OGND GND VccclOO VO O L20P 0 F15 JM4 IO01 4 B2B DP VO USB Vcccloo VO IO L21IN O Op JMA IO02 6 B2B DN VO USB 2 B B 8 JM4 IO34 K12 lO L39N O VO 0 VccclOo VccclOO 0 VO lO_L21P_0 D17 JM4 1003 10 JM4 IO35 J12 lO_L39P_0 VO 0 Vcccloo Vcccloo 0 VO IO L22N 0 C15 JM4 1004 12 JM4 1036 D8 lO_L40N_0 VO 0 VecciO0 VccclOO 0 VO lO L22P 0 D16 JM4 I005 14 JM4 1037 C8 IO_L40P O VO 0 VccclOO VccclO0 0 VO IO L23N O A15 JM4 1006 16 GND OGND GND GND VccclOO 0 VO lO_L23P_0 B15 JM4 I007 18 JM4 1038 C6 IO L41N_0 VO 0 VecciO0 VccclOO 0 VO IO L24N 0 F14 JM4 1008 20 JM4 1039 B6 lO_L41P_0 VO 0 VecciO0 VccclOO 0 VO O L24PO E14 JM4 I009 22 JM4 1040 C7 IO L42N_ 0 VO 0 VecciO0 GND GN GND 24 JM4 1041 B7 lO_L42P_0 VO 0 VccclOO Ao 010 0 Ze JM4 1010 26 JM4 l042 K11 lO_L43N_0 VO 0 VecciO0 Ao 010 eer JM4 1011 28 JM4 l043 J11 lO_L43P_0 VO 0 VecciO0 GCLK4 VcceclOoO a JM4 1012 30 VecciO0 VO 0 VccclOO Ao 010 ine JM4 1013 32 JM4 1044 D6 lO_L44N_0 VO 0 VccclOO Ao 010 as JM4 1014 34 JM4 1045 C5 lO_L44P_0 VO 0 VecciO0 Ao 010 CS JM4 1015 36 JM4 1046 B4 lO_L45N_0 VO 0 VccclOO 37 38 JM4 1047 A4 lO_L45P_0 VO 0 Vcccloo lO_L28N_0 Ao 010 GCLK11 ALEA SOJA 39 40 JM4 l1048 H10 IO L46N O VO 0 VecciO0 lO_L28P_0 Ao 010 0 GCLK10 A ON 41 42 JM4 1049 G10 IO L46P O VO 0 VecciO0 VccclOO 0 VO O L29N O B12 JM4 I018 43 44 VccclO0 VO 0 VccclOo Vcccloo 0 VO O L29P 0 A12 JM4 I019 45
41. EX Swap Bits OFF BIN Swap Bits ON BIN Swap Bits OFF UFP CC format ISC Output File Name fpga Enable Compression Auto Select PROM Description In this step you will enter information to assist in setting up and generating a PROM file for the targeted storage device and mode A Checksum Fill Yalue When data is insufficient to fill the entire memory of a PROM the value specified here is used to calculate the checksum of the unused portions es Output File Name This allows you to specify the base name of the file to which your PROM data will be written es Output File Location This allows you to specify the directory in which the file named above will be created i e Format PROM files can he nenerated in any numher of industry standard formats Denendina on the PROM file Format vour PROM nronorammer uses vououtouk a TEK Any other name than fpga for the output file name input field is not allowed B Add Device e Start adding device File to Jj Revision O Just acknowledge the pup up message Add Device Suchen in B implementation D eE m Ed 3 cache Drs232_wrapper KJ chipscope_icon_O_wrapper Dspi_flash_wrapper Zuletzt Dchipscope_ila_0_wrapper DD switches_wrapper verwendete D clock_generator_O_wrapper xps_fx2_0_wrapper 3 Dddr_sdram_wrapper Dxps_i2c_slave_0_wrapper B rowse to th e 7 imp dh ementat 1 on 1 fo der of Ddebug_module_wrap
42. EZ USB ae Flash custom master S2 FX2PON deselected slave FX2_PS_EN 0 inactive master FPGA gt Flash custom SPI Z SPI_ S 1 deselected slave inactive au master B2B JM5 ae Flash custom NR S2 FX2PON _ slave SPI Z FX2 PS EN 0 SPI_ S 0 master ou EZ USB lt B2B JM5 custom SPI S 4 S2 FX2PON slave deselected FX2_PS_EN 0 slave el master EZ USB lt B2B JM5 custom 8 S2 FX2PON _ deselected SPI C Z FX2 PS EN 0 SPI_ S 1 Table 10 SPI bus modes for operation Other combinations of master and slave units are neither supported nor recommended 6 6 1 System LED D1 23 82 LED D1 is connected to the DONE pin The DONE pin is powered by the VCCAUX supply The FPGA actively drives the DONE pin Low during configuration Thus LED D1 is unconditionally turned off during configuration To have LED D1 turned on or off after successful configuration please see paragraph 11 Recommended Design Tools Settings www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 pea ea bd hd bd bd Figure 30 DONE LED D1 bottom side 6 6 2 User LEDs D 5 8 TE0320 is provided with 4 user LEDs ALED is lit when the corresponding signal listed in Table 11 is set high logical 1 LED signal FPGAball FPGApin bank D5 ULI R20 IO_L22N_1 1 D6 UL2 V23 IO_L21P_i1 1 D UL R19 IO_L22P_1 1 IO_L23N_1 VREF_1 D8 UL4 U24 1
43. M S1B 2 M2 mode pin M2 1 M2 0 S1C 3 M1 mode pin M1 1 MI 0 S1D 4 MR master reset module reset module running Table 13 S1X settings description DIP slide switches S1A is ON by default to allow the USB microcontroller to read the serial EEPROM and enumerate as a custom specific USB device When DIP slide switches S1A is ON the USB microcontroller can re write the serial EEPROM to for example store a new custom specific firmware When DIP slide switch is OFF the USB microcontroller cannot read the serial EEPROM and enumerates as a generic USB device www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 6 8 2 Slide Switch S2 TEO320 is provided with a slide switch S2 Figure 33 Slide switch S2 angle view Slide switch S2 conditions the value of signal PS_EN Signal PS_EN enables high or disables low power rails 2 5V and 1 2V According to the corresponding assembly option power rail VCCCIOO can depend or not on the 2 5V power rail Power rail 3 3V is not controlled by signal PS_EN and is unconditionally enabled Table 14 summarizes all switching options implied by slide switch S2 under the standard assembly option S2 FX2 PON S2 FX2 PON power rail S2 PON X2 ps EN 1 FX2 PS EN 0 2 5V 1 2V VCCCIOO 2 5V VCCCIOO 3 3V Table 14 Slide switch S2 settings overview 6 8 2 1 Slide Switch S2
44. N after SPI Flash memory programming see paragraph 6 8 2 Slide Switch S2 default 1 power on after upgrade 10 2 4 3 2 usb bin file The step4 user usb bin file contains the firmware to be written in the large EEPROM of the EZ USB FX2LP USB microcontroller and loaded at module Start up to implement the DEWE Gott instruction set 10 2 5 Firmware Upgrade Tool utilization 10 2 5 1 Switch Settings For the Firmware Upgrade Tool to operate correctly switch S1 and S2 shall be set properly 10 2 5 2 DIP Switch S1 Ensure that DIP switch S1 is set to USB microcontroller large EEPROM enabled S1A set to ON configuration mode set to Master SPI S1B and S1C set to ON 52 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 master reset disabled S1D set to OFF S1 S1 label signal status S1A 1 EEPROM serial data ON S1B 2 M2 ON S1C 3 M1 ON S1D 4 MR master reset OFF Table 29 S1 settings for configuration via USB bus Figure 51 S1 settings for configuration via USB bus 10 2 5 3 Slide Switch S2 Ensure that slide switch S2 is setto FX2 PON switch signal status S2 PON FX2 PON FX2PON Table 30 S2 settings for SPI Flash programming via USB bus iair Figure 22 S2 settings for SPI Flash programming via USB bus FX2 PON This will allow the EZ USB FX2LP USB microcontroller to power off the FPGA release the SPI lines
45. PON When slide switch S2 is in the right position PON power rails unconditionally on signal PS_EN is set to power rail 3 3V Thus power rails 2 5V and 1 2V are unconditionally enabled Figure 34 S2 on position PON 6 8 2 2 Slide Switch S2 FX2 PON 26 82 When slide switch S2 is in the left position FX2 PON power rails conditionally on depending on signal FX2_PS_EN signal PS_EN is set to signal FX2_PS_EN driven by the EZ USB FX2LP USB microcontroller under user control When the EZ USB FX2LP USB microcontroller sets signal FX2_PS_EN high power rails 2 5V and 1 2V are enabled This setting can be useful for dynamic www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 full power operation Figure 35 S2 on position FX2 PON FX2_PS_EN high When the EZ USB FX2LP USB microcontroller resets signal FX2_PS_EN low the following components are switched off FPGA core logic 1 2V DDR SDRAM 2 5V FPGA bank 3 2 5V VREF 2 5V VCCCIOO 2 5V FPGA bank 0 This setting can be useful for dynamic low power operation Figure 36 S2 on position FX2 PON FX2_PS_EN low 6 8 2 3 Alternate Assembly Options for Slide Switch S2 Slide switch S2 can be replaced by one resistors in the following cases cost sensitive applications applications where just one position of S2 is required application where switching of S2 is not allowed Assemb
46. To define low zero level VAR pin connected to ground rail through zero resistor to define high one level VAR pin left float open These pins should be configured with pullup option in user design Available module assembly variants listed in Table 38 VAR5 1 VAR4 VAR3 1 4 VAR2 VAR1 VARO 1 1 1 Variant EVO1 4 4 4 1 1 0 EV02 Table 38 Module assembly variants 15 3 Availability For the latest product details and available options please visit 69 82 www trenz electronic de To order or obtain information e g on pricing or delivery please visit shop trenz electronic de www trenz electronic de TEO320 Series User Manual 16 Product Support UM TE0320 v2 08 22 February 2012 16 Product Support 70 82 Trenz Electronic provides support via its site at www trenz electronic de gt support This web site is used as a means to make files and information easily available to customers It contains the following information product support data sheets errata application notes sample programs design resources user s guides hardware support documents latest software releases archived software general technical support Frequently Asked Questions FAQ technical support requests business of Trenz Electronic product selector ordering guides latest press releases listing of events listings of business partners
47. UM TE0320 v2 08 22 February 2012 e RI unten Figure 41 R135 bottom side Figure 42 R136 top side Any other combination of resistors R135 and R136 is not supported 32 82 www trenz electronic de TEO320 Series User Manual 8 Memories UM TE0320 v2 08 22 February 2012 8 Memories The TEO300 has three on board memories DDR SDRAM SPI Flash serial EEPROM 8 1 DDR SDRAM TE0320 modules have two 512Mb DDR SDRAM components each with a 16 bit data bus connected in parallel to FPGA bank 3 as a virtual 512Mb DDR SDRAM component with a 32 bit data bus Memory available in industrial and commercial temperature grade 8 2 SPI Flash TEO320 has an STMicroelectronics M25P32 64 128 32 64 128 Mbit low voltage serial Flash memory with 75 MHz SPI bus interface for configuration and operating storage accessible through USB or SPI Default module configuration contain 32 Mbit Flash chip M25P32 others available by request 8 3 Serial EEPROM TEO300 modules have a Micron Technology 24LC128 128 kbit 12C CMOS Serial EEPROM for EZ USB FX2 firmware vendor ID and device ID storage accessible through the EZ USB FX2 microcontroller 33 82 www trenz electronic de TEO320 Series User Manual 9 System Requirements UM TE0320 v2 08 22 February 2012 9 System Requirements 9 1 Power Supply Requirements TE0320 can be power supplied by one of the following power sources USB bus 5 V JM5 1 4 4 V to 7 V powe
48. able 41 pin out of B2B connector JM5 www trenz electronic de TEO320 Series User Manual 18 B2B Connectors Pin Descriptions UM TEO320 v2 08 22 February 2012 18 4 Signal Integrity Considerations 77 82 Traces of differential signals pairs are NOT routed symmetrically as symmetric pairs Traces of differential signals pairs are NOT routed with equal length For applications where traces length has to be matched or timing differences have to be compensated Table 42 and Table 43 list the trace length of I O signal lines measured from FPGA balls to B2B connector pins Traces of differential signals pairs are routed with a differential impedance between the two traces of 60 ohm Pairs of pins that form a differential I O pair appear colored together in the table An electronic version of these pin out tables are available for download from the Trenz Electronic support area of the web site www trenz electronic de TEO320 Series User Manual 18 B2B Connectors Pin Descriptions 18 4 1 JM4 Signals Trace Length 78 82 UM TEO320 v2 08 22 February 2012 len FPGA FPGA JM4 JM4 FPGA FPGA len y JM4 pin mm Din ball singal s
49. an 3A DSP FPGA using Xilinx IMPACT 11 5 To write the SPI Flash memory perform the following steps a disable the master reset S1D do not care about all other switches at write time b connect the Xilinx platform cable to JTAG connector J2 as described in paragraph 6 3 1 JTAG connector J2 c generate or locate the FPGA bit stream file you want to store on the memory d prepare an SPI PROM file using the ISE IMPACT graphical software from the FPGA bit stream file e use the ISE iMPACT graphical software to in system program the SPI PROM In order to have the module to configure from its SPI Flash memory next time it is re booted ensure one of following DIP switch settings etch S1A S1B SiC S1D S2 EEPROM serial data M2 M1 MR master reset PS_EN state 0 ON Uz ON O ON 1 OFF X do note care state 1 OFF 0 ON Oz ON NO FX2 PON Table 31 S1 settings for booting from SPI Flash memory For your convenience a reference video is available on the TrenzElectronic s Channel at YouTube For further reference please read Xilinx XAPP974 Indirect Programming of SPI Serial Flash PROMs with Spartan 3A FPGAs 55 82 www trenz electronic de TEO320 Series User Manual 11 Recommended Design Tools Settings UM TEO320 v2 08 22 February 2012 11 Recommended Design Tools Settings 11 1 DONE LED When the configuration process successfully completes the FPGA either actively d
50. an be configured in the following ways B2B connector JTAG Slave Parallel SelectMAP Slave Parallel JTAG port SPI Flash memory For further information on Xilinx Spartan 3A DSP configuration modes please consult the documentation listed in chapter 17 Related Materials and References The SPI Flash memory can be programmed in the following ways s B2B connector SPI direct FPGA JTAG SPI indirect USB bus Firmware Upgrade Tool SPI Flash SPI indirect f JTAG B2B USB O O Figure 43 configuration modes overview www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 10 1 Mode Select Pins M 2 0 The mode select pins M 2 0 define the configuration mode that the FPGA uses to load its bitstream Table 20 shows the configuration modes supported by TEO320 The logic level applied to the mode pins is sampled on the rising edge of INIT_B immediately after the FPGA completes initializing its internal configuration memory See Xilinx UG332 Spartan 3 Generation Configuration User Guide for additional information on these signals configuration mode M2 M1 MO master SPI 007 1 JTAG 1 0 1 slave parallel SelectMAP 1 1 O iz EL e slave serial Table 20 mode pin settings supported by TE0320 Xilinx Spartan 3 generation FPGAs have a dedicated four wire IEEE 1149 1 1532 JTAG port that is always available any time the FPG
51. ber of DSP48As 3 out of Number of RAMB16BWERs 30 out of Number of BSCAN SPARTAN3As 1 out of Number of RPM macros 1 Average Fanout of Non Clock Nets 2 469 24 126 126 25 20 12 100 je O 23 100 60 82 www trenz electronic de TEO320 Series User Manual 12 Reference Design Summaries ISE 11 5 Initializing temperature to 85 000 Celsius Initializing voltage to 1 140 Volts Device speed data version Design Summary Report Number of External IOBs 119 out of 469 Number of External Input IOBs 30 Number of External Input IBUFs 30 Number of LOCed External Input IBUFs 30 Number of External Output IOBs 43 Number of External Output DIFFMs 2 Number of LOCed External Output DIFFMs 2 Number of External Output DIFFSs 2 Number of LOCed External Output DIFFSs 2 Number of External Output IOBs 39 Number of LOCed External Output IOBs 39 Number of External Bidir IOBs 46 Number of External Bidir IOBs 46 Number of LOCed External Bidir IOBs 46 Number of BSCANs 1 out Number of BUFGMUXs 5 out Number of DCMs I Sue Number of DSP48As 3 out Number of RAMB16BWERS 30 out Number of Slices 7889 out Number of SLICEMs 1156 out Number of LOCed Slices 125 out Number of LOCed SLICEMs 83 out Overall effort level ol Router effort level rl1l 61 82 High High default Range default Range UM TE0320 v2 08 22 February 2012 0 000 to 85 000 Celsius 1 140 to 1 260 Volts PRODUCTION 1 33 201
52. ce Manual TRM www cypress com rID 14667 17 3 Tutorials Xilinx ISE 10 1 In Depth Tutorial Chapter 7 IMPACT Tutorial www xilinx com direct ise10_tutorials ise 1 Otut pdf Xilinx UG695 ISE In Depth Tutorial Chapter 7 iMPACT Tutorial http www xilinx com support documentation sw_manuals xilinx1 1 ise1 1tut pdf 17 4 Application Notes Xilinx XAPP104 A Quick JTAG ISP Checklist Most Xilinx CPLDs PROMs and FPGAs have an IEEE Standard 1149 1 JTAG port Xilinx devices with a JTAG port are in system programmable ISP through the JTAG port The ISP feature is beneficial for fast prototype development This application note describes a short list of considerations needed to get the best performance from your ISP designs www xilinx com support documentation application_notes xapp104 paf Xilinx XAPP974 Indirect Programming of SPI Serial Flash PROMs with Spartan 3A FPGAs 71 82 www trenz electronic de TEO320 Series User Manual 17 Related Materials and References UM TEO320 v2 08 22 February 2012 This application note describes how to indirectly program an SPI Serial Flash PROM through the JTAG interface of a Spartan 3A FPGA using IMPACT 9 1 01i The hardware setup software flows for file generation and programming are also covered www xilinx com support documentation application_notes xapp974 pdf ISP Standards Specifications Brief descriptions of In system Programmability ISP standards and specifications www
53. ch can be used for low battery detection power fail warning or for monitoring Vsup power rail An additional power fail circuit can be used to monitor the input voltage At 4 4V a power fail signal PFO is sent to the FPGA Should you wish or need another threshold voltage please contact Trenz Electronic 13 82 www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 6 Inputs and Outputs 6 1 Board to Board Connectors 14 82 The module has two B2B board to board connectors JM4 and JM5 with the following features gender female overall number of contacts 160 contacts per connector 80 rows per connector 2 pitch 1 27 mm 50 mil 050 Figure 15 Board to board connector assembled on the TE0320 Trenz Electronic recommends to mate the standard B2B connectors with the following ones m 2x W P 6110 080 00 10 PPTR 1 27 mm 50 mil 050 pitch 80 pin double row boxed plug male header board to board B2B connectors Figure 16 Close up of the recommended mating B2B connector This connector couple offers the following two advantages the module is protected against polarity inversion the connection presents a mechanical resistance sufficient for most applications Ordering codes for connectors JM4 JM5 and their mating connectors are given www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08
54. clO0 mnemonics source TE0320 00 EV01 XC3SD1800A 4FGG676C USB 3 3 V evaluation TEO320 00 EVO2 XC3SD1800A 4FGG676C B2B 3 3 V evaluation TE0320 00 EV02B XC3SD3400A 4FGG676C B2B 3 3V evaluation big Table 34 assembly options overview To determine the FPGA device you just read the code on the package under the Xilinx Spartan label To determine the power supply source please see paragraph 5 2 Power Supply Sources To determine the VccclOO voltage please see paragraph 5 3 On Board Power Rails To determine PCB revision and assembly variant from FPGA TE0320 have dedicated user signals which can be read by user core Board revision coded in 4 bits REV 3 0 Signal name FPGA pin REVO C21 REV1 D21 REV2 E21 REV3 C20 Table 35 Board revision pins To define low zero level REV pin connected to ground rail to define high one level REV pin left float open These pins should be configured with pullup option in user design See Table 12 for current list of board revisions REV3 REV2 REV1 REVO Board revision 1 1 1 1 Revision 00 Table 36 Board revisions Module assembly variant encoded using VAR 5 0 pins 68 82 www trenz electronic de TEO320 Series User Manual 15 Ordering Information Signal name FPGA pin VARO F17 VAR1 K16 VAR2 J16 VAR3 E17 VAR4 D20 VAR5 A20 Table 37 Assembly variants pins UM TE0320 v2 08 22 February 2012
55. den Ger tetreiber Laufmerk ausgew hlt ist Wahlen Sie den Hersteller und das Modell der Hardwarekomponente und klicken Sie auf Wetter Klicken Sie auf Datentr ger wenn Sie uber einen Datentr ger verf gen der den erforderlichen Treiber enth lt Dateien des Herstellers kopieren won Kompatible Hardware anzeigen E TEO32041 st_programdriver Ww Modell Cypress Generic USB Device A Dieser Treiber ist nicht digital signiert Datentr ger Warum ist Treibersignierung wichtig 40 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 Hardwareinstallation Assistent f r das Suchen neuer Hardware Fertigstellen des Assistenten Die Software die f r diese Hardware installiert wird Cypress Generic USB Device Die Software f r de folgende Hardware wurde installiert hat den Windows Logo T est nicht bestanden der die Kompsat bilit t mit Windows lt P berpraft warum ist dieser Test wichtig of e Das Fortsetzen der Installation dieser Software kann die korrekte Funktion des Systems direkt oder n Zukunft beeintr chtigen Microsoft empfiehlt strengstens die Installation jetzt abzubrechen und sich mit dem Hardwarehersteller fur Software die den Windows Logo Test bestanden hat in Verbindung zu setzen Cypress Generic USB Device _ Installation fortsetzen E Installation abbrechen Klicken Sie auf Fertig stell
56. download bit IMPACT Processes Available Operations are mb Generate File HGH kl Add one device fas bl Console Errors Warnings Generate System ACE or PFF File PROM File Generation Target Xilinx PROM 8 197 280 Bits used File fpga in Location C Daten 50 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 You should see the following message in the main panel generate succeeded E ISE iMPACT PROM File Formatter Xilinx Flash PROM er File Edit View Operations Output Debug Window Help Deals SO ae iMPACT Flows cr DI di xX 29 Boundary Scan S 0x 0000_0000 Gel SlaveSerial Gel Direct SPI System CE Create PROM File PROM File Formatter xc32c01 5004 download bit download bit LE 3415319 IMPACT Processes Available Operations are Generate File HGH IC O lt 000F_FFFF PROM File Formatter line Flash PROM Console Writing file C Daten fpga sig Writing file C Daten fpga cfi Z BATCH CMD setCurrentDesign wersion D Errors Warnings PROM File Generation Target ln PROM 8 197 260 Bits used File fpga in Location C Daten E iMPACT Save Project i 2 Save current project before exiting You might now want to save your Xilinx IMPACT project settings for future use K In the folder corresponding
57. echen 45 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 Hardwareinstallation Assistent fiir das Suchen neuer Hardware Fertigstellen des Assistenten Die Software die fur diese Hardware installiert wird DEWESoft USE Device Die Software f r die folgende Hardware wurde installiert DEWESof USB Device hat den Windows Logo Test nicht bestanden der die Kompatibilit t mit Windows AH berpruft parum ist dieser Test wichtig Das Fortsetzen der Installation dieser Software kann die korrekte Funktion des Systems direkt oder n Zukunft beeintr chtigen Microsoft empfiehlt strengstens die Installation jetzt abzubrechen und sich mit dem Hardwarehersteller fur Software die den Windows Logo Test bestanden hat in Yerbindung zu setzen Klicken Sie auf Fertig stellen um den Vorgang abzuschlie en Installation fortsetzen 1 Installation abbrechen lt Zur ck Feri Abbrechen After successful installation of the specific device driver TE0320 should be identified as DEWESoft USB Device and the Device Manager panel should look like Figure 50 E Ger te Manager Datei Aktion Ansicht 3 amp p 4 Anschl sse COM und LPT 8 Audio video und Gamecontroller 3 Bildbearbeitungsger te e Computer 43 Eingabeger te Human Interface Devices a Grafikkarte IDE ATANATAPI Controller Ey Laufwerke 19 M use und andere Zeigeger te Ed Monitore BS Net
58. en um den Yorgang abzuschlie en El uck 1 IC Net j Abbrechen After successful installation of the generic device driver TEO320 should be identified as Cypress Generic USB Device and the Device Manager panel should look like Figure 46 Es Ger te Manager Datei Aktion Ansicht 7 ch 4 E Wd Anschl sse COM und LPT 2 Audio Yideo und Gamecontroller 38 Bildbearbeitungsger te e 7i Computer ob DYDCO ROM Laurwerke 43 Eingabeger te Human Interface Devices Grafikkarte Sy IDE ATAJATAPI Controller See Laufwerke a M use und andere Zeigeger te Monitore E8 Netzwerkadapter Prozessoren y Speichervolumes i F Systemger te 2 Tastaturen E USB Controller E H EE H E E E EE Figure 46 Device manager after successful installation of the generic device driver Now the EZ USB microcontroller can be controlled from a computer by the Cypress USB Console 10 2 2 USB microcontroller large EEPROM programming TEO320 users are not normally required to perform this step Disconnect the TEO320 from the USB bus or leave it unconnected if it already IS Ensure that DIP switch S1 is set as follows S1A OFF this disconnect the serial data line between the USB microcontroller and the large EEPROM in so doing the USB microcontroller enumerates as a 41 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 Cypress gen
59. eric USB device S1B and S1C do not care configuration mode is irrelevant for this step S1D OFF master reset disabled switch S1 label signal name SIA 1 EEPROM serial data OFF S1B 2 M2 X SIC 3 Mi x S1D 4 MR master reset OFF Table 26 S1 settings for forcing the EZ USB FX2LP USB microcontroller to enumerate as a generic USB device driver Figure 47 S1 settings for forcing the EZ USB FX2LP USB microcontroller to enumerate as a generic USB device driver Connect the TEO320 to a USB port on your computer using a USB cable The USB microcontroller should now enumerate as a Cypress generic USB device Toggle S1A to ON this will Connect the serial data line between the USB microcontroller and the large EEPROM s Allow the EZ USB FX2LP USB microcontroller to program the large EEPROM Prevent the EZ USB FX2LP USB microcontroller to enumerate again for any content of the large EEPROM switch S1 label signal name S1A 1 EEPROM serial data ON S1B 2 M2 X S1C 3 Mi X S1D 4 MR master reset OFF Table 27 S1 settings for programming EZ USB FX2LP USB microcontroller large EEPROM ei a N UR Figure 48 S1 settings for programming EZ USB FX2LP USB microcontroller large EEPROM 42 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 PETERS Run Cypress USB Console application from the E TE0
60. ice and mode Checksum Fill Yalue When data is insufficient to fill the entire memory of a PROM the value specified here is used to calculate the checksum of the unused portions es Output File Name This allows you to specify the base name of the file to which your PROM data will be written In step 3 enter data ofthe right panel type fpga in the output file name input field choose a suitable path for the output file location input field select BIN swap bits ON from the drop down menu file format in the flash PROM file property sub panel press the OK button in the bottom left corner of the current window 48 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 E PROM File Formatter Step 1 Select Storage Target Step 2 Add Storage Device s Step 3 Enter Data Storage Device Type General File Detail value Xilinx Flash PROM Checksum Fill Non Volatile FPGA Device bits xcfO1s 1 m value PROM Family Platform Flash FF Spartan3AN SPI Flash Add Storage Device Remove Storage Device A Configure Single FPGA Output File f y Configure MultiBoot FPGA AA C Daten E BPI Flash Configure Single FPGA Configure MultiBoot FPGA Flash PROM File Property Value Configure from Paralleled PROMs File Format BIN Swap Bits ON Y Generic Parallel PROM Enable Revisioning MCS EXO Number Of Revisions TEK HEX Swap Bits ON H
61. ingal ball pin mm 1 26 IO_L2OP_O F15 JM4 1001 3 4 5 6 7 8 JM4 IO34 K12 IO_L39N_O 29 9 10 JM4 I035 J12 O L39P O 26 24 lO L22N D C15 JM4 I004 11 12 26 lO L22P 0 D16 JN4 I005 13 14 15 16 17 18 JM4 1038 C6 O L41N O 24 22 IO L24N O0 F14 JV4 1008 19 20 JMA I039 B6 IO L41P O 24 18 lO L24P O E14 JM4 I009 21 23 25 26 JM4 1042 K11 O L43N O 24 27 28 JM4 1043 J11 lO_L43P_0 23 lO_L26N_0 dd GCLK7 A14 JM4 lO12 29 30 lO_L26P_0 11 GCLK6 B14 JM4 l013 31 32 33 34 35 36 JMA IO46 B4 O LAN O 15 37 38 JMA I047 A4 O L45P O 14 IO L28N_ 0 13 GCLK11 C13 JM4 1016 39 40 lO_L28P_0 12 GCLK10 B13 JM4 lIO17 41 42 45 46 JM4 1050 H9 O L47N 0 15 27 IO L3ON O C12 JM4 l020 47 48 JNA I051 G9 IO L47P O 14 30 O L3OP O D13 JM4 1021 49 50 51 52 53 54 JMA I054 B3 IO L51N O 9 IO LS3P A1 Ai CO 55 56 JMA I055 A3 lO_L51P_0 9 20 O L34N 0 D10 JM4 I024 57 58 21 O L34P_ O0 C10 JM4 025 59 60 61 62 63 64 JM4 lO58 A22 lO LO7N_O 36 65 66 JM4 lO059 B23 lO LO7P O 41 27 IO_L36N_O B9 JM4 1028 67 68 27 10 L36P 0 A9 JM4 1029 69 70 73 74 29 IO_L38N_O B8 JM4 1032 75 76 28 IO_L38P_0 A8 JM4 1033 77 78 79 80 Table 42 trace length of signal pins of B2B connector JM4 www trenz electronic de TEO320 Series User Manual 18 B2B Connectors Pin Descriptions 18 4 2 JM5 Signals T
62. ins in clock number an even clock number and the next higher odd value For example GCLKO and GCLK1 are a differential pair 18 2 Pin Types Most pins of B2B connectors JM4 and JM5 are general purpose user defined I O pins GPIOs There are however up to 9 different functional types of pins on the TEO320 as outlined in Table 39 In pin out tables 40 and 41 the individual pins are colour coded according to pin type as in Table 39 type D D colour code description I O Unrestricted general purpose user I O pin Most pins can be paired together to form differential I Os Dual purpose pin used in some configuration modes during the configuration process and then usually available as a user I O after configuration If the pin is not used during configuration this pin behaves as an l O type pin See Xilinx UG332 Spartan 3 Generation Configuration User Guide for additional information on these signals VREFO provides a reference voltage input for certain I O standards See paragraph 6 9 Voltage Reference VREFO for additional information on this signal Either a user UO pin or an input to a specific clock buffer driver Packages have 16 global clock inputs that optionally clock the entire device See the Using Global Clock Resources chapter in UG331 Spartan 3 Generation FPGA User Guide for additional information on these signals Dedicated configuration pin two per device Not available as a user l O pin Every package has tw
63. l oscillator generates the configuration clock frequency The FPGA provides this clock on its CCLK output pin driving the PROM s Slave Clock input pin The FPGA begins configuring using its lowest frequency setting If so specified in the configuration bitstream the FPGA increases the CCLK frequency to the specified setting for the remainder of the configuration process The maximum frequency is specified using the ConfigRate bitstream generator option The maximum frequency supported by the FPGA configuration logic depends on the timing for the SPI Flash device For TEO320 SPI Flash PROM use ConfigRate 12 or lower This options are set graphically in Xilinx ISE Software Project Navigator by selecting the following Generate Programming File gt Process Properties gt Configuration Options gt Configuration Rate gt 12 or lower 57 82 www trenz electronic de TEO320 Series User Manual 12 Reference Design Summaries ISE 11 5 UM TEO320 v2 08 22 February 2012 12 Reference Design Summaries ISE 11 5 12 1 Reference Design Summary for Xilinx Spartan 3A DSP 1800 platgen p xc3sd1800afg676 4 lang vhdl lp x xxx projects EDK Release 11 5 platgen Xilinx EDK 11 5 Build EDK 155 70 Copyright c 1995 2009 Xilinx Inc All rights reserved nt Command Line Running post placement packing Design Summary Number of errors 0 Number of warnings 1272 Logic Utilization Number of Slice Flip Flops Number
64. ly option when resistor R17 not populated and R19 populated is equivalent to slide switch S2 permanently set to PON Figure 37 assembly option S2 PON 27 82 www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 Assembly option when resistor R17 populated and R19 not populated is equivalent to slide switch S2 permanently set to FX2 PON Figure 38 Assembly option S2 FX2 PON Any other assembly options of R17 and R19 are not allowed 6 8 3 DIP Slide Switches S5 A H TEO320 is provided with 8 user DIP slide switches as shown in Figure 39 SSA to SSH oe en ee O Pe woz u DEE EB am e les h e Oy ES LN LOr 00 IA Figure 39 DIP slide switches S5 A H Please note the 8 switch labels are on one side and the lt ON gt label is on the opposite side DIP slide switches S5 A H condition the value of some user signals as described in Table 15 S5 signal FPGA FPGA SES label name ball FPGA pin bank S5A 1 US1 F24 IO L54N 1 1 S5B 2 US2 E24 IO L56P_1 1 S5C 3 US3 E26 IO L60P_1 1 S5D 4 US4 D24 IO L61N 1 1 S5E 5 US5 D26 IO L60N_1 1 S5F 6 US6 D25 IO L61P 1 1 IO_L63P_1 S5G 7 US7 C26 AD 1 IO_L63N_1 S5H 8 US8 C25 A23 1 Table 15 S1X settings description 28 82 www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 A signal listed in Table 15 is
65. m or by any means including electronic storage and retrieval or translation into a foreign language without prior agreement and written consent from Trenz Electronic 20 4 Technology Licenses The hardware firmware software described in this document are furnished under a license and may be used modified copied only in accordance with the terms of such license 81 82 www trenz electronic de TEO320 Series User Manual 21 Document Change History UM TEO320 v2 08 22 February 2012 21 Document Change History ver date author description 1 00 2009 10 22 FDR Release 2 00 2009 12 16 FDR Added USB over B2B connector Added S1 description Added JTAG interface Added I2C bus description Added SPI bus description Added VREFO description Added LEDs buttons and switches description Added clock networks Added on board memories description Added mode select pins Added configuration options Improved Bootload ini file description Added YouTube reference to product support Added JM4 and JM5 pin out tables Added signal integrity considerations Improved system requirements Added glossary Introduced some other minor changes 2 01 2010 01 18 FDR Updated number of FPGA I O pins Removed TEO320 00B EVO1 2 02 2010 01 19 FDR Updated some software package paths Corrected pin name of JM5 signal RDWR_B ball Y12 SPI_ S and SPI_ C pins of connector JM5 were swapped in pin out and trace length tables
66. material contained in this document is provided as is and is subject to being changed at any time without notice Trenz Electronic does not warrant the accuracy and completeness of the materials in this document Further to the maximum extent permitted by applicable law Trenz Electronic disclaims all warranties either express or implied with regard to this document and any information contained herein including but not limited to the implied warranties of merchantability fitness for a particular purpose or non infringement of intellectual property Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing use or performance of this document or of any information contained herein 20 2 Limitation of Liability In no event will Trenz Electronic its suppliers or other third parties mentioned in this document be liable for any damages whatsoever including without limitation those resulting from lost profits lost data or business interruption arising out of the use inability to use or the results of use of this document any documents linked to this document or the materials or information contained at any or all such documents If your use of the materials or information from this document results in the need for servicing repair or correction of equipment or data you assume all costs thereof 20 3 Copyright Notice No part of this manual may be reproduced in any for
67. ning the FPGA configuration bitstream to the SPI serial Flash memory slave e FPGA Flash the FPGA master configures itself in Master SPI mode from the SPI serial Flash memory slave In case a the FPGA shall be turned off to release its shared SPI pins In case b the USB microcontroller shall three state Z high impedance its shared SPI pins 22 82 www trenz electronic de TE0320 Series User Manual 6 Inputs and Outputs UM TEO320 v2 08 22 February 2012 description usage EZ USB FX2LP FPGA B2B JM5 serial Flash FUT ol EZ USB Flash API master S2 FX2PON deselected slave FX2_PS_EN 0 FUT Inactive master FPGA Flash API SPI Z SPI_ S 1 deselected slave B2B JM5 Flash custom a S2 ron As o Slave FX2_PS_EN 0 eh Table 9 SPI bus modes for configuration The PROM file containing the FPGA configuration bitstream can be written to the SPI serial Flash memory slave also through the SPI pins of B2B connector JM5 attached device set to master mode In this case the FPGA shall be turned off or three stated to release its shared SPI pins and the USB microcontroller shall three state Z high impedance its shared SPI pins 6 5 2 SPI bus for operation A plurality of usage combinations of the SPI bus during operation is made available to the user as suggested in Table 10 6 6 LEDs description usage EZ USB FX2LP FPGA B2B JM5 serial Flash off
68. nts UM TEO320 v2 08 22 February 2012 Table 19 software requirements chart EDK Xilinx Embedded Development Kit XPS SDK XPS Xilinx Platform Studio for hardware engineers SDK Xilinx Software Development Kit for software engineers Xilinx ISE WebPACK is a free development environment featuring Xilinx ISE Foundation device limited Xilinx ISE Simulator ISim Xilinx PlanAhead TE0320 reference design requires Xilinx EDK Please visit the official Xilinx ISE Design Suite page for latest information about Xilinx design tools 9 5 Operating System Support 35 82 Xilinx ISE Design Suite is supported on both 32 bit and 64 bit versions of both Microsoft Windows and GNU Linux operating systems Please consult the Xilinx ISE Design Suite Product Table and Xilinx ISE Design Suite Software Matrix on the official Xilinx ISE Design Suite page for latest information about Xilinx ISE Design Suite operating system support TE0320 software package includes EZ USB FX2LP USB microcontroller device drivers for the 32 bit version of Microsoft Windows operating system TE0320 software package includes the Firmware Upgrade Tool for the 32 bit version of Microsoft Windows operating system www trenz electronic de TEO320 Series User Manual 10 Configuration UM TEO320 v2 08 22 February 2012 10 Configuration 36 82 JEWOS SARIS u AVIA99 9S jelleued anels B2B The Xilinx Spartan 3A DSP FPGA on the TE0320 c
69. o dedicated configuration pins These pins are powered by VCCAUX See Xilinx UG332 Spartan 3 Generation Configuration User Guide for additional information on these signals Control and status pins for the power saving Suspend mode SUSPEND is a dedicated pin and is powered by VCCAUX AWAKE is a Dual Purpose pin Unless Suspend mode is enabled in the application AWAKE is available as a user UC pin Dedicated JTAG pin 4 per device Not available as a user UO pin Every package has four dedicated JTAG pins These pins are powered by VCCAUX 73 82 www trenz electronic de TEO320 Series User Manual 18 B2B Connectors Pin Descriptions UM TEO320 v2 08 22 February 2012 Dedicated ground pin All must be connected TE Trenz Electronic specific pin type See the description of each pin in the user manual for additional information on the corresponding signals Table 39 types of pins on TE0320 74 82 www trenz electronic de TEO320 Series User Manual 18 B2B Connectors Pin Descriptions 18 3 B2B Connectors Pin Out 18 3 1 JM4 Pin Out sup ply type FPGA pin FPGA ball JM4 singal JM4 singal UM TEO320 v2 08 22 February 2012 FPGA ball FPGA pin type bank EEN 3 3V GN
70. of 4 input LUTs Logic Distribution Number of occupied Slices Number of Slices containing only related logic Number of Slices containing unrelated logic 6 442 out of 8 291 out of 7 304 out of platgen p xc3sd1800afg676 4 lang vhdl 1p 33 280 33 280 16 640 Ze 43 4 out of O out of 7 304 100 7 304 0 See NOTES below for an explanation of the effects of unrelated logic 33 280 Total Number of 4 input LUTs Number Number Number Two Number used as logic 6 213 used as a route thru 372 used for Dual Port RAMs 1 892 LUTs used per Dual Port RAM used as Shift registers 186 8 663 out of 26 The Slice Logic Distribution report is not meaningful if the design is over mapped for a non slice resource or if Placement fails Number of bonded IOBs 119 IOB Flip Flops 39 IOB Master Pads 2 IOB Slave Pads 2 Number of ODDR2s used 44 Number of DDR ALIGNMENT NONE 44 Number of DDR ALIGNMENT co 0 Number of DDR ALIGNMENT C1 0 Number of BUFGMUXs 5 Number of DCMs I Number of BSCANs 1 Number of DSP48As 3 Number of RAMB16BWERs 30 Number of BSCAN SPARTAN3As 1 Number of RPM macros 1 Average Fanout of Non Clock Nets Out out out out out out out of of of of of or of 519 24 84 84 1 22 20 123 100 Q O 355 100 58 82 www trenz electronic de TEO320 Series User Manual 12 Reference Design Summaries ISE 11 5 UM TE0320 v2 08
71. orresponding box has been USE EEPROM W FPGA FLASH selected USB Pic uploading 0 USB Firmware Upgrade Tool USB Device el ersion j The tool will then attempt to write the SPI Flash memory if the corresponding box has been W LSB EEPROM w FPGA FLASH sel ected FPG4 uploading 0 USB Fi Upgrade Tool X irmware Upgrade Tool X When the progress bar reaches 100 the Firmware upgrade successful following pop up message notifies the successful completion of the USB upgrade procedure If the FPGAPowerON bit in the Bootload ini file was set to 1 the FPGA will try to configure from SPI Flash memory straight after successful completion of the FUT utilization lf the FPGAPowerON bit in the Bootload ini file was set to 0 the FPGA keep powered off 54 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 10 3 Configuration Using Indirect SPI Configuration Mode Similar to the traditional configuration memories SPI serial Flash memories must be loaded with the configuration data SPI serial Flash memories have a single interface for programming but there are multiple methods to deliver the data to this interface This section discusses the hardware setup the PROM file generation flow and the software flow for ISP indirect in system programming of a Trenz Electronic TE0320 SPI serial Flash configuration PROM through the JTAG interface of a Xilinx Spart
72. peed data FPGA TX 0 Exit Resetting all FIFOs memory loser date vyer r iestiom PASSED Teansterted IZ0000 kB am 22 2658 5 35 861 MB s TE0320 DLL Example 1 0 Get number of modules Connect module No 0 Connect module No 1 Disconnect Get FX2 status Get FX2 version Get FPGA firmware version Get FX2 FIFO Status Reset FX2 FIFO Status Write high speed data Read high speed data Exit FPGA RX FPGA TX 1 2 3 4 5 6 7 8 Si W r 0 Drucken Sie eine beliebige Taste TEO320 Series User Manual 14 High Resolution Pictures UM TE0320 v2 08 22 February 2012 14 High Resolution Pictures a Figure 53 TEO320 high resolution top view b Figure 54 TEO320 high resolution bottom view c Figure 55 TEO320 angle view 64 82 www trenz electronic de TEO320 Series User Manual UM TEO320 v2 08 22 February 2012 14 High Resolution Pictures 14 1 Top View E00 m to o D a Wm fm eg gp wn u DO dl DI C77 2 Ga PD tite S KR GI AC sf 22 EE E i i wo o Ten 4 D e ei m O Le KR RT oz DE EE Sess Aum gaua IIA III Figure 53 TE0320 high resolution top view TEO320 Series User Manual www trenz electronic de 65 82 UM TEO320 v2 08 22 February 2012 14 High Resolution Pictures 14 2 Bottom View e KA 5 AAA eS RT e mm y OD
73. per Dxps_intc_0_wrapper Desktop DO dimb_cntlr_wrapper Dxps_npi_dma_0_wrapper y our e D roj ct fo d er an d Se e ct t h e b it st ream O dimb_wrapper xps timer D wapper VG ilmb_cntlr_wrapper fi e down 1 Oa d b 1 je Dilmb_wrapper system bit Eigene Dateien ed wrapper Press the open button in the bottom left corner O Imb_bram_wrapper mb_plb_wrapper of the current window CH microblaze_O_wrapper Arbeitsplatz Dproc_sys_reset_0_wrapper Netzwerkumgeb Dateiname download bi D ung Dateityp FPGA Bit Files bit D Abbrechen e Add Device ch Would vou like to add another device File Eo Your design likely consist of just one device file So deny the request by pressing the NO button Revision 0 49 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 B Add Device 2 gt You have completed the device File entry bp Click Ok to continue Just acknowledge the pup up message OK Select operations generate file or double click generate file fromthe iMPACT processes panel ISE iMPACT PROM File Formatter Xilinx Flash PROM Seles Sa File Edit view eier Output Debug Window Help De a KE Access eFUSE Registers M ZK IMPACT Flows Generate File EE Boundary Scan o Ea SlaveSerial Sel Direct SPI B SystemAce i B Create PROM File PROM File Formatter xc3sd1 5004
74. ply pin types Vecaux dedicated auxiliary power supply pins Vecinr dedicated internal core logic power supply pins Veco supplies power to the output buffers within the I O bank and sets the input threshold voltage for some I O standards TE0320 has the following power rails on board Vsup It is the main internal power rail irrespective of the external power supply It is supplied by either Vb2b or Vusb It manages power distribution conversion and supervision It is routed also to connector JM5 as a user power supply output s b2b It is the main power rail when the module is supplied from B2B connector JM usb It is the main power rail when the module is supplied from USB mini B connector J1 The maximum current than can be provided to J1 is determined by the USB power source 3 3V It is converted from Vsup by a step down DC DC converter and can provide up to 3 0 Ato the module and connectors JM4 and JM5 2 DV lt is converted from Vsup by a step down DC DC converter and can provide up to 3 0 Ato the DDR SDRAM and connectors JM5 1 2V It is converted from Vsup by a step down DC DC converter and can provide up to 3 0 Ato the Vecinr power supply pins and connectors JM5 VCCAUX 9 82 www trenz electronic de TEO320 Series User Manual 5 Power Supply UM TE0320 v2 08 22 February 2012 Here there are two assembly options a If inductor L2 is not populated and the low noise low drop out regulator U6 is po
75. pulated VCCAUX power rail is supplied with its nominal voltage of 2 5 V This is the recommended option for noise sensitive circuitry such as clocking and timing infrastructures Figure 8 assembly option for VCCAUX 2 5 V bottom view b if the ferrite bead L2 is populated and U6 is not populated the 3 3V power rail is simply filtered to generate VCCAUX power rail This is the recommended option for cost sensitive applications In this case b 1 ensure the noise level on power rail VOCUAX is suitable to your application b 2 avoid the connection of noise sources to power rail VOCUAX Figure 9 assembly option for VCCAUX 3 3 V bottom view Any other assembly combination of L2 and U6 is not allowed VCCCIOO VCCCIOO supplies Veco to FPGA bank 0 The following assembly options are possible a if both resistors R131 and R132 are not populated VCCCIOO power can be supplied through pins 30 and 44 of B2B connector JM4 HUHHHHH tee 10 82 www trenz electronic de TEO320 Series User Manual 5 Power Supply UM TE0320 v2 08 22 February 2012 Figure 10 assembly option for VCCAUX off bottom view Pins 30 and 44 of JM4 are power supply inputs in this case b if resistor R131 is not populated and R132 is populated VCCCIOO power rail is set to power rail 2 5V nominal voltage 2 5 V TT LS O AAA do Figure 11 assembly option for VCCAUX 2 5 V bottom view
76. r supply 5 V recommended System current consumption is design dependent USB buses able to supply only 100 mA are not supported See paragraph 5 2 Power Supply Sources for additional information on this topic 9 2 Hardware Design Requirements PUDC_B pull up during configuration active Low pin in TE0320 modules is hard wired high determining user l O pins to float before and during configuration Turning off pull up resistors in hot swap or hot insertion applications disables potential current paths to the I O power rail However external pull up or pull down resistors may be required on each individual O pin depending on the specific application 9 3 USB Requirements Recommended USB bus classes are 1 1 and 2 0 TE0320 can be connected to a USB bus through connector either J1 or JM4 4 6 SPI serial Flash memory can be written through the Firmware Upgrade Tool and the API Data communication over USB can be implemented through the API 9 4 JTAG Requirements TE0320 can be configured and debugged over JTAG through connector either J2 or JM4 74 76 78 80 See paragraph 6 3 JTAG Interface for additional information on this topic 9 4 1 Software Requirements Software requirements depend on the intended design goal design goal ISE WebPACK EDK HDL design e MicroBlaze design e e reference design e e 34 82 www trenz electronic de TEO320 Series User Manual 9 System Requireme
77. race Length 79 82 D A UM TEO320 v2 08 22 February 2012 1 2 3 4 5 6 7 8 9 10 IO_L30N 2 11 12 SPLD ABIS osycsie 5 13 15 49 IO LO2P2M2 Y7 M2 17 lO_L17P 2 IO_LO2N 2 23 IT Y12 RDWR_B 19 20 SPL S AA7 er 95 21 22 23 24 D4 Na Sa 14 D4 25 26 D5 ari2 Preta 13 D5 27 28 7 Gase AE18 D1 29 30 lO L36P_2 7 E AF18 D2 31 33 34 35 020 AA18 IO L47N 2 22 lO_L27P 2 13 a Y14 J5 1001 35 36 35 021 AB18 lO L47P 2 16 37 38 IO L28P 2 9 SC AF14 J5 l002 39 40 12 IO L29N 2 AC14 J5 IO03 41 42 J5 l024 AE25 10 L51P 2 26 43 44 45 46 J5 1025 AF25 lO L51P 2 34 21 IO LAON 2 AC19 J5 1006 47 48 22 IO L40P 2 AD19 Jon 49 50 51 52 35 028 AF3 IO LO6N 2 10 53 54 35 029 AE3 IO LO6P 2 11 55 56 27 IO L42N 2 U16 J5 IO10 57 58 30 IO L42P 2 V16 J5 1011 59 61 62 J5 1032 AD6 lO LO8N 2 21 63 64 J5 1033 AC6 IO LO8P 2 26 65 44 IO L44N 2 AD21 J5 I014 67 IO L25N 2 39 lO _L44P 2 AE21 J5 IO15 69 70 J5 1036 ei als 43 A IO L25P 2 73 74 J5 I037 AA13 eweg 40 44 O L46N 2 V17 35 018 75 45 IO L46P 2 W17 J5 1019 77 79 80 J5 1040 W13 IO
78. re 24 VREF GND TCK TDO TDI TMS Figure 24 JTAG connector J2 To connect your computer to JTAG connector J2 you typically need m a JTAG cable with standard 6 pin JTAG female header m a 2 54 mm pitch 1 x 6 pin gender changer header some examples of JTAG cable set are listed in Table 4 JTAG cable flying leads software gender changer Xilinx Platform Cable USB included Xilinx IMPACT 1x6 pin Digilent XUP USB JTAG Programming Cable XUP Fly Wire Assembly Xilinx IMPACT 1x6 pin www trenz electronic de TEO320 Series User Manual 6 Inputs and Outputs UM TE0320 v2 08 22 February 2012 Digilent JTAG USB Full Speed Module not needed Digilent Adept 20 1x6 pin Table 4 some examples of JTAG cable set Figure 25 shows a standard 6 pin JTAG female header in this case flying leads with a gender changer header Figure 26 shows how a JTAG cable in this case a Xilinx Platform Cable USB with flying leads and gender changer is connected to a TE0320 Ss T k AA Q O Figure 25 standard 6 pin JTAG female header with gender changer Figure 26 sample JTAG cable connection TE0320 side Figure 27 shows a recommended set up for TE0320 configuration and operation The USB cable provides for power supply and data communication channel The JTAG is ideal for quick configuration and effective debugging Figure 27 recommended TE0320 set up 19 82 www trenz electronic de TEO320 Series User Manual
79. recommended stand off distance bolts height is 7 mm TEO320 has 4 mounting holes one in each corner The module can be fixed by screwing M3 screws ISO 262 into a carrier board through those mounting holes TE0320 weighs about 25 g www trenz electronic de TEO320 Series User Manual 5 Power Supply UM TE0320 v2 08 22 February 2012 5 Power Supply 5 1 Power Supply Range The power supply range of TE0320 is 4 0 V to 7 0 V 5 2 Power Supply Sources TE0320 can be power supplied in two ways through USB connector J1 through B2B connector JM5 pins 1 to 4 The power supply source is determined by assembly option See Figure 5 an LZ USB 3 3V en E J1 VCCAUX R79 VUSB VSUP us H weg U7 nn BANK 0 3 3V R131 B2B Figure 5 Power supply options diagram lf resistors R9 and R11 are populated and R12 is not populated then TEO320 is power supplied through JM5 B2B connector Figure 6 assembly combination for power supply through JM5 lf resistors R9 and R11 are not populated and R12 is populated then TEO320 is power supplied through J1 USB bus 8 82 www trenz electronic de TEO320 Series User Manual 5 Power Supply UM TE0320 v2 08 22 February 2012 Figure 7 assembly combination for power supply through J1 Any other assembly combination of R9 R11 and R12 is not allowed 5 3 On Board Power Rails According to the Xilinx Spartan 3A DSP literature there are the following power Sup
80. rives the DONE pin High DriveDone or allows the DONE pin to float High using either an internal or external pull up resistor controlled by the DonePin bitstream generator option To have DONE LED D1 lit after successful FPGA configuration DriveDone and DonePin bitstream generator options for the DONE pin have to be set to have DONE actively driving its line See Figure 52 and Table 32 FPGA Active driver LVCMOS VCCAUX Startup Sequencer UG332_c2_01_120106a Figure 52 DriveDone and DonePin set to have DONE actively driving its line DriveDone defines whether the DONE pin is an active driver or an open drain output DonePin defines whether or not the DONE pin has an internal pull up resistor bitstream generator BitGen option Setting DriveDone Yes DonePin Pullnone Table 32 DriveDone and DonePin settings for having DONE actively driving its line see Xilinx UG332 Spartan 3 Generation Configuration User Guide paragraph DONE Pin for additional information on these signals This options are set graphically in Xilinx ISE Software Project Navigator by selecting the following Generate Programming File gt Process Properties gt Startup Options gt Drive Done Pin High gt check the box Generate Programming File gt Process Properties gt Configuration Options gt Configuration Pin Done gt float Xilinx ISE Project Navigator option setting Drive Done Pin High checked
81. t ipf Browse Select file new project Choose create a new project Press OK Cancel E Welcome to iMPACT Please select an action from the list below O Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File FY Select prepare a PROM file using Slave Serial mode Press OK Configure devices Cancel Select step 1 storage target Xilinx Flash PROM of the left panel and press the left green arrow 47 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 E PROM File Formatter Step 1 Select Storage Target Step 2 Add Storage Device s Step 3 Storage Device Type Non Yolatile FPGA Spartan3AN SPI Flash Configure Single FPGA Output File Configure MultiBoot FPGA Location BPI Flash Configure Single FPGA Configure MultiBoot FPGA Flash PROM File Property Configure from Paralleled PROMs File Format HEX Generic Parallel PROM L Enter Data z General File Detail Value Target FPGA Spartan3E e Checksum Fill Storage Device bits 312K value FF Output File Name Untitle Add Storage Device Remove Storage Device e e Name Unkkiod C xilinx Use Power of 2 for Start Addr Number of Bitstream 2 Bitstream 0 Start Address 0
82. t NOllce ea einen nun heran een 81 es UA Bien 81 STAGE En ee ee new 82 4 82 www trenz electronic de TEO320 Series User Manual 1 Block Diagram UM TE0320 v2 08 22 February 2012 1 Block Diagram y 245 12Mbit CR DDR SDRAM 32 USB MCU o B26 Cypress EZ USB JTAG id FX2LP J2 JTAG BE JIMS gege Spartan 3A DSP WW TE ser VO FEPROM 24LC120 on y X Be 4x EI BEIS Default Flash option Figure 3 TE0320 block diagram SFI Flash 42 64 120 Mbit system user 350 15004 466076 ALSSDS4004 4F6 50776 2 Module options FPGA options Module can be ordered with Spartan 3A DSP XC3SD1800A or XC3SD3400A chip Flash options Module can be ordered with 32 64 or 128 Mbit SPI Flash chip Temperature grade options Module can be ordered in commercial or in extended from 25 C to 85 C temperature grade 5 82 www trenz electronic de TEO320 Series User Manual 3 Specifications UM TE0320 v2 08 22 February 2012 3 Specifications FPGA Xilinx Spartan 3A DSP XC3SD1800A 4FGG676C XC3SD1800A 4FGG676l or XC3SD3400A 4FGG6 76C XC3SD3400A 4FGG676l Cypress EZ USB FX2LP USB microcontroller high speed USB peripheral controller CY7C68013A 56LT XC commercial grade or CY7C68013A 56LT XI industrial grade Numonyx M25P32 M25P64 M25P128 low voltage serial Flash memory with 75 MHz SPI bus interface 2 x 16 bit data bus 512 Mbit DDR SDRAM connected in parallel as a virtual
83. troller XTALIN and the FPGA as detailed in Table 17 signal FPGApin FPGA ball FPGA bank IO L28N 2 GCLK3 Table 17 24 MHz clock signal details 24MHZ1 AE14 2 7 3 Interface Clock IFCLK The IFCLK line synchronizes the communication between the EZ USB FX2LP USB microcontroller and the FPGA as detailed in Table 18 signal FPGA pin FPGA ball FPGA bank lO_L31N_1 IFCLK TRDY1 P25 1 RHCLK3 Table 18 Interface clock signal details 7 4 Digital Clock Manager DCM The DCMs of the FPGA can be used to synthesize arbitrary clock frequencies from any on board clock network differential clock input pair or single ended clock input For further reference please read Xilinx DS485 Digital Clock Manager DCM Module and the DCM chapter in Xilinx UG331 Spartan 3 Generation FPGA User Guide 7 5 Watchdog TE0320 has a watchdog timer that is periodically triggered by a positive or negative transition of the watchdog input WDI signal When the supervising system fails to retrigger the watchdog circuit within the time out interval min 1 1 30 82 www trenz electronic de TEO320 Series User Manual 7 Timing 31 82 UM TEO320 v2 08 22 February 2012 s typ 1 6 s max 2 3 s the watchdog output becomes active and asserts the master reset MR signal This event also reinitializes the watchdog timer If resistors R135 and R165 are not populated the watchdog is disabled lf resistors R135 and R165 are populated the
84. watchdog can be enabled In this case there are still two options To enable the watchdog after module power up drive the WDI signal to generate a transition no matter if positive or negative To keep the watchdog disabled set the WDI FPGA signal output to high impedance One way to reach this goal is to leave FPGA pin V24 FPGA signal IO_L19P_1 undeclared in the user constraints file UCF and set the Xilinx Project Navigator options as follows project properties gt configuration options gt unused IOB Pins gt float ES Process Properties Configuration Options Category General Options Configuration Options Startup Options Readback Options Encryption Options Configuration Clk Configuration Pins Pull Up Property Name Value Configuration Rate 4 EA Configuration Pin MO Configuration Pin Mi Configuration Pin M2 Configuration Pin Program aada Configuration Pin Done Configuration Pin Init lt Configuration Pin CS Configuration Pin Din OS Configuration Pin Busy Configuration Pin Rdwr JTAG Pin TCK JTAG Pin TDI JTAG Pin TDO JTAG Pin TMS Unused IOB Pins Pull Down UserlD Code 8 Digit Hexadecimal DCI Update Mode Pull Up Float Property display level Advanced v lt lt IKII IK Figure 40 configuration option in Xilinx ISE Project Navigator www trenz electronic de TE0320 Series User Manual 7 Timing
85. zwerkadapter g s Prozessoren s Speichervolumes Systemger te gt Tastaturen E USB Controller 74 200 DEWESoft USE Device 0 AHS E E El LPL Figure 50 device manager after successful installation of the specific device driver Now the EZ USB FX2LP USB microcontroller can be controlled from a computer by the DEWESoft API 10 2 4 FWU file generation In order to generate the FWU file you shall a generate a bit stream file from your Xilinx EDK design b generate a PROM file from the bit stream file c generate a FWU file from the PROM file 10 2 4 1 bit stream file from your Xilinx EDK design In order to generate a bit bit stream file from your Xilinx EDK design you shall 46 82 www trenz electronic de TEO320 Series User Manual 10 Configuration UM TE0320 v2 08 22 February 2012 open your system xmp project file with Xilinx EDK select project clean all generated files optional select hardware generate bitstream This will generate the bit stream file download bit inthe implementation folder of your project folder 10 2 4 2 PROM file from the bit stream file In order to generate a bin PROM file from the bit stream file download bit Start Xilinx IMPACT The following example shows the case of Xilinx IMPACT 11 3 E New iMPACT Project I want to load most recent project C Load most recent project file when iMPACT starts create a new project ipf defaul

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