USER MANUAL SED 1520 GRAPHIC CONTROLLER SED 1520
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1. o ReadmodiywiteON pend qojr o s i v Po faa o Recm ywieor Ree gjojs o s i s Jofo o v sowers USER MANUAL SED 1520 ELECTRONIC ASSEMBLY Command Description Table 3 is the command table The SED 1520 series identifies a data bus using a combination of AO and R W RD or WR signals As the MPU translates a command in the internal timing only independent from the external clock its speed is very high The busy check is usually not required Display ON OFF Ao ojrjo rjoyj op tg vj 1 AEAFH This command turns the display on and off e 1 Display ON D 0 Display OFF Display Start Line This command specifies the line address shown in Figure 3 and indicates the display line that corresponds to COMO The display area begins at the specified line address and continues in the line address increment direction This area having the number of lines of the specified display duty is displayed If the line address is changed dynamically by this command the vertical smooth scrolling and paging can be used efan iit o for fon obo foe fo oe 1 sofa ata a This command loads the display start line register Line Address A4 A3 A2 A1 Ao COH to DFH See Figure 2 Set Page Address This command specifies the page address that corresponds to the low address of the display data RAM when it is accesse2. Display area USER MANUAL SED 1520 ADC Start line Example Response Common output O Q O COM 1 COM 3 COM 4 COM 6 COM 7 COM COM 9 COM 10 COM 11 COM 1 COM 15 COM 16 COM 17 COM 1 COM 1 COM 2 COM 21 COM 22 eee lt lt lt cO PIDIN COM 24 COM 25 COM 26 COM 27 COM 28 COM 29 COM 30 SEU A Figure 2 Display Data RAM Addressing USER MANUAL SED 1520 ELECTRONIC ASSEMBLY COMMANDS Summary Command A0 RD WR Display OWOFF DEDE m Turns display on or off 1 ON 0 OFF Display start line Ong Display start address 0 to 31 p RAM line corresponding to top line of displa register Set column EE Column address 0 to 79 Sets display RAM column address in segment address column address register Reads the following status BUSY 1 Busy 0 Ready ADC 1 CW output Read status Busy ADC ON OFF 0 CCW output ON OFF 1 Display off 0 Display on RESET 1 Being reset 0 Normal Write display data nnn Write we Writes data from data bus into display RAM Read Read dpa L i m ead data n data from RN RAM onto data Exc L Ae e e Te ramen oa Statis drive 0 Selects static driving operation ON OFF 1 Static drive 0 Normal driving DEM SE 1 1 32 0 1 16 ReadModifywrte o 1 o 1
3. bus is fetched at the rising edge of WR signal 3 LCD Drive Circuit Signals Input Effective for an external clock operation model only This is a display data latch signal to count up the line counter and common counter at each signal falling and rising edges If the system has a built in oscillator this is used as an output pin of the oscillator amp and an Rf oscillator resistor is con nected to it USER MANUAL SED 1520 ELECTRONIC ASSEMBLY BLOCK DESCRIPTION System Bus MPU interface 1 Selecting an interface type The SED1520 series transfers data via 8 bit bidirec tional data buses DO to D7 As its Reset pin has the MPU interface select function the 80 series MPU or the 68 series MPU can directly be connected to the MPU bus by the selection of high or low RES signal RES signal input level MPU type Active high Data transfer The SED1520 and SED1521 drivers use the AO E or RD and R W or WR signals to transfer data between the system MPU and internal registers The combina tions used are given in the table blow In order to match the timing requirements of the MPU with those of the display data RAM and control registers all data is latched into and out of the driver This introduces a one cycle delay between a read request for data and the data arriving For example when the MPU A0 RW RD _ 1 1 O O o1 0 j 1 1 1 0 0 0 1 Reset Circuit Detects a risin
4. current to 30 pA Senter V5 5 0V 5 0 7 5 SEGO to 79 COMO to 15 V5 3 5 V 90 0 See note 11 a Tam D for 2kHz 20 50 Voo R 1MO 95 150 pA Seenote 12 for 18kHz 50 100 138 14 1 During display 38500 4 5 D During access tcyc 200 kHz a oe Ipo 2 Vss 3V EN pA See note 8 During access tcyc 200 EB Input pin capacitance Ta 25deg C 1MHz 20 000 Rt 1 0 2 Vss 5 0 V 1 0 MQ 42 See note 9 VSS 3 0 V RES o Notes 1 Operation over the specified voltage range is guaranteed except where the supply voltage changes suddenly during CPU access _ 2 0 DO to D7 E or RD R W or WR and CS 3 CL FR M S and RES 4 D0 to D7 5 FR _ _ 6 AO E or RD R W or WR CS CL M S and RES 7 When DO to D7 and FR are high impedance 8 During continual write acess at a frequency of tcyc Current consumption during access is effectively proportional to the access frequency 9 See figure below for details 10 See figure below for details 11 Fora voltage differential of 0 1 V between input V1 V4 and output COM SEG pins All voltages within specified operating voltage range 12 SED1520 a and SED1521 A and SED1522 a only Does not include transient currents due to stray and panel capacitances 13 SEDI520 0 and SED1522 0 only Does not include transi
5. divider circuit the current passing through this resistor must be cut by the Power Save signal SED1520 V3 SED1522 Power Save signal VSSH If the LCD drive power is generated by resistance division the resistance and capacitance are determined by the LCD panel size After the panel size has been determined reduce the resistance to the level where the display quality is not affected and reduce the power consumption using the divider resistor 11 USER MANUAL SED 1520 ELECTRONIC ASSEMBLY SPECIFICATIONS Absolute Maximum Ratings Parameter Symbol Unit m 29 mW Notes 1 All voltages are specified relative to VDD 0 V 2 The following relation must be always hold VDD 2 V 2 V22 V3 gt V4 gt V5 3 Exceeding the absolute maximum ratings may Cause permanent damage to the device Functional operation under these conditions is not implied 4 Moisture resistance of flat packages can be reduced by the soldering process so care should be taken to avoid thermally stressing the package during board assembly Electrical Specifications DC Characteristics Ta 20 to 75 deg C VDD 0 V unless stated otherwise Parameter Condition _ ug T op Tas um voltage 1 Vss V Vss A e v n 80 See note 10 Allowable V V2 Toews vo V v3 va 04x5 Ve
6. setup time Address hold time Data setup time Data hold time Output disable time 100 pF Enable 200 ms tEw E pulse width 160 ms Bseandfalume tu T 5 n Notes 1 tCYC6 is the cycle time of CS E H not the cycle time of E 15 TECHNISCHE DATEN USER MANUAL SED 1520 APPLICATION NOTES MPU Interface Configuration 80 Family MPU n e Jun 91 HIGH LEVEL Grafikkontroller fur Displays mit SED 1520 F R LC GRAFIKDISPLAYS 122x32 120x32 MIT SED 1520 Q A KEINE TIMINGPROBLEME MEHR BEI SCHNELLEM BUSSYSTEM Vor des se PROGRAMMIERUNG UBER HOCHSPRACHENAHNLICHE BEFEHLE jen one GERADE PUNKT BEREICH UND ODER EXOR BARGRAPH 3 VERSCHIEDENE FONTS INTEGRIERT ZOOM FUNKTION 2 3 UND 4 FACH ALLER FONTS 4 16 FREI DEFINIERBARE ZEICHEN JE NACH GROBE TEXT UND GRAFIK MISCHEN ANSTEUERUNG UBER RS 232 CMOS PEGEL DIREKTER ANSCHLUB VON ICL232 O A MOGLICH BAUDRATE PROGRAMMIERBAR VON 150 BIS 115 200 BAUD BELASTET NICHT DAS PROZESSORSYSTEM NUR 4 EXTERNE BAUTEILE ERFORDERLICH 8 DIGITALE l O S ZUR FREIEN VERWENDUNG HARDWARE CODIERUNG VON BIS ZU 4 ADRESSEN BESTELLBEZEICHNUNG HIGH LEVEL GRAFIKKONTROLLER 122x32 F R SED1520 EA 1C1520 PGH KERAMIKRESONATOR SMD 7 37MHz 3 PINS INKL C s EA KERS7M37 C PASSENDES GRAFIKDISPLAY MIT SED1520 122x32 E
7. 198 USER MANUAL SED 1520 GRAPHIC CONTROLLER SED 1520 ine counter V1 V2 V3 V4 V5 to COM s z E SEGo to SEGeo uq 09S2 Kejdsig FEATURES FAST 8 BIT MPU INTERFACE COMPATIBLE WITH 80 AND 68 FAMILY MICROCOMPUTERS MANY COMMAND SET LOW POWER 30uW AT 2KHZ EXTERNAL CLOCK WIDE RANGE OF SUPPLY VOLTAGES VDD VSS 2 4 TO 7 0 V VDD VEE 3 5 TO 13 0 V LOW POWER CMOS INTELLIGENT ADD ON CONTROLLER BOARD AVAILABLE COMPLETE TEXTMODE WITH 2 CHARACTER SETS CLEAR AREA SET LINE ETC EA 9720 COMPLETE GRAPHIC MODULES AVAILABLE E G EA P122 5NLED 122x32 DOTS ELECTRONIC LOCHHAMER SCHLAG 17 D 82166 GRAFELFING ASSEMBLY TELEFON 089 8541991 TELEFAX 089 85417 21 USER MANUAL SED 1520 ELECTRONIC ASSEMBLY PIN DESCRIPTION 1 Power Pins Connected to the 5Vdc power Common to the Vcc MPU power pin 0 Vdc pin connected to the system ground V1 V2 V3 Va Vs Multi level power supplies for LCD driving The voltage determined for each liquid crystal cell is divided by resistance or it is converted in impedance by the op amp and supplied These voltages must satisfy the following Voo gt Vi gt V2 gt V3 gt V4 gt Vs 2 System Bus Connection Pins D7 to D0 Three state I O The 8 bit bidirectional data buses to be connected to the 8 or 16 bit standard MPU data buses A0 Input Usually connec
8. A P122 NLED ELECTRONIC LOCHHAMER SCHLAG 17 D 82166 GRAFELFING TELEFON 089 8541991 TELEFAX 089 854 17 21 ASSEMBLY
9. d ON OFF 1 Display OFF ON OFF 0 Display ON The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode RESET 1 Currently executing reset command RESET 0 Normal operation Write Display Data vs os os oe or o Write data Writes 8 bits of data into the display data RAM at a location specified by the contents of the column address and page address registers and then increments the column address register by one USER MANUAL SED 1520 ELECTRONIC ASSEMBLY Read Display Data R W Ao WR D7 Da Reads 8 bits of data from the data I O latch updates the contents of the I O latch with display data from the display data RAM location specified by the contents of the column address and page address registers and then increments the column address register After loading a new address into the column address register one dummy read is required before valid data is obtained Select ADC or o os o os o Ao WR D7 D3 D2 D1 oft tots fot This command selects the relationship between display data RAM column addresses and segment drivers 1 SEGO lt column address 4FH inverted D 0 SEGO lt column address normal This command is provided to reduce restrictions on the placement of driver ICs and routin g of traces during printed circuit board design See Figure 2 for a table of s
10. d by the MPU Any bit of the display data RAM can be accessed when its page address and column address are specified The display status is not changed even when the page address is changed o osos tits ole This command loads the page address register B8H to BBH See Figure 2 USER MANUAL SED 1520 ELECTRONIC ASSEMBLY Set Column Address This command specifies a column address of the display data RAM When the display data RAM is accessed by the MPU continuously the column address is incremented by 1 each time it is accessed from the set address Therefore the MPU can access to data continuously The column address stops to be incremented at address 80 and the page address is not changed continuously PIFIFIFIFS Read Status WH ov o os oe os oe 1 BUSY ADC DNOFF R us the command I O register A0 0 yields system status information The busy bit indicates whether the driver will accept a command or not Busy 1 The driver is currently executing a command or is resetting No new command will be accepted Busy 0 The driver will accept a new command The ADC bit indicates the way column addresses are assigned to segment drivers ADC 1 Normal Column address n segment driver n ADC 0 Inverted Column address 79 u segment driver u The ON OFF bit indicates the current status of the display It is the inverse of the polarity of the display ON OFF comman
11. egister are copied into the line count register at the start of every frame that is on each edge of FR The line count register is incremented by the CL clock once for every display line thus generating a pointer to the current line of data in display data RAM being transferred to the segment driver circuits Bus Buffer Delay Column Address Counter The column address counter is a 7 bit presettable counter that supplies the column address for MPU access to the display data RAM See Figure 2 The counter is incremented by one every time the driver receives a Read or Write Display Datacommand Addresses above 50H are invalid and the counter will not increment past this value The contents of the column address counterare set with the Set Column Address command Page Register The page resiter is a 2 bit register that supplies the page address for MPU access to the display data RAM See Figure 2 The contents of the page register are set by the Set Page Register command Display Data RAM The display data RAM stores the LCD display data ona bit per pixel basis The relation ship between display data display address and the display is shown in Figure 2 Do 44d _ _ EE i M ttt EE Foz Ht tt 03 D1 D2 0 0 tot Da aao Page 0 04 Ds G4 05 Ds 44 06 Dr 07 Di 44 0 09 D OA Os Page 1 D4 Ds
12. egments and column addresses for the two values of D Static Drive ON OFF Forces display on and all common outputs to be selected D 1 Static drive on D 0 Static drive off Select Duty c po o o amc This command sets the duty cycle of the LCD drive and is only valid for the SEDI520F and SED1522F It is invalid for the SEDI521F which performs passive operation The duty cycle of the SED1521F is determined by the externally generated FR signal SED1520 SED1522 D i 1 32 duty cycle 1 16 duty cycle D 0 1 16 duty cycle 1 8 duty cycle When using the SED1520F0A SED1522F0A having a built in oscillator and the SED1521FOA continuously set the duty as follows LL SED S21 Fo 1 32 1 16 1 32 1 16 USER MANUAL SED 1520 ELECTRONIC ASSEMBLY Read Modify Write Le m or oe os o os o o oo pots tots lem This command defeats column address register auto increment after data reads The current conetents of the column address register are saved This mode remains active until an End command is received Operation sequence during cursor display When the End command is entered the column address is returned to the one used during input of Read Modify Write command This function can reduce the load of MPU when data change is repeated at a specific display area such as cursor blinking Any command other than Data Read or Write can be used in the Read Modify Write m
13. ent currents due to stray and panel capacitances 14 SEDI521 0 only Does not include transient currents due to stray and panel capacitances 15 tR Reset time represents the time from the RES signal edge to the completion of reset of the internal circuit Therefore the SED1520 series enters the normal operation status after this tR 13 USER MANUAL SED 1220 NIC ASSEMBLY AC Characteristics e MPU Bus Read Write I 80 family MPU WR RD DO to D7 WRITE D0 to D READ we u 15 Address setuptime tawe 20 L 0 ase time a ns W8 control pulsewidth Data setuptime ws 80 m Dataholdtime wm C C C 19 RD access time c 30 m L 100 pF 10 6 ns o oo T 5 Rise and fall time VSS 2 7 to 4 5 V Ta 20 to 75 C Address hold time ns s Fr rm a _ _ E _ 0 5 System cycle time oe WR RD 400 _ m _ 20 Data hold ime 2 L 5 soup RD access ime L 3 Output disable time Miseandfalume tu 7 USER MANUAL SED 1520 ELECTRONIC ASSEMBLY MPU Bus Read Write II 68 family MPU e X WRITE DO to D gt READ i ooo Ta 20 to 75 deg C Vss 5 V 10 unless stated otherwise pulsewidth System cycle time Address
14. g or falling edge of an RES input and initializes the MPU during power on nitialization status Display is off Display start line register is set to line 1 Static drive is turned off Column address counter is set to address O Page address register is set to page 3 1 32 SED1520 or 1 16 duty SED1522 is selected 7 Forward ADC is selected ADC command DO is 1 and ADC status flag is 1 8 Read modify write is turned off SA gt 25 ao 68 MPU 80 MPU 0 j Write display data level after reset see Table 1 When the CS signal is high the SED1520 series is disconnected from the MPU bus and set to stand by However the reset signal is entered regardless of the internal setup status executes a read cycle to access display RAM the current contents of the latch are placed on the system data bus while the desired contents of the display RAM are moved into the latch This means that a dummy read cycle has to be executed at the start of every series of reads See Figure 1 No dummy cycle is required at the start of a series of writes as data is transferred automatically from the input latch to its destination Read display data Read status Write to internal register command The input signal level at RES pin is sensed and an MPU interface mode is selected as shown on Table 1 For the 80 series MPU the RES input is passed through the inverter and the active high reset signal m
15. ode However the Column Address Set command cannot be used Set Page Address Set Column Address Read Modify Write Dummy Read Read Data Write Data Completed es w ov EREBFREBEBENERL This command cancels read modify write mode and restores the contents of the column address register to their value prior to the receipt of the Read Modify Write command Return USER MANUAL SED 1520 ELECTRONIC ASSEMBLY Reset jos os os os oe or oo 1 15 5 1 o This command clears the display start line register and set page address register to 3 page It does not affect the contents of the display data RAM When the power supply is turned on a Reset signal is entered in the RES pin The Reset command cannot be used instead of this Reset signal Power Save Combination command The Power Save mode is selected if the static drive is turned ON when the display is OFF The current consumption can be reduced to almost the static current level In the Power Save mode a The LCD drive is stopped and the segment and common driver outputs are set to the VDD level b The external oscillation clock input is inhibited and the OSC2 is set to the floating mode c The display and operation modes are kept The Power Save mode is released when the display is tumed ON or when the static drive is turned OFF If the LCD drive voltage is supplied from an external resistance
16. r VD High level input voltage vc o2xvs Vo 02xVss 02xVss Vo y wr Ns Vss 08 Low level input voltage Vc 08xVss VIT Vess 3V Vs 85xVss Vss 0 8xVss ere eee 3 0 mA Vss 24 OSC2 2 0 mA Vss24 V Sec note 485 High level output voltage 0862 10H 120 p 2xvss gneve output voltage Vor vss 3V__ lH 2mAlo2xvss See note 4 45 Vouc Vss 3V lon 2mA 02xVvss v Oso i Vss 3V lon 50pAl0 2xVss continued USER MANUAL SED 1520 ELECTRONIC ASSEMBLY DC Characteristics Cont d 20 to 75 deg C VDD 0 V unless stated otherwise m See note 4 amp 5 OSC 2 LCD driver ON resistance Static current dissipation Ta 25 deg C During display V5 5 0 V Voo See note 12 amp 13 Dynamic current dissipation pA Oscillation frequency fosc Vor 3 04 OSC Naci jlo 20mA vss04 V See note 4 amp 5 09 2 oeoa Tass Vor Vss 3V 2 08xVss Vaci Vss 3V llo 2m v Voca Vss 3V 50 08155 u 5 10 Se Output leakage
17. ted to the low order bit of the MPU address bus and used to identify the data or a command A0 0 D0 to D7 are display control data A0 1 DO to D7 are display data Input When the RES signal goes J the 68 series MPU is initialized and when it goes L the 80 series MPU is initialized The system is reset during edge sense of the RES signal The interface type to the 68 series or 80 series MPU is selected by the level input as follows High level 68 series MPU interface Low level 80 series MPU interface Input Active low Effective for an external clock operation model only An address bus signal is usually decoded by use of chip select signal and it is entered If the system has a built in oscillator this is used as an input pin to the oscillator amp and an Rf oscillator resistor is connected to it In such case the RD WR and E signals must be ORed with the CS signals and entered e f th series MPU i nn Input Active high Used as an enable clock input of the 68 series MPU If the 80 series MPU is connected Input Active low The RD signal of the 80 series MPU is entered in this pin When this signal is kept low the SED1520 data bus is in the output status If the 68 series MPU is connected Input Used as an input pin of read control signals if R W is high or write control signals if low If th series MPU i nn Input Active low The WR signal of the 80 series MPU is entered in this pin A signal on the data
18. ust be entered For the 68 series MPU the active low reset signal must be entered As shown for the MPU interface reference example the RES pin must be connected to the Reset pin and reset at the same time as the MPU initialization If the MPU is not initialized by the use of RES pin during power on an unrecoverable MPU failure may occur When the Reset command is issued initialization items 2 and 5 above are executed Mes N timing hold READ USER MANUAL SED 1520 ELECTRONIC ASSEMBLY MPU DATA gt CTD Address set at N E m HD Internal timing Column Dummy read Data read Data read at N atN 1 N 1 N 2 gt Bus 5 hold CTE EE GA Figure 1 Busy flag When the Busy flag is logical 1 the SED1520 series is executing its internal operations Any command other than Status Read is rejected during this time The Busy flag is output at pin D7 by the Status Read command If an appropriate cycle time tcyc is given this flag needs not be checked at the beginning of each command and therefore the MPU processing capacity can greatly be enhanced Display Start Line and Line Count Registers The contents of this register form a pointer to a line of data in display data RAM corresponding to the first line of the display COMO and are set by the Display Start Line command See section 3 The contents of the display start line r
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