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User's Manual Revision 3.2.1

1. Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OxB4 DMS 1 0 res RF1L F1F res 1 5 0 R 0x0 R 0x0 RO R 0 R 0x0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E J 0 0 0 0 RO R 0x0 R Read n value after reset Table 33 Rx FIFO 1 Status address OxB4 Bits 31 30 DMS 1 0 Debug Message Status 00 Idle state wait for reception of debug messages DMA request is cleared 01 Debug message A received 10 Debug messages A B received 11 Debug messages A B C received request is set 34 16 03 2015 BOSCH Revision 3 2 1 M CAN Bit 25 RF1L Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR RF1L When IR RF1L is reset this bit is also reset No Rx FIFO 1 message lost 1 Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note Overwriting the oldest message when RXF1C F10OM 1 will not set this flag e II Bit 24 F1F Rx FIFO 1 Full 0 Rx FIFO 1 not full 1 RxFIFO 1 full Bit 21 16 F1PI 5 0 Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range O to 63 Bit 13 8 F1GI 5 0 Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63 Bit 6 0 F1FL 6 0 Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64 2 3 33 Rx FIFO 1 Acknowledge RXF1A Bits 31 30 29 28 27 2 2 24 23 22 21 20 19 18 17 16 OxB8 res R 0x0 Bits 15 14 13 12 11 10 9 8 7 86 5 4 3 2 1 0 res F1AI
2. Table 55 Rx Buffer FIFO Element Size 16 03 2015 67 M CAN Revision 3 2 1 3 4 2 1 Rx FIFO Blocking Mode The Rx FIFO blocking mode is configured by RXFnC FnOM 0 This is the default operation mode for the Rx FIFOs When an Rx FIFO full condition is reached RXFnS FnPI RXFnS FnGl no further messages are written to the corresponding Rx FIFO until at least one message has been read out and the Rx FIFO Get Index has been incremented An Rx FIFO full condition is signalled by RXFnS FnF 1 In addition interrupt flag IR RFnF is set In case a message is received while the corresponding Rx FIFO is full this message is discarded and the message lost condition is signalled by RXFnS RFnL 1 In addition interrupt flag IR RFnL is set 3 4 22 Rx FIFO Overwrite Mode Figure 9 68 The Rx FIFO overwrite mode is configured by RXFnC FnOM 1 When an Rx FIFO full condition RXFnS FnPI RXFnS FnGl is signalled by RXFnS FnF 1 the next message accepted for the FIFO will overwrite the oldest FIFO message Put and get index are both incremented by one When an Rx FIFO is operated in overwrite mode and an Rx FIFO full condition is signalled reading of the Rx FIFO elements should start at least at get index 1 The reason for that is that it might happen that a received message is written to the Message RAM put index while the CPU is reading from the Message RAM get index In this case inconsisten
3. BOSCH M CAN 2 3 13 Bits 0x40 Bits Revision 3 2 1 Error Counter Register ECR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res CEL 7 0 R 0x0 X 0x0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RP REC 6 0 TEC 7 0 R 0 R 0x0 R 0x0 R Read X Reset on read n value after reset Table 14 Error Counter Register address 0x40 16 Bits 23 16 CEL 7 0 CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented It is reset by read access to CEL The counter stops at OxFF the next increment of TEC or REC sets interrupt flag IR ELO Bit 15 RP Receive Error Passive 0 The Receive Error Counter is below the error passive level of 128 12 The Receive Error Counter has reached the error passive level of 128 Bits 14 8 REC 6 0 Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127 Bits 7 0 TEC 7 0 Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255 Note When CCCR ASM is set the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected but CEL is still incremented 16 03 2015 Revision 3 2 1 M CAN 2 3 14 Protocol Status Register PSR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x44 res TDCV
4. 15 2 3 12 Timeout Counter Value 15 2 313 Error Counter Register ECH 16 2 3 14 Protocol Status Register PSR 17 2 3 15 Transmitter Delay Compensation Register TDCR 19 2 3 16 Interrupt Register RH 20 2 9 17 Interrupt Enable Aar tee 23 2 3 18 Interrupt Line Select i 25 2 3 19 Interrupt Line Enable LEI 26 2 3 20 Global Filter Configuration 2 27 2 3 21 Standard ID Filter Configuration SIDFC 28 2 3 22 Extended ID Filter Configuration XIDFC 28 2 8 23 Extended ID AND Mask RR III 29 2 3 24 High Priority Message Status HPMS 29 2 3 25 New Data 1 NDAT1 ssssesseeee waqa 30 2 3 26 NewData2 NDAT2 eae 30 2 8 27 Rx FIFO 0 Configuration RXFOC 2 ee 31 2 3 28 Rx FIFOO Status RXFOS eae 32 2 3 29 Rx FIFO 0 Acknowledge RXFOA 33 2 3 30 Rx Buffer Configuration RKBC 33 2 8 31 Rx FIFO 1 Configuration RKF1C 2 ee 34 2 8 32 Rx FIFO 1 Status RSEIG eae 34 2 3 33 Rx FIFO 1 Acknowledge RXF1A 35 2 3 34 Rx Buffer FIFO Element Size Configuration RXESC
5. Debug on CAN support M CAN Revision 3 2 1 16 03 2015 1 M CAN Revision 3 2 1 1 2 Block Diagram m can tx m can rx Host IF 8 16 32 Memory IF 32 CAN Clock Domain Host Clock Domain Figure 1 M CAN Block Diagram CAN Core CAN Protocol Controller and Rx Tx Shift Register Handles all ISO 11898 1 protocol functions Supports 11 bit and 29 bit identifiers Sync Synchronizes signals from the Host clock domain to the CAN clock domain and vice versa CIk Synchronizes reset signal to the Host clock domain and to the CAN clock domain Cfg amp Ctrl CAN Core related configuration and control bits Interrupt amp Timestamp Interrupt control and 16 bit CAN bit time counter for receive and transmit timestamp generation An externally generated 16 bit vector may substitute the integrated 16 bit CAN bit time counter for receive and transmit timestamp generation Tx Handler Controls the message transfer from the external Message RAM to the CAN Core A maximum of 32 Tx Buffers can be configured for transmission Tx buffers can be used as dedicated Tx Buffers as Tx FIFO part of a Tx Queue or as a combination of them A Tx Event FIFO stores Tx timestamps together with the corresponding Message ID Transmit cancellation is also supported 2 16 03 2015 BOSCH Revision 3 2 1 M CAN Rx Handler Controls the transfer of received messages from the CAN Core to the external Message RAM The Rx Handler supports two Receive FIFOs each o
6. 001 110 Second ID of extended ID filter element 2 EFEC 111 Filter for Rx Buffers or for debug messages EFID2 10 9 decides whether the received message is stored into an Rx Buffer or treated as message A B or C of the debug message sequence 00 Store message into an Rx Buffer 01 Debug Message A 10 Debug Message B 11 Debug Message C EFID2 8 6 is used to control the filter event pins m_can_fe 2 0 at the Extension Interface A one at the respective bit position enables generation of a pulse at the related filter event pin with the duration of one m can hclk period in case the filter matches EFID2 5 0 defines the offset to the Rx Buffer Start Address RXBC RBSA for storage of a matching message 54 16 03 2015 BOSCH Chapter 3 3 Functional Description 3 1 Operating Modes 3 1 1 Software Initialization Software initialization is started by setting bit CCCR INIT either by software or by a hardware reset when an uncorrected bit error was detected in the Message RAM or by going Bus_Off While CCCR INIT is set message transfer from and to the CAN bus is stopped the status of the CAN bus output m_can_tx is recessive HIGH The counters of the Error Management Logic EML are unchanged Setting CCCR INIT does not change any configuration register Resetting CCCR INIT finishes the software initialization Afterwards the Bit Stream Processor BSP synchronizes itself to the data transfer on the CAN bus by waiting
7. 10 Bits 1 0 TSS 1 0 Timestamp Select 00 Timestamp counter value always 0x0000 01 2 Timestamp counter value incremented according to TCP 10 External timestamp counter value used 11 Same as 00 2 3 10 Timestamp Counter Value TSCV Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x24 res R 0x0 Bits 15 14 13 12 11 10 9 8 7 86 5 4 3 2 1 0 TSC 15 0 RC 0x0 R Read C Clear on write n Value after reset Table 11 Timestamp Counter Value address 0x24 Bit 15 0 TSC 15 0 Timestamp Counter The internal external Timestamp Counter value is captured on start of frame both Rx and Tx When TSCC TSS 01 the Timestamp Counter is incremented in multiples of CAN bit times 1 16 depending on the configuration of TSCC TCP A wrap around sets interrupt flag IR TSW Write access resets the counter to zero When TSCC TSS 10 TSC reflects the external Timestamp Counter value A write access has no impact Note A wrap around is a change of the Timestamp Counter value from non zero to zero not caused by write access to TSCV 14 16 03 2015 BOSCH Revision 3 2 1 M CAN 2 3 11 Timeout Counter Configuration TOCC For a description of the Timeout Counter see Section 3 3 Timeout Counter Bits 31 30 2 28 27 26 25 24 2 22 21 20 19 18 17 16 RP OxFFFF Bits 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 R 0x0 0 R Read P Protected write n value after reset T
8. 36 2 3 35 Tx Buffer Configuration TXBC 37 2 8 36 Tx FIFO Queue Status 5 38 2 3 37 Tx Buffer Element Size Configuration TXESC 39 2 3 38 Tx Buffer Request Pending 40 2 3 39 Tx Buffer Add Request TXBAR 2 2 2 rh 41 2 340 Tx Buffer Cancellation Request 41 2 341 Tx Buffer Transmission Occurred TXBTO 42 2 342 Tx Buffer Cancellation Finished 42 2 343 Tx Buffer Transmission Interrupt Enable TXBTIE a na nananana aaan 43 2 344 Tx Buffer Cancellation Finished Interrupt Enable TSBCHEI 43 2 345 Tx Event FIFO Configuration TXEFC 44 16 03 2015 vii BOSCH M CAN viii Revision 3 2 1 2 346 Tx Event FIFO Status ee 45 2 347 Tx Event FIFO Acknowledge 45 24 Message RAM E EE EACUS sas RA A CERIS 46 2 4 1 Message RAM 46 2 4 2 Rx Buffer and FIFO Element 47 2 4 3 Tx Buffer 49 2 4 4 Tx Event FIFO Element 51 2 4 5 Standard
9. M CAN Controller Area Network User s Manual Revision 3 2 1 16 03 2015 Robert Bosch GmbH Automotive Electronics M CAN Revision 3 2 1 LEGAL NOTICE Copyright 2008 2015 by Robert Bosch GmbH and its licensors All rights reserved Bosch is a registered trademark of Robert Bosch GmbH The content of this document is subject to continuous developments and improvements All particulars and its use contained in this document are given by BOSCH in good faith NO WARRANTIES TO THE MAXIMUM EXTENT PERMITTED BY LAW NEITHER THE INTELLECTUAL PROPERTY OWNERS COPYRIGHT HOLDERS AND CONTRIBUTORS NOR ANY PERSON EITHER EXPRESSLY OR IMPLICITLY WARRANTS ANY ASPECT OF THIS SPECIFICATION SOFTWARE RELATED THERETO CODE AND OR PROGRAM RELATED THERETO INCLUDING ANY OUTPUT OR RESULTS OF THIS SPECIFICATION SOFTWARE RELATED THERETO CODE AND OR PROGRAM RELATED THERETO UNLESS AGREED TO IN WRITING THIS SPECIFICATION SOFTWARE RELATED THERETO CODE AND OR PROGRAM RELATED THERETO IS BEING PROVIDED AS IS WITHOUT ANY WARRANTY OF ANY TYPE OR NATURE EITHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND ANY WARRANTY THAT THIS SPECIFICATION SOFTWARE RELATED THERETO CODE AND OR PROGRAM RELATED THERETO IS FREE FROM DEFECTS ASSUMPTION OF RISK THE RISK OF ANY AND ALL LOSS DAMAGE OR UNSATISFACTORY PERFORMANCE OF THIS SPECIFICATION RESPECTIVELY THE
10. TRP20 TRP19 TRP18 TRP47 TRP16 RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRP15 TRP14 TRP13 TRP42 TRP11 TRP10 TRP9 TRP8 TRP7 TRP6 TRP5 TRP4 TRP3 TRP2 TRP1 TRPO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R Read n value after reset Table 39 Tx Buffer Request Pending address OxCC Bit 31 0 TRP 31 0 Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit The bits are set via register TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR TXBRP bits are set only for those Tx Buffers configured via TXBC After a TXBRP bit has been set a Tx scan see Section 3 5 Tx Handling is started to check for the pending Tx request with the highest priority Tx Buffer with lowest Message ID A cancellation request resets the corresponding transmission request pending bit of register TXBRP In case a transmission has already been started when a cancellation is requested this is done at the end of the transmission regardless whether the transmission was successful or not The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset After a cancellation has been requested a finished cancellation is signalled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been st
11. Write n value after reset Table 17 Interrupt Register address 0x50 Bit 29 ARA Access to Reserved Address 0 No access to reserved address occurred 1 Access to reserved address occurred Bit 28 PED Protocol Error in Data Phase Data Bit Time is used 0 No protocol error in data phase 1 Protocol error in data phase detected PSR DLEC gt 0 7 Bit 27 PEA Protocol Error in Arbitration Phase Nominal Bit Time is used 0 No protocol error in arbitration phase 12 Protocol error in arbitration phase detected PSR LEC 0 7 Bit 26 WDI Watchdog Interrupt 0 Message RAM Watchdog event occurred 1 Message RAM Watchdog event due to missing READY Bit 25 BO Bus_Off Status 0 Bus_Off status unchanged 1 Bus Off status changed Bit 24 EW Warning Status 0 Error Warning status unchanged 1 Error Warning status changed Bit 23 EP Error Passive 0 Error Passive status unchanged 1 Error Passive status changed Bit 22 ELO Error Logging Overflow 0 CAN Error Logging Counter did not overflow 12 Overflow of CAN Error Logging Counter occurred 20 16 03 2015 Revision 3 2 1 M CAN Bit 21 BEU Bit Error Uncorrected Message RAM bit error detected uncorrected Controlled by input signal m can aeim berr 1 generated by an optional external parity ECC logic attached to the Message RAM An uncorrected Message RAM bit error sets CCCR INIT to 1 This is done to avoid transmission of corrupted data 0 No bi
12. 6201 6240 1 39 mmu osa osav 08319 0 01 0839 n ENS 0 00 ieu LOL ER au jiwa s o 2 Q o o o o Oo gt Q UI iL LL LL 5 gt lt gt lt gt lt gt lt gt lt gt lt x Q s amp a P m 80 Revision 3 2 1 4 2 Module Interface M CAN The M CAN module s toplevel entity has the ports listed in the table below More details on how to connect the M CAN to a customer specific design can be found in 2 and 3 PORT DIR DOMAIN DESCRIPTION Clocks and Reset m can hclk IN Host clock m can cclk IN CAN clock m can reset IN module reset Physical Layer Interface m can rx IN ASYNC receive input m can D OUT CCLK CAN transmit output Generic Slave Interface m can aei sel IN module select m can aei wirt IN module write m can aei byteen 3 0 IN module byte enable m can aei addr 8 2 IN module address bus m can aei wdata 31 0 IN module data bus input m can aei ready OUT module ready m can aei rdata 31 0 OUT module data bus output Generic Master Interface m can aeim ready IN memory ready m can aeim rdata 31 0 IN memory data bus input m can aeim berr 1 0 IN Message RAM bit error m can aeim sel OUT memory select m can aeim wir OUT memory write m can aeim addr 15 2 OUT memory address bus 32 bit word address m can aeim wdata 31 0 OUT memory data
13. PRODUCTS MAKING USE OF IT IN PART OR AS A WHOLE SOFTWARE RELATED THERETO CODE AND OR PROGRAM RELATED THERETO RESTS WITH YOU AS THE USER TO THE MAXIMUM EXTENT PERMITTED BY LAW NEITHER THE INTELLECTUAL PROPERTY OWNERS COPYRIGHT HOLDERS AND CONTRIBUTORS NOR ANY PERSON EITHER EXPRESSLY OR IMPLICITLY MAKES ANY REPRESENTATION OR WARRANTY REGARDING THE APPROPRIATENESS OF THE USE OUTPUT OR RESULTS OF THE USE OF THIS SPECIFICATION SOFTWARE RELATED THERETO CODE AND OR PROGRAM RELATED THERETO IN TERMS OF ITS CORRECTNESS ACCURACY RELIABILITY BEING CURRENT OR OTHERWISE NOR DO THEY HAVE ANY OBLIGATION TO CORRECT ERRORS MAKE CHANGES SUPPORT THIS SPECIFICATION SOFTWARE RELATED THERETO CODE AND OR PROGRAM RELATED THERETO DISTRIBUTE UPDATES OR PROVIDE NOTIFICATION OF ANY ERROR OR DEFECT KNOWN OR UNKNOWN IF YOU RELY UPON THIS SPECIFICATION SOFTWARE RELATED THERETO CODE AND OR PROGRAM RELATED THERETO YOU DO SO AT YOUR OWN RISK AND YOU ASSUME THE RESPONSIBILITY FOR THE RESULTS SHOULD THIS SPECIFICATION SOFTWARE RELATED THERETO CODE AND OR PROGRAM RELATED THERETO PROVE DEFECTIVE YOU ASSUME THE COST OF ALL LOSSES INCLUDING BUT NOT LIMITED TO ANY NECESSARY SERVICING REPAIR OR CORRECTION OF ANY PROPERTY INVOLVED TO THE MAXIMUM EXTEND PERMITTED BY LAW DISCLAIMER IN NO EVENT UNLESS REQUIRED BY LAW OR AGREED TO IN WRITING SHALL THE INTELLECTUAL PROPERTY OWNERS COPYRIGHT HOLDERS OR ANY PERSON BE LIABLE FOR ANY LOSS EXPENSE OR DAMAGE OF
14. Read P Protected write n value after reset Bits 14 8 TDCO 6 0 Transmitter Delay Compensation Offset 0x00 0x7F Offset value defining the distance between the measured delay from m can tx to m can rx and the secondary sample point Valid values are 0 to 127 mtq Bits 6 0 TDCF 6 0 Transmitter Delay Compensation Filter Window Length 0x00 0x7F Defines the minimum value for the SSP position dominant edges on m can rx that would result in an earlier SSP position are ignored for transmitter delay measure ment The feature is enabled when TDCF is configured to a value greater than Valid values 0 to 127 mtq 16 03 2015 19 M CAN Revision 3 2 1 2 3 16 Interrupt Register IR The flags are set when one of the listed conditions is detected edge sensitive The flags remain set until the Host clears them A flag is cleared by writing a 1 to the corresponding bit position Writing a 0 has no effect A hard reset will clear the register The configuration of IE controls whether an interrupt is generated The configuration of ILS controls on which interrupt line an interrupt is signalled Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dd nd e ew er ero eeu pec oo d raw R 0x0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Read W
15. from the CAN Core to the Message RAM as well as providing receive message status information The Tx Handler is responsible for the transfer of transmit messages from the Message RAM to the CAN Core as well as providing transmit status information Acceptance filtering is implemented by a combination of up to 128 filter elements where each one can be configured as a range as a bit mask or as a dedicated ID filter The M CAN can be connected to a wide range of Host CPUs via its 8 16 32 bit Generic Slave Interface The M CAN s clock domain concept allows the separation between the high precision CAN clock and the Host clock which may be generated by an FM PLL Features Conform with CAN protocol version 2 0 part A B and ISO 11898 1 CAN FD with up to 64 data bytes supported CAN Error Logging AUTOSAR support SAE J1939 support mproved acceptance filtering Two configurable Receive FIFOs Separate signalling on reception of High Priority Messages Upto 64 dedicated Receive Buffers Up to 32 dedicated Transmit Buffers Configurable Transmit FIFO Configurable Transmit Queue Configurable Transmit Event FIFO Direct Message RAM access for Host CPU Multiple M CANs may share the same Message RAM Programmable loop back test mode Maskable module interrupts 8 16 32 bit Generic Slave Interface for connection customer specific Host CPUs Two clock domains CAN clock and Host clock Power down support
16. 0 Identifier Standard or extended identifier depending on bit XTD A standard identifier is stored into ID 28 18 E1 Bits 31 24 MM 7 0 Message Marker Copied from Tx Buffer into Tx Event FIFO element for identification of Tx message status E1 Bit 23 22 ET 1 0 Event Type 00 Reserved 01 Txevent 10 Transmission in spite of cancellation always set for transmissions in DAR mode 11 2 Reserved E1 Bit 21 FD Format 0 Standard frame format 1 CAN FD frame format new DLC coding and CRC E1 Bit 20 BRS Bit Rate Switch 0 Frame transmitted without bit rate switching 1 Frame transmitted with bit rate switching E1 Bits 19 16 DLC 3 0 Data Length Code 0 8 CAN FD frame with 0 8 data bytes transmitted 9 157 frame with 8 data bytes transmitted 9 15 CAN FD frame with 12 16 20 24 32 48 64 data bytes transmitted 16 03 2015 51 M CAN Revision 3 2 1 E1 Bits 15 0 TXTS 15 0 Tx Timestamp Timestamp Counter value captured on start of frame transmission Resolution depending on configuration of the Timestamp Counter Prescaler TSCC TCP 2 4 5 Standard Message ID Filter Element Up to 128 filter elements can be configured for 11 bit standard IDs When accessing a Standard Message ID Filter element its address is the Filter List Standard Start Address SIDFC FLSSA plus the index of the filter element 0 127 SFID1 10 0 SFID2 10 0 Table 52 Standard Message ID Filter Element Bits 31 30 SFT
17. 1 2 3 27 Rx FIFO 0 Configuration RXFOC M_CAN Bits 31 30 29 28 27 2 25 24 23 22 21 20 19 17 16 OxAO FOOM FOWM 6 0 res FOS 6 0 RP 0 RP 0x0 R 0 RP 0x0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0 F0SA 15 2 res 0 0 R 0x0 R Read P Protected write Value after reset Table 28 Bit 31 FIFO 0 can be operated in blocking or in overwrite mode see Section 3 4 2 Rx FIFO 0 Configuration address FOOM FIFO 0 Operation Mode 0 FIFO 0 blocking mode 1 FIFO 0 overwrite mode Bit 30 24 0 1 64 gt 64 Bit 22 16 0 1 64 gt 64 FOWM 6 0 Rx FIFO 0 Watermark Watermark interrupt disabled Level for Rx FIFO 0 watermark interrupt IR RFOW Watermark interrupt disabled FOS 6 0 Rx FIFO 0 Size No Rx FIFO 0 Number of Rx FIFO 0 elements Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to FOS 1 Bit 15 2 FOSA 15 2 Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM 32 bit word address see Figure 2 16 03 2015 31 6 BOSCH M CAN Revision 3 2 1 2 3 28 Rx FIFO 0 Status RXFOS Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 4 res RFOL FOF res FOPI 5 0 R 0x0 RO R 0 R 0x0 R 0x0x0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res FOGI 5 0 res FOFL 6 0 R 0x0 R 0x0 R 0 R 0x0 R Read n value after reset Table 29 Rx FIFO 0 Status addr
18. 17 Transmitter Delay Compensation Register address 0x048 19 Interrupt Register address UxvbO eene 20 Interrupt Enable address shale 23 Interrupt Line Select address 0x58 U eene nenne 25 Interrupt Line Select address 0 5 eene ener nnns 26 Global Filter Configuration address 0 80 eene 27 Standard ID Filter Configuration address xv 28 Extended ID Filter Configuration address 0x88 sss 28 Extended ID AND Mask address xp 29 High Priority Message Status address 0x94 a 29 New Data 1 address 0X98 nct t iR c D du acera DI Mees 30 New Data 2 address OX9C uuu ua Eg bd tes ER t ads 30 Rx FIFO 0 Configuration address 0xA0 a 31 Rx FIFO 0 Status address OXA 32 Rx FIFO 0 Acknowledge address 8 33 Rx Buffer Configuration address NA 33 Rx FIFO 1 Configuration address 0xB0 u 34 Rx FIFO 1 Status address OxBA ssssssssssssesssee nenne eene rennen 34 Rx FIFO 1 Acknowledge address UND 35 Rx Buffer FIFO Element Size Configuration address 36 Tx Buffer Configuration address 0xC0 nee ennemis 37 Tx FlFO Queue Statu
19. 48 64 data bytes T2 Bits 31 24 DB3 7 0 Data Byte 3 T2 Bits 23 16 DB2 7 0 Data Byte 2 T2 Bits 15 8 DB1 7 0 Data Byte 1 T2 Bits 7 0 DBO 7 0 Data Byte 0 Bits 31 24 DB7 7 0 Data Byte 7 Bits 23 16 DB6 7 0 Data Byte 6 T3 Bits 15 8 DB5 7 0 Data Byte 5 T3 Bits 7 0 DB4 7 0 Data Byte 4 Tn Bits 31 24 DBm 7 0 Data Byte m Tn Bits 23 16 DBm 1 7 0 Data Byte m 1 Tn Bits 15 8 DBm 2 7 0 Data Byte m 2 Tn Bits 7 0 DBm 3 7 0 Data Byte m 3 Note Depending on the configuration of the element size TXESC between two and sixteen 32 bit words Tn z 3 17 are used for storage of a CAN message s data field 50 16 03 2015 Revision 3 2 1 M CAN 2 4 4 Tx Event FIFO Element Each element stores information about transmitted messages By reading the Tx Event FIFO the Host CPU gets this information in the order the messages were transmitted Status information about the Tx Event FIFO can be obtained from register TXEFS 31 24 23 16 15 0 12 o Eo je lE ID 28 0 LL IO E1 MM 7 0 1 0 S DLC 3 0 TXTS 15 0 Table 51 Tx Event FIFO Element E0 Bit 31 ESI Error State Indicator 0 Transmitting node is error active 1 Transmitting node is error passive EO Bit 30 XTD Extended Identifier 0 11 bit standard identifier 1 29 bit extended identifier EO Bit 29 RTR Remote Transmission Request 0 Data frame transmitted 1 Remote frame transmitted EO Bits 28 0 ID 28
20. 6 0 R 0x0 R 0x0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res PXE RFDF RBRS RESI DLEC 2 0 BO EW EP ACT 1 0 LEC 2 0 R 0 x0 x0 x0 S 0x7 RO R 0 R 0 R 0x0 S 0x7 R Read 5 Set on read X Reset on read value after reset Table 15 Protocol Status Register address Ox44 Bits 22 16 TDCV 6 0 Transmitter Delay Compensation Value 0x00 0x7F Position of the secondary sample point defined by the sum of the measured delay from m can tx to m can rx and TDCR TDCO The SSP position is in the data phase the number of mtq between the start of the transmitted bit and the secondary sample point Valid values are 0 to 127 mtq Bit 14 PXE Protocol Exception Event 0 No protocol exception event occurred since last read access 1 Protocol exception event occurred Bit 13 RFDF Received a CAN FD Message This bit is set independent of acceptance filtering 0 Since this bit was reset by the CPU no CAN FD message has been received 1 Message in CAN FD format with FDF flag set has been received Bit 12 RBRS BRS flag of last received CAN FD Message This bit is set together with RFDF independent of acceptance filtering 0 Last received CAN FD message did not have its BRS flag set 1 Last received CAN FD message had its BRS flag set Bit 11 RESI ESI flag of last received CAN FD Message This bit is set together with RFDF independent of acceptance filtering 0 Last received CAN FD message did not have its ESI flag set 1 Las
21. Data Bit Timing amp Prescaler Register DBTP This register is only writable if bits CCCR CCE and CCCR INIT are set The CAN bit time may be programed in the range of 4 to 49 time quanta The CAN time quantum may be programmed in the range of 1 to 32 m can cclk periods t DBRP 1 mtq DTSEG1 is the sum of Prop Seg and Phase Seg1 DTSEG2 is Phase Geo Therefore the length of the bit time is programmed values DTSEG1 DTSEG2 3 ty or functional values Sync Seg Prop Seg Phase Seg1 Phase Seg 2 tg The Information Processing Time IPT is zero meaning the data for the next bit is available at the first clock edge after the sample point Bits 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 R 0x0 RP 0 R 0x0 0 0 12 11 10 9 8 7 6 5 4 15 14 13 2 1 0 DTSEG1 4 0 DTSEG2 3 0 DSJW 3 0 R 0x0 RP 0x3 RP 0x3 Bits R Read P Protected write value after reset Table 5 Data Bit Timing amp Prescaler Register address OxOC Bit 23 TDC Transmitter Delay Compensation 0 Transmitter Delay Compensation disabled 1 Transmitter Delay Compensation enabled Bits 20 16 DBRP 4 0 Data Bit Rate Prescaler 0x00 0x1F The value by which the oscillator frequency is divided for generating the bit time quanta The bit time is built up from a multiple of this quanta Valid values for the Bit Rate Prescaler are 0 to 31 The actual interpretation by the hardware of this value is such that one more
22. Level remain unchanged A Tx FIFO element allocates Element Size 32 bit words in the Message RAM see Table 59 Therefore the start address of the next available free Tx FIFO Buffer is calculated by adding Tx FIFO Queue Put Index TXFQS TFQPI 0 211 Element Size to the Tx Buffer Start Address TXBC TBSA 16 03 2015 73 5 BOSCH M CAN Revision 3 2 1 3 5 4 Tx Queue Tx Queue operation is configured by programming TXBC TFQM to 1 Messages stored in the Tx Queue are transmitted starting with the message with the lowest Message ID highest priority In case that multiple Queue Buffers are configured with the same Message ID the Queue Buffer with the lowest buffer number is transmitted first New messages have to be written to the Tx Buffer referenced by the Put Index TXFQS TFQPI An Add Request cyclically increments the Put Index to the next free Tx Buffer In case that the Tx Queue is full TXFQS TFQF 1 the Put Index is not valid and no further message should be written to the Tx Queue until at least one of the requested messages has been sent out or a pending transmission request has been cancelled The application may use register TXBRP instead of the Put Index and may place messages to any Tx Buffer without pending transmission request A Tx Queue Buffer allocates Element Size 32 bit words in the Message RAM see Table 59 Therefore the start address of the next available free Tx Queue Buffer is calculated by adding Tx
23. Message ID Filter 52 2 4 6 Extended Message ID Filter Element 53 3 Functional Description 55 3 1 Operating Modes c enr RS RI be RU UR aS eee GERE CPP RES 55 3 1 1 Software Initialization 55 3 1 2 Normal x eR ERE AW eee su ERA 56 3 1 3 CAN FD 2 56 3 1 4 Transmitter Delay 57 3 1 5 Restricted Operation Mode 59 3 1 6 Bus Monitoring Mode 59 3 1 7 Disabled Automatic Retransmission 60 3 1 8 Power Down Sleep Mode 60 3 1 9 Test Modes 60 3 2 Timestamp Generation 61 3 8 tee 62 3 4 PRIOR Pes 63 3 4 1 Acceptance 63 3 4 2 E di ole REENEN 67 3 4 3 Dedicated Rx Buffers _ _ 69 3 4 4 Debug on CAN Support u u saus asa da aaa Qasa en 70 KSE le Elte EEN 72 3 5 1 Transmit Pause uos x bua b eR RR NA URN a p CAR e eR 72 3 5 2 Dedicated Tx Buffers 72 3 5 3 e
24. Rx FIFO 1 Status 0000 0000 R 0xB8 RXF1A Rx FIFO 1 Acknowledge 00000000 RW OxBC RXESC Rx Buffer FIFO Element Size Configuration 00000000 RP 0xC8 TXESC Tx Buffer Element Size Configuration 39 00000000 RP OxCC TXBRP Tx Buffer Request Pending 40 0000 0000 R Tx Buffer Add Request 41 00000000 RW 0 04 TXBCR Tx Buffer Cancellation Request 41 00000000 RW OxEO TXBTIE Tx Buffer Transmission Interrupt Enable 43 00000000 RW 4 TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 43 0000 0000 RW OxE8 EC reserved 2 0000 0000 R OxFO TXEFC Tx Event FIFO Configuration 44 0000 0000 RP OxFC reserved 1 0000 0000 R R Read 5 Set on read X Reset on read W Write P Protected write p Protected set C Clear preset on write r release d date Table 1 M CAN Register Map 2 2 1 Access to reserved Register Addresses In case the application software wants to access one of the reserved addresses in the M CAN register map read or write access interrupt flag IR ARA is set and if enable the interrupt is signalled via the assigned interrupt line m can intO or m can int1 BOSCH 16 03 2015 Revision 3 2 1 M CAN 2 3 Registers 2 3 1 Customer Register Address 0x08 is reserved for an optional 32 bit customer specific register The Customer Register is intended to hold customer specific configuration control and status bits A description of the functionality is not part of this docum
25. arbitration priority should be inverse This may lead to a case where one ECU sends a burst of CAN messages that cause another ECU s CAN messages to be delayed because that other messages have a lower CAN arbitration priority If e g CAN ECU 1 has the transmit pause feature enabled and is requested by its application software to transmit four messages it will after the first successful message transmission wait for two CAN bit times of bus idle before it is allowed to start the next requested message If there are other ECUs with pending messages those messages are started in the idle time they would not need to arbitrate with the next message of ECU 1 After having received a message ECU 1 is allowed to start its next transmission as soon as the received message releases the CAN bus The transmit pause feature is controlled by bit CCCR TXP If the bit is set the M CAN will each time it has successfully transmitted a message pause for two CAN bit times before starting the next transmission This enables other CAN nodes in the network to transmit messages even if their messages have lower prior identifiers Default is transmit pause disabled CCCR TXP 0 This feature looses up burst transmissions coming from a single node and it protects against babbling idiot scenarios where the application program erroneously requests too many transmissions 3 5 2 Dedicated Tx Buffers Dedicated Tx Buffers are intended for message transmission
26. bus output Miscellaneous m can ext ts 15 0 IN external timestamp vector m can clkstop req IN clock stop request m can scanmode IN scan mode enable disable modification on read m can dis mord IN ECR CEL PSR PXE PSR RFDF PSR RBRS PSR RESI PSR DLEC PSR LEC m can intO OUT interrupt O m can int1 OUT interrupt 1 m can clkstop ack OUT HCLK clock stop acknowledge DMA Interface m can dma ack IN HCLK DMA acknowledge m can dma req OUT HCLK DMA request Extension Interface mican cok IN calibration OK has to be hardwired to 1 in case no ES H Clock Calibration on CAN unit is connected m can ir 31 0 OUT Interrupt Register flags m can txbrp 31 0 OUT HCLK Tx Buffer Request Pending TXBRP Table 61 16 03 2015 M CAN Module Interface 81 5 BOSCH M CAN Revision 3 2 1 PORT DIR DOMAIN DESCRIPTION m can rxfd OUT CCLK receive fast data m can txfd OUT CCLK transmit fast data m can fe 2 0 OUT filter events 0 2 m can cce OUT HCLK Configuration Change Enable CCCR CCE m can spt OUT sample point delayed by one m can cclk period m can mrx OUT CCLK message received m can calf OUT calibration field m can aff OUT HCLK acceptance filtering finished Table 61 M CAN Module Interface Note Signals m can m can spt m can mrx m can calf m can aff and one of the filter event outputs m can fe are interfacing to an optional Clock Calibration on CAN unit In case the M CAN is used without Cloc
27. for the occurrence of a sequence of 11 consecutive recessive bits _ before it can take part in bus activities and start the message transfer Access to the M_CAN configuration registers is only enabled when both bits CCCR INIT and CCCR CCE are set protected write CCCR CCE can only set reset while CCCR INIT 1 CCCR CCE is automatically reset when CCCR INIT is reset The following registers are reset when CCCR CCE is set HPMS High Priority Message Status RXFOS Rx FIFO 0 Status RXF1S Rx FIFO 1 Status TXFQS Tx FlFO Queue Status TXBRP Tx Buffer Request Pending TXBTO Tx Buffer Transmission Occurred TXBCF Tx Buffer Cancellation Finished TXEFS Tx Event FIFO Status The Timeout Counter value TOCV TOC is preset to the value configured by TOCC TOP when CCCR CCE is set In addition the state machines of the Tx Handler and Rx Handler are held in idle state while CCCR CCE 1 The following registers are only writeable while CCCR CCE 0 TXBAR Tx Buffer Add Request TXBCR Tx Buffer Cancellation Request CCCR TEST and CCCR MON can only be set by the Host while CCCR INIT 1 and CCCR CCE 1 Both bits may be reset at any CCCR DAR can only set reset while CCCR INIT 1 and CCCR CCE 1 Note In case the Message RAM is equipped with parity or ECC functionality it is recommended to initialize the Message RAM after hardware re
28. rate inside of this CAN FD frame is switched A CAN FD bit rate switch is signified by res dominant and BRS recessive The coding of res recessive is reserved for future expansion of the protocol In case the M CAN receives a frame with FDF recessive and res recessive it will signal a Protocol Exception Event by setting bit PSR PXE When Protocol Exception Handling is enabled CCCR PXHD 0 this causes the operation state to change from Receiver PSR ACT 10 to Integrating PSR ACT 00 at the next sample point In case Protocol Exception Handling is disabled CCCR PXHD 1 theM CAN will treat a recessive res bit as an form error and will respond with an error frame CAN FD operation is enabled by programming CCCR FDOE In case CCCR FDOE 1 transmission and reception of CAN FD frames is enabled Transmission and reception of Classic CAN frames is always possible Whether a CAN FD frame or a Classic CAN frame is transmitted can be configured via bit in the respective Tx Buffer element With CCCR FDOE 0 received frames are interpreted as Classic CAN frames which leads to the transmission of an error frame when receiving a CAN FD frame When CAN FD operation is disabled no CAN FD frames are transmitted even if bit FDF of a Tx Buffer element is set CCCR FDOE and CCCR BRSE can only be changed while CCCR INIT and CCCR CCE are both set With CCCR FDOE 0 the setting of bits FDF and BRS is ignor
29. rx D Rx Tx Rx M CAN M CAN External Loop Back Mode Internal Loop Back Mode Figure 5 Pin Control in Loop Back Modes 3 2 Timestamp Generation For timestamp generation the M CAN supplies a 16 bit wrap around counter A prescaler TSCC TCP can be configured to clock the counter in multiples of CAN bit times 1 16 The counter is readable via TSCV TSC A write access to register TSCV resets the counter to zero When the timestamp counter wraps around interrupt flag IR TSW is set On start of frame reception transmission the counter value is captured and stored into the timestamp section of an Rx Buffer Rx FIFO RXTS 15 0 or Tx Event FIFO TXTS 15 0 element By programming bit TSCC TSS an external 16 bit timestamp can be used 16 03 2015 61 M CAN 3 3 Revision 3 2 1 Timeout Counter To signal timeout conditions for Rx FIFO 0 Rx FIFO 1 and the Tx Event FIFO the M CAN supplies a 16 bit Timeout Counter It operates as down counter and uses the same prescaler controlled by TSCC TCP as the Timestamp Counter The Timeout Counter is configured via register TOCC The actual counter value can be read from TOCV TOC The Timeout Counter can only be started while CCCR INIT 0 It is stopped when CCCR INIT 1 e g when the M CAN enters Bus Off state The operation mode is selected by TOCC TOS When operating in Continuous Mode the counter starts when CCCR INIT is reset A write to TOCV presets the counter to the va
30. than the value programmed here is used 8 16 03 2015 BOSCH Revision 3 2 1 M CAN Bits 12 8 DTSEG1 4 0 Data time segment before sample point 0x00 0x1F Valid values are 0 to 31 The actual interpretation by the hardware of this value is such that one more than the programmed value is used Bits 7 4 DTSEG2 3 0 Data time segment after sample point 0x0 OxF Valid values are 0 to 15 The actual interpretation by the hardware of this value is such that one more than the programmed value is used Bits 3 0 DSJW 3 0 Data Re Synchronization Jump Width 0x0 OxF Valid values are 0 to 15 The actual interpretation by the hardware of this value is such that one more than the value programmed here is used Note With a CAN clock m can cclk of 8 MHz the reset value of 0x00000A33 configures the M CAN for a dala phase bit rate of 500 kBit s Note The bit rate configured for the CAN FD data phase via DBTP must be higher or equal to the bit rate configured for the arbitration phase via NBTP 2 3 5 Test Register TEST Write access to the Test Register has to be enabled by setting bit CCCR TEST to 1 All Test Register functions are set to their reset values when bit CCCR TEST is reset Loop Back Mode and software control of pin m can tx are hardware test modes Programming of TX z 00 may disturb the message transfer on the CAN bus Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x10 res 0 0 15 14 13 12 1
31. the first matching enabled filter element or when the end of the filter list is reached If EFEC 100 101 or 110 a match sets interrupt flag IR HPN and if enabled an interrupt is generated In this case register HPMS is updated with the status of the priority match 000 Disable filter element 001 7 Store in Rx FIFO 0 if filter matches 010 7 Store in Rx FIFO 1 if filter matches 011 7 Reject ID if filter matches 100 Set priority if filter matches 101 2 Set priority and store in FIFO 0 if filter matches 110 Set priority and store in FIFO 1 if filter matches 111 2 Store into Rx Buffer or as debug message configuration of EFT 1 0 ignored F0 Bits 28 0 EFID1 28 0 Extended Filter ID 1 16 03 2015 First ID of extended ID filter element When filtering for Rx Buffers or for debug messages this field defines the ID of an extended message to be stored The received identifiers must match exactly only XIDAM masking mechanism see Section 3 4 1 5 Extended Message ID Filtering is used M CAN Revision 3 2 1 F1 Bits 31 30 EFT 1 0 Extended Filter Type 00 Range filter from EFID1 to EFID2 EFID2 EFID1 01 Dual ID filter for EFID1 or EFID2 10 Classic filter EFID1 filter EFID2 mask 11 Range filter from EFID1 to EFID2 EFID2 gt EFID1 mask not applied F1 Bits 28 0 EFID2 28 0 Extended Filter ID 2 This bit field has a different meaning depending on the configuration of EFEC 1 EFEC
32. 0 receive filter list enabled gt pr gt 0 0 match filter element 0 yes SIDFC LSS 7 0 reject match filter element SIDFC LSS acceptance rejection no accept GFC ANFS 1 1 accept non matching frames GFC ANFS 1 0 Y FIFO selected and target FIFO full blocking no store frame Figure 6 Standard Message ID Filter Path 16 03 2015 65 M CAN Revision 3 2 1 3 4 1 5 Extended Message ID Filtering Figure 7 below shows the flow for extended Message ID 29 bit Identifier filtering The Extended Message ID Filter element is described in Section 2 4 6 Controlled by the Global Filter Configuration and the Extended ID Filter Configuration SIDEC Message ID Remote Transmission Request bit RTR and the Identifier Extension bit IDE of received frames are compared against the list of configured filter elements The Extended ID AND Mask XIDAM is ANDed with the received identifier before the filter list is executed 2 valid frame received 11 29 bit identifier GFC RRFE 1 reject remote frames remote frame no GFC RRFE 0 receive filter list enabled XIDFC LSE 6 0 gt 0 5 yes lt match filter element 0 z no o B II Y match filter element XIDFC LSE no reject acceptance rejection accept GFC ANF
33. 0 0 SFID2 10 0 Standard Filter ID 2 This bit field has a different meaning depending on the configuration of SFEC 1 001 110 Second ID of standard ID filter element 2 SFEC 111 Filter for Rx Buffers for debug messages 52 16 03 2015 Revision 3 2 1 M CAN SFID2 10 9 decides whether the received message is stored into an Rx Buffer or treated as message A B or C of the debug message sequence 00 Store message into an Rx Buffer 01 Debug Message A 10 Debug Message B 11 Debug Message C SFID2 8 6 is used to control the filter event pins m can fe 2 0 at the Extension Interface A one at the respective bit position enables generation of a pulse at the related filter event pin with the duration of one m can hclk period in case the filter matches SFID2 5 0 defines the offset to the Rx Buffer Start Address RXBC RBSA for storage of a matching message 2 4 6 Extended Message ID Filter Element Table 53 Up to 64 filter elements can be configured for 29 bit extended IDs When accessing an Extended Message ID Filter element its address is the Filter List Extended Start Address XIDFC FLESA plus two times the index of the filter element 0 63 EFEC 2 0 EFID1 28 0 EFID2 28 0 Extended Message ID Filter Element F0 Bit 31 29 EFEC 2 0 Extended Filter Element Configuration All enabled filter elements are used for acceptance filtering of extended frames Acceptance filtering stops at
34. 0 R 0x0 R Read P Protected write n value after reset Table 23 Extended ID Filter Configuration address 0x88 Bit 22 16 LSE 6 0 List Size Extended 0 No extended Message ID filter 1 64 Number of extended Message ID filter elements gt 64 Values greater than 64 are interpreted as 64 Bit 15 2 FLESA 15 2 Filter List Extended Start Address Start address of extended Message ID filter list 32 bit word address see Figure 2 28 16 03 2015 BOSCH Revision 3 2 1 2 3 28 Extended ID AND Mask XIDAM M CAN Bits 31 30 29 28 27 26 2 24 2 22 21 20 19 18 17 16 0x90 res EIDM 28 16 R 0x0 RP 0x1FFF Bits 15 14 13 12 11 10 9 7 6 5 4 3 2 1 EIDM 15 0 RP 0xFFFF R Read P Protected write n value after reset Table 24 Extended ID AND Mask address 0x90 Bit 28 0 EIDM 28 0 Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame Intended for masking of 29 bit IDs in SAE J1939 With the reset value of all bits set to one the mask is not active 2 3 24 High Priority Message Status HPMS This register is updated every time a Message ID filter element configured to generate a priority event matches This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages Bits 31 30 29 28 2 26 2 24 2 22 21 20 19 18 17 16 0x94 res R 0x0
35. 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note Incase the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO only the number of bytes as configured by RXESC are stored to the Rx Buffer resp Rx FIFO element The rest of the frame s data field is ignored 16 03 2015 Revision 3 2 1 2 3 35 Tx Buffer Configuration TXBC M CAN Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DCH res TFQM TFQS 5 0 res NDTB 5 0 RO RP 0 RP 0x0 R 0x0 RP 0x0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBSA 15 2 res RP 0x0 R 0x0 R Read P Protected write n value after reset Table 36 Tx Buffer Configuration address OxCO Bit 30 TFQM TxFIFO Queue Mode 0 Tx FIFO operation 1 Tx Queue operation Bit 29 24 TFQS 5 0 Transmit FIFO Queue Size 0 No Tx 1 322 Number of Tx Buffers used for Tx FIFO Queue gt 32 Values greater than 32 are interpreted as 32 Bit 21 16 NDTB 5 0 Number of Dedicated Transmit Buffers 0 No Dedicated Tx Buffers 1 322 Number of Dedicated Tx Buffers gt 32 Values greater than 32 are interpreted as 32 Bit 15 2 TBSA 15 2 Tx Buffers Start Address Start address of Tx Buffers section in Message RAM 32 bit word address see Fig
36. 03 2015 Revision 3 2 1 M CAN Table of contents 1 Overview uu dues ER PERPE DR qua TIER RARI A ERRAT YET 1 Le xL ETT 1 1 2 Block Diagram wicca acer Res ead RS 2 1 3 Dual Clock Sources 3 1 4 Dual Interrupt CLINGS ENT RS RO er ENEE US 3 2 Programmer s Modells 2 Ghee v ERR TAA ea boda dera na Ea de E Rep na 5 2 14 M Hardware Reset Descriptioh 5 2 2 Register Map s serge xax x RR Path ae da dun x pad a upon 5 2 2 1 Access to reserved Register 55 65 6 23 Regist rs ss beo eee nex Seda Ase dE EE 7 2 3 1 Customer Register ossia A Eana e eae edge HERE DEP 7 2 3 2 Core Release Register CREL 7 2 3 3 Endian Register ENDN qasa akka 8 2 3 4 Data Bit Timing 4 Prescaler Register 8 2 3 5 Test Register ES e ead Qa 9 2 3 6 RAM Watchdog RW 10 2 3 7 CC Control Register CCCR L s l ranta eects 11 2 3 8 Nominal Bit Timing 4 Prescaler Register 13 2 3 9 Timestamp Counter Configuration 14 2 3 10 Timestamp Counter Value 5 14 2 3 11 Timeout Counter Configuration TOCCO
37. 1 0x5C Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 res 1 R 0x0 RW 0 RW 0 R Read W Write n value after reset Table 20 Interrupt Line Select address 0x5C Bit 1 EINT1 Enable Interrupt Line 1 0 Interrupt line m can int1 disabled 1 Interrupt line m can int1 enabled Bit 0 EINTO Enable Interrupt Line O 0 Interrupt line m can disabled 1 Interrupt line m can Int enabled 26 5 BOSCH 16 03 2015 Revision 3 2 1 M CAN 2 3 20 Global Filter Configuration GFC Global settings for Message ID filtering The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure 6 and Figure 7 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x80 res 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0x0 RP 0x0 RP 0x0 RP 0 RP 0 R Read P Protected write value after reset Table 21 Global Filter Configuration address 0x80 Bit 5 4 ANFS 1 0 Accept Non matching Frames Standard Defines how received messages with 11 bit IDs that do not match any element of the filter list are treated 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Bit 3 2 ANFE 1 0 Accept Non matching Frames Extended Defines how received messages with 29 bit IDs that do not match any element of the filter list are treated 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Bit 1 RRFS Reject Remote Frames St
38. 1 0 Standard Filter Type 00 Range filter from SFID1 to SFID2 SFID2 gt SFID1 01 Dual ID filter for SFID1 or 52102 10 Classic filter SFID1 filter 52102 mask 11 Filter element disabled Note With SFT 11 the filter element is disabled and the acceptance filtering continues same behaviour as with SFEC 000 Bit 29 27 SFEC 2 0 Standard Filter Element Configuration All enabled filter elements are used for acceptance filtering of standard frames Acceptance filtering stops at the first matching enabled filter element or when the end of the filter list is reached If SFEC 100 101 or 110 a match sets interrupt flag IR HPN and if enabled an interrupt is generated In this case register HPMS is updated with the status of the priority match 000 Disable filter element 001 7 Store in Rx FIFO 0 if filter matches 010 Store in Rx FIFO 1 if filter matches 011 7 Reject ID if filter matches 100 Set priority if filter matches 101 2 Set priority and store in FIFO 0 if filter matches 110 Set priority and store in FIFO 1 if filter matches 111 2 Store into Rx Buffer or as debug message configuration of SFT 1 0 ignored Bits 26 16 SFID1 10 0 Standard Filter ID 1 First ID of standard ID filter element When filtering for Rx Buffers or for debug messages this field defines the ID of a standard message to be stored The received identifiers must match exactly no masking mechanism is used Bits 1
39. 1 10 9 8 7 6 5 4 3 2 1 0 0 0 R U RP 0x0 RP 0 0 0 R Read P Protected write U undefined value after reset Table 6 Test Register address 0x10 Bit 7 RX Receive Pin Monitors the actual value of pin m can rx 0 The CAN bus is dominant m can rx 0 1 The CAN bus is recessive m can rx 1 Bits 6 5 TX 1 0 Control of Transmit Pin 00 Reset value m can tx controlled by the CAN Core updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m can tx 10 Dominant 0 level at pin m can tx 11 Recessive 1 at pin m can tx Bit 4 LBCK Loop Back Mode 0 Reset value Loop Back Mode is disabled 12 Loop Back Mode is enabled see Chapter 3 1 9 16 03 2015 9 M CAN Revision 3 2 1 2 3 6 RAM Watchdog RWD The RAM Watchdog monitors the READY output of the Message RAM m can aeim ready A Message RAM access via the M CAN s Generic Master Interface m can aeim sel active starts the Message RAM Watchdog Counter with the value configured by RWD WDC The counter is reloaded with RWD WDC when the Message RAM signals successful completion by activating its READY output In case there is no response from the Message RAM until the counter has counted down to zero the counter stops and interrupt flag IR WDI is set The RAM Watchdog Counter is clocked by the Host clock m can hclk Bits 31 30 29 28 27 2 2 24 23 22 21 20 19 18 17 16 0x14 res R 0x0 Bits 15 1
40. 4 3 2 0 07 11 2014 3 2 1 16 03 2015 Bit NISO added to register CCCR Table 61 description of m Can dis updated Baud Rate replaced by Bit Rate Note about Message RAM initialization added minor textual enhancements and corrections 16 03 2015 TRACKING OF MAJOR CHANGES M CAN Revision 3 2 1 TERMS AND ABBREVIATIONS This document uses the following terms and abbreviations Term BRP BSP BTL CAN CAN FD CRC DLC ECC ECU EML FSM mtq SSP TDC TSEG1 TSEG2 TTCAN Meaning Bit Rate Prescaler Bit Stream Processor Bit Timing Logic Controller Area Network Controller Area Network with Flexible Data rate Cyclic Redundancy Check Data Length Code Error Correction Code Electronic Control Unit Error Management Logic Finite State Machine minimum time quantum CAN clock period m can cclk Secondary Sample Point Transmitter Delay Compensation time quantum Time Segment before Sample Point Time Segment after Sample Point Time Triggered CAN CONVENTIONS The following conventions are used within this User s Manual Arial bold Arial italic Names of bits and ports States of bits and ports REFERENCES This document refers to the following documents Ref Author s 1 Iso 2 5 3 5 vi BOSCH Title ISO 11898 1 CAN data link layer and physical signalling M_ TT CAN System Integration Guide M_CAN Module Integration Guide 16
41. 4 13 12 11 10 9 8 7 86 5 4 3 2 1 0 WDV 7 0 WDCI 7 0 R 0x0 RP 0x0 R Read W Write P Protected write n value after reset Table 7 RAM Watchdog address 0x14 Bits 7 0 WDV 7 0 Watchdog Value Actual Message RAM Watchdog Counter Value Bits 7 0 WDC 7 0 Watchdog Configuration Start value of the Message RAM Watchdog Counter With the reset value of 00 the counter is disabled 10 16 03 2015 Revision 3 2 1 M CAN 2 3 7 CC Control Register CCCR For details about setting and resetting of single bits see Section 3 1 1 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x18 TS R 0x0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NISO TXP EFBI PXHD res BRSE FDOE TEST DAR CSR CSA ASM CCE INIT RP 0 RP 0 RP 0 0 R 0x0 RP 0 0 Rp 0 RP 0 Rp 0 RW 0 RO Rp 0 RP 0 RW 1 R Read W Write P Protected write p Protected set n value after reset Table 8 CC Control Register address 0x18 Bit 15 NISO Non ISO Operation If this bit is set the M CAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1 0 0 CAN FD frame format according to 15011898 1 1 CAN FD frame format according to Bosch CAN FD Specification V1 0 Note When the generic parameter iso only g is set to 1 in hardware synthesis this bit be comes reserved and is read as 0 The M CAN always operates with the
42. 44 Tx Buffer Transmission Interrupt Enable address OxEO Bit 31 0 TIE 31 0 Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit 0 Transmission interrupt disabled 1 Transmission interrupt enable 2 3 44 Tx Buffer Cancellation Finished Interrupt Enable TXBCIE Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SC RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Read W Write n value after reset Table 45 Tx Buffer Cancellation Finished Interrupt Enable address OxE4 Bit 31 0 CFIE 31 0 Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled 16 03 2015 43 BOSCH M CAN Revision 3 2 1 2 3 45 Tx Event FIFO Configuration TXEFC Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OxFO res EFWN 5 0 res EFS 5 0 R 0x0 RP 0x0 R 0x0 RP 0x0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFSA 15 2 res 0 0 R 0x0 R Read P Protected write value after reset Table 46 Tx Event FIFO Configuration address OxFO Bit 29 24 EFWN 5 0 Event FIFO Watermark 0 Watermark interrupt disabled 1 32 Level for Tx Event FIFO watermark i
43. 5 0 R 0x0 RW 0x0 R Read W Write n value after reset Table 34 Rx FIFO 1 Acknowledge address 0xB8 Bit 5 0 F1AI 5 0 Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI This will set the Rx FIFO 1 Get Index RXF1S F1GI to F1AI 1 and update the FIFO 1 Fill Level RXF1S F1FL 16 03 2015 35 M CAN Revision 3 2 1 2 3 34 Hx Buffer FIFO Element Size Configuration RXESC Configures the number of data bytes belonging to an Rx Buffer Rx FIFO element Data field sizes 28 bytes are intended for CAN FD operation only Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0x0 Bits 15 14 B R 0x0 RP 0x0 RP 0x0 RP 0x0 R Read P Protected write U undefined n value after reset Table 35 Rx Buffer FIFO Element Size Configuration address 0xBC 36 Bits 10 8 RBDS 2 0 Rx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Bits 6 4 F1DS 2 0 Rx FIFO 1 Data Field Size 000 7 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Bits 2 0 FODS 2 0 Rx FIFO 0 Data Field Size
44. 69 Table 57 Example Filter Configuration for Debug Messages mme 70 Table 58 Possible Configurations for Frame 72 Table 59 Tx Buffer FIFO Queue Element Size nennen nnns 73 Table 60 M Register OVErViGW Uu tanen EET Ld RR 77 Table 61 M CAN Module Interface l nacta ra bed aa RR ta bc rb a bed rade EE 81 16 03 2015 85 BOSCH
45. 9 ARAE Access to Reserved Address Enable Bit 28 PEDE Protocol Error in Data Phase Enable Bit 27 PEAE Protocol Error in Arbitration Phase Enable Bit 26 WDIE Watchdog Interrupt Enable Bit 25 BOE Bus_Off Status Interrupt Enable Bit 24 EWE Warning Status Interrupt Enable Bit 23 EPE Error Passive Interrupt Enable Bit 22 ELOE Error Logging Overflow Interrupt Enable Bit 21 BEUE Bit Error Uncorrected Interrupt Enable Bit 20 BECE Bit Error Corrected Interrupt Enable Bit 19 DRXE Message stored to Dedicated Rx Buffer Interrupt Enable Bit 18 TOOE Timeout Occurred Interrupt Enable Bit 17 MRAFE Message RAM Access Failure Interrupt Enable Bit 16 TSWE Timestamp Wraparound Interrupt Enable Bit 15 TEFLE Tx Event FIFO Event Lost Interrupt Enable Bit 14 TEFFE Tx Event FIFO Full Interrupt Enable Bit 13 TEFWE Tx Event FIFO Watermark Reached Interrupt Enable Bit 12 Tx Event FIFO New Entry Interrupt Enable 16 03 2015 23 M CAN Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 24 BOSCH TFEE TCFE TCE HPME RF1LE RF1FE RF1WE RF1NE RFOLE RFOFE RFOWE RFONE Revision 3 2 1 Tx FIFO Empty Interrupt Enable Transmission Cancellation Finished Interrupt Enable Transmission Completed Interrupt Enable High Priority Message Interrupt Enable Rx FIFO 1 Message Lost Interrupt Enable Rx FIFO 1 Full Interrupt Enable Rx FIFO 1 Watermark Reached Interrupt Enable Rx F
46. A write access to CCCR INIT will have no effect Now the module clock inputs m can hclk and m can cclk may be switched off To leave power down mode the application has to turn on the module clocks before resetting signal m can clkstop req resp CC Control Register flag CCCR CSR TheM CAN will acknowledge this by resetting output signal m can clkstop and resetting CCCR CSA Afterwards the application can restart CAN communication by resetting bit CCCR INIT Test Modes To enable write access to register TEST see Section 2 3 5 bit CCCR TEST has to be set to one This allows the configuration of the test modes and test functions Four output functions are available for the CAN transmit pin m can tx by programming TEST TX Additionally to its default function the serial data output it can drive the CAN Sample Point signal to monitor the M CAN s bit timing and it can drive constant dominant or recessive values The actual value at pin m can rx can be read from TEST RX Both functions can be used to check the CAN bus physical layer Due to the synchronization mechanism between CAN clock and Host clock domain there may be a delay of several Host clock periods between writing to TEST TX until the new configuration is visible at output pin m can tx This applies also when reading input pin m can rx via TEST RX 16 03 2015 Revision 3 2 1 M CAN Note Test modes should be used for production tests or self test only The software co
47. ANY TYPE OR NATURE ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SPECIFICATION SOFTWARE RELATED THERETO CODE AND OR PROGRAM ii 16 03 2015 Revision 3 2 1 M CAN RELATED THERETO INCLUDING BUT NOT LIMITED TO CLAIMS SUITS OR CAUSES OF ACTION INVOLVING ALLEGED INFRINGEMENT OF COPYRIGHTS PATENTS TRADEMARKS TRADE SECRETS OR UNFAIR COMPETITION INDEMNIFICATION TO THE MAXIMUM EXTEND PERMITTED BY LAW YOU AGREE TO INDEMNIFY AND HOLD HARMLESS THE INTELLECTUAL PROPERTY OWNERS COPYRIGHT HOLDERS AND CONTRIBUTORS AND EMPLOYEES AND ANY PERSON FROM AND AGAINST ALL CLAIMS LIABILITIES LOSSES CAUSES OF ACTION DAMAGES JUDGMENTS AND EXPENSES INCLUDING THE REASONABLE COST OF ATTORNEYS FEES AND COURT COSTS FOR INJURIES OR DAMAGES TO THE PERSON OR PROPERTY OF THIRD PARTIES INCLUDING WITHOUT LIMITATIONS CONSEQUENTIAL DIRECT AND INDIRECT DAMAGES AND ANY ECONOMIC LOSSES THAT ARISE OUT OF OR IN CONNECTION WITH YOUR USE MODIFICATION OR DISTRIBUTION OF THIS SPECIFICATION SOFTWARE RELATED THERETO CODE AND OR PROGRAM RELATED THERETO ITS OUTPUT OR ANY ACCOMPANYING DOCUMENTATION GOVERNING LAW THE RELATIONSHIP BETWEEN YOU AND ROBERT BOSCH GMBH SHALL BE GOVERNED SOLELY BY THE LAWS OF THE FEDERAL REPUBLIC OF GERMANY THE STIPULATIONS OF INTERNATIONAL CONVENTIONS REGARDING THE INTERNATIONAL SALE OF GOODS SHALL NOT BE APPLICABLE THE EXCLUSIVE LEGAL VENUE SHALL BE DUESSELDORF GERMANY MANDATORY LAW SHALL BE UNAFFECTED BY THE FOREGOING
48. Bits 15 14 13 12 1 10 9 8 7 86 5 4 3 2 1 0 FLST FIDX 6 0 MSI 1 0 BIDX 5 0 R 0 R 0x0 R 0x0 R 0x0 R Read n Value after reset Table 25 High Priority Message Status address 0x94 Bit 15 FLST Filter List Indicates the filter list of the matching filter element 0 Standard Filter List 1 Extended Filter List Bit 14 8 FIDX 6 0 Filter Index Index of matching filter element Range is 0 to SIDFC LSS 1 resp XIDFC LSE 1 Bit 7 6 MSI 1 0 Message Storage Indicator 00 No FIFO selected 01 FIFO message lost 10 Message stored in FIFO 0 11 Message stored in FIFO 1 Bit 5 0 BIDX 5 0 Buffer Index Index of Rx FIFO element to which the message was stored Only valid when MSI 1 1 16 03 2015 29 5 BOSCH M CAN Revision 3 2 1 2 3 25 New Data 1 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x98 ND31 ND30 ND29 ND28 ND27 ND26 ND25 ND24 ND23 ND22 ND21 ND20 ND19 ND18 ND17 ND16 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ND15 ND14 ND13 ND12 ND11 10 ND9 8 ND7 ND6 ND5 ND4 ND3 ND2 ND1 NDO RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Read n value after reset Table 26 New Data 1 address 0x98 Bi
49. CAN FD frame format according to 15011898 1 Bit 14 TXP Transmit Pause If this bit is set the M CAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame see Section 3 5 0 Transmit pause disabled 1 Transmit pause enabled Bit 13 EFBI Edge Filtering during Bus Integration 0 Edge filtering disabled 1 Two consecutive dominant tq required to detect an edge for hard synchronization Bit 12 PXHD Protocol Exception Handling Disable 0 Protocol exception handling enabled 1 Protocol exception handling disabled Note When protocol exception handling is disabled the M CAN will transmit an error frame when it detects a protocol exception condition Bit 9 BRSE Bit Rate Switch Enable 0 Bitrate switching for transmissions disabled 1 Bit rate switching for transmissions enabled Note When CAN FD operation is disabled FDOE 0 is not evaluated Bit 8 FDOE FD Operation Enable 0 FD operation disabled 1 operation enabled 16 03 2015 11 BOSCH M CAN Revision 3 2 1 Bit 7 TEST Test Mode Enable 0 Normal operation register TEST holds reset values 1 Test Mode write access to register TEST enabled Bit 6 DAR Disable Automatic Retransmission 0 Automatic retransmission of messages not transmitted successfully enabled 1 Automatic retransmission disabled Bit 5 MON Bus Monitoring Mode Bit MON can only be set by the Host when both CCE a
50. E 1 AND CCCR INIT 1 There is a delay from writing to a command register until the update of the related status register bits due to clock domain crossing ADDRESS SYMBOL NAME RESET ACC 0x00 CREL Core Release Register 7 rrrd dddd R 0x04 ENDN Endian ee 8 8765 4321 R 0x10 TEST Test Register 9 0000 0000 RP 0x14 RWD RAM Watchdog 10 0000 0000 RP 0x18 CCCR CC Control Register 0000 0001 RWPp 0x1C NBTP Nominal Bit Timing amp Prescaler Register 06000A03 RP 0x28 TOCC Timeout Counter Configuration FFFF0000 RP 0x2C TOCV Timeout Counter Value 0000 FFFF RC 0x30 3C reserved 4 0000 0000 R 0x40 ECR Error Counter dicia 00000000 RX 0x4C reserved 1 0000 0000 R 0x50 IR Interrupt Register 00000000 RW 0x54 IE Interrupt Enable 00000000 RW 0x58 ILS Interrupt Line Select 00000000 RW 0x80 GFC Global Filter Configuration 27 00000000 RP 0x84 SIDFC Standard ID Filter Configuration 28 00000000 RP Table 1 M CAN Register Map M CAN Revision 3 2 1 16 03 2015 5 M CAN Revision 3 2 1 ADDRESS SYMBOL NAME RESET ACC 0x88 XIDFC Extended ID Filter Configuration 28 00000000 RP 0x8C reserved 1 0000 0000 R 0x98 NDAT1 New Data 1 30 00000000 RW 0x9C NDAT2 New Data 2 30 00000000 RW RXFOC Rx FIFO 0 Configuration 31 00000000 RP 4 RXF0S Rx FIFO 0 Status 32 0000 0000 R 0xB0 RXF1C Rx FIFO 1 Configuration 00000000 RP 0xB4 RXF1S
51. E 1 1 accept non matching frames GFC ANFE 1 0 FIFO selected and target FIFO full blocking no store frame Figure 7 Extended Message ID Filter Path 66 16 03 2015 Revision 3 2 1 M CAN 3 4 2 Rx FIFOs Rx FIFO 0 and Rx FIFO 1 can be configured to hold up to 64 elements each Configuration of the two Rx FIFOs is done via registers and RXF1C Received messages that passed acceptance filtering are transferred to the Rx FIFO as configured by the matching filter element For a description of the filter mechanisms available for Rx FIFO 0 and Rx FIFO 1 see Section 3 4 1 The Rx FIFO element is described in Section 2 4 2 To avoid an Rx FIFO overflow the Rx FIFO watermark can be used When the Rx FIFO fill level reaches the Rx FIFO watermark configured by RXFnC FnWM interrupt flag IR RFnW is set When the Rx FIFO Put Index reaches the Rx FIFO Get Index an Rx FIFO Full condition is signalled by RXFnS FnF In addition interrupt flag IR RFnF is set Get Index 5 Put Index RXFnS FnPI Fill Level RXFnS FnFL Figure 8 Rx FIFO Status When reading from an Rx FIFO Rx FIFO Get Index RXFnS FnGI FIFO Element Size has to be added to the corresponding Rx FIFO start address RXFnC FnSA RXESC RBDS 2 0 Data Field FIFO Element Size RXESC FnDS 2 0 bytes RAM words 000 8 4 001 12 5 010 16 6 20 7 24 8 101 32 10 110 48 14 111 64 18
52. FIFO Queue Put Index TXFQS TFQPI 0 31 Element Size to the Tx Buffer Start Address TXBC TBSA 3 5 5 Mixed Dedicated Tx Buffers Tx FIFO In this case the Tx Buffers section in the Message RAM is subdivided into a set of Dedicated Tx Buffers and a Tx FIFO The number of Dedicated Tx Buffers is configured by TXBC NDTB The number of Tx Buffers assigned to the Tx FIFO is configured by TXBC TFQS In case TXBC TFQS is programmed to zero only Dedicated Tx Buffers are used Dedicated Tx Buffers Tx FIFO Buffer Index TxSequence 1 5 4 6 2 3 Get Index Put Index Figure 11 Example of mixed Configuration Dedicated Tx Buffers Tx FIFO Tx prioritization Scan Dedicated Tx Buffers and oldest pending Tx FIFO Buffer referenced by TXFS TFGI Buffer with lowest Message ID gets highest priority and is transmitted next 74 16 03 2015 BOSCH Revision 3 2 1 M CAN 3 5 6 Mixed Dedicated Tx Buffers Tx Queue In this case the Tx Buffers section in the Message RAM is subdivided into a set of Dedicated Tx Buffers and a Tx Queue The number of Dedicated Tx Buffers is configured by TXBC NDTB The number of Tx Queue Buffers is configured by TXBC TFQS In case TXBC TFQS is programmed to zero only Dedicated Tx Buffers are used Dedicated Tx Buffers Tx Queue Buffer Index Tx Sequence 2 5 4 6 3 1 Put Index Figure 12 Example of mixed Configuration Dedicated Tx Buffers Tx Queue Tx prioritization Scan all Tx Buffers
53. Full Rx FIFO 1 not full Rx FIFO 1 full RF1W Rx FIFO 1 Watermark Reached Rx FIFO 1 fill level below watermark Rx FIFO 1 fill level reached watermark RF1N Rx FIFO 1 New Message No new message written to Rx FIFO 1 New message written to Rx FIFO 1 RFOL Rx FIFO 0 Message Lost No Rx FIFO 0 message lost Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero RFOF Rx FIFO 0 Full Rx FIFO 0 not full Rx FIFO 0 full RFOW Rx FIFO 0 Watermark Reached Rx FIFO 0 fill level below watermark Rx FIFO 0 fill level reached watermark RFON Rx FIFO 0 New Message No new message written to Rx FIFO 0 New message written to Rx FIFO 0 16 03 2015 BOSCH Revision 3 2 1 M CAN 2 3 17 Interrupt Enable IE The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signalled on an interrupt line 0 Interrupt disabled 1 Interrupt enabled Bits 31 30 2 2 27 26 2 2 2 2 21 20 19 18 17 16 R 0x0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 fens TEFFE TEFNE TFEE TCFE TCE HPME RF1FE RFOLE RFOFE RFOWE RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Read W Write n value after reset Table 18 Interrupt Enable address 0x54 Bit 2
54. Handler handles transmission requests for the dedicated Tx Buffers the Tx FIFO and the Tx Queue It controls the transfer of transmit messages to the CAN Core the Put and Get Indices and the Tx Event FIFO Up to 32 Tx Buffers can be set up for message transmission The CAN mode for transmission Classic CAN or CAN FD can be configured separately for each Tx Buffer element The Tx Buffer element is described in Section 2 4 3 Table 58 below describes the possible configurations for frame transmission CCCR Tx Buffer Element Frame Transmission ignored 0 ignored ignored Classic CAN 0 0 Classic CAN 1 ignored FD without bit rate switching Classic CAN 1 0 FD without bit rate switching 1 FD with bit rate switching Table 58 Possible Configurations for Frame Transmission 0 1 Note AUTOSAR requires at least three Tx Queue Buffers and support of transmit cancellation The Tx Handler starts a Tx scan to check for the highest priority pending Tx request Tx Buffer with lowest Message ID when the Tx Buffer Request Pending register TXBRP is updated or when a transmission has been started 3 5 1 Transmit Pause The transmit pause feature is intended for use in CAN systems where the CAN message identifiers are permanently specified to specific values and cannot easily be changed These message identifiers may have a higher CAN arbitration priority than other defined messages while in a specific application their relative
55. IFO 1 New Message Interrupt Enable Rx FIFO 0 Message Lost Interrupt Enable Rx FIFO 0 Full Interrupt Enable Rx FIFO 0 Watermark Reached Interrupt Enable Rx FIFO 0 New Message Interrupt Enable 16 03 2015 Revision 3 2 1 M CAN 2 3 18 Interrupt Line Select ILS The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines For interrupt generation the respective interrupt line has to be enabled via ILE EINTO and ILE EINT1 0 Interrupt assigned to interrupt line m can intO 1 Interrupt assigned to interrupt line m can int1 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E 0 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEFNL TFEL TCFL TCL HPML RF1LL RF1FL RFTWL RFINL RFOLL RFOFL RFOWL RFONL E TEFFL TEFWL RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Read W Write n value after reset Table 19 Interrupt Line Select address 0x56 Bit 29 ARAL Access to Reserved Address Line Bit 28 PEDL Protocol Error in Data Phase Line Bit 27 PEAL Protocol Error in Arbitration Phase Line Bit 26 WDIL Watchdog Interrupt Line Bit 25 BOL Bus Status Interrupt Line Bit 24 EWL Warning Status Interrupt Line Bit 23 EPL Error Passiv
56. IFO element In addition the flag IR DRX Message stored in Dedicated Rx Buffer in the interrupt register is set Filter SFID1 10 0 SFID2 10 9 SFID2 5 0 Element EFID1 28 0 EFID2 10 9 EFID2 5 0 0 ID message 1 00 00 0000 1 ID message 2 00 00 0001 ID message 3 00 00 0010 Example Filter Configuration for Rx Buffers After the last word of a matching received message has been written to the Message RAM the respective New Data flag in register NDAT1 2 is set As long as the New Data flag is set the respective Rx Buffer is locked against updates from received matching frames The New Data flags have to be reset by the Host by writing a 1 to the respective bit position While an Rx Buffer s New Data flag is set a Message ID Filter Element referencing this specific Rx Buffer will not match causing the acceptance filtering to continue Following Message ID Filter Elements may cause the received message to be stored into another Rx Buffer or into an Rx FIFO or the message may be rejected depending on filter configuration 3 4 3 1 Buffer Handling Resetinterrupt flag IR DRX Read New Data registers Read messages from Message RAM Reset New Data flags of processed messages 16 03 2015 69 M CAN Revision 3 2 1 3 4 4 Debug on CAN Support Debug messages are stored into Rx Buffers For debug handling three consecutive Rx buffers e g 61 62 63 have to be used for storage of debug mess
57. It is not necessary to configure each of the sections listed in Figure 2 nor is there any restriction with respect to the sequence of the sections When operated in CAN FD mode the required Message RAM size strongly depends on the element size configured for Rx FIFOO Rx FIFO1 Rx Buffers and Tx Buffers via RXESC FODS RXESC F1DS RXESC RBDS and TXESC TBDS Start Address SIPEG FESS 0 128 elements 0 128 words AIBFGIPEESA 0 64 elements 0 128 words RXFOC FOSA 0 64 elements 0 1152 words RXF1C F1SA max 4352 words 0 64 elements 0 1152 words RXBC RBSA 0 64 elements 0 1152 words TAERC ETOA 0 32 elements 0 64 words TXBC TBSA Y LL 0 32 elements 0 576 words a 32 bit Figure 2 Message RAM Configuration When the M CAN addresses the Message RAM it addresses 32 bit words not single bytes The configurable start addresses are 32 bit word addresses i e only bits 15 to 2 are evaluated the two least significant bits are ignored Note The M CAN does not check for erroneous configuration of the Message RAM Especially the configuration of the start addresses of the different sections and the number of elements of each section has to be done carefully to avoid falsification or loss of data 46 16 03 2015 BOSCH Revision 3 2 1 M CAN 2 4 2 Rx Buffer and FIFO Element Up to 64 Rx Buffers and two Rx FIFOs can be configured in the Message RAM Each Rx FIFO section can be configured to store up to 64 received mess
58. LC in CAN FD In CAN FD frames the bit timing will be switched inside the frame after the BRS Bit Rate Switch bit if this bit is recessive Before the BRS bit in the CAN FD arbitration phase the nominal CAN bit timing is used as defined by the Nominal Bit Timing amp Prescaler Register NBTP In the following CAN FD data phase the data phase bit timing is used as defined by the Data Bit Timing amp Prescaler Register DBTP The bit timing is switched back from the data phase timing at the CRC delimiter or when an error is detected whichever occurs first The maximum configurable bit rate in the CAN FD data phase depends on the CAN clock frequency m can cclk Example with a CAN clock frequency of 20MHz and the shortest configurable bit time of 4 tq the bit rate in the data phase is 5 Mbit s In both data frame formats CAN FD and CAN FD with bit rate switching the value of the bit ESI Error Status Indicator is determined by the transmitter s error state at the start of the transmission If the transmitter is error passive ESI is transmitted recessive else it is transmitted dominant 3 1 4 Transmitter Delay Compensation During the data phase of a CAN FD transmission only one node is transmitting all others are receivers The length of the bus line has no impact When transmitting via pin m can tx the M CAN receives the transmitted data from its local CAN transceiver via pin m can rx The received data is delayed by the transmitter de
59. M interrupt flag IR TEFW is set When reading from the Tx Event FIFO two times the Tx Event FIFO Get Index TXEFS EFGI has to be added to the Tx Event FIFO start address TXEFC EFSA FIFO Acknowledge Handling The Get Indices of Rx FIFO 0 Rx FIFO 1 and the Tx Event FIFO are controlled by writing to the corresponding FIFO Acknowledge Index see Section 2 3 29 Section 2 3 33 and Section 2 3 47 Writing to the FIFO Acknowledge Index will set the FIFO Get Index to the FIFO Acknowledge Index plus one and thereby updates the FIFO Fill Level There are two use cases When only a single element has been read from the FIFO the one being pointed to by the Get Index this Get Index value is written to the FIFO Acknowledge Index When a sequence of elements has been read from the FIFO it is sufficient to write the FIFO Acknowledge Index only once at the end of that read sequence value Index of the last element read to update the FIFO s Get Index Due to the fact that the CPU has free access to the M CAN s Message RAM special care has to be taken when reading FIFO elements in an arbitrary order Get Index not considered This might be useful when reading a High Priority Message from one of the two Rx FIFOs In this case the FIFO s Acknowledge Index should not be written because this would set the Get Index to a wrong position and also alters the FIFO s Fill Level In this case some of the older FIFO elements would be lost Note The applicat
60. O RO RO RO RO RO RO RO RO RO Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO R O RO R 0 RO RO R O RO R O R O RO R O RO R O RO R Read n value after reset Table 43 Transmit Buffer Cancellation Finished address OxDC Bit 31 0 CF 31 0 Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR In case the corresponding TXBRP bit was not set at the point of cancellation CF is set immediately The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR 0 No transmit buffer cancellation 1 Transmit buffer cancellation finished 42 16 03 2015 Revision 3 2 1 M CAN 2 3 43 Tx Buffer Transmission Interrupt Enable TXBTIE Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OxEO TIE31 TIE29 TIE28 TIE27 TIE26 TIE25 TIE24 TIE23 TIE22 TIE21 TIE20 TIE19 TIE18 TIE17 TIE16 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIE15 TIE14 TIE13 12 TIE11 TIE10 TIE9 TIE8 TIE7 TIE6 TIES 4 TIE2 TIEO RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Read W Write n value after reset Table
61. PARAGRAPHS INTELLECTUAL PROPERTY OWNERS COPYRIGHT OWNERS CONTRIBUTORS ROBERT BOSCH GMBH ROBERT BOSCH PLATZ 1 70839 GERLINGEN GERMANY AND ITS LICENSORS 16 03 2015 iii M CAN Revision 3 2 1 SPECIFICATION REVISION HISTORY REVISION DATE NOTES 0 1 18 01 2008 initial working revision 0 2 12 02 2008 first revised working revision 0 3 10 03 2008 second revised working revision 0 5 22 07 2008 fourth revised working revision 0 6 24 10 2008 fifth revised working revision 1 0 25 03 2009 first complete revision 1 1 25 06 2009 Tx Handler functionality updated 1 21 10 02 2010 address 0x08 reserved for customer defined register 1 22 26 11 2010 minor textual enhancements 1 23 18 02 2011 typos corrected 2 0 27 10 2011 debug on CAN dedicated Rx Buffers CAN FD Extension IF 2 0 1 12 03 2012 minor corrections interface signals to Clock Calibration on CAN unit updated 2 0 2 23 05 2012 Section 3 1 3 CAN FD Operation corrected 3 0 17 10 2012 FIFO overwrite mode transmit pause support of CAN FD 64 byte frames 3 0 1 26 11 2012 registers FBTP and TEST updated minor textual enhancements 3 0 2 14 02 2013 Section 2 4 1 Message RAM Configuration corrected minor corrections enhancements iv 16 03 2015 Revision 3 2 1 M CAN REVISION DATE NOTES 3 1 0 22 07 2014 Register FBTP renamed to DBTP and restructured TDCO moved to new register TDCR increased configuration range for da
62. S u e LS Es G Qo Deo Qo e Oo Ke E 8 FS FS FS Fe S eS Fe Fe FS x Le oau 0 032 001 049 n o a n __ S w s w Zo zo n 2 z oi eo lt o es n Lal rau vuv v49 1 sau ES SHO SOL 840 1 urs ai so n r zw o 230 n jw am so 830 n mS eau BS 640 601 639 n f oa 0LOL 0130 1 30 D m na L LLOL wao usu 39 m e AEM ZLOL 2 30 30 J got BER BER LOL e9 ea 40 DENEN i nau FUN FLH 7 7130 1 30 SSS Deeg LST get BER SLOL s9 sau 40 u e eau 9 9149 9LOL au 30 See ao 40 I get grav 8149 SOL so 40 i a ds eia 6142 6LOL eau 39 Je oan RES 0259 0201 0249 1 30 Lan Lzuv 101 1230 39 C C ag 8 ont 223 2230 2201 2220 1 amp eza zuv zuo 2201 e240 n 0 jJ IS redu 210 FEH 1 30 43 SCH SCH SZOL 9230 1 39 au 8 aan 9zuv 9280 9201 9230 1 39 2 i 5 son zzv em 2201 2280 n 40 2 O edu 8280 8201 8230 1 30 D _ Ee eau
63. a TXBC The bits remain set until the corresponding bit of TXBRP is reset 0 No cancellation pending 1 Cancellation pending 16 03 2015 41 M CAN Revision 3 2 1 2 3 41 Tx Buffer Transmission Occurred Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OxD8 TO31 TO29 TO28 TO27 26 TO25 024 TO23 TO22 TO21 20 TO19 18 TO17 TO16 R 0 R0 RO RO RO RO RO RO RO RO RO RO RO RO RO RO Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TO15 TO14 TO13 TO12 TO11 TO10 9 TO8 7 TOS TO4 TOS TO1 TOO R 0 R0 RO RO RO RO RO RO RO RO RO RO RO RO RO RO R Read n value after reset Table 42 Tx Buffer Transmission Occurred address OxD8 Bit 31 0 TO 31 0 Transmission Occurred Each Tx Buffer has its own Transmission Occurred bit The bits are set when the corresponding TXBRP bit is cleared after a successful transmission The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR 0 transmission occurred 1 Transmission occurred 2 3 42 Tx Buffer Cancellation Finished TXBCF Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OxDC CF31 CF30 CF29 CF28 CF27 CF26 CF25 CF24 CF23 CF22 CF21 CF20 CF19 CF18 CF17 CF16 R 0 R 0 RO RO RO RO R
64. able 12 Timeout Counter Configuration address 0x28 Bit 31 16 TOP 15 0 Timeout Period Start value of the Timeout Counter down counter Configures the Timeout Period Bits 2 1 TOS 1 0 Timeout Select When operating in Continuous mode a write to TOCV presets the counter to the value configured by TOCC TOP and continues down counting When the Timeout Counter is controlled by one of the FIFOs an empty FIFO presets the counter to the value configured by TOCC TOP Down counting is started when the first FIFO element is stored 00 Continuous operation 01 Timeout controlled by Tx Event FIFO 10 Timeout controlled by Rx FIFO 0 11 Timeout controlled by Rx FIFO 1 Bit 0 ETOC Enable Timeout Counter 0 Timeout Counter disabled 1 Timeout Counter enabled Note For use of timeout function with CAN FD see Section 3 3 2 3 12 Timeout Counter Value TOCV Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x2C res R 0x0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TOC 15 0 RC OxFFFF R Read C Clear on write n value after reset Table 13 Timeout Counter Value address 0x2C Bit 15 0 TOC 15 0 Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times 1 16 depending on the configuration of TSCC TCP When decremented to zero interrupt flag IR TOO is set and the Timeout Counter is stopped Start and reset restart conditions are configured via TOCC TOS 16 03 2015 15
65. ages The structure of a Rx Buffer FIFO element is shown in Table 49 below The element size can be configured for storage of CAN FD messages with up to 64 bytes data field via register RXESC 31 24 23 16 15 8 7 0 Py 90 bn EIE ID 28 0 o Ju lo R1Z FIDX 6 0 a X DLC 30 RXTS 15 0 lt um R2 DB3 7 0 DB2 7 0 DB1 7 0 DBO 7 0 DB7 7 0 DB6 7 0 DB5 7 0 DB4 7 0 Rn DBm 7 0 DBm 1 7 0 DBm 2 7 0 DBm 3 7 0 Table 49 Rx Buffer and FIFO Element RO Bit 31 ESI Error State Indicator 0 Transmitting node is error active 1 Transmitting node is error passive RO Bit 30 XTD Extended Identifier Signals to the Host whether the received frame has a standard or extended identifier 0 11 bit standard identifier 1 29 bit extended identifier RO Bit 29 RTR Remote Transmission Request Signals to the Host whether the received frame is a data frame or a remote frame 0 Received frame is a data frame 1 Received frame is a remote frame Note There are no remote frames in CAN FD format In CAN FD frames FDF 1 the dominant RRS Remote Request Substitution bit replaces bit RTR Remote Transmission He quest RO Bits 28 0 ID 28 0 Identifier Standard or extended identifier depending on bit XTD A standard identifier is stored into ID 28 18 R1 Bit 31 ANMF Accepted Non matching Frame Acceptance of non matching frames may be enabled via GFC ANFS and GFC ANFE 0 Receiv
66. ages A B and C The format is the same as for an Rx Buffer or an Rx FIFO element see M CAN User s Manual section 2 4 2 Advantage Fixed start address for the DMA transfers relative to RXBC RBSA no additional configuration required For filtering of debug messages Standard Extended Filter Elements with SFEC EFEC 111 have to be set up Messages matching these filter elements are stored into the Rx Buffers addressed by SFID2 EFID2 5 0 After message C has been stored the DMA request output m can dma req is activated and the three messages can be read from the Message RAM under DMA control The RAM words holding the debug messages will not be changed by the M CAN while m can dma req is activated The behaviour is similar to that of an Rx Buffers with its New Data flag set After the DMA has completed the DMA unit sets m can dma ack This resets m can dma req Now the M CAN is prepared to receive the next set of debug messages 3 4 4 1 Filtering for Debug Messages Table 57 Filtering for debug messages is done by configuring one Standard Extended Message ID Filter Element for each of the three debug messages To enable a filter element to filter for debug messages SFEC EFEC has to be programmed to 111 In this case fields SFID1 SFID2 and EFID1 EFID2 have a different meaning see Section 2 4 5 and Section 2 4 6 While SFID2 EFID2 10 9 controls the debug message handling state machine SFID2 EFID2 5 0 controls
67. aler are 0 to 511 The actual interpretation by the hardware of this value is such that one more than the value programmed here is used Bits 15 8 NTSEG1 7 0 Nominal Time segment before sample point 0x01 OxFF Valid values are 1 to 255 The actual interpretation by the hardware of this value is such that one more than the programmed value is used Bits 6 0 NTSEG2 6 0 Nominal Time segment after sample point 0x00 Ox7F Valid values are 0 to 127 The actual interpretation by the hardware of this value is such that one more than the programmed value is used Note With a CAN clock m can cclk of 8 MHz the reset value of 0x06000A03 configures the M CAN for a bit rate of 500 kBit s 16 03 2015 13 M CAN Revision 3 2 1 2 3 9 Timestamp Counter Configuration TSCC For a description of the Timestamp Counter see Section 3 2 Timestamp Generation Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0x0 RP 0x0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTT E R 0x0 RP 0x0 R Read P Protected write value after reset Table 10 Timestamp Counter Configuration address 0x20 Bit 19 16 TCP 3 0 Timestamp Counter Prescaler 0x0 0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times 1 16 The actual interpretation by the hardware of this value is such that one more than the value programmed here is used Note With CAN FD an external counter is required for timestamp generation TSS
68. andard 0 Filter remote frames with 11 bit standard IDs 1 Reject all remote frames with 11 bit standard IDs Bit 0 RRFE Reject Remote Frames Extended 0 Filter remote frames with 29 bit extended IDs 1 Reject all remote frames with 29 bit extended IDs 16 03 2015 27 M CAN Revision 3 2 1 2 3 21 Standard ID Filter Configuration SIDFC Settings for 11 bit standard Message ID filtering The Standard ID Filter Configuration controls the filter path for standard messages as described in Figure 6 Bits 31 30 29 2 27 26 25 24 2 22 21 20 19 18 17 16 R 0x0 RP 0x0 Bits 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 x e RP 0x0 R 0x0 R Read P Protected write n value after reset Table 22 Standard ID Filter Configuration address 0x84 Bit 23 16 LSS 7 0 List Size Standard 0 No standard Message ID filter 1 128 Number of standard Message ID filter elements gt 128 Values greater than 128 are interpreted as 128 Bit 15 2 FLSSA 15 2 Filter List Standard Start Address Start address of standard Message ID filter list 32 bit word address see Figure 2 2 3 22 Extended ID Filter Configuration XIDFC Settings for 29 bit extended Message ID filtering The Extended ID Filter Configuration controls the filter path for standard messages as described in Figure 7 Bits 31 30 2 2 27 26 25 24 2 22 21 20 19 18 17 16 0x88 res LSE 6 0 R 0x0 RP 0x0 Bits 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 FLESA 15 2 res RP 0x
69. arted at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful The corresponding TXBCF bit is set for all unsuccessful transmissions No transmission request pending Transmission request pending Note bits which are set while a Tx scan is in progress are not considered during this particular Tx scan In case a cancellation is requested for such a Tx Buffer this Add Request is cancelled immediately the corresponding bit is reset 16 03 2015 Revision 3 2 1 M CAN 2 3 39 Tx Buffer Add Request TXBAR Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OxDO AR31 AR30 AR29 AR28 AR27 AR26 AR25 AR24 AR23 AR22 AR21 AR20 AR19 AR18 AR17 AR16 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AR15 AR14 AR13 AR12 AR11 AR10 ARQ AR8 AR7 AR6 ARS ARA AR3 AR2 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Read W Write n value after reset Table 40 Tx Buffer Add Request address OxDO Bit 31 0 AR 31 0 Add Request Each Tx Buffer has its own Add Request
70. bit Writing a 1 will set the corresponding Add Request bit writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR TXBAR bits are set only for those Tx Buffers configured TXBC When no Tx scan is running the bits are reset immediately else the bits remain set until the Tx scan process has completed 0 No transmission request added 1 Transmission requested added Note If an add request is applied for a Tx Buffer with pending transmission request corre sponding bit already set this add request is ignored 2 3 40 Tx Buffer Cancellation Request TXBCR RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CRS CR2 CR1 CRO RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Read W Write n value after reset Table 41 Tx Buffer Cancellation Request address OxD4 Bit 31 0 CR 31 0 Cancellation Request Each Tx Buffer has its own Cancellation Request bit Writing a 1 will set the corresponding Cancellation Request bit writing a 0 has no impact This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR TXBCR bits are set only for those Tx Buffers configured vi
71. ble 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 84 M CAN Register aa AEREE geb e e ee 5 Core Release Register addresses 0X00 eene 7 Example for Coding of RevisiOris cci dtr Y RE ER YE ER DATA ES 7 Endian Register address 0x04 U nennen nnns 8 Data Bit Timing 4 Prescaler Register address 8 Test Register address 0x10 U U U U U uuu 9 RAM Watchdog address 0Xx14 U 10 CC Control Register address 0 18 11 Nominal Bit Timing 4 Prescaler Register address 1 13 Timestamp Counter Configuration address 0x20 14 Timestamp Counter Value address 0x24 l enne 14 Timeout Counter Configuration address 0x28 15 Timeout Counter Value address OX2C uuu 15 Error Counter Register address 0x40 a aa 16 Protocol Status Register address 0 44
72. clock domains Note In order to achieve a stable function of the M CAN the Host clock must always be faster than or equal to the CAN clock Also the modulation depth of a spread spectrum clock has to be regarded 1 4 Dual Interrupt Lines The module provides two interrupt lines Interrupts can be routed either to m can Int to m can int1 By default all interrupts are routed to interrupt line m can Int By programming ILE EINTO and ILE EINT1 the interrupt lines can be enabled or disabled separately 16 03 2015 3 BOSCH M CAN Revision 3 2 1 4 16 03 2015 BOSCH Chapter 2 2 Programmer s Model 2 1 Hardware Reset Description After hardware reset the registers of the M CAN hold the reset values listed in Table 1 Additionally the Bus Off state is reset and the output m can tx is set to recessive HIGH The value 0x0001 CCCR INIT 1 in the CC Control Register enables software initialization The M CAN does not influence the CAN bus until the CPU resets CCCR INIT to 0 2 2 Register Map The M CAN module allocates an address space of 256 bytes All registers are organized as 32 bit registers The M CAN is accessible by the Host CPU via the Generic Slave Interface using a data width of 8 bit byte access 16 bit half word access or 32 bit word access Write access by the Host CPU to registers bits marked with P Protected Write is possible only with CCCR CC
73. d Tx Buffers Example For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO 38 16 03 2015 Revision 3 2 1 M CAN 2 3 37 Tx Buffer Element Size Configuration TXESC Configures the number of data bytes belonging to a Tx Buffer element Data field sizes gt 8 bytes are intended for CAN FD operation only Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ R 0x0 RP 0x0 R Read P Protected write U undefined n value after reset Table 38 Tx Buffer Element Size Configuration address 0xC8 Bits 2 0 TBDS 2 0 Tx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC TBDS the bytes not defined by the Tx Buffer are transmitted as OxCC padding bytes 16 03 2015 39 M CAN Revision 3 2 1 2 3 38 Tx Buffer Request Pending TXBRP Bits 31 30 2 2 27 2 2 24 23 22 21 20 19 18 17 16 OxCC TRP31 TRP30 TRP29 TRP28 TRP27 TRP26 TRP25 TRP24 TRP23 TRP22 TRP21
74. e Interrupt Line Bit 22 ELOL Error Logging Overflow Interrupt Line Bit 21 BEUL Bit Error Uncorrected Interrupt Line Bit 20 BECL Bit Error Corrected Interrupt Line Bit 19 DRXL Message stored to Dedicated Rx Buffer Interrupt Line Bit 18 TOOL Timeout Occurred Interrupt Line Bit 17 MRAFL Message RAM Access Failure Interrupt Line Bit 16 TSWL Timestamp Wraparound Interrupt Line Bit 15 TEFLL Tx Event FIFO Event Lost Interrupt Line Bit 14 TEFFL Tx Event FIFO Full Interrupt Line Bit 13 TEFWL Tx Event FIFO Watermark Reached Interrupt Line Bit 12 TEFNL Tx Event FIFO New Entry Interrupt Line 16 03 2015 25 M CAN Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 TFEL TCFL TCL HPML RF1LL RF1WL RF1NL RFOLL RFOFL RFOWL RFONL Revision 3 2 1 Tx FIFO Empty Interrupt Line Transmission Cancellation Finished Interrupt Line Transmission Completed Interrupt Line High Priority Message Interrupt Line Rx FIFO 1 Message Lost Interrupt Line Rx FIFO 1 Full Interrupt Line Rx FIFO 1 Watermark Reached Interrupt Line Rx FIFO 1 New Message Interrupt Line Rx FIFO 0 Message Lost Interrupt Line Rx FIFO 0 Full Interrupt Line Rx FIFO 0 Watermark Reached Interrupt Line Rx FIFO 0 New Message Interrupt Line 2 3 19 Interrupt Line Enable ILE Each of the two interrupt lines to the CPU can be enabled disabled separately by programming bits EINTO and EINT1 Bits 3
75. e frozen while Error Logging ECR CEL is active The Host can set the M CAN into Restricted Operation mode by setting bit CCCR ASM The bit can only be set by the Host when both CCCR CCE and CCCR INIT are set to 1 The bit can be reset by the Host at any time Restricted Operation Mode is automatically entered when the Tx Handler was not able to read data from the Message RAM in time To leave Restricted Operation Mode the Host CPU has to reset CCCR ASM The Restricted Operation Mode can be used in applications that adapt themselves to different CAN bit rates In this case the application tests different bit rates and leaves the Restricted Operation Mode after it has received a valid frame If the M CAN is connected to a Clock Calibration on CAN unit CCCR ASM is controlled by input m can cok In case m can cok switches to 0 bit CCCR ASM is set When m can cok switches back to 1 bit CCCR ASM returns to the previously written value When there is no Clock Calibration on CAN unit connected input m can cok is hardwired to 1 Note The Restricted Operation Mode must not be combined with the Loop Back Mode internal or external 3 1 6 Bus Monitoring Mode Figure 4 16 03 2015 The M_CAN is set in Bus Monitoring Mode by programming CCCR MON to one In Bus Monitoring Mode see 15011898 1 10 12 Bus monitoring the M CAN is able to receive valid data frames and valid remote frames but cannot start a transmission In t
76. ed and frames are transmitted in Classic CAN format With CCCR FDOE 1 and CCCR BRSE 0 only bit of a Tx Buffer element is evaluated With CCCR FDOE 1 and CCCR BRSE 1 transmission of CAN FD frames with bit rate switching is enabled All Tx Buffer elements with bits FDF and BRS set are transmitted in CAN FD format with bit rate switching A mode change during CAN operation is only recommended under the following conditions The failure rate in the CAN FD data phase is significant higher than in the CAN FD arbitration phase In this case disable the CAN FD bit rate switching option for transmissions During system startup all nodes are transmitting Classic CAN messages until it is verified that they are able to communicate in CAN FD format If this is true all nodes switch to CAN FD operation Wake up messages in CAN Partial Networking have to be transmitted in Classic CAN format End of line programming in case not all nodes are CAN FD capable Non CAN FD nodes are held in Silent mode until programming has completed Then all nodes switch back to Classic CAN communication 56 16 03 2015 Revision 3 2 1 M CAN Table 54 In the CAN FD format the coding of the DLC differs from the standard CAN format The DLC codes 0 to 8 have the same coding as in standard CAN the codes 9 to 15 which in standard CAN all code a data field of 8 bytes are coded according to Table 54 below Lus Coding of D
77. ed frame matching filter index FIDX 1 Received frame did not match any Rx filter element 16 03 2015 47 5 BOSCH M CAN Revision 3 2 1 R1 30 24 FIDX 6 0 Filter Index 0 127 Index of matching Rx acceptance filter element invalid if ANMF 1 Range is 0 to SIDFC LSS 1 resp XIDFC LSE 1 R1 Bit 21 FD Format 0 Standard frame format 12 CAN FD frame format new DLC coding and CRC R1 Bit 20 BRS Bit Rate Switch 0 Frame received without bit rate switching 1 Frame received with bit rate switching R1 Bits 19 16 DLC 3 0 Data Length Code 0 8 CAN CAN FD received frame has 0 8 data bytes 9 15 CAN received frame has 8 data bytes 9 15 CAN FD received frame has 12 16 20 24 32 48 64 data bytes R1 Bits 15 0 RXTS 15 0 Rx Timestamp Timestamp Counter value captured on start of frame reception Resolution depending on configuration of the Timestamp Counter Prescaler TSCC TCP R2 Bits 31 24 DB3 7 0 Data Byte R2 Bits 23 16 DB2 7 0 Data Byte 2 R2 Bits 15 8 DB1 7 0 Data Byte 1 R2 Bits 7 0 DBO 7 0 Data Byte 0 R3 Bits 31 24 DB7 7 0 Data Byte 7 R3 Bits 23 16 DB6 7 0 Data Byte 6 R3 Bits 15 8 DB5 7 0 Data Byte 5 R3 Bits 7 0 DB4 7 0 Data Byte 4 Rn Bits 31 24 DBm 7 0 Data Byte m Rn Bits 23 16 DBm 1 7 0 Data Byte m 1 Rn Bits 15 8 DBm 2 7 0 Data Byte m 2 Rn Bits 7 0 DBm 3 7 0 Data Byte m 3 Note Depending on the configuration of the element size RXESC between two and
78. edge TXEFA Bits 31 30 29 28 27 26 2 24 2 22 21 20 19 18 17 16 OxF8 res R 0x0 Bits 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 res EFAI 4 0 R 0x0 RW 0x0 R Read W Write n value after reset Table 48 Tx Event FIFO Acknowledge address 0xF8 Bit 4 0 EFAI 4 0 Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI This will set the Tx Event FIFO Get Index TXEFS EFGI to EFAI 1 and update the Event FIFO Fill Level TXEFS EFFL 16 03 2015 45 BOSCH M CAN Revision 3 2 1 2 4 Message RAM For storage of Rx Tx messages and for storage of the filter configuration a single or dual ported Message RAM has to be connected to the M_CAN module Note In case the Message RAM is equipped with parity or ECC functionality itisrecommended to initialize the Message RAM after hardware reset by writing e g 0x00000000 to each Message RAM word to create valid parity ECC checksums This avoids that reading from uninitialized Message RAM sections will activate interrupt IR BEC Bit Error Corrected or IR BEU Bit Error Uncorrected 2 4 1 Message RAM Configuration The Message RAM has a width of 32 bits In case parity checking or ECC is used a respective number of bits has to be added to each word The M CAN module can be configured to allocate up to 4352 words in the Message RAM
79. ent 2 3 2 Core Release Register CREL Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x00 REL 3 0 STEP 3 0 SUBSTEP 3 0 YEAR 3 0 R r R r R r R d Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R d R d R Read r release d time stamp value defined at synthesis by generic parameter Table 2 Core Release Hegister addresses 0 00 Bits 31 28 REL 3 0 Core Release One digit BCD coded Bits 27 24 STEP 3 0 Step of Core Release One digit BCD coded Bits 23 20 SUBSTEP 3 0 Sub step of Core Release One digit BCD coded Bits 19 16 YEAR 3 0 Time Stamp Year One digit BCD coded This field is set by generic parameter on M CAN synthesis Bits 15 8 MON 7 0 Time Stamp Month Two digits BCD coded This field is set by generic parameter on M CAN synthesis Bits 7 0 DAY 7 0 Time Stamp Day Two digits BCD coded This field is set by generic parameter on M CAN synthesis Release Step SubStep Year Month Day Name 0 2 0 9 03 26 Revision 0 2 0 Date 2009 03 26 Table 3 Example for Coding of Revisions 16 03 2015 7 M CAN Revision 3 2 1 2 3 3 Endian Register ENDN Bits 31 30 29 28 27 26 2 24 2 22 21 20 19 18 17 16 0x04 ETV 81 16 R 0x8765 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETV 15 0 R 0x4321 R Read t test value Table 4 Endian Register address 0x04 Bits 31 0 ETV 31 0 Endianness Test Value The endianness test value is 0x87654321 2 3 4
80. er element has to be configured with SF1ID SF2ID resp EF1ID EF2ID 3 4 1 3 Classic Bit Mask Filter Classic bit mask filtering is intended to filter groups of Message IDs by masking single bits of a received Message ID With classic bit mask filtering SF1ID EF1ID is used as Message ID filter while SF2ID EF2ID is used as filter mask A zero bit at the filter mask will mask out the corresponding bit position of the configured ID filter e g the value of the received Message ID at that bit position is not relevant for acceptance filtering Only those bits of the received Message ID where the corresponding mask bits are one are relevant for acceptance filtering In case all mask bits are one a match occurs only when the received Message ID and the Message ID filter are identical If all mask bits are zero all Message IDs match 64 16 03 2015 Revision 3 2 1 M CAN 3 4 1 4 Standard Message ID Filtering Figure 6 below shows the flow for standard Message ID 11 bit Identifier filtering The Standard Message ID Filter element is described in Section 2 4 5 Controlled by the Global Filter Configuration GFC and the Standard ID Filter Configuration SIDFC Message ID Remote Transmission Request bit RTR and the Identifier Extension bit IDE of received frames are compared against the list of configured filter elements valid frame received 11 29 bit identifier GFC RRFS 1 reject remote frames no GFC RRFS
81. ess OxA4 Bit 25 RFOL Rx FIFO 0 Message Lost This bit is a copy of interrupt flag IR RFOL When IR RFOL is reset this bit is also reset 0 No Rx FIFO 0 message lost 12 RxFIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note Overwriting the oldest message when RXFOC F0OM 1 will not set this flag Bit 24 FOF Rx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full Bit 21 16 FOPI 5 0 Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range O to 63 Bit 13 8 F0GI 5 0 Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63 Bit 6 0 FOFL 6 0 Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64 32 16 03 2015 Revision 3 2 1 M CAN 2 3 29 Rx FIFO 0 Acknowledge RXFOA Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res R 0x0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res FOAI 5 0 R 0x0 RW 0x0 R Read W Write n value after reset Table 30 Rx FIFO 0 Acknowledge address 0xA8 Bit 5 0 FOAI 5 0 Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to FOAI This will set the Rx FIFO 0 Get Index RXFOS FOGI to FOAI 1 and update the FIFO 0 Fill Level RXFOS FOFL 2 3 30 Rx Buffer Configuration RXBC Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OxAC res 0 0 Bit
82. evaluated for this message The main features are Each filter element can be configured as range filter from to filter for one or two dedicated IDs classic bit mask filter Each filter element is configurable for acceptance or rejection filtering Each filter element can be enabled disabled individually Filters are checked sequentially execution stops with the first matching filter element Related configuration registers are Global Filter Configuration GFC Standard ID Filter Configuration SIDEC Extended ID Filter Configuration XIDFC Extended ID AND Mask XIDAM Depending on the configuration of the filter element SFEC EFEC a match triggers one of the following actions Store received frame in FIFO 0 or FIFO 1 Store received frame in Rx Buffer Store received frame in Rx Buffer and generate pulse at filter event pin Reject received frame Set High Priority Message interrupt flag IR HPM Set High Priority Message interrupt flag IR HPM and store received frame in FIFO 0 or FIFO 1 Acceptance filtering is started after the complete identifier has been received After acceptance filtering has completed and if a matching Rx Buffer or Rx FIFO has been found the Message Handler starts writing the received message data in portions of 32 bit to the matching Rx Buffer or Rx FIFO If the CAN protocol controller has detected an error condition e g CRC error this message is discarded with the fo
83. f configurable size and up to 64 dedicated Rx Buffers for storage of all messages that have passed acceptance filtering A dedicated Rx Buffer in contrast to a Receive FIFO is used to store only messages with a specific identifier An Rx timestamp is stored together with each message Up to 128 filters can be defined for 11 bit IDs and up to 64 filters for 29 bit IDs Generic Slave Interface Connects the M CAN to a customer specific Host CPU The Generic Slave Interface is capable to connect to an 8 16 32 bit bus to support a wide range of interconnection structures Generic Master Interface Connects the M CAN access to an external 32 bit Message RAM The maximum Message RAM size is 16K 32 bit A single M CAN can use at most 4 25K 32 bit Extension Interface flags from the interrupt Register IR as well as selected internal status and control signals are routed to this interface The interface is intended for connection of the M CAN to a module external interrupt unit or to other module external components The connection of these signals is optional 1 3 Dual Clock Sources To improve the EMC behavior a spread spectrum clock can be used for the Host clock domain m can hclk Due to the high precision clocking requirements of the CAN Core a separate clock without any modulation has to be provided as m can cclk Within the M CAN module there is a synchronization mechanism implemented to ensure save data transfer between the two
84. have been written to the Tx FIFO The M CAN calculates the Tx FIFO Free Level TXFQS TFFL as difference between Get and Put Index It indicates the number of available free Tx FIFO elements New transmit messages have to be written to the Tx FIFO starting with the Tx Buffer referenced by the Put Index TXFQS TFQPI An Add Request increments the Put Index to the next free Tx FIFO element When the Put Index reaches the Get Index Tx FIFO Full TXFQS TFQF 1 is signalled In this case no further messages should be written to the Tx FIFO until the next message has been transmitted and the Get Index has been incremented When a single message is added to the Tx FIFO the transmission is requested by writing a 1 to the TXBAR bit related to the Tx Buffer referenced by the Tx FIFO s Put Index When multiple n messages are added to the Tx FIFO they are written to n consecutive Tx Buffers starting with the Put Index The transmissions are then requested via TXBAR The Put Index is then cyclically incremented by n The number of requested Tx buffers should not exceed the number of free Tx Buffers as indicated by the Tx FIFO Free Level When a transmission request for the Tx Buffer referenced by the Get Index is cancelled the Get Index is incremented to the next Tx Buffer with pending transmission request and the Tx FIFO Free Level is recalculated When transmission cancellation is applied to any other Tx Buffer the Get Index and the FIFO Free
85. his mode it sends only recessive bits on the CAN bus If the M CAN is required to send a dominant bit ACK bit overload flag active error flag the bit is rerouted internally so that the M CAN monitors this dominant bit although the CAN bus may remain in recessive state In Bus Monitoring Mode register TXBRP is held in reset state The Bus Monitoring Mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits Figure 5 shows the connection of signals m can tx and m can rx to the M CAN in Bus Monitoring Mode m can tx m can rx i Bus Monitoring Mode Pin Control in Bus Monitoring Mode 59 BOSCH M CAN 3 1 7 3 1 7 1 3 1 8 3 1 9 Revision 3 2 1 Disabled Automatic Retransmission According to the CAN Specification see 15011898 1 6 3 3 Recovery Management the M CAN provides means for automatic retransmission of frames that have lost arbitration or that have been disturbed by errors during transmission By default automatic retransmission is enabled To support time triggered communication as described in ISO 11898 1 chapter 9 2 the automatic retransmission may be disabled via CCCR DAR Frame Transmission in DAR Mode In DAR mode all transmissions are automatically cancelled after they started on the CAN bus A Tx Buffers Tx Request Pending bit TXBRP TRPx is reset after successful transmission when a transmission has not yet been started at the point of cance
86. ion has to ensure that a valid value is written to the FIFO Acknowledge Index The M CAN does not check for erroneous values 16 03 2015 6 BOSCH Chapter 4 4 Appendix 4 1 Register Overview Symbol RE14 10 20 SUBSTEP CREL STEP 4 0 YEAR 4 0 MON 7 O DAY 7 0 a un ENDN SES 8765 4321 CUST 31 0 DBRP 4 0 DTSEG1 4 0 x 2 TEST x 0000 0000 DBTP dadd 0000 0A33 DTSEG2 3 0 E a CCCR 0000_0001 NSJWI6 NBTP 6 0 NBRP 8 0 NTSEG1 7 0 NTSEG2 6 0 re TSCC TSCV mme pd iD TOCC Ge Table 60 M CAN Register Overview M CAN Revision 3 2 1 16 03 2015 M CAN Revision 3 2 1 Symbol _ mm bi mm e ES i i DLEC 2 0 IR 0000 0000 IE 0000 0000 ILS 0000 0000 RFOFL RFOFE RFOF ILE 0000 0000 T III IIIIIIIIIIIII I I XIDAM FIDMI28 0 1 _ IIIIIIIIII E E EES Table 60 M CAN Register Overview GFC 0000 0000 SIDFC 0000 0000 XIDFC 0000 0000 z o LL D o LL D Gei z o LL D z O LL D D 78 16 03 2015 6 BOSCH Revision 3 2 1 M CAN Symbol NDAT1 0000 0000 NDAT2 0000 0000 FOWM 6 0 FOS 6 0 FOSA 15 2 e 0000 0000 0000 0000 Table 60 M CAN Register Overview 16 03 2015 79 6 BOSCH Revision 3 2 1 M CAN e a 85 x x S o8 8 S o8 2 lt 8 ss rs lt OS ES OS S OS L
87. k Calibration on CAN unit input m can cok has to be hardwired to 1 82 16 03 2015 Revision 3 2 1 M CAN List of Figures Figure 1 MAN Block Diagram t ep ddr e eu oe RE FERE ee ee 2 Figure 2 Message RAM Gonfiguration ie E tae MuR eden pae add uM eR C ERE ER 46 Figure 3 Transmitter Delay Measurement 4 isse cette doe Rea aa ak RR Red A 58 Figure 4 Pin Control in Bus Monitoring Mode A 59 Figure 5 Pin Control in Loop Back Modes eene ener en 61 Figure 6 Standard Message ID Filter Path 65 Figure 7 Extended Message ID Filter Path iiie U u uuu 66 Figure 8 RO FIFO E 67 Figure 9 Rx FIFO Overflow Flandli g ot ioi rti tad d en dde 68 Figure 10 Debug Message Handling State Machine a 71 Figure 11 Example of mixed Configuration Dedicated Tx Buffers Tx FIFO 74 Figure 12 Example of mixed Configuration Dedicated Tx Buffers Tx Queue 75 16 03 2015 83 BOSCH M CAN Revision 3 2 1 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Ta
88. k ohne EE MIR ha RR SAN 73 3 5 4 IK de TEE 74 3 5 5 Mixed Dedicated Tx Buffers TX 74 3 5 6 Mixed Dedicated Tx Buffers Tx Queue 75 3 5 7 Transmit Cancellation 75 3 5 8 Tx Event Handling 76 3 6 FIFO Acknowledge 76 4 EE 77 4 1 Register OVelyieW ERIS ae esd 77 4 2 Module Interface 81 16 03 2015 BOSCH Chapter 1 1 1 Overview The M CAN module is the new CAN Communication Controller IP module that can be integrated as stand alone device or as part of an ASIC It is described in VHDL on RTL level prepared for synthesis The M CAN performs communication according to 15011898 1 Bosch CAN specification 2 0 part A B and to Bosch CAN FD specification V1 0 Additional transceiver hardware is required for connection to the physical layer The message storage is intended to be a single or dual ported Message RAM outside of the module It is connected to the M CAN via the Generic Master Interface Depending on the chosen ASIC integration multiple M CAN controllers can share the same Message RAM All functions concerning the handling of messages are implemented by the Rx Handler and the Tx Handler The Rx Handler manages message acceptance filtering the transfer of received messages
89. lay In case this delay is greater than TSEG1 time segment before sample point a bit error is detected In order to enable a data phase bit time that is even shorter than the transmitter delay the delay compensation is introduced Without transmitter delay compensation the bit rate in the data phase of a CAN FD frame is limited by the transmitter delay 3 1 4 1 Description 16 03 2015 The M protocol unit has implemented a delay compensation mechanism to compensate the transmitter delay thereby enabling transmission with higher bit rates during the CAN FD data phase independent of the delay of a specific CAN transceiver To check for bit errors during the data phase of transmitting nodes the delayed transmit data is compared against the received data at the Secondary Sample Point SSP If a bit error is detected the transmitter will react on this bit error at the next following regular sample point During arbitration phase the delay compensation is always disabled The transmitter delay compensation enables configurations where the data bit time is shorter than the transmitter delay it is described in detail in the new 15011898 1 It is enabled by setting bit DBTP TDC The received bit is compared against the transmitted bit at the SSP The SSP position is defined as the sum of the measured delay from the M_CAN s transmit output m_can_tx through the transceiver to the receive input m_can_rx plus the transmitter delay compensation
90. llation has been aborted due to lost arbitration or when an error occurred during frame transmission Successful transmission Corresponding Tx Buffer Transmission Occurred bit TXBTO TOx set Corresponding Tx Buffer Cancellation Finished bit TXBCF CFx not set Successful transmission in spite of cancellation Corresponding Tx Buffer Transmission Occurred bit TXBTO TOx set Corresponding Tx Buffer Cancellation Finished bit TXBCF CFx set Arbitration lost or frame transmission disturbed Corresponding Tx Buffer Transmission Occurred bit TXBTO TOx not set Corresponding Tx Buffer Cancellation Finished bit TXBCF CFx set In case of a successful frame transmission and if storage of Tx events is enabled a Tx Event FIFO element is written with Event Type ET 10 transmission in spite of cancellation Power Down Sleep Mode The M CAN can be set into power down mode controlled by input signal m can clkstop req or via CC Control Register CCCR CSR As long as the clock stop request signal m can clkstop req is active bit CCCR CSR is read as one When all pending transmission requests have completed the M CAN waits until bus idle state is detected Then the M CAN sets then CCCR INIT to one to prevent any further CAN transfers Now the M CAN acknowledges that it is ready for power down by setting output signal m can clkstop ack to one and CCCR CSA to one In this state before the clocks are switched off further register accesses can be made
91. llowing impact on the affected Rx Buffer or Rx FIFO Rx Buffer New Data flag of matching Rx Buffer is not set but Rx Buffer partly overwritten with received data For error type see PSR LEC respectively PSR DLEC Rx FIFO Put index of matching Rx FIFO is not updated but related Rx FIFO element partly overwritten with received data For error type see PSR LEC respectively PSR DLEC In case the matching Rx FIFO is operated in overwrite mode the boundary conditions described in Section 3 4 2 2 have to be considered 16 03 2015 63 BOSCH M CAN Revision 3 2 1 Note When an accepted message is written to one of the two Rx FIFOs or into an Rx Buffer the unmodified received identifier is stored independent of the filter s used The result of the acceptance filter process is strongly depending on the sequence of configured filter elements 3 4 1 1 Range Filter The filter matches for all received frames with Message IDs in the range defined by SF1ID SF2ID resp EF1ID EF2ID There are two possibilities when range filtering is used together with extended frames EFT 00 The Message ID of received frames is ANDed with the Extended ID AND Mask XIDAM before the range filter is applied EFT 11 The Extended ID AND Mask XIDAM is not used for range filtering 3 4 1 2 Filter for specific IDs A filter element can be configured to filter for one or two specific Message IDs To filter for one specific Message ID the filt
92. lue configured by TOCC TOP and continues down counting When the Timeout Counter is controlled by one of the FIFOs an empty FIFO presets the counter to the value configured by TOCC TOP Down counting is started when the first FIFO element is stored Writing to TOCV has no effect When the counter reaches zero interrupt flag IR TOO is set In Continuous Mode the counter is immediately restarted at TOCC TOP Note The clock signal for the Timeout Counter is derived from the CAN Core s sample point signal Therefore the point in time where the Timeout Counter is decremented may vary due to the synchronization re synchronization mechanism of the CAN Core If the bit rate switch feature in CAN FD is used the timeout counter is clocked differently in arbi tration and data field 16 03 2015 Revision 3 2 1 M CAN 3 4 Rx Handling The Rx Handler controls the acceptance filtering the transfer of received messages to the Rx Buffers or to one of the two Rx FIFOs as well as the Rx FIFO s Put and Get Indices 3 4 1 Acceptance Filtering The M CAN offers the possibility to configure two sets of acceptance filters one for standard identifiers and one for extended identifiers These filters can be assigned to an Rx Buffer or to Rx FIFO 0 1 For acceptance filtering each list of filters is executed from element 0 until the first matching element Acceptance filtering stops at the first matching element The following filter elements are not
93. n error passive node will always transmit the ESI bit recessive TO Bit 30 XTD Extended Identifier 0 11 bit standard identifier 1 29 bit extended identifier TO Bit 29 RTR Remote Transmission Request Transmit data frame 1 Transmit remote frame Note When 1 the M CAN transmits a remote frame according to 15011898 1 even if CCCR FDOE enables the transmission in CAN FD format II TO 28 0 ID 28 0 Identifier Standard or extended identifier depending on bit XTD A standard identifier has to be written to ID 28 18 16 03 2015 49 5 BOSCH M CAN Revision 3 2 1 T1 Bits 31 24 MM 7 0 Message Marker Written by CPU during Tx Buffer configuration Copied into Tx Event FIFO element for identification of Tx message status T1 Bit 23 EFC Event FIFO Control 0 Don t store Tx events 1 Store Tx events T1 Bit 21 FD Format 0 Frame transmitted in Classic CAN format 1 Frame transmitted in CAN FD format T1 Bit 20 BRS Bit Rat Switching 0 CAN FD frames transmitted without bit rate switching 1 CAN FD frames transmitted with bit rate switching Note Bits ESI FDF and BRS are only evaluated when CAN FD operation is enabled CCCR FDOE 1 Bit BRS is only evaluated when in addition CCCR BRSE 1 T1 Bits 19 16 DLC 3 0 Data Length Code 0 8 CAN CAN FD transmit frame has 0 8 data bytes 9 15 CAN transmit frame has 8 data bytes 9 15 CAN FD transmit frame has 12 16 20 24 32
94. nd INIT are set to 1 The bit can be reset by the Host at any time 0 Bus Monitoring Mode is disabled 1 Bus Monitoring Mode is enabled Bit 4 CSR Clock Stop Request 0 clock stop is requested 1 Clock stop requested When clock stop is requested first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle Bit 3 CSA Clock Stop Acknowledge 0 No clock stop acknowledged 1 M CAN may be set in power down by stopping m can hclk and m can cclk Bit 2 ASM Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to 1 The bit can be reset by the Host at any time For a description of the Restricted Operation Mode see Section 3 1 5 0 Normal CAN operation 1 Restricted Operation Mode active Bit 1 CCE Configuration Change Enable 0 The CPU has no write access to the protected configuration registers 1 CPU has write access to the protected configuration registers while CCCR INIT 1 Bit 0 INIT Initialization 0 Normal Operation 1 Initialization is started Note Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to INIT can be read back Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value 12 16 03 2015 Revision 3 2 1 M CAN 2 3 8 Nominal Bi
95. nterrupt IR TEFW 232 Watermark interrupt disabled Bit 21 16 EFS 5 0 Event FIFO Size 0 Tx Event FIFO disabled 1 322 Number of Tx Event FIFO elements gt 32 Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS 1 Bit 15 2 EFSA 15 2 Event FIFO Start Address Start address of Tx Event FIFO in Message RAM 32 bit word address see Figure 2 16 03 2015 Revision 3 2 1 M CAN 2 3 46 Tx Event FIFO Status TXEFS Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OxF4 res TEFL EFF res EFPI 4 0 R 0x0 R 0 R 0 R 0x0 R 0x0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res EFGI 4 0 res EFFL 5 0 R 0x0 R 0x0 R 0x0 R 0x0 R Read n value after reset Table 47 Tx Event FIFO Status address OxF4 Bit 25 TEFL Tx Event FIFO Element Lost This bit is a copy of interrupt flag IR TEFL When IR TEFL is reset this bit is also reset 0 No Tx Event FIFO element lost 12 Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero Bit 24 EFF Event FIFO Full 0 Tx Event FIFO not full 12 Tx Event FIFO full Bit 20 16 EFPI 4 0 Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31 Bit 12 8 EFGI 4 0 Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31 Bit 5 0 EFFL 5 0 Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32 2 3 47 Tx Event FIFO Acknowl
96. ntrol for pin m can interferes with all CAN protocol functions It is not recommended to use test modes for application 3 1 9 1 External Loop Back Mode The M CAN can be set in External Loop Back Mode by programming TEST LBCK to one In Loop Back Mode the M CAN treats its own transmitted messages as received messages and stores them if they pass acceptance filtering into an Rx Buffer or an Rx FIFO Figure 5 shows the connection of signals m can tx and m can rx to the M CAN in External Loop Back Mode This mode is provided for hardware self test To be independent from external stimulation the M CAN ignores acknowledge errors recessive bit sampled in the acknowledge slot of a data remote frame in Loop Back Mode In this mode the M CAN performs an internal feedback from its Tx output to its Rx input The actual value of the m can rx input pin is disregarded by the M CAN The transmitted messages can be monitored at the m can tx pin 3 1 9 2 Internal Loop Back Mode Internal Loop Back Mode is entered by programming bits TEST LBCK and CCCR MON to one This mode can be used for a Hot Selftest meaning the M CAN can be tested without affecting a running CAN system connected to the pins m can tx and m can rx In this mode pin m can rx is disconnected from the M CAN and pin m can tx is held recessive Figure 5 shows the connection of m can tx and m can rx to the M CAN in case of Internal Loop Back Mode m can tx can rx m can tx can
97. offset as configured by TDCR TDCO The transmitter delay compensation offset is used to adjust the position of the SSP inside the received bit e g half of the bit time in the data phase The position of the secondary sample point is rounded down to the next integer number of mtq PSR TDCV shows the actual transmitter delay compensation value PSR TDCV is cleared when CCCR INIT is set and is updated at each transmission of an FD frame while DBTP TDC is set M CAN Revision 3 2 1 The following boundary conditions have to be considered for the transmitter delay compensation implemented in the M CAN The sum of the measured delay from m can tx to m can rx and the configured transmitter delay compensation offset TDCR TDCO has to be less than 6 bit times in the data phase The sum of the measured delay from m can tx to m can rx and the configured transmitter delay compensation offset TDCR TDCO has to be less or equal 127 mtq In case this sum exceeds 127 mtq the maximum value of 127 mtq is used for transmitter delay compensation The data phase ends at the sample point of the CRC delimiter that stops checking of receive bits at the SSPs 3 1 4 2 Transmitter Delay Compensation Measurement If transmitter delay compensation is enabled by programming DBTP TDC 1 the measurement is started within each transmitted CAN FD frame at the falling edge of bit FDF to bit res The measurement is stopped when this edge is seen at the receive inpu
98. or transmission without error Note Note No Error No error occurred since LEC has been reset by successful reception or transmis sion Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received mes sage where this is not allowed Form Error A fixed format part of a received frame has the wrong format AckError The message transmitted by the M_CAN was not acknowledged by another node Bit1Error During the transmission of a message with the exception of the arbitration field the device wanted to send a recessive level bit of logical value 1 but the monitored bus value was dominant BitOError During the transmission of a message or acknowledge bit or active error flag or overload flag the device wanted to send a dominant level data or identifier bit logical value 0 but the monitored bus value was recessive During Bus Off recovery this status is set each time a sequence of 11 recessive bits has been monitored This enables the CPU to monitor the proceeding of the Bus Off recovery sequence indicating the bus is not stuck at dominant or continuously disturbed CRCError The CRC check sum of a received message was incorrect The CRC of an incom ing message does not match with the CRC calculated from the received data NoChange Any read access to the Protocol Status Register re initializes the LEC to 7 When the LEC shows the value 7 no CAN bus event was detected since the la
99. rt Tx event handling the M CAN has implemented a Tx Event FIFO After the M CAN has transmitted a message on the CAN bus Message ID and timestamp are stored in a Tx Event FIFO element To link a Tx event to a Tx Event FIFO element the Message Marker from the transmitted Tx Buffer is copied into the Tx Event FIFO element The Tx Event FIFO can be configured to a maximum of 32 elements The Tx Event FIFO element is described in Section 2 4 4 The purpose of the Tx Event FIFO is to decouple handling transmit status information from transmit message handling i e a Tx Buffer holds only the message to be transmitted while the transmit status is stored separately in the Tx Event FIFO This has the advantage especially when operating a dynamically managed transmit queue that a Tx Buffer can be used for a new message immediately after successful transmission There is no need to save transmit status information from a Tx Buffer before overwriting that Tx Buffer When a Tx Event FIFO full condition is signalled by IR TEFF no further elements are written to the Tx Event FIFO until at least one element has been read out and the Tx Event FIFO Get Index has been incremented In case a Tx event occurs while the Tx Event FIFO is full this event is discarded and interrupt flag IR TEFL is set To avoid a Tx Event FIFO overflow the Tx Event FIFO watermark can be used When the Tx Event FIFO fill level reaches the Tx Event FIFO watermark configured by TXEFC EFW
100. s address A 38 Tx Buffer Element Size Configuration address 0xC8 39 Tx Buffer Request Pending address CC 40 Tx Buffer Add Request address xt 41 Tx Buffer Cancellation Request address OD 41 Tx Buffer Transmission Occurred address OxfDp a 42 Transmit Buffer Cancellation Finished address 42 Tx Buffer Transmission Interrupt Enable address 0 43 Tx Buffer Cancellation Finished Interrupt Enable address 0xE4 43 Tx Event FIFO Configuration address vU 44 Tx Event FIFO Status address LL is dte dte a de be et Era cn 45 Tx Event FIFO Acknowledge address ONEO nm 45 Rx Buffer and FIFO cierre rrt ere et ei s R 47 Tx Buffer Element 2 dne ero n CORE EDO ebd pua Oe cunctas ede Ee 49 Tx Event FIFO Element uuu it Lio eit te KEREN KEEN erba ccu te ean te d b te ua 51 16 03 2015 Revision 3 2 1 M CAN Table 52 Standard Message ID Filter Element 52 Table 53 Extended Message ID Filter Element eccentric nn 53 Table 54 Coding of DEC in CAN RE 57 Table 55 Rx Buffer FIFO Element Size U U U L U nennen nnne enn 67 Table 56 Example Filter Configuration for Rx Bufters enn
101. s 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RP 0x0 R 0x0 R Read P Protected write value after reset Table 31 Rx Buffer Configuration address Bit 15 2 RBSA 15 2 Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM 32 bit word address Also used to reference debug messages A B C 16 03 2015 33 M CAN Revision 3 2 1 2 3 31 Rx FIFO 1 Configuration RXF1C Bits 31 30 2 28 27 26 25 24 2 22 21 20 19 18 17 16 0xBO F10M F1WM 6 0 res F1S 6 0 RP 0 RP 0x0 R 0 RP 0x0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F1SA 15 2 res 0 0 R 0x0 R Read P Protected write value after reset Table 32 Rx FIFO 1 Configuration address OxBO Bit 31 F10M FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode see Section 3 4 2 0 FIFO 1 blocking mode 1 FIFO 1 overwrite mode Bit 30 24 F1WM 6 0 Rx FIFO 1 Watermark 0 Watermark interrupt disabled 1 64 Level for Rx FIFO 1 watermark interrupt IR RF1W 264 Watermark interrupt disabled Bit 22 16 F1S 6 0 Rx FIFO 1 Size 0 No Rx FIFO 1 1 64 Number of Rx FIFO 1 elements 264 Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to F1S 1 Bit 15 2 F1SA 15 2 Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM 32 bit word address see Figure 2 2 3 32 Rx FIFO 1 Status RXF1S
102. set by writing e g 0x00000000 to each Message RAM word to create valid parity ECC checksums This avoids that reading from uninitialized Message RAM sections will activate interrupt IR BEC Bit Error Corrected or IR BEU Bit Error Uncorrected M CAN Revision 3 2 1 16 03 2015 55 M CAN Revision 3 2 1 3 1 2 Normal Operation Once the M_ CAN is initialized and CCCR INIT is reset to zero the M CAN synchronizes itself to the CAN bus and is ready for communication After passing the acceptance filtering received messages including Message ID and DLC are stored into a dedicated Rx Buffer or into Rx FIFO 0 or Rx FIFO 1 For messages to be transmitted dedicated Tx Buffers and or a Tx FIFO or a Tx Queue can be initialized or updated Automated transmission on reception of remote frames is not implemented 3 1 3 CAN FD Operation There are two variants in the CAN FD frame transmission first the CAN FD frame without bit rate switching The second variant is the CAN FD frame where control field data field and CRC field are transmitted with a higher bit rate than the beginning and the end of the frame The previously reserved bit in CAN frames with 11 bit identifiers and the first previously reserved bit in CAN frames with 29 bit identifiers will now be decoded as FDF bit FDF recessive signifies a CAN FD frame FDF dominant signifies a Classic CAN frame In a CAN FD frame the two bits following FDF res and BRS decide whether the bit
103. sixteen 32 bit words Hn z 3 17 are used for storage of a CAN message s data field 48 16 03 2015 Revision 3 2 1 M CAN 2 4 3 31 Tx Buffer Element The Tx Buffers section can be configured to hold dedicated Tx Buffers as well as a Tx FIFO Tx Queue In case that the Tx Buffers section is shared by dedicated Tx buffers and a Tx FIFO Tx Queue the dedicated Tx Buffers start at the beginning of the Tx Buffers section followed by the buffers assigned to the Tx FIFO or Tx Queue The Tx Handler distinguishes between dedicated Tx Buffers and Tx FIFO Tx Queue by evaluating the Tx Buffer configuration TXBC TFQS and TXBC NDTB The element size can be configured for storage of CAN FD messages with up to 64 bytes data field via register TXESC 24 23 16 15 8 7 0 ESI XTD RTR ID 28 0 MM 7 0 EFC res Lo x DLC 3 0 res uw m DB3 7 0 DB2 7 0 DB1 7 0 DBO 7 0 DB7 7 0 DB6 7 0 DB5 7 0 DB4 7 0 DBm 7 0 DBm 1 7 0 DBm 2 7 0 DBm 3 7 0 Table 50 Tx Buffer Element TO Bit 31 ESI Error State Indicator 0 ESI bit in CAN FD format depends only on error passive flag 1 ESI bit in CAN FD format transmitted recessive Note The ESI bit of the transmit buffer is or ed with the error passive flag to decide the value of the ESI bit in the transmitted FD frame As required by the CAN FD protocol specifi cation an error active node may optionally transmit the ESI bit recessive but a
104. ssage transmission is aborted In case of a Tx Handler access failure the M CAN is switched into Restricted Operation Mode see Section 3 1 5 To leave Restricted Operation Mode the Host CPU has to reset CCCR ASM 0 Message RAM access failure occurred 1 Message RAM access failure occurred Bit 16 TSW Timestamp Wraparound 0 No timestamp counter wrap around 1 Timestamp counter wrapped around Bit 15 TEFL Tx Event FIFO Element Lost 0 No Tx Event FIFO element lost 1 Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero Bit 14 TEFF Tx Event FIFO Full 0 Tx Event FIFO not full 1 Tx Event FIFO full Bit 13 TEFW Tx Event FIFO Watermark Reached 0 Tx Event FIFO fill level below watermark 1 Tx Event FIFO fill level reached watermark 16 03 2015 21 BOSCH M CAN 22 Bit 12 Revision 3 2 1 TEFN Tx Event FIFO New Entry Tx Event FIFO unchanged Tx Handler wrote Tx Event FIFO element TFE Tx FIFO Empty Tx FIFO non empty Tx FIFO empty TCF Transmission Cancellation Finished No transmission cancellation finished Transmission cancellation finished TC Transmission Completed No transmission completed Transmission completed HPM High Priority Message No high priority message received High priority message received RF1L Rx FIFO 1 Message Lost No Rx FIFO 1 message lost Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero RF1F Rx FIFO 1
105. st CPU read access to the Protocol Status Register When a frame in CAN FD format has reached the data phase with BRS flag set the next CAN event error or valid frame will be shown in DLEC instead of LEC An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error not Stuff Error The Bus Off recovery sequence see CAN Specification Rev 2 0 or I8011898 1 cannot be shortened by setting or resetting CCCR INIT If the device goes Bus_Off it will set CCCR INIT of its own accord stopping all bus activities Once CCCR INIT has been cleared by the CPU the device will then wait for 129 occurrences of Bus Idle 129 11 conseculive recessive bits before resuming normal operation At the end of the Bus Off recovery sequence the Error Management Counters will be reset During the waiting time after the resetting of CCCR INIT each time a sequence of 11 recessive bits has been monitored a BitOError code is written to PSR LEC enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus Off recovery sequence ECR REC is used to count these sequences 16 03 2015 Revision 3 2 1 M CAN 2 3 15 Transmitter Delay Compensation Register TDCR Bits 31 30 29 28 27 2 25 24 2 22 2 20 19 18 17 16 Table 16 Transmitter Delay Compensation Register address 0x048 0x048 res 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E JE R 0 RP 0x0 R 0 RP 0x0 R
106. t 31 0 ND 31 0 New Data The register holds the New Data flags of Rx Buffers 0 to 31 The flags are set when the respective Rx Buffer has been updated from a received frame The flags remain set until the Host clears them A flag is cleared by writing a 1 to the corresponding bit position Writing OU has no effect A hard reset will clear the register 0 Rx Buffer not updated 1 Rx Buffer updated from new message 2 3 26 New Data 2 NDAT2 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x9C ND63 ND62 ND61 058 ND57 ND56 ND55 ND54 ND53 ND52 ND51 ND50 ND49 ND48 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ND47 ND46 ND45 ND44 ND43 ND42 ND41 ND40 ND39 ND38 ND37 ND36 ND35 ND34 ND33 ND32 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Read value after reset Table 27 New Data 2 address 0x9C Bit 31 0 ND 63 32 New Data The register holds the New Data flags of Rx Buffers 32 to 63 The flags are set when the respective Rx Buffer has been updated from a received frame The flags remain set until the Host clears them A flag is cleared by writing a 1 to the corresponding bit position Writing a OU has no effect A hard reset will clear the register 0 Rx Buffer not updated 1 Rx Buffer updated from new message 30 16 03 2015 Revision 3 2
107. t Timing amp Prescaler Register NBTP This register is only writable if bits CCCR CCE and CCCR INIT are set The CAN bit time may be programed in the range of 4 to 385 time quanta The CAN time quantum may be programmed in the range of 1 to 512 m can cclk periods t NBRP 1 mtq NTSEG1 is the sum of Prop Seg and Phase Seg1 NTSEG2 is Phase Geo Therefore the length of the bit time is programmed values NTSEG1 NTSEG2 3 ty or functional values Sync Seg Prop Seg Phase Seg1 Phase Seg 2 ta The Information Processing Time IPT is zero meaning the data for the next bit is available at the first clock edge after the sample point Bits 31 30 2 28 2 2 2 24 23 22 21 20 19 18 17 16 1 NSJW 6 0 NBRP 8 0 RP 0x3 RP 0x0 Bits 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 NTSEG 7 0 res NTSEG2 6 0 R 0 RP 0x3 R Read P Protected write value after reset Table 9 Nominal Bit Timing amp Prescaler Register address Ox1C Bits 31 25 NSJW 6 0 Nominal Re Synchronization Jump Width 0x00 Ox7F Valid values are 0 to 127 The actual interpretation by the hardware of this value is such that one more than the value programmed here is used Bits 24 16 NBRP 8 0 Nominal Bit Rate Prescaler 0x000 0x1FF The value by which the oscillator frequency is divided for generating the bit time quanta The bit time is built up from a multiple of this quanta Valid values for the Bit Rate Presc
108. t data may be read from the respective Rx FIFO element Adding an offset to the get index when reading from the Rx FIFO avoids this problem The offset depends on how fast the CPU accesses the Rx FIFO Figure 9 shows an offset of two with respect to the get index when reading the Rx FIFO In this case the two messages stored in element 1 and 2 are lost Rx FIFO Full Rx FIFO Overwrite RXFnS FnF 1 RXFnS FnF 1 RXFnS FnPI RXFnS FnGl element 0 overwritten RXFnS FnPI RXFnS FnGl read Get Index 2 FIFO Overflow Handling After reading from the Rx FIFO the number of the last element read has to be written to the Rx FIFO Acknowledge Index RXFnA FnA This increments the get index to that element number In case the put index has not been incremented to this Rx FIFO element the Rx FIFO full condition is reset RXFnS FnF 0 16 03 2015 BOSCH Revision 3 2 1 M CAN 3 4 3 Dedicated Rx Buffers Table 56 The M CAN supports up to 64 dedicated Rx Buffers The start address of the dedicated Rx Buffer section is configured via RXBC RBSA For each Rx Buffer a Standard or Extended Message ID Filter Element with SFEC EFEC 111 and SFID2 EFID2 10 9 00 has to be configured see Section 2 4 5 and Section 2 4 6 After a received message has been accepted by a filter element the message is stored into the Rx Buffer in the Message RAM referenced by the filter element The format is the same as for an Rx F
109. t error detected when reading from Message RAM 1 Bit error detected uncorrected e g parity logic Bit 20 BEC Bit Error Corrected Message RAM bit error detected and corrected Controlled by input signal m can aeim berr 0 generated by an optional external parity ECC logic attached to the Message RAM 0 No bit error detected when reading from Message RAM 1 Biterror detected and corrected e g ECC Bit 19 DRX Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer 0 Rx Buffer updated 1 Atleast one received message stored into an Rx Buffer Bit 18 TOO Timeout Occurred 0 No timeout 1 Timeout reached Bit 17 MRAF Message RAM Access Failure The flag is set when the Rx Handler has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message was not able to write a message to the Message RAM In this case message storage is aborted In both cases the FIFO put index is not updated resp the New Data flag for a dedicated Rx Buffer is not set a partly stored message is overwritten when the next message is stored to this location The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time In this case me
110. t m can rx of the transmitter The resolution of this measurement is one mtq Transmitter Delay E S FDF L res BRS DLC m can tx arbitration phase data phase m_can_rx arbitration phase data phase Start Stop m_can_cclk Delay Counter SSP Position Delay Compensation Offset TDCR TDCO Figure 3 Transmitter Delay Measurement To avoid that a dominant glitch inside the received FDF bit ends the delay compensation measurement before the falling edge of the received res bit resulting in a to early SSP position the use of a transmitter delay compensation filter window can be enabled by programming TDCR TDCF This defines a minimum value for the SSP position Dominant edges on m can rx that would result in an earlier SSP position are ignored for transmitter delay measurement The measurement is stopped when the SSP position is at least TDCR TDCF AND m can rx is low 58 16 03 2015 Revision 3 2 1 M CAN 3 1 5 Restricted Operation Mode In Restricted Operation Mode the node is able to receive data and remote frames and to give acknowledge to valid frames but it does not send data frames remote frames active error frames or overload frames In case of an error condition or overload condition it does not send dominant bits instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication The error counters ECR REC ECR TEC ar
111. t received CAN FD message had its ESI flag set Bits 10 8 DLEC 2 0 Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set Coding is the same as for LEC This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred reception or transmission without error Bit 7 BO Bus Off Status 0 TheM CAN is not Bus Off 1 M_CAN is in Bus Off state Bit 6 EW Warning Status 0 Both error counters are below the Error Warning limit of 96 1 Atleast one of error counter has reached the Error Warning limit of 96 16 03 2015 17 M CAN 18 Bit 5 0 1 Revision 3 2 1 EP Error Passive The M CAN is in the Error Active state It normally takes part in bus communication and sends an active error flag when an error has been detected The M CAN is in the Error Passive state Bits 4 3 ACT 1 0 Activity Monitors the module s CAN communication state 00 7 Synchronizing node is synchronizing on CAN communication 01 7 Idle node is neither receiver nor transmitter 10 Receiver node is operating as receiver 11 Transmitter node is operating as transmitter Note ACT is set to 00 by a Protocol Exception Event Bits 2 0 LEC 2 0 Last Error Code The LEC indicates the type of the last error to occur on the CAN bus This field will be cleared to 0 when a message has been transferred reception
112. ta bit timing Register TEST restructured TDCV moved to register PSR Register CCCR restructured FDBS and FDO removed new control bit EFBI replaces status flag FDBS new control bit PXHD replaces status flag FDO CMR removed transmit format configured in Tx Buffer element CME replaced by FDOE and BRSE Register BTP renamed to NBTP and restructured BRP renamed to NBRP range reduced TSEG1 renamed to NTSEG1 range expanded TSEG2 renamed to NTSEG2 range expanded SJW renamed to NSJW range expanded Register PSR updated TDCV moved from register TEST range increased status flag PXE added FLEC renamed to DLEC Register TDCR added TDCO moved from register DBTP range expanded new configuration TDCF field Register IR updated interrupt flags STE FOE ACKE BE CRCE replaced by ARA PED PEA Register IE updated interrupt enable bits STEE FOEE ACKEE BEE CRCEE replaced by ARAE PEDE PEAE Register ILS updated interrupt line select bits STEL FOEL ACKEL BEL CRCEL replaced by ARAL PEDL PEAL Rx buffer and FIFO element updated bit EDL renamed to FDF Tx buffer element updated transmission of bit ESI recessive configurable selection of Classic FD format transmission via flag FDF configuration of bit rate switching via BRS Section 3 1 3 CAN FD Operation updated Section 3 1 4 Transmitter Delay Compensation updated Minor amendments and textual enhancements 3 1 5 14 10 201
113. the location for storage of a received debug message When a debug message is stored neither the respective New Data flag nor IR DRX are set The reception of debug messages can be monitored via RXF1S DMS Filter SFID1 10 0 SFID2 10 9 SFID2 5 0 Element EFID1 28 0 EFID2 10 9 EFID2 5 0 0 ID debug message A 01 11 1101 1 ID debug message B 10 11 1110 ID debug message C 11 11 1111 Example Filter Configuration for Debug Messages 3 4 4 2 Debug Message Handling 70 The debug message handling state machine assures that debug messages are stored to three consecutive Rx Buffers in correct order In case of missing messages the process is restarted The DMA request is activated only when all three debug messages A B C have been received in correct order 16 03 2015 BOSCH Revision 3 2 1 M CAN The status of the debug message handling state machine is signalled via RXF1S DMS HWresetor TO Init state T0 reset m can dma req output enable reception of debug messages A B and C T1 reception of debug message A T2 reception of debug message A T3 reception of debug message C T4 reception of debug message B T5 reception of debug messages A B T6 reception of debug message C T7 DMA transfer completed T8 reception of debug message A B C message rejected Figure 10 Debug Message Handling State Machine 16 03 2015 7i BOSCH M CAN Revision 3 2 1 3 5 Tx Handling The Tx
114. under complete control of the Host CPU Each Dedicated Tx Buffer is configured with a specific Message ID In case that multiple Tx Buffers are configured with the same Message ID the Tx Buffer with the lowest buffer number is transmitted first 72 16 03 2015 5 BOSCH Revision 3 2 1 M CAN Table 59 3 5 3 If the data section has been updated a transmission is requested by an Add Request via TXBAR ARn The requested messages arbitrate internally with messages from an optional Tx FIFO or Tx Queue and externally with messages on the CAN bus and are sent out according to their Message ID A Dedicated Tx Buffer allocates Element Size 32 bit words in the Message RAM see Table 59 Therefore the start address of a dedicated Tx Buffer in the Message RAM is calculated by adding transmit buffer index 0 31 Element Size to the Tx Buffer Start Address TXBC TBSA TXESC TBDS 2 0 pide me d 000 8 001 12 010 16 S 011 20 7 100 24 8 101 32 10 110 48 44 111 64 18 Tx Buffer FIFO Queue Element Size Tx FIFO Tx FIFO operation is configured by programming TXBC TFQM to 0 Messages stored in the Tx FIFO are transmitted starting with the message referenced by the Get Index TXFQS TFGI After each transmission the Get Index is incremented cyclically until the Tx FIFO is empty The Tx FIFO enables transmission of messages with the same Message ID from different Tx Buffers in the order these messages
115. ure 2 Note Be aware that the sum of TFQS and NDTB may be not greater than 32 There is no check for erroneous configurations The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers 16 03 2015 37 M CAN Revision 3 2 1 2 3 36 Tx FIFO Queue Status TXFQS The Tx FIFO Queue status is related to the pending Tx requests listed in register TXBRP Therefore the effect of Add Cancellation requests may be delayed due to a running Tx scan TXBRP not yet updated Bits 31 30 2 2 27 26 2 24 2 22 21 20 19 18 17 16 0xC4 res TFQPI 4 0 R 0x0 R 0 R 0x0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0x0 R 0x0 R 0x0 R 0x0 R Read n value after reset Table 37 Tx FIFO Queue Status address 0xC4 Bit 21 TFQF Tx FIFO Queue Full 0 Tx FIFO Queue not full 1 Tx FIFO Queue full Bit 20 16 TFQPI 4 0 Tx FIFO Queue Put Index Tx FIFO Queue write index pointer range 0 to 31 Bit 12 8 TFGI 4 0 Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31 Read as zero when Tx Queue operation is configured TXBC TFQM 1 Bit 5 0 TFFL 5 0 Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI range 0 to 32 Read as zero when Tx Queue operation is configured TXBC TFQM 1 Note In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicate
116. with activated transmission request Tx Buffer with lowest Message ID gets highest priority and is transmitted next 3 5 7 Transmit Cancellation The M CAN supports transmit cancellation This feature is especially intended for gateway applica tions and AUTOSAR based applications To cancel a requested transmission from a dedicated Tx Buffer or a Tx Queue Buffer the Host has to write a 1 to the corresponding bit position number of Tx Buffer of register TXBCR Transmit cancellation is not intended for Tx FIFO operation Successful cancellation is signalled by setting the corresponding bit of register to 1 In case a transmit cancellation is requested while a transmission from a Tx Buffer is already ongoing the corresponding TXBRP bit remains set as long as the transmission is in progress If the transmission was successful the corresponding TXBTO and TXBCF bits are set If the transmission was not successful it is not repeated and only the corresponding TXBCF bit is set Note In case a pending transmission is cancelled immediately before this transmission could have been started there follows a short time window where no transmission is started even if another message is also pending in this node This may enable another node to transmit a message which may have a lower priority than the second message in this node 16 03 2015 75 BOSCH M CAN 3 5 8 3 6 76 Revision 3 2 1 Tx Event Handling To suppo

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