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UC1394a-1 DSP Master BSP User's Guide

1. 48 NN ENE 48 4122 FPGA VO pin interrupts tte Eeer 48 4123 Streaming interrupts s E 48 4 13 4 External interrupts INT3 and INTA ssssssseeennnnnm mmn 48 5 DETAILED INTERFACE DESCRIPTION ccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeees 49 5 1 Peripheral At ET 49 5 1 1 Wait State Generator Programming eene eene nen 50 5 2 IEEET394 interface Lama 50 5 2 1 How Data is Transferred Over IEEE1394 sese 50 5 2 2 Plug amp Play features of IEEET3938d enenatis pa a AA 51 5 23 Power Distribution Over EEE1394 aaa nA AA 51 sra ce E 51 5 3 Software e eee 51 5 4 UART Interface iiia iiie NAGA SNE ENER Dux E Uu Fe ssa ES ENER EE ERE CR AA 61 UsER s GUIDE Date l 7 November 2006 LF UC1394A 1 DSP MASTER BSP GER e Orsys Page 5 5 4 1 UART Hardware en 61 5 4 2 UART Qe cT 62 5 5 V PINS Tw 65 5 5 1 I O Pin Hardware Interface AN ise ees 66 55 2 VOPin F R TG 66 5 6 Other Interfaces Provided by FPGA Registers eee 69 5 6 1 System Control Register SYS CT aaa treten ete rese ege Kan 69 5 6 2 Watchdog Control Register WDG anas an 70 5 5 9 Version Register VER ios io Deo blc arai s EC 71 6 HARDWARE IMPLEMENTATION GUIDELINES
2. EEN 73 6 1 ower Sp een eee eee ee eee 73 6 2 IEEET1394 interface LG GA NEKTAR 73 63 RS 232 Level Converter paNIRA ANAN ANA 75 64 JTAG Item K GABI GEN RANA ee 75 6 5 Unused EE E 76 6 6 Minimal Connection Example aa 76 7 TECHNICAL DATA Lung 78 7 1 Signal Overview and Connector Pinout Tables eee 78 7 2 Individual Signal Description aaa AA AA 81 7 3 Dimensions of the UC 1394 1 AA AGA NecEN 86 7 4 Environmental Condillons ecr retenti tear xip ace tk enirn tta ant INR NER NAAN 86 TAN BEE vr 86 7 4 2 SERIES 86 7 4 3 Ambient TEMP Gray ET Em 87 75 E TE lte 87 7 6 Power Require Mena GRAE 88 7 7 Signal Levels and LoadS E 88 Jalle ERGA SINAIS EE 88 DNA Reset Sigal E 89 TTS DEP SONG Ee 89 Li Analog ue LE 90 Ao Other Sigal a AA AA AA a E AAO 90 7 8 Peripheral Interface Timing EE 90 7 8 4 Timings for a 200MHz TMS320VC5509A nennen nennen 91 7 8 2 Timings for a 144MHz TMG22OVCDhbOO AAA 91 O USER S GUIDE UC1394A 1 DSP MASTER BSP Date 7 November 2006 Doc no DSP_master_BSP_UG Iss Rev 2 1 M orsys Page 6 TS Reset TIMING aaa KAKANAN 92 7 10 10 Pin TIMING CN 92 B GEOSSARV ansetter feed desse 93 9 LITERATURE REFERENCES n USER S GUIDE Date 7 November 2006 2 UC1394a 1 DSP MASTER BSP a e Orsys Page 7 List of Tables Table 1 CPU address NAP EE 45 Table 2 Flash memory A E 45 Table 3 L
3. parameter value name description ax di strobe signals low after control signals valid o tu datavalidafterstrobehigh Jones taz control signals valid after strobe signals high 5ns is ARDY valid before strobe He 5ons Figure 26 Peripheral interface read timing 144MHz parameter tn strobe signals low after control signals valid 5ns ti strobe signals active Jam CS Ee tas data valid after strobe high 5 ns ta control signals valid after strobe signals high 5ns o ARDY valid beforestrobehigh 50ns Figure 27 Peripheral interface write timing 144MHz To relax these timings for slower peripheral components the EMIF settings can be modified by increasing the default settings for setup strobe and hold cycles for read or write accesses Each additional clock adds one CPU clock period 6 94 ns for a CPU clock of 144MHz to the timings as listed below e Increasing the setup time increases ty for read and write accesses allowing more time for chip select address and direction decoding e Increasing the number of strobe cycles increases tp1 for read and write accesses For read accesses this allows longer access times tac t5 tsu1 of the peripheral component For write accesses this allows longer setup times for the peripheral component e Increasing the hold time increases ty for read accesses and ty for write accesses This gives the peripheral component
4. e USER S GUIDE Date l 7 November 2006 Le H UC1394A 1 DSP MASTER BSP Wap aaa orsys Page 18 4 Programming the UC1394a 1 This chapter describes the software programming interfaces of the UC1394a 1 It is intended for programmers who want develop their own customized software to run on the UC1394a 1 The UC1394a 1 provides the following programming interfaces e EEE1394 API generic or protocol specific e register level programming of the BSP specific FPGA peripherals e on chip peripherals of the TMS320VC5509 Programming the FPGA peripherals is described in chapter 5 Programming the on chip DSP peripherals is supported on register level by the provided header files or by the chip support library which is part of Code Composer Studio 4 1 Required Tools e TI Code Composer Studio V3 x e FlashBurnDSK utility included on the distribution media e JTAG Emulator for program download such as TI XDS510 or other products 4 2 Software Development Flow User defined software can be written as C source code The source code modules are compiled by the C compiler The resulting object files must be linked with at least the runtime library for the TMS320VC5509 rts55x 1ib Usually one or more object libraries are added during the linker process such as the IEEE1394 API libraries and the module support library The output of the linker is an executable file which can be downloaded to the UC1394a 1 over the JTAG interface usi
5. Date 7 November 2006 LOO USER S GUIDE Doc no DSP_master_BSP_UG iJ Iss Rev 2 1 orsys Page 1 User s Guide DSP Master BSP for the UC1394a 1 MCM Orsys Orth System GmbH Am Stadtgraben 25 88677 Markdorf Germany http www orsys de USER S GUIDE Date 7 November 2006 15 UC1394A 1 DSP MASTER BSP ee orsys Page 2 Contents 1 PREFACE 9 1 1 Document Organization wicssccscsscasecneccecsssncescetacsentecanssccecernmsnese daveaneseteenseeextansusseeanasnceneceatanceecs 9 1 2 Documentation Overview a 9 1 3 Notatlonal Conventions umaasam kA GG NAGANA GAAN AG 9 1 4 TAMA KS ABAKA 11 15 Revision NINONG RAANG 11 2 SYSTEM OVERVIEW PE 12 2 1 Applications EN 12 22 Block Betrag 13 23 DSP RR 14 St EES 14 25 Peripheral Inter a6 B IAANGAT 14 2 6 IEEE 1394 Interieur 14 27 VART En EE 14 28 HERE a 15 29 MCcBSP Interlaces me NAKAANGAT ANAN 15 210 USB IME SEE dee T 15 211 ent EE 15 212 ADC oae E E E 15 213 RIC E 15 2144 Eegeregie 15 Ry mee saai waansin adatepe anaa anaa EPI Iu Mc aaas edanan asaan anri 16 2 16 DSP JTAG Interface sansen 16 217 FPGA JTAG Nima paaa chter 16 218 EE TT UE 16 3 QUICK START Lunnan FlbPTaLE LEID IUE vM DEDUES Qu AOI RE UE DM aean FR MPR UN DUUM DIE 17 USER S GUIDE Date 7 November 2006 2 UC139
6. TAG This bit field specifies the type of the payload data The data type is application specific however the default for unformatted data is O which is defined as uc1394a STR HDR1 TAG UNFORMATTED N dsp master bsp h This value is the default value which shouldn t be changed by the application software 5 3 1 1 3 Streaming Header Register 2 STR HDR2 Description This register specifies second half of the header for transmitted packets It specifies the payload data size for one packet In receive direction this register is ignored Do not program the header register of the IEEE1394 chipset directly The value in the header register of the LLC will be overwritten by the value in the STR HDR2 register Address 0200C31s Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSV PACKET DATA LENGTH RSV r 000 r w 00000000001 r 00 Packet payload size in quadlets PACKET DATA LENGTH This bit field determines the payload size of a packet counted in quadlets Together with the two reserved LSBs the payload size can be specified in bytes Default value is 1 quadlet 4 bytes Programming example include dsp master bsp h board support package definitions INT16U usPacketSizeInBytes 0x100 256 bytes payload 64 quadlets UC1394A STR HDR2 usPacketSizeInBytes 5 3 1 1 4 Streaming Frame Size Number of Packets per Frame STR FRMSZ Description This register defines the number of packets that are group
7. 4 6 Howto Store an Application in Flash Memory The UC1394a 1 supports up to 384KB of flash memory for application code This application code must be in a format suitable for the processor s boot loader To generate such a file the projects on the distribution CD contain a final build step that uses the hex55 utility To program your application into the UC1394a s flash memory you must Build the project as normal connect the JTAG emulator to the UC1394a 1 Start the FlashBurnDSK utility Select Create a new FlashBurn Configuration and click on OK For Step 1 Connection select a suitable Code Composer connection such as C5509A XDS510 Emulator CPU_1 and click on Connect For Step 2 FBTC program file locate FBTCOrsysUC1394a 1 0ut and click on Download FBTC The FBTC program file is typically located on the distribution media in the folder FlashBurn For Step 3 File to Burn locate the application code such as toggle led hex within the respective project folder such as examples toggle_led Debug Leave Conversion Cmd File empty Click on Erase Flash to erase the flash memory This erases only the application area but not the FPGA code Click on Program Flash to store the application to flash memory Close FlashBurnDSK Before exiting FlashBurnDSK asks to save the current settings to a file for future use power cycle the UC1394a 1 switch off and then on again Now the application is loaded from
8. FF defined in hexutil h synopsis void HexByte2Ascii unsigned char ucNum char pResult parameters ucNum 8 bit number to convert pResult Pointer to result Must be at least 3 bytes return value none 4 10 34 HexDword2Ascii Converts a 32 bit number into a string 00000000 FFFFFFFF defined in hexutil h synopsis void HexDword2Ascii unsigned long ulNum char pResult parameters ulNum 32 bit number to convert pResult Pointer to result Must be at least 9 bytes return value none USER S GUIDE Date 7 November 2006 LJ y UC1394A 1 DSP MASTER BSP GER orsys Page 44 4 10 35 HexNibble2Ascii Converts a 4 bit number lower 4 bits of 8 bit number into a string O F defined in hexutil h synopsis void HexNibble2Ascii const INT8U digit char pResult parameters digit 8 bit number to convert pResult Pointer to result Must be at least 2 bytes return value none 4 10 36 HexWord2Ascii Converts a 16 bit number into a string 0000 FFFF defined in hexutil h synopsis void HexWord2Ascii INT16U usNum char pResult parameters usNum 16 bit number to convert pResult Pointer to result Must be at least 5 bytes return value none 4 11 Memory Map and Register Description 4 11 1 Memory Map of the UC1394a 1 The table below shows the data memory map of the TMS320VC5509 specific to the UC1394a 1 The addresses are given as word addresses so each
9. UC1394A FLASH SA10 OFFS ulLengthInWords Number of 16 bit word to read pusData Specifies the location where the retrieved data is stored return value None 4 10 17 DebugBufmgr Writes one character form the debug transmit buffer to the debug interface if there is data in the transmit buffer and the underlying debug interface is ready to accept it Reads one character from the debug interface to the debug receive buffer if data is available and the buffer is not already full The function doesn t operate interrupt driven so it must be called periodically defined in debug h UsER s GUIDE Date 7 November 2006 CH d UC1394a 1 DSP MASTER BSP er a na e orsys Page 38 synopsis void DebugBufmgr void parameters none return value none 4 10 18 DebugFlush Flushes the debug transmit buffer The function just calls DebugBufmgr as long as the debug transmit buffer is not empty defined in debug h synopsis void DebugFlush void parameters none return value none 4 10 19 DebugGetc Reads one character from the debug receive buffer defined in debug h synopsis int DebugGetc void parameters none return value character read from the debug receive buffer or DEBUG_EOF if buffer is empty UsER s GUIDE Date 7 November 2006 Ly d UC1394a 1 DSP MASTER BSP GE orsys Page 39 4 10 20 DebugGets Gets a debug message from the debug receive buffer The debug r
10. usLength number of characters in debug string without trailing NO pDebugText pointer to debug message return value number of characters actually written 4 10 25 DecSignedByte2Ascii Converts a signed 8 bit number into a character string in decimal ASCII representation The Character string consists of 4 characters starting with either space for positive numbers or for negative numbers The string contains leading zeros if the absolute value is less than 100 defined in decutil h synopsis void DecSignedByte2Ascii INT8S digit char pResult parameters digit number to be converted pDebugText pointer to storage for the converted string return value none n USER S GUIDE Date l 7 November 2006 2 UC1394a 1 DSP MASTER BSP ee Orsys Page 41 4 10 26 DecSignedDword2Ascii Converts a signed 32 bit number into a character string in decimal ASCII representation The Character string consists of 11 characters starting with either space for positive numbers or for negative numbers The string contains leading zeros if the absolute value is less than 1000000000 defined in decutil h synopsis void DecSignedDword2Ascii INT32S digit char pResult parameters digit number to be converted pDebugText pointer to storage for the converted string return value none 4 10 27 DecSignedNibble2Ascii Converts a signed 4 bit number into a character string in decimal ASCII representation The Char
11. 0208001 URE rr reserved reserved FPGA register set repeats each 100015 words Table 4 LLC and FPGA register map ov o o o D o ov o o o Wei 4 DI O gt 4 gt a la o 0200CF 0200D0 Dn o OY OY o o Fr Fr o Hr t Hy t o o o a o Fr Fr o o Hr fz Hr t o o o ov Dn 4 12 LLC registers Accesses to the LLC are managed by the FPGA Therefore the FPGA must be correctly loaded before the LLC can be accessed The LLC register set is usually handled by the IEEE1394 API In most cases there is no need to program LLC registers directly from application level The LLC registers are 32 bit wide so each LLC register occupies two 16 bit locations The most significant word MSW is located at the lower address and the least significant word LSW USER S GUIDE Date 7 November 2006 2 UC1394a 1 DSP MASTER BSP Emu E e orsys Page 48 at the higher address To access a register either 16 bit accesses or 32 bit accesses can be used Example int 0x020000 reads the MSW of the LLC version register and should yield 711516 int 0x020001 reads the LSW of the LLC version register and should yield 38A0 long 0x020000 reads the complete version register and should yield 711538A04 Please note when writing LLC registers the MSW must be written first Therefore 32 bit accesses may only occur at even addres
12. Peripheral interface write timing 200MHz en 91 Figure 26 Peripheral interface read timing 144MH2 ssssesseeennenm men 92 Figure 27 Peripheral interface write timing 144MH2 oronnnnnnnnvnnnnnnnrrnnnrnnnrrnnnnrrrrrnennrnnrrrnnnennnnnnnnn 92 e USER S GUIDE Date l 7 November 2006 Le y UC1394A 1 DSP MASTER BSP ee orsys Page 9 1 Preface 1 1 Document Organization This document is organized as follows e Chapter 2 gives a brief overview of the whole system and its interfaces Chapter 3 tells how to do the very first steps Chapter 4 describes how to develop software for the UC1394a 1 Chapter 5 describes each interface in detail including the associated registers Chapter 6 shows how to integrate the UC1394a 1 in a customized hardware environment Chapter 7 lists technical data of the UC1394a 1 such as pinning and timings Chapter 8 explains the abbreviations that are used throughout this document Chapter 9 lists documents that contain further information 1 2 Documentation Overview This chapter lists the documentation from Orsys that is shipped together with the DSP master board support package Further documents from other vendors are listed in chapter 8 and are referenced throughout the document in square brackets DSP Development Kit User s Guide 15 psp_pevxit_uc pa Shipped with the DSP development kit only Describes the environment that the carrier board adds to the UC1394a 1 MCM a
13. digit number to convert and put to debug the interface return value none 4 9 10 DebugOutUByteDec Converts an unsigned 8 bit number into a string of 3 characters and puts the string into the debug transmit buffer This is a macro that calls the functions DecUnsignedByte2Ascii and DebugPuts defined in debug h synopsis void DebugOutUByteDec INT8U digit parameters digit number to convert and put to the debug interface return value none 4 9 11 DebugOutUDwordDec Converts an unsigned 32 bit number into a string of 10 characters and puts the string into the debug transmit buffer This is a macro that calls the functions DecUnsignedDword2Ascii and DebugPuts defined in debug h synopsis void DebugOutUDwordDec INT32U digit parameters digit number to convert and put to the debug interface return value none e USER S GUIDE Date l 7 November 2006 Le H UC1394A 1 DSP MASTER BSP Ee orsys Page 31 4 9 12 DebugOutUNibbleDec Converts an unsigned 4 bit number into a string of two characters and puts the string into the debug transmit buffer This is a macro that calls the functions DecUNibble2Ascii and DebugPuts defined in debug h synopsis void DebugOutUNibbleDec INT8U digit parameters digit number to convert and put to the debug interface return value none 4 9 13 DebugOutUWordDec Converts an unsigned 16 bit number into a string of 5 characters and puts the string into the d
14. 10 7 EDOM AH 34 4 108 EE goo cm 34 410 9 o tmm 34 4 1010 NN 35 41011 T NES eene Eed Een 35 4 1012 FL EE 35 410 13 PIASNGSUIGVICCIING 36 4 10 14 RE 36 USER S GUIDE Date 7 November 2006 2 UC1394a 1 DSP MASTER BSP er e orsys Page 4 4 10 15 la AA 37 AA 37 4 10 17 DEDUGBUNG soseen aa AA AA AG 37 4 10 18 EDU MI GE 38 4 10 19 DebugGetc eden 38 4 10 20 e ET 39 FT me eL EE 39 EE 39 4 1029 MERI OL m 40 4 10 24 D PE AA AA EREE EGA 40 4 10 25 Dee EE OE MT 40 41026 e ee EE 41 4 10 27 Bee ve 41 41028 ee e EE 41 4 10 29 BDec nsignedByle2 ASCII aaa NAGA dee 42 4 10 30 Ree EE 42 4 10 31 AE 42 4 10 32 WecUnsioned EE 43 4 10 33 TEE 43 4 10 34 Re EE 43 4 10 35 HexNibble2Ascii E 44 4 10 36 TEX WOR ASO E 44 4 11 Memory Map and Register Description nenne 44 4 11 1 Memory Map of the UC1394a 1 muuaaasauauwannnuaaanananaaaaaanaaaaanananaaanaananasanannannaransanannanasaanasann 44 4 11 2 Internal RAM of the Processor seeeeesseseseeseeeeeeneenee eene nnn innen nnne nnne trn nnns 45 4113 Fash MEMO naaa cete Eb aod huesca un bu tu IA Coh aud ende lepra ka emi tmu us Sa ERG PE NAAN 45 411 4 External RAM erain Em TT 45 2 11 5 E EE 45 4 11 6 FPGA register overview saaan AGANG KANAN teens Macaboararememmadiominws 46 4 11 7 FPGA register MAP EE 46 412 LLO d ee ee 47 mM
15. 8 for details 4 13 4 External interrupts INT3 and INTA The external MCM interrupt inputs INT3 and INT4 are connected to the TMS320VC5509 interrupt lines INT3 and INT4 through the FPGA The external interrupts are falling edge triggered just as all DSP interrupts Connector locations of these interrupts can be found in chapter 6 USER S GUIDE Date f 7 November 2006 LY UC1394a 1 DSP MASTER BSP of EON orsys Page 49 5 Detailed Interface Description This section describes the interfaces provided by the DSP Master BSP in detail On chip interfaces of the DSP are described by the respective documentation from TI which is listed throughout chapter 2 for each on chip interface 5 1 Peripheral interface The peripheral interface is based on the asynchronous memory interface of the DSP The components are selected using chip select signals IOCS 7 0 Within each chip select up to 256 different locations are addressable by IOADDR 7 0 The control signals are similar to other commonly used bus interfaces of DSPs or microcontrollers They are provided as a direction select strobe pair IOSTRB IOR W as well as separate strobe signals for each direction IOWR IORD Data is transferred on IODATA 15 0 with simple low level bus cycles that don t use higher lever protocols The timing of bus cycles is defined by the EMIF settings of the DSP and should be left as set up in the project examples because the peripheral in
16. UC1394a 1 DSP MASTER BSP ae dE rsys Page 87 7 4 3 Ambient Temperature storage temperature operating temperature 0 C Please note The ambient temperature can be higher than 60 C if the FPGA case temperature is limited to 80 C by appropriate cooling methods such as ventilation heat sinks and good thermal design of the carrier PCB 7 5 Soldering Process The UC1394a 1 is designed to be placed and soldered like an integrated circuit allowing mass production The UC1394a 1 can be soldered using vapor phase or reflow processes just like BGA packages Figure 21 shows an example of a temperature curve that was measured during production of the UC1394a 1 using a lead free reflow process Please note that the UC1394a 1 starting with S N 012231 is RoHS compliant and therefore produced using a lead free process For mounting older versions of the UC1394a 1 please contact Orsys Unless otherwise noted on the packaging baking is required before soldering Figure 21 Soldering temperature example USER S GUIDE Date l 7 November 2006 CX UC1394A 1 DSP MASTER BSP ee Orsys Page 88 7 6 Power Requirements the power requirements shown below are valid for both 144MHz and 200MHz versions of the UC1394a 1 The higher clock frequency of the 200MHz TMS320VC5509A is compensated by the newer power saving architecture so that the overall power consumption is the same or slightly less than the one of a 144M
17. an API for generic high level access to IEEE1394 e routines for setting up and using the MCM s DSP e project framework for creating own applications e application examples For easy start of development the UC1394a 1 with DSP Master BSP is available in form of general purpose or specialized development kits Please contact Orsys for further information on available development kits 2 1 Applications audio still image and low bandwidth video high speed data transmission distributed data acquisition RS 232 over 1394 connection of nearly any embedded system to the PC world via IEEE1394 I O expander for the PC via IEEE1394 point to point communication in embedded systems The IEEE1394 API may be replaced by some higher level API depending on some development kits Date 7 November 2006 my orays USER S GUIDE UC1394A 1 DSP MASTER BSP Doc no DSP master BSP UG Iss Rev 2 1 Page 13 2 2 Block Diagram PHY TSB41AB2 Peripheral Interface UO pins Config inputs Power supply UC1394a 1 MCM with DSP Master BSP LLC TSB12LV32 Figure 1 Internal block diagram of the UC1394a 1 withDSP Master BSP USER S GUIDE Date 7 November 2006 LF UC1394A 1 DSP MASTER BSP Cee ee e orsys Page 14 23 DSP The UC1394a 1 uses a 16 bit fix point DSP DSP type is either a TMS320VC5509 with 144MHz or a TMS320VC5509A with 200MHz The necessary set up of the DSP clock EMIF
18. and JTAG DSP EMU1 inputs have a 4 7kQ pull up resistor polarity built in termination handling when not used depending on specific signal leave open JTAG FPGA TCK JTAG FPGA TDO JTAG FPGA TDI JTAG FPGA TMS These pins can be used for downloading FPGA code They are used with Xilinx download cables together with the FPGA development option polarity built in termination handling when not used depending on specific signal leave open e USER S GUIDE Date l 7 November 2006 y UC1394a 1 DSP MASTER BSP PE aaa Orsys Page 86 73 Dimensions of the UC1394a 1 36 6 nt O e a o d top and side view r WO o all dimensions in milimeters mm Figure 19 Dimensions of the UC1394a 1 including connector pins 37 08 1 46 C1 C1 M mmm M Bana 3 NG Ex S E ES i 2 o Z O S S ana 7 nnm mna 11 016 2 03 0 04 on all dimensions are in milimeters mm all dimensions are in inches compatible square layout for future versions Figure 20 Recommended PCB footprint of the UC1394a 1 Please note The PCB area below the UC1394a 1 should not be used for components 7 4 Environmental Conditions 7 4 4 Storage The UC1394a 1 can be stored in its original packaging for one year at the conditions given in chapters 7 4 2 and 7 4 3 7 4 2 Ambient Humidity Parameter storage non condensing operating non condensing e USER s GUIDE Date l 7 November 2006 Le
19. are currently supported for the DSP master BSP FPGA version applicable for UC1394a 1 with a 144MHz TMS320VC5509 UC1394a 1 with a 200MHz TMS320VC5509A Application software should check the version register after loading the FPGA Programming example include dsp master bsp h board support package basic hardware def s include fpga load h FPGA loader Z orsys Page USER S GUIDE Date l 7 November 2006 UC1394a 1 DSP MASTER BSP ea 72 load FPGA from Flash if FpgaLoad INT32U UC1394A FLASH FPGA CODE BASE UC1394A FLASH FPGA CODE LENGTH FPGA SUCCESS while 1 stop we do not have a LED as indicator yet check for correct FPGA version usFpgaVersion UC1394A VERSION amp UC1394A VERSION VER MASK gt gt 8 if bIs5509A if if usFpgaVersion 0x07 while 1 stop we probably do not have a LED as indicator yet usFpgaVersion 0x03 while 1 stop we probably do not have a LED as indicator yet USER S GUIDE Date l 7 November 2006 2 UC1394a 1 DSP MASTER BSP er e orsys Page 73 6 Hardware Implementation Guidelines This chapter shows the necessary connections for integrating the UC1394a 1 into a customized hardware environment A complete wiring example is shown in chapter 6 6 6 1 Power Supply The UC1394 1 requires a stabilized 3 3 V supply All of the supply and ground pins must be connected The carrier PCB mus
20. be configured e configuration inputs these I O pins can only be polled e external flag XF this is a dedicated output of the DSP which can be controlled by BSET BCLR instructions see 1 or 2 FPGA UO pins Bee O Input or output O gt Push pull or open collector c Interrupt capability oj CFG O inputs O O gt Inputs only O e O gt Output only Figure 9 I O pin block diagram Each FPGA I O pin can be individually configured to be an e input e push pull output e open drain output Date 7 November 2006 A USER S GUIDE Doc no DSP_master_BSP_UG UC1394A 1 DSP MASTER BSP lee Hey E orsys Em Input Push pull output Open drain output Figure 10 I O pin configurations 5 5 1 I O Pin Hardware Interface MCM connector pin Table 8 I O pin assignments 5 5 2 O Pin Programming Each FPGA UO pin is controlled by an associated FPGA pin control register PCR If configured as an input I O pins can generate interrupts These interrupts are OR ed together and connected to the INT1 input of the DSP All configuration inputs are read through the CFG register These inputs can only be polled and have no interrupt capability The XF pin can be set and cleared in C using asm statements as shown below Please note the whitespace before the XF instruction It prevents that the BSET instruction is interpreted as a label set XF pin to high 3 3V asm BSET XF set XF
21. fact that spurious interrupts may occur during the transfer caused by simultaneous FIFO access from the IEEE1394 chipset and the FPGA Address 0200C8i Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DMERR UN OV F AF AE E r 000000000 LW LW r w 0 HW rwO r w 0 rw O Empty interrupt enable E If this bit is set to 1 interrupts are generated while the empty flag is set Almost empty interrupt enable AE If this bit is set to 1 interrupts are generated while the almost empty flag is set Application software typically uses this bit for triggering transfers in transmit direction To trigger transmits by the AE flag application software must UsER s GUIDE Date l 7 November 2006 CH d UC1394a 1 DSP MASTER BSP He E e orsys Page 58 e program the AE level to FIFO size 4096 2 bytes minus the transfer size in bytes UC1394a STR AEL 4098 100 interrupt when gt 100 bytes fit in FIFO e install an interrupt handler for DSP interrupt 2 C5xIntHook C5509 INT2 IsoTxIntHandler e clear and enable DSP interrupt 2 C5xIntClear C5509 INT2 C5xIntEnable C5509 INT2 e clear and enable FPGA interrupts through the AE flag UC1394A STR INTF UC1394A STR INTF AE UC1394A STR INTM UC1394A STR INTM AE e disable the interrupt after it has occurred UC1394A STR INTM 0 e transfer the data or start a data transfer using DMA e Clear the interru
22. flash memory and executed In case of problems the UC1394a 1 must be initialized by CCS as follows o Select Wiew gt Show Code composer from the menu o In CCS select File gt Load Gel from the menu locate UC1394a 1 master gel and click on Open select the GEL gt Initialization gt CPU reset and init 200MHz from the menu select the File gt Reload Program command from the File menu select the Debug gt Run from the menu Now Code Composer Studio must display the cursor at DoMessageProc in the disassembly window o In FlashBurnDSK repeat the last step s O O O O Further help can be found in the help menu of FlashBurnDSK or at 16 e USER s GUIDE Date 7 November 2006 Ly UC1394a 1 DSP MASTER BSP EE E Orsys Page 328 4 7 Hints for Programming the TMS320VC5509 4 7 1 A Byte is 16 Bits Please note that the TMS320VC5509 can only access data in units of 16 bit Even a character array will consist of 16 bit The screenshots below illustrate this mi Memory DATA 16 Bit Hex TI Style DAS 0055 B041 0052 0054 Figure 4 Memory view of a string in binary format E Further information can be found in 4 chapter Memory and I O space and in 7 chapter Data types 4 7 2 64K Page Limit The TMS320C5000 series DSPs use a 16 bit architecture which adds restrictions to pointer accesses Although the DSP as well as the C compiler support 23 bit point
23. limited FIFO size it is recommended to use a smaller value for packets with 2048 or more bytes payload Otherwise the FIFO is not emptied until it is nearly full and FIFO overflows may occur Programming example include dsp master bsp h board support package definitions sSetup uiIsoPacketsizeInQuads 0x100 1024 bytes per packet this is the default and very safe trigger method The FIFO causes an interrupt whenever a complete packet is in the FIFO This is safe but doesn t allow full bandwidth UC1394A STR FIFO AFL 4 sSetup uilsoPacketsizeInQuads Adaress 0200C616 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED AF_LEVEL r 000 r w 1FE046 Almost full level AF_LEVEL This bit field determines the almost full level in bytes Only even numbers of bytes are allowed AF LEVEL 0 is ignored and is always set to 0 e USER S GUIDE Date l 7 November 2006 Le H UC1394A 1 DSP MASTER BSP oe orsys Page 57 5 3 1 1 6 Streaming port FIFO almost empty level register STR AEL Description This register controls the almost empty AE flag of the streaming port s FIFO If the FIFO contains AE LEVEL or less bytes the almost empty flag will become active This register can be used to implement a flow control mechanism Application software typically uses this register when transmitting streaming data and sets it to the FIFO size minus packet payload size This causes
24. location holds 16 bit of data To access a memory location use a pointer to the desired address C code example int 0x8000 accesses the first location of on chip SARAM Please note Accesses to program memory are done using byte addresses For example address 1000 in data memory space equals address 200046 in program memory space This is important to know when debugging your code The processor s on chip peripherals are located within the I O memory page and must be accessed using special instructions For details please refer to 7 chapter The ioport keyword The I O page memory map is not shown here Please refer to 2 for details USER S GUIDE Date 7 November 2006 CR UC1394a 1 DSP MASTER BSP er e orsys Page 45 00006216 003FFF on chip dualaccessRAM_ 02300045 gt dmm 6 LLC and FPGA registers reserved repeated occurrence of LLC and FPGA registers Table 1 CPU address map 4 11 2 Internal RAM of the Processor The internal RAM consists of 256 kB It can be used by application software for any purpose Usually speed critical code and data should be placed in the internal RAM Please note that the first locations in internal memory are reserved for memory mapped registers and for DSP boot loader usage 4 11 3 Flash Memory The Flash memory consists of 512 kB nonvolatile storage It is used for storing application code and FPGA code FPGA code can only be ch
25. more time to finish the access 7 9 Reset Timing m lam min RESETIN input pulse width 280ms RESETOUT pulse width Table 29 Reset timing 7 10 I O Pin Timings For the I O pins no timings are defined because the I O pins mainly depend on software processing n USER S GUIDE Date 7 November 2006 LJ y UC1394a 1 DSP MASTER BSP WU T e orsys Page 93 8 Glossary ADC analog to digital converter BSP board support package a specific combination of software and FPGA design that adds certain functions to the UC1394a 1 Byte A data word consisting of 8 bits of data This terminology appears in the IEEE1394 standards and is also commonly used CCS Code Composer Studio An integrated development environment for Configuration ROM Doublet Endiannes firmware FPGA Ee IEEE1394 LED LLC LSB LSW MCM MSB MSW McBSP n a open collector output open drain output Phy push pull output Quadlet root directory RSV RTC TBC TBD USB digital signal processors provided by Texas Instruments a well defined location that must be implemented in each device lt contains information about the device such as capabilities and supported software protocols A data word consisting of 16 bits of data This terminology appears in the IEEE1394 standards The order in which data words are assembled to larger entities i e bytes to quadlets The IEEE1394 standards use big endian notation so the most signif
26. pin to low 0V asm BCLR XF n USER S GUIDE Date l 7 November 2006 LF UC1394a 1 DSP MASTER BSP naay a a e orsys Page 67 5 5 2 1 Pin control registers PCR Description These registers control operation of the I O pins Each register has an associated I O pin e g PCR 0 is associated with l OO Address 02008046 02008416 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED IPOL ISRC IF IE O MOD DIR DAT r 00000000 r w 0 r w 00 r we 0 r w 0 r w 0 LW r w 0 Pin state DAT For input pins this bit reflects the current state of the pin DAT read only For output pins this bit controls the current state of the pin and can be read back Pin direction DIR This bit controls the pin s direction Output mode O MOD This bit field configures the behavior of the I O pin when configured as an output In input mode DIR 0 this bit field has no meaning O MOD output type o open collector default push pull totem pole output Interrupt enable IE For input pins this bit controls whether or not interrupts are generated by this pin For output pins this bit has no effect If an interrupt is currently pending IF 1 and is disabled IE 0 it will become active as soon as IE is set to 1 Therefore it might be necessary to clear previously pending interrupts before IE is set to 1 IQ disabled default Interrupt flag IF The interrupt fla
27. purpose output The McBSP signals are directly connected to the DSP Please refer to 5 for a detailed description polarity built in termination handling when not used programmable McBSPO CLKR McBSP1 CLKR McBSP2 CLKR Data receive clock of the respective McBSP interface This pin can also be used as a general purpose UO pin The McBSP signals are directly connected to the DSP Please refer to 5 for a detailed description polarity built in termination handling when not used bi directional programmable none leave open or pull up McBSPO CLKX McBSP1 CLKX McBSP2 CLKX Data transmit clock of the respective McBSP interface This pin can also be used as a general purpose UO pin The McBSP signals are directly connected to the DSP Please refer to 5 for a detailed description built in termination handling when not used bi directional programmable none leave open or pull up McBSPO FSR McBSP1 FSR McBSP2 FSR Receive frame synchronization I O of the respective McBSP interface This pin can also be used as a general purpose UO pin The McBSP signals are directly connected to the DSP Please refer to 5 for a detailed description polarity built in termination handling when not used bi directional programmable none leave open or pull up McBSPO FSX McBSP1 FSX McBSP2 FSX Transmit frame synchronization I O of the respective McBSP interface This pin can also be used as a general purpose UO pin T
28. the AE flag to be set whenever one complete packet fits into the FIFO However due to the limited FIFO size it is recommended to use a smaller value for packets with 2048 or more bytes payload Otherwise the FIFO can t be filled in time and transmit performance will be degraded Programming example include dsp master bsp h board support package definitions sSetup uiIsoPacketsizeInQuads 0x100 1024 bytes per packet this is the default and very safe trigger method The FIFO causes an interrupt whenever a complete packet fits into the FIFO This is safe but doesn t allow full transmit bandwidth UC1394A STR FIFO AEL UC1394A STR FIFO SIZE 4 sSetup uilsoPacketsizeInQuads Address 0200C7 15 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED AE LEVEL r 000 r w 001 Eie Almost empty level AE LEVEL This bit field determines the almost empty level in bytes Only even numbers of bytes are allowed AE LEVEL 0 is ignored and is always set to 0 5 3 1 1 7 Streaming port interrupt mask register STR INTM Description This register controls the generation of interrupts for the streaming port Application software can use this register to enable and disable interrupts that trigger data transfers or indicate error conditions Please note although the FPGA interrupts can automatically trigger DMA transfers the transfers should always be triggered by software The reason for this is the
29. 11 10 9 8 7 6 5 4 3 2 1 0 TAG CHANNEL NUMBER TCODE SYNC r w 00 r w 000000 r w 1010 r w 0000 SYNC This bit field specifies the sync bit pattern The LLC inserts this bit pattern in the header of the first packet of a frame A frame is a contiguous sequence of isochronous packets The default for this bit field is 0 On the UC1394a 1 the frame size is set up in the STR_FRMSZ register For the USER S GUIDE Date 7 November 2006 2 UC1394a 1 DSP MASTER BSP wu de Orsys Page 55 IEEE1394 API the frame size must be set equal to the packet size parameter QuadletsPerFrame of sbilsoTalk must be set to 4 the value of parameter iPacketDataSizeBytes Application software can use the SYNC bit field for synchronization on the receiver side and to indicate a new section of streaming data such as a new picture frame in case of image camera data See also the description of the RXSYNC bit in the STR CTL register TCODE This bit field specifies the transaction code for the packet to be sent The default value is A16 defined as uc1394a STR HDR1 TCoDE IsocH str in dsp master bsp h which identifies the packet as a isochronous streaming packet Application software should not change this value CHANNEL NUMBER The channel number specifies the isochronous channel for outgoing packets Several data sources can perform isochronous streaming on different channels simultaneously provided that the overall bandwidth isn t exceeded
30. 2 bit number into a character string in decimal ASCII representation The Character string consists of 10 characters and contains a leading zero if the result is less than 1000000000 defined in decutil h synopsis void DecUnsignedDword2Ascii INT32U digit char pResult parameters digit number to be converted pDebug Text pointer to storage for the converted string return value none 4 10 31 DecUnsignedNibble2Ascii Converts an unsigned 4 bit number into a character string in decimal ASCII representation The Character string consists of 2 characters and contains a leading zero if the result is less than 10 defined in decutil h synopsis void DecUnsignedNibble2Ascii INT8U digit char pResult parameters digit number to be converted pDebugText pointer to storage for the converted string n USER S GUIDE Date l 7 November 2006 2 UC1394a 1 DSP MASTER BSP er Es Orsys Page 43 return value none 4 10 32 DecUnsignedWord2Ascii Converts an unsigned 16 bit number into a character string in decimal ASCII representation The Character string consists of 5 characters and contains leading zeros if the result is less than 10000 defined in decutil h synopsis void DecUnsignedWord2Ascii INT16U digit char pResult parameters digit number to be converted pDebugText pointer to storage for the converted string return value none 4 10 33 HexByte2Ascii Converts a 8 bit number into a string 00
31. 4a 1 DSP MASTER BSP er e Orsys Page 3 4 PROGRAMMING THE UG1394A 1 aNG BIGKAS 18 21 Hedgulled TOONS ama 18 4 2 Software Development Flow rrrnnnnnnvnnnnnnnnvnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 18 4 2 1 Module Support Library EE 19 43 Startup Proc 0 fee eee 20 4 4 System Milana AA Ama aa 21 45 Main Loop EN 23 4 6 How to Store an Application in Flash Memory eere 24 4 7 Hints for Programming the TMS320VC5509 esee eene enne ennt 25 7 1 A Byte is 16 BE e Cm 25 4 7 2 E E 25 475 POE eee 25 48 Global Variables Reference mmmimemnrremssesnrrsmnsennrisanennerknknannknekkkndnnenesmandvnkkdanndavnennadaeknane 26 281 DSP TE ee EE Ee Ke E 26 4 8 2 Interrupt Vector iio er 27 49 Macros Reference La GABI AABANG 27 49 1 De bugOulBylaHex i e n Kaanak 27 492 DebugOutConstString EE 27 BOS DebugOutDwordHeXx eege eege 27 4 9 4 DebugOutNibbleHeXx se 28 295 DO MAE 28 4 9 6 eeneg 29 4 9 7 ee Ee 29 295 awe Re mm 29 LUE CUS RTE 30 NNN 30 29171 DeEDUGOUIIDWOMIDEC Es 30 49 12 ee EE 31 49 13 DebugOutUWordDec isneinemmneemen a GA Aa 31 4 9 14 Deg EK E 31 4 10 Functions BeleFGn6B uis nda vn dida on eaa dix adi li dc d ce oni dcr abra Giai HR GE a RE 32 LIO BED D rnm 32 4 10 2 51410010 EEE utm kemietadiu Gia a AE Ren bu raE Ud end rat die er audi 32 410 3 EEN 33 ek EE TE Lr T 33 EE e AA gehcnemiaeens 33 100 LEO E AA 34 4
32. 7 November 2006 Doc no DSP BSP Vag y UC1394a 1 DSP MASTER BSP Vai E Orsys Page 75 local supply 8 30V Diode prevents current flow L LJ 1A fuse back into local power supply protects Power against supply excessive currents 3 3V Voltage em GND 6 pin IEEE1394 connector IEEE1394 TPB TPB TPA TPA Figure 15 Supplying power to the IEEE1394 cable 6 3 RS 232 Level Converter Figure 16 shows a wiring example and Table 11 shows the required cable wiring A detailed schematic example is shown in Figure 18 Using a 3 3V type is recommended 9 pin Sub D connector Figure 16 Wiring of the UART interface Level converter Sub D 9 pin_ Sub D 25 pin RD IS 2 TxD 13 8 Bg o CIS GND 5 Table 11 Required cable connection to a host PC RxD TxD CTS GND 6 4 JTAG Interface The JTAG Interface is not needed during operation or configuration However it provides a possibility for debugging or for firmware updates in situations where the firmware loader doesn t USER S GUIDE Date 7 November 2006 Le UC13944 1 DSP MASTER BSP ae PE Orsys Kag a work If the application permits the JTAG signals of the DSP should be available in end application environment for service purposes The FPGA JTAG signals are not required Figure 17 shows the wiring of the JTAG connector that can be used with the standard development tools st
33. BSPO DX A5 X SC INVALID Hg X McBSPO_CLKR ag X FORCEON 55 ee McBSPO CLKX HA7 X FORCEOFF McBSPO_FSR Lag X McBSPO FSX X MAX3225CAP Aessen pn L I McBSP1 DX L McBSP1 CLKR Leg X McBSP1 CLKX 85 X McBSP1_FSR h g X McBSPi_FSX X McBSP2 DR LB McBSP2 DX Lenz McBSP2 CLKR eX McBSP2_CLKX Lg X McBSP2 FSR eis X McBSP2 FSX X Figure 18 Required connections UC1394a 1 DSP Master BSP USER S GUIDE Date l 7 November 2006 y UC13944 1 DSP MASTER BSP Lao a orsys Page 78 7 Technical Data 7 1 Signal Overview and Connector Pinout Tables This chapter defines all signals that are supported by the UC1394a 1 with DSP master BSP The shaded entries in Table 12 show signals that are always available independent of the board support package whereas all other signals are specific to the DSP master BSP Connector B Connector C Dr 3 3V McBSP1 DR TPB1 GND McBSP1 DX TPB1 DATAO McBSP1_CLKR TPA1 DATA1 McBSP1_CLKX TPA1 McBSPO CLKR DATA2 McBSP1 FSR GND 6 McBSPO CLKX DATA3 McBSP1 FSX ADDRO 7 McBSP0 FSR DATA4 GND ADDR1 McBSPO FSX DATA5 McBSP2 DR ADDR2 8 9 RESET OUT DATA6 McBSP2 DX ADDR3 RESET_IN DATA7 McBSP2_CLKR ADDR4 GND McBSP2_CLKX ADDR5 CFGO DATA8 McBSP2
34. D Bs GND Ba DATAO ae GND GND GND GND B5 Date GND B7 DATA3 GND B8 DATA4 GND B ag 6 ao DATA GND GND Reset pushbutton B13 DATAS ag 1 3 ez DATA9 RESET OUT Aio X p 11 B15 DATA10 RESET IN GND Big DATA B17 DATAI2 A22 IEEE1394 Big DATA13 1394 TPAO Apg X 4 pin connector Big DATA14 1394 TPAO ASF X 4 pin connecto DATA15 1394_TPBO FAE as defined in Di4 1394 TPBO 7X 1394a 2000 D15 csi D4 Dig 1 C82 1394_TPA1 CES 4 TPA D17 C53 1394_TPA1 pp 3 TPA nar cSt 1894 TPB1 DT 2 TPB B r C95 1394 TPB1 1 TPB D25 S8 GND shield get a JTAG DSP gun 218 B22 QUE a DE EN C17 DSP JTAG connector E Gan JTAG DEP TOK Gig Program download and debugging ec IORW JTAG DSP TDO r ze IORDY JTAG DSP TDI 057 pa m pal JTAG DSP TMS 11 EMUO EMU 12 D27 NTS c22 g TCK GND 55 GND e mere ee CH ger SE E A17 JTAG FPGA TDI E 3 av 02 3 3 5V 4 RS 237 interface Ag UART TxD JTAG FPGA TMS x UD Ka Jeun 20 HART OTS us8 DP 223x 3 3V0 121 43 5v ct E AGBRE USB DN 230 Emulator connector if i De x212 yoo Deas spacing g T0on ipon oon or 4 D20 or AN 3 2x pin 6 removed o C24 Bae 02 AIN 2 SIX oH x TT lo sias On xD22 103 AN L O15 X opp 6 HE 104 AN 0 X Oo 17 C2 13 A12 os AI IKOt TXM k 245 CFGO D32 0 5 TXO2 TXI2 544 CFG1 120 SOL Lex 10 OTs 16 15 ag CFG2 I2C SDA X X OF g Bai RXO1 Hio X8 CFG3 x oj x RXI2 RXO2 x CFG4 KG 1 698 McBSPO DR Ay X SUB D 9 connector READY jr X X XFOUT Mc
35. E 1394 ports The IEEE1394 interface is typically used for high level and high speed connections to other intelligent devices such as host PCs or cameras Application software accesses the IEEE1394 interface over an API which is included in the development kits Depending on the development kits different levels of IEEE1394 operation are available With the DSP Development Kit 15 customers have full access to IEEE1394 and can implement generic IEEE1394 operation with user defined protocols With the DCAM Frame Capture Kit high level access to IIDC DCAM compliant cameras is supported On all kits the following IEEE1394 features are supported e operate the IEEE1394 transaction layer e bus management e asynchronous transactions e high speed software data streaming Software streaming is done over a register interface which is implemented in the FPGA Software streaming allows transparent low level data transfer with minimum software overhead A detailed description of the IEEE1394 interface can be found in chapter 5 2 Software streaming is described in chapter 5 3 2 7 UART interface The UART interface is compatible with the standard RS 232 interfaces in personal computers Different baud rates are supported as well as RTS CTS handshake e USER S GUIDE Date l 7 November 2006 Le H UC1394A 1 DSP MASTER BSP Wap aa orsys Page 15 The UART interface is typically used for low speed control and status exchange with ex
36. FSR ADDR6 13 CFG1 DATA9 McBSP2 FSX ADDR7 CFG3 GND JTAG_DSP_EMU1 JTAG DSP EMUO 17 UART TxD JTAG DSP TRST Ea UART RxD JTAG DSP TCK MART RTS DATA15 JTAG DSP TDO GND JTAG DSP TDI mme JTAG DSP TMS JTAG FPGA TCK JTAG FPGA TDO JTAG FPGA TDI JTAG FPGA TMS 26 AINO USB DP AIN1 USB DN 31 AIN2 GC SDA AIN3 20 SOL Pin function independent of the DSP Master BSP Table 12 Pinout sorted by pins USER s GUIDE Date l 7 November 2006 UC1394a 1 DSP MASTER BSP GE Page 79 CSS D23 C14 C28 Table 15 I O pin signals D18 D28 RESET IN A10 RESET OUT c OT Table 16 UART interface signals Table 17 DSP JTAG signals UC1394A 1 DSP MASTER BSP USER S GUIDE Date 7 November 2006 Doc no DSP_master_BSP_UG Iss Rev 2 1 Page 80 McBSPO DR A3 McBSPO DX A4 McBSP1_FSX McBSP2_CLKR McBSP2 CLKX McBSP2 FSR McBSP2 FSX Table 19 McBSP signals Table 20 ADC signals Pin number GC SDA GC SCL Table 21 lC signals Pin number USB DP USB DN Table 22 USB signals USER S GUIDE Date l 7 November 2006 c UC1394a 1 DSP MASTER BSP a e Orsys Page 81 7 2 Individual Signal Description 3 3V Power supply for the UC1394a 1 These pins provide
37. Hz UC1394a 1 with a TMS320VC5509 DSP supply voltage 3 2V 13 3V 36V 450mA Table 23 Power requirements 7 7 Signal Levels and Loads In general all digital logic pins can be used with 3 3V signal levels Detailed specifications for each signal group are listed throughout this chapter CAUTION Applying more than 3 6V to inputs that are not 5V tolerant will damage the device 7 7 1 FPGA Signals A group of signals are connected to the FPGA They use a 5V input tolerant LVTTL I O standard Please refer to 11 for a detailed description of the FPGA s LVTTL signal levels The following signals include Peripheral interface USER S GUIDE Date 7 November 2006 I UC1394a 1 DSP MASTER BSP oe ee Orsys Page 89 Parameter Value Compatible I O standards 5V TTL 3 3V LVTTL 2 5V CMOS High input level 2 0V 5 5V High output level Low output level Table 24 Signal levels and loads for FPGA signals 7 7 2 Reset Signals RESET IN is connected to the on board power on reset circuit It can furthermore be pulled low by the FPGA Therefore RESET IN is a bi directional signal A 4 7kQ pull up resistor gives a default level of 3 3V at no load Parameter Value Compatible I O standards 3 3V LVTTL 2 5V CMOS High input level 2 3V 3 3V Low input level OV 1 0V Table 25 RESET IN signal levels RESET OUT is a push pull output which is directly driven from the on board reset genera
38. IFO remains full the full flag will be set again after it was cleared Application software can use this bit for test purposes e g for determining the FIFO size Streaming port FIFO overflow flag OV This bit indicates an overflow condition this means an attempt was made to write to the FIFO of the streaming port while the FIFO was full An overflow occurs if e in receive direction the DSP does not read the data from STR DATA fast enough slower than the IEEE1394 chipset e in transmit direction the DSP writes to STR DATA faster than the IEEE1394 chipset reads the data The overflow flag will be set each time a write to a full FIFO is performed To clear this error indication write a 1 to the OV bit In general overflow errors should be avoided by triggering data transfers by the fill level related interrupts FIFO flags AE for transmit AF for receive Application software should regularly poll this bit for detecting transfer errors Streaming port FIFO underflow flag UN This bit indicates an underflow condition this means an attempt was made to read from the FIFO of the streaming port while the FIFO was empty An underflow occurs if e in receive direction the DSP reads more data than available faster than the IEEE1394 chipset fills the FIFO e in transmit direction the DSP writes to STR_DATA slower than the IEEE1394 chipset transmits the data The underflow will be set each time a read from an empty FIFO is performed To cl
39. Kit User s Guide Orsys DSP Devkit UG paf 16 FlashBurn homepage Software Design Solutions INC www softwaredesignsolutions com
40. LC and FPGA register overvieW EE 46 Table 4 LLC and FPGA register map 47 Tabi Interrupt BEE re 48 Fable 6 Peripheral interface signal iN RNB 50 Table 7 UART connector pin assignments aaa AA AA 62 Table 8 VO pin ie lu TC 66 Table 9 Pinning of the IEEE1394 connechors Hee 73 Table 10 IEEE13984 connector part numbers aaa NAA KA accents Rs nen 73 Table 11 Required cable connection to a host PC 75 Table 12 Pinout sorted by Ps s eoe ER ettet hi cag Rohde Deed hates or ule be Papi oes Con Edu pire ERR ER US omens 78 Table 13 Power supply and reset signals icr tere ete ER ENNER E n ec ia x ea ikea ir 79 Table 14 Peripheral interface signals iiie etr bert rar esi senos ch pra Cover pus s dde henne 79 Table 15 I O PNAS 79 Table 16 UART interface E 79 Table TPM Ia EE 79 Table 16 Ee TE 80 Table 19 as SAL CN 80 Table 20 ADC SA Mm 80 ERE EE 80 able ENN 80 Fable acp i e Pia CRT LI EE 88 Table 24 Signal levels and loads for FPGA signals rrnnrnnnrrnnnnrrrrrnnnnnrnrrrnnnnnnnrnnnnnnnnvnnnnrnnnnnnnerenn 89 Table 25 RESET IN signal levels AEN 89 Table 26 AR ME EN 89 Table 27 Signal level and loads for the DSP aonals 90 Table 28 Allowed input voltage range for the ADC inputs s essssnnsseeeeneeneresserrnrerernrrsrnrrnssrrrnne 90 Table 29 Reset MING E 92 List of Figures Figure 1 Internal block diagram of the UC1394a 1 withDSP Master BG 13 Figure 2 Software development Now maa GA AA 19 Figure 3 Memory vie
41. R r 00000000 r w 0 r 00 r 0 r r w 0 w 0 r w 0 i USER S GUIDE Date l 7 November 2006 y UC1394a 1 DSP MASTER BSP GE E orsys Page 53 Streaming direction DIR This bit controls the direction of the streaming port as follows DIR Direction 0 recei receive from 1394 network to streaming port default transmit from streaming port to 1394 network The FIFO of the streaming port is not cleared by a direction change Therefore data can be written to it and read back for test purposes Notes on direction change 1 A direction change on the streaming port always requires that the DMRX bit of the LLC DM Control register is set accordingly This is usually done by 1394 API software e g by calling sbilsoListen sbilsoTalk preceded by sbilsoStop if necessary To avoid bus contention on the between FPGA and IEEE 1394 chipset the following sequences must be performed a direction change from receive to transmit e First change direction of LLC call sbilsoStop then sbilsoTalkt e then set the DIR bit in the streaming port s control register b direction change from transmit to receive e First change direction of the streaming port by clearing the DIR bit in the streaming port s control register e then change direction of LLC call sbilsoStop then sbilsoListen 2 Before the direction is changed it must be guaranteed that no transfer between FPGA and LLC is currently act
42. Register SYS CTL This register controls two functions e the red LED that is located on the UC1394a 1 e asoftware triggered hardware reset Several sources can drive the LED for diagnostic purposes The LED can also be controlled by application software using the LED bit When LEDSRC is set to its default value of zero the LED can be controlled by the functions LedOn and LedOff of the module support library Address 02004016 USER S GUIDE Date 7 November 2006 c UC13944 1 DSP MASTER BSP ee s orsys Page 70 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SWR LED RESERVED LEDSRC r 0000000 WO rwo r 000 r w 000 LED source selection LEDSRC This bit field controls which signal controls the LED It is encoded as follows LEDSRC value controlling source manual control through LED bit default LLC STATO pin LLC register accesses LED control bit LED This bit controls the LED when LEDSRC is set to manual LED control Application software can use the LED as an optical indicator e g for system status display If this bit is set to 1 the red LED of the UC1394a 1 will light Software reset SWR This bit can be used to reset the complete system by software When this bit is set to 1 a hardware reset will be issued by pulling the RESET IN line low for a short time so the system will behave exactly like it does when an external reset is asserted Reading the
43. SWR bit always returns 0 5 6 2 Watchdog Control Register WDG The UC1394a 1 has a built in watchdog timer which can be used to recover from fatal conditions such as deadlocks or software crashes The watchdog timer if enabled must be reset periodically for normal operation This is usually done by a function that is called periodically and which is vital for the user s application In case of a fatal condition the watchdog timer will no longer be reset it will it time out and a system reset will be triggered This is done by the FPGA pulling the RESET IN line low for at least 1us so the system will behave exactly like it does when an external reset is asserted Address 02004115 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED WDE WDR r 00000000000000 r w 0 w 0 watchdog reset WDR Each time this bit is written as 1 the watchdog timer is reset and the system operates normally This bit has no effect if the watchdog timer is disabled WDE set to 0 WDE is always read as 0 The WDR bit must be written at least once per second to keep the watchdog permanently reset The watchdog must be reset first before it is enabled watchdog enable WDE This bit field selects the source from which the watchdog can be reset It is encoded as i USER S GUIDE Date l 7 November 2006 y UC1394a 1 DSP MASTER BSP a ee orsys Page 71 watchdog status o watchdog disabled manual res
44. TS CTS handshake is enabled see chapter 5 4 2 2 RTS is controlled by the UART hardware A logic low level on this signal indicates that the UART interface can accept more data If RTS CTS handshake is disabled RTS is always active UART_CTS Handshake input of the UART interface For RS 232 usage this signal must be connected to a level converter An example is shown in Figure 18 If RTS CTS handshake is enabled see chapter 5 4 2 2 the UART hardware only transmits characters if UART_CTS is active low If RTS CTS handshake is disabled this input is ignored 5 4 2 UART Programming The UART interface is accessed through three FPGA registers UART receive data UART transmit data UART control and status register Using the UART interface is straightforward Initialize the UART interface by writing the desired configuration baud rate handshake to the UART control register Then data can be transferred using the transmitter and receiver ready flags and the UART data register Programming example include dsp master bsp h board support package definitions initialize UART for 115200 baud and hardware handshake UsER s GUIDE Date 7 November 2006 Ly d UC1394a 1 DSP MASTER BSP Wap pr E e orsys Page 63 UC1394A UART CTL UC1394A UART CTL BAUD 115200 UC1394A UART CTL HS RTS CTS check if a character can be sent if UC1394A UART CTL amp UC1394A UART CTL TXRDY transmit a char
45. UC13944 1 DSP MASTER BSP NN a Orsys Page 94 9 Literature References Further information that is not covered in this user s guide can be found in the documents listed below References to this list are given in square brackets throughout this document The documents are listed by title author and literature number or file name 1 TMS320VC5509 Fixed Point Digital Signal Processor Data Manual Tl sprsie3 2 TMS320VC5509A Fixed Point Digital Signal Processor Data Manual Tl sprs205 3 TMS320VC5509 Digital Signal Processor Silicon Errata Tl sPRzooe 4 TMS320C55x DSP CPU Reference Guide Tl spru371 5 TMS320C55x DSP Peripherals Reference Guide Tl sPRu317 6 TMS320C55x Assembly Language Tools User s Guide Tl spru2so 7 TMS320C55x Optimizing C C Compiler User s Guide Tl seRu281 8 FireWire System architecture by Don Anderson Mind Share Inc ISBN 0 201 48535 x 9 EEE Standard for a High Performance Serial Bus JEEE sta 1394 1995 10 EEE Standard for a High Performance Serial Bus Amendment 1 IEEE sta 1394a 2000 11 EEE Standard for a Control and Status Registers CSR Architecture for Microcomputer Buses IEEE sta 1212 2001 12 Spartan Il 2 5V FPGA Family DC and Switching Characteristics Xilinx Ds001 3 www xilinx com 13 TSB12LV32 IEEE1394 and P1394a Compliant General Purpose Link Layer Controller Tl spru317 14 User Guide IEEE1394 embedded API Orsys emb 1394 API UG paf 15 DSP Development
46. UC1394a 1 DSP MASTER BSP ed s orsys Page CYA return value FLASH OK Operation was successful 4 10 15 FlashProgram Programs data into a previously erased area During programming a user specified callback function is executed to allow the application to continue processing or to indicate the progress of the operation The callback is called each time when 250 words have been programmed to the flash After programming the programmed data is verified defined in flash29lv400 h synopsis int FlashProgram INT32U ulStartOffset INT32U ulLengthInWords INT16U pusData void pCallback void parameters ulStartOffset Destination offset relative to start of the flash specified in 16 bit words Allowed values 0000000046 0004000015 or one of UC1394A FLASH SAO OFFS UC1394A FLASH SA10 OFFS ulLengthInWords Number of 16 bit words to program pusData Points to the source data pCallback User callback function return value FLASH OK Programming was successful FLASH COMPARE ERROR Verification of the programmed data failed 4 10 16 FlashRead Reads a block of data from flash memory Can be used to load application specific data from flash defined in flash29lv400 h synopsis void FlashRead INT32U ulStartOffset INT32U ulLengthInWords INT16U pusData parameters ulStartOffset Offset relative to start of the flash specified in 16 bit words Allowed values 00000000i 0004000016 or one of UC1394A FLASH SAO OFFS
47. acter UC1394A UART DATA pTxBuffer 5 4 2 1 UART Data Register UART DATA Description This register is used to transfer data from and to the UART interface Data written to it will be transmitted on the UART interface Received data can be read from this register Before accessing this register the status bits of the UART TXRDY and RXRDY should be checked Address 02005015 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UART_DATA r 00000000 r w UART_DATA Read Accesses Only 8 bit receive data Read accesses to this register read one character from the 16 bit receive FIFO If the FIFO is empty the last read value is repeated Please check for available characters before reading this register include dsp_master_bsp h board support package definitions check for incoming characters if UC1394A UART CTL amp UC1394A UART CTL RXDY INT8U ucRxChar UC1394A UART DATA process incoming character UART DATA Write Accesses Only 8 bit transmit data The character that is written to this register is converted to serial format and transmitted on the TxD line as soon as e no other character is currently being transmitted and e RTS CTS Handshake is disabled or CTS is active low Before writing to the transmit data register software must check if the transmitter hardware can accept a new character include dsp master bsp h board support package definitions can I send n
48. acter string consists of 2 characters starting with either space for positive numbers or for negative numbers defined in decutil h synopsis void DecSignedNibble2Ascii INT8U digit char pResult parameters digit number to be converted pDebugText pointer to storage for the converted string return value none 4 10 28 DecSignedWord2Ascii Converts a signed 16 bit number into a character string in decimal ASCII representation The Character string consists of 6 characters starting with either space for positive numbers or for negative numbers The string contains leading zeros if the absolute value is less than 10000 defined in decutil h synopsis void DecSignedWord2Ascii INT16S digit char pResult parameters digit number to be converted pDebugText pointer to storage for the converted string return value n USER S GUIDE Date l 7 November 2006 2 UC1394a 1 DSP MASTER BSP er Es Orsys Page 42 none 4 10 29 DecUnsignedByte2Ascii Converts an unsigned 8 bit number into a character string in decimal ASCII representation The Character string consists of 3 characters and contains leading zeros if the result is less than 100 defined in decutil h synopsis void DecUnsignedByte2Ascii INT8U digit char pResult parameters digit number to be converted pDebugText pointer to storage for the converted string return value none 4 10 30 DecUnsignedDword2Ascii Converts an unsigned 3
49. age 22 Now the FPGA resources are available and the debugging interface and also the UART interface can be initialized initialize debugging output this will also initialize the UART interface DebugInit Next part is the initialization of the 1394 API Device information configuration ROM location and some essential callbacks are passed to the API s initialization function Please note that this step and subsequent steps may look different depending on the actual development kit Get and show device information sInitInfo ulSerialNumberLow UC1394A FLASH SERIAL NUMBER sInitInfo ucSerialNumberHigh UC1394 CHIP ID HIGH DebugOutConstString Node vendor ID chipID high and serial number 00B02A DebugOutByt eHex sInitInfo ucSerialNumberHigh DebugOutConstString DebugOutDwordHex sInitInfo ulSerialNumberLow DebugOutConstString DebugOut UDwordDec sInitInfo ulSerialNumberLow DebugOutConstString r n r npress to get help page r n DebugFlush initialize the API sInitInfo pulDriverConfigROM sInitInfo ucSerialNumberHigh sInitInfo ulSerialNumberLow sInitInfo pBusResetCompleteCallback appBusResetCallback sInitInfo pErrorDetectedCallback appErrorDetectedCallback if iError sbilnitialize amp sInitInfo SBI NO ERROR ulConfigRom already initialized already initialized II II uon wou DebugOutConstString sbiInit DebugOutWor
50. and file for the hex conversion utility or by CCS initialization using a suitable GEL file See also description of eMode below Default initialization of the interrupt vector table causes deterministic behavior when uninitialized interrupts are triggered Clearing the interrupts prevents unwanted interrupts on startup when re starting an application during debugging defined in misc h synopsis void SetupDSP DSP MODE eMode parameters DSP MODE eMode Controls if and how the DSP is to be set up regarding clock generator and EMIF Must be one of eSameSpeed Leaves clock and EMIF settings untouched Should be used as default e144MHz Sets up CPU clock to 144 MHz and EMIF clock to 72 MHz independent of the actual DSP type Operation with a 200MHz TMS32VC5509A is not verified Please note that clock initialization may destroy SDRAM contents e200MHz Sets up CPU clock to 200 MHz and EMIF clock to 100 MHz if the DSP is a 200MHz TMS32VC5509A Please note that clock initialization may destroy SDRAM contents return value none 4 10 2 C5xIntHook defined in misc h Description Installs an interrupt handler for the given interrupt number in the interrupt vector table The interrupt numbers are defined in c5509 h The interrupt handler must be defined with the interrupt keyword n USER S GUIDE Date l 7 November 2006 CH 7 UC1394a 1 DSP MASTER BSP GE ER orsys Pap 2 synopsis void C5xIntHook int iIntNumber
51. andard 2x7 header 0 1 inch spacing Pin 6 removed JTAG interface JTAG DSP EMU1 JTAG DSP EMU ISTAG DSP TRST JTAG DSP TCK JTAG DSP TDO JTAG DSP TDI JTAG DSP TMS Figure 17 Wiring of the DSP JTAG interface 6 5 Unused Signals Signals that are not used can be left unconnected Most inputs have pull up resistors or keeper circuits see chapter 7 2 for details For the McBSP signals external pull up resistors can be added to avoid unnecessary power consumption caused by floating inputs The same applies to the USB interface here a pull up can be added to DP and a pull down to DN 6 6 Minimal Connection Example Figure 18 shows the required connections for basic operation of the UC1394a 1 MCM assuming that the following interfaces are being used e EEE1394 e UART interface e peripheral interface USER S GUIDE Date 7 November 2006 fy UC1394a 1 DSP M BSP Doc no DSP master BSP UG A A ASTER Iss Rev 2 1 orsys Pa 177 peripheral hardware 100nF 100nF 100nF 100nF D6 A1 D7 ADDRO 3 3V nog t 0 3 3V pg ADDRi 3 3V BT r O43 3V Ba ADDR2 43 3V Bog O43 3V pio ADDR3 3 3V 0 3 3V Bil ADBH4 A2 D12 ADDRS GND D13 ADDR6 GND ADDR7 GN
52. anged by means of a dedicated programmer executable supplied by Orsys Application code can be changed as described in chapter 4 6 Application code is stored as a boot data stream including a header that contains some initial register settings The DSP boot loader loads sets up the required registers especially EMIF registers and loads application code into RAM 0 200000 16KB Application code 7 23000015 64KB FPGA code 0 23800015 64KB Table 2 Flash memory layout 4 11 4 External RAM The external RAM consists of 8 MB SDRAM It can be used by application software for any purpose 4 11 5 FPGA registers These registers provide access to the interfaces that are implemented in the FPGA such as the UART interface or the peripheral interface Further the IEEE1394 link layer controller LLC is also accessed through the FPGA How to use the FPGA registers is described separately for each interface in chapter 5 USER S GUIDE Date 7 November 2006 no DSP BSP LJ y UC1394a 1 DSP MASTER BSP ge a orsys Page OG 4 11 6 FPGA register overview 02004016 02004Fi 02010016 0201FF peripheral interface CS1 address space 6 6 6 02020016 0202FFi peripheral interface CS2 address space 6 02030016 0203FF peripheral interface CS3 address space peripheral interface CS4 address space 02050016 0205FF amp peripheral interface CS5 address space 02060016 0206FF1s peripheral inte
53. ases it is recommended to access the data with 32 bit accesses using STR DATA This allows faster accesses than using STR DATA L and or STR DATA H separately However if 16 bit transfers must be used for some reason STR DATA L or STR DATA H can be used in any sequence since both registers are identical In receive direction STR DATA is read only Please note that for 16 bit accesses the most significant word is always transferred first The FIFO can be read back for test purposes in either direction However writing to the FIFO is only allowed in transmit direction DIR bit in STR CTL 1 Programming example include dsp master bsp h board support package definitions write one quadlet to the stremaing port UC1394A STR DATA 0x123345678 write some 16 bit words to the FIFO nd UC1394A STR DATA L 0x0001 MSW 2 quadlet UC1394A STR DATA L 0x0002 LSW of 2 quadlet UC1394A STR DATA H 0x0003 MSW of 3 quadlet UC1394A STR DATA H 0x0004 LSW of 3 quadlet UC1394A STR DATA L 0x0005 MSW of 4 quadlet UC1394A STR DATA H 0x0006 LSW of 4 quadlet Address 0200CE 0200CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO DATA r W X 5 4 UART Interface The UC1394a 1 MCM has an UART interface that can be used for standard asynchronous communication Different baud rates are supported as well as RTS CTS handshake The signals of the UART interface operate with LVTTL lo
54. built in termination handling when not used pull up FPGA leave open IORDY This pin is the active high ready input of the UC1394a 1 peripheral interface peripheral accesses the IORDY input is sampled by the processor If IORDY is sampled low the current access is extended by one EMIF clock and then IORDY is sampled again If IORDY is sampled high the access cycle completes If the connected peripherals do not use the IORDY signal IORDY should be left unconnected The necessary pull up resistor is provided on the UC1394a 1 Please note The IORDY input should only be used when the wait state generator see chapter 5 1 1 does not provide enough cycle time polarity built in termination handling when not used active high pull up FPGA leave open 00 O4 General purpose I O pins They can be used as e inputs e open drain outputs e push pull outputs Please refer to chapter 5 5 for details IO 4 0 have pull up resistors implemented in the FPGA polarity built in termination handling when not used bi directional active high pull up FPGA leave open XFOUT This pin is directly connected to the DSP of the UC1394a 1 It can be used as a general purpose output pin The default state of XFOUT after reset is high polarity built in termination handling when not used active high leave open UART TxD Transmit data output of the UART interface For RS 232 usage this signal must be converted to the appropr
55. clock EMIF interrupts etc SetupDSP eSameSpeed The interrupt handler of the IEEE1394 API is installed using C5x ntHook from the module support library install 1394 API s interrupt handler INT_LLC is defined in sbicfg h C5xIntHook INT LLC LynxHALNodeISR If other user interrupts are required they must be installed now Below is an example for installing a receive interrupt handler McBsp0 Rx ISR for McBSP Interface 0 C5xIntHook C55x RINTO McBspO Rx ISR C5xIntEnable C55x RINTO Then the FPGA is loaded from flash memory and the FPGA version register is checked for the correct version Please refer to chapter 5 6 3 for a list of suitable FPGA versions load FPGA from Flash if FpgaLoad INT32U UC1394A FLASH FPGA CODE BASE UC1394A FLASH FPGA CODE LENGTH FPGA SUCCESS while 1 stop we do not have a LED as indicator yet check for correct FPGA version usFpgaVersion UC1394A VERSION amp UC1394A VERSION VER MASK gt gt 8 if bIs5509A if usFpgaVersion 0x07 while 1 stop we probably do not have a LED as indicator yet else if usFpgaVersion 0x03 while 1 stop we probably do not have a LED as indicator yet After successfully loading the FPGA the red LED of the MCM is switched off switch off red LED which is on by default after FPGA load LedOff n USER S GUIDE Date l 7 November 2006 Le UC1394a 1 DSP MASTER BSP er s Orsys P
56. d unsigned long dummy vectab 32 4 8 2 Interrupt Vector Table The module support library maintains an interrupt vector table This table is initialized by SetupDSP User interrupt handlers can be inserted by calling IntHook The table is accessible from outside of the module support library in order to better support debugging Directly accessing the interrupt vector table should be avoided 4 9 Macros Reference This chapter lists the macros that are defined by the module support library Currently the only available macros are utility functions for debug c 4 9 1 DebugOutByteHex Converts a 8 bit number into a string hexadecimal and puts the string into the debug transmit buffer This is a macro that calls the functions HexByte2Ascii and DebugPuts defined in debug h synopsis void DebugOutByteHex INT8U digit parameters digit 8 bit number to convert and put to the debug interface return value none 4 9 2 DebugOutConstString Puts a string into the debug transmit buffer This is a macro that calls the function DebugPuts It is intended for constant string output 3 such as DebugOutConstString Hello world r n Pointers to strings will fail because the length of the string is not known at compile time defined in debug h synopsis INT16U DebugOutConstString char cString parameters cString output string for the debug interface return value number of characters actually written 4 9 3 DebugOutD
57. dHex iError DebugOutConstString r n DebugFlush Ledon exit 1 Now the API is initialized IEEE1394 processing is started by enabling LLC interrupts and causing a bus reset SbiCauseBusReset issue bus reset to get self IDs etc LLC INT ENABLE start processing of API events After processing the bus reset the API creates device handles for all devices that are present wait for bus enumeration to complete while sbiEnumerationCompleted FALSE DebugBufmgr YieldToCallQ DebugOutConstString DebugOutConstString r n show who is present on the bus ListNodes Q orsys UC1394A 1 DSP MASTER BSP Date 7 November 2006 Doc no DSP_master_BSP_UG Iss Rev 2 1 Page 23 USER S GUIDE For incoming transactions an address space is allocated This step strongly depends on the application and the protocol that is used The asynctst example simply allocates a buffer for test purposes at address 0 When implementing specific protocols such as defined by the IIDC or SBP 2 standard the protocol standard defines which address ranges must be allocated allocate address range for incoming transactions sRangeInfo pulBuffer aulBuffer sRangeInfo uiBufferLengthInBytes 4 ASYTST MAX BLOCKSIZE IN QUADS sRangeInfo iAccessType ACCESS TYPE READ ACCESS TYPE WRITE sRangeInfo usAddressStartHigh 0x0000 sRangeInfo ulAddre
58. dated to RoHS compliant production Implementation guidelines for IEEE1394 connectors revised Minimum pulse width for MCM internal reset on RESETIN removed UART interface Rx Tx FIFO mentioned Updated to current module support library modified function SetupDSP Updated to FlashBurn V3 x e USER S GUIDE Date l 7 November 2006 Le H UC1394A 1 DSP MASTER BSP ee orsys Page 12 2 System Overview The DSP Master board support package BSP adds software streaming capability and a flexible peripheral interface to the UC1394a 1 multi chip module MCM This creates a versatile development platform featuring low cost and small size ready to be used in high volume production lots The DSP master BSP provides the following interfaces a 16 bit parallel bus interface for connecting peripherals Two IEEE1394a ports with 400Mbps UART interface digital I O McBSP USB FC 4 ADC channels with up to 21 5kHz sampling rate real time clock The plug amp play capabilities of IEEE1394 allow the UC1394a 1 to recognize other devices on the IEEE1394 network to identify their protocol and to select a suitable partner device such as host computers cameras other UC1394a 1 devices etc In turn the UC1394a 1 will be recognized as a compliant IEEE1394 device by other devices The UC1394a 1 is fully interoperable with other devices on the bus such as cameras hard disks host computers etc This board support package includes e
59. debug transmit buffer This is a macro that calls the functions DecSignedDword2Ascii and DebugPuts defined in debug h synopsis void DebugOutsDwordDec INT32S digit parameters digit number to convert and put to the debug interface return value none 4 9 7 DebugOutSNibbleDec Converts a signed 4 bit number into a string of two characters and puts the string into the debug transmit buffer This is a macro that calls the functions DecSigneaNibble2Ascii and DebugPuts defined in debug h synopsis void DebugOutSNibbleDec INT8S digit parameters digit number to convert and put to the debug interface return value none 4 9 8 DebugOutString Puts a string into the debug transmit buffer This is a macro that calls the function DebugPuts Pointers to strings are allowed since the length of the string is determined at run time defined in debug h synopsis INT16U DebugOutString char pString parameters pString pointer to output string for debug the interface return value number of characters actually written e USER S GUIDE Date l 7 November 2006 Le y UC1394a 1 DSP MASTER BSP Dr orsys Page 30 4 9 9 DebugOutSWordDec Converts a signed 16 bit number into a string of 6 characters and puts the string into the debug transmit buffer This is a macro that calls the functions DecSignedWord2Ascii and DebugPuts defined in debug h synopsis void DebugOutSWordDec INT16S digit parameters
60. dition is only polled through the STR INTF register but FIFO full interrupts are not used FIFO overflow interrupt enable OV If this bit is set to 1 an interrupt is generated when data is written to a full FIFO Application software can use this bit for error checking However the OV bit is usually only polled through the STR INTF register but overflow interrupts are not used FIFO underflow interrupt enable UN If this bit is set to 1 an interrupt is generated when data is read from an empty FIFO Application software can use this bit for error checking However the UN bit is usually only polled through the STR INTF register but underflow interrupts are not used USER S GUIDE Date 7 November 2006 2 UC1394a 1 DSP MASTER BSP ee s Orsys Page 59 Datamover error interrupt enable DMERR If this bit is set to 1 an interrupt is generated when the LLC signals a datamover error Application software can use this bit for error checking However the DMERR bit is usually only polled through the STR_INTF register but data mover error interrupts are not used 5 3 1 1 8 Streaming port flag register STR_FLAG Description This register contains various flags most of them contain information related to the streaming port s FIFO It can be used by application software for polling the FIFO fill level and triggering transfers or for error detection The E AE AF and F bits are being set permanently while the respectiv
61. e fill level condition is active Therefore if for example the AF flag is cleared while the FIFO is still in almost full condition the AF flag is set again and the DSP receives a new interrupt All other flags are set by a temporary condition which is only active for a short time Address 0200C9 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DMERR UN OV F AF AE E r 000000000 r wc 0 r WC 0 r we 0 r wc 0 r we 0 r wc 1 r wc 1 Empty flag E This bit will be set whenever the streaming port s FIFO is empty It can be cleared by writing a 1 to it If the FIFO remains empty the empty flag will be set again after it was cleared To get the most recent state of the FIFO this bit should be cleared before it is checked Application software can use this bit for error checking Usually before and after a transfer the FIFO should be empty Programming example Check FIFO must be left empty from previous operation UC1394A STR INTF UC1394A STR INTF E PIPELINE DELAY if UC1394A STR INTF amp UC1394A STR INTF E 0 Almost empty flag AE This bit will be set whenever the streaming port s FIFO is almost empty see chapter 5 3 1 1 6 for details It can be cleared by writing a 1 to it If the FIFO remains almost empty the almost empty flag will be set again after it was cleared To get the most recent state of the FIFO this bit should be cleared before it is checked a
62. eaming UC1394A STR CTL UsER s GUIDE Date l 7 November 2006 CH d UC1394a 1 DSP MASTER BSP vr e orsys Page 54 Incoming cycle start detect RCYSTART This bit is read only If set RCYSTART 1 it indicates that a cycle start packet was received from the IEEE1394 bus Application software can poll this bit before starting streaming operation to ensure that a cycle master is present Without a cycle master isochronous streaming can t work and no packets are transmitted Please note that this bit is cleared after reading Therefore to get the most recent state of this bit it should be read twice Programming example include dsp master bsp h board support package definitions update the cycle start detect bit by a dummy read UC1394A STR CTL get the current time from the IEEE1394 chipset ulNow sbiGetElapsedCycleTime 0 wait with two cycles timeout 250us for a cycle start to appear while sbiGetElapsedCycleTime ulNow 0x00002000 KE UC1394A STR CTL amp UC1394A STR CTL RCYSTART break cycle start detected if UC1394A STR CTL amp UC1394A STR CTL RCYSTART 0 error handling no cycle master present The RCYSTART bit is usually set because the IEEE1394 API has cycle master capability A missing cycle start is usually an indicator for problems with bus management Receive synchronization RXSYNC This bit can be used by application softwa
63. ear this error indication write a 1 to the UN bit In general underflow errors should be avoided by triggering data transfers by the fill level related interrupts FIFO flags AE for transmit AF for receive Application software should regularly poll this bit for detecting transfer errors Datamover error flag DMERR This bit is set whenever the LLC signals an error on the datamover port The following conditions cause this bit to be set invalid datamover configuration of the LLC doesn t happen if the IEEE1394 API is used for LLC programming header error in receive direction CRC error in receive direction Application software should regularly poll this bit for detecting transfer errors 5 3 1 1 9 Streaming FIFO Fill Level Register STR_FIFO_LEVEL This register contains the number of 16 bit words that are currently present in the FIFO Application software can use this bit for test purposes This register is read only Address 0200CD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FIFO LEVEL r 0000 r 000000000000 USER S GUIDE Date 7 November 2006 Ly j UC1394a 1 DSP MASTER BSP pa aa e orsys Page 61 5 3 1 1 10 Streaming Data Registers STR DATA STR DATA L STR DATA H Description These registers are used to transfer streaming data between the DSP and the streaming FIFO in the FPGA Application software can use either software controlled transfers or use DMA transfers In both c
64. ebug transmit buffer This is a macro that calls the functions DecUnsignedWord2Ascii and DebugPuts defined in debug h synopsis void DebugOutUWordDec INT16U digit parameters digit number to convert and put to the debug interface return value none 4 9 14 DebugOutWordHex Converts a 16 bit number into a string hexadecimal and puts the string into the debug transmit buffer This is a macro that calls the functions HexWord2Ascii and DebugPuts defined in debug h synopsis void DebugOutWordHex INT16U digit parameters digit 16 bit number to convert and put to the debug interface return value none e USER S GUIDE Date l 7 November 2006 Le H UC1394A 1 DSP MASTER BSP GER orsys Page 32 4 10 Functions Reference This chapter gives a brief description of the module support library functions 4 10 1 SetupDSP SetupDsp performs some additional initialization which is not done by the boot loader or GEL file if explicitly specified sets up processor clock and EMIF settings disables the on chip ROM by setting the MPNMC bit sets up and initializes the interrupt vector with a dummy interrupt handler DefaultISR disables and clears all maskable interrupts disables interrupts globally during initialization an enables them again when SetupDSP returns Clock and EMIF settings shouldn t be modified with SetupDSP Instead these settings should be performed by the DSP boot loader using a suitable comm
65. eceive buffer is read until a a newline character 1n is encountered b a carriage return character r is encountered c a null character 0 is encountered d usMaxLen 1 characters are read e buffer is empty defined in debug h synopsis unsigned short DebugGets unsigned short usMaxLength char pDebugText parameters usMaxlength maximum size of the debug message with trailing O pDebugText pointer to debug message return value number of actually read characters 4 10 21 Debuglnit Initializes the debug interface defined in debug h synopsis void DebugInit void parameters none return value none 4 10 22 DebugKbhit Tests whether the debug receive buffer is empty defined in debug h synopsis BOOL DebugKbhit void parameters none n USER S GUIDE Date l 7 November 2006 2 UC1394a 1 DSP MASTER BSP ee e s orsys Page 40 return value TRUE there is at least one character in the debug receive buffer FALSE debug receive buffer is empty 4 10 23 DebugPutc Puts one character into the debug transmit buffer defined in debug h synopsis INT8U DebugPutc char c parameters C output character for debug interface return value number of characters actually written 0 or 1 4 10 24 DebugPuts Puts a message into the debug transmit buffer defined in debug h synopsis INT16U DebugPuts unsigned short usLength char pDebugText parameters
66. ecting the CPU reset and init command from the GEL gt Initialization menu Now the user application can be loaded executed and debugged using the emulator UsER s GUIDE Date 7 November 2006 CH d UC1394a 1 DSP MASTER BSP CE a aaa orsys Page 21 4 4 System Initialization This section shows a typical startup procedure for an application that uses e FPGA features e the IEEE 1394 API e buffered character I O over the UART using debug c such as the asynctst example on the distribution media The following header files are required dsp_master_bsp h Defines the FPGA registers and includes basic hardware definitions of the UC1394a 1 misc h Contains function prototypes for the main part of the module support library such as initialization and interrupt management fpga load h functions for loading the FPGA debug h Defines a simple buffered character I O interface using the UART interface Suitable for debugging output as well as general character I O sbicfg h Contains various settings that were used to compile the IEEE1394 API Required for definition of the LLC interrupt resources sbiapi h User interface of the 1394 API PacAsync h This file defines the speed codes used for IEEE1394 transactions In main the DSP is set up clock EMIF interrupts by calling SetupDSP Please note that no EMIF or clock initialization is specified because this would corrupt SDRAM contents initialize the system
67. ed together in a frame It is only used for transmit direction from MCM to IEEE1394 The header of the first packet of a frame has its SYNC bit field set to the value configured in the STR HDR1 register The remaining packets have a SYNC bit field of 00002 Writing to this register sets the number of packets per frame and resets the packet counter so that the next packet will be treated as the start of a new frame This register must be programmed with number of packets per frame 1 so for a frame of 5 packets a value of e USER S GUIDE Date l 7 November 2006 Le y UC1394a 1 DSP MASTER BSP nr orsys Page 56 4 must be programmed to STR FRMSZ By default STR FRMSZ is set to O which means a frame size of 1 packet so that the SYNC bit fields of each packet header are set according to the SYNC bit field in STR HDR1 Address 020005 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STR_FRMSZ r w 0000i6 5 3 1 1 5 Streaming port FIFO almost full level register STR_FIFO_AFL Description This register controls the almost full AF flag of the streaming port s FIFO If the FIFO contains at least AF_LEVEL bytes AF will become active This register can be used to implement a flow control mechanism Application software typically uses this register when receiving streaming data and sets it to the packet payload size This causes the AF flag to be set whenever one complete packet is received However due to the
68. ers pointer manipulation is always done modulo 64K Below is a code example that shows how to handle arrays which cross 64K boundaries wrong will stay in the lower 64K bytes static int array 100000 int i for i 0 i lt sizeof array i array i 0 correct use a cast to calculate the pointer for each access static int array 100000 unsigned long i for i unsigned long array i lt unsigned long array sizeof array i unsigned long i 0 4 7 3 Pipeline Accesses to memory may take some clock cycles until they are completed since the execution is broken down into several pipelined steps For memory accesses this is no problem However accesses to hardware registers can lead to unexpected results One example is disabling interrupts asm BSET INTM asm asm asm asm asm asm NOP Without the NOP instruction an interrupt can occur immediately after the BSET INTM instruction The execution of the NOPs ensures that all stages of the BSET INTM instruction have been performed before further code is executed The NOPs must be inserted only if the code immediately following the BSET INTM instruction must be protected against interrupts i NOP Another point is access to peripherals in a write read back fashion Since a write access takes longer to be performed than a read access the read may occur before the write resulting in outdated data When
69. et by the WDR bit Note The WDE bit can only be set but not reset Once set the WDE bit stays set for until the next hardware reset This prevents accidental disabling of the watchdog If you plan to use the watchdog it must be periodically reset as long as the system is running until power off The watchdog timer is disabled after reset so if you don t plan to use it no action is required Before enabling the watchdog it must be reset Programming example include dsp master bsp h board support package definitions include misc h module support lib functions void main void Setup DSP reset and enable watchdog UC1394A WDG CTL UC1394A WDG RESET UC1394A WDG CTL UC1394A WDG ENABLE enter main loop while 1 reset watchdog UC1394A WDG CTL UC1394A WDG RESET 5 6 3 Version Register VER This register contains information about the FPGA version It can be used by application software to check that the correct FPGA version is loaded and to check which FPGA revision is loaded Address 02004316 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FPGA revision REV This bit field contains the current FPGA revision The FPGA revision can be changed due to bug fixes or product enhancement FPGA version VER This bit field identifies the current FPGA version The version defines the functional behavior of the FPGA as well as the supported registers The following FPGA versions
70. g signals whether an interrupt is currently pending The state of the IE bit has no influence on the IF bit A pending interrupt can be cleared by writing a 1 to this bit Interrupt source ISRC This bit field controls how interrupts can be generated by this pin if the pin is configured as an input DIR 0 It is encoded as follows USER S GUIDE Date l 7 November 2006 LF y UC1394A 1 DSP MASTER BSP oe Ww orsys Page 68 ISRC 005 No interrupts will be generated by this pin default 1012 level triggered interrupt see also IPOL bit edge triggered interrupt see also IPOL bit 115 delta interrupt an interrupt will be generated by both a falling or a rising edge on this pin Interrupt polarity bit IPOL This pin determines the polarity of this pin when used as a level or edge triggered interrupt interrupts on IQ high level rising edge default low level falling edge together with the ISRC field the following interrupt sources are available ISRC IPOL 000 0 No interrupts will be generated by this pin default o interrupts will be generated as long as this pin is low 1 interrupts will be generated as long as this pin is high 10 o interrupts will be generated on each falling edge on this pin interrupts will be generated on each rising edge on this pin An interrupt will be generated by both a falling or a rising edge on this pin Programming examples include o
71. gic levels therefore an external level converter is required for usage as an RS 232 interface see chapter 6 3 for an example Incoming and outgoing characters are buffered by a 16 character FIFO The UART interface is typically used for control of external hardware or for diagnostic purposes External hardware 3 3V UC1394a 1 with DSP master BSP UART External hardware FIFO Level 2x 16 char converter RS 232 Figure 7 UART interface block diagram 5 4 1 UART Hardware Interface The UART interface uses 2 data lines and 2 handshake lines Date 7 November 2006 LOO USER S GUIDE Doc no DSP_master_BSP_UG J UC1394A 1 DSP MASTER BSP Iss Rev 2 1 orsys Page 162 UART TxD UART_RxD UART interface UART_RTS UART_CTS Figure 8 UART signals MCM connector pin UART_TxD UART_RxD UART_RTS UART_CTS Table 7 UART connector pin assignments UART_TxD Transmit data output of the UART interface For RS 232 usage this signal must be connected to a level converter An example is shown in Figure 18 This signal is high when no data is transmitted UART_RxD Receive data input of the UART interface For RS 232 usage this signal must be connected to a level converter An example is shown in Figure 18 This input must be high when idle UART_RTS Handshake output of the UART interface For RS 232 usage this signal must be connected to a level converter An example is shown in Figure 18 If R
72. h bit field is a description of its read write accessibility and its default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C D E F G H J K L N O r w Q r w 0 r w 0 r w 0 r w 0 r w 0 r w 010 r 0 r wc 0 W r w 0 rc 0 r w 0 r w 0 accessibility and default value legend r bit is readable rc this bit is cleared after a read rw bit is readable and writeable reading yields the previously written value unless otherwise specified W bit is writeable read value is undefined wc writing a 1 to this bit clears it w 0 bitis write only reading always yields 0 0 default value USER S GUIDE Date l 7 November 2006 LF y UC1394A 1 DSP MASTER BSP Wap a orsys Page 41 1 4 Trademarks TI Code Composer DSP BIOS and TMS320C5000 are registered trademarks of Texas Instruments Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries Hypterterminal is a trademark of Hilgraeve Inc All other brand or product names are trademarks or registered trademarks of their respective companies or organizations 1 5 Revision History First public release Completely revised DSP memory map description of reserved locations added Different levels of IEEE1394 API support described FpgaLoad in code examples updated to recommended usage 2 1 Module and footprint dimensions revised Up
73. have the same timing as the IOSTRB signal They are useful to connect Intel compatible peripheral devices to the board using the control signals CSn chip select IORD I O read and IOWR I O write polarity built in termination handling when not used leave open IOR W and IOSTRB These are the read write IOR W and the active low I O strobe IOSTRB output lines of the peripheral interface They indicate a dedicated I O read cycle IOR Wzhigh and IOSTRB low or a dedicated UO write cycle IOR W low and IOSTRB low of the UC1394a 1 peripheral interface These signals allow to connect Texas Instruments or Motorola compatible peripheral devices to the board using the signals CSn chip select IOR W I O read write and IOSTRB I O strobe The processor latches read data at the rising edge of IOSTRB Peripherals usually latch write data at the rising edge of IOSTRB polarity built in termination handling when not used leave open USER S GUIDE Date l 7 November 2006 CX UC1394A 1 DSP MASTER BSP Wap aa orsys Page 83 INT3 INT4 These are the two maskable interrupt input lines of the UC1394a 1 peripheral interface They can be used as interrupts or for DMA synchronization Interrupts are triggered on the falling edge of the interrupt signal The INT 4 3 signals are routed to the processor s interrupt lines INT 4 3 respectively Pull up resistors for these signals are implemented in the FPGA polarity
74. he McBSP signals are directly connected to the DSP Please refer to 5 for a detailed description polarity built in termination handling when not used bi directional programmable none leave open or pull up USB_DP USB_DN USB data lines They must be connected according to the USB standard Please refer to 5 for a detailed description USER S GUIDE Date l 7 November 2006 CX UC1394A 1 DSP MASTER BSP Cee ee orsys Page 85 polarity built in termination handling when not used bi directional 1K5 pull up on DP leave open I2C SDA IC data line This line is a bi directional signal with open drain output and a 4 7kQ pull up resistor Please refer to 5 for a detailed description polarity built in termination handling when not used bi directional active high 4 7 KQ pull up leave open I2C SCL I C clock line This line is an open drain output with a 4 7kQ pull up resistor Please refer to 5 for a detailed description polarity built in termination handling when not used active high 4 7 kQ pull up leave open AINO AIN3 ADC inputs of the UC1394a 1 MCM DSP These pins are directly connected to the DSP polarity built in termination handling when not used leave open JTAG DSP EMU JTAG DSP EMUO JTAG DSP TRST JTAG DSP TCK JTAG DSP TDO JTAG DSP TDI JTAG DSP TMS These pins are used for debugging and software download and can be used with a JTAG emulator The JTAG DSP EMUO
75. hether or not data transfers use the RTS CTS handshake lines If enabled RTS CTS handshake is controlled by the UART hardware No further software intervention is required Programming example include dsp master bsp h board support package definitions initialize UART to use RTS CTS handshake and 115200 baud UC1394A UART CTL UC1394A UART CTL HS RTS CTS UC1394A UART CTL BAUD 115200 Handshake IO none default RTS CTS handshake Receiver overflow OV This bit is set whenever a character from the RS 232 interface is received while the receive FIFO of the UART is full Writing a 1 to this bit clears it Programming example include dsp master bsp h board support package definitions check for receiver overflow if UC1394A UART CTL amp UC1394A UART CTL OV increment error counter UartErrors clear the error flag UC1394A UART CTL UC1394A UART CTL UC1394A UART CTL OV USER S GUIDE Date 7 November 2006 LI UC1394a 1 DSP MASTER BSP ee orsys Page 05 ON JMeaning O IO normal operation receiver overflow at least one character got lost 5 5 I O Pins Please note With exception of the XF pin all I O pins of the MCM are implemented in the FPGA whereas the on chip GPIO pins of the DSP are not available on the UC1394a 1 The available I O pins are divided into three groups e bi directional FPGA I O these I O pins can
76. iate level as shown in chapter 6 3 polarity built in termination handling when not used active high leave open UART RxD Receive data input of the UART interface For RS 232 usage this signal must be driven by a level converter as shown in chapter 6 3 UART RxD has a pull up implemented in the FPGA polarity built in termination handling when not used pull up FPGA leave open UART_RTS Handshake output of the UART interface For RS 232 usage this signal must be converted to the appropriate level as shown in chapter 6 3 polarity built in termination handling when not used leave open USER S GUIDE Date l 7 November 2006 CX UC1394A 1 DSP MASTER BSP GER Orsys Page 84 UART_CTS Handshake input of the UART interface For RS 232 usage this signal must be driven by a level converter as shown in chapter 6 3 UART_RTS has a pull up implemented in the FPGA polarity built in termination handling when not used pull up FPGA leave open McBSPO DR McBSP1 DR McBSP2 DR Data receive input of the respective McBSP interface This pin can also be used as a general purpose input The McBSP signals are directly connected to the DSP Please refer to 5 for a detailed description built in termination handling when not used programmable none leave open or pull up McBSPO DX McBSP1 DX McBSP2 DX Data transmit output of the respective McBSP interface This pin can also be used as a general
77. icant part comes first and is located at lower addresses The combination of software and FPGA code that is installed on the UC1394a 1 This software will be booted from flash memory at power up or system reset field programmable gate array IIC inter IC communication A two wire interface between integrated circuits such as EEPROM s temperature sensors etc Standard for a high speed serial bus Also known as Fire Wire or i Link which are the trademarks of Apple inc and SONY respectively light emitting diode link layer controller for IEEE1394 least significant bit or byte least significant word multi chip module most significant byte most significant word multi channel buffered serial port TMS320VC5509 DSP of the UC1394a 1 not available an output that drives only the logic 0 state to GND an output that drives only the logic 0 state to GND physical layer transceiver for IEEE1394 an output that drives both states logic 0 to VCC and logic 1 to GND A data word consisting of 32 bits of data This terminology appears in the IEEE1394 standards an entry in the configuration ROM that contains general information about the device reserved real time clock to be changed This is subject to change so do not rely on it to be defined The value for this is not yet defined universal serial bus an interface for peripheral devices A peripheral interface of the USER S GUIDE Date 7 November 2006 CH d
78. ing e FPGA registers e the IEEE1394 chipset over IEEE1394 API calls sbilsoListen sbilsoTalk e DSP interrupts if required e the DMA controller of the DSP if required Then streaming data is transferred in the configured direction by accessing the STR_DATA register Transfers are triggered by the FIFO fill level which affects the FIFO flags in the STR_INTF register Application software can poll these bits or use interrupt driven transfers Interrupts can be enabled in the STR_INTM register The FIFO fill level controls the AE and AF flags of the STR_INTF register according to the trigger levels programmed to STR_AEL and STR_AFL Please note that setting up streaming must be done in a different order depending on the desired transfer direction This avoids bus contention between the FPGA and the IEEE1394 chipset The correct sequence is listed in the description of the DIR bit in the STR_CTL register below A safe default is to set up the FPGA to receive from the 1394 chipset and to set up the 1394 chipset for transmit This ensures that neither side is driving data Programming examples for software streaming are described in the respective kit documentation such as 15 5 3 1 1 1 Streaming Control Register STR_CTL Description This register controls the basic operation of the streaming port Address 0200C076 Encoding 15 14 13 12 11 10 9 38 7 6 5 4 3 2 1 0 RESERVED RXSYNC RSV RCYSTART LOCK EN RST DI
79. ive This can be done by checking the FIFO empty condition before a direction switch or by resetting the streaming port In receive direction the LLC receive operation must be disabled before a direction switch see 1 Streaming reset RST This bit is only writeable A read always returns 0 When a 1 is written to this bit the streaming port will be immediately reset Resetting the streaming port aborts all current transfers clears the internal FIFO of the streaming port Streaming enable EN This bit can be used to control streaming operation It must be set to enable streaming operation Setting this bit to 0 stops streaming operation Transmit operation between FPGA and the IEEE1394 chipset is stopped at packet boundaries whereas receive operation between the IEEE1394 chipset and the FPGA is stopped immediately streaming operation IQ 7 disabled default Clock generator lock status LOCK This bit is read only It indicates that the FPGA internal clock used for streaming is stable LOCK 1 This bit is mainly intended for diagnostic purpose and can be ignored However if application software accesses the streaming registers within 1us after loading the FPGA the LOCK bit should be polled as follows include dsp master bsp h board support package definitions FpgaLoad wait until FPGA internal clock is stable while UC1394A STR CTL amp UC1394A STR CTL DLL LOCK 0 set up str
80. k node ID s are automatically assigned for the connected devices This is done by the chipset without any software intervention Independent of the node ID most devices provide some more information about themselves There is an area within the IEEE1394 address space that is called configuration ROM The configuration ROM holds information about e the manufacturer of the device e device serial number e software interface of the device The serial number together with the manufacturer form a world wide unique 64 bit ID Using this 64 bit ID the device can be identified independently of the network topology or the currently assigned node ID The next higher level of identification is the protocol level By default the UC1394a 1 when equipped with the DSP Master BSP identifies itself as a device running a generic protocol specified by Orsys This protocol can be used on a host PC to load appropriate device drivers customized protocol identification is available at Orsys on request 5 2 3 Power Distribution Over IEEE1394 The IEEE1394 standard defines a 6 wire cable that allows to supply devices over the cable This is often used for digital cameras for example To operate the UC1394a 1 powered from the IEEE1394 cable an external voltage regulator is required The IEEE1394 standard allows up to 10W power consumption for a device 5 2 4 Isolation The IEEE1394 interface of the UC1394a 1 is directly connected to the remaining circuit There is
81. led low e when the firmware of the UC1394a 1 performs a software reset FPGA register e when the watchdog timer of the UC1394a 1 triggers a reset This output will stay low for 140ms 300ms after the reset condition is removed After that time the output is pulled high built in termination handling when not used leave open CFGO0 CFG4 These pins can be used as general purpose inputs The current state of CFG 4 0 can be read from a FPGA register see chapter 5 5 2 2 polarity built in termination handling when not used active high pull up FPGA leave open TPAO TPAO TPB0 TPBO IEEE1394 signals of port 0 They must be connected as defined in 9 or 10 See also chapter 6 for connection examples polarity built in termination handling when not used bi directional 1100 differential leave open USER S GUIDE Date 7 November 2006 c UC1394a 1 DSP MASTER BSP wu d E e Orsys Page 82 TPA1 TPA1 TPB1 TPB1 IEEE1394 signals of port 1 They must be connected as defined in 9 or 10 See also chapter 6 for connection examples polarity built in termination handling when not used bi directional 1100 differential leave open DATAO DATA15 These are the bi directional data lines of the peripheral interface DATAO DATA15 are only driven during write cycles to the peripheral interface When DATA 15 0 are not driven bus hold circuits keep these signal at the previou
82. lightly higher level of access is provided by TI s chip support library which is part of Code Composer Studio 2 11 PC interface The DSP of the UC1394a 1 has an on chip 12C interface It supports the I2C bus specification V2 1 The I2C interface can be programmed on register access level which is described in 5 A slightly higher level of access is provided by TI s chip support library which is part of Code Composer Studio 2 12 ADC The DSP of the UC1394a 1 provides 4 ADC channels that support 10 bit sampling at up to 21 5 kHz The ADC converter can be programmed on register access level which is described in 5 A slightly higher level of access is provided by Tl s chip support library which is part of Code Composer Studio 2 13 RTC The DSP of the UC1394a 1 has an on chip RTC However the RTC is not supported by the default configuration of the MCM because the respective MCM pins are used as I O pins If the RTC is required please contact Orsys for information on RTC usage 2 14 LED The red LED of the UC1394a 1 MCM is available for user control and can be used for optical status display or diagnostics How to control the LED is described in chapter 5 6 1 USER S GUIDE Date 7 November 2006 c UC1394a 1 DSP MASTER BSP vu kr a EM E orsys Page 16 2 15 System Reset Several sources can cause a hardware reset on the UC1394a 1 A hardware reset puts the system into a well defined state from where it can
83. long with some quick start examples IEEE1394 embedded API User s Guide 14 emb 1394 apr UG paf Describes the application programmer interface API for the IEEE1394 subsystem 1 3 Notational Conventions Names of registers bit fields and single bits are written in capital letters Example LLC VERSION Names of signals are also given in capital letters active low signals are marked with a at the beginning of the name Example RESETIN Configuration parameters function names path names and file names are written in italic typeface Example dev id Source code examples are given in a small fixed width typeface Example int a 10 Menus and commands from menus and submenus are enclosed in double quotes Example Create a new project using the Create Project command from the File menu The members of a bit field or a group of signals are numbered starting at zero which is the least significant bit Example CFG 4 0 identifies a group of five signals where CFGO is the least significant bit and CFG4 is the most significant bit If necessary numbers are represented with a suffix that specifies their base Example 12ABjg is a hexadecimal number base 16 hexadecimal and is equal to 4779 USER S GUIDE Date 7 November 2006 Doc no DSP BSP fy UC1394a 1 DSP MASTER BSP mao E orsys Page 10 The bit fields of a register are displayed with the most significant bit to the left Below eac
84. ly not changed by the user During software development this library is simply added to the project However the source code is provided for reference and for cases where a customization is necessary A CCS project for creating the USER S GUIDE Date 7 November 2006 LF UC1394A 1 DSP MASTER BSP naay ae A s orsys Page 20 module support library is also provided Please note after compiling the library sources the compiled libraries reside in the respective output directories Debug and or Release For using them with the example projects they must be copied to the ib Release and ib Debug directories The module support library contains the following modules initialization and module support functions FPGA loader flash programming routines debug c simple buffered I O over the UART interface binary to hexadecimal ASCII conversion binary to decimal ASCII conversion Below is a brief description of each module The functions of module are explained in chapter 4 10 4 2 1 1 misc c This module defines initialization and utility functions for the MCM such as interrupt control 4 2 1 2 fpga load c This module contains a loader for FPGA code The FPGA must be loaded using this loader at system startup FPGA resources are only available after loading 4 2 1 3 flash29lv400 c Contains flash programming routines It is recommended that application software does not modify the flash memory Instead the provided
85. methods for accessing the flash memory should be used FlashBurnDSK utility for application code programming see chapter 4 3 or FPGA flasher executable for updating programming FPGA code 4 2 1 4 debug c This module contains a simple system for buffered character I O over the UART interface Typically the functions of this module are not used directly but over associated macros see chapter 4 9 debug c can be used as an alternative for the stdio functions e g printf especially when small code size is required or no emulator is available 4 2 1 5 hexutil c Utility functions that convert binary values to hexadecimal ASCII 4 2 1 6 decutil c Utility functions that convert binary values to decimal ASCII 4 3 Startup Procedure After power up or a system reset the DSP starts its internal boot loader The boot loader initializes the MCM according to the information of the boot header Then it loads the application from flash memory into internal RAM or SDRAM and starts program execution at the specified address This is the default startup procedure in end system environment During development the startup procedure looks a little bit different After power up or a system reset the DSP starts its internal boot loader The boot loader tries to load an application from flash which may succeed or leave the DSP in an unknown state The user starts Code Composer Studio loads UC1394a 1 GEL and puts the DSP to an initialized state by sel
86. ng an emulator To store the user application permanently in flash memory the out file must be converted to a boot data stream by the hex conversion tool To program this boot data stream the FlashBurnDSK utility must be started The FlashBurnDSK utility e loads the Target Component executable FBTCOrsysUC1394a 1 0ut to the UC1394a 1 and starts it e sends the boot data stream to FBTCOrsysUC 1394a 1 which in turn programs it to the flash memory Further details on flash programming can be found in chapter 4 3 This development flow is shown in the picture below The distribution media contains some project examples which perform this development flow ER IDE Date 7 November 2006 fy USER S GU Doc no DSP master BSP UG A UC1394a 1 DSP MASTER BSP pi orsys Page ife Development flow for testing and debugging C source code C compiler IEEE1394 Module Object API support library modules Linker UC1394a 1 COFF executable out Target download via emulator Hex55 utility Boot data stream hex Additional steps for flash programming select TOOLS gt FlashBurn from CCS Menu FlashBurn utility Figure 2 Software development flow 4 2 14 Module Support Library Internal RAM External RAM ocOooauomn FPGA The module support library is a collection of functions that are commonly used when programming the UC1394a 1 MCM The code in this library is usual
87. no galvanic isolation between the IEEE1394 cable and the local power supply In a custom hardware design the VG pin of the 1394 connector must be connected to the GND pins of the UC1394a 1 5 3 Software Streaming Software streaming allows to transfer large amount of data between the DSP and IEEE1394 with minimal overhead Data transfers are buffered by a FIFO so that the DSP can operate independent of the IEEE1394 timing Streaming transfers are unidirectional and must be set up with the IEEE1394 API as well as the streaming registers in the FPGA The maximum transfer rate for streaming is 32 768 000 byte s Software streaming uses isochronous streaming Isochronous streaming is explained in chapter 5 2 1 The DSP Master BSP allows to e transmit synchronization information in the data stream see description of the STR_FRMSZ register USER S GUIDE Date f 7 November 2006 Le UC1394a 1 DSP MASTER BSP er Orsys Page 52 e synchronize receive operation to the incoming data stream See description of the RXSYNC bit in the STR CTL register IEEE1394a po dj 2048x16 400Mbps IEEE 1394 magpost Poto LITO FIFO 400Mbps IEEE1394 ic Port1 Paanu mula anos Foster a ZE D gt gt z 8 8 otc E 8 8 EE set Figure 6 Software streaming block diagram 5 3 1 1 Streaming Programming Programming the streaming port is usually a straightforward process First streaming is set up by programm
88. o chapter 7 6 for further details such as voltage limits and current consumption e USER S GUIDE Date l 7 November 2006 LJ H UC1394A 1 DSP MASTER BSP Wap aa orsys Page 17 3 Quick Start Usually the UC1394a 1 DSP Master BSP is shipped as part of a development kit which includes documentation and quick start examples tailored for the kit In contrast this chapter describes the first steps when using the UC1394a 1 in a stand alone environment If you purchased UC1394a 1 DSP Master BSP as part of a kit such as the DSP Development Kit then please refer to the kit s documentation e Required items o UC1394a 1 integrated into your hardware environment as described in chapter 6 o aJTAG emulator o a suitable power supply o adevelopment PC with Code Composer Studio installed o Optional a terminal program such as Hyperterminal and a RS 232 cable connect the JTAG emulator and the RS 2332 cable optional to the system power on the system start Code Composer Studio select the Load GEL command from the File menu locate uc1394a 1 master gel from the GEL folder on the distribution media and open it select the Initialization gt CPU reset and init 144MHz command from the GEL menu select the Load Program command from the File menu locate one of the application examples from the examples folder on the distribution media and open it e g toggle led out e select the Run command from the Debug menu
89. one return value none 4 10 8 LedToggle Toggles the red LED of the MCM switches off if on and vice versa defined in misc h synopsis void LedOff void parameters none return value none 4 10 9 Timerlnit Initializes on of the DSP on chip timers for use as a single shot or periodic timer single shot or continuous operation as well as a software prescaler can be implemented by application software by using the parameters bAutoReload and ullnterval in conjunction with the global timer variables see chapter 4 8 defined in Date 7 November 2006 USER s GUIDE Doc no DSP master BSP UG MS UC1394A 1 DSP MASTER BSP Iss Rev 2 1 e Orsys Page 35 misc h synopsis VOID TimerInit INT16U usTimerNo BOOL bAutoReload INT32U ulInterval parameters usTimerNo Specifies which timer to initialize Allowed values O or 1 bAutoReload Flag for application specific the interrupt handlers Gets stored in bSWAutoReload0 or bSWAutoReload1 ullnterval 32 bit Timer period The 16 LSBs go to the timer period register The next 4 return value none bits initialize the timer prescaler The remaining bits are stored in ulSWPreload0 7 ulSWPreload1 ana ulSWPrescalerO 7 ulSWPrescaler1 for use by an application specific software prescaler 4 10 10 TimerStart Starts timer operation defined in misc h synopsis VOID TimerStart INT16U usTimerNo parameters usTimerNo return value none Specifies which timer
90. ow if UC1394A UART CTL amp UC1394A UART CTL TXDY yes send now UC1394A UART DATA rrt 5 4 2 2 UART Control and Status Register UART CTL Description This register provides two function It controls the baud rate at which the UART interface transmits and receives data and it provides status flags Address 020051 16 UsER s GUIDE Date 7 November 2006 Ly UC1394A 1 DSP MASTER BSP oe ee 8 orsys Page 64 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED OV BD1 HS BDO RXRDY TXRDY Transmit ready TXRDY This bit indicates that the transmitter part of the UART is ready to accept a new data word to transmit This bit must be read as 1 set before data is written to the UART DATA register See also the code example above UART DATA write access Receiver ready RXRDY This bit indicates that receive data is available in the UART DATA register This bit should be checked to poll for incoming data See also the code example above UART DATA read access Baud rate BD 1 0 This bit controls the baud rate of the UART Programming example include dsp master bsp h board support package definitions initialize UART to use 115200 baud and RTS CTS handshake UC1394A UART CTL UC1394A UART CTL BAUD 115200 UC1394A UART CTL HS RTS CTS o fo D 1 115200 default 1 10 38400 LJ reserved Handshake HS This bit controls w
91. programmed or contains invalid data e the FPGA Code was created for a device other than a XC2S50 e the FPGA Code was created with incorrect programming file options 4 10 13 FlashGetDevicelnfo Reads manufacturer and device ID from the flash and stores them in the specified locations Default manufacturer ID is 000115 AMD Default device ID is 22BA 6 29LV400 defined in flash29lv400 h synopsis void FlashGetDeviceInfo INT16U pManufacturer INT16U pDevice void pCallback void parameters pManufacturer pointer to location where manufacturer ID is stored pDevice pointer to location where device ID is stored return value None 4 10 14 FlashEraseSector Erases the specified sector During the erase process a user specified callback function is executed to allow the application to continue processing or to indicate the progress of the operation The callback is called whenever the erase status is queried Since the flash memory is completely used for storing application and FPGA code see chapter 4 11 3 application software should not modify the flash contents defined in flash29Iv400 h synopsis void FlashEraseSector int iSector void pCallback void parameters iSector Sector number to be erased Allowed values 0 10 pCallback Pointer to a user callback function Must be set to a valid user callback function or to NULL if no callback is used USER S GUIDE Date 7 November 2006 2
92. pt after the transfer UC1394A STR INTF UC1394A STR INTF AE e re enable the interrupt for the next transfer UC1394A STR INTM UC1394A STR INTM AE Almost full interrupt enable AF If this bit is set to 1 interrupts are generated while the almost full flag is set Application software typically uses this bit for triggering transfers in receive direction To trigger reception by the AF flag application software must e program the AF level to the transfer size in bytes UC1394a STR AFL 100 interrupt when gt 100 bytes are available e install an interrupt handler for DSP interrupt 2 C5xIntHook C5509 INT2 IsoRxIntHandler e clear and enable DSP interrupt 2 C5xIntClear C5509 INT2 C5xIntEnable C5509 INT2 e clear and enable FPGA interrupts through the AE flag UC1394A STR INTF UC1394A STR INTF AF UC1394A STR INTM UC1394A STR INTM AF e disable the interrupt after it has occurred UC1394A STR INTM 0 e transfer the data or start a data transfer using DMA e clear the interrupt after the transfer UC1394A STR INTF UC1394A STR INTF AF e re enable the interrupt for the next transfer UC1394A STR INTM UC1394A STR INTM AF Full interrupt enable F If this bit is set to 1 interrupts are generated while the full flag is set Application software can use this bit for testing e g FIFO size detect and for detecting situations where the FIFO is about to overflow However usually the full con
93. re to synchronize to the next packet that contains a matching sync bit pattern When RXSYNC is set by application software all incoming data is skipped until a packet with matching sync bits is received Sync bits match if at least one bit is set in both the SYNC bit field of incoming packet s header and the iSyncBits parameter of sbilsoTalk The RXSYNC feature is used for receive operation only and has no effect for transmit Please note that the RXSYNC feature uses a sync pattern set up by the IEEE1394 API whereas the SYNC bit field of the STR HDR1 register is not used for receive operation 5 3 1 1 2 Streaming Header Register 1 STR_HDR1 Description This register specifies one half of the header for transmitted packets In receive direction this register is ignored Do not program the header register of the IEEE1394 chipset directly The value in the header register of the LLC will be overwritten by the value in the STR HDR1 register Default values and shift constants for this register are defined in the dsp master bsp header file Programming example include dsp master bsp h board support package definitions UC1394A STR HDR1 UC1394A STR HDR1 TAG UNFORMATTED lt lt UC1394A STR HDR1 TAG SHIFT 1 lt lt UC1394A STR HDR1 CH NO SHIFT UC1394A STR HDR1 TCODE ISOCH STR UC1394A STR HDR1 TCODE SHIFT 1 lt lt UC1394A STR HDR1 SYNC SHIFT Address 0200C2 6 Encoding 15 14 13 12
94. reading back data that has just been written two NOP instructions should be inserted between write and read Below is an example taken from the flash programming routines n USER S GUIDE Date l 7 November 2006 Ly UC1394a 1 DSP MASTER BSP Ee aa s orsys Page 26 Wrong do not use that for ulWords 0 ulWords lt ulLengthInWords ulWords enter programming mode volatile INT16U UC1394A FLASH BASE 0x0555 OxAA volatile INT16U UC1394A FLASH BASE 0x02AA 0x55 volatile INT16U UC1394A FLASH BASE 0x0555 OxA0 See write data word to flash volatile INT16U ulFlashAdr volatile INT16U ulDataAdr mr wait until programmed while volatile INT16U ulFlashAdr volatile INT16U ulDataAdr asm NOP ulFlashAdr ulDataAdr if ulWords amp FLASH PRG CALLBACK RATIO 0 amp amp pCallback NULL pCallback corrected code for ulWords 0 ulWords ulLengthInWords ulWords enter programming mode volatile INT16U UC1394A FLASH BASE 0x0555 OxAA volatile INT16U UC1394A FLASH BASE 0x02AA 0x55 volatile INT16U UC1394A FLASH BASE 0x0555 OxA0 V a write data word to flash volatile INT16U ulFlashAdr volatile INT16U ulDataAdr The following NOP s causes the write operation to finish before the programming status is read Otherwise the pipeline could exchange write and read which ca
95. rface CS6 address space 02070016 0207FF1s peripheral interface CS7 address space reserved FPGA register set repeats each 100015 words Table 3 LLC and FPGA register overview 4 11 7 FPGA register map 02000416 02000515 0200 6 0200 6 s E E s E E Fie 6 02002616 02002715 02002A1 02002Big 02003016 02003116 02003616 02003715 02003C 6 02003Di5 reserved reserved USER S GUIDE Date 7 November 2006 no DSP BSP y UC1394a 1 DSP MASTER BSP er Orsys ee a 020040 020041 020042 020043 020044 020050 020051 02005215 02005Fis_ reserved 020080 PCRO 020081 PCR1 020082 PCR2 Opin2controlregiste 020083 PCR3 020084 PCR4 020085 02009F reserved 0200C0 STR_CTRL 0200C1 reserved 0200C2 STR HEADER 0200C3 STR HEADER2 Streaming header register2 0200C4 reserved 0200C5 STR FRMSZ 0200C6 STR FIFO AFL 0200C7 STR FIFO AEL 020008 STR INTM 0200C9 STR FLAG 02000315 0200CD reserved 0200CE Streaming data 32 bit STR DATA L Streaming data 16 bit LSB STR DATA H 0200FF 02010016 0201FF peripheral interface CS1 0202001 0202FF peripheral interface CS2 020300 0209F F peripheral interface CS3 02040076 0204F F peripheral interface CS4 02050016 0205F F peripheral interface CS5 02060015 0206FF peripheral interface CS6 020700 0207F F peripheral interface CS7
96. ripheral interface work with half of the CPU clock which imposes one CPU clock uncertainty The actual timing may be extended by one CPU clock 5ns at 200MHz USER S GUIDE Date 7 November 2006 2 UC1394a 1 DSP MASTER BSP er 2 Orsys Page 51 e data that occurs in regular intervals Asynchronous transfers can occur at any time provided that the bus is free They are point to point transfers so the originator of the transfer must know who to talk to An asynchronous transfer consists of a request that is sent to the destination device and a response that the destination device sends back This enables error checking at the sender Asynchronous transfers are well suited for e data that occurs randomly e g control and status information e transfers where the originator of the transfer must be informed about the status of each single transfer There is one more transfer method asynchronous streaming which is similar to isochronous transfers Asynchronous streaming uses the same transfer elements as an isochronous transfer but has no guaranteed bandwidth and the transfer may occur anytime provided that the bus is free At the receiver side it makes no difference whether isochronous or asynchronous streaming is used This kind of transfer is well suited for situations where a minimum latency is required 5 2 2 Plug amp Play features of IEEE1394 When devices are connected to or disconnected from the IEEE1394 networ
97. robe use together with IOWR write strobe use together with IORD irection select use together with IOSTRB ata strobe use together with IOR W ready input for very slow peripherals INT 4 3 interrupt inputs routed to the respective DSP interrupts Table 6 Peripheral interface signals 5 1 1 Wait State Generator Programming 5 1 1 1 Wait State Control Register WSG Address 02004415 Encoding 15 M 13 12 1 10 9 8 7 6 5 4 3 2 1 0 RESERVED WS r 000000000000 r w 0000 WS Number of wait states to insert for peripheral accesses This default setting of bit field is 0 WS is encoded as follows WS wait states minimum IOSTRB width in CPU clocks in ns at 200MHZ CPU clock o none Mi 155 5 2 IEEE1394 Interface 5 2 1 How Data is Transferred Over IEEE1394 Two kind of transfers are provided isochronous transfers and asynchronous transfers Isochronous transfers occur at intervals of 125s at a guaranteed bandwidth This transfer method is an excellent solution for transferring data Isochronous transfers are multicast transfers which are identified by a channel so there is always one talker and one or more listeners The transfer is typically done without any software overhead Error detection is done at the receiver side Isochronous transfers are well suited for e large amounts of data e data distribution to several devices 3 The IOSTRB width can vary by 1 CPU clock because the FPGA and the pe
98. rstypes h architecture independent data types include c5509 h DSP definitions include dsp master bsp h board support package definitions include misc h module support lib functions void pin_examples void set up I O Pin 0 as an input for polling UC1394A PCRO UC1394A PCR DIR IN set up I O Pin 1 as an input with interrupts on either edge UC1394A PCRO UC1394A PCR DIR IN UC1394A PCR ISRC DELTA install interrupt handler for I O pin interrupts C5xIntHook C5509 INT1 IoPinISR enable I O pin interrupts on DSP level C5xIntEnable C5509 INT1 enable interrupts for I O pin 1 UC1394A PCR1 UC1394A PCR INT ENABLE disable interrupts for I O pin 1 UC1394A PCRI amp UC1394A PCR INT ENABLE set up I O pin 2 as a push pull output Note When switching from input to output it is recommended to set the pin state first and then to change direction set state if OutputState 1 UC1394A PCR2 UC1394A PCR DAT else UC1394A PCR2 amp UC1394A PCR DAT change direction UC1394A PCR2 UC1394A PCR DIR OUT toggle output UC1394A PCR2 UC1394A PCR DAT change back to input UC1394A PCR2 amp UC1394A PCR DIR OUT interrupt void IoPinISR void int iPinIdx BOOL bInterruptPresent TRUE repeat as long as there is any interrupt Otherwise the interrupt line stays asserted low and no further interrupt
99. s Date 7 November 2006 LO USER S GUIDE Doc no DSP_master_BSP_UG iJ UC1394A 1 DSP MASTER BSP Iss Rev 2 1 orsys Page 69 can be triggered while bInterruptPresent TRUE bInterruptPresent FALSE for iPinIdx 0 iPinIdx lt 4 iPinIdx check which pin generated the interrupt if volatile INT16U amp PCRO iPinIdx amp UC1394A PCR INT FLAG clear pin s interrupt flag volatile INT16U amp PCRO iPinIdx UC1394A PCR INT FLAG take the appropriate action fe cause pins to be checked for interrupts again bInterruptPresent FALSE 5 5 2 2 Configuration Register CFG This register contains the state of the configuration inputs CFG 4 0 The configuration inputs are used for configuring the operation mode in other UC1394a 1 based products For the DSP Master BSP these pins can simply be used as general purpose inputs Address 02004216 Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CFG r 000000000000 r Configuration CFG This bit field contains the current state of CFG 4 0 Programming example include dsp master bsp h board support package definitions int iPin poll all CFG pins for iPin 0 iPin lt 4 iPin if UC1394A CFG amp 1 iPin pin is high else pin is low 5 6 Other Interfaces Provided by FPGA Registers 5 6 1 System Control
100. s described above for the E bit Application software can poll this bit for triggering transfers in transmit direction see description of the AE bit in the STR INTM register When DSP interrupts are used the AE flag should be cleared after a transfer triggered by the AE flag has finished This ensures that a new interrupt is generated either immediately or if the FIFO is no longer almost empty when it is almost empty again Almost full flag AF This bit will be set whenever the streaming port s FIFO is almost full see chapter 5 3 1 1 5 for details It can be cleared by writing a 1 to it If the FIFO remains almost full the almost full flag will be set again after it was cleared To get the most recent state of the FIFO this bit should be cleared before it is checked as described above for the E bit Application software can poll this bit for triggering transfers in receive direction see description of the AF bit in the STR INTM register When DSP interrupts are used the AF flag should be cleared after a transfer triggered by the AF flag has finished This ensures that a new interrupt is generated either immediately or if the FIFO is no longer almost full when it is almost full again USER S GUIDE Date 7 November 2006 LF UC1394A 1 DSP MASTER BSP Cee ee ep orsys Page 60 Full flag F This bit will be set whenever the streaming port s FIFO is full It can be cleared by writing a 1 to it If the F
101. s logic level and keep them from floating polarity built in termination handling when not used bi directional active high bus holder FPGA leave open ADDRO ADDR7 These are the address bus output lines of the UC1394a 1 peripheral interface They are driven during read and write cycles of the peripheral interface While the peripheral interface is idle bus hold circuits keep these signal at the previous logic level and keep them from floating polarity built in termination handling when not used tri state active high bus holder FPGA leave open output CS1 CS7 These are the seven active low chip select output lines of the UC1394a 1 peripheral interface They pre select which external peripheral component has to be accessed during a UC1394a 1 peripheral access CS 7 1 are always driven During a peripheral access one of CS 7 1 is active low while the other chip select lines stay high polarity built in termination handling when not used leave open IORD and IOWR These are the active low read strobe IORD and I O write strobe IOWR output lines of the UC1394a 1 peripheral interface They indicate a dedicated I O read cycle IORD or a dedicated I O write cycle IOWR of the UC1394a 1 peripheral interface In case of a read cycle data is latched at the rising edge of IORD Write data is valid prior the rising edge of IOWR IORD and IOWR are generated from the signals IOR W and IOSTRB and
102. ses as shown in the example above Further the GRF register must be accessed by 32 bit accesses only For a detailed description of LLC registers please refer to the LLC s data manual 13 Address 02000016 02003F 5 Please note the LLC registers are already defined in c h which is automatically included when you include the BSP header dsp_master_bsp h include dsp master bsp h board support package definitions printf LLC version register 8 81X n LLC version 4 13 Interrupts The TMS320VC5509 has five interrupt lines INTO INT4 They are used as described below Interrupt line INTO LLC interrupts INT1 I O pin interrupts INT2 Software streaming interrupts INT3 External interrupt INT4 External interrupt Table 5 Interrupt usage 4 13 1 LLC interrupts INTO is used by the LLC LLC interrupts must be enabled during the IEEE1394 API initialization as shown in chapter 4 3 The LLC interrupts are then handled by API software 4 13 2 FPGA UO pin interrupts All FPGA UO pins share the same interrupt In order to identify the interrupt source the I O pin control registers must be checked In order to generate a new interrupt all pending interrupt sources must be serviced Programming details about I O pin handling can be found in chapter 5 5 2 4 13 3 Streaming interrupts Streaming interrupts are controlled by the STR INTM and STR FLAG registers Please refer to chapter 5 3 1 1 7 and 5 3 1 1
103. settings as set up by the module support library IOADDR 7 0 IORW IOCSx IORE IOSTRB IODATA 7 0 Figure 22 Peripheral interface read timing USER S GUIDE Date 7 November 2006 Doc no DSP BSP CX UC1394a 1 DSP MASTER BSP EL EE orsys Page 91 IOADDR 7 0 IORW IOCSx IOWE IOSTRB IODATA 7 0 Figure 23 Peripheral interface write timing 7 8 1 Timings for a 200MHz TMS320VC5509A Measurement conditions e FPGA V7 02 e UC1394a 1 set up by GEL file or the DSP boot loader and module support library function SetupDsp e Wait state generator at default setting 0 wait states strobe signals active Figure 24 Peripheral interface read timing 200MHz parameter name description strobe signals low after control signals valid strobe signals active data valid after strobe low NEN data valid after strobe high Figure 25 Peripheral interface write timing 200MHz To relax these timings for slower peripheral components the peripheral accesses can be extended up to 205 ns strobe time by using the wait state generator see chapter 5 1 1 Each wait state adds 2 CPU clocks 5 ns at 200 MHz to timing parameter tp1 7 8 2 Timings for a 144MHz TMS320VC5509 Measurement conditions e FPGA V3 09 e UC1394a 1 set up by GEL file or the DSP boot loader and module support library function SetupDsp USER S GUIDE Date l 7 November 2006 c UC13944 1 DSP MASTER BSP Pe orsys Page 92
104. ssStartLow 0x00000000 sRangeInfo iNotificationOptions NOTIFY AFTER READ NOTIFY AFTER WRITE sRangeInfo pNotificationCallback appNotificationCallback iError sbiAllocateAddressRange amp sRangeInfo if iError SBI NO ERROR DebugOutConstString sbiAllocateAddressRange failed vs DebugOutWordHex iError DebugOutConstString r n DebugFlush return After some application specific setup the main loop is entered which ever is remote select default destination node node 0 or 1 sSetup hRemoteNode sbiGetDeviceHandle sInitInfo uiThisNodesID 1 0 DebugOutConstString press for help page lt space gt to start a transaction r n DebugFlush bBusReset FALSE main loop while 1 4 5 Main Loop The main loop performs the following tasks e Serving the callback queue of the IEEE1394 API All IEEE1394 transaction layer activity is handled by callback functions which are processed sequentially by calling YieldToCallQ e handling user commands which come in over the UART interface e EEE1394 bus reset handling main loop while 1 char acCmd 2 process API callbacks YieldToCallQ acCmd 0 0 DebugInString 1 acCmd if acCmd 0 No switch acCmd 0 MC if bBusReset TRUE ListNodes bBusReset FALSE e USER S GUIDE Date l 7 November 2006 Le H UC1394A 1 DSP MASTER BSP a ee orsys Page 24
105. start Sources for a hardware reset can be supply voltage out of bounds This reset happens at each power on Software triggered reset Application software triggered a hardware reset over the FPGA Watchdog reset external hardware reset An external device pulled the RESETIN signal low This is what is done by a reset pushbutton When one of these events occurs the MCM is reset and the RESETOUT output indicates the reset condition Reset timing is described in chapter 7 8 2 A detailed description of a software reset can be found in chapter 5 6 1 A detailed description of the watchdog can be found in chapter 5 6 2 2 16 DSP JTAG Interface The DSP JTAG interface is used during development for downloading application code and debugging During system manufacturing the JTAG interface can be used to install the final application code for DSP and FPGA by programming it into the flash memory See also chapters 4 2 and 4 3 for further information How to connect the DSP JTAG interface to a TI emulator POD is described in chapter 6 4 2 17 FPGA JTAG Interface The FPGA JTAG interface is usually not used since the FPGA code is downloaded by the DSP It can be used optionally during FPGA development for temporary download of FPGA code However the loaded FPGA code is lost as soon as power is removed or the DSP is loading the FPGA 2 18 Power Supply The UC1394a 1 requires a single regulated supply voltage of nominal 3 3V Please refer t
106. t have a ground plane with short connections to the MCM s ground pins Decoupling capacitors of 100nF are recommended at each of the supply pins Additional decoupling capacitors can be placed between the VCC and ground planes near the GND pins of the MCM If the carrier PCB uses a voltage regulator to generate the 3 3 V follow the instructions of the regulator s manufacturer for the type and value of the regulator s output capacitor s If the carrier PCB is directly supplied with 3 3 V from a cable a 10 100uF capacitor in parallel with a 100nF capacitor is recommended at the point where the cable is connected 6 2 IEEE1394 Interface For connection to the IEEE 1394 network the 4 pin and 6 pin connectors defined in the standards 9 10 should be used The PCB traces to the connector TPA and TPB signal pairs e must be kept as short as possible must be routed as a differential pair e must have a differential impedance of 110 60 Table 10 shows part number examples for both connector types Please note that the cable shield usage differs between the 4 pin and the 6 pin connector See Figure 14 or Figure 15 and Figure 18 for connection details of the 6 pin and 4 pin connectors pin connector 6 pin connector TPA 4 signal ground connector shield cable power chassis ground connector shield Table 9 Pinning of the IEEE 1394 connectors oO Connector type Molex part No 6 pin IEEE1394 1995 53462 xx
107. terface shares its EMIF settings with the FPGA registers However the bus cycles can be extended by the MCM s FPGA A programmable wait state generator allows to adapt the peripheral interface to the speed of the connected components Very slow peripherals can further extend the bus cycle by de asserting the IORDY signal Two interrupt inputs INT 4 3 allow interrupt driven data transfers The peripheral address space is mapped into the DSP address space and can be accessed with simple C statements include dsp master bsp h board support package definitions initialization set up for 5 wait states UC1394A WSG 5 write to address 1 in chip select space 1 INT16U UC1394A CS1 BASE 1 O Timing diagrams of the peripheral interface are shown in chapter 7 8 A detailed description of the peripheral interface s signals can be found in chapter 7 2 Peripheral interface ODATA 15 0 IOADDR 7 0 IOCS NORD OWR IORW IOSTRB IORDY INT 4 3 Figure 5 Peripheral interface signals The wait state generator is only available in 200MHz versions of the UC1394a 1 used in current production 144MHz Versions did not have this feature and need to modify the EMIF timings if necessary USER S GUIDE Date 7 November 2006 CR UC1394a 1 DSP MASTER BSP er Orsys Page 50 IODATA 15 0 bi directional IOADDR 7 0 address bus output IOCS 7 0 chip select lines output read st
108. ternal components or as an interface for service or debugging A detailed description of the UART interface can be found in chapter 5 4 2 8 I O Pins The I O pins provide bit level digital I O for controlling or sensing single digital signals The DSP Master BSP supports e 5 dedicated inputs e 51 0 pins configurable as input with interrupt capability output or open drain output e 1 dedicated output pin A detailed description of these I O pins can be found in chapter 5 4 1 Further some of the DSP on chip interfaces such as the McBSP interfaces can be also be configured as general purpose I O Details about these interfaces can be found in 5 2 9 McBSP Interfaces The DSP of the UC1394a 1 provides 3 McBSP ports These interfaces are high speed serial interfaces They support multiple channels and a lot of different operation modes such as SPI or AC97 Using this interface a wide range of peripherals such as codecs ADCs DACs or other DSP s can be directly connected to the UC1394a 1 The McBSP interfaces can be programmed on register access level which is described in 5 A slightly higher level of access is provided by TI s chip support library which is part of Code Composer Studio 2 10 USB interface The DSP of the UC1394a 1 has an on chip USB interface The USB interface is implemented as a slave port and supports 12Mbps transfer rates The USB interface can be programmed on register access level which is described in 5 A s
109. the power supply for the UC1394a 1 All necessary internal voltages are generated from this voltage Please refer to chapter 0 for voltage limits and recommended operating conditions The power supply lines must be properly stabilized by decoupling capacitors as described in chapter 6 1 polarity built in termination handling when not used n a power l GND These pins are the power supply and signal ground pins of the UC1394a 1 They should be directly connected to the ground plane of the carrier PCB polarity built in termination handling when not used n a power RESET_IN Reset input and software reset output If this pin is set to logic low level the UC1394a 1 is reset This pin should only be driven by an open drain output or a pushbutton connected to ground When software or the watchdog timer of the UC1394a 1 trigger a reset RESET_IN is pulled low for at least 1us The minimum input pulse width for externally applied resets is also 1 us A power on reset circuit is provided on the UC1394a 1 so that RESET_IN can be left open if not used polarity built in termination handling when not used bi directional 4 7 kQ pull up leave open RESET_OUT This is the active low reset output line of the UC1394a 1 It allows external hardware devices to be reset and exactly be started together with the UC1394a 1 This output is pulled low whenever a system reset is active thus e after power on e when RESET IN is externally pul
110. timings interrupts is done within the module support library which is described in chapter 4 2 1 Key features of the DSP are e 6 94 or 5 ns instruction cycle time with one or two instructions per cycle e 128Kx16 on chip memory e on chip peripherals such as 2 timers 6 DMA channels 3 serial ports IFC interface USB interface 2 4 FPGA The UC1394a 1 uses a 50k gate Spartan 2 FPGA With the DSP Master BSP the function of the FPGA is pre defined to those features described in this document Customized FPGA designs are possible but require an additional development license For details on FPGA development please contact Orsys Optionally the UC1394a 1 can be equipped with a 200k gate FPGA Please contact Orsys for further details on availability Depending on the DSP type the DSP master BSP uses different FPGA code How to check that the correct FPGA type is installed is described in chapter 5 6 3 The FPGA code is located in flash memory It is programmed to flash memory using a dedicated programmer executable which is included in the distribution The FPGA is loaded on system startup as shown in chapter 4 3 2 5 Peripheral Interface The peripheral interface provides a straightforward connection to up to seven peripheral components such as memories FIFOs or I O controllers without glue logic A detailed description of the Peripheral interface can be found in chapter 5 1 2 6 IEEE1394 Interface The UC1394a 1 MCM has two 400Mbps IEE
111. to start Allowed values 0 or 1 4 10 11 TimerStop Stops timer operation defined in misc h synopsis VOID TimerStop INT16U usTimerNo parameters usTimerNo return value none Specifies which timer to stop Allowed values 0 or 1 4 10 12 FpgaLoad Loads code to the FPGA usually from flash memory Default address when loading the FPGA code from flash is uc1394n FLASH FPGA coDE BAsE The code length can be retrieved from the code s header by specifying uci394a FLASH FPGA cobE LENGTH When the FPGA code is linked to the application the parameters must be modified accordingly Please note The FPGA code is usually preceded by a header FpgaLoad supports both code with and without header Care must be taken to specify the correct length for each variant For a 50k gates FPGA the code length is USER S GUIDE Date 7 November 2006 2 UC1394a 1 DSP MASTER BSP wg ban a orsys Page 36 69900 bytes without header and 69928 bytes with header uc1394a FLASH FPGA CODE LENGTH always evaluates to the length without header defined in fpga load h synopsis int FpgaLoad INT32U pBootData INT32U ulLength parameters pBootData pointer to FPGA image typically in flash memory ulLength length of FPGA image in bytes return value FPGA success zero if FPGA image is loaded successfully otherwise the FPGA has not been loaded Possible reasons for this are e the flash area for FPGA code is not
112. tor Parameter Value Compatible I O standards 3 3V LVTTL 2 5V CMOS Table 26 RESET_OUT signal levels 7 7 3 DSP Signals A group of digital lines are directly connected to the DSP Please refer to 5 for a detailed description These signals are Interface McBSP all Signals input output XFOUT PC I2C_SDA lac SCL USER S GUIDE Date 7 November 2006 UC13944 1 DSP MASTER BSP EE Ss Orsys Page 90 Q Parameter Value Compatible I O standards 3 3V LVTTL 2 5V CMOS High input level see 1 2 Table 27 Signal level and loads for the DSP signals 7 7 4 Analog Inputs These signals are directly connected to the DSP Please refer to 5 for a detailed description AIN S 0 input Parameter Value minimum input voltage maximum input voltage Table 28 Allowed input voltage range for the ADC inputs 7 7 5 Other Signals The remaining signals are intended to be used with the appropriate interfaces only For example the FPGA JTAG signals should only be used with programming equipment from XILINX so that correct signal levels and loads are guaranteed The interfaces for use with dedicated equipment are e EEE1394 signals e USB e JTAG signals for the DSP e JTAG signals for the FPGA 7 8 Peripheral Interface Timing The peripheral interface timing is based on the TMS320VC5509 EMIF timing The timing diagrams and tables below show the timing parameters for the default EMIF
113. uses a premature abort asm NOP asm NOP Se Ee wait until programmed while volatile INT16U ulFlashAdr volatile INT16U ulDataAdr asm NOP ulFlashAdr ulDataAdr if ulWords amp FLASH PRG CALLBACK RATIO 0 amp amp pCallback NULL pCallback 4 8 Global Variables Reference The variables below are intended for use with application specific use of the DSP on chip timers They can be used to store application specific values for use by timer interrupt handlers They are set up by Timerlnit If not used they can safely be ignored global variables for timer operation extern INT16U usSWPreload0 extern INT16U usSWPreloadl extern INT16U usSWPrescaler0 extern INT16U usSWPrescalerl extern BOOL bSWAutoReload0 extern BOOL bSWAutoReload1 4 8 1 DSP Type After calling SetupDSP the variable shown below is set to rrur if a 200MHz TMS320VC5509A DSP is detected and set to rares if a 144MHz TMS320VC5509 is detected This variable can be used to calculate software controlled timings and to decide which FPGA code is to be used ER IDE Date 7 November 2006 fy Us Ba BSP Doc no DSP master BSP UG KI UC1394A 1 DSP MASTER BS Iss Rev 2 1 orsys Pag 27 initialized afer calling SetupDSP Tells whether a 144MHz TMS320VC5509 or a 200MHz TMS320VC5509A is present extern BOOL bIs5509A interrupt vector table extern struct void handler voi
114. void pHandler void parameters int ilntNumber number of interrupt to be inserted pHandler pointer to the interrupt handler return value none 4 10 3 C5xIntEnable Enables the specified interrupt in the corresponding Interrupt Enable Register The interrupt numbers are defined in c5509 h defined in misc h synopsis void C5xIntEnable int ilntNumber parameters int ilntNumber number of interrupt to be enabled return value none 4 10 4 C5xIntDisable Disables the specified interrupt in the corresponding Interrupt Enable Register The interrupt numbers are defined in c5509 h defined in misc h synopsis void C5xIntDisable int ilntNumber parameters int ilntNumber number of interrupt to be disabled return value none 4 10 5 C5xIntClear Clears the specified interrupt in the corresponding Interrupt Flag Register if pending The interrupt numbers are defined in c5509 h defined in misc h synopsis void C5xIntClear int iIntNumber parameters ilntNumber number of interrupt to be cleared see c5509 h e USER S GUIDE Date l 7 November 2006 Le H UC1394A 1 DSP MASTER BSP GER orsys Page 34 return value none 4 10 6 LedOn Switches on the red LED of the MCM defined in misc h synopsis void LedOn void parameters none return value none 4 10 7 LedOff Switches off the red LED of the MCM defined in misc h synopsis void LedOff void parameters n
115. w of a string in character Tomat 25 Figure 4 Memory view of a string in binary format 1 11111 1 cece ee eeeeeeeeeeeeeeeeeeeeeeeeeeneees 25 Figure 5 Peripheral interface SIgials aaa oa unis AA AA 49 Figure 6 Software streaming block diagram ana AA 52 Figure 7 DART interface block diagram ia NANANA 61 Figure 8 VART SIQI al S eT S 62 Figure 9 NO pin block diagram ina Ah GA NAA 65 Figure 10 I O pin configurations dama ANA GAAN AA 66 Figure 11 6 pin El 74 Figure 12 4 pin IEEE1394a connector EE 74 Figure 13 Pin numbering for 6 pin and 4 pin IEEE1394 connectors top view 74 Figure 14 Supplying the MCM from IEEET 204 74 Figure 15 Supplying power to the IEEE1394 cable e 75 Figure 16 Wiring of the DART interface Lesen RA rt nee ean mana aec 75 Figure 17 Wiring of the DSP JTAG mtertace ERR 76 Figure 18 Required connections ease 77 Figure 19 Dimensions of the UC1394a 1 including connector pins eesessssses 86 Figure 20 Recommended PCB footprint of the UC 1204a le 86 Figure 21 Soldering temperature example AEN 87 Figure 22 Peripheral interface read timing 1 1 111111111177 90 e USER S GUIDE Date 7 November 2006 ZZ j UC1394a 1 DSP MASTER BSP naay ee e orsys Page 8 Figure 23 Peripheral interface write Hminmg EE 91 Figure 24 Peripheral interface read timing 200MH2 EEN 91 Figure 25
116. wordHex Converts a 32 bit number into a string hexadecimal and puts the string into the debug transmit buffer This is a macro that calls the functions HexLong2Ascii and DebugPuts n USER S GUIDE Date 7 November 2006 CH 7 UC13944 1 DSP MASTER BSP ee orsys Page 28 defined in debug h synopsis void DebugOutDwordHex INT32U digit parameters digit 32 bit number to convert and put to the debug interface return value none 4 9 4 DebugOutNibbleHex Converts a 4 bit number lower 4 bits of 8 bit number into a string hexadecimal and puts the string into the debug transmit buffer This is a macro that calls the functions HexNibble2Ascii and DebugPuts defined in debug h synopsis void DebugOutNibbleHex INT8U digit parameters digit 8 bit number to convert and put to the debug interface return value none 4 9 5 DebugOutSByteDec Converts a signed 8 bit number into a string of 4 characters and puts the string into the debug transmit buffer This is a macro that calls the functions DecSigneaByte2Ascii and DebugPuts defined in debug h synopsis void DebugSByteDec INT8S digit parameters digit number to convert and put to the debug interface return value none e USER S GUIDE Date l 7 November 2006 Le H UC1394A 1 DSP MASTER BSP GER orsys Page 29 4 9 6 DebugOutSDwordDec Converts an signed 32 bit number into a string of 11 characters and puts the string into the
117. x 6 pin with latch 55395 xxx 4 pin IEEE1394a 2000 54515 xxx Table 10 IEEE1394 connector part numbers IEEE1394 1995 requires an isolation circuit such as shown in Figure 14 between cable shield and chassis ground whereas IEEE1394a removed the requirement for an isolated cable shield connection e USER s GUIDE Date 7 November 2006 Le UC1394a 1 DSP MASTER BSP paier O rsys Page 74 When cable power is required the 6 pin connector defined by IEEE1394 1995 must be used as shown in Figure 11 Otherwise the 4 pin connector defined by IEEE1394a can be used Figure 12 This connector is smaller and is often used in laptop computers For industrial environment 6 pin connectors with a robust case and latch are also available Figure 14 shows an example for supplying the MCM from IEEE1394 Figure 15 shows how to additionally supply power to IEEE 1394 Further information about cable power usage can be found in 8 9 and 10 Connection details for the 4 pin connector are shown in Figure 18 Figure 11 6 pin IEEE1394 connectors Figure 12 4 pin IEEE1394a connector O3 Or ZN an Figure 13 Pin numbering for 6 pin and 4 pin IEEE1394 connectors top view 6 pin IEEE1394 4 8 30V Voltage Figure 14 Supplying the MCM from IEEE1394 Power supply 3 3 V GND IEEE1394 TPB TPB TPA TPA USER S GUIDE Date

UC1394a-1 DSP Master BSP User's Guide

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