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DHQ11 User Guide

1. 1 4 1 2 Example of a DHQ11 Configuration 1 6 1 3 DHOII Connections EIA 232 D Rech ER EUN TES 1 7 1 4 DHOII Connections DECA23 iie sse a vea ER DU e os d 1 8 1 5 DHOQII Functional Block Diagram 1 15 2 1 Location of Switchpacks 22222 22 be aM Ves rm PUE NR 2 4 2 2 Setting the Device Address sagen Re EO EAS 2 5 2 3 Setting th Vector Address sissie shee 2 6 2 4 Bus Grant Continuity cese Cade dug d tes 2 7 2 5 Installing the DHQ11 EIA 232 D 2 10 2 6 Installing the DHQ11 DEC423 2 10 2 7 I O Insert Panels and Adapter Plate EIA 232 D 2 11 2 8 Insert Panel 2 3 oru SEE LER 2 12 2 9 H3101 Loopback Connector be RR E 2 14 2 10 H3173 A Circuit Dia tram 2 16 2 11 Null Modem Cable Connections 2 19 3 Register Coding ERE SEX eR acid ta Ma us 3 3 4 1 Troubleshooting DEC423 Installations 4 2 C 1 Transmitted Data Flow Control C 2 C 2 Receive FIFO Level Flow Control
2. 1 2 Physical Description 1 2 On Board Switchpacks 352229 pe phos oS 1 3 Communications Standard 1 3 Versions Of The DHQ11 1 23 uuu iw Set EUER EU 1 4 erste epu 1 5 Connections ee ee teste 1 7 SPECIFICATIONS 25 8 EIU tu 1 8 Environmental Conditions 1 8 Electrical Requirements 1 9 120808225222 eate het nsus aca 1 9 MO C oc 1 9 Data Rates een 1 9 Throughput cos cdot sew p RE eeu we 1 9 SERIAL INTERFACES 2254 vens ds ER xau e MES 1 10 Interface Standards 6002 4 queue v sb 1 10 Line 1 1 Line Transmitters we oe S ES Fer oou wi diet 1 11 Speed And Distance Considerations 1 11 FUNCTIONAL DESCRIPTION S n DER Ken ers 1 13 General tea Nea es Rw ee eee at aS 1 13 Main EuUnctons ee OU var ate M S OE RR 1 13 Control Cine eos esu deci et Da eR RE NUM Eq a 1 13 OCTART Chip ooi sv vbt EU M ea
3. C 3 C 3 Program Initiated Flow Control C 4 TABLES Table No Title Page 1 1 EIA CCITT Signal Relationships 1 10 1 2 Maximum Distance Guidelines for DHQl1 1 12 2 1 DHOIT Options scs tirer DR d A Meca wax 2 2 2 2 H31 3 A Connections db ed Wa ERA Sos MP IV E E OPEN 2 17 2 3 Serial Line Connections for the 36 Pin Connector 2 20 3 1 DHQI11 Registers in DHVI1 Mode 3 2 3 2 DHQI1 Registers in DHUI1 Mode 3 2 3 3 Rates PN ERR a 3 11 3 4 11 Self Test Error Codes os tase ERIS S DRM 3 28 A 1 Modem Control Leads Os Oise ge od RISE FA A 1 B 1 Floating Device Address Assignments B 1 B 2 Floating Vector Address Assignments ub 3 1 DHQ11 Q Bus Connections 1 The DHQl1 User Guide provides reference information on physical layout system configuration installation and testing programming characteristics and maintenance There is a glossary of technical terms generally used in DIGITAL technical manuals The manual is divided
4. 3 15 Transmit Buffer Address Register Number 1 TBUFFADI 3 19 Transmit Buffer Address Register Number 2 TBUFFAD2 3 19 Transmit DMA Buffer Counter TBUFFCT 3 20 PROGRAMMING FEATURES er EYE RII Ine 3 22 IntialiZAUOD 3 22 Config ration S edt PLE I dede DR META TE 3 23 Transmitting bred 3 23 DMA Transfers ironie BIA 3 23 Programmed I O DHV11 Mode 3 24 Programmed I O DHU11 Mode 3 24 RECEIVING ERITEENETE EEEE 3 24 Interrupt 5 25 dava xt aves e pta diete RIS 3 25 Auto And iiie asus enia EN EAST 3 25 IAUTO o ut vex EE Cod DE aU 3 26 FORCE XOFF TOTUM EP 3 26 97 05010 MM 3 26 DISABAXRPT ES 3 27 Error Indication EE 3 27 t t2 t t t bo by bn bo bo bo CHAPTER 4 4 1 4 2 4 3 4 4 4 4 1 4 4 2 4 5 4 5 1 4 5 1 1 4 6 4 6 1 4 7 APPENDIX A 2 2 1 APPENDIX B 1 B 2 APPENDIX C 1 2 3 5941 29 2 Modem Control 210 os dee eee bake 3 27 Maintenanc
5. 4 3 MicroPDP 11 DIAGNOSTICS 22 ERAS eases 4 3 User Mode Diagnostics 4 3 Running User Mode Tests 4 3 MicroVAX II DIAGNOSTICS Cente 4 3 ser Mode Tests ERE SV ER oe 4 4 FIELD REPLACEABLE UNITS FRUs 4 5 MODEM CONTROL SCOPE A 1 MODEM CONTROL bindu st ei oiae T Onen EVEA A 1 Example Of Auto Answer Modem Control For The PSTN A 2 FLOATING ADDRESSES FLOATING DEVICE ADDRESSES 2222 40 099 x9 T bem eser B 1 FLOATING VECTORS 2360506 eni dedu cem dei Ed IURE eds B 3 AUTOMATIC FLOW CONTROL OVERVIEW rot adi adit C 1 CONTROL OF TRANSMITTED DATA C 1 CONTROL OF RECEIVED DATA epe ERE C 2 Flow Control By The Level Of The Receive FIFO C 2 Flow Control By Program Initiation C 4 3 3 Mixing The Two Types Of Received Data Flow Control C 5 APPENDIX D GLOSSARY OF TERMS D 1 SCOPE MR D 1 D 2 GLOSSARY ps D 1 APPENDIX E DHQ11 Q BUS CONNECTIONS FIGURES Figure No Title Page 1 1 Layout of the DHOI
6. 12 1 Read Write Transmit Buffer Address 2 TBUFFAD2 Base 140 Read Wnite Transmit Buffer Count TBUFFCT 16 1 Read Write Table 3 2 DHQ11 Registers in DHU11 Mode Register Address Type Octal Control and Status Register CSR Base Read Write Receive Buffer RBUFF 2 Read Receive Timer RXTIMER 2 Write byte Line Parameter Register LPR Base 4 I Read Write FIFO Data FIFODATA 6 1 Write FIFO Size FIFOSIZE Base 6 I Read byte Line Status STAT 7 1 Read byte Line Control LNCTRL 100 Read Write Transmit Buffer Address 1 TBUFFAD1 Base 12 1 Read Write Transmit Buffer Address 2 TBUFFAD2 Base 140 Read Write Transmit Buffer Count TBUFFCT Base 16 1 Read Write Only accessible when CSR3 0 gt 0000 NOTE It is possible to write to the line status register However the host should not write to this register There are eight line parameter registers only one of which is accessed at any one time The register which is accessed is associated with the line selected using CSR lt 3 07 For example to read the line parameter register of channel 3 the following I O commands would be executed MOVB CHAN MOVB 5 4 WRITE CHANNEL NUMBER SEE BELOW CSR READ THE LINE PARAMETER REGISTER In the above example CHAN Oer00011 binary Where 3 2 the RXIE of the CSR the MASTER RESET bit which would be 0 channel
7. Name Description If there is an overrun condition the four character UART receive buffer for that channel will be cleared This data will be lost A null character is placed in the receive FIFO and RBUF lt 14 gt is set The DHQ11 does not have a break detect bit A line break is indicated to the program as a null character with FRAME ERR set and overrun is clear 3 2 2 3 Transmit Character Register TXCHAR Single character programmed transfers are made through the transmit character register TXCHAR WRITE BASE 2 DHV11 MODE 15 14 13 12 11 10 TRANSMIT DATA VALID Bit Name 15 TX DATA VALID Transmit Data Valid W lt 7 0 gt TX CHAR Transmit Character W TRANSMIT CHARACTER RE2749 Description When set this bit instructs the 11 to transmit the character held in bits lt 7 07 The bit is sensed by the DHQ11 which then transfers the character clears the bit and sets TX ACTION TX DATA VALID and TX CHAR can be written together or by separate MOVB instructions This contains the char cter to be transmitted The LSB is bit 0 3 2 2 4 Receive Timer Register RXTIMER DHU11 Mode Only The indirect address register CSR 3 07 must lt 0000 in order to access the receive timer The host can use the timer to delay the receive interrupt Rx TIMER WRITE BASE 2 DHU11 MODE 14 13 12 11 10 09 08 07 06 05 04 03 02 01 RE2750 3 8 Descrip
8. 3 bara READY 1 5 20 mwemocwonis aemrosew vs C3 REQUEST SEND 1 5 NE 4 DATA SET READY 1 5 6 8 DATA CARRIER DETECT 1 5 W1 PROTECTIVE GROUND J3 DATA CARRIER DETECT 2 6 DATA SET READY 2 6 REQUEST TO SEND 2 6 CLEAR TO SEND 2 6 RING INDICATOR 2 6 22 DATA TERMINAL READY 2 6 20 RECEIVE DATA 2 6 TRANSMIT DATA 2 6 o SIGNAL GROUND 1 DATA CARRIER 3 7 8 DATA SET READY 3 7 6 REQUEST TO SEND 3 7 4 CLEAR TO SEND 3 7 5 RING INDICATOR 3 7 22 DATA TERMINAL READY 3 7 20 RECEIVE DATA 3 7 3 TRANSMIT DATA 3 7 EB 2 SIGNAL GROUND EE 7 801147 Figure 2 10 H3173 A Circuit Diagram 2 16 Table 2 2 is for two distribution panels The numbers within parentheses apply to channels 4 to 7 Table 2 2 H3173 A Connections Signal Name Circuit No J5 Pin No SIG GND 0 4 102 1 2 TXDO 4 Transmitted Data 103 1 2 B RXDO 4 Received Data 104 C 2 C DTRO 4 Data Terminal Ready 108 2 1 D 2 D RIO 4 Ringing Indicator 125 1 E 2 E 50 4 Clear to Send 106 1 2 F RTSO 4 Request to Send 105 1 2 DSRO 4 Data Set Ready 107 1 K 2 K DCDO0 4 Data Carrier Detected 109 1 L 2 L SIG GND 1 5 102 1 M 2 M TXD1 5 103 1 2 N RXD1 5 104 1 2 P DTRI 5 108 2 1 R 2 R 1 5 125 1 5 2 5 CTS1 5 106 1 T 2 RTS1 5 105 U 2 0 05 1 5 107 1 W 2 W DCD1 5 109 1 X 2
9. en Eus ou Oe o er 2 12 Installation Tests MicroPDP 11 Systems 2 12 Testing In MicroVAX II Systems 2 13 H3101 LOOPBACK CONNECTOR 2 13 CABLES AND CONNECTORS EIA 232 D 2 15 Distribution Panel 2 15 Null Modenm Cables ak ve 2 18 Full Moden Cables iol ae med es Bae Vaca 2 19 CABLES AND CONNECTORS DEC423 2 20 PROGRAMMING SCOPE o cd is 3 1 Rd 3 1 Register ACCESS 2 00 rd ud San re us 3 1 Register Bit Definitions estu 3 3 Control And Status Register CSR 3 3 Receive Buffer cs an te vun sateen les 3 6 Transmit Character Register TXCHAR 3 8 Receive Timer Register RXTIMER DHU11 Mode Only 3 8 Line Parameter Register LPR 3 9 Line Status Register STAT 3 12 FIFO Size Register FIFOSIZE DHU11 Mode Only 3 14 FIFO Data Register FIFODATA DHU11 Mode Only 3 14 Line Control Register LNCTRL
10. Grounds APPENDIX E DHQ11 Q BUS CONNECTIONS Table 1 DHQ11 Q Bus Connections Signal Function BDALO L 11 BDAL2 L 15 L BDAL16 L 17 L BDALI8 L 21 L Data Address Lines BDOUT L Data Output Strobe BRPLY L Reply Handshake BDIN L Data Input Strobe BSYNC L Synchronize Strobe BWTBT L Write Byte Control BBS7 L I O Page Select BIRQ L Int Req Level 4 BIAKI L Int Ack Input BIAKO L Int Ack Output BDMR L DMA Request BDMGI L DMA Grant Input BDMGO L DMA Grant Output BSACK L Bus Grant Acknowledge BREF L Refresh and Block Mode BINIT L Initialization Strobe 5V De volts 12 V De volts GND Ground Connections GND Ground Connections GND Ground Connections GND Ground Connections Pin Number AU2 AV2 BE2 BV2 ACI ADI BC AE2 AF2 AH2 AJ2 AK2 AP2 AL2 AM2 AN2 ANI AR2 AS2 BN1 2 2 DA2 AD2 BD2 AC2 DC2 AMI BM1 INDEX A Address device 2 8 B 1 vector 2 8 2 5 B 3 B Background monitor program 3 30 4 2 4 3 BCO5L cables 1 2 1 6 1 7 2 2 4 1 BC16C cables 4 2 Cable concentrator H3104 2 2 2 17 Cables BCOSL 1 2 1 6 1 7 2 2 4 1 16 4 2 full modem 2 21 null modem 2 20 D Data rates 1 8 3 11 DEC423 1 1 1 2 1 6 1 7 1 8 1 9 1 10 1 11 1 12 2 2 2 9 2 10 2 11 2 13 2 22 4 1 Device address 2 3 B 1 DHU11 Mode 1 1 1 3 2 5 2 6 3 1 3 18 3 24 DHV11 Mode
11. 9 11 oe ys Rx 13 15 Rx 17 NOT USED due NOT USED 19 Tx RR s Rx 21 Tx 23 Tx Rx 25 Rx 27 Ec Rx 29 Rx 31 Rx 33 ceu Rx 35 NOT USED 36 NOT USED LINE O LINE 1 LINE 2 LINE 3 LINE 4 LINE 5 LINE 6 LINE 7 LINE O LINE 1 LINE 2 LINE 3 LINE 4 LINE 5 LINE 6 LINE 7 Figure 2 9 H3101 Loopback Connector 2 14 RE2439 FEMALE CONNECTOR RE2438 29 CABLES AND CONNECTORS EIA 232 D 2 9 4 Distribution Panel Each H3173 A distribution panel adapts one of the DHQ11 Berg connectors to four subminiature D type EIA 232 D connectors Noise filtering is provided on each pin of the EIA 232 D connectors This reduces electromagnetic radiation from the cables and also provides the logic with some protection against static discharge Figure 2 13 shows the circuit of the H3173 A There is no CCITT equivalent of EIA circuit AA Protective Ground To implement this circuit a ground strap must be installed between the H3173 A and the system cabinet The 0 ohm link W1 not installed at the factory can then be installed to connect this circuit and removed to disconnect it as needed 2 15 SIGNAL GROUND 7 DATA SET READY 0 4 DATA CARRIER DETECT 0 4 1 J2 SIGNAL GROUND 7 Lmwwswrpe vs Imcwewaws
12. If bit 7 0 and bit 0 1 then bits 5 2 contain circuit revision information 3 28 Table 3 4 DHQ11 Self Test Error Codes Cont Code Explanation Octal bits lt 7 0 Bit 6 always reads 1 for the DHQ11 and indicates that the circuit contains control and OCTART chips Bit 1 indicates to which chip the information refers 0 Control 1 OCTART After self test the eight FIFO codes consist of six diagnostic codes and two circuit revision codes If there are less than six errors to report null codes 201 octal fill the unused places After an error free test six null codes and two circuit revision codes will be returned Self test may be skipped to shorten the initialization cycle see Section 3 3 10 3 The module is still tested even if self test is skipped The reset delay is much shorter but test coverage is not affected therefore skipping self test is advantageous After skip self test self test the eight FIFO codes consist of six diagnostic codes and two circuit revision codes If there are less than six errors to report 203 octal codes fill the unused places After an error free test six 203 octal codes and two circuit revision codes will be returned 3 3 10 3 Skipping Self Test In DHUI11 mode only the method is to set SKIP CSR bit 4 and MASTER RESET CSR bit 5 simultaneously that is write 60 octal to the base CSR SKIP must not be cleared until at least 20 microseconds after it was
13. Otherwise the proper rules for address assignment must be applied these are given in Appendix C 2 3 2 Setting The Address Switches The device address for the DHQI11 is set on the 10 position switchpack E19 the location of this switchpack is shown in Figure 2 1 Switch 1 on the switchpack is used to setup the module in DHU11 or DHV11 programming mode 10 POSITION SWITCHPACK ADDRESS W1 Cod 8 POSITION SWITCHPACK VECTOR RE4503 Figure 2 1 Location of Switchpacks Figure 2 2 shows how to set the device address on the switchpack The example shown is for the factory set address of 17760440 2 4 DHU DHV MODE SELECTION DHU MODE SELECTED PART OF SWITCHPACK E19 LEGEND DEVICE ADDRESS SELECTION PART OF SWITCHPACK E19 lt SWITCH OFF BINARY O OPEN EXAMPLE SWITCH ON BINARY 1 CLOSED SETTING 217760440 INTERPRETED AS ALL ONES DECODED BY DEVICE SEE NOTE BIT NO DEVICE 1 7 7 0 ADDRESS S Pd EACH GROUP IDENTICAL hi x 7 lt 6 1 USE THE BLANK ROW PENCIL IN THE ADDRESS PATTERN YOU NEED u u uw NOOAWN HO 0 0 1 1 0 4 0 1 1 RE4504 Figure 2 2 Setting the Device Address 2 3 3 Setting The Vector Switches The six high order bits of the interrupt are set on the eight position switchpack E11 Figure 2 1 shows the location of this switchpack Figure 2 3 shows an example of these switches set to the factory setting o
14. 1 1 1 3 2 5 2 6 3 1 3 18 3 24 Diagnostics 2 18 3 4 3 11 3 41 MicroPDP 11 4 3 MicroVAX 4 3 Distribution panel panel 2 11 2 17 H3100 2 22 H3173A 2 2 2 20 DMA 8 20 3 23 3 35 request 2 8 Driver line 1 10 E EIA 232 D 1 1 1 2 1 6 1 7 1 8 1 9 1 10 1 11 2 2 2 9 2 10 2 11 2 13 2 17 2 20 4 1 1 F Full modem cables 2 21 H H3100 distribution panel 2 22 H3101 loopback connector 2 2 2 17 4 2 H3104 cable concentrator 2 2 2 17 H3173A distribution panel 2 2 2 20 I Interface serial 1 9 Interrupt request 2 8 L Line driver 1 10 receiver 1 10 Loopback connector H3101 2 2 2 17 4 2 M MicroPDP 11 diagnostics 4 8 MicroVAX II diagnostics 4 3 Mode DHU11 1 1 1 3 2 5 2 6 3 1 3 18 3 24 DHV11 1 1 1 3 2 5 2 6 3 1 3 18 3 24 Modem control 1 2 1 12 3 27 A 1 signals 1 9 2 19 3 12 3 18 1 full cables 2 21 null cables 2 20 signals 2 21 Monitor background program 3 30 4 2 4 3 Null modem cables 2 20 signals 2 21 OCTART 1 16 P Panel distribution 2 11 2 17 H3100 distribution 2 22 H3173A distribution 2 2 2 20 PSTN A 2 A 3 Q Q bus 1 2 1 8 1 12 2 7 R Receiver line 1 10 Request DMA 2 8 interrupt 2 8 Self test 3 28 4 2 Serial interface 1 9 Signals modem control 1 9 2 19 3 12 3 13 A 1 null modem 2 21 Switchpacks 1 2 1 3 2 8 2 4 2 5 2 6 V V 10 1 9 24 1 9 1 28 1 9 Vector
15. CMP 000400 R1 TXI BNE 2 IGNORE THE TX ACT IT 15 NOT OURS SHOULD NOT HAPPEN BR i GO BACK FOR NEXT CHARACTER 3 RTS PC MESSAGE SENT MESG ASCIZ SINGLE CHARACTER MESSAGE FOR CHANNEL 1 3 34 3 4 3 5 DMA Transfer THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE 29011 AND HALTS THE MACHINE WHEN ALL TRANSMISSIONS HAVE COMPLETED THE MESSAGES ARE TRANSMITTED USING DMA MODE AND INTERRUPTS ARE USED TO SIGNAL TRANSMISSION COMPLETION DMAINT MOV STXINT STXVECT SET UP THE INTERRUPT VECTORS MOV 200 TXPSW INTERRUPT PRIORITY FOUR MOV 8 RO EIGHT LINES TO START CLR R1 START LINE ZERD 1 MOVB Ri DHQCSR SELECT THE REGISTER BANK MOV DMASIZ TBFCNT SET LENGTH OF MESSAGE MOV DMAMES TBFAD1 SET LOWER 16 ADDRESS BITS MOV 100200 TBFAD2 START DMA WITH TRANSMITTER ENABLED ASSUME UPPER ADDRESS BITS ARE ZERO INC Ri POINT TO NEXT CHANNEL 508 RO 1 REPEAT FOR ALL LINES CLR R5 R5 IS USED BY INTERRUPT ROUTINE MOVB 100 DHGCSR 1 ENABLE TRANSMITTER INTERRUPTS 2 CMP 8 5 WAIT FOR ALL LINES TO FINISH BNE 25 3 HALT ALL DONE SO STOP BR 3 TRANSMITTER INTERRUPT ROUTINE R5 IS INCREMENTED AS EACH LINE COMPLETES ws TXINT MOV DHOCSR RO LINE NUMBER OF FINISHED LINE BIT 100000 RO CHECK FOR ANOTHER TX ACTION 45 IF GO RETURN AND WAIT INC R5 FLAG THAT ANOTHER LIN
16. PIN A BACKPLANE E c 022 15 BUS BCOSL XX s CABLE 40 PIN BERG gt 5 H3100 ACTIVE y ZA EY BULKHEAD PANEL 1 E S BACKPLANE K 022 18 BUS 2 Zs COLOURED STRIP POWER CABLE 70 22775 NOTE BCO5L 01 30cm 12 INCHES BCOSL 1K 53cm 21 INCHES BCOSL 03 92cm 36 INCHES RE3203 Figure 2 6 Installing the DHQ11 DEC423 2 10 2 6 2 Distribution Panels The rear I O distribution panel has six cutouts two type A cutouts and four type B cutouts In addition a removable bracket between the third and fourth cutout allows you to install three more type A insert panels by mounting an adapter plate Figure 2 7 shows typical type A and type B insert panels and the adapter plate 2 6 3 Installing The EIA 232 D Distribution Panels The has two type B distribution panels Figure 2 7 shows how these are installed in a BA23 box Installation in BA123 and H9642 cabinets is similar To fit the distribution panels 1 Remove the two type B blanking panels 2 Bolt the two H3173 A distribution panels into the cutouts 3 Connect the free end of the BCOSL XX cable from connector 71 of the module to the first distribution panel 4 Connect the free end of the BCOSL XX cable from connector J2 of the module to the second distribution panel TYPE B PANELS REMOVABLE INSERT 50 PIN CONNECTOR EXPANSION SLOTS TYPE A RE3204 Figure 2 7 I O Insert Panels and Adapter Plate EIA 232 D 2 6 4
17. R W DTR Data Terminal Ready R W MAINTENANCE OAUTO RX MODE ENABLE ABORT LINK FORCE BREAK RE2442 Description This bit controls the Request To Send RTS signal 1 ON 0 OFF This bit controls the Data Terminal Ready DTR signal 3 15 Link Type R W 7 6 MAINT Maintenance Mode R W Description ON 0 OFF This bit must be set if the channel is to be connected to a modem When the bit is set any change in modem status will be reported through the receive FIFO as well as the STAT register If this bit is cleared this channel becomes data leads only channel Modem status information is loaded in the high byte of STAT but is not placed in the receive FIFO These bits can be written by the driver or test programs in order to test the channel The coding is as follows 00 Normal operation 01 Automatic echo mode Received data is looped back to the terminal regardless of the state of TX ENA at the data rate selected for the receiver The received characters are processed normally and placed in the receive FIFO Any data that the host attempts to transmit on this channel will be discarded by the OCTART The RX ENA bit must be set when operating in this mode 10 Local loopback Data transmitted by host is looped back to the receive buffer Data received from the terminal is ignored a
18. Since DTR is already asserted the modem will auto answer the incoming call and start its handshaking sequence with the calling station The time needed to complete the handshaking sequence can be in the order of tens of seconds if fallback mode speed selection and satellite links are involved The modem will assert DSR to indicate to the DHQ11 that the call has been successfully answered and a connection established NOTE On some older types of modem used on the PSTN the opposite effect is also true The RI signal may be very short or it may not even occur if DTR was previously asserted When this type of modem answers an incoming call it asserts DSR almost immediately and deasserts RI at the line interface Programs must therefore expect RI or DSR or DCD as the first dataset status change received from the modem when establishing a connection As RTS was previously asserted the modem s carrier will be placed on the line when DSR is asserted When the modem has successfully placed its carrier on the line it will assert CTS This indicates to the DHQI11 that it can start to transmit data If the incoming call is the result of a misdialed number carrier signal may never be received To guard against this the host starts a timer when it detects RI or DSR This is usually in the range 15 to 40 seconds within which time the carrier must be detected When the modem detects the remote modem s carrier signal on the line it will assert DCD This
19. The logic uses these states for auto flow control Each channel has a separate IAUTO bit If there are 191 or more characters in the receive FIFO and a character is received on a channel with IAUTO set an XOFF character is sent If the channel does not respond to XOFF the DHQ11 will send another XOFF in response to every alternate character received An XON will be sent when the receive FIFO contains less than 128 characters unless the FORCE XOFF bit for that channel is set XONs are only sent to channels to which an XOFF has previously been sent By inserting XON and XOFF characters into the data stream the program can perform flow control directly However if the DHQI1 is in IAUTO mode the results will be unpredictable In IAUTO mode if RX ENA 15 set XON and XOFF characters will be transmitted even if TX ENA 15 cleared 3 3 6 2 FORCE XOFF When FORCE XOFF is set the DHQ11 sends an XOFF and then acts as if IAUTO is set and the receive FIFO is critical was three quarters full and is not yet less than half full When FORCE XOFF is reset an XON will be sent unless the receive FIFO is critical and IAUTO is set 3 3 6 3 OAUTO Ifthe program sets OAUTO the DHQ11 will automatically respond to XON XOFF characters from the channel It does this by clearing or setting the TX ENA bit The program may also control the TX ENA bit so in this case it is important to keep track of received XON and XOFF characters Received XON
20. This bit gives the present status of the Data Carrier Detected DCD signal from the modem 1 0 ON OFF This bit gives the present status of the Clear To Send CTS signal from the modem 1 0 ON OFF Always reads as 0 for DHQ11 to indicate that the module has modem support capability NOTE It is only necessary to read the modem support status for one line since all the other lines will have the same setting DHUID DHUII Identification bit R This bit allows software to distinguish between DHV11 mode and DHU11 mode 0 DHVI1I 1 DHUII 3 13 3 2 2 7 FIFO Size Register FIFOSIZE DHU11 Mode Only This low byte register holds number which indicates the space available in the transmit FIFO FIFOSIZE READ BASE 6 DHU11 MODE 14 13 12 11 10 09 EL 07 me 05 04 03 02 01 00 a RT 0 _ RI CTS FIFO SIZE 0 TO 64 RING DHUID INDICATOR SET TO 1 DHU11 MODE MDL MODEM SUPPORT PROVIDED FOR THIS LINE 1 MODEM SUPPORT NOT PROVIDED FOR THIS LINE Bit Name Description lt 7 0 gt FIFOSIZE This byte indicates the in characters available space FIFO Size in the transmit FIFO The range is 00000000 binary R BYTE to 01000000 binary 0 to 64 decimal This register should be read before sending a character or a sequence of characters to the transmit FIFO data register The byte is set to 01000000 binary by MASTER RESET 3 2 2 8 FIFO Data Register FIF
21. the DHOII will already be installed and you should refer to the instructions for unpacking the system If ordered as an add on option to an existing system a DHQ11 M Q bus module will be supplied together with a cabinet kit distribution panels and interconnecting cables The choice of cabinet kit depends on the type of system and on whether EIA 232 D or DEC423 connection standards apply Table 2 1 gives details of these options NOTE DEC423 is a term used in this manual to indicate a data leads only implementation of the RS 423 A electrical interface standard If the equipment is to be installed by DIGITAL Field Service the customer should not open the packages If the DHQ11 was ordered as an add on option find the carton marked OPEN FIRST and carefully unpack it There is a shipping list inside the carton Undo each package and examine the contents for physical damage Check that the contents of each package are complete Report any damaged or missing items to the shipping agent and to the DIGITAL representative Do not dispose of the packing material until the unit has been installed and is operational 2 1 DHQ11 M CK DHQI1 AA CK DHQ11 AF Contents H3173A BCOSL 1K BCOSL 01 BCOSL 03 CK DHQ11 WA CK DHQ11 WB CK DHQ11 WF Contents H3100 BCOSL 1K BCOSL 01 BCOSL 03 70 22775 1 70 22775 01 70 22775 03 H3104 BC16C 25 H3101 Table 2 1 DHQ11 Options M3107 module DHQ11 User Guide
22. the host must provide the addresses of suitable routines to deal with the above conditions In DHU11 mode an interrupt is generated either immediately data is put into an empty receive FIFO or after a delay set by RX TIMER 3 3 6 Auto XON And XOFF XON and XOFF characters are commonly used to control data flow on communications channels To use this facility interfaces must have suitable decoding hardware or software A channel using flow control that receives an XOFF stops sending characters until it receives an XON 3 25 the receive FIFO becomes more than three quarters the DHQ11 will send an XOFF code to that channel and to any other channel which receives a character and has the IAUTO bit set When FIFO becomes less than half full an XON will be sent to all channels which had previously been sent an XOFF The automatically controls character flow when programmed accordingly auto flow Four bits control this function IAUTO LNCTRL lt 1 gt FORCE XOFF LNCTRL lt 5 gt OAUTO LNCTRL lt 4 gt DISAB XRPT LPR lt 0 gt IAUTO and FORCE XOFF both control incoming characters IAUTO is an enable bit which allows the level of the receive FIFO to control the generation of XOFF and XON characters The FORCE XOFF bit is a direct command from the program to control the incomimg data stream 3 3 6 1 IAUTO The DHQ11 hardware recognizes when the receive FIFO is three quarters full and half full
23. Code Data Rate Maximum Bits s Error 0000 50 0 01 0001 75 0 01 0010 110 0 08 3 11 Table 3 3 Data Rates Cont Code Data Rate Maximum Bits s Error 96 0011 134 5 0 07 0100 150 0 01 0101 300 0 01 0110 600 0 01 0111 1200 0 01 1000 1800 0 01 1001 2000 0 19 1010 2400 0 01 1011 4800 0 01 1100 7200 0 01 1101 9600 0 01 1110 19200 0 01 1111 38400 0 01 3 2 2 6 Line Status Register STAT The high byte of this register holds modem status information In DHV11 mode the low byte is undefined STAT READ BASE 6 15 14 13 12 11 10 9 8 7 6 5 4 s g 1 fe DSR DCD DHUID SET 0 DHV11 MODE RI RING CTS MDL INDICATOR MODEM SUPPORT PROVIDED FOR THIS LINE 1 2 MODEM SUPPORT NOT PROVIDED FOR THIS LINE Bit Name Description 15 DSR This bit gives the present status of the Data Set Data Set Ready R Ready DSR signal from the modem 1 ON 0 OFF 3 12 13 12 11 Description NOTE In order to report a change of modem status the DHQI11 writes the high byte of STAT into the low byte of RBUF RBUF 14 127 indicates to the host that RBUF lt 7 0 gt holds modem status information instead of a received character RI Ring Indicator R DCD Data Carrier Detected R CTS Clear to Send R MDL MDL Modem Support Low R This bit gives the present status of the Ring Indicator RI signal from the modem 1 ON 0
24. EK DHQ11 UG Base Option EIA 232 D Cabinet Kits BA123 boxes BA23 boxes H9624 cabinets 4 line 25 way distribution panel 2 2 2 40 way ribbon cable 21 inch 2 40 way ribbon cable 12 inch 2 40 way ribbon cable 36 inch 2 DEC423 Cabinet Kits BA123 boxes BA23 boxes H9624 cabinets Active bulkhead panel Ribbon cable 2 inch Ribbon cable 12 inch 2 Ribbon cable 36 inch 2 Bulkhead power cable Bulkhead power cable 1 Bulkhead power cable Cable concentrator Multiway cable Multiway cable loopback pb 2 2 2 3 PREPARING THE DHQ11 MODULE Please check that your system has sufficient power and bus load capacity before installing additional modules see your system manual Before installing the DHQ11 you must define three parameters by selecting them on the on board switchpacks The parameters are Module address Interrupt vector or DHUII programming mode NOTE Ensure that you are wearing an antistatic wriststrap part number 29 11762 00 2 3 1 Address And Vector Assignment The has a floating device address and vector It is shipped from the factory with a device address of 17760440 and a vector of 300 These assignments are determined by the floating address and vector rules The factory settings are only correct if no other floating address option is installed in the system
25. FIFO CRIT T IAUTO 0 IAUTO 0 IAUTO 1 FIFO CRIT F CHAR CHAR RCVD IAUTO O FIFO CRIT T RCVD FIFO CRIT T FIFO CRIT F FIFO CRIT F 802252 Figure C 2 Receive FIFO Level Flow Control The receive FIFO level flow control mode is enabled by setting IAUTO 1 of the line control register and disabled by clearing the bit The default for this mode is disabled If IAUTO is cleared after an XOFF is sent but before the receive FIFO level drops below half full an XON is still sent NOTE FIFO CRIT is set T when the receive FIFO is being filled and contains 192 characters It is cleared F when receive FIFO reaches 127 characters as it is being emptied C 3 2 Flow Control By Program Initiation Occasionally the program itself may need to invoke flow control for example when host buffers become full To allow this the DHQ11 has FORCE XOFF bit bit 5 of the line control register When the FORCE XOFF bit is set the DHQ11 transmits an XOFF character for that channel A further XOFF bit is transmitted for every second character received on the channel afterwards An XON is sent when the FORCE XOFF bit is cleared Figure C 3 shows the operation of program initiated flow control The FORCE XOFF bit is cleared by DHQII reset sequence CHAR RCVD FORCE XOFF 1 CHAR CHAR RCVD RCVD FORCE XOFF 0 FORCE XOFF 0 802253 Figure 3 Program Initiated Flow Control NOTE If the program sets the FORCE XOFF
26. Grn Wht Line 1 Transmit 21 Wht Grn Line 1 Transmit 4 Brn Wht Line 1 Receive 22 Wht Brn Line 1 Receive 5 SIt Wht Line 2 Transmit 23 Wht Sit Line 2 Transmit 6 Blu Red Line 2 Receive 24 Red Blu Line 2 Receive 7 Org Red Line 3 Transmit 25 Red Org Line 3 Transmit 8 Grn Red Line 3 Receive 26 Red Gm Line 3 Receive 9 Brn Red Line 4 Transmit 27 Red Brn Line 4 Transmit 10 SIt Red Line 4 Receive 28 5 Line 4 Receive 11 Blu Blk Line 5 Transmit 29 Blk Blu Line 5 Transmit 12 Line 5 Receive 30 Blk Org Line 5 Receive 13 Grn Blk Line 6 Transmit 31 Blk Grn Line 6 Transmit 14 Brn Blk Line 6 Receive 32 Line 6 15 SIt BIk Line 7 Transmit 33 Blk Sit Line 7 Transmit 16 Blu Yel Line 7 Receive 34 Yel Blu Line 7 Receive 17 Org Yel Spare 35 Yel Org Spare 18 Grn Yel Spare 36 Yel Grn Spare 2 20 3 PROGRAMMING 31 SCOPE This chapter describes the device registers and how they are used to control and monitor the DHQ11 The chapter covers The bit functions and format of each register Programming features available to the host Some programming examples are also included NOTE DHUI11 programming mode is the preferred mode of operation for the DHQ11 The development of user drivers that use DHQ11 in DHV11 programming mode is not recommended 3 2 REGISTERS The host system controls and monitors the DHQ11 module th
27. MACHINE WHEN ALL TRANSMISSIONS HAVE COMPLETED THE MESSAGES ARE TRANSMITTED USING MODE AND INTERRUPTS ARE USED SIGNAL TRANSMISSION COMPLETION AUTOMATIC FLOW CONTROL IS ENABLED ON THE OUTGOING DATA TXAUTO MOY MOV MOV CLR 1 MOVE BIS MOV M V MOV INC 508 CLR MOVB 2 CMP BNE 35 HALT BR ATOINT TXVECT SET UP THE INTERRUPT VECTORS 200 STXPSW INTERRUPT PRIORITY FOUR 8 RO EIGHT LINES TO START Ri START AT LINE ZERO Ri DH CSR SELECT THE REGISTER BANK 24 8 LNCTRL ENABLE AUTOMATIC FLOW CONTROL ON THE TRANSMITTED DATA AUTOSZ TBFCNT SET LENGTH OF MESSAGE AUTOMS TBFAD1 SET LOWER 16 ADDRESS BITS 100200 TBFAD2 START DMA WITH TRANSMITTER ENABLED ASSUME UPPER ADDRESS BITS ARE ZERO POINT TO NEXT CHANNEL RO 1 REPEAT FOR ALL LINES R5 R5 IS USED BY INTERRUPT ROUTINE 100 9DHQCSR 1 ENABLE TRANSMITTER INTERRUPTS 8 R5 WAIT FOR ALL LINES TO FINISH 2 ALL DONE 50 STOP 3 3 39 TRANSMITTER INTERRUPT ROUTINE R5 IS INCREMENTED AS EACH LINE COMPLETES ATOINT MOV SDHOCSR RO GET LINE NUMBER FINISHED LINE BIT 10000 0 CHECK FOR FAILURE BNE 4 GO HALT MEMORY PROBLEM INC R5 FLAG THAT ANOTHER LINE HAS FINISHED 2 RTI 4 HALT MEMORY PROBLEM BR 4 AUTOMS ASCII 15 12 7 72 7 SYSTEM CLOSING DOWN NOW AUTOSZ AUTOMS EVEN 3 40 3 4 6
28. Transmitter Enable R W characters When this bit is cleared the DHQl1 will only transmit internally generated flow control characters The bit is set by MASTER RESET In the OAUTO mode this bit is used by the DHQ11 to control outgoing characters 3 19 Name Description 7 TX DMA START This bit is set by the host to start a DMA transfer Transmit DMA Start R W The DHQI11 will clear the bit before returning TX ACTION The bit is cleared MASTER RESET NOTE After setting this bit the host must not write to TBUFFCT TBUFFADI or TBUFFAD2 lt 7 0 gt until the TX ACTION report has been returned 5 07 TBUFFAD 21 16 Bits 21 16 of the DMA address Before DMA Transmit Buffer Address High transfer TBUFFAD1 and the low byte of R W TBUFFAD2 are loaded with the start address of the buffer This address will be continuously changing during a DMA transfer and has no meaning Once TX ACTION has been returned the register contains the final DMA transfer address 3 2 2 12 Transmit DMA Buffer Counter TBUFFCT TBUFFCT BASE 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pen CHARACTER COUNT WHEN VALID HOLDS NO OF CHARS STILL TO BE SENT Bit Name Description 15 0 TX CHAR CT This word is loaded with the number of characters to Transmit Character Count R W transferred by DMA The number of characters is specified as a 16 bit unsigned intege
29. and receive baud rates for each line can be individually programmed Ithasa total module throughput of 60 000 characters per second using 8 bit characters with all channels operating at 38 4 kbaud for both character reception and transmission 1 1 The supports 16 18 or 22 bit addressing including block mode data transfer with suitable memories The can be programmed to filter XON XOFF characters from the received data flow Self test and background monitor testing Dual height module M3107 Switchpacks for selecting the Q bus base address vector address and DHV11 or DHUII programming mode All other functions are selected by program 1 2 1 1 Modem Control Facility eight channels have sufficient modem control to allow auto answer dial up operation over the public switched telephone network using suitable modems such as DIGITAL s DF124 or Bell models 103 113 212 Equivalent modems from other manufacturers can also be used The DHQ11 is designed to minimize software requirements for modem link control Appendix gives further information on modem control Modem control can be used for driving modems over both public and private lines Please note that in some countries modems must be approved by the PTT for that country for connection to the public network 1 2 1 2 Self Test Facility The DHQI1 incorporates self test sequencers which operate independently of the host The result
30. flickers and end of self test is delayed for 1 2 seconds to maintain compatibility with DHV11 At the end of the delay period the LED turns on and the MASTER RESET is cleared If the board is in DHU11 mode the LED flickers and the end of self test is delayed for 1 7 seconds to maintain compatibility with DHU11 At the end of the delay period the LED turns on and the MASTER RESET is cleared In all three cases if the self test encounters a failure the LED will be off after the self test and delay has completed NOTE The DIAG FAIL bit controls the LED when the DIAG FAIL bit is set the LED is off and when it is clear the LED is off Self test provides a high level of confidence that the majority of the module logic is working The user diagnostics must also be used to test the Q bus interface and verify that the switch settings on the module switchpacks are correct 4 4 20 Background Monitor Program BMP When the DHQ11 is not doing other tasks the BMP carries out tests on the module If an error is detected the BMP reports to the host via the FIFO and also switches OFF the diagnostics passed LED By writing codes to the line parameter register the host can cause the BMP to report the status of the device even if an error has not been detected This facility is used if the host suspects that the option is faulty More information on the self test and BMP diagnostics is given in Chapter 3 of this manual 4 5 Mic
31. identify whether the problem is caused by The module A terminal The cabling and distribution panels First decide whether the problem is associated with one channel a group of four channels or all eight channels If all channels are faulty run the user diagnostics to test the module Also check whether your software has a driver for the DHQ11 If a group of four channels are faulty check the BCOSL xx cable connected to the module For single channel problems EIA 232 D 1 Check for loose cables and connectors 2 Verify that the terminal is working correctly If necessary swap it with another one 3 When a modem line is suspect check that the modem is correctly configured for modem signals supported by the DHQ11 Also check that the software driver has the correct baud rate setting and that modem support is enabled for that line 4 If the problem cannot be solved call DIGITAL Field Service For single channel problems DEC423 1 Check for loose cables and connectors 4 1 2 Verify that terminal is working correctly If necessary swap it with another one 3 Disconnect the BC16C XX cable from the distribution panel and connect it to the H3101 loopback connector 4 characters at terminal connected to suspect line If characters echoed back when the H3101 is connected the cables and terminal are working If characters are not echoed back the fault lies with the cable conne
32. indicates to the DHQ11 that data is valid on the line The modem can now exchange data between the DHQ11 and the calling station for as long as DCD DSR and CTS stay asserted If any of these three signals disappears or if RI is detected during normal transmission a fault condition is indicated A change of state of any of these signals causes an interrupt through the receive FIFO The handling of the fault conditions now becomes country specific since some telephone systems tolerate a transient carrier loss while others do not In the USA itis usual to proceed with a call if carrier resumes within two seconds In non USA areas it is possible for telephone supervisory signals such as dial tone to be misinterpreted by the modem as a resumption of carrier In this case the host program would assume that the connection had been re established to the original caller and would cause a hung channel To prevent this DTR should be deasserted immediately after the loss of DCD CTS or DSR to abort the connection DTR should stay deasserted for at least two seconds after which time a new call could be answered APPENDIX FLOATING ADDRESSES 1 FLOATING DEVICE ADDRESSES On Q bus systems a block of addresses in the top 4K words of address space is reserved for options with floating device addresses This range is from 17760010 to 177637764 Options which can be assigned floating device addresses are listed in Table B 1 This tabl
33. into four chapters as follows CHAPTER 1 INTRODUCTION This chapter gives a physical description of the DHQ11 explains how it can be configured and explains how it interfaces with the system bus and serial data lines CHAPTER 2 INSTALLATION Chapter 2 describes how to install DHQ11 option with detailed information on device and vector address selection backplane positioning cables and connectors and testing after installation CHAPTER 3 PROGRAMMING This chapter describes the DHQ11 registers Some programming examples are also included CHAPTER 4 TROUBLESHOOTING Chapter 4 explains maintenance strategy and how to use diagnostic programs to locate a faulty module APPENDICES These include additional information on topics discussed in this manual APPENDIX A MODEM CONTROL APPENDIX B FLOATING ADDRESSES APPENDIX C AUTOMATIC FLOW CONTROL APPENDIX D GLOSSARY OF TERMS APPENDIX E BUS CONNECTIONS This revision of the manual contains new information The DHQ11 can operate in two different modes making it compatible with software drivers written for either the DHV11 or the DHU11 Revision 001 of this manual contained information on DHV11 mode of operation only 1 INTRODUCTION 1 1 SCOPE This chapter gives an overview of the DHQ11 asynchronous multiplexer describes the features that it offers and defines its physical parameters and electrical requirements 1 20 OVERVIEW 1 2 1 Gener
34. number 3 0011 NOTE 1 Notallregister bits are used In a write action all unused bits must be written as 0s In a read action unused bits are undefined 2 Read modify write instructions may be used on all registers except CSR and RBUF 3 2 2 Register Bit Definitions Registers which are modified by reset sequences are coded as shown in Figure 3 1 CLEARED BY MASTER RESET SET BY MASTER RESET CLEARED BY BINIT BUT NOT BY MASTER RESET RD2249 aad Figure 3 1 Register Coding 3 2 2 1 Control And Status Register CSR CSR BASE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SKIP DIAGNOSTICS TRANSMIT DUM INDIRECT ADDRESS REG POINTER ACTION FAILURE LINE NUMBER CHANNEL NO IUE ENABLE TRANSMIT RCVE DATA MASTER DMA ERROR AVAILABLE RESET DHU11 MODE ONLY UNUSED IN DHV11 MODE RE10 14 13 TX ACTION Transmitter Action R Description This bit is set by the when 1 The last character of a DMA buffer has left the OCTART 2 A DMA transfer has been aborted 3 A DMA transfer has been terminated by the DHQI11 because non existent memory has been addressed or because of a host memory parity error 4 In DHV11 mode single character programmed output has been accepted that is to say the character has been taken from TX CHAR 5 In DHU11 mode following a programmed data transfer the module has emptied a transmit FIFO The bit is clea
35. 0 Connections to external equipment are made via 25 pin male subminiature D type connectors as specified for EIA 232 D or 6 pin MMJ connectors for DEC423 NOTE The H3173 A distribution panel does not support separate transmit and receive grounds Table 1 1 shows how the signals in EIA 232 D V 24 and RS 449 are related and lists the pin connections for male subminiature D type connectors Table 1 1 EIA CCITT Signal Relationships Signal Name D type EIA2232 D Circuit Circuit Pin CCITT RS 449 V 24 Signal Ground SIG 7 AB 102 SG GND RS 423 A Receive Common RC 102B Transmitted Data TXD 2 BA 103 SD Received Data RXD 3 104 RD Request To Send RTS 4 CA 105 RS Clear To Send CTS 5 CB 106 CS Data Set Ready DSR 6 CC 107 DM Data Terminal Ready DTR 20 CD 108 2 TR Data Carrier Detect DCD 8 CF 109 RR Ring Indicator RI 22 125 IC Not Connected 1 10 1 4 2 Line Receivers The DHOI1 uses octal serial line receivers which convert line input signals to TTL levels for the OCTART Signals are inverted by the receivers 1 4 8 Line Transmitters The uses EIA transmitters which convert TTL level signals from the OCTART and modem latches to line levels on the data and modem lines 1 4 4 Speed And Distance Considerations As of December 1985 the Electronics Industries Association EIA have replaced the RS identifier for RS 232 C with EIA Therefore RS 232 C has been replaced by EIA 232 D T
36. 7760440 first device of this type has a fixed address Any extra devices have a floating address The first two devices of this type have a fixed address Any extra devices have a floating address The 0211 and DZI11 F are treated as two 07115 The address assignment rules are as follows l Addresses starting at 17760010 for Q bus systems are assigned according to the sequence of Table B 1 Option and gap addresses are assigned according to the octal modulus as follows Devices with an octal modulus of 4 are assigned an address a 4 boundary the two lowest order address bits 0 Devices with an octal modulus of 10 are assigned an address on 10 boundary the three lowest order address bits 0 Devices with an octal modulus of 20 are assigned an address on a 20 boundary the four lowest order address bits 0 Devices with an modulus of 40 are assigned an address on a 40 boundary the five lowest order address bits 0 Address space equal to the device s modulus must be allowed for each device which is connected to the bus A 1 word gap assigned according to rule 2 must be allowed after the last device of each type This gap could be bigger when rule 2 15 applied to the following rank 5 Al word gap assigned according to rule 2 must be allowed for each unused rank on the list if a device with a higher address is used This gap could be bigger when rule 2 is ap
37. CK FOR NEXT CODE RTS PC RETURN CARD IS RESET DHO11 HAS FAILED TO RESET PROPERLY 50 HALT AND WAIT FOR THE FIELD SERVICE ENGINEER DIAGER HALT BR DIAGER 3 31 3 4 22 Configuration This routine sets the characteristics of channel 1 as follows 1 Transmit and receive at 300 bits s 2 Seven data bits with even parity and one stop bit 3 Transmitters and receivers enabled 4 No modem control 5 No automatic flow control SETUP 1 DHQCSR LOAD INDEX REG WITH CHANNEL MOV 052560 LPR DATA RATE STOP BITS PARITY AND LENGTH MOV 84 SLNCTRL ENABLE THE RECEIVER MOVB 200 TBFAD2 1 ENABLE THE TRANSMITTER RTS PC RETURN CHANNEL 1 DONE 3 32 3 4 3 Transmitting 3 4 3 1 Single Character Programmed Transfer DHU11 Mode The following is a program to send a message on channel 1 The CSR is polled for TX ACTION reports but a TX ACTION interrupt could also be used This program would function on a DHQ11 with only this channel active Otherwise it would lose TX ACTION reports of other channels However a program to control all channels would be too big to use as an example FIFOUT MOV MOV MOV 1 TSTB MOVB 508 2 MOV BPL BIC CMP BNE RTS 1 DHQCSR MESG RO MESIZE Ri FIFOSIZE 1 FIFODATA R1 1 SDHOCSR R2 2 8170377 R2 000400 R2 2 PC A ROUTINE TO WRIT
38. Checking Diagnostic Codes THIS ROUTINE CHECKS THE DIAGNOSTICS CODES RETURNED FROM THE DHQ14 ON ENTRY CONTAINS THE CHARACTER RECEIVED FROM THE DHQ11 ON EXIT THE CARRY BIT WILL BE CLEAR FOR SUCCESS SET FOR FAILURE DIAG MOV RO SP SAVE THE CODE FOR LATER BIC 107776 RO CHECK THAT IT IS A DIAG CODE CMP 070004 BNE DIAGEX IF NOT JUST EXIT NORMALLY MOV SP RO GET THE CODE BACK BITB 200 RO CHECK FOR CHIP VERSION NUMBER BEG DIAGEX CMPB 201 RO SELF TEST NULL CODE BEG DIAGEX CMPB 203 0 SELF TEST SKIPPED CODE BEG DIAGEX CMPB 305 DHO RUNNING CODE BEG DIAGEX ALL THE REST ARE ERROR CODES SEC AN ERROR CODE WAS RECEIVED SO BR DIAGXX SET THE CARRY FLAG DIAGEX CLC EVERYTHING OK SO CLEAR CARRY DIAGXX RESTORE THE CHARACTER INFO HOV SP RO RTS PC 3 41 4 TROUBLESHOOTING 41 SCOPE This chapter explains how to isolate the cause of a communications problem between the DHQ11 and the equipment to which it is connected 42 PREVENTIVE MAINTENANCE No preventive maintenance is needed for this option However you should always ensure that all cables are clear of danger and that all the connectors are secure Make sure that all cables are clearly labelled so that you can easily identify which channel number and which module are associated with each terminal 43 TROUBLESHOOTING PROCEDURES Troubleshooting procedures are to
39. DZ11 DZS11 DZV11 0232 4 10 28 KMCII 4 10 29 LPP11 4 10 30 VMV21 4 10 31 VMV3I 4 10 32 01 4 10 33 DWR70 4 10 34 RL11 RLV11 2 4 35 TS11 TU80 2 4 36 11 4 10 37 IP11 IP300 2 4 38 KW11 C 4 10 39 RX11 RX211 RXV11 RXV21 2 4 40 DR11 W 2 4 41 DRI11 B 2 4 42 DMPI1 4 10 43 DPVI1 4 10 44 2 4 7 45 4 10 46 DMVI11 4 10 47 DEUNA 2 4 48 KDASO RQDX3 2 4 49 DMF32 16 4 50 KMSII 6 10 51 11 4 10 52 VS100 2 4 53 81 2 4 54 11 4 10 55 KCT32 4 10 56 IEX 4 10 57 DHVII DHUI1 DHQII 4 10 B 4 Table 2 Floating Vector Address Assignments Cont Rank Device Size Modulus Decimal Octal 58 DMZ32 CPI32 async 12 4 59 CPI32 sync 12 4 60 QNA 12 4 61 QVSS 4 10 62 VS31 2 4 63 LNV11 2 4 64 QPSS 2 4 65 QTA 2 4 66 DSV11 2 4 first device of this type has a fixed vector Any extra devices have a floating vector KL11 or is used as the console it has a fixed vector MILII is a MASSBUS device which can connect UNIBUS via a bus adapter APPENDIX AUTOMATIC FLOW CONTROL C1 OVERVIEW Flow control is the control of the flow of data along a communications line to prevent an overspill of queues or buffers or to prevent the loss of data which the receiver is unable to accept The method of flow control adopted for the DHQ11 is datastream embedded ASCII control characters The control characters used are XOFF oc
40. E DEC423 to 1 232 0 is intended for local communication In general communication devices can become non operational or be damaged if the total cable length exceeds 300 metres 1000 feet for DEC423 devices The cable should not be run outside the building and the low voltage data wiring must be separated from ac power wiring The installation or sites may require additional devices to correct problems in communication NOTE Under ideal conditions DEC423 devices can drive cables considerably longer than the 1000 foot maximum stated above However differences in 1 12 ground potential pick up from mains ac power cabling and risk of induced interference limit the maximum distance for reliable communications in most practical situations 1 5 FUNCTIONAL DESCRIPTION 1 5 1 General The 11 functional blocks are shown in Figure 1 5 Most of the functions are provided by two chips the control chip and the OCTART chip Q bus buffering uses six DC021 bidirectional buffers Serial line interface buffering uses five octal line receivers 5180 and three octal line transmitters 5170 used for data and modem signals A 2k x 8 static RAM chip 2018D 45 provides the memory requirements Switchpacks provide vector address and module address selection 1 5 2 Main Functions The main functions of the DHQ11 are Transmission Single characters DHV11 mode or multiple characters DHU11 mode can be transmitted using programm
41. E A MESSAGE TO CHANNEL 1 USING FIFO OUTPUT MODE PROGRAMMED TRANSFERS POINT TO CHANNEL WE WISH TO TALK POINT TO MESSAGE PUT COUNT IN CHECK THAT THERE IS SPACE IN THE FIFO MOVE CHARACTER TO TRANSMIT FIFO GO BACK FOR NEXT CHARACTER WAIT FOR TX ACT ISOLATE CHANNEL NUMBER IGNORE THE TX ACT IF IT IS NOT OURS SHOULD NOT MESSAGE SENT MESG ASCII A TRANSMIT FIFO MESSAGE FOR CHANNEL 1 MESIZE EVEN 56 3 33 3 4 3 2 Single Character Programmed Transfer DHV11 Mode This is program to send a message on channel 1 The message MESG 15 an ASCII string with a null character as terminator Polling is used but a TX ACTION interrupt could also be used This program would function on a DHQ11 with only this channel active Otherwise it would lose TX ACTION reports of other channels However a program to control all channels would be too big to use as an example ROUTINE URITE MESSAGE CHANNEL 4 USING SINGLE CHARACTER MODE SINGOT MOV 1 DHQCSR LOAD INDEX REG WITH CHANNEL NO MOV MESG POINT MESSAGE 1 MOVB RO TXCHAR CHARACTER TO TRANSMIT BUFFER 35 60 RETURN ALL CHARACTERS GONE MOVB 8200 8TXCHAR41 SET DATA VALID BIT TO START 2 MOV SDHGCSR R1 WAIT FOR TX ACT BPL 25 BIC 174377 R1 ISOLATE CHANNEL NUMBER
42. E HAS FINISHED BR TXINT 4 RTI 5 HALT MEMORY PROBLEM BR 5 DMAMES ASCII 15 12 72 7 7 SYSTEM CLOSING DOWN NOW DMASIZ DMAMES EVEN 3 35 3 4 3 4 Aborting A Transmission THIS ROUTINE IS CALLED ABORT A TRANSMISSION EITHER DMA OR FIFO IN PROGRESS ON A SPECIFIED LINE THIS ROUTINE MAKES THE RATHER RASH ASSUMPTION THAT THERE ARE NO OTHER TRANSFERS IN PROGRESS ON ENTRY RO CONTAINS THE NUMBER OF THE LINE TO BE ABORTED ws TXABRT MOV RO DH CSR POINT THE CHANNEL BE ABORTED BIS 1 LNCTRL SET THE TRANSMIT ABORT BIT 15 MOV DHGCSR R1 WAIT FOR THE TX ACT BPL 15 SWAB Ri CHECK IT IS OUR LINE BIC 177760 R1 CMP RO R1 BNE 1 IGNORE IT IF IT IS NOT OUR ASSUMPTION WAS WRONG BIC 1 SLNCTRL CLEAR DOWN THE ABORT FLAG FOR NEXT TIME RTS PC BUFFER COMPLETELY ABORTED DMA REGISTERS REFLECT WHERE IF DMA WAS IN PROGRESS THE THE DHO44 HAD TO 3 36 3 4 4 Receiving THIS ROUTINE PROCESSES RECEIVED CHARACTERS UNDER INTERRUPT CONTROL IF AN XOFF IS RECEIVED THE TRANSMITTER FOR THAT CHANNEL IS TURNED OFF IF AN XON IS RECEIVED THE TRANSMITTER IS TURNED BACK ON ALL OTHER CHARACTERS ARE IGNORED THIS IS JUST AN EXAMPLE A BETTER WAY TO PERFORM FLOW CONTROL IS TO USE THE AUTOMATIC CAPABILITIES OF THE DHO11 Ss RXAUTO MOV SRXINT SRXVECT SET UP THE INTERRU
43. EK DHQ11 UG 002 DHQ1 1 User Guide Prepared by Educational Services of Digital Equipment Corporation Second Edition July 1987 Copyright 1987 by Digital Equipment Corporation All Rights Reserved Printed in U S A The information in this document is subject to change without notice Digital Equipment Corporation assumes responsibility for any errors herein The following are trademarks of Digital Equipment Corporation il MASSBUS RT 11 DECmate PDP UNIBUS DECsystem 10 P OS VAX DECSYSTEM 20 Professional VAXBI DECUS Rainbow VMS DECwriter RSTS VT DIBOL RSX Work Processor FALCON 1 DOD ERA 1151999999999999 ba ad jd o jm 4 jd deed pd eR CHAPTER 2 2 1 2 2 2 3 2 3 1 2 3 2 2 3 3 2 3 4 2 4 2 4 1 CONTENTS INTRODUCTION SCOPE 5 M PIC Apte 1 1 OVERVIEW iit cai hated tack ont ates duda A LE 1 1 General Description a ha ee 1 1 Modem Control Facility DUE 1 2 SEM Test Facility ouo Ero 1 2 Diagnostic Programs 1 2 Preventing Data Loss
44. Installing The DEC423 Distribution Panels The DHQ11 has one type B distribution panel Figure 2 8 shows how this is installed in a BA23 box Installation in BA123 and H9642 cabinets is similar 2 11 To fit the distribution panels 1 Remove a type B blanking panel 2 Bolt the H3100 active distribution panel into the cutout 3 Connect the free end of the BCOSL XX cable from connector J1 of the module to the upper J2 connector on the distribution panel 4 Connect the free end of the BCOSL XX cable from connector J2 of the module to the lower J1 connector on the distribution panel 5 Connect the free end of the power cable 70 22775 X X to the left hand power connector J5 on the distribution panel REMOVABLE INSERT 50 PIN CONNECTOR EXPANSION SLOTS RE3205 Figure 2 8 I O Insert Panel DEC423 2 7 INSTALLATION TESTING This section details the diagnostics used to test the option during and after installation The diagnostics are also used to test other Q bus modules in the same family for example DHV11 The diagnostics will automatically size the option to determine which one is being tested Both MicroPDP 11 and MicroVAX II diagnostics are described After successful completion of the appropriate system test the DHQ11 may be connected to external equipment Further information on the diagnostics is given in Chapter 4 2 7 1 Installation Tests On MicroPDP 11 Systems To verify that the MicroPDP 11 system and th
45. ODATA DHU11 Mode Only To send a character or characters through a transmit FIFO the host writes the character s to the transmit FIFO data register of the appropriate channel To make sure that there is room in the transmit FIFO the host should first read the associated transmit FIFO size register If single characters are sent they must be written to the low byte of FIFODATA FIFODATA WRITE BASE 6 DHU11 MODE 14 13 12 11 10 09 08 07 06 05 04 03 02 01 DATA CHARACTER TX DATA RE2720 lt 15 0 gt lt 7 0 gt Name FIFODATA lt 15 0 gt FIFO Data Register W FIFODATA 7 0 gt FIFO Data register W BYTE Description This word contains two characters for transfer through the transmit FIFO After a write word action to this register FIFODATA lt 7 0 gt and then FIFODATA lt 15 8 are transferred to the transmit FIFO The least significant bits of the characters are in FIFODATA bits 0 and 8 This byte contains one character for transfer through the transmit FIFO After a write byte action to this register FIFODATA lt 7 0 gt is transferred to the transmit FIFO The least significant bit of the character is in FIFODATA bit 0 3 22 9 Line Control Register LNCTRL The main function of this register is to control the line interface LNCTRL BASE 10 15 14 13 12 11 10 09 08 07 06 05 04 03 02 00 5 DTR Name RTS Request To Send
46. PT VECTORS MOV 200 RXPSW INTERRUPT PRIORITY FQUR MOV 8 ENABLE ALL THE RECEIVERS CLR R1 STARTING AT CHANNEL ZERO 1 MOVB Ri DHQCSR SELECT THE LINE BIS 84 8SLNCTRL ENABLE THIS RECEIVER INC Ri SET POINTER TO NEXT CHANNEL SOB RO 1 MOVB 100 ENABLE THE RECEIVER INTERRUPTS RTS PC RETURN INTERRUPTS DO THE RESET 3 37 INTERRUPT ROUTINE DO THE MAIN TASK RXINT RXNXTC 15 RXIEND MOV MOV BPL MOV BIC BNE BIC SWAB BIS MOVB SWAB CMPB BNE BISB BR CMPB BNE BICB BR MOV RTI RO SP SAVE CALLER S REGISTERS RBUFF RO GET THE CHARACTER RXIEND IF DATA VALID WE HAVE FINISHED CHECK FOR ERRORS MODEM AND 107777 5 DIAGNOSTICS CODES RXNXTC JUST IGNORE THEM BAD PRACTICE 170200 RO REMOVE UNNECESSARY BITS RO POINT TO THIS CHARACTER S LINE 100 RO ADD THE INTERRUPT ENABLE BIT RO DHOCSR RO PUT CHARACTER BACK IN LOWER BYTE 421 0 WAS IT 1 NO GO CHECK FOR AN 200 8TBFAD2 1 ENABLE THE TRANSMITTER RXNXTC GO CHECK FOR MORE CHARACTERS 23 RO WAS IT AN XOFF RXNXTC NO GO CHECK FOR MORE CHARACTERS 200 TBFAD2 1 DISABLE THE TRANSMITTER RXNXTC GO CHECK FOR MORE CHARACTERS SP RO RESTORE THE DESTROYED REGISTER 3 38 3 4 5 Auto XON And THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE 011 AND HALTS THE
47. Saad 1 14 INSTALLATION SCOPE CC 2 1 UNPACKING AND INSPECTION 2 1 PREPARING THE DHQ11 MODULE 2 3 Address And Vector Assignment 2 3 Setting The Address Switches 2 3 Setting The Vector Switches 2 5 DHV11 DHU11 Programming Selection 2 6 BUS CONTINUITY ERST see ee 2 6 Bus Grant Continuity Jumpers 2 7 iii D A UN UJ N NNNNNNNNNNNN Ne NNI Whe WW AU i PRIORITY SELECTION Ce ted dee erba 2 8 DMA Request PEOPDED dese reet mra REN FRE NERVAE 2 8 Interrupt Request Priority PR tam natin Gece sa dala 2 8 Recommendations 5502 toned EU te COP DEI Ue 2 8 INSTALLING THE 11 2 TR amen cone e EAE EN RES 2 8 Installing The M3107 Module 2 8 Distribution Panels san E Des XE RM ROC 2 1 Installing The EIA 232 D Distribution Panels 2 11 Installing The DEC423 Distribution Panels 2 11 INSTALLATION TESTING 25
48. X DCD2 6 109 1 Y 2 Y DSR2 6 107 1 Z 2 Z RTS2 6 105 1 BB 2 BB CTS2 6 106 1 CC 2 CC RI2 6 125 1 DD 2 DD DTR2 6 108 2 1 EE 2 EE RXD2 6 104 1 FF 2 FF TXD2 6 103 1 2 SIG GND 2 6 102 1 2 JJ DCD3 7 109 KK 2 KK DSR3 7 107 1 LL 2 LL RTS3 7 105 1 NN 2 NN CTS3 7 106 1 PP 2 PP RI3 7 125 1 2 RR DTR3 7 108 2 1 SS 2 SS RXD3 7 104 1 TT 2 TT TXD3 7 103 UU 2 UU SIG GND 3 7 102 1 VV 2 VV The following examples show how to use Table 2 2 Signal TXDO is the transmitted data line for channel 0 the CCITT circuit number is 103 and it is connected to J5 pin B on the first H3173 A for channels 0 to 3 2 17 Signal 4 is the transmitted data line for channel 4 the CCITT circuit number is 103 and it is connected to J5 pin B on the second H3173 A for channels 4 to 7 2 9 2 Null Modem Cables Null modem cables are used for local EIA 232 D connection when a modem is not used Because of Federal Communications Commission FCC regulations the cable specifications for the United States and Canada are different from those for non FCC countries Other countries may also have similar electromagnetic interference EMI control regulations EMC RFI shielded cabinets are now available for systems which conform to FCC requirements Recommended null modem cables are as follows 1 BC22D for EMC RFI shielded cabinets Rounded 6 conductor fully shielded cable to FCC specifica
49. ack Modem The word is a contraction of MOdulator DEModulator A modem interfaces a terminal to a transmission line A modem is sometimes called a dataset MSB Most Significant Bit Multiplexer A device which allows a number of inputs to share one common output Null modem A cable which allows two terminals which use modem control signals to be connected together directly It is only possible over short distances OCTART A single IC containing eight UARTs PCB Printed Circuit Board Protocol A set of rules which define the control and flow of data in a communications system PSTN Public Switched Telephone Network Q bus A global term fora specific DIGITAL bus which the address and data are multiplexed RAM Random Access Memory RFI Radio Frequency Interference ROM Read Only Memory Split speed A facility of a data communications channel which can transmit data at a different speed from the received data UART Universal Asynchronous Receiver Transmitter A device which converts between serial and parallel data used for transmission and reception of serial asynchronous data a channel XOFF A control code 23s used to disable a transmitter Special hardware or software is needed for this function XON A control code 21 used to enable a transmitter which has been disabled by an XOFF code D 2 Category Data Address Data Control Interrupt Control DMA Control System Control Power Supplies
50. address 2 3 2 5 B 3 26 1 9 1 2 3 25 3 26 3 39 1 2 C 8 4 5 Xon 1 2 3 25 3 26 3 39 1 C 2 C 8 4 C 5 INDEX 2
51. al Description The 11 option is a serial line interface which provides eight full duplex serial data channels on Q bus systems The DHQ11 option consists of a single Q bus module and one of two groups of cabinet kits depending on the communication standard supported The cabinet kits contain the cabinet bulkhead panels and connecting cables The main application of the is for interactive terminal handling it can also be used for data concentration and real time processing It has two programming modes 11 and DHUII The register sets in these modes are compatible with those of the DHV11 and DHU11 respectively The preferred mode of operation is DHU11 mode The main features of the DHQ11 are Eight full duplex asynchronous data channels For transmission DMA transfers or for each line program transfers to a l character transmit buffer in DHV11 mode or to a 64 character transmit FIFO in DHU11 mode For receive a 256 entry FIFO buffer for received characters dataset status changes and diagnostic information It supports EIA 232 D V 28 or DEC423 with the appropriate cabinet kit NOTE DEC423 is a term used in this manual to indicate a data leads only implementation of the RS 423 A electrical standard DEC423 uses MMJ connectors instead of the 37 way connectors specified by RS 449 It is compatible with all DIGITAL DHV11 and DHU11 device drivers Itcan auto answer on a switched line The transmit
52. and XOFF characters will always be reported through the receive FIFO unless the DISAB XRPT bit is set It is possible during read modify write operations by the program for the DHQI11 to change the TX ENA bit between the read and the write actions For this reason if DMA transfers are started while is set it is advisable to write to the low byte of TBUFFAD2 only 3 26 3 3 6 4 DISAB XRPT If DISAB XRPT is clear XON and XOFF characters will be processed as normal characters and are entered into the receive FIFO DISAB XRPT allows the individual line OAUTO bits to control whether XON or XOFF characters received on that channel are discarded When DISAB XRPT is set and OAUTO is set this filtering is enabled NOTES 1 When checking for flow control characters the DHQI11 only checks characters which do not contain transmission errors The parity bit is stripped and the remaining bits are checked for XON 21 and XOFF 23 codes 2 Auto flow control does not absolutely guarantee that overrun errors will not occur These errors may still occur if the transmitting devices do not respond to the XOFF immediately 3 3 7 Error Indication Four bits inform the program of transmission and reception errors TX DMA ERR 5 lt 12 gt PARITY ERR RBUF lt 12 gt FRAME ERR RBUF lt 13 gt OVERRUN ERR RBUF lt 14 gt RBUF 14 12 also identify a diagnostic or modem status code 3 3 8 Modem Contro
53. ata in the receive FIFO It is recommended that the receive character routine continues to read characters from the receive FIFO until DATA VALID is clear 3 24 NOTE The interrupt is dynamic It is raised as RX DATA AVAIL is set after RXIE or as RXIE is set after RX DATA AVAIL If the interrupt routine does not empty the receive FIFO RXIE must be toggled to raise another interrupt In DHU11 mode the interrupt is generated after a delay set by RX TIMER If RXIE not set program must poll RBUF often enough to prevent data loss 3 3 5 Interrupt Control The provides one of two vector addresses during a bus interrupt sequence The receive vector address is the address set up on the vector address switches The transmit vector address is the receive vector address 4 The receive interrupt vector is generated when RXIE is set and a character is placed into an empty receive FIFO RXIE is changed from 0 to 1 and the receive FIFO contains one or more characters NOTE In DHU11 mode an interrupt is generated either immediately or after the delay set by RX TIMER The transmit interrupt vector 15 generated when TXIE is set and TX ACTION becomes set TXIE is changed from 0 to 1 while TX ACTION is set NOTE Up to 16 TX ACTION reports are buffered It is therefore recommended that your program reads the CSR until the TX ACTION bit becomes clear otherwise TX ACTION will be lost At the two vectors
54. bit and then immediately clears it the XOFF code may not be transmitted This is because there is a delay of up to 350 microseconds before the DHQ11 detects the need to send an XOFF If the conditions for sending an XOFF clear before within this time delay no XOFF code will be sent 4 C 3 3 Mixing The Two Types Of Received Data Flow Control To calculate the effect of using the two modes they should be logically ORed together an XON will not be sent until both sources are inactive An XOFF will be sent when FORCE XOFF is set even if FIFO critical mode is active and an XOFF has already been sent on that channel If the receive FIFO critical mode becomes active whilst FORCE XOFF is set then another XOFF is sent in response to the next received character C 5 APPENDIX D GLOSSARY OF TERMS D 1 SCOPE This appendix contains a glossary of terms used in this manual and in other DIGITAL technical manuals in this series The terms are in alphabetical order for easy reference D2 GLOSSARY Asynchronous A method of serial transmission in which data is preceded by a start bit and followed by a stop bit The receiver provides the intermediate timing to identify the data bits Auto answer A facility of a modem or terminal to answer a call automaticallly Auto flow Automatic flow control A method by which the DHQ1I1 controls the flow of data by means of special characters within the data stream Backward channel A channel which transmit
55. cess to the various sequencers 1 13 1 5 4 OCTART Chip This chip contains eight UARTs which perform parallel to serial and serial to parallel data conversions It interfaces with the control chip through eight registers Four are read only and four are write only n index register is used to access individual lines The OCTART chip shares the RAM bus with the control chip and the RAM itself The OCTART chip also includes Receive and transmit control blocks Interrupt logic for interfacing with the control chip A 16 output baud rate generator All necessary line parameter registers Diagnostic loopback logic Modem status multiplexers 1 14 SI I Q BUS BIDIRECTIONAL BUFFERS CONTROL CHIP DATA ADDRESS 2K x8 PUER RAM DMA ARBITRATOR SEQUENCER Vo SEQUENCER LINES SEQUENCER p 0 TO 7 Q BUS INTERFACE MODEM Ie ee ghee CONTROL LATCHES 0 TO 7 SELF TEST SEQUENCERS SWITCHPACKS AND SHIFT REGISTERS Figure 1 5 DHQII Functional Block Diagram LINE BUFFERS LINE DATA AND MODEM SIGNALS OUT 8 CHANNELS LINE DATA AND MODEM SIGNALS IN RE3222 2 INSTALLATION 2 1 SCOPE This chapter describes the preparation and installation of the DHQ11 option It contains the following sections Unpacking Preparation Installation Testing 22 UNPACKING AND INSPECTION If ordered as part of a system
56. cm 21 INCHES BCOSL 03 92cm 36 INCHES RE3201 Figure 1 4 DHQl1 Connections DEC423 1 3 SPECIFICATIONS 1 3 1 Environmental Conditions The following environmental constraints for storage and operation apply to the DHQII The storage temperature must be within the range 40 degrees C to 66 degrees 40 degrees F to 151 degrees The operating temperature must be within the range 5 degrees C to 60 degrees C 41 degrees to 140 degrees F When operating the relative humidity must be within the range 10 percent to 95 percent non condensing at a maximum wet bulb temperature of 32 degrees C and a minimum dew point of 2 degrees C DIGITAL normally defines the operating temperature range for a system as 5 degrees C to 50 degrees C 41 degrees F to 122 degrees F the 10 degrees C difference between the upper limits quoted allows for the temperature gradient within the system box 1 8 The maximum operating temperatures must derated by 1 8 degrees C 1000 m above sea level 1 degree F 1000 ft for operation at high altitude sites 1 3 2 Electrica Requirements needs the following electrical supplies EIA 232 D options 5 volts dc plus or minus 5 percent at 1 7 A maximum current 1 4 typical For DEC423 options 5 volts dc plus or minus 5 percent at 2 2 A maximum current 1 9 A typical For EIA 232 D and DEC423 options 12 volts dc plus or minus 5 percent at 300 mA maxim
57. ction to the terminal or with the terminal itself 5 Rectify the cable or terminal fault if there is one If not make sure that the user diagnostics for the module run correctly 6 the problem cannot be solved call DIGITAL Field Service H3101 LOOPBACK CONNECTOR Li BC16C XX TO TERMINALS RE3206 Figure 4 1 Troubleshooting DEC423 Installations 4 4 INTERNAL DIAGNOSTICS Internal diagnostics run without intervention from the operator There are two tests the self test and the background monitor program BMP 4 4 1 Self Test The self test starts immediately after the Q bus or module has been reset It performs a comprehensive internal logic test but does not test the Q bus interface The DIAG FAIL bit and the diagnostics passed LED on the module give an indication of a successful self test The self test also reports error or status information to the host via the receive FIFO The self test has completed successfully if the LED is on 1 7 seconds after the self test has been initiated The self test is started by setting the MASTER RESET bit in the CSR either by resetting the module through the program interface or by a Q bus initialisation sequence The LED is turned off when the self test starts and the test completes after 30ms The self test then finishes in one of three ways If skip self test was used the LED turns on and the MASTER RESET is cleared 4 2 Ifthe board is in DHV11 mode the LED
58. e DHQ11 module are functioning correctly 2 12 1 Switch on the system 2 gt After 2 seconds check that the green self test LED on the DHQ11 module is on If it does not come on call DIGITAL Field Service 3 Boot the Micro 11 Customer Diagnostic media Refer to your MicroPDP 11 System Manual for further information 4 Type T at the main menu to allow the diagnostics to identify the new module and add it to the configuration file NOTE Look at the list of devices displayed and make sure that the new module is included If it is not included repeat the installation sequence and make sure that the module switches have been set correctly 5 at the main menu to run the system tests These should complete without error if an error occurs call DIGITAL Field Service A MicroPDP 11 Maintenance Kit is available and may be ordered from your local DIGITAL office This kit allows traiued personnel to run individual diagnostic programs under the XXDP diagnostic monitor and to configure and run DECX11 system test programs The XXDP functional diagnostic is VHQA BIN and the DECX11 module is XDHV OBJ 2 7 2 Testing In MicroVAX II Systems To verify that the MicroVAX II system and the DHQ11 module are functioning correctly 1 Check that the green self test LED on the DHQ11 module is on 2 Bootthe MicroVAX Maintenance System media Refer to your MicroVAX II System Manual for further information 3 Ty
59. e Programming 3 28 Diagnostic Codes Dio VADE 3 28 Self Test Diagnostic Codes 3 28 Interpretation Of Self Test Codes 3 28 Skipping Sells IESE ae en 3 29 Background Monitor Program BMP 3 30 PROGRAMMING EXAMPLES 3 31 Resettne The 5 y RIS SR 3 31 ELO M aei ane 3 32 Transmitting Ee RE ES servi ews cane ees 3 33 Single Character Programmed Transfer DHUI1 Mode 3 33 Single Character Programmed Transfer DHV11 Mode 3 34 DMA Iranstere s 2 20 Uie duda edad 3 35 Aborting A Transmission 3 36 asit p 3 37 Auto XON And XOFF 525555 UE RR Base AS EA 3 39 Checking Diagnostic Codes 3 41 TROUBLESHOOTING SCOPE e au and arn as 4 1 PREVENTIVE MAINTENANCE 2 uem E E 4 1 TROUBLESHOOTING PROCEDURES 4 1 INTERNAL DIAGNOSTICS Psi tains Dig ape 4 2 Self Test rr 4 2 Background Monitor Program BMP
60. e are international standards which telephone network applications should obey There are no hardware interlocks between the modem control logic and the transmitter and receiver logic Program control manages these actions as necessary A subset of the leads listed in Table A 1 could be used to establish a communications link using modems connected to the switched telephone network Ring Indicator RI Data Terminal Ready DTR and Data Carrier Detected DCD are the absolute minimum requirements In some countries Dataset Ready DSR is also needed It is usually desirable however to implement modem control protocols which will operate over most telephone systems in the world Also some protection should be included to guard against network faults particularly in applications such as dial up timesharing systems Such faults include Making a channel permanently busy hung because of a misdialed connection from a non data station Connecting a new incoming call on an in use channel This fault might occur for example after a temporary carrier loss if the host system assumed that the carrier was reasserted by the original caller Modem control with some protection against common faults and which is compatible with the telephone networks in most geographic areas can be implemented by using all the signals listed in Table A 1 in the way described by the CCITT V 24 recommendations Section 2 1 describes a method of implementing a
61. e gives the sequence of addresses for both UNIBUS and Q bus options For example the address sequences could be DJ11 DH11 DUI11 DUVI1 and so on Having one list allows us to use one set of configuration rules and one configuration program Table B 1 Floating Device Address Assignments Rank Device Size Modulus Address Decimal Octal 1 DJ11 gap 4 10 17760010 2 DH11 gap 8 20 17760020 3 gap 4 10 17760030 4 DU11 DUVII gap 4 10 17760040 5 DUP11 gap 4 10 17760050 6 LKIIA gap 4 10 17760060 7 DMC11 DMRI11 gap 4 10 17760070 8 DZ11 DZV11 DZS11 DZ32 4 10 17760100 gap 9 11 gap 4 10 17760110 10 LPP11 gap 4 10 17760120 11 2 gap 4 10 17760130 12 VMV31 gap 8 20 17760140 13 DWR70 gap 4 10 17760150 14 RL11 RLV11 gap 4 10 17760160 15 LPA11 K gap 8 20 17760200 16 KWI11 C gap 4 10 17760210 17 VSV21 gap 4 10 17760220 18 RX11 RX211 RXV11 RXV21 4 10 17760230 gap B 1 Rank 19 20 21 22 23 24 25 26 27 28 29 30 3l 32 Table B 1 Floating Device Address Assignments Cont Device Size Modulus Address Decimal Octal DRI11 W gap 4 10 17760240 DR11 B gap 4 10 17760250 DMPI1 gap 4 10 17760260 DPV11 gap 4 10 17760270 ISB11 gap 4 10 17760300 DMV11 gap 8 20 17760320 DEUNA gap 4 10 17760330 KDASO UDASO RQDX3 gap 2 4 17760334 DMF32 gap 16 40 17760340 511 gap 6 20 17760360 VS100 gap 8 20 17760400 81 gap 2 4 17760404 11 gap 8 20 17760420 DHVII DHUII DHQll1gap 8 20 1
62. e host can set bits 7 and 6 of LNCTRL to allow each channel to be configured in normai automatic echo local loopback and remote loopback modes These modes allow an individual data channel to be looped back to the host or to be looped back to the terminal to assist in isolating communication problems The host must provide suitable software to use these modes 3 3 10 Diagnostic Codes 3 3 10 1 Self Test Diagnostic Codes After bus reset or master reset the DHQ11 executes a self test and initialization sequence During the sequence eight diagnostic codes are put in the receive FIFO and RX DATA AVAIL is set After an error free test DIAG FAIL will be reset and the diagnostic passed LED will be on If an error is detected DIAG FAIL will be set and the LED will be off 3 3 10 2 Interpretation Of Self Test Codes The high byte of diagnostic codes in RBUF can be interpreted as in Section 3 2 2 2 except that bits lt 11 8 gt are not the line number They indicate the sequence of the diagnostic byte that is to say 0 first byte 1 second byte and so on Table 3 3 shows the meaning of each of the error codes Table 3 4 DHQI11 Self Test Error Codes bits 27 0 gt 201 Self test null code used as a filler 203 Self test skipped 211 OCTART error 225 RAM error 231 RTS CTS DCD error 235 DTR RI DSR error All other codes should be treated as an undefined error
63. ed by MASTER RESET 6 EVEN PARITY If LPR 5 is set this bit defines the type of parity Even Parity R W 1 Even parity Odd parity The bit is cleared MASTER RESET 5 PARITY ENAB This bit causes a parity bit to be generated on transmit Parity Enable R W and checked and stripped on receive 1 0 Parity enabled Parity disabled The bit is cleared by MASTER RESET 3 10 Name Description 43 CHAR LGTH These two bits define the length of characters The Character Length R W length does not include start stop and parity bits 00 5 bits 01 6 bits 10 7 bits 11 8 bits They are set to 11 by MASTER RESET 2 1 DIAG Diagnostic control codes are are used by the host as Diagnostic Code R W follows 00 Normal operation 01 Causes the background monitor program BMP to report the DHQ11 status through the receive FIFO Other codes are reserved lt 0 gt DISAB XRPT 0 XON and XOFF characters are reported on Disable XON XOFF all channels Reporting R W 1 If LNCTRL lt 4 gt also set for a particular channel these characters are filtered from the received data stream to relieve the host of the need to do so On initialization this bit 15 cleared In order to read or write to this bit CSR lt 3 07 must equal zero An XON code 21 DC CTRL Q An XOFF code 23 DC3 CTRL S No other codes are specified for the interface Table 3 3 Data Rates
64. ed transfers Characters can also be transferred by DMA Reception Received characters are deserialized by the OCTART and transferred to a four character area in the RAM one such area per line by the control chips OCTART sequencer following an interrupt from the OCTART The control chip s OCTART sequencer later removes characters from the bottom of the 4 character FIFO and places them in the 256 x 16 receive FIFO which can be read by the host Modem Control The modem control latches are external to the control chip Data is written to the latches from RAM by the OCTART interface sequencer The sequencer also samples modem status lines every 10 milliseconds and reports on changes via the STAT register and also via the receive FIFO if programmed to do so 1 5 3 Control Chip The control chip contains the following functional blocks Q bus Interface Matches addresses generates vector addresses and handles interrupts It also interfaces the Q bus signals to other functional blocks Data I O Sequencer Controls host access to device registers OCTART Sequencers Transfers data between the OCTART and RAM and handles flow control Self Test Power Up Sequencer This section powers up the module to a fixed set of initial conditions such as 9600 baud rate on all lines it also handles self test DMA Sequencer Initiates and manages all DMA data transfers to the module RAM Arbitrator Provides RAM and OCTART bus ac
65. er message 3 3 3 3 Programmed I O DHU11 Mode Before writing a character or sequence of characters to the FIFODATA register the program should read the FIFOSIZE register to check that there is space in the transmit FIFO If there is enough space characters can be written as bytes one character or words two characters to FIFODATA After a low byte write FIFODATA 7 0 is transferred to the FIFO After word write FIFODATA c 7 02 is transferred to the FIFO followed FIFODATA 15 0 High byte writes to FIFODATA are not allowed The DHQ11 returns TX ACTION when the transmit FIFO becomes empty An interrupt will also be generated if TXIE is set As distinct from DMA mode in programmed I O mode TX ACTION is returned when the DHQ11 transfers the last character from the transmit FIFO to the OCTART not when it has been transmitted Thus if line parameters are changed immediately after the last TX ACTION of a message the end of the message could be lost The program can avoid this loss by adding two null characters to the end of each programmed transfer FIFO message 3 3 4 Receiving Received characters tagged with the channel number error information and DATA VALID are placed in the receive FIFO RX DATA AVAIL is clear when the receive FIFO is empty When a character is put into the empty receive FIFO the DHQ11 sets RX DATA AVAIL A receive interrupt is generated if RXIE is set RX DATA AVAIL stays set while there is valid d
66. est being acknowledged OR there is a host memory parity error The and TBUFFADJO registers will contain the address of the memory location at which the error occurred TBUFFCT will be cleared If TX ACTION is set these bits hold the line number to which TX ACTION refers When set this bit indicates that a received character is available It 15 clear when the receive FIFO 15 empty It is used with RXIE to request a receive interrupt It is set after MASTER RESET because the receive FIFO contains diagnostic information When set this bit allows the DHQ11 to interrupt the host when RX DATA AVAIL is set An interrupt is generated under the following conditions 1 RXIE is set and a character is placed into empty receive FIFO 2 The receive FIFO contains one or more characters and RXIE is changed from 0 to It is cleared by BINIT but not by MASTER RESET This bit is set by the host to reset the module It stays set while the DHQ11 runs the self test and performs an initialization sequence The bit is then cleared to tell the host that the process is complete 3 5 Description This bit can be set directly by the host or indirectly by BINIT bus initialization signal 4 SKIP Skip Self Test In DHU11 mode this bit is used RW to shorten the reset initialization time to about 30 milliseconds The host program must only set this bit at the same time as it sets MASTER RESET It
67. f 300 octal Switches 1 and 2 are used during manufacture SW 1 must be set ON closed and SW 2 must be set OFF open for correct operation of the DHQII MANUFACTURING TEST SWITCHES SW1 MUST BE ON CLOSED SW2 MUST BE OFF OPEN PART OF SWITCHPACK E11 LEGEND SWITCH OFF BINARY O OPEN SWITCH ON BINARY 1 CLOSED INTERPRETED AS ALL ZEROES 1 SEE NOTE BIT NO VECTOR 0 0 ADDRESS NOTE USE THE BLANK ROW TO PENCIL IN THE ADDRESS PATTERN YOU NEED on Jo o o7 06 os VECTOR ADDRESS SELECTION PART OF SWITCHPACK E11 3 4 5 6 7 8 EXAMPLE SETTING 300 I 1 DECODED BY DEVICE 0 0 BOTH GROUPS IDENTICAL mg wu RE3224 Figure 2 3 Setting the Vector Address 2 3 4 DHV11 Or DHU11 Programming Mode Selection The DHQ11 offers two separate program interfaces DHV11 mode DHU11 mode Select the mode appropriate to the device driver within the system by setting switch 1 of the on board switchpack E19 see Figures 2 1 and 2 2 Modules prior to revision have a jumper installed W1 which locks the module in DHV11 mode See figure 2 1 for the position of the jumper Remove W1 to enable selection of DHV11 or DHU11 mode by the switch NOTE DHUI11 programming mode generally gives better performance because of reduced CPU overhead in transferring characters to and f
68. full duplex auto answer communications link through modems over the PSTN It is provided here only to show the operation and interaction of DHQ11 modem control leads in a typical application 2 1 Example Of Auto Answer Modem Control For The PSTN The system operator determines which DHQ11 channels should be configured for either local or remote operation Local operation implies control of data leads only while remote operation implies that modem control will be supported The host software will assert and RTS together with the bit the LNCTRL register for all DHQ11 channels configured for remote operation DTR informs the modem that the DHQ11 is powered up and ready to acknowledge control signals from A 2 the modem RTS is asserted for full duplex mode of operation and causes modem to place its carrier on the telephone line when the modem answers call Link Type LNCTRL 87 enables modem status information to be placed in the receive character FIFO where it will be handled by an interrupt service routine Modem status changes are always reported in the STAT register regardless of the state of LNCTRL lt 8 gt The modem is now prepared to auto answer an incoming call Dialing modem s number causes RI to be asserted at the line interface This informs DHQ11 that a new call is being received RI has to be in a stable state for at least 30 ms or the change will not be reported by the DHQ11
69. he DHQ11 has two on board switchpacks to select the following functions Switchpack 19 10 position Switch 1 selects DHV11 programming mode when closed or DHU11 programming mode when open Switches 2 to 10 select the device address Switchpack E 11 8 position Switch 1 enables the on board oscillator This is a manufacturing test switch and is closed for normal operation Switch 2 selects manufacturing self test mode This is a manufacturing test switch and is open for normal operation Switches 3 to 8 select the device vector address Chapter 2 gives further information about these switchpacks 1 2 2 2 Communications Standard The serial drivers the M3107 module are compatible with EIA 232 D However the CK DHQ11 W cabinet kits provide level conversion for DEC423 FUSE J1 CONNECTOR CHANNELS 0 3 OCTART CONTROL CHIP ADDRESS VECTOR 10 POSITION 8 POSITION SWITCHPACK SWITCHPACK RE3200 Figure 1 1 Layout of the DHQ11 Module 1 2 3 Versions Of DHQ11 The option consists of the M3107 Q bus module and the User Guide It can be used with one of six cabinet kits The choice of kit depends on the type of system cabinet and on whether a EIA 232 D or a DEC423 communication interface is needed The cabinet kits available for use with the 11 are 1 4 EIA 232 D CK DHQII AA for BA123 BA11 M boxes CK DHQII AB for BA23 bo
70. hese two standards are compatible with each other This manual uses EIA 232 D The RS 232 C CCITT V 28 standard was originally designed to specify the connection between a local interface and a modem It was not intended to be used for connecting to terminals over long distances The maximum specified cable length is 50 feet 15 metres Shielded cable must be used in order to meet the requirements of FCC and VDE Radio Frequency Interference RFT regulations Although cable lengths greater than 50 feet can be used with reasonable success cable capacitance noise and ground potential difference restrict the line speed as the distances increase Consequently the performance of long distance communications to a terminal using EIA 232 D often does not meet today s requirements for terminal wiring DEC423 is data leads only implementation of the RS 423 A CCITT V 10 standard RS 423 A has a different grounding and signal return path arrangement from EIA 232 D DEC423 uses line driver and receiver chips which have better filtering and tighter level tolerances than those specified by RS 423 A In addition DEC423 devices include transient suppressors for electrical overstress EOS and electrostatic discharge ESD protection DEC423 devices may also be connected with unshielded cable The features provided by DEC423 devices are reliable data communication over increased distances typically 1000 feet 300 metres at 9600 baud See Table 1 2 for maxim
71. hold a normal character The line number RBUF 11 87 0 BMP normally only reports when it finds an error However the program can get a BMP report at any time to check the DHQ11 This is done by setting DIAG LPR lt 2 1 gt of any channel to 01 The line number returned is that of the LPR used to request the report On completing the check BMP clears this 01 code The host should not write to the LPR of that channel until LPR lt 2 1 gt becomes 00 34 PROGRAMMING EXAMPLES These programs are not presented as the only way of driving the option and are neither guaranteed nor supported 3 4 1 Resetting The DHQ11 In the following example DIAGC isa routine to check the diagnostic codes It returns with CARRY set if it detects an error code The loop at 1 takes 1 2 seconds so the programmer could poll through a timer or poll at interrupt level zero ROUTINE TO RESET THE 0 011 AND CHECK THAT IT IS FUNCTIONING CORRECTLY DHORES MOV 40 DHOCSR SET MASTER RESET AND CLEAR INTERRUPT ENABLES 1 BIT 40 DHQCSR WAIT FOR MASTER RESET TO BNE 1 CLEAR BIT 520000 DHOCSR CHECK THE DIAGNOSTICS BNE DIAGER FAIL BIT NOTE TEST INSTRUCTION IS BECAUSE THERE ARE TRANSMIT ACTS PENDING MOV 8 R5 SET UP A COUNT 2 MOV SRBUFF RO GET NEXT DIAGNOSTIC CODE JSR PC DIAG PROCESS IT BCS DIAGER CARRY SET MUST HAVE BEEN ERROR 508 5 25 60 BA
72. l Each channel of the module provides modem control bits for RTS and DTR Also on each channel are modem status inputs CTS DSR RI and DCD See Section 3 2 2 6 for a description of each of these signals CTS DSR and DCD are sampled every 10 ms Therefore for a change to be detected these bits must stay steady for at least 10 ms RIis also sampled every 10 ms but a change is not reported unless the new state is held for three consecutive samples Modem signals must be coordinated under program control there is no hardware modem control logic Modem status change reports are placed in the receive FIFO only if LINK TYPE is set but any changes are updated in STAT irrespective of the state of LINK TYPE Appendix A gives more details of modem control By clearing LINK TYPE a channel is selected as a data lines only channel Modem control and status bits can still be managed by the program but status bits must be polled at the line status register Changes of modem status will not be reported to the program 3 27 Status change reporting is done through receive FIFO as follows When OVERRUN ERR FRAME ERR and PARITY ERR are all set the eight low order bits contain either status change or diagnostic information In this case If RBUF lt 0 gt 0 RBUF 7 1 holds STAT 15 9 see Section 3 2 2 6 If RBUF lt 0 gt I RBUF 7 1 holds diagnostic information see Section 3 3 10 3 3 9 Maintenance Programming Th
73. must then clear the bit but must wait at least 20 microseconds before doing so It is recommended that the host always set SKIP when setting MASTER RESET DHQ11 will execute the full self test regardless of whether SKIP is set or not The 1 7 seconds delay during MASTER RESET is purely for DHU11 hardware compatibility In DHV11 mode this bit is ignored for compatibility reasons 3 0 IND ADDR REG For indexed registers these bits select one of sixteen Indirect Address Register channels However on the DHQ11 only the lower R W eight channels are defined So when writing these bits CSR lt 3 gt must be zero 3 2 2 2 Receive Buffer RBUF A read from base 2 is interpreted by the 1 hardware as a read from the receive FIFO Therefore RBUF is a 256 character register with a 1 word address The least significant bit LSB of the character is in bit 0 RBUF READ BASE 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALID ERROR LINE NUMBER QR DATA SET FROM HIGH BYTE OVERRUN PARITY STATUS FLAGS OF STAT ERROR ERROR oR DIAGNOSTIC INFO 3 6 14 11 8 gt lt 7 0 gt Name DATA VALID Data Valid R OVERRUN ERR Overrun Error R Description This bit is set if there is data in the receive FIFO When this bit is clear the contents of RBUF lt 14 0 gt is not valid After self test diagnos
74. nd the transmit data line to the terminal is held in the mark condition The data rate selected for the transmitter is used for both transmission and reception The TX ENA bit still controls transmission in this mode The RX ENA bit is ignored Remote loopback In this mode data received from the terminal is looped back to the terminal at a clock rate equal to the received clock rate The data is not placed in the receive FIFO The state of TX ENA is ignored The RX ENA bit must be set on this channel 3 16 FORCE XOFF Force XOFF R W OAUTO Outgoing Auto Flow R W BREAK Break Control R W Description This bit can be set by the program to indicate that this channel is congested at the host system for example if the typeahead buffer is full When it sees this bit set the DHQ11 will send an XOFF code Until the bit is cleared XOFFs will be sent after every alternate character received on this channel When the bit is cleared an XON will be sent unless IAUTO is set and the receive FIFO is critical This bit is the auto flow control bit for outgoing characters When set if RX ENA is also set the DHQ11 will automatically respond to XON and XOFF codes received from a channel The DHQ11 uses the TX ENA bit in TBUFFAD2 to stop and start the flow If DISAB XRPT is also set XON XOFF codes are not entered in the receive FIFO If set this bit forces the transmitter of this channel to the
75. not have to be disconnected from the DHQ11 during the tests See Chapter 2 for more details 47 FIELD REPLACEABLE UNITS FRUs The are Reference No Item M3107 Dual height DHQ11 module BCOSL xx Flat cable 40 conductor For EIA 232 D Installations H3173 A Distribution panel For DEC423 Installations H3100 Active distribution panel 16 25 Multiway cable H3104 Cable concentrator 70 22775 Power cable 4 5 APPENDIX A MODEM CONTROL SCOPE This appendix contains information useful to both the programmer and the engineer It defines control signals describes typical modem control methods and warns against likely network faults A detailed example of auto answer operation is included 2 MODEM CONTROL The DHQ11 supports sufficient modem control to permit full duplex operation over the public switched telephone network PSTN and over private telephone lines Table A 1 lists the control leads supported by the DHQ11 together with an explanation of their use and purpose In this appendix the terms modem and dataset have the same meaning They refer to the device which is used to modulate and demodulate the signals transmitted over the communications circuits Table A 1 Modem Control Leads Name EIA 232 D 24 25 Pin Definition GND AB 102 7 Signal Ground This is a reference level for the data and control signals used at the line interface TXD BA 103 2 From DHQl1 to modem This signal contains the
76. ns 2 9 3 Full Modem Cables Recommended full modem cables are as follows l BC22F for EMC RFI shielded cabinets Rounded 25 conductor fully shielded cable Subminiature 25 pin D type female connector on one end male connector the other Lengths available BC22F 10 3 1 m 10 ft BC22F 25 7 6 m 25 ft BC22F 35 10 7 m 35 ft BC22F 50 15 2 m 50 ft BC22F 75 22 9 m 75 ft 2 BCOSD e Round 25 conductor cable Subminiature 25 pin D type female connector on one end male connector on the other 2 19 Lengths available BCOSD 10 3 1m 10 ft BCOSD 25 76m 25 ft 05 50 152m 50 ft 050 60 186m 60 050 0 30 5m 100 In some countries protective hardware may be needed when connecting to certain lines Refer to the national regulations before making a connection 2 10 CABLES AND CONNECTORS DEC423 The H3100 active distribution panel adapts the the two DHQI11 Berg connectors to one 36 way AMP connector Noise filtering is provided on each pin of the connector This reduces electromagnetic radiation from the cables and also provides the logic with some protection against static discharge Table 2 3 shows connections to the 36 pin AMP filtered connectors used on DHQI1 with DEC423 installations Table 2 3 Serial Line Connections for the 36 Pin Connector 1 Blu Wht Line 0 Transmit 19 Wht Blu Line 0 Transmit 2 Org Wht Line 0 Receive 20 Wht Org Line 0 Receive 3
77. of the self test is provided to the host system through the receive FIFO buffer A green LED indicates GO NO GO status for the device More details are given in Section 4 3 1 2 1 3 Diagnostic Programs A full range of diagnostic programs is available These run under the MicroPDP 11 diagnostic supervisor or MicroVAX II maintenance system Loopback test connectors are not needed when running the user mode diagnostics Service mode diagnostics and loopback connectors are available from DIGITAL 1 2 1 4 Preventing Data Loss The DHQ11 can be programmed for automatic and XOFF operation to prevent the loss of data at high throughput The reporting of received XON XOFF characters to the software driver can be enabled or disabled 1 2 2 Physical Description The DHQ11 is an M3107 dual height Q bus module It is 21 6 cm 8 51 inches long and 13 2 cm 5 19 inches wide Figure 1 1 shows the layout Connectors A and B are for the Q bus while connectors J1 and J2 interface to the communications lines via BCOSL xx cables and distribution panels Two distribution panels are supplied with an EIA 232 D option and a single panel is supplied with a DEC423 option Connector 73 provides power to the active distribution panel supplied with DEC423 options This connector is not used with EIA 232 D options Mixed use that is one EIA 232 D and one DEC423 panel connected to a single module is not supported by DIGITAL 1 2 1 2 2 1 On Board Switchpacks T
78. pe 2 at the main menu to show the system configuration and devices NOTE Look at the list of devices displayed and make sure that the new module is included If it is not included repeat the installation sequence and make sure that the module switches have been set correctly 4 Type l atthe main menu to run the system tests These should complete without error if an error occurs call DIGITAL Field Service 2 8 H3101 LOOPBACK CONNECTOR The H3101 loopback connector see Figure 2 9 is used during diagnostic tests for DEC423 installations Itis two loopback connectors in one package and consists of a female 36 way loopback connector and a male 36 way loopback connector It can be inserted into the cabling at the distribution panel or at the cable concentrator To test the cables type characters at the keyboard and make sure that they are echoed to the screen refer to Chapter 4 2 13 MALE CONNECTOR LINE O LINE 1 LINE 2 LINE 3 LINE 4 LINE 5 LINE 6 LINE 7 LINE O LINE 1 LINE 2 LINE 3 LINE 4 LINE 5 LINE 6 LINE 7 Rx Rx Rx Tx NOT USED NOT USED Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Rx NOT USED NOT USED 1 Tx 3 1 al 5 e es 7 8
79. plied to the following rank If extra devices are added to a system the floating addresses may have to be reassigned in agreement with these rules B 2 FLOATING VECTORS Each device needs two 16 bit locations for each vector For example a device with one receive and one transmit vector needs four words of vector space The vector assignment rules are as follows 1 Each device occupies vector address space equal to Size words For example the DLV11 J occupies 16 words of vector space If its vector were 300 the next available vector would be at 3403 2 There are no gaps except those needed to align an octal modulus Table B 2 Floating Vector Address Assignments Rank Device Size Modulus Decimal Octal 1 4 10 1 TUS8 4 10 2 KL11 4 10 2 DL11 A 4 10 2 DL11 B 4 10 2 DLV11 J 16 10 2 DLV11 DLV11 F 4 10 3 11 4 10 4 DM11 A 4 10 5 2 4 6 DM11 BB BA 2 4 7 DH11 modem control 2 4 8 1 DRVII B 4 10 9 DR11 C DRVI 4 10 10 PA611 reader punch 8 10 11 LPD11 4 10 12 DT07 4 10 13 4 10 14 DL11 C to 4 10 15 DJ11 4 10 16 4 10 17 VT40 8 10 17 VSV11 8 10 18 LPS11 12 10 B 3 Table B 2 Floating Vector Address Assignments Cont Rank Device Size Modulus Decimal Octal 19 4 10 20 KWI11 W KWVI11 4 10 21 DU11 DUVI11 4 10 22 DUPII 4 10 23 modem control 6 10 24 LK11 A 4 10 25 DWUN 4 10 26 DMCII DMR1I 4 10 27
80. quest priorities first and then consider interrupt bus requests 2 5 1 DMA Request Priority DMA request priority is usually assigned according to throughput Faster devices higher throughput usually have priority over slower DMA devices for example disk has priority over tape which itself has priority over communications devices This is because fast devices usually reach overrun or underrun conditions sooner than slower ones 2 5 2 Interrupt Request Priority The has a fixed interrupt priority level of 4 and cannot be changed to other priority levels It does not monitor any of the higher level interrupt request lines Because of this both the interrupt request and DMA non processor request priorities of the DHOI1 are selected by the position of the DHQ11 on the bus it must therefore be positioned after any device that does monitor any of the request lines Devices closest to the processor module have the highest priority 2 5 3 Recommendations In general the DHQ11 bus position is not critical However it is recommended that you place the module after any mass storage interfaces and high speed synchronous communications options these are more sensitive to bus position 2 6 INSTALLING THE Once you have defined the backplane position for the DHQ11 you can begin to install the DHQ11 module 2 6 1 Installing The M3107 Module WARNING Shut off the system power and disconnect the main system power cord before perfo
81. r 3 20 Name Description After a DMA transfer has been aborted this location wil hold the number of characters stil to be transferred See also the previous NOTE 3 21 33 PROGRAMMING FEATURES 3 3 1 Initialization The is initialized by its on board sequencers Initialization takes place after a bus reset sequence or when the host sets CSR lt 5 gt MASTER RESET Before starting initialization the on board sequencers perform a self test The results of this test are reported by eight diagnostic bytes in the receive FIFO The DHQ11 state after a successful self test is as follows 1 Eight diagnostic codes are placed in the receive FIFO 2 The diagnostic fail bit CSR lt 13 gt is clear 3 All channels are set for a Send and receive 9600 bits s b Eight data bits stop bit d No parity e Parity odd f Auto flow off Receive disabled h Transmit enabled i break on line j No loopback k Link type set to data leads only l DTR and RTS off m DMA character counter zero n DMaA start address registers zero o TX DMA START cleared cleared q Auto flow reports enabled 3 22 The clears the MASTER RESET CSR lt 5 gt when initialization and self test are complete 3 3 2 Configuration After DHQ11 self initialization the driver program can configure the DHQ11 as needed This is done through the LPR and LNCTRL registers The line characteris
82. ransmitted the last character of the DMA buffer abort a DMA transfer program must set TX ABORT The DHQ11 will stop transmission and update TBUFFCT TBUFFADI and TBUFFAD2 7 0 gt to reflect the number of characters which have been transmitted TX DMA START will be cleared If TXIE is set TX ACTION will interrupt the program at the transmit vector If the program clears TX ABORT and sets TX DMA START the transfer can be continued without loss of characters If a DMA transfer fails because of a host memory error the transmission will be terminated TBUFFADI and TBUFFAD2 will point to the failing location TBUFFCT will be cleared 3 3 3 2 Programmed I O DHV11 Mode Single characters are transferred through the channel TX CHAR register The character and the DATA VALID bit must be written as defined in Section 3 2 2 3 Note that the character and the DATA VALID bit can be written by separate MOVB instructions When the DHQ11 removes the character from TX CHAR it returns TX ACTION This will generate an interrupt if TXIE is set NOTE In single character mode TX ACTION is returned when the DHQ11 accepts the character not when it has been transmitted Each channel can buffer up to three characters Therefore if line parameters are changed immediately after the last TX ACTION of a message the end of the message could be lost unless three null characters are added to the end of each single character programmed transf
83. red if the host reads the CSR after the TX ACTION FIFO has become empty To avoid losing TX ACTION reports the host must not let more than 16 reports accumulate It is advisable to read the CSR until TX ACTION becomes clear NOTE TX ACTION reports may be lost if the upper byte of the CSR is discarded following a read of the CSR TXIE Transmit Interrupt Enable R W DIAG FAIL Diagnostic Fail R When set this bit allows the DHQ11 to interrupt the host when CSR lt 15 gt TX ACTION becomes set It is cleared by BINIT but not by MASTER RESET When set this bit indicates that the DHQ11 internal diagnostics have detected an error The error may have been detected by the self test sequencer or by the background monitor program BMP 3 4 12 lt 11 8 gt TX DMA ERROR Transmit DMA Error R TX LINE Transmit Line Number R RX DATA AVAIL Received Data Available R RXIE Receiver Interrupt Enable R W MASTER RESET Master Reset R W Description This bit is associated with the diagnostic passed LED When it is set the LED will be off When it is cleared the LED will be on The bit is set by MASTER RESET It is cleared after the self test has run successfully Not valid if MASTER RESET is set If this bit is set and TX ACTION 15 also set either the channel indicated by CSR lt 11 8 gt has failed to transfer DMA data within 10 microseconds of the bus requ
84. rming any procedure in this chapter ATTENTION Avant d effectuer l une des proc dures de ce chapitre mettez le syst me hors tension et d branchez le cordon d alimentation VORSICHT Schalten Sie das System ab und ziehen Sie das Netzkabel bevor Sie die in diesem Kapitel beschriebenen Anweisungen ausf hren ATENCION Apague el sistema y desconecte el cable principal de alimentaci n antes de realizar ning n procedimiento de este cap tulo RE2848 Connect the BCOSL cables to J1 and J2 Figure 2 5 for EIA 232 D installations and Figure 2 6 for DEC423 installations show how the parts of the option connect together Install the module in its correct backplane position as previously defined NOTE Be careful not to snag module components on the card guides or adjacent modules Check that bus continuity exists If necessary install bus grant continuity cards Do not connect the cables to the bulkhead panels 2 9 A PRINTED ON 40 PIN BERG CONNECTORS 1 CHANNELS 0703 RED LINE RED LINE TOA TO A 5 gt 5 H3173 A z DISTRIBUTION lt B PANEL a lt g 25 PIN D TYPE RED LINE RED LINE CONNECTORS 198 BCOBL XX CABLE CHANNELS 4 7 NOTE BCO5L O1 30 48 12 INCHES BCOSL 1K 53 34 CM 21 INCHES BCOS5L 03 91 44 CM 36 INCHES RES Figure 2 5 Installing the DHQ11 EIA 232 D o 3100 e L2 1 e c3 70 22775 XX J5 J6
85. roPDP 11 DIAGNOSTICS 4 5 1 User Mode Diagnostics These tests can be used by an untrained operator to verify the basic operation of the option User mode tests do not cause any disruption to data networks or devices to which the DHQ11 may be connected Such networks and devices do not have to be disconnected from the DHQ11 during the tests The MicroPDP 11 system manuals describe how to load and run these diagnostics 4 5 1 1 Running User Mode Tests user mode tests are run by selection from the test menu displayed when the user diagnostics are booted See Chapter 2 for more details A MicroPDP 11 Maintenance Kit is available which allows trained personnel to run individual diagnostic programs under the XXDP diagnostic monitor and to configure and run DECX11 system test programs The XXDP functional diagnostic is VHQA BIN and the DECX11 module is XDHV OBJ 4 6 MicroVAX II DIAGNOSTICS Diagnostics for MicroVAX II systems all run under the MicroVAX Maintenance System MMS The MicroVAX II system manuals describe how to load the MMS into the MicroVAX II and how to run MMS diagnostics All the tests can be run by selection from the test menus displayed when MMS is booted 4 3 4 6 1 User Mode Tests These tests can be used by an untrained operator to verify basic operation of the option User mode tests do not cause any disruption to data networks or devices to which the DHQ11 may be connected Such networks and devices do
86. rom the device The Software Product Description states whether the operating system supports DHU11 programming mode 2 4 BUS CONTINUITY Bus grant continuity jumper cards M9047 are used in vacant backplane slots to provide bus continuity see Figure 2 4 2 6 NOTE To find out the type of backplane on your system consult your system manual Q Q BACKPLANE Q CD BACKPLANE PROCESSOR TERMINATOR RE3202 Figure 2 4 Bus Grant Continuity 2 4 4 Bus Grant Continuity Jumpers Backplanes suitable for DHQI11 fall into two groups Q CD Q bus on A and B connectors user defined signals on C and D Q Q Q bus on A and B and C and D connectors In Q CD backplanes bus grant signals pass through each installed module via the A and C connectors of each bus slot Q Q backplanes are designed so that two dual height options can be installed in a quad height bus slot The Q bus lines are routed as follows 1 AB first slot 2 first slot 3 CD second slot 4 AB second slot and so on Each dual height module extends the continuity of the bus grant signals BIAK and BDMG to the next module Therefore with a Q Q backplane if a quad module DHV11 is replaced with a dual module DHQ11 a Q bus grant continuity card M9047 is needed for the vacant slot 2 5 PRIORITY SELECTION The bus backplane position may be a compromise between DMA and interrupt priority requirements As a general rule consider DMA re
87. rough several Q bus addressable registers Command words or bytes written to the registers are interpreted and executed by the module Status reports and data are also transferred through the registers 3 2 1 Register Access The DHQl1 registers occupy 8 words 16 bytes of Q bus memory mapped I O space The base physical address of the eight DHQ11 registers is selected by using switches on the module The address selected is in the peripheral I O space The term base means the lowest I O address on the module that is to say when the four low order address bits 0 Table 3 1 and 3 2 list the DHQ11 registers and their addresses in DHV11 and DHU11 mode The suffix 1 means that there are eight of these registers one for each channel When 1 register is accessed the contents of CSR lt 3 0 select which of the eight registers at that address is actually accessed NOTE CSR lt 3 0 gt allows up to 16 channels to be addressed However only the lower eight channels are used Therefore CSR bit 3 must always be 0 3 1 Table 3 1 DHQ11 Registers in DHV11 Mode Register Address Type Octal Control and Status Register CSR Base Read Write Receive Buffer RBUF 2 Read Only Transmit Character TXCHAR 2 1 Write Only Line Parameter Register LPR 4 1 Read Write Line Status STAT 6 1 Read Only Line Control LNCTRL 10 1 Read Write Transmit Buffer Address 1 TBUFFAD1
88. s in the opposite direction to the usual data flow Normally used for supervisory or control signals Base address The Q bus address of the first lowest device register CSR BMP Background Monitor Program CCITT Comit Consultatif International de T l phonie et de T l graphie An international standards committee for telephone telegraph and data communications networks Dataset See modem DMA Direct Memory Access A method which allows a bus master to transfer data to or from system memory without using the host CPU Duplex A method of transmitting and receiving on the same channel at the same time EIA Electrical Industries Association An American organization with the same function as the CCTIT FCC Federal Communications Commission American organization which regulates and licenses communications equipment FIFO First In First Out The term describes a register or memory from which the oldest data is removed first Floating address An address assigned to an option which does not have a fixed address allocated The address is dependent on other floating address devices connected to the bus Floating vector An interrupt vector assigned to an option which does not have a fixed vector allocated The vector is dependent on other floating vector devices connected to the bus D 1 FRU Field Replaceable Unit IC Integrated Circuit I O Input Output LSB Least Significant Bit MMJ Modified Modular J
89. serial bit stream to be transmitted to the remote station RXD BB 104 3 From modem to DHQ11 This signal is the serial bit stream received by the modem from the remote station RTS CA 105 4 From DHQll to modem Causes the modem s carrier to be placed on the line CTS CB 106 5 From modem to DHQ11 Indicates that the modem has successfully placed its carrier on the line and that data presented on circuit BA will be transmitted to the communication channel DSR CC 107 6 From modem to DHQ11 Indicates that the modem has completed call establishment functions and is successfully connected to a communications channel Table 1 Modem Control Leads Cont Name EIA 232 D 24 25 Pin Definition DTR CD 108 2 20 From to modem Indicates to the modem that the DHQ11 is powered up and ready to answer an incoming call DCD CF 109 8 From modem to DHQ11 Indicates to DHQI1 that the remote station s carrier signal has been detected and is within appropriate limits RI CE 125 22 From modem to DHQ11 Indicates that a new incoming call is being received by the modem The DHQ11 modem control interface can be used in many applications These include control of serial line printers terminal cluster controllers and industrial I O equipment in addition to the more usual applications in telephone networks The use of the control leads described in Table A 1 is therefore completely dependent on the application although ther
90. set SKIP must be cleared by the host so that the master reset sequence can complete In DHV11 mode this also works in DHU11 mode but the previous method is preferred the following method 15 used 1 The program resets the 11 2 The program waits 10 ms 1 ms after issuing reset and then attempts to write 052525 to any of the control registers except the CSR within the next 4 ms 3 Following self test the DHQ11 hardware checks whether an attempt was made to write the skip code to the registers during the 4 ms window after reset see step 2 above If an attempt was made the MASTER RESET bit is cleared at 30 ms after issuing a reset instead of 1 2 s The 1 2 s reset time was retained for compatibility with the DHV11 NOTE The program must not write to the CSR or to the control registers during the period starting 15 ms after reset and ending when the MASTER RESET bit is cleared Writing during this period could cause a diagnostic fail condition 3 29 3 3 10 4 Background Monitor Program BMP The 11 BMP logic performs background self tests by checking for OCTART interrupts One of two codes is returned to the receive FIFO 1 305 octal DHQI11 running 307 octal DHQI1 defective also LED off A single diagnostic word is returned to the receive FIFO The low byte contains the diagnostic code In the high byte OVERRUN ERR FRAME ERR and PARITY ERR are all set to indicate that bits 7 07 do not
91. smitted data mode of flow control is enabled by setting OAUTO bit 4 of the line control register and is disabled by clearing it The default for this mode is disabled Received flow control characters are processed in the same way as normal characters and are placed into the receive FIFO This is not affected by OAUTO but these characters can be filtered out by setting DISAB XRPT If DISAB XRPT is set you do not need a routine in your software driver to filter flow control characters from the data stream C 3 CONTROL OF RECEIVED DATA Received data flow control is slightly more complicated than transmitted data flow control Therefore the two modes of received data flow control are described separately C 3 1 Flow Control By The Level Of The Receive FIFO Occasionally the program may not be able to empty the receive FIFO as fast as the received data is filling it Because the program does not know how full the receive FIFO is it cannot take action to prevent data loss To overcome this problem the DHQ11 can be programmed on a channel basis When the receive FIFO becomes three quarters full an XOFF is sent to the channels from which data is received XOFF character is then sent in response to every second received character until the receive FIFO level drops below half full An XON character is then transmitted The operation of receive FIFO level flow control is shown in Figure C 2 FIFO CRIT F IAUTO 1 FIFO CRIT F
92. spacing state If this bit is set while a character is being transmitted transmission is completed before break is asserted on the line Transmission 15 re enabled when the bit 15 cleared NOTE If the line is idle there may be a delay of up to 170 microseconds between writing the bit and the channel changing state If a character is already being transmitted by the OCTART the BREAK signal will be transmitted immediately afterwards RX ENA Receiver Enable R W IAUTO Incoming Auto Flow R W If this bit is set this receiver channel is enabled If this bit is cleared when this channel is assembling a character that character is lost The bit is cleared by MASTER RESET This is the auto flow control bit for incoming characters If it is set the will control incoming characters by transmitting XON and XOFF codes Transmit Abort R W Description If the receive FIFO becomes more than three quarters full the DHQ11 will send an XOFF code to that channel and to any other channel which receives a character and has the IAUTO bit set When FIFO becomes less than half ful an XON will be sent to all channels which had previously been sent an XOFF This bit is set by the driver program to halt data transmission If a DMA transfer was in progress the address and count registers TBUFFADI TBUFFAD2 and TBUFFCT will be updated to reflect the number of characters
93. tal 023 and XON octal 021 XOFF stops transmission and XON starts transmission The codes are transmitted in the opposite direction to that of the data they control The has one mode of operation for transmitted data received flow control characters and two modes of operation for received data transmitted flow control characters Each mode can be enabled on a per channel basis Each direction of flow is discussed separately within this appendix C 2 CONTROL OF TRANSMITTED DATA The transmitted data mode of flow control is the simplest of the three flow control modes of the DHQI11 When the DHQ11 receives XOFF character for a particular channel the TX ENA bit for that channel is cleared When this bit is clear the DHQ11 will not transmit any data on that channel however internally generated flow control characters will still be transmitted When an XON character is received the TX ENA bit for that channel is set Figure C 1 illustrates the operation of the transmitted data flow control XON RECEIVED OAUTO 0 OAUTO 1 XOFF RCVD OAUTO 0 OAUTO 0 XOFF RECEIVED 802251 Figure 1 Transmitted Data Flow Control Only characters without transmission errors are checked for XON and XOFF codes The characters have their parity bit stripped before comparison NOTE For the automatic flow control to operate correctly the terminal must also recognize and respond to flow control characters The tran
94. tic information is loaded into the receive FIFO Therefore this bit is always set after a successful master reset sequence This bit is set if one or more previous characters of the channel indicated by bits lt 11 8 gt were lost because of a full receive FIFO NOTE The all 1s code for bits lt 14 12 gt is reserved This code indicates that RBUF lt 7 0 gt holds modem status or diagnostic information FRAME ERR Framing Error R PARITY ERR Parity Error R RX LINE Receive Line Number R RX CHAR Received Character R This bit is set if the first stop bit of the received character was not detected also see RX CHAR This bit is set if this character has a parity error and if parity is enabled for the channel indicated by bits lt 11 8 gt also see These bits hold the binary number of the channel on which the character of RBUF lt 7 0 gt was received or on which a data set change was reported If RBUF lt 14 12 gt 000 these eight bits contain the oldest character in the receive FIFO The character is good If RBUF lt 14 12 gt 001 010 or 011 these eight bits contain the oldest character in the receive FIFO The character is bad If RBUF lt 14 12 gt 111 these eight bits contain diagnostic or modem status information In this case RBUF lt 0 gt has the following meanings 0 1 Modem status in RBUF lt 7 1 gt Diagnostic information in RBUF 7 17 3 7
95. tics for a channel can be set up by writing to the LPR and LNCTRL registers associated with this channel These are Transmit speed Receive speed Number of stop bits Parity type or parity disabled Character length Flow control characteristics Normal or maintenance mode Receiver enable disable Modem or data leads only NOTE If RX ENA is reset while a received character is being assembled that character will be lost 3 3 3 Transmitting Each DHQ11 channel can be set up to transfer the characters by DMA or under program control 3 3 3 1 DMA Transfers Before setting up the transfer of a DMA buffer the program should make sure that TX DMA START is not set TBUFFCT TBUFFADI and TBUFFAD2 should not be written unless TX DMA START is clear Transmission will start when the program sets TX DMA START The size of the DMA buffer and its start address can be written to TBUFFCT TBUFFADI and TBUFFAD2 in any order provided that the TX DMA start bit TCBUFFAD2 7 is not set However TBUFFAD2 contains TX ENA and TX DMA START so itis probably simpler to write 2 last By using byte operations on this register TX ENA and TX DMA START be separated The DHQ11 will perform the transfer and set TX ACTION when it is complete If TXIE is set the program will be interrupted at the transmit vector Otherwise TX ACTION must be polled TX ACTION is not returned until the UART has completely t
96. tion 7 0 RX TIMER The receive interrupt is normally raised when a Receive timer received character is loaded into the previously empty receive FIFO The binary number loaded into RX TIMER modifies this procedure as follows 0 Infinite timeout This timeout will be overridden by the conditions below 1 No timeout The interrupt will be raised immediately 2 to 255 Timer delay in milliseconds The timer is overriden when the receive FIFO becomes three quarters full critical or when a modem status change is written to the FIFO This bit is set to 1 by MASTER RESET 3 2 2 5 Line Parameter Register LPR This register is used to configure its associated channel LPR BASE 4 15 14 13 TRANSMIT STOP PARITY DIAGNOSTIC SPEED CODE ENABLE CODE RECEIVE EVEN CHARACTER DISABLE SPEED PARITY LENGTH XON XOFF REPORTING RE3239 3 9 Name Description lt 1512 gt TX SPEED This bit is set to 1101 by MASTER RESET 9600 Transmitted Data Rate R W bits s It defines the transmit data rate Table 3 2 lt 11 8 gt RX SPEED This bit is set to 1101 by MASTER RESET 9600 Received Data Rate R W bits s It defines the receive data rate Table 3 2 7 STOP CODE This bit defines the length of the transmitted stop bit Stop Code R W n stop bit for 5 6 7 or 8 bit characters 2 stop bits for 6 7 or 8 bit characters or 1 5 stop bits for 5 bit characters The bit is clear
97. tion Subminiature 25 pin D type female connector moulded on each end 3 1m 7 6 m 10 7 m 15 2 m 22 9 m 30 5 m 76 2m 10 ft 25 ft 35 ft 50 ft 75 ft 100 ft 250 ft Round 6 conductor three twisted pairs each pair shielded Cables over 30 5 m 100 ft have a 25 pin subminiature D type female connector at one end The other end is unterminated for passing through the conduit Cables 30 5 m 100 ft and less have a similar connector at each end 7 6 m 30 5 m 76 2m 152 4 m 304 8 m e e Lengths available BC22D 10 BC22D 25 BC22D 35 BC22D 50 BC22D 75 220 0 BC22D B5 BC03M E e e Lengths available BC03M 25 BC03M A0 BC03M B5 BC03M E0 BC03M LO BC22A Round 6 conductor cable e 25 ft 100 ft 250 ft 500 ft 1000 ft Subminiature 25 pin D type female connector moulded at each end 2 18 Lengths available 22 10 3 1m 10 ft BC22A 25 7 6 m 25 ft Cables of groups 1 2 and 3 are all connected as in Figure 2 11 The cables are not polarized They can be connected either way round i PIN PIN NUMBERS NUMBERS 1 o PROTECTIVE GROUND PROTECTIVE GROUND 2 o TRANSMITTED DATA RECEIVED DATA o RECEIVED DATA TRANSMITTED DATA 2 7 o SIGNAL GROUND SIGNAL GROUND o DATA SET READY DATA TERMINAL READY _ 20 20 DATA TERMINAL READY DATA SET READY o6 801150 Figure 2 1 Null Modem Cable Connectio
98. um 230 mA typical An on board switched mode power supply generates a 10 V supply for the serial line drivers 1 3 2 1 Q bus Loads The loads applied to the Q bus 3 2 loads 0 5 dc loads 1 3 3 Performance 1 3 3 1 Data Rates Each channel can be separately programmed to operate at one of 16 speeds in bits s 50 1800 75 2000 110 2400 134 5 4800 150 7200 300 9600 600 19200 1200 38400 NOTE See also Section 1 4 4 Speed and Distance Considerations Chapter 3 contains further information on data rates for EIA 232 D 1 3 3 2 Throughput Each channel is capable of full duplex operation at the maximum data rate The following maximum throughput is obtainable At7 bits per character with 1 start bit 1 stop bit and 1 parity bit the throughput is 61440 characters per second 5 bits per character with 1 start bit 1 stop bit and no parity the throughput is 87771 characters per second This throughput may be limited by your driver software 1 4 SERIAL INTERFACES 1 4 Interface Standards The DHQ11 provides modem control signals which conform to EIA CCITT standard EIA 232 D V 24 The electrical characteristics of the data signal lines conform either to EIA 232 D V 24 or to RS 423 A V 28 depending on which cabinet kit is fitted The interface is compatible with X 26 V 10 standards The slew rate requirements for RS 423 A V 28 are different from the slew rate requirements for X 26 V 1
99. um distance guidelines Table 1 2 Maximum Distance Guidelines for DHQ11 Up to 4 8 Kb 9 6 Kb 19 2 Kb 38 4 Kb DEC423 to DEC423 1000 ft 1000 ft 1000 ft 500 ft 300 m 300 m 300 m 150 m DEC423 to EIA 232 D 250 ft 200 ft 75 60 m The DEC423 standard is for data leads only connections to terminal equipment and is not suitable for connection to modems or other Wide Area Network equipment The standard also specifies the use of a 6 pin Modified Modular Jack connector instead of the much larger 37 pin D type connector used with RS 423 A DEC423 is signal compatible with the EIA 232 D standard when used for data leads only interconnection in that interconnection between devices using the different standards is possible However the restrictions on the speed and distance of EIA 232 D will still apply DEC423 should always be used in preference to EIA 232 D for direct terminal connection over extended distances NOTE An H3105 active terminal adapter is necessary when using an EIA 232 D terminal with a DEC 423 interface if the longer cable lengths obtainable with DEC423 are required The recommended cable for DEC423 is BC16E XX which is available with 6 pin MMJ plugs at each end in lengths up to 100 feet This cable is also available without MMJ connectors in 1000 foot reels DIGITAL part number H8220 Unshielded four twisted pair cable can also be used This is available in 1000 foot reels DIGITAL part number H8245 A NOT
100. which have been transmitted The transfer can be continued by clearing TX ABORT and then setting TX DMA START in TBUFFAD2 No characters will be lost If DMA is not in progress the following actions will occur DHV11 mode no action DHU11 mode characters in the transmit FIFO will be discarded Because of up to two characters could be transmitted after the TX ABORT bit is set The host cannot determine exactly how many characters have been lost with this operation When an abort sequence has been completed the DHO11 will set the TX ACTION bit in the CSR If the transmitter interrupt is enabled the program will be interrupted at the transmit vector The program must make sure that TX ABORT is clear before setting TX DMA START otherwise the transfer will be aborted before any characters are transmitted The bit is cleared by MASTER RESET 3 2 2 10 Transmit Buffer Address Register Number 1 TBUFFADI TBUFFAD1 BASE 12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXMIT ADDRESS BITS O TO 15 RD1178 Bit Name Description 150 TBUFFAD lt 15 0 gt Bits lt 15 0 gt of the DMA address Transmit Buffer Address Low R W 3 2 2 11 Transmit Buffer Address Register Number 2 TBUFFAD2 TBUFFAD2 BASE 14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXMIT DMA TXMIT DMA ADDRESS ENABLE START BITS 16 TO 21 Bit Name Description 15 TX ENA When this bit is set the DHQ11 will transmit all
101. xes CK DHOII AF for H9642 cabinets DEC423 CK DHQ11 WA 123 11 boxes CK DHQ11 WB for BA23 boxes CK DHQIlI WF for H9642 cabinets 1 2 4 Configurations The can be used in many different system configurations Figure 1 2 shows a typical EIA 232 D application HOST PROCESSOR Q BUS LOCAL EQUIPMENT DHQ1 1 LOCAL EIGHT TERMINAL DATA CHANNELS TELEPHONE OR DATA COMMS LINES ANY MODEM ASYNCHRONOUS DEVICE EIGHT AN REMOTE REMOTE pene EES REMOTE EQUIPMENT TERMINAL TERMINAL REMOTE DHO11 OR DHV11 REMOTE Q BUS PROCESSOR Figure 1 2 Example of a DHQ11 Configuration 1 6 1 2 5 Connections The DHQ11 module is connected directly to Q bus by connectors A and B Figures 1 3 and 1 4 show the interconnections for EIA 232 D and DEC423 40 PIN BERG CONNECTORS CHANNELS TO 3 aD 2 ea a H3173 A ej DISTRIBUTION PANELS B al Z 25 PIN D TYPE lt CONNECTORS CHANNELS 4 TO 7 NOTE BCOS5L 01 30 12 INCHES BCO5L 1K 53 cm 21 INCHES BCOB5L 03 92 cm 36 INCHES RES Figure 1 3 11 Connections EIA 232 D BCOBL XX 40 PIN BERG CONNECTORS H3100 ACTIVE BULKHEAD PANEL H3104 CABLE CONCENTRATOR BACKPLANE Q22 LSI BUS CONNECTOR S COLOURED STRIP POWER CABLE 70 22775 XX BC16C 25 NOTE BCO5L 01 30cm 12 INCHES BCOBL 1K 53

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