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COMe-cP2020 User Guide, Revision 1.0

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1. 76 Figure 5 2 Cooling Solution COMe cP2020i 77 8 www kontron com COMe P2020 User Guide Proprietary Note This document contains information proprietary to Kontron It may not be copied or transmitted by any means disclosed to others or stored in any retrieval system or media without the prior written consent of Kontron or one of its authorized agents The information contained in this document is to the best of our knowledge entirely correct However Kontron cannot accept liability for any inaccuracies or the consequences thereof or for any liability arising from the use or application of any circuit product or example shown in this document Kontron reserves the right to change modify or improve this document or the product described herein as seen fit by Kon tron without further notice Trademarks Kontron and the Kontron logo are trade marks owned by Kontron AG Germany In addition this document may include names company logos and trademarks which are registered trademarks and therefore proprietary to their respective owners Environmental Protection Statement This product has been manufactured to satisfy environmental protection requirements where possible Many of the com ponents used structural parts printed circuit boards connectors batteries etc are capable of being
2. ACTION D7 D6 05 04 pins CODI DO READ NU NU NU NU cfg_rom_loc 0 3 WRITE NU NU NU NU NU POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION D3 D0 0000 PCI Express 1 0001 PCI Express 1 0010 Serial RapidIO 1 0011 Serial RapidIO 2 0100 DDR Controller 0101 PCI Express 3 0110 On chip boot ROM SPI configuration 0111 On chip boot ROM eSDHC configuration 1000 Local bus FCM 8 bit NAND flash small page 1001 Reserved 1010 Local bus FCM 8 bit NAND flash large page 1011 Reserved 1100 Reserved 1101 Local bus GPCM 8 bit 1110 Local bus GPCM 16 bit ROM 1111 Local bus GPCM 16 bit ROM default Table 3 40 0x301 Default Host Agent Configuration Register ACTION D7 06 05 04 03 02 01 DO READ NU NU NU NU NU cfg_host_agt 0 2 WRITE NU NU NU NU NU POWER UP 0 0 0 0 0 1 1 1 BITFIELD DESCRIPTION 00 02 000 P2020 acts as an agent on all its PCI Express and SRIO interfaces 001 P2020 acts as an agent on PCI Express 1 or host on Serial RapidIO 2 P2020 acts as a host on PCI Express 2 Serial RapidIO 1 P2020 acts as a host on PCI Express 3 010 P2020 acts as a host on PCI Express 1 or agent on Serial RapidIO 2 P2020 acts as an agent on PCI Express 2 Serial RapidIO 1 P2020 acts as a host on PCI Express 3 011 P2020 acts as a host on PCI Express 1 Serial RapidIO 2 P2020 acts as a host on PCI Express 2 Serial RapidIO 1 P2020 act
3. PIN IGNAL TYPE TERMINATION MMENT a GROUP 9 097 RSVD19 Local Bus 0 3 3 LA19 098 5 5 22 SERDES N C D99 SERDES TX22 SERDES N C D100 GND PWR GND D101 SERDES_TX23 SERDES N C D102 SERDES TX23 SERDES N C D103 GND PWR GND D104 VCC 12V PWR VCC 12V D105 VCC 12V PWR VCC 12V D106 VCC 12V PWR VCC 12V 0107 VCC 12V PWR VCC 12V D108 VCC 12V PWR VCC 12V D109 VCC 12V PWR VCC 12V D110 GND PWR GND Table 2 5 General Signal Description TYPE DESCRIPTION 1 0 3 3 Bi directional 3 3V I0 Signal I 3 3 3 3V Input 0 3 3 3 3V Output 00 3 3 Open Drain Output DP I 0 Differential Pair Input Output DP I Differential Pair Input DP 0 Differential Pair Output PDS Pulldown Strap Straping Input during Power Up do STRAP not connect any external Pullup or Pulldown resistor PWR Power Connection www kontron com COMe P2020 User Guide 2 5 2 Signal Descriptions COM Express Connectors 2 5 2 1 Ethernet Group GigE MDT The COMe cP2020 module provides three Gigabit Ethernet interface whose signals are already at copper Ethernet transmis sion voltage levels physical levels MDI in accordance to the COM Express Base Specification So the carrier board needs to add only the galvanic isolation magnetics function and the appropriate transmission connector type Additionally for monitoring and control purposes LED functionality is provided to indicate activity G
4. PIN SIGNAL GROUP TERMINATION COMMENT B91 VGA GRN RSVD N C B92 VGA BLU RSVD N C B93 VGA HSYNC RSVD N C B94 VGA VSYNC RSVD N C B95 VGA I2C CK RSVD N C B96 VGA I2C DAT RSVD N C 97 SPI_CS SPI 0 3 3 SPI_CSO SPI_CS1 B98 MDC clause 45 GBE MDIO N C B99 clause 45 GBEMDIO N C B100 GND PWR GND B101 FAN_PWNOUT BOARD CTRL N C B102 FAN_TACHIN BOARD CTRL 1 3 3 N C B103 SLEEP BOARD CTRL 1 3 3 N C B104 VCC 12V PWR VCC 12V B105 VCC 12V PWR VCC 12V B106 12V PWR VCC 12V B107 VCC 12V PWR VCC 12V B108 VCC 12V PWR VCC 12V B109 VCC 12V PWR VCC 12V B110 GND PWR GND www kontron com Table 2 3 SIGNAL Connector J2 Row C Pinout COMe P2020 User Guide PIN SIGNAL GROUP TYPE TERMINATION COMMENT C1 GND PWR GND C2 GND PWR eTSEC2_GBE1_ACT C3 USB SSRXO USB3 0 eTSEC2 GBE1 MDI3 C4 USB_SSRX0 USB3 0 eTSEC2_GBE1_MDI3 C5 GND PWR eTSEC2_GBE1_LINK100 USB_SSRX1 USB3 0 eTSEC2 GBE1 MDI2 C7 05 SSRX1 USB3 0 eTSEC2_GBE2_MDI2 C8 GND PWR eTSEC2_GBE1_LINK1000 C9 USB SSRX2 USB3 0 eTSEC2_GBE1_MDI1 C10 USB_SSRX2 USB3 0 eTSEC2_GBE1_MDI1 C11 GND PWR GND C12 USB SSRX3 USB3 0 eTSEC2 GBE1 MDIO C13 USB_SSRX3 USB3 0 eTSEC2_GBE2_MDI0 C1
5. 63 Table 3 53 0 30 Default Core1 Speed Register Reserved see note 64 Table 3 54 Default SerDes PLL Time out Enable Register 64 Table 3 55 0 320 0 321 Scratchpad Registers 40 41 64 6 www kontron com COMe P2020 User Guide Table 3 56 0 322 0 327 Scratchpad Registers 2 7 Not implemented 65 Table 3 57 0x330 Power Status Register 65 Table 3 58 0x338 CPU Status Register 4 65 Table 3 59 0x339 CPU Control Register 66 Table 3 60 Ox33A Board Variant Register 66 Table 3 61 0x350 PCIe Status Register 4 66 Table 3 62 0x351 PCIe Control Stabus Register 67 Table 3 63 0x370 Carrier Interrupt Direction Register 67 Table 3 64 0x374 Carrier Interrupt Mode 1 Register 68 Table 3 65 0x375 Carrier Interrupt Mode 2 Register 68 Table 3 66 0x3
6. ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 NFWP SPDWP 0 EEWP BFWP WRITE NU NU NU NFWP SPDWP NU EEWP BFWP POWER UP 0 0 0 0 1 0 1 0 BITFIELD DESCRIPTION 00 BFWP SPI Boot Flash 1 2 write protection 0 Boot Flash not write protected forces PLD output to logic HIGH 1 Boot Flash write protected PLD drives forces PLD output to HIGH Z 01 System data EEPROM write protection 0 EEPROM not write protected forces PLD output to Logic LOW 1 EEPROM write protected forces PLD output to HIGH Z D3 SPDWP SPD write protection 0 SPD not write protected forces PLD output to HIGH Z 1 SPD write protected forces PLD output to logic HIGH 04 NFWP NOR Flash write protection 0 NOR Flash not write protected forces PLD output to logic HIGH 1 NOR Flash write protected forces PLD output to HIGH Z Table 3 31 0 285 Reset Status Register ACTION D7 06 05 04 03 02 01 00 READ PORS 0 0 0 0 0 0 WTRS WRITE wic NU NU NU NU NU NU wic POWER UP 1 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 WTRS Watchdog timer reset status writing 1 clears the register 0 System reset not generated by Watchdog timer 1 System reset generated by Watchdog timer D7 PORS Power On reset status writing 1 clears the register 0 System reset generated by software warm reset 1 System reset generated by Power On cold reset Table 3 32 0x286 Board Interrupt Configuration Register not implem
7. 52 Table 3 27 0x085 Debug High Byte Register 53 Table 3 28 0x280 Status Register 0 53 Table 3 29 0x282 Control Register 0 53 Table 3 30 0x284 Device Protection Register 54 Table 3 31 0x285 Reset Status Register 54 Table 3 32 0x286 Board Interrupt Configuration Register not implemented 54 Table 3 33 0x288 Board ID High Byte Register 55 Table 3 34 0x289 Board and PLD Revision Register 55 Table 3 35 0 28 Watchdog Timer Register 56 Table 3 36 Ox28D Board ID Low Byte Register 56 Table 3 37 0x290 LED Configuration Register 57 Table 3 38 0x291 LED Control Register 57 Table 3 39 0x300 Default Boot ROM Lo
8. 37 Table 3 1 DIP Switch SW1 Configuration 38 Table 3 2 COMe bP2020 Virtual and Physical Memory Address 39 3 3 Address ee RR e RR ARR ERR ERI ER OIL CER I URN UR A UE AURA A ER RE 40 Table 3 4 0x000 User Boot ROM Location Configuration Register 43 Table 3 5 0x001 User Host Agent Configuration 44 Table 3 6 0x002 User 1 0 Port Selection Register 45 Table 3 7 0x003 User Boot Configuration Register 46 Table 3 8 0x004 User Boot Sequencer Configuration 15 2 46 Table 3 9 0x005 User SerDes Reference Clock Configuration Register 46 Table 3 10 0x006 User eTSEC2 SGMII Mode Configuration Register 47 Table 3 11 0x007 User eTSEC3 SGMII Mode Configuration Register 47 Table 3 12 0x008 User eTSEC1 Width Configuration Register 47 Table 3 13 0x009 User eTSEC2 Protocol Configuration Register 48 Table 3 14 User eTSEC3 Protocol
9. ACTION D7 D6 D5 04 D3 D2 D1 DO READ 0 0 0 0 0 0 0 Into WRITE NU NU NU NU NU NU NU wic POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 Into Interrupt occurred triggered by WATCHDOG line Register is cleared by write to 1 0 Interrupt 1 Interrupt is active Table 3 69 0 379 Board Interrupt Pending Register 4 ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 0 0 0 0 0 WRITE NU NU NU NU NU NU NU NU POWER UP 0 0 0 0 0 0 0 0 Register is currently read only read value is always 0x00 Table 3 70 0 37 Board Interrupt Enable Register 1 ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 En4 En3 En2 1 0 NU NU NU En4 En3 En2 En1 0 POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION D0 End Enable bit for CON_IRQ 1 Interrupt Request Register 0 Interrupt 1 Interrupt is active D1 1 Enable bit for CON_IRQ 2 Interrupt Request Register 0 no Interrupt 1 Interrupt is active D2 En2 Enable bit for CON_IRQ 3 Interrupt Request Register 0 no Interrupt 1 Interrupt is active D3 En3 Enable bit for CON_IRQ 4 Interrupt Request Register 0 no Interrupt 1 Interrupt is active D4 En4 Enable bit for CON_IRQ 5 Interrupt Request Register 0 no Interrupt 1 Interrupt is active www kontron com COMe P2020 User Guide Table 3 71 0 37 Board Interrupt Enable Register 2 ACTION D7 D6 D5 04 03 0
10. GE 9x DDR3 x8 1 banksoldered GbE j EMMg1 m 4x USBHost esc xz 5 ES SPI 8 2xROIPORTSCIS 9 9 OS Boot ROM 4 a Local Bus o 5 i i 3 bd Jc msc 9 8 33 25 2 22 15 1 2 1 05 075 8 pope x f 1 A IN 12 IEEE4588 strictly confidential www kontron com COMe P2020 User Guide Figure 1 2 2020 Board Layout Top View Figure 1 3 2020 Board Layout Bottom View 13 www kontron com COMe P2020 User Guide 1 3 Table 1 1 Technical Specifications COMe cP2020 Main Specifications COMe cP2020 SPECIFICATIONS PROCESSOR CPU The COMe cP2020 supports the following microprocessor Freescale QorIQ P2020 processor 1 2 GHz 667 MHz platform frequency standard temperature range Freescale QorlQ P2020 processor 1 0 GHz 667 MHz platform frequency ex tended temperature range Other operating speeds and processor variants P2010 P1020 and P1011 are available on request Integrated Controllers Controllers integrated in the CPU and utilized by the COMe cP2020 are eSDHC eLBC DUART eTSEC PCIe sRIO SPI MEMORY Memory Main memory Up to 4 GB dual channel DDR3 SDRAM memory with ECC running at 667 MHz 800 MHz version is avail
11. 11 ms half sine Shock Count 500 Climatic Humidity IEC60068 2 78 93 RH at 40 C non condensing see notice below WEEE Directive 2002 96 EC Waste electrical and electronic equipment RoHS II Directive 2011 65 EC Restriction of the use of certain hazardous substances in electri cal and electronic equipment www kontron com COMe P2020 User Guide Kontron performs comprehensive environmental testing of its products in accordance with appli cable standards Customers desiring to perform further environmental testing of Kontron products must contact Kontron for assistance prior to performing any such testing This is necessary as it is possible that environmental testing can be destructive when not performed in accordance with the appli cable specifications In particular for example boards without conformal coating must not be exposed to a change of temperature exceeding 1K minute averaged over a period of not more than five minutes Other wise condensation may cause irreversible damage especially when the board is powered up again Kontron does not accept any responsibility for damage to products resulting from destructive environmental testing 1 5 Related Publications Table 1 3 Related Publications SPECIFICATION S NDA do COM Express PICMG 0 COM Express Module Base Specification Revision 2 0 August 8 2010 Freescale Kontron and Emerson
12. www kontron com COMe P2020 User Guide Table 2 3 SIGNAL Connector J2 Row C Pinout Continued PIN SIGNAL GROUP TYPE TERMINATION COMMENT C97 RSVD19 Local Bus 0 3 3 LA20 C98 SERDES_RX22 SERDES N C C99 SERDES_RX22 SERDES N C C100 GND PWR GND C101 SERDES_RX23 SERDES N C C102 SERDES_RX23 SERDES N C C103 GND PWR GND C104 VCC 12V PWR VCC 12V C105 VCC 12V PWR VCC 12V C106 VCC 12V PWR VCC 12V C107 VCC 12V PWR VCC 12V C108 VCC 12V PWR VCC 12V C109 VCC 12V PWR VCC 12V C110 GND PWR GND www kontron com COMe P2020 User Guide Table2 4 Connector J2 Row D Pinout SIGNAL PIN SIGNAL GROUP TYPE TERMINATION COMMENT D1 GND PWR GND D2 GND PWR eTSEC3_GBE2_ACT D3 USB SSTXO USB3 0 eTSEC3 GBE2 MDI3 04 05 55 0 05 3 0 eTSEC3_GBE2_MDI3 05 GND PWR eTSEC3_GBE2_LINK100 06 USB_SSTX1 USB3 0 eTSEC3_GBE2_MDI2 07 USB_SSTX1 USB3 0 eTSEC3_GBE2_MDI2 D8 GND PWR eTSEC3 GBE2 LINK10004 09 USB SSTX2 USB3 0 eTSEC3_GBE2_MDI1 D10 USB_SSTX2 USB3 0 eTSEC3_GBE2_MDI1 011 GND PWR GND 012 USB_SSTX3 USB3 0 eTSEC3_GBE2_MDIO 013 USB_SSTX3 USB3 0 eTSEC3 GBE2 MDIO D14 GND PWR eTSEC3_GBE2_LINK 015 DDI1_CTRLCLK_AUX DDI N C D16 DDI1_CTRLDATA_AUX DDI
13. 014h 07Fh Reserved 080h POST Code Low Byte Register 081h POST Code High Byte Register 082h 083h Reserved 084h Debug Low Byte Register 085h Debug High Byte Register 086h 27Fh Reserved 280h Status Register 0 281h Status Register 1 Reserved www kontron com COMe P2020 User Guide Table 3 3 1 0 Address Map Continued ADDRESS FUNCTION 282h Control Register 0 283h Control Register 1 Reserved 284h Device Protection Register 285h Reset Status Register 286h Board Interrupt Configuration Register not implemented 287h Status Register 2 Reserved 288h Board ID High Byte Register 289h Board and PLD Revision Register 28Ah 28Bh Reserved 28Ch Watchdog Timer Register 28Dh Board ID Low Byte Register 28Eh 28Fh Reserved 290h LED Configuration Register 291h LED Control Register 292h 29Fh Reserved 300h Default Boot ROM Location Configuration Register 301h Default Host Agent Configuration Register 302h Default I 0 Port Selection Register 303h Default Boot Configuration Register 304h Default Boot ROM Location Configuration Register 305h Default SerDes Reference Clock Configuration Register 306h Default eTSEC2 SGMII Mode Configuration Register 307h Default eTSEC3 SGMII Mode Configuration Register 308h Default eTSEC1 Width Configuration Register 309h Default eTSEC2 Protocol Configuration Register 30Ah Default eTSE
14. 1 Serdes 2 Serdes 3 Config SS SSS SSS SSS S555 SSS SSS SS SS SS SSS fo SSS SSS SSS SSS SSS po SSS SSS SSS SSS SSS lt 0 gt OFF OFF OPE OFF me ee PCPs 82 0 BC a 82 5 8225 BC PCIEx 92 5 RC lt gt IC ip 5 PCIExX 40 5 lt 4 Ciel 12025 INC 55 hp e SGMII SGMII lt IC IA 8 5 SGMII SGMII 6 reise 0229 RC SF ke 0092501 SGMII SGMII 7 SRIOx1 62 5 H SRIOx1 82 5 H SGMII SGMII 8 SRIOx4 3 125H eTSEC2 configured in SGMII mode eTSEC3 configured in SGMII mode SRIO host mode device ID is 0 Boot ROM location is spi gt sconf set etsec2 rgmii Default configuration active gt sconf set etsec3 rgmii Default configuration active gt sconf info Default configuration active www kontron com COMe P2020 User Guide Listing available base configurations Serdes 0 Serdes 1 Serdes 2 Serdes 3 Config ose SSeS SSS SSS S55 oS SS SSS SS SS SS SSS SS SSS SS S SS SS SS SS lt OS OFF OFF OFF OFF Ae set PCIA 04 5 RC lt 25 02 5 INC 01229 INC lt 3e DCH 02 5 INC C2 3 INC lt 4 gt POTE 82 5 RC S SGMII SGMII lt Be POTEZ 0225 SGMII SGMII lt gt 2 5 IRC SRIOXI 82 5 H SGMII SGMII 7 SRIOx1 02 5 H SRIOx1 82 5 H SGMII
15. 105 7 3 Express Module to Carrier Assembly Considerations 105 4 www kontron com COMe P2020 User Guide List of Tables Table 1 1 COMe cP2020 Main Specifications 14 Table 1 2 euo 17 Table 1 3 Related PublICati ns 18 Table 2 1 Connector J1 RowAP Pinout 21 Table 2 2 Connector JT Row B PIBOUE sasccicdapcasesescnccetescacdacepanade catthasdenscacayataiaetaqscsedzahadedine 24 Table 2 3 Connector J2 Row nsa eon 27 Table 2 4 Connector Row DPinout 30 Table2 5 General Signal 32 Table 2 6 P2020 SerDes Lane Routing 33 Table 2 7 SerDes Protocol 34 Table 2 8 Signal 35 Table 2 9 On Board Device Resource 35 Table 2 10 JTAG Debug Connector J4 Pinout
16. C 0 66A 8 0 W 25 C 0 70A 8 4 W 85 C 0 85 10 2 W www kontron com COMe P2020 User Guide 5 Thermal There are different cooling solutions for the standard COMe cP2020c and the extended temperature board variant COMe cP2020i The standard board variant is populated by a heatspreader and the extended temperature board variant is popu lated by a heat sink with fins Both variants are able to run without any additional cooling solution convection cooled up to 50 C ambient temperature For life time issues it is recommended to operate the board below 35 C ambient temperature if there is no heat sink and no air flow 5 1 Cooling Solution COMe cP2020c The thermal concept of the COMe cP2020c is based on a specially designed full board heatspreader which contacts the main hot spots of the board and therefore provides optimal heat transfer from the board s top surface The heatspreader plate is NOT a heat sink but is sufficient to cool the standard board variant Nevertheless the heatspreader can be used as a COM Express standard thermal interface for use with a heat sink or other cooling solution bolted to the heatspreader with four skews To determine cooling performance the module temperature can be measured at the temperature reference point indicated in the figure below The cooling solution must in any event maintain a heatspreader plate temperature of 85 C or less Figure 5 1 Cooling Solution COMe
17. SATA2 TX SATA N C A24 SUS_S5 BOARD CTRL 0 3 3 Undefined A25 SATA2_RX SATA N C A26 SATA2_RX SATA N C www kontron com COMe P2020 User Guide Table 2 1 Connector 21 Row A Pinout Continued SIGNAL PIN SIGNAL GROUP TYPE TERMINATION COMMENT A27 BATLOW BOARD CTRL 3 3 Interrupt Source A28 S ATA ACTH SATA N C A29 AC HAD SYNC AUDIO N C A30 AC HAD_RST AUDIO N C A31 GND PWR GND A32 AC HAD BITCLK AUDIO N C A33 AC HAD SDOUT AUDIO N C A34 BIOS_DISO BOARD CTRL 1 3 3 N C A35 THERMTRIP BOARD CTRL 0 3 3 THERMTRIP A36 USB6 USB2 0 N C A37 USB6 USB2 0 N C A38 USB_6_7_OC USB2 0 N C A39 USB4 USB2 0 N C A40 USB4 USB2 0 N C A41 GND PWR GND A42 USB2 USB2 0 USB2 USB3 0 A43 USB2 USB2 0 USB2 USB3 0 A44 USB_2_3_0C USB2 0 I 3 3 USB_2_3_OC USB3 0 A45 USBO USB2 0 DP I 0 USBO USB3 0 A46 05 0 USB2 0 DP I 0 USBO USB3 0 A47 VCC_RTC PWR 3V VCC_RTC A48 EXCDO_PERST EXP CARD 0 3 3 Undefined A49 EXCDO_CPPE EXP CARD I 3 3 Undefined A50 RSVD Local Bus 0 3 3 LA16 A51 GND PWR GND A52 SERDES_TX5 SERDES N C A53 SERDES TX5 SERDES N C A54 GPIO SD_DATAO GPIO SDIO 1 0 3 3 SD DATAO A55 SERDES_TX4 SERDES DP 0 MUX PCIE TX1 P A56 SERDES TX4 SERDES DP 0 MUX PCIE
18. Saving environment to SPI Flash 2 MiB SF Detected AT25DF161 with page size 256 Bytes total 2 MiB 112218 1 SPL ias TE SLL clome gt reset gt printenv ethact ethact eTSEC3 gt 6 5 4 1 2 ethact ethact is used to define the currently active interface and to change the required interface without rebooting If a reboot or a power cycle is done the active Ethernet interface will be set back to the interface defined in ethprime or selected by the ethrotate functionality Example gt setenv ethact eTSEC2 gt 100 100 55 Using eTSEC2 device iesu 172 100 100 835 alive gt 6 5 4 1 3 ethrotate ethrotate can be used to force the selection of the next available interface if for example there is no link available for the selected interface If set to yes or undefined U Boot updates the ethact variable accordingly and tries to download the file again This is repeated until either the file is downloaded or all interfaces have been exhausted Inthe eventthe link is active for the selected interface and ethrotate is yes or undefined U Boot tries to download the file If it cannot download the file it tries the next available interface If the file is not available on the server U Boot stops trying and issues an error message If ethrotate is set to no only the interface defined in ethact is used Please note that the setting of the et
19. itis possible to use the dhcp or bootp commands An automatic run of the update script at every startup takes place if the update scriptis started in the preboot environment variable gt setenv preboot run update gt Saveenv gt 6 8 Recovery Mechanism There are two SPI boot flashes available with each device holding a copy of U Boot In case the contents of the Standard SPI boot flash has been corrupted e g as a result of a power failure during an update the Recovery SPI boot flash must be selected This is done by powering the system down deinstalling the COMe cP2020 module setting switch 2 of the SW1 DIP switch to the on position reinstalling the COMe cP2020 module and then restarting the system The board now starts from the Recovery SPI boot flash In this state the Standard SPI boot flash can be programmed again with the update or netupdate scripts described in Chapter 6 7 Update The update scripts provided ensure that prior to the update the Standard SPI boot flash is selected and the U Boot update image is available and correct Once the update is completed switch 2 of the SW1 DIP switch must be set to off to again allow booting from the Standard SPI boot flash The contents of the Recovery SPI boot flash should never be updated in order to avoid a completely inoperable system with no accessing capability 6 9 Copyrights and Licensing U Boot is Free Software It is copyrighted by Wolfgang Denk and
20. kontron 13 pgs Tank Ls COMe P2020 User Guide Revision History Publication Title COMe P2020 User Guide Brief Description of Changes Date of Issue 0 5 Initial Issue 18 February 2013 1 0 Chapter 3 updated 17 September 2013 Imprint Kontron Europe GmbH may be contacted via the following MAILING ADDRESS TELEPHONE AND E MAIL Kontron Europe GmbH 49 0 800 SALESKONTRON SudetenstraRe 7 sales kontron com D 87600 Kaufbeuren Germany For further information about other Kontron products please visit our Internet web site www kontron com Disclaimer Copyright O 2013 Kontron AG AIL rights reserved ALL data is for information purposes only and not guaranteed for legal purposes Infor mation has been carefully checked and is believed to be accurate however no responsibility is assumed for inaccuracies Kontron and the Kontron logo and all other trademarks or registered trademarks are the property of their respective owners and are recognized Spec ifications are subject to change without notice www kontron com COMe P2020 User Guide Contents R vision 2 EE 2 2 Proprietary uuu De dE 9 licht M c 9 Environmental Protection
21. 1 Booting Linux To boot Linux at least a kernel image and a FDT Flattened Device Tree must be loaded to memory Optionally an initrd can be loaded Furthermore a command line must be prepared in the environment variable bootargs The boot itself is initiated with the bootm command To simplify the setup of the board three predefined scripts are already programmed in the default environment nfsboot to boot from a tftp server and mount the root over NFS nandboot to boot from the NAND flash and also mount it as root sdboot to boot from SD Card and also mount it as root multi img boot to boot from the multi image provided The multi image consists of a FDT a kernel and a rootfs www kontron com COMe P2020 User Guide For a one time only bootup this can be accomplished with the run command for example gt run nfsboot gt To make this permanent and have the board execute it automatically it must be stored in the bootcmd environment vari able and the environment must be saved to flash Example setenv bootcmd run nandboot saveenv gt 6 5 9 2 Booting VxWorks To boot a Wind River VxWorks image a boot image file of the corresponding ROM able VxWorks binary image and an FDT Flattened Device Tree must be loaded to memory By default U Boot operates on uImage files boot image for U Boot which contain a special header and in the data por tion the operating sy
22. 3 3 3 3V Source for carrier SPI flash A92 SPI MISO SPI I 3 3 SPI MISO A93 GPOO SD CLK GPIO SDIO 0 3 3 SD CLK A94 SPI CLK SPI SPI CLK A95 SPI MOSI SPI 0 3 3 SPI MOSI A96 TPM PP BOARD CTRL GND 97 TYPE10 TYPE Single 4K7 pull down DNI A98 SERO_TX UART 0 3 3 UO TXD A99 SERO RX UART 1 3 3 UO RXD A100 GND PWR GND A101 SER1_TX UART 0 3 3 U1_TXD A102 SER1_RX UART I 3 3 U1_RXD A103 LID BOARD CTRL N C A104 VCC 12V PWR VCC 12V A105 VCC 12V PWR VCC 12V A106 VCC 12V PWR VCC 12V A107 VCC 12V PWR VCC 12V A108 VCC 12V PWR VCC 12V A109 VCC 12V PWR VCC 12V A110 GND PWR GND www kontron com COMe P2020 User Guide Table 2 2 Connector J1 Row B Pinout SIGNAL PIN SIGNAL GROUP TERMINATION COMMENT B1 GND PWR B2 GBEO ACT GigE MDI B3 1588 CLK OUT IEEE1588 0 3 3 1588 CLK OUT B4 1588 PULSE 1 IEEE1588 0 3 3 1588 PULSE OUT1 B5 1588 PULSE 2 IEEE1588 0 3 3 1588 PULSE 2 1588 ALARM 1 IEEE1588 0 3 3 1588 ALARM OUT1 B7 1588 ALARM OUT2 IEEE1588 0 3 3 1588 ALARM OUT2 B8 1588 TRIG IN1 IEEE1588 I 3 3 1588 TRIG IN1 B9 1588 TRIG IN2 IEEE1588 1 3 3 1588 TRIG IN2 B10 1588 CLK IN IEEE1588 I 3 3 1588 CLK IN B11 GND PWR GND B12 PWRBTN BOARD CTRL 1 3 3 Undefined B13 SMB CK SMB 1 0 3 3 SMB CK B14 SMB DAT SMB 1 0 3 3
23. 36 3 38 3 1 DIP Switch Ce ds 38 3 2 Board Memory Map ree ansa eee see eo acea cadence 39 3 3 D O Address ec 40 3 4 Board Control and Status Registers 43 4 PoW r 74 4 1 Electrical Specifications iiie iei rettet 74 4 1 1 Supply Voltages eiiis ries eret ede re ir es dena abono doa Yea PER rn euo 74 4 2 Power Supply Rise Time 74 3 www kontron com COMe P2020 User Guide 4 3 Supply Voltage nnne sheet eser 74 4 4 PowerConsuimpLiOn eR aee En Te kan e Rae SER e Eo eae ae Race pau 74 5 ree Terr UE 76 5 1 Cooling Solution COMe cP2020c 76 5 2 Cooling Solution COMe cP2020i 77 78 6 1 Introduction to U BOOE rh e RR EARN HRK 78 6 2 Standard U Boot Commands 78 6 3 Kontron Specifi
24. Common Pinout Definition PCI Express PCI Express Base Specification Revision 2 0 Dec 20 2006 Serial RapidIO RapidIO Interconnect Specification Part 6 LP Serial Physical Layer Specification Rev 2 0 1 March 2008 Ethernet IEEE802 3 Part 3 Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Physical Layer Specification Clause 22 Platform Firmware DENX U Boot Universal Boot Loader online documentation at www denx de Kontron Kontron s Product Safety and Implementation Guide ID 1021 9142 www kontron com COMe P2020 User Guide 2 Functional Description 2 1 Processor The COMe cP2020 supports the high performance 32 bit 45nm dual core Freescale QorIQ P2020 processor with the fol lowing functions and features Two e500v2 cores built on Power Architecture technology running up to 1 2 GHz clock speed 512 Kbyte shared level two cache 64 bit DDR3 SDRAM memory controllers with ECC and chip select interleaving support Data path acceleration architecture incorporating acceleration for Packet Buffer and Queue Management Three 1 Gbps Ethernet controllers Uptothree PCI Express 1 0a controllers ports running at 2 5 Gbps Two serial RapidIO controllers ports version 1 2 running at up to 3 125 Gbps One ULPI controller One SD MMC controller One SPI controller Two 2 controllers Two DUARTs One enhanced local bus controller
25. N C 017 LCSO Local Bus 0 3 3 LCSO 018 LCS1 Local Bus 0 3 3 LCS1 D19 SERDES_TX6 SERDES N C 020 SERDES_TX6 SERDES N C 021 GND PWR GND D22 SERDES_TX7 SERDES N C D23 SERDES TX7 SERDES N C D24 LA17 Local Bus 0 3 3 LA31 D25 LA16 Local Bus 0 3 3 LA30 D26 DDI1_PAIRO DDI N C 027 DDI1_PAIRO DDI N C 028 GND PWR GND D29 DDI1_PAIR1 DDI N C D30 DDI1_PAIR1 DDI N C 031 GND PWR GND D32 DDI1_PAIR2 DDI N C D33 DDI1_PAIR2 DDI N C D34 DDI1 DDC AUX SEL DDI N C D35 LALE Local Bus 0 3 3 LALE D36 DDI1_PAIR3 DDI N C 037 DDI1_PAIR3 DDI N C 038 GND PWR GND D39 SER1_CTS UART 1 3 3 UO CTS 040 SER1_RTS UART 0 3 3 UO_RTS 041 GND PWR GND D42 SER2_CTS UART 1 3 3 U1 CTS D43 SER2_RTS UART 0 3 3 U1_RTS 044 LBCTL Local Bus 0 3 3 LBCTL D45 LGTA Local Bus 0 3 3 LGTA D46 IRQ3 IRQ 1 3 3 Undefined 047 IRQ4 IRQ 1 3 3 Undefined 048 LA15 Local Bus 0 3 3 LA29 www kontron com COMe P2020 User Guide Table2 4 Connector J2 Row D Pinout Continued SIGNAL PIN SIGNAL GROUP TERMINATION COMMENT D49 LA14 Local Bus 0 3 3 LA28 D50 IRQ_OUT IRQ 0 3 3 Undefined 051 GND PWR GND D52 SERDES_TX8 SERDES N C D53 SERDES_TX8 SERDES N C D54 PEG_LANE_RV PCIE SERDES 1 3 3 Unde
26. SGMII lt 55 SRIOx4 3 125H eTSEC2 configured in RGMII mode eTSEC3 configured in RGMII mode SRIO hos mode device ID is 0 Boot ROM location is spi gt After configuration has finished completely configuration is saved permanently in the glue logic using the sconf save command In addition an automatic power cycle of the module is performed Configuration changes will not take effect without power cycle of the module The user configuration is stored in the internal user flash memory ofthe glue logic Due to techni cal restrictions writing to this area is limited to some 100 cycles For this reason it is recom mended to use the sconf save command carefully www kontron com COMe P2020 User Guide 6 5 4 Using the Network 6 5 4 1 Interface Selection U Boot provides support for multiple Ethernet interfaces for transferring files from a file server This is accomplished using the environment variables ethprime ethact and ethrotate 6 5 4 1 1 ethprime ethprime is used to select the required interface after power up or reset During boot up the U Boot checks if ethprime is set If set ethprime is used as the first active Ethernet interface ethact Please note that the setting of the ethprime is lost after a reset To retain the environment permanently use the command saveenv which saves the complete environment to flash Example gt setenv ethprime eTSEC3 gt saveenv
27. Statement 9 General Instructions on Usage 9 Two Year TILES 9 MES ug 11 1 1 COMe cP2020 DUGIVIGW 11 1 2 Board Diagrams ioo n eee o tects kusa qas 12 1 3 Technical Specifications iiie oie de cence sees e Pea 14 MES Q u 17 1 5 Related aa dise 18 2 Functional DescripLloii uus een e e RECON X EX CERE X ERR 19 2 1 dU Dg PETIT 19 2 0 un RH 19 2 21 sS a fr iU 19 2 2 2 Flash MEMON ag us au vede 19 2 2 3 System User Data EEPROMS 20 TMS c 20 2 4 Watchdog 20 2 5 JCORlleCbOTS eese 21 2 5 1 COM Express Connectors 21 2 5 2 Signal Descriptions COM Express Connectors 33 2 5 2 JTAG Deb g Interfa u nanasqa
28. UC_IRQ 10 ZU CON IRQ 4 i lt UC IRQ 10 4 Dir4 g CON_IRQ 5 gt 0 11 4 CON_IRQ 5 lt UC 11 Table 3 64 0x374 Carrier Interrupt Mode 1 Register ACTION READ Mode4 Mode3 Mode2 Model WRITE Mode4 Mode3 Mode2 Mode1 POWER UP 00 00 00 00 BITFIELD DESCRIPTION 20 01 Mode1 Interrupt Mode Definition of CON_IRQ 1 line 00 edge triggered high to low falling edge 01 edge triggered low to high rising edge 10 level triggered low active 11 level triggered high active D2 D3 Mode2 Interrupt Mode Definition of IRQ 2 H line 00 edge triggered high to low falling edge 01 edge triggered low to high rising edge 10 level triggered low active 11 level triggered high active D4 D5 Mode3 Interrupt Mode Definition of CON_IRQ 3 line 00 edge triggered high to low falling edge 01 edge triggered low to high rising edge 10 level triggered low active 11 level triggered high active D6 D7 Mode4 Interrupt Mode Definition of IRQ 4 H line 00 edge triggered high to Low falling edge 01 edge triggered low to high rising edge 10 level triggered low active 11 level triggered high active Table 3 65 0x375 Carrier Interrupt Mode 2 Register ACTION READ 00 00 00 Mode5 WRITE NU NU NU Mode5 POWER UP 00 00 00 00 BITFIELD DESCRIPTION 00 01 Mode5 Interrupt Mode De
29. YEAR LIMITED HARDWARE WARRANTY as described in the follow ing However no other warranties that may be granted or implied by anyone on behalf of Kontron are valid unless the con sumer has the express written consent of Kontron Kontron warrants their own products excluding software to be free from manufacturing and material defects for a period of 24 consecutive months from the date of purchase This warranty is not transferable nor extendible to cover any other users or long term storage of the product It does not cover products which have been modified altered or repaired by any other party than Kontron or their authorized agents Furthermore any product which has been or is suspected of being damaged as a result of negligence improper use incorrect handling servicing or maintenance or which has been dam aged as a result of excessive current voltage or temperature or which has had its serial number s any other markings or parts thereof altered defaced or removed will also be excluded from this warranty If the customer s eligibility for warranty has not been voided in the event of any claim he may return the product at the earliest possible convenience to the original place of purchase together with a copy of the original document of purchase a full description of the application the product is used on and a description of the defect Pack the product in such a way as to ensure safe transportation see our safety instructions www
30. acts as an agent on PCI Express 1 or host on Serial RapidIO 2 P2020 acts as a host on PCI Express 2 Serial RapidIO 1 P2020 acts as a host on PCI Express 3 010 P2020 acts as a host on PCI Express 1 or agent on Serial RapidIO 2 P2020 acts as an agent on PCI Express 2 Serial RapidIO 1 P2020 acts as a host on PCI Express 3 011 P2020 acts as a host on PCI Express 1 Serial RapidIO 2 P2020 acts as a host on PCI Express 2 Serial RapidIO 1 P2020 acts as an agent on PCI Express 3 100 P2020 acts as an agent on PCI Express 1 Serial RapidIO 2 P2020 acts as an agent on PCI Express 2 Serial RapidIO 1 P2020 acts as a host on PCI Express 3 101 P2020 acts as an agent on PCI Express 1 or host on Serial RapidIO 2 P2020 acts as a host on PCI Express 2 Serial RapidIO 1 P2020 acts as an agent on PCI Express 110 P2020 acts as a host on PCI Express 1 or agent on Serial RapidIO 2 P2020 acts as an agent on PCI Express 2 Serial RapidIO 1 P2020 acts as an agent on PCI Express 111 P2020 acts as the host processor root complex for all PCI Express Serial RapidIO interfaces www kontron com COMe P2020 User Guide Table 3 6 0x002 User 1 0 Port Selection Register ACTION READ NU NU NU NU cfg io ports 0 3 WRITE NU NU NU NU cfg io ports 0 3 POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION D3 D0 0000 PCI Express 1 x1 2 5Gbps SerDes lane 0 SerDes lanes 1 3 powered
31. cP2020c reference measurement point www kontron com COMe P2020 User Guide 5 2 Cooling Solution COMe cP2020i The thermal concept of the 20201 is based on a specially designed full board heat sink with fins which contacts the main hot spots of the board and therefore provides optimal heat transfer from the board s top surface The heat sink with fins is designed for operating the board up to 85 ambient temperature This heat sink needs external air flow of about 4mps to reach the maximum cooling performance To determine cooling performance the module temperature can be measured at the temperature reference point indicated in the figure below The air flow must in any event maintain a heatspreader plate temperature of 92 or less Figure 5 2 Cooling Solution COMe cP2020i reference measurement point O www kontron com COMe P2020 User Guide 6 U Boot 6 1 Introduction to U Boot U Boot is an open source bootloader software developed and maintained by DENX Software Engineering GmbH http www denx de Kontron provides U Boot with all its standard features as well as Kontron specific features for usage with Kontron s COMe cP2020 module This software is pre installed at the facotory and is ready for use on powerup This user guide provides specific information on Kontron s implementation of U Boot and its usage Please refer to the DENX web site for up to date
32. down 0001 SerDes lanes 0 3 powered down 0010 PCI Express 1 x1 2 5 Gbps SerDes lane 0 PCI Express 2 x1 2 5 Gbps SerDes lane 1 PCI Express 3 x2 2 5 Gbps SerDes lanes 2 3 0011 Reserved 0100 PCI Express 1 x2 2 5 Gbps SerDes lanes 0 1 PCI Express 3 x2 2 5 Gbps SerDes lanes 2 3 0101 Reserved 0110 PCI Express 1 x4 2 5 Gbps SerDes lanes 0 3 0111 SRIO2 1x 3 125 Gbps SerDes lane 0 SRIO1 1x 3 125 Gbps SerDes lane 1 SerDes lanes 2 3 powered down 1000 SRIO2 4x 1 25 Gbps SerDes lanes 0 3 1001 SRIO2 4x 2 5 Gbps SerDes lanes 0 3 1010 SRIO2 4x 3 125 Gbps SerDes lanes 0 3 1011 SRIO 2 1x 1 25 Gbps SerDes lane 0 SRIO 1 1x 1 25 Gbps SerDes lane 1 SGMII eTSEC2 x1 1 25 Gbps SerDes lane 2 SGMII eTSEC3 x1 1 25 Gbps SerDes lane 3 1100 SRIO 2 1x 2 5 Gbps SerDes lane 0 SRIO 1 1x 2 5 Gbps SerDes lane 1 SGMII eTSEC2 x1 1 25 Gbps SerDes lane 2 SGMII eTSEC3 x1 1 25 Gbps SerDes lane 3 1101 PCI Express 1 x1 2 5 Gbps SerDes lane 0 SRIO 1 1x 2 5 Gbps SerDes lane 1 SGMII eTSEC2 x1 1 25 Gbps SerDes lane 2 SGMII eTSEC3 x1 1 25 Gbps SerDes lane 3 1110 PCI Express 1 x1 2 5 Gbps SerDes lane 0 PCI Express 2 x1 2 5 Gbps SerDes lane 1 SGMII eTSEC2 x1 1 25 Gbps SerDes lane 2 SGMII eTSEC3 x1 1 25 Gbps SerDes lane 3 1111 PCI Express 1 x2 2 5 Gbps S
33. free status of all derivatives of our free software and of promoting the sharing and reuse of software generally NO WARRANTY 11 BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE THERE IS NO WARRANTY FOR THE PROGRAM TO THE EXTENT PERMITTED BY APPLICABLE LAW EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND OR OTHER PARTIES PROVIDE THE PROGRAM AS IS WITHOUT WARRANTY OF ANY KIND EITHER EXPRESSED OR IM PLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU SHOULD THE PROGRAM PROVE DEFECTIVE YOU ASSUME THE COST OF ALL NECESSARY SERVICING REPAIR OR COR RECTION www kontron com COMe P2020 User Guide 12 INNO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER OR ANY OTHER PARTY WHO MAY MODIFY AND OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE BE LIABLE TO YOU FOR DAMAGES INCLUDING ANY GENERAL SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OP ERATE WITH ANY OTHER PROGRAMS EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBIL ITY OF SUCH DAMAGES END OF TERMS AND CONDITIONS 6 10 Obtaining Source Code The software include
34. high performance reliability and security 2 2 2 4 MRAM Memory The COMe cP2020 supports 512 kB of MRAM memory Magnetorestrictive Random Access Memory for fast non volatile data storage optional 2 2 2 5 SDHC Socket The COMe cP2020 is provided with a microSDHC card socket J1 which accepts microSD and microSDHC cards up to 32 GB Tf used the card must be installed prior to installation of the COMe cP2020 in a system If the SDHC interface is routed to the COM Express connector via DIP switch SW1 switch 1 the onboard socket J1 cannot be used 2 2 3 System User Data EEPROMs The COMe cP2020 provides two 64 kBit EEPROMs one for system data storage and one which is free for user data storage The user data EEPROM is accessible via the OS or an application The system data EEPROM is reserved for system usage 2 3 Timer The COMe cP2020 is equipped with the following timer Real Time Clock RTC The COMe cP2020 is equipped with an onboard high precision real time clock RV 8564 C3 The RV 8564 C3 RTC is register compatible with the PCF8564A RTC from Philips NXP In addition it provides a very tight frequency tolerance at low power consumption The COMe cP2020 does not include a 3 V lithium battery or a GoldCap power source for RTC backup Power for the RTC is supplied by the carrier via the VCC_RTC pin 2 4 Watchdog Timer The COMe cP2020 provides a Watchdog timer that is programmable for a timeout period ranging from 125 ms to 4
35. interfaces operate in their standard width TBI GMII or MII mode Equivalent CPU strapping is hard coded in CPLD depends on board variant read value is always OxFE www kontron com COMe P2020 User Guide Table 3 48 0x309 Default eTSEC2 Protocol Configuration Register Reserved See note ACTION D7 D6 D5 04 03 D2 01 00 READ NU NU NU NU NU NU cfg tsec2 prto 0 1 WRITE NU NU NU NU NU NU NU POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 20 01 00 Reserved 01 The eTSEC2 controller operates using the MII protocol or RMII if configured in reduced mode if not configured to operate in SGMII mode 10 The eTSEC2 controller operates using the GMII protocol or RGMII if configured in reduced mode if not configured to operate in SGMII mode 11 The eTSEC2 controller operates using the TBI protocol or RTBI if configured in reduced mode if not configured to operate in SGMII mode Equivalent CPU strapping is hard coded in CPLD depends on board variant read value is always OxFC Table 3 49 0x30A Default eTSEC3 Protocol Configuration Register Reserved See note ACTION D7 D6 D5 D4 D3 D2 D1 00 READ NU NU NU NU NU NU cfg tsec2 prto 0 1 WRITE NU NU NU NU NU NU NU POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 20 01 00 Reserved 01 The eTSEC3 controller operates using the RMII protocol if not configured to operat
36. interven tion in the boot process 6 5 Working with U Boot 6 5 1 General Operation Most operations are carried out using the main memory as an intermediate step It is not possible for example to boot a kernel image directly from a tftp server Instead the kernel image is first loaded to memory and then booted from there with another command The same is true when writing new contents to the SPI boot flashes This concept is very flexible since it separates the commands which handle the loading of data from the commands that carry out actions like booting or programming flash devices 6 5 2 Using the sconf Command In previous board designs DIP switches were used to configure the fabric interfaces In response to evolving application requirements the sconf command has been designed to provide increased configuration flexibility The COMe cP2020 is delivered with a default configuration for the external interfaces routed to the COM Express connec tors If required these interfaces may be configured via the sconf command according to the application requirements The factory default configuration for the COMe cP2020 is as follows sconf base configuration 1 PCIEx4 22 5 eTSEC2 mode RGMII eTSEC3 mode RGMII Boot ROM location SPI To obtain information about the currently active configuration invoke the sconf info command www kontron com COMe P2020 User Guide 6 5 3 Examples of sconf Comm
37. kontron com COMe P2020 User Guide 3 4 Board Control and Status Registers The following registers are special registers which the COMe cP2020 uses to monitor and control the onboard hardware special features Take care when modifying the contents of these registers as the system may be relying on the state of the bits under its control Table 3 4 0 000 User Boot ROM Location Configuration Register ACTION READ NU NU NU NU cfg_rom_loc 0 3 WRITE NU NU NU NU cfg_rom_loc 0 3 POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION D3 D0 0000 PCI Express 1 0001 PCI Express 1 0010 Serial RapidIO 1 0011 Serial RapidIO 2 0100 DDR Controller 0101 PCI Express 3 0110 On chip boot ROM SPI configuration 0111 On chip boot ROM eSDHC configuration 1000 Local bus FCM 8 bit NAND flash small page 1001 Reserved 1010 Local bus FCM 8 bit NAND flash large page 1011 Reserved 1100 Reserved 1101 Local bus GPCM 8 bit 1110 Local bus GPCM 16 bit ROM 1111 Local bus GPCM 16 bit ROM default www kontron com COMe P2020 User Guide Table 3 5 0x001 User Host Agent Configuration Register ACTION READ NU NU NU NU NU cfg host agt 0 2 WRITE NU NU NU NU NU cfg host agt 0 2 POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 02 00 000 P2020 acts as an agent on all its PCI Express and SRIO interfaces 001 P2020
38. kontron com COMe P2020 User Guide Kontron provides for repair or replacement of any part assembly or sub assembly at their own discretion or to refund the original cost of purchase if appropriate In the event of repair refunding or replacement of any part the ownership of the removed or replaced parts reverts to Kontron and the remaining part of the original guarantee or any new guarantee to cover the repaired or replaced items will be transferred to cover the new or repaired items Any extensions to the original guarantee are considered gestures of goodwill and will be defined in the Repair Report issued by Kontron with the repaired or replaced item Kontron will not accept liability for any further claims resulting directly or indirectly from any warranty claim other than the above specified repair replacement or refunding In particular all claims for damage to any system or process in which the product was employed or any loss incurred as a result of the product not functioning at any given time are excluded The extent of Kontron liability to the customer shall not exceed the original purchase price of the item for which the claim exists Kontron issues no warranty or representation either explicit or implicit with respect to its products reliability fitness quality marketability or ability to fulfil any particular application or purpose As a result the products are sold as is and the responsibility to ensure thei
39. many others who contributed code see the actual source code for details You can redistribute U Boot and or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation Most of it can also be distributed at your option under any later version of the GNU General Public License see individual files for exceptions NOTE This license does not cover the so called standalone applications that use U Boot services by means of the jump table provided by U Boot exactly for this purpose this is merely considered normal use of U Boot and does not fall under the heading of derived work The header files include image h and include asm u boot h define interfaces to U Boot Including these unmodi fied header files in another file is considered normal use of U Boot and does not fall under the heading of derived work Also note that the GPL below is copyrighted by the Free Software Foundation but the instance of code that it refers to the U Boot source code is copyrighted by me and others who actually wrote it Wolfgang Denk GNU GENERAL PUBLIC LICENSE Version 2 June 1991 Copyright C 1989 1991 Free Software Foundation Inc 59 Temple Place Suite 330 Boston MA 02111 1307 USA www kontron com COMe P2020 User Guide Everyone is permitted to copy and distribute verbatim copies of this license document but changing it is not allowed Preamble The licen
40. mode and uses SGMII SerDes lane 3 pins 1 eTSEC3 Ethernet interface operates in standard parallel interface mode and uses the TSEC3 pins Table 3 12 0 008 User eTSEC1 Width Configuration Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ NU NU NU NU NU NU NU cfg tsec reduce WRITE NU NU NU NU NU NU NU cfg tsec reduce POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 00 0 eTSEC1 and eTSEC2 Ethernet interfaces operate in reduced pin mode either RTBI RGMII or RMII mode 1 eTSEC1 and eTSEC2 Ethernet interfaces operate in their standard width TBI GMII or MII mode Register value is no more used to force CPU strapping but register is used for checksum calculation write Register value to 0x00 Equivalent CPU strapping is hard coded in CPLD depends on board vari ant value is Ob www kontron com COMe P2020 User Guide Table 3 13 0 009 User eTSEC2 Protocol Configuration Register ACTION D7 D6 D5 04 03 02 01 00 READ NU NU NU NU NU NU cfg tsec2 prto 0 1 WRITE NU NU NU NU NU NU cfg tsec2 prto 0 1 POWER UP 1 1 1 1 1 1 1 1 01 00 00 Reserved 01 The eTSEC2 controller operates using the MII protocol or RMII if configured in reduced mode if not configured to operate in SGMII mode 10 The eTSEC2 controller operates using the GMII protocol or RGMII if configured in reduced mode if not configured to operate in SGMII mode 11 T
41. offer to distribute corresponding source code This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer in accord with Subsection b above The source code for a work means the preferred form of the work for making modifications to it For an executable work complete source code means all the source code for all modules it contains plus any associated interface definition files plus the scripts used to control compilation and installation of the executable However as a special exception the source code distributed need not include anything that is normally distributed in either source or binary form with the major components compiler kernel and so on of the operating system on which the executable runs unless that component itself accompanies the executable If distribution of executable or object code is made by offering access to copy from a designated place then offering equiv alent access to copy the source code from the same place counts as distribution of the source code even though third par ties are not compelled to copy the source along with the object code 4 You may not copy modify sublicense or distribute the Program except as expressly provided under this License Any attempt otherwise to copy modify sublicense or distribute the Program is void and will automatically ter minate your rights under this License However pa
42. powered down 1000 SRIO2 4x 1 25 Gbps SerDes lanes 0 3 1001 SRIO2 4x 2 5 Gbps SerDes lanes 0 3 1010 SRIO2 4x 3 125 Gbps SerDes lanes 0 3 1011 SRIO 2 1x 1 25 Gbps SerDes lane 0 SRIO 1 1x 1 25 Gbps SerDes lane 1 SGMII eTSEC2 x1 1 25 Gbps SerDes lane 2 SGMII eTSEC3 x1 1 25 Gbps SerDes lane 3 1100 SRIO 2 1x 2 5 Gbps SerDes lane 0 SRIO 1 1x 2 5 Gbps SerDes lane 1 SGMII eTSEC2 x1 1 25 Gbps SerDes lane 2 SGMII eTSEC3 x1 1 25 Gbps SerDes lane 3 1101 PCI Express 1 x1 2 5 Gbps SerDes lane 0 SRIO 1 1x 2 5 Gbps SerDes lane 1 SGMII eTSEC2 x1 1 25 Gbps SerDes lane 2 SGMII eTSEC3 x1 1 25 Gbps SerDes lane 3 1110 PCI Express 1 x1 2 5 Gbps SerDes lane 0 PCI Express 2 x1 2 5 Gbps SerDes lane 1 SGMII eTSEC2 x1 1 25 Gbps SerDes lane 2 SGMII eTSEC3 x1 1 25 Gbps SerDes lane 3 1111 PCI Express 1 x2 2 5 Gbps SerDes lanes 0 1 SGMII eTSEC2 x1 1 25 Gbps SerDes lane 2 SGMII eTSEC3 x1 1 25 Gbps SerDes lane 3 www kontron com COMe P2020 User Guide Table 3 42 0 303 Default Boot Configuration Register ACTION D7 D6 D5 04 D3 D2 01 00 READ NU NU NU NU NU NU cfg_cpu0 1_boot WRITE NU NU NU NU NU NU NU POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 20 01 00 CPU boot holdoff mode for both cores The e500 cores are prevented from booting until configu
43. starts Reading of UFM User configuration bit is set by register access and Self cleared by CPLD D7 UfmBusy UFM status bit UFM command Erase read or write is in progress if bit is High any UFM access 15 NOT allowed 0 no command 1 UFM command is in progress Table 3 24 0 080 POST Code Low Byte Register ACTION READ POST_Code_Low_Byte 7 0 WRITE POST_Code_Low_Byte 7 0 POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 07 POST Code Low Byte 7 0 POST Code Low Byte Register Table 3 25 0 081 POST Code High Byte Register ACTION 07 READ POST_Code_High_Byte 7 0 WRITE POST_Code_High_Byte 7 0 POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 20 07 POST Code High Byte 7 0 POST Code High Byte Register Table 3 26 0 084 Debug Low Byte Register ACTION READ Debug_Low_Byte 7 0 WRITE Debug_Low_Byte 7 0 POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 07 Debug Low Byte 7 0 Debug Low Byte Register www kontron com COMe P2020 User Guide Table 3 27 0 085 Debug High Byte Register ACTION READ Debug High Byte 7 0 WRITE Debug High Byte 7 0 POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 07 Debug High Byte 7 0 Debug High Byte Register Table 3 28 0 280 St
44. tribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations then as a consequence you may not distribute the Program at all For example if a patent license would not permit royalty free redistribution ofthe Program by all those who receive copies directly or indirectly through you then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Pro gram If any portion of this section is held invalid or unenforceable under any particular circumstance the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances Itis not the purpose of this section to induce you to infringe any patents or other property right claims or to contest valid ity of any such claims this section has the sole purpose of protecting the integrity of the free software distribution system which is implemented by public license practices Many people have made generous contributions to the wide range of soft ware distributed through that system in reliance on consistent application of that system it is up to the author donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License 8 Ifthe distribution and or use ofthe Program is restrict
45. 0 Direction of line CON_IRQ 2 0 Line is used as Input and forces automatically UC_IRQ 8 line when enabled 1 Line is used as Output and driven by UC_IRQ 8 line D2 Dir2 10 Direction of line IRQ 3 4 0 Line is used as Input and forces automatically UC IRQ 9 4 line when enabled 1 Line is used as Output and driven by UC_IRQ 9 line D3 Dir3 10 Direction of line CON_IRQ 4 0 Line is used as Input and forces automatically UC_IRQ 10 when enabled 1 Line is used as Output and driven by UC_IRQ 10 line D4 Dir4 10 Direction of line CON_IRQ 5 0 Line is used as Input and forces automatically UC_IRQ 11 line when enabled 1 Line is used as Output and driven by UC_IRQ 11 line Register settings control as well direction of UC_IRQ 11 7 lines If equivalent IRQ 5 1 it line is used as Input equivalent UC_IRQ 11 7 line is automatically configured as Output if CON_IRQ 5 1 is used as Output equivalent UC_IRQ 11 7 is configured as Input for details see table below www kontron com COMe P2020 User Guide REGISTERBIT LEVEL DIRECTION Diro 0 CON_IRQ 1 gt UC_IRQ 7 zH CON_IRQ 1 lt UC_IRQ 7 Dir o CON_IRQ 2 gt UC_IRQ 8 417 CON_IRQ 2 lt UC_IRQ 8 Dir2 Q CON IRQ 3 4 gt UC 0 9 CON_IRQ 3 lt UC_IRQ 9 Dir3 0 CON_IRQ 4 gt
46. 00000 256MB V 04 gt 0000000 0000 I G RWX 9 00 d0000000 256MB 0 gt 40000000 0000 I G RWX 10d 00 0000000 64MB V Od gt f 10000000 0000 I G RWX 11d 00 4000000 64MB V Od gt f 4000000 0000 I G RWX www kontron com COMe P2020 User Guide Table 6 8 Command vpd Provides functions for configuration of external interfaces SYNTAX print name limport 11 params vpd command print option displays VPD information source System EEPROM if lt name gt is not used all VPD entities are displayed name parameter text string x gt name of VPD entity addressed by option import option imports VPD information to the U Boot environment source System EEPROM target RAM all params parameter text constant all params selects all VPD entities for importing to the U Boot environment DESCRIPTION Vital Product Data are information stored in the System EEPROM which are required for proper operation of the board With this command the VPD entities can be displayed or imported to the U Boot environment in RAM Among the VPD entities are for example the board serial number and the board s Ethernet MAC addresses If the option import is invoked existing VPD entities in the environment in RAM are overwritten If a saveenv is then invoked the previously stored values in the currently active SPI boot
47. 096 s in 16 steps Failure to trigger the Watchdog timer in time results in a interrupt or a system reset or both In dual stage mode it results in a combination of both interrupt and reset if the Watchdog is not serviced A hardware status flag will be pro vided to determine if the Watchdog timer generated the reset Refer to the Watchdog Timer Control Register WTIM in Chapter 3 for further information There are four possible modes of operation involving the Watchdog timer Timer only mode Reset mode Interrupt mode Dual stage mode At power on the Watchdog is not enabled If required the bits of the Watchdog Timer Control Register must be set according to the application requirements To operate the Watchdog the mode and time period required must first be set and then the Watchdog enabled Once enabled the Watchdog can only be disabled or the mode changed by powering down and then up again To prevent a Watchdog timeout the Watchdog must be retriggered before timing out This is done by writing a 1 to the WTR bit In the event a Watchdog timeout does occur the WTE bit is set to 1 What transpires after this depends on the mode selected www kontron com COMe P2020 User Guide The four operational Watchdog timer modes can be configured by the WMD 1 0 bits and are described as follows Timer only mode In this mode the Watchdog is enabled using the required timeout period Normally the Watchdog is retrigger
48. 1 02 5 RC PCIEx1 2 5 RC 2 82 5 RC lt 3 gt PCIEx2 82 5 RC PCIEx2 82 5 RC lt 4 PCIEx1 02 5 RC PCIEx1 02 5 RC SGMII SGMII 5 PCIEx2 62 5 RC SGMII SGMII lt gt PCIEx1 82 5 RC SRIOxI 42 5 H SGMII SGMII 7 SRIOx1 82 5 H SRIOx1 82 5 H SGMII SGMII lt 8 gt SRIOx4 3 125H www kontron com COMe P2020 User Guide Table 6 7 tlbdbg Command tlbdbg Displays current configuration of TLBO and TLB1 SYNTAX tlbdbg tlbdbg command DESCRIPTION This command provides information on the translation look aside buffers TLBO ad TLB1 for debugging purposes during U Boot development or for debugging OS startup issues USAGE 1 Display TLBO TLB1 information tlbdbg TLBx Configuration Register 04110200 101bc010 TLBO check 512 entries IDX PID EPN SIZE V TS RPN UO U3 WIMGE UUUSSS TLB1 check 16 entries IDX PID EPN SIZE TS RPN UO U3 WIMGE UUUSSS Od 00 4kB V 0 gt 0 7ffff000 0000 I G RWX 1 00 ffe00000 1MB V 0 gt f ffe00000 0000 I G RWX 2d 00 80000000 1GB V 0 gt e 80000000 0000 I G RWX 00 00000 256kB V Od gt ffc00000 0000 I G RWX 4 00 8000000 V 0 gt f 8000000 0000 I G RWX 5d 00 000000 4kB V 0 gt f 000000 0000 I G RWX 00 00000000 1GB V gt 0 00000000 0000 RWX 7d 00 40000000 16 V 0d gt 0 40000000 0000 c RWX 8d 00 c00
49. 2 01 00 En7 En6 En5 En4 En3 En2 1 0 WRITE En7 En6 En5 En4 En3 En2 Eni EnO POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION D0 0 Enable bit for CON_SMB_ALERT Interrupt Request Register 0 no Interrupt 1 2 Interrupt is active D1 1 Enable bit for LM73_TEMP_ALERT Interrupt Request Register 0 no Interrupt 1 Interrupt is active D2 En2 Enable bit for CON_THERM Interrupt Request Register 0 no Interrupt 1 Interrupt is active D3 En3 Enable bit for CON_PWR_OK Interrupt Request Register 0 no Interrupt 1 Interrupt is active D4 En4 Enable bit for CON_BATLOW Interrupt Request Register 0 Interrupt 1 Interrupt is active D5 En5 Enable bit for RTC_INT Interrupt Request Register 0 Interrupt 1 2 Interrupt is active D6 En6 Enable bit for CON_WAKEO Interrupt Request Register 0 no Interrupt 1 2 Interrupt is active D7 En7 Enable bit for 1 Interrupt Request Register 0 no Interrupt 1 Interrupt is active Table 3 72 0 37 Board Interrupt Enable Register 3 ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 0 0 0 0 EnO WRITE NU NU NU NU NU NU NU EnO POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION D0 0 Enable bit for WATCHDOG Interrupt Request Register 0 no Interrupt 1 Interrupt is active www kontron com COMe P2020 Us
50. 4 GND PWR eTSEC2_GBE1_LINK C15 DDI1_PAIR6 DDI N C C16 DDI1_PAIR6 DDI N C C17 LOE Local Bus 0 3 3 LOE C18 LWE Local Bus 0 3 3 LWE C19 SERDES_RX6 SERDES N C C20 SERDES_RX6 SERDES N C C21 GND PWR GND C22 SERDES_RX7 SERDES N C C23 SERDES_RX7 SERDES N C C24 DDI1_HPD DDI N C C25 DDI1_PAIR4 DDI N C C26 DDI1_PAIR4 DDI N C C27 LADO Local Bus 1 0 3 3 LADO C28 LAD1 Local Bus 1 0 3 3 LAD1 C29 DDI1_PAIR5 DDI N C C30 DDI1_PAIR5 DDI N C C31 GND PWR GND C32 LAD2 Local Bus 1 0 3 3 2 C33 LAD3 Local Bus 1 0 3 3 LAD3 C34 LAD4 Local Bus 1 0 3 3 LAD4 C35 LADS Local Bus 1 0 3 3 LAD5 C36 LAD6 Local Bus 1 0 3 3 LAD6 C37 LAD7 Local Bus 1 0 3 3 LAD7 C38 LAD8 Local Bus 1 0 3 3 LAD8 C39 LAD9 Local Bus 1 0 3 3 LAD9 C40 LAD10 Local Bus 1 0 3 3 LAD10 C41 GND PWR GND C42 LAD11 Local Bus 1 0 3 3 LAD11 C43 LAD12 Local Bus 1 0 3 3 LAD12 C44 LAD13 Local Bus 1 0 3 3 LAD13 C45 LAD14 Local Bus 1 0 3 3 LAD14 C46 LAD15 Local Bus 1 0 3 3 LAD15 C47 MDC clause 22 GBE MDIO 0 2 5 MDC clause 22 C48 clause 22 GBE MDIO 1 0 2 5 MDIO clause 22 www kontron com COMe P2020 User Guide Table 2 3 SIGNAL Connector J2 Row C Pinout Continued PIN SIGNAL GROUP TERMINATIO
51. 76 Board Interrupt Pending Register 1 69 Table 3 67 0x377 Board Interrupt Pending Register 2 69 Table 3 68 0x378 Board Interrupt Pending Register 3 70 Table 3 69 0x379 Board Interrupt Pending Register 4 70 Table 3 70 7 Board Interrupt Enable Register 1 70 Table 3 71 0x37B Board Interrupt Enable Register 2 71 Table 3 72 0 37 Board Interrupt Enable Register 3 71 Table 3 73 0x37D Board Interrupt Enable Register 4 72 Table 3 74 0x380 Interrupt Multiplexer Register 1 72 Table 3 75 0x381 Interrupt Multiplexer Register 2 72 Table 3 76 0x390 Carrier Control Register 73 Wable 4 12 Supply 5 u a asa aa a aa assaka aE KEE E ea Saan ELEN EEEE EEE REKE 74 Table 4 2 Workload Dependency 74 Table 4 3 Power Consumption vs Ambient Temperature St
52. 96 04 WEN WTR Watchdog timer enable watchdog trigger 0 Watchdog timer not enabled Prior to the Watchdog being enabled this bit is known as WEN After the Watchdog is enabled it is known as WTR Once the Watchdog timer has been enabled this bit cannot be reset to 0 As long as the Watchdog timer is enabled it will indicate a 1 Watchdog timer enabled Writing a 1 to this bit causes the Watchdog to be retriggered to the timer value indicated by bits WTM 3 0 D5 D6 WMD Watchdog mode 00 Timer only mode 01 Reset mode 10 Interrupt mode 11 Cascaded mode dual stage D7 WTE Watchdog timer expired status bit writing 1 clears the bit 0 2 Watchdog timer has not expired 1 Watchdog timer has expired Table 3 36 0 28 Board ID Low Byte Register ACTION READ Board Register Low Byte 7 0 WRITE Board Register Low Byte 7 0 POWER UP 0 1 0 0 1 0 0 0 BITFIELD DESCRIPTION 00 07 Board Register Low Byte 7 0 Board Identification Low Byte COMe P2020 0xD048 www kontron com COMe P2020 User Guide Table 3 37 0x290 LED Configuration Register ACTION READ 0 0 0 0 LCON WRITE NU NU NU NU LCON POWER UP 0 0 0 0 0000 BITFIELD DESCRIPTION 00 03 LCON Use specific LED configuration 0000 POST 0001 Mode A General Purpose Mode others Reserved POST Mode LEDs b
53. BE 0 2 Ethernet link 21 LINK Ethernet speed 100Mbit s GBE 0 2 LINK100 and Ethernet speed 1000Mbit s GBE 0 2 _LINK1000 Reference voltage for carrier board Ethernet magnetics center tap is not required 2 5 2 2 Ethernet Management ETH MGT The management communication between the Ethernet MACs and the external connected Ethernet PHYs is realized by using the signal group ETH MGT EC MDC EC MDIO 2 5 2 3 IEEE 1588 The Freescale QorIQ CPUs provide support for the Ethernet Precision Time Protocol PTP defined in the IEEE 1588 specifica tion In order to utilize this functionality the CPUs provide additional IEEE 1588 time stamp signals For a more detailed description of those signals please refer to the CPU s reference manual 2 5 2 4 SerDes The signal group SerDes reflects all the high speed low voltage differential signals provided by the CPU The SerDes signals are grouped into so called lanes and links set of differential signal pairs one pair for transmission and one pair for reception is called a lane One or more lanes together form a link which can support various logical protocols such as PCIe sRIO SGMIT The P2020 Processor provides 4 SerDes lanes lane 0 to lane 3 SerDes lanes 1 to 3 are configurable Each lane can be switched via on board multiplexer to different COMe connector SerDes Ports The multiplexer are controlled by CPLD see chapter xxx User SerDes Multiplexer Control Registe
54. B_RESET B51 GND PWR GND B52 SERDES_RX5 SERDES N C B53 SERDES_RX5 SERDES N C B54 GPO1 SD CMD GPIO SDIO 0 3 3 SD CMD B55 SERDES_RX4 SERDES DP I MUX_PCIE_RX1_P B56 5 5 4 SERDES DP I MUX PCIE RX1 N B57 GPO SD WP GPIO SDIO 0 3 3 SD WP 58 SERDES_RX3 SERDES DP I PCIE_RX3 B59 SERDES_RX3 SERDES DP I PCIE_RX3 B60 GND PWR GND B61 SERDES_RX2 SERDES DP I PCIE RX24 B62 SERDES RX2 SERDES DP I PCIE RX2 B63 GP03 SD_CD GPIO SDIO 1 3 3 SD_CD B64 SERDES_RX1 SERDES DP I PCIE_RX1 B65 SERDES_RX1 SERDES DP I PCIE_RX1 B66 WAKEO BOARD CTRL 1 3 3 N C B67 BOARD CTRL 1 3 3 N C B68 SERDES_RX0 SERDES DP I 0 69 SERDES RXO SERDES DP I PCIE 0 B70 GND PWR GND B71 LVDS_BO LVDS N C B72 LVDS_BO LVDS N C B73 LVDS_B1 LVDS N C B74 LVDS_B1 LVDS N C B75 LVDS_B2 LVDS N C B76 LVDS_B2 LVDS N C B77 LVDS_B3 LVDS N C B78 LVDS_B3 LVDS N C B79 LVDS_BKLT_EN LVDS N C B80 GND PWR GND B81 LVDS B CK LVDS N C B82 LVDS_B_CK LVDS N C B83 LVDS BKLT CTRL LVDS N C B84 VCC 5V SBY PWR VCC 5V SBY B85 VCC 5V SBY PWR VCC 5V SBY B86 VCC 5V SBY PWR VCC 5V SBY B87 VCC 5V SBY PWR VCC 5V SBY B88 BIOS_DIS1 SPI 1 3 3 Undefined B89 VGA RED RSVD N C B90 GND PWR GND www kontron com COMe P2020 User Guide Table 2 2 SIGNAL Connector J1 Row B Pinout Continued
55. C lt 2 gt 1 02 5 RC 62 5 RC PCIEx2 62 5 RC 3 PCIEx2 2 5 RC PCIEx2 02 5 RC lt 4 PCIEx1 02 5 RC PCIEx1 02 5 RC SGMII SGMII lt S gt PCIEx2 2 5 RC SGMII SGMII 6 PCIEx1 02 5 RC SRIOx1 82 5 H SGMII SGMII 7 SRIOx1 82 5 H SRIOx1 82 5 H SGMII SGMII 8 SRIOx4 3 125H 5 2 configured in SGMII mode 5 configured in SGMII mode SRIO host mode device ID is 0 Boot ROM location is spi gt www kontron com COMe P2020 User Guide Table 6 6 sconf Command Continued 2 Select new base configuration gt sconf select 7 Default configuration active SGMII mode SGMII mode 5 2 configured in leTSEC3 configured in SRIO host mode device ID is 0 Boot ROM location is spi gt confine new base configuration gt sconf set etsec2 rgmii Default configuration active gt sconf set etsec3 rgmii Default configuration active 4 check changes gt sconf info Default configuration active 5 2 configured in RGMII mode 5 configured in RGMII mode SRIO host mode device ID is 0 Boot ROM location is spi gt 5 Save new configuration Board is power cycled automatically gt sconf save pow m 0 Serdes 1 Serdes 2 Serdes 3 Config 0 OFF OFF OFF OFF lt 1 gt PCIEx4 82 5 RC lt 2 gt PCIEx
56. C3 Protocol Configuration Register 30Bh Default RapidIO Device ID Register 30Ch Default RapidIO System Size Register 30Dh Default CoreO Speed Register 30Eh Default Core1 Speed Register 30Fh Default SerDes PLL Time out Enable Register 310h 31F Reserved www kontron com COMe P2020 User Guide Table 3 3 1 0 Address Map Continued ADDRESS FUNCTION 320h 321h Scratchpad Registers 0 1 322h 327h Scratchpad Registers 2 7 not implemented 328h 32Fh Reserved 330h Power Status Register 331h 337h Reserved 338h CPU Status Register 339h CPU Control Register 33Ah Board Variant Register 33Bh 34Fh Reserved 350h PCIe Status Register 351h PCIe Control Status Register 352h 36Fh Reserved 370h Carrier Interrupt Direction Register 371h 373h Reserved 374h Carrier Interrupt Mode 1 Register 375h Carrier Interrupt Mode 2 Register 376h Board Interrupt Pending Register 1 377h Board Interrupt Pending Register 2 378h Board Interrupt Pending Register 3 379h Board Interrupt Pending Register 4 37Ah Board Interrupt Enable Register 1 37Bh Board Interrupt Enable Register 2 37Ch Board Interrupt Enable Register 3 37Dh Board Interrupt Enable Register 4 37Eh 37Fh Reserved 380h Interrupt Multiplexer Register 1 381h Interrupt MultiplexerRegister 2 382h 38Fh Reserved 390h Carrier Control Register Test only www
57. Configuration Register 48 Table 3 15 OxOOB User RapidIO Device ID Register 49 Table 3 16 0 00 User RapidIO System Size Register 49 Table 3 17 0 000 User CoreO Speed Register 49 Table 3 18 User Corel Speed Register 50 Table 3 19 OxOOF User SerDes OLL Time out Enable Register 50 Table 3 20 0x010 Serdes Multiplexer Control Register 51 5 www kontron com COMe P2020 User Guide Table 3 21 0x011 User Checksum Register 51 Table 3 22 0x012 UFM Erase Control Register 51 Table 3 23 0x013 UFM CPU Control and Status Register 5g Table 3 24 0x080 POST Code Low Byte Register 52 Table 3 25 0x081 POST Code High Byte Register 52 Table 3 26 0x084 Debug Low Byte Register
58. Configurations BIOS DIS14 FUNCTION SIGNAL ROUTING Boot from on module P2020 eSPI chip select SPI CS2it is available Open flashes on the carrier P2020 eSPI chip select SPI_CSO boot chip Pulled to GND Boot from external flash select is available on the carrier The BIOS_DISO signal defined in the COM Express Base specification is not used on the COMe cP2020 2 5 2 9 Serial Interface The COMe cP2020 provides two UART interfaces which makes the following configuration possible 2x 4 wire UARTs manufacturer preset 2 5 2 10 SMB 12 The COMe cP2020 supports two I2C controllers with speeds up to 400 kHz for customer usage The signals the COM Express connector labeled SMB CK and SMB_DAT are connected to I2C controller 1 of the P2020 The resources occupied for the on board devices are as follows Table 2 9 On Board Device Resource DEVICE I2C User EEPROM 1010 110x OxAC System EEPROM 1010 111x OxAE RTC 1010 001x 0 2 Thermal Sensor 1001 000x 0x90 SPD EEPROM 1010 000x OxAO The signals on the COM Express connector labeled I2C CK and I2C DAT are connected to I2C controller IIC2 of the P2020 This controller is completely dedicated to user purposes www kontron com COMe P2020 User Guide 2 5 2 11 IRQs The COMe cP2020 provides five IRQ inputs which can be configured for edge level high and low active usage The opera tional mode of the IRQs is progr
59. Core 1 clock frequency is greater than 1000 MHz Register value is no more used to force CPU strapping but register is used for checksum calculation write Register value to 0x00 Equivalent CPU strapping is hard coded in CPLD depends on board vari ant Table 3 19 0 00 User SerDes OLL Time out Enable Register ACTION D7 06 05 D4 D3 D2 D1 DO READ NU NU NU NU NU NU NU cfg_srds_pll _toe WRITE NU NU NU NU NU NU NU cfg_srds_pll _toe POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 00 00 Enable PLL Lock time out counter The power on reset sequence waits for the SerDes PLL to lock while the time out counter has not expired 01 Disable PLL Lock time out counter The power on reset sequence waits indefinately for the SerDes PLL to Lock www kontron com Table 3 20 0x010 Serdes Multiplexer Control Register COMe P2020 User Guide ACTION D7 D6 D5 D4 D3 D2 D1 DO READ NU NU NU NU NU Sel2 Sel1 Sel1 WRITE NU NU NU NU NU Sel2 Sel1 Sel1 POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 02 00 5 0 Serdesit1 Multiplexer selection 0 CPU Serdes Lane 1 is connected to Carrier Serdes Lane 1 1 CPU Serdes Lane 1 is connected to Carrier Serdes Lane 4 Sel1 Serdesit2 Multiplexer selection 0 CPU Serdes Lane 2 is connected to Carrier Serdes Lane 2 1 CPU Serdes Lane 2 is connected to Carrier Serdes Lane 10 Sel2 Serde
60. D 0 0 0 0 0 0 CPPE1 CPPEO WRITE NU NU NU NU NU NU CPPE1 CPPEO POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 CPPEO PCIe slot 0 card request 0 Card is not present 1 Card is present 01 1 PCIe slot 1 card request 0 Card is not present 1 Card is present www kontron com COMe P2020 User Guide Table 3 62 0x351 PCIe Control Status Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 LANEREV 0 0 PERST1 PERSTO WRITE NU NU NU NU NU NU PERST1 PERSTO POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION D0 PERSTO PCIe slot 0 card reset 0 Card reset is not activ 1 Card reset is active Reset is automatically asserted when CPU is in reset state 01 PERST1 PCIe slot 1 card reset 0 Card reset is not activ 1 Card reset is active Reset is automatically asserted when CPU is in reset state D4 LANEREV PCIe Lane reversal 0 Lane reversal 15 not active 1 Lane reversal is active Table 3 63 0 370 Carrier Interrupt Direction Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 Dir4 Dir3 Dir2 Dirt Diro WRITE NU NU NU Dir4 Dir3 Dir2 Dirt Diro POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 Diro I0 Direction of line CON_IRQ 1 0 Line is used as Input and forces automatically UC_IRQ 7 line when enabled 1 Line is used as Output and driven by UC_IRQ 7 line D1 Dir1 1
61. Des expects a 125 MHz reference clock frequency 1 SerDes expects a 100 MHz reference clock frequency www kontron com COMe P2020 User Guide Table 3 45 0 306 Default eTSEC2 SGMII Mode Configuration Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ NU NU NU NU NU NU NU cfg sgmii2 WRITE NU NU NU NU NU NU NU NU POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 00 0 eTSEC2 Ethernet interface operates in SGMII mode and uses SGMII SerDes lane 2 pins 1 eTSEC2 Ethernet interface operates in standard parallel interface mode and uses the TSEC2 pins Table 3 46 0 307 Default eTSEC3 SGMII Mode Configuration Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ NU NU NU NU NU NU NU cfg_sgmii3 WRITE NU NU NU NU NU NU NU NU POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 00 0 eTSEC3 Ethernet interface operates in SGMII mode and uses SGMII SerDes lane 3 pins 1 eTSEC3 Ethernet interface operates in standard parallel interface mode and uses the TSEC3 pins Table 3 47 0x308 Default eTSEC1 Width Configuration Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ NU NU NU NU NU NU NU cfg tsec reduce WRITE NU NU NU NU NU NU NU NU POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 00 0 eTSEC1 and eTSEC2 Ethernet interfaces operate in reduced pin mode either RTBI RGMII or RMII mode 1 eTSEC1 and eTSEC2 Ethernet
62. Iex2 4 PCIex1 off off off PCIex1 SGMII SGMII 5 PCIex2 off off off SGMII SGMII 6 PCIex1 off off off SRIOx1 SGMII SGMII 7 SRIOx1 off off off SRIOx1 SGMII SGMII 8 SRIOx4 off off off 2 5 2 5 Local Bus GPIO 2 5 2 5 1 Local Bus The COMe cP2020 provides a local bus interface for connecting directly memory mapped parallel bus devices SRAM style The Local Bus implementation on the COMe cP2020 supports 8 bit and 16 bit data signal paths depending on the Local Bus chip select configuration and an 8Mbyte address range for each of the two Local Bus chip selects The Local Bus signals designated as LADO 15 incorporate multipexed address and data information whereby the Local Bus signals LA16 31 are dedicated address lines Please be aware that external address latches must be provided on the LAD8 15 lines if an address range greater than 64kB is to be addressed The numbering scheme for the Local Bus LA LAD pins is noted in Power Architecture style meaning that LADO is the most significant bit and LA31 is the least significant bit For a better understanding of the QorIQ P2020 Local Bus functionality and all the involved control signals please refer to the CPU s reference manual 2 5 2 5 2 GPIO The COMe cP2020 provides the possibility to convert part of the Interrupt signals to GPIO functionality There are 5 signals on the COM Express connector which can be multiplexed between Interrupt functionality and GPIO functionality 2 5 2 6 USB The COMe
63. Multicore programmable interrupt controller 2 2 Memory 2 2 1 DDR3 The COMe cP2020 supports a soldered single channel 72 bit Double Data Rate DDR3 memory with Error Checking and Correcting ECC running at up to 800 MHz memory error detection and reporting of 1 bit and 2 bit errors and correction of 1 bit failures The available memory configuration can be either 1 GB 2 GB or 4 GB 2 2 2 Flash Memory 2 2 2 1 SPI Boot Flash The COMe cP2020 provides two 2 MB SPI boot flashes for two separate U Boot images a standard SPI boot flash and a recovery SPI boot flash The fail over mechanism for the U Boot recovery can be controlled via the DIP switch SW1 switch 1 Refer to Chapter 6 10 for further information The SPI boot flashes include a hardware write protection option If write protection is enabled writing to the SPI boot flashes is not possible The U Boot code and settings are stored in the SPI boot flashes Changes made to the U Boot set tings are available only in the currently selected SPI boot flash Thus switching over to the other SPI boot flash may result in operation with different U Boot code and settings www kontron com COMe P2020 User Guide 2 2 2 2 SPI OS User Flash The COMe cP2020 supports 8 MB of soldered flash memory for the OS 2 2 2 3 NAND Flash The COMe cP2020 supports up to 2 GB of soldered NAND flash memory which is an SLC based NAND flash Tt is optimized for embedded systems providing
64. N COMMENT C49 IRO14 IRQ Undefined C50 IRQ2 IRQ Undefined C51 GND PWR GND C52 SERDES_RX8 SERDES N C C53 SERDES_RX8 SERDES N C C54 TYPEO TYPE Single 4K7 pull down DNI C55 SERDES_RX9 SERDES N C C56 SERDES_RX9 SERDES N C C57 TYPE1 TYPE Single 4K7 pull down DNI C58 SERDES_RX10 SERDES DP I MUX_PCIE_RX2_P C59 SERDES_RX10 SERDES DP I MUX PCIE RX2 N C60 GND PWR GND C61 SERDES_RX11 SERDES DP I MUX_PCIE_RX3_P C62 SERDES_RX11 SERDES DP I MUX_PCIE_RX3_N C63 RSVD19 Local Bus 0 3 3 LA25 C64 RSVD19 Local Bus 0 3 3 LA24 C65 SERDES_RX12 SERDES N C C66 SERDES_RX12 SERDES N C C67 RSVD19 Local Bus 0 3 3 LA23 C68 SERDES_RX13 SERDES N C C69 SERDES_RX13 SERDES N C C70 GND PWR GND C71 SERDES_RX14 SERDES N C C72 SERDES_RX14 SERDES N C C73 GND PWR GND C74 SERDES_RX15 SERDES N C C75 SERDES_RX15 SERDES N C C76 GND PWR GND C77 RSVD19 Local Bus 0 3 3 LA22 C78 SERDES RX164 SERDES N C C79 SERDES RX16 SERDES N C C80 GND PWR GND C81 SERDES RX174 SERDES N C C82 SERDES RX17 SERDES N C C83 RSVD19 Local Bus 0 3 3 LA21 C84 GND PWR GND C85 SERDES_RX18 SERDES N C C86 SERDES_RX18 SERDES N C C87 GND PWR GND C88 SERDES_RX19 SERDES N C C89 SERDES_RX19 SERDES N C C90 GND PWR GND C91 SERDES_RX20 SERDES N C C92 SERDES_RX20 SERDES N C C93 GND PWR GND C94 SERDES_RX21 SERDES N C C95 SERDES_RX21 SERDES N C C96 GND PWR GND
65. P2020 User Guide Table 3 59 0x339 CPU Control Register ACTION D7 06 05 04 03 02 01 00 0 0 0 0 0 0 0 0 WRITE NU NU NU NU CCntrl3 CCntrl2 CCntrl1 CCntrlo POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 CCntrlo Core 0 unconditional Debug request 0 no request 1 Debug request is triggered bit is set by CPU and self cleared by CPLD length is about 1us D1 CCntrl1 Core 1 unconditional Debug request 0 no request 1 Debug request is triggered bit is set by CPU and self cleared by CPLD length is about 1us 02 CCntrl2 Core 0 Machine check request 0 no request 1 Machine check request is triggered bit is set by CPU and self cleared by CPLD length is about 1us 03 CCntrl3 Core 1 Machine check request 0 no request 1 Machine check request is triggered bit is set by CPU and self cleared by CPLD length is about 1us Table 3 60 0x33A Board Variant Register ACTION READ BrdVar WRITE BrdVar POWER UP OxXX BITFIELD DESCRIPTION 00 07 BrdVar Register shows current Board Variant depends on strapping option Board Variant gt Strapping P2020 1200MHz 667MHz gt OxEO P2020 1000MHz 667MHz gt 0 00 P2020 1200MHz 800MHz gt OxE8 P2010 1200MHz 800MHz gt OxA8 P1020 800MHz 667MHz gt 0x40 Table 3 61 0 350 PCIe Status Register ACTION D7 D6 D5 D4 D3 D2 D1 DO REA
66. S The boot itself is initiated with the bootm command To perform autobooting of a VxWorks image requires that appropri ate U Boot environment variables or script s be defined for the boot operation to be performed For more detailed infor mation with examples of boot command sequences refer to the Kontron VxWorks BSP online documentation For more information on how to configure and build VxWorks images and how to utilize them e g for a subsequent VxWorks boot process please refer to the appropriate Wind River documentation www kontron com COMe P2020 User Guide 6 6 Getting Help U Boot was configured with support for longhelp This means that online help is available for every command while work ing with the system To access the online help enter or help at the console prompt This will show an overview of all available commands To get specific help enter command command group or help command command group For example to get help on the saves command enter saves gt saves saves save S Record file over serial line Usage saves off size baud save S Record file over serial line with offset off size size and baudrate baud To get help on the mmc command group enter mmc gt mmc mmc MMC sub system Usage mmc read device num addr blk cnt mmc write device num addr blk cnt mmc rescan device num mmc part device num lists available par
67. SMB_DAT B15 SMB_ALERT SMB 3 3 Interrupt Source B16 SATA1_TX SATA N C B17 SATA1 TX SATA N C B18 SUS_STAT BOARD CTRL 0 3 3 N C B19 SATA1_RX SATA N C B20 SATA1_RX SATA N C B21 GND PWR GND B22 SATA3_TX SATA N C 23 5 SATA N C B24 PWR OK BOARD CTRL 1 3 3 PWR_OK B25 SATA3_RX SATA N C 26 SATA3_RX SATA N C B27 WDT BOARD CTRL WDT B28 AC HAD_SDIN2 AUDIO N C B29 AC HAD_SIN1 AUDIO N C B30 AC HAD_SINO AUDIO N C B31 GND PWR GND B32 SPKR BOARD CTRL N C B33 2 CK 12C 1 0 3 3 I2C CK B34 I2C DAT 12C 1 0 3 3 I2C DAT B35 THERM BOARD CTRL 1 3 3 Interrupt Source B36 USB7 USB2 0 N C B37 USB7 USB2 0 N C B38 USB 4 5 OC USB2 0 N C B39 USB5 USB2 0 N C B40 USB5 USB2 0 N C B41 GND PWR GND B42 USB3 USB2 0 USB3 USB3 0 B43 USB3 USB2 0 USB3 USB3 0 B44 05 1 0 05 2 0 1 3 3 USB 01 0 USB3 0 www kontron com COMe P2020 User Guide Table 2 2 SIGNAL Connector J1 Row B Pinout Continued PIN SIGNAL GROUP TYPE TERMINATION COMMENT B45 USB1 USB2 0 USB1 USB3 0 B46 USB1 USB2 0 USB1 USB3 0 47 EXCD1_PERST EXP CARD 0 3 3 Undefined B48 EXCD1_CPPE EXP CARD I 3 3 Undefined B49 SYS_RESET BOARD CTRL 1 3 3 SYS_RESET B50 CB_RESET BOARD CTRL 0 3 3 C
68. TX1 N A57 GND PWR GND A58 SERDES_TX3 SERDES DP 0 SERDES TX3 4 A59 SERDES TX3 SERDES DP 0 SERDES TX3 A60 GND PWR GND A61 SERDES_TX2 SERDES DP 0 SERDES TX24 A62 SERDES TX2 SERDES DP 0 SERDES TX2 A63 GPI1 SD DATA1 GPIO SDIO 1 0 3 3 SD DATA1 A64 SERDES 1 SERDES DP 0 SERDES TX14 A65 SERDES TX1 SERDES DP 0 SERDES TX1 A66 GND PWR GND A67 GPI2 SD DATA2 GPIO SDIO 1 0 3 3 50 DATA2 A68 SERDES 0 SERDES DP 0 SERDES_TX0 A69 SERDES TXO SERDES DP 0 SERDES A70 GND PWR GND www kontron com COMe P2020 User Guide Table 2 1 SIGNAL Connector J1 Row A Pinout Continued PIN SIGNAL GROUP TERMINATION COMMENT A71 LVDS_A0 LVDS RSVD A72 LVDS_AO LVDS RSVD A73 LVDS_A1 LVDS RSVD A74 LVDS_A1 LVDS RSVD 75 LVDS_A2 LVDS RSVD A76 LVDS_A2 LVDS RSVD 77 lVDS VDD EN LVDS RSVD A78 LVDS_A3 LVDS RSVD A79 LVDS A3 LVDS RSVD A80 GND PWR GND A81 LVDS A LVDS RSVD A82 LVDS A CK LVDS RSVD A83 LVDS I2C CK LVDS RSVD A84 LVDS I2C DAT LVDS RSVD A85 GPI3 SD_DATA3 GPIO SDIO 1 0 3 3 SD_DATA3 A86 RSVD19 Local Bus 0 3 3 LA18 A87 RSVD19 Local Bus 0 3 3 LA17 A88 SERDES_CK_REF1 SERDES 0 3 3 SERDES_CK_REF A89 SERDES_CK_REF1 SERDES 0 3 3 SERDES_CK_REF A90 GND PWR GND A91 SPI POWER SPI 0
69. U NU cfg device id 5 7 POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 02 00 Device ID used for RapidIO hosts Table 3 16 0 00 User RapidIO System Size Register ACTION D7 D6 D5 04 03 02 01 00 READ NU NU NU NU NU NU NU cfg rio sys size WRITE NU NU NU NU NU NU NU cfg rio sys size POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION D0 00 Large system size up to 65 536 devices 01 Small system size up to 256 devices Table 3 17 0 000 User 0 Speed Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ NU NU NU NU NU NU NU cfg coreO sp eed WRITE NU NU NU NU NU NU NU cfg coreO sp eed POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION D0 00 Core 0 clock frequency is less than or equal to 1000 MHz 01 Core 0 clock frequency is greater than 1000 MHz Register value is no more used to force CPU strapping but register is used for checksum calculation write Register value to 0x00 Equivalent CPU strapping is hard coded in CPLD depends on board vari ant www kontron com COMe P2020 User Guide Table 3 18 0 00 User Core1 Speed Register ACTION D7 D6 D5 04 03 02 01 00 READ NU NU NU NU NU NU NU cfg corel sp eed WRITE NU NU NU NU NU NU NU cfg corel sp eed POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION D0 00 Core 1 clock frequency is less than or equal to 1000 MHz 01
70. able on request Cache structure 32kBinstruction cache for each e500 core 32 data cache for each e500 core 512 kB shared L2 cache Flash memory Two SPI boot flashes 2 x 2 MB for U Boot selectable via the DIP switch One 8 MB SPI flash for operating system or application Mass storage device Upto 2 GB flash via an integrated embedded flash controller Up to 32 GB microSDHC flash via an integrated SDHC controller MRAM memory 512 kB of non volatile memory Two serial EEPROMs with 64 kbit One for system data storage One free for user data storage www kontron com COMe P2020 User Guide Table 1 1 COMe cP2020 Main Specifications Continued COMe cP2020 SPECIFICATIONS Gigabit Ethernet Up to five Gigabit Ethernet ports Three Gigabit Ethernet port through COMe MDI interface Up to two Gigabit Ethernet ports through SGMIT interface SRIO Serial RapidIO interfaces operate in host or agent configuration in various speeds 1 25 GHz 2 5 GHz or 3 125GHz depending on configuration Oneinterface x1 One interface x4 Two interfaces x1 PCI Express PCI Express interface operates in host or agent at 2 5 GHz PCIe GEN1 de pending on configuration Oneinterface x1 Oneinterface x2 INTERCONNECTION Oneinterface x4 Twointerfaces x1 Twointerfaces x2 Threeinterfaces x1 x1 x2 Debug Interface One debug port Serial In
71. ammed via the Carrier Interrupt Mode1 and Carrier Interrupt Mode2 registers Refer to Chapter 3 for further information The following figure demonstrates the IRQ routing of the COMe cP2020 Figure 2 1 IRQ Routing Scheme U_IRQ7 11 2 5 2 12 Miscellaneous MISC These signals are normally pre defined for an X86 architecture board and have no defined functionality on Power Architec ture CPUs On the COMe cP2020 these signals may be used as gerneral purpose output 2 5 3 JTAG Debug Interface The COMe cP2020 provides one JTAG Debug connector J4 to facilitate software debugging using an emulation probe The connector type is 1x20_SAMTECH_ZF www kontron com COMe P2020 User Guide The following table provides pinout information for the debug connector J4 Table 2 10 JTAG Debug Connector J4 Pinout PIN SIGNAL FUNCTION 1 0 1 TDO JTAG data output 0 2 NC Not connected gt 3 TDI JTAG data input I 4 COP_TRST JTAG test reset I 5 NC Not connected 6 SENSE Analog connected to 3V3 7 TCK JTAG test clock I 8 CKSTOP IN4 COP checkstop input I 9 TMS JTAG test mode select I 10 NC Not connected 11 COP_SOFT_RST COP soft reset I 12 GND Ground signal 13 COP_HARD_RST COP hard reset I 14 NC Not connected 15 COP_CKSTOP_OUT COP checkstop output 0 16 GND GND signal 17 NC Not connected 18 NC Not connected 19 NC Not connected 20 NC Not conne
72. and Usage 6 5 3 1 sconf select To change the setting invoke the sconf select command Example gt sconf select 7 Default configuration active 4 Base Serdes 0 Serdes 1 Serdes 2 Serdes 3 Config I Go SSS SSS SSS SSS SSS po SS SS SS SSS SSS SSS fo SSS SSS SSS SSS SSS 0S OFF OFF OFF OFF ee EET RE lt AS PETEA TORRE POIRXT 82 5 BC 2 92 5 lt gt 40 5 lt 4 82515 IC Ciel C2 ORRE SGMII SGMII lt B IC eI SGMII SGMII lt gt PETE 0025 IRC SF rO OI Ie SGMII SGMII 7 SRIOx1 62 5 H SRIOx1 82 5 H SGMII SGMII o8 SRIOx4 3 125H eTSEC2 configured in SGMII mode eTSEC3 configured in SGMII mode SRIO host mode device ID is 0 Boot ROM location is spi gt 6 5 3 2 sconf set The setting of the chosen base configuration can be changed via the sconf set command In the following example the sconf info command is used to show the current configuration After that sconf set etsec2 and sconf set etsec3 are used to configure RGMII mode www kontron com COMe P2020 User Guide gt sconf info Default configuration active Listing available base configurations 4 Base Serdes 0 Serdes
73. andard Board Variant 74 Table 4 4 Power Consumption vs Ambient Temperature Extended Temperature Board Variant 75 Table 6 1 Standard U Boot Commands Configured for the 2020 78 Table 6 2 Kontron Specific Commands 81 Table 6 3 LIC nm 82 Table6 4 kboardinfo Command 83 Tabl amp 6 5 md5sum Commando uev tna dinge eu OUS 84 Table 6 6 d ulIeTTT 85 Table 6 7 2 25 aa a RR Den aa 88 Table 6 8 Command iiiter orte rere de cence 89 Table 6 9 Naming Convertiotis 98 7 www kontron com COMe P2020 User Guide List of Figures Figure 1 1 COMe cP2020 Block Diagram 12 Figure 1 2 2020 Board Layout Top View 13 Figure 1 3 2020 Board Layout Bottom View 13 Figure 2 1 IRQ Routing Scheme e M 36 Figure 5 1 Cooling Solution COMe cP2020c
74. ation DESCRIPTION This command collects information from various board sources and provides a summary listing of this USAGE 1 Display board information gt kboardinfo Board id Hardware rev Logic rev Boot flash In system slot Geographic address Material number Serial number U Boot article name U Boot material num gt 0xd048 0 1 Standard Flash na na na na SK FIRM UBOOT D048 1053 5072 www kontron com COMe P2020 User Guide Table6 5 md5sum Command Creates or checks the md5 message digest over a memory area SYNTAX md5sum data address length lt cksum address gt md5sum command lt data address gt parameter hexadecimal start address of memory area lt length gt parameter hexadecimal length of memory area lt cksum address gt parameter hexadecimal If present compares the calculated md5 message digest with the md5 message digest available at this address If absent calculates the md5 message digest over the specified memory range and prints it to the console DESCRIPTION This command is used to create or check the md5 message digest over a memory area If the optional 3 parameter lt checksum address gt is omitted the md5 message digest is calculated over the specified memory range and printed to the console If the optional parameter lt cksum address gt is specified the md5 message dig
75. atus Register 0 ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 BFSS DIP4 DIP3 DIP2 DIP1 WRITE NU NU NU NU NU NU NU NU POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 DIP1 Dip Switch status of LED POST Code configuration SW 0 Off logic level is High 1 On logic level is Low 01 DIP2 Dip Switch status of BIOS Flash boot selection SW 0 Off logic level is High 1 On Logic level is Low D2 DIP3 Dip Switch status of SD Card Multiplexer tbd SW 0 Off logic level is High 1 2 On Logic level is Low 03 DIP4 Dip Switch status when LOW CPU starts with Default Configuration SW2 2 0 Off logic level is High 1 On logic level is Low D4 D5 BFSS U Boot Flash selection status 00 Standard boot Flash active 01 Recovery boot Flash active 10 External boot Flash active 11 Reserved Table 3 29 0 282 Control Register 0 ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 BFUS 0 0 0 0 0 WRITE NU NU BFUS NU NU NU NU NU POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION D5 BFUS Boot Flash update selection 0 active Boot Flash will not be changed 1 toggle between standard and recovery boot flash www kontron com Table 3 30 COMe P2020 User Guide 0x284 Device Protection Register
76. c Commands 81 6 4 lJ Boot Access and Startup treten haqa REN kaqpas Re TEE SEES VERE C 90 6 5 Working With U BOOT u uu ua M 90 6 5 1 General Operation 22252 2 saan o ehe 90 6 5 2 Using the sconf Command 90 6 5 3 Examples of sconf Command Usage 91 6 5 4 Using the Network 94 6 5 5 Using SD Cards 95 Spon BESIDES 95 6 5 7 Using the Onboard Flash 96 6 5 8 Using the SPI Flash for S uuu 97 6 5 9 05 Te cob uqa pe eere veste Sees oed 97 6 6 Getting Helpies E dae eene gei s 99 6 7 Update PC 99 6 8 RECOVERY MeclanisiTi icai Tone o 100 6 9 Copyrights and Licensing 100 6 10 Obtaining Source Code uu teh exe exe e exe EY eR de age 104 t Installation e 105 A 105 7 2 GeneralInstructions on Usage
77. cP2020 supports four USB 2 0 high speed USB ports The USB ports USBO 3 at the COM Express connectors are provided using a 4 port USB hub with its Uplink Port connected via an external USB PHY to the USB controller ULPIO Interface on the QorIQ P2020 2 5 2 7 SDHC SDIO The Freescale QorIQ CPUs incorporate an enhanced Secure Digital Host Controller eSDHC which provides support for Mul tiMediaCards MMC and Secure Digital SD Cards The interfacing signals of the CPU are multiplexed between the on board SD card socket and the dedicated SDIO signals on the COM Express connectors The selection between on board socket and external interfacing is done via the DIP Switch SW1 switch 1 www kontron com COMe P2020 User Guide 2 5 2 8 SPI The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard developed by Motorola that oper ates in full duplex mode Devices communicate in master slave mode where the master device initiates the data frame Mul tiple slave devices are allowed with individual slave select chip select lines Sometimes SPI is called a four wire serial bus contrasting with three two and one wire serial buses For a detailed signal description please refer to the COM Express base specification chapter 4 3 12 The COMe cP2020 supports boot from an external SPI flash Therefore it can be configured by pin B88 BIOS 151 for the following configurations Table 2 8 Signal
78. cation Configuration Register 58 Table 3 40 0x301 Default Host Agent Configuration Register 58 Table 3 41 0x302 Default I O Selection Register 59 Table 3 42 0x303 Default Boot Configuration Register 60 Table 3 43 0x304 Default Boot ROM Location Configuration Register 60 Table 3 44 0x305 Default SerDes Reference Clock Configuration Register 60 Table 3 45 0x306 Default eTSEC2 SGMII Mode Configuration Register 61 Table 3 46 0x307 Default eTSEC3 SGMII Mode Configuration Register 61 Table 3 47 0x308 Default eTSEC1 Width Configuration Register 61 Table 3 48 0x309 Default eTSEC2 Protocol Configuration Register Reserved See note 62 Table 3 49 Default eTSEC3 Protocol Configuration Register Reserved See note 62 Table 3 50 0 30 Default RapidIO Device ID Register 63 Table 3 51 0 30 Default RapidIO System Size Register 63 Table 3 52 Ox30D Default 0 Speed Register
79. cation data In terms of I Os the module interfaces the QorIQ specific I Os to the carrier board In addition to USB 2 0 ports there are also UART TxD RxD RTC and CTS and Gigabit Ethernet interfaces Flexible interface support is guaranteed by 4 SERDES lanes which can be configured according to application specific needs A comprehensive range of different combinations for example as PCIe x4 sRIO x4 and Serial Gigabit Media Inde pendent Interface SGMIT is available The COMe cP2020 targets high bandwidth telecommunication and data processing applications With its long term avail ability of more than 10 years it is also a good fit to be used in long life cycle network applications in the medical military and transportation markets Kontron offers two modules in standard and extended temperature range COMe cP2020c P2020NSN2MFC 1200 MHZ 2GByte 667 MHz DDR3 Memory 1GByte NAND e 0 C 60 Ambient Temperature Standard COMe Heatspreader COMe cP2020i P2020NXN2KFC 1000 MHZ 2GByte 667 MHz DDR3 Memory 1GByte NAND 40 C 85 C Ambient Temperature Extended 95x95 mm Forced Air Cooling Heatsink www kontron com COMe P2020 User Guide 1 2 Board Diagrams Figure 1 1 COMe cP2020 Block Diagram COMe P2020 COM Express module based on QorlQ P2020 Upto 2x sRIOxt or 3x PCle x1 x2 4 or 2x GbE SGMI N i 1 4 e DDR3 SDRAM 1 24 GBw ECC
80. cted www kontron com COMe P2020 User Guide 3 Configuration 3 1 DIP Switch Configuration The COMe cP2020 is equipped with one 4 bit DIP switch SW1 used for board configuration Table3 1 DIP Switch SW1 Configuration SWITCH SETTING DESCRIPTION 1 OFF Boot from the standard SPI boot flash ON Boot from the recovery SPI boot flash 2 OFF The SDHC interface is routed to the onboard MicroSD ON The SDHC interface is routed to the COM Express connectorResaerved 3 OFF Reserved ON 4 OFF Uses the SerDes configuration which is defined via the U Boot sconf command ON The COME P2020 uses a default SerDes configuration The default position for the above settings is OFF www kontron com COMe P2020 User Guide 3 2 Board Memory Map Table 3 2 COMe bP2020 Virtual and Physical Memory Address START ADDRESSES PCIe3 IO Oxffc20000 PCIe2 IO Oxffc10000 Oxe ffc10000 PCIe1 IO Oxffc00000 Oxe ffc00000 Onboard Logic Oxffc000000 Oxf_ff000000 CCSR Oxffe00000 Oxf_ffe00000 NAND 3 0xf8098000 Oxf f8098000 NAND 2 0 8090000 Oxf f8090000 NAND 1 Oxf8088000 Oxf_f8088000 NAND 0 0 8080000 0 8080000 MRAM Oxf8000000 0 f8000000 L2 SRAM Oxffd00000 Oxf_ffd00000 COMe 1 Oxf4000000 Oxf_f4000000 COMe0 0xf0000000 Oxf_f0000000 SRI02 0xd0000000 Oxd d0000000 SRIO1 0xc0000000 0 c0000000 PCIe3 Memory 0xb0000000 PCI
81. d in CPLD depends on board variant read value is always OxFE www kontron com COMe P2020 User Guide Table 3 53 0 30 Default Core1 Speed Register Reserved see note ACTION D7 D6 D5 D4 D3 D2 D1 DO READ NU NU NU NU NU NU NU cfg_core1_speed WRITE NU NU NU NU NU NU NU NU POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 0 Core 1 clock frequency is less than or equal to 1000 MHz Core 1 clock frequency is greater than 1000 MHz Equivalent CPU strapping is hard coded in CPLD depends on board variant read value is always OxFE Table 3 54 0 30 Default SerDes PLL Time out Enable Register ACTION D7 06 05 04 03 02 01 00 READ NU NU NU NU NU NU NU cfg srds pll toe WRITE NU NU NU NU NU NU NU NU POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 0 Enable PLL lock time out counter The power on reset sequence waits for the SerDes PLL to lock while the time out counter has not expired Disable PLL lock time out counter The power on reset sequence waits indefinately for the SerDes PLL to Lock Table 3 55 0 320 0 321 Scratchpad Registers 0 1 ACTION READ Scratchpad n WRITE Scratchpad n POWER UP OxXX BITFIELD DESCRIPTION 00 07 Scratchpad n Scratchpad registers 0 1 www kontron com COMe P2020 User Guide Table 3 56 0x322 0x327 Scratchpad Registers 2 7 Not
82. d in this product contains copyrighted software that is licensed under the GPL A copy of that license is included in this document beginning on page 5 You may obtain the complete corresponding source code from Kontron for a period of three years after our last shipment of this product Please contact Kontron for further assistance in obtaining the source code www kontron com COMe P2020 User Guide 7 Installation 7 1 Safety This Kontron product was developed and tested carefully to provide all features necessary to ensure its compliance with electrical safety requirements Tt was also designed for a long fault free life However the life expectancy of this product can be drastically reduced by improper treatment during unpacking and installation Therefore in the interest of personnel safety and of the correct operation of this product it is recommended to conform with the following guidelines Electronic boards and their components are sensitive to static electricity Therefore care must be taken during all handling operations and inspection of this product in order to ensure product integrity at all times Donothandlethis product out of its protective enclosure while itis not used for operational purposes unless itis oth erwise protected Whenever possible unpack or pack this product only at EOS ESD safe work stations Where a safe work station is not guaranteed itis important for the user to be electrically discharged befo
83. e in SGMII mode 10 The eTSEC3 controller operates using the RGMII protocol if not configured to operate in SGMII mode 11 The eTSEC3 controller operates using the RTBI protocol if not configured to operate in SGMII mode default Equivalent CPU strapping is hard coded in CPLD depends on board variant read value is always OxFC www kontron com COMe P2020 User Guide Table 3 50 0 30 Default RapidIO Device ID Register ACTION D7 D6 05 04 03 DO READ NU NU NU NU NU cfg device id 5 7 WRITE NU NU NU NU NU NU POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 00 02 Device ID used for RapidIO hosts Table 3 51 0 30 Default RapidIO System Size Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ NU NU NU NU NU NU NU cfg_rio_sys_size WRITE NU NU NU NU NU NU NU NU POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION D0 0 Large system size up to 65 536 devices 1 Small system size up to 256 devices Table 3 52 0 300 Default CoreO Speed Register ACTION D7 06 05 04 03 02 01 00 READ NU NU NU NU NU NU NU cfg coreO speed WRITE NU NU NU NU NU NU NU NU POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION D0 0 Core 0 clock frequency is less than or equal to 1000 MHz 1 Core 0 clock frequency is greater than 1000 MHz Equivalent CPU strapping is hard code
84. e on the terms of this License whose permissions for other licensees extend to the entire whole and thus to each and every part regardless of who wrote it Thus it is not the intent of this section to claim rights or contest your rights to work written entirely by you rather the intent is to exercise the right to control the distribution of derivative or collective works based on the Program In addition mere aggregation of another work not based on the Program with the Program or with a work based on the Program on a volume of a storage or distribution medium does not bring the other work under the scope of this License 3 You may copy and distribute the Program or a work based on it under Section 2 in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following a Accompany it with the complete corresponding machine readable source code which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange or b Accompany it with a written offer valid for at least three years to give any third party for a charge no more than your cost of physically performing source distribution a complete machine readable copy of the corresponding source code to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange or c Accompany it with the information you received as to the
85. e2 Memory 0xa0000000 0 0000000 PCIe1 Memory 0x80000000 0 80000000 DDR3 SDRAM 0x00000000 0x0 00000000 www kontron com COMe P2020 User Guide 3 3 1 0 Address Map For the COMe cP2020 the register address is composed of the base address of the Onboard Logic 4k indicated in the virtual memory map see Table XX and the respective address offset indicated in the 1 0 address map Table XX register address 0 0 0000 base address offset Table 3 3 1 0 Address Map ADDRESS FUNCTION 000h User Boot ROM Location Configuration Register 001h User Host Agent Configuration Register 002h User 1 0 Port Selection Register 003h User Boot Configuration Register 004h User Boot ROM Location Configuration Register 005h User SerDes Reference Clock Configuration Register 006h User eTSEC2 SGMII Mode Configuration Register 007h User eTSEC3 SGMII Mode Configuration Register 008h User eTSEC1 Width Configuration Register 009h User eTSEC2 Protocol Configuration Register 00Ah User eTSEC3 Protocol Configuration Register 00Bh User RapidIO Device ID Register 00Ch User RapidIO System Size Register 00Dh User Core0 Speed Register OOEh User Core1 Speed Register OOFh User SerDes PLL Time out Enable Register 010h Serdes Multiplexer Control Register 01th User Checksum Register 012h UFM Erase Control Register 013h UFM CPU Control and Status Register
86. ed by writing a 1 to the WTR bit In the eventa timeout occurs the WTE bit is set to 1 This bit can then be polled by the application and handled accordingly To continue using the Watchdog write a 1 to the WTE bit and then retrigger the Watchdog using WTR The WTE bit retains its setting as long as no power down up is done Therefore this bit may be used to verify the status of the Watchdog Reset mode This mode is used to force a hard reset in the event of a Watchdog timeout In addition the WTE bit is not reset by the hard reset which makes it available if necessary to determine the status of the Watchdog prior to the reset Interrupt mode This mode causes the generation of an interrupt in the event of a Watchdog timeout The interrupt han dling is a function of the application If required the WTE bit can be used to determine if a Watchdog timeout has occurred Dual stage mode This is a complex mode where in the event of a timeout two things occur 1 an interrupt is generated and 2 the Watchdog is retriggered automatically In the event a second timeout occurs following the first timeout a hard reset will be generated The second timeout period is the same as the first If the Watchdog is retriggered normally as spec ified above operation continues The interrupt generated at the first timeout is available to the application to handle the first timeout if required As with all of the other modes the WTE bit is available fo
87. ed in certain countries either by patents or by copyrighted interfaces the original copyright holder who places the Program under this License may add an explicit geo graphical distribution limitation excluding those countries so that distribution is permitted only in or among countries not thus excluded In such case this License incorporates the limitation as if written in the body of this License 9 The Free Software Foundation may publish revised and or new versions of the General Public License from time to time Such new versions will be similar in spirit to the present version but may differ in detail to address new problems or concerns Each version is given a distinguishing version number If the Program specifies a version number of this License which applies to it and any later version you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation If the Program does not specify a version number of this License you may choose any version ever published by the Free Software Foundation 10 Ifyouwish to incorporate parts of the Program into other free programs whose distribution conditions are differ ent write to the author to ask for permission For software which is copyrighted by the Free Software Foundation write to the Free Software Foundation we sometimes make exceptions for this Our decision will be guided by the two goals of preserving the
88. ented ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 0 0 0 WICF WRITE NU NU NU NU NU NU WICF POWER UP 0 0 0 0 0 0 00 BITFIELD DESCRIPTION 00 01 WICF Watchdog interrupt configuration 00 Watchdog is disabled 01 CPU IRQ 9 10 CPU IRQ 10 11 Reserved www kontron com COMe P2020 User Guide Table 3 33 0 288 Board ID High Byte Register ACTION READ Board Register High Byte 7 0 WRITE Board Register High Byte 7 0 POWER UP 1 1 0 1 0 0 0 0 BITFIELD DESCRIPTION 00 07 Board Register High Byte 7 0 Board Identification High Byte COMe P2020 0xD048 Table 3 34 0 289 Board and PLD Revision Register ACTION READ Revision Byte 7 0 WRITE Revision Byte 7 0 POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 07 Revision Byte 7 0 Board Revision identification Revision Byte 7 0 PLD Revision identification www kontron com COMe P2020 User Guide Table 3 35 0 28 Watchdog Timer Register ACTION READ WTE WMD WEN WTR WTM WRITE wic WMD WEN WTR WTM POWER UP 0 00 0 0000 BITFIELD DESCRIPTION 00 03 WTM Watchdog timeout settings 0000 0 125 0001 0 25 0010 0 5 0011 5 15 0100 225 0101 45 0110 8 5 0111 16 5 1000 32 1001 64 1010 128 5 1011 256 5 1100 5125 1101 1024 1110 20485 1111 40
89. er Guide Table 3 73 0x37D Board Interrupt Enable Register 4 ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 0 0 0 0 0 WRITE NU NU NU NU NU NU NU NU POWER UP 0 0 0 0 0 0 0 0 Register is read only read value is always 0x00 Table 3 74 0x380 Interrupt Multiplexer Register 1 ACTION READ MuxSel3 MuxSel2 MuxSel1 5 0 WRITE MuxSel3 MuxSel2 MuxSel1 5 0 POWER UP 0 0 1 1 0 0 1 0 BITFIELD DESCRIPTION 00 01 5 0 Interrupt GPIO Multiplexer for UC_IRQ 7 line connected to 00 line is not used 01 CON_IRQ 1 line 10 IRQ header line default state 11 Watchdog line D2 D3 MuxSel1 Interrupt GPIO Multiplexer for UC_IRQ 8 line connected to 00 line is not used 01 CON_IRQ 2 line 10 IRQ header line 11 Watchdog line D4 D5 MuxSel2 Interrupt GPIO Multiplexer for UC_IRQ 9 line connected to 00 line is not used 01 CON_IRQ 3 line 10 IRQ header line 11 Watchdog line default state D6 D7 MuxSel3 Interrupt GPIO Multiplexer for UC_IRQ 10 line connected to 00 line is not used 01 CON_IRQ 4 line 10 IRQ header line 11 Watchdog line Table 3 75 0x381 Interrupt Multiplexer Register 2 ACTION READ 00 00 00 MuxSel5 WRITE NU NU NU MuxSel5 POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 01 MuxSe
90. er version www kontron com COMe P2020 User Guide 6 3 Kontron Specific Commands Kontron s implementation of U Boot includes certain enhancements to provide specific functions not incorporated in the standard U Boot The following table provides a complete listing of all Kontron specific U Boot commands implemented on the COMe cP2020 Table 6 2 Kontron Specific Commands COMMAND DESCRIPTION FLash SWitch flsw Indicates or selects the currently active SPI boot flash Kontron Board Information kboardinfo 22 Displays a summary of board and configuration information Message digest 5 checksum md5sum Creates or checks the md5 message digest over a memory area Kontron Board Configuration sconf Provides functions for software based configuration of external interfaces available on the COM Express connectors tlbdb Translation Look aside Buffer DeBuG 1 Displays current configuration of TLBO and TLB1 Vital Product Data vpd Provides display and importing functions for vital product data entities The following tables provide command syntax reference information a short description and in some cases usage exam ples Where an ellipsis appears in the command syntax it means that the command is continued on the next line Observe spaces before the ellipsis www kontron com COMe P2020 User Guide Table 6 3 flsw Command Indicates or selects the currently act
91. erDes lanes 0 1 SGMII eTSEC2 x1 1 25 Gbps SerDes lane 2 SGMII eTSEC3 x1 1 25 Gbps SerDes lane 3 www kontron com COMe P2020 User Guide Table 3 7 0x003 User Boot Configuration Register ACTION D7 06 05 D4 D3 D2 D1 DO READ NU NU NU NU NU NU cfg_cpu0 1_boot WRITE NU NU NU NU NU NU cfg_cpu0 1_boot POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 01 00 00 CPU boot holdoff mode for both cores The e500 cores are prevented from booting until configured by an external master 01 e500 core 1 is allowed to boot without waiting for configuration by an external master while e500 core 0 is prevented from booting until configured by an external master or the other core 10 e500 core 0 is allowed to boot without waiting for configuration by an external master while e500 core 1 is prevented from booting until configured by an external master or the other core 11 Both e500 cores are allowed to boot without waiting for configuration by an external master Table 3 8 0 004 User Boot Sequencer Configuration Register ACTION 07 READ NU NU NU NU NU NU cfg boot seq 0 1 WRITE NU NU NU NU NU NU cfg boot seq 0 1 POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 01 00 00 Reserved 01 Normal I2C addressing mode is used Boot sequencer is enabled and loads configuration information from a ROM on the I2C1 interface A valid ROM
92. est is calculated over the specified memory range and compared with the md5 message digest at lt cksum address gt If the digest is identical the command returns 0 if the digests do not match a value other than zero is returned When a comparison is made nothing is printed to the console since this usage of the command is meant to be used within scripts The md5 message digest at lt cksum address gt may be specified in ASCII or binary format USAGE 1 Calculate an md5 message digest md5sum 100000 80000 8 e7006660a2d 22 65b7cd707eb98786 gt 2 Check the md5 message digest of a file previously loaded to 100000 with a size of 80000 and its md5 message digest loaded to 10000 in a script gt setenv check crc if md5sum 100000 80000 10000 then echo md5 message digest OK else echo md5 message digest BAD fi run check crc md5 message digest OK gt www kontron com COMe P2020 User Guide Table6 6 Command sconf Provides functions for configuration of external interfaces SYNTAX sconf info select num set lt par gt val clear save undo raw X byteO bytell bytel6 sconf command info option displays available configurations select option selects base configuration num lt num gt parameter decimal 0 1 8 number of base configuration set option indicate or configure parameter for new base configuration lt par gt
93. et all of these conditions a You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change b You must cause any work that you distribute or publish that in whole or in part contains or is derived from the Program or any part thereof to be licensed as a whole at no charge to all third parties under the terms of this License c Ifthe modified program normally reads commands interactively when you must cause it when started running for such interactive use in the most ordinary way to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty or else saying that you provide a warranty and that users may redistribute the program under these conditions and telling the user how to view a copy of this License Exception if the Program itself is interactive but does not normally print such an announcement your work based on the Program is not required to print an announcement These requirements apply to the modified work as a whole If identifiable sections of that work are not derived from the Program and can be reasonably considered independent and separate works in themselves then this License and its terms do not apply to those sections when you distribute them as separate works But when you distribute the same sec tions as part of a whole which is a work based on the Program the distribution of the whole must b
94. fined 055 SERDES_TX9 SERDES N C 056 SERDES_TX9 SERDES N C D57 2 TYPE 0 Single 4K7 pull down DNI D58 SERDES_TX10 SERDES DP 0 MUX PCIE TX2 P D59 SERDES_TX10 SERDES DP 0 MUX PCIE TX2 N D60 GND PWR GND 061 SERDES_TX11 SERDES DP 0 MUX PCIE TX3 P D62 SERDES_TX11 SERDES DP 0 MUX PCIE TX3 D63 RSVD19 Local Bus 0 3 3 LA27 D64 RSVD19 Local Bus 0 3 3 LA26 D65 SERDES_TX12 SERDES N C D66 SERDES_TX12 SERDES N C 067 GND PWR GND D68 SERDES_TX13 SERDES N C 069 SERDES_TX13 SERDES N C 070 GND PWR GND 071 SERDES_TX14 SERDES N C D72 SERDES_TX14 SERDES N C 073 GND PWR GND 074 SERDES_TX15 SERDES N C D75 SERDES_TX15 SERDES N C 076 GND PWR GND 077 IRQ5 IRQ 1 3 3 Undefined D78 SERDES_TX16 SERDES N C 079 SERDES_TX16 SERDES N C 080 GND PWR GND 081 SERDES_TX17 SERDES N C D82 SERDES_TX17 SERDES N C 083 TYPE3 TYPE 0 Single 4K7 pull down DNI 084 GND PWR GND D85 SERDES_TX18 SERDES N C D86 SERDES_TX18 SERDES N C 087 GND PWR GND 088 SERDES_TX19 SERDES N C 089 SERDES_TX19 SERDES N C D90 GND PWR GND D91 SERDES_TX20 SERDES N C D92 SERDES_TX20 SERDES N C 093 GND PWR GND 094 SERDES_TX21 SERDES N C D95 SERDES_TX21 SERDES N C 096 GND PWR GND www kontron com COMe P2020 User Guide Table2 4 Connector J2 Row D Pinout Continued SIGNAL
95. finition of IRQ 5 H line 00 edge triggered high to Low falling edge 01 edge triggered low to high rising edge 10 level triggered low active 11 level triggered high active www kontron com COMe P2020 User Guide Table 3 66 0x376 Board Interrupt Pending Register 1 ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 Int4 Int3 Int2 Inti Into WRITE NU NU NU wic wic wic wic wic POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 Into Interrupt occurred triggered by CON_IRQ 1 line Register is cleared by write to 1 0 no Interrupt 1 2 Interrupt is active D1 Inti Interrupt occurred triggered by IRQ 2 4 line Register is cleared by write 1 0 no Interrupt 1 Interrupt is active D2 Int2 Interrupt occurred triggered by IRQ 3 4 line Register is cleared by write 1 0 no Interrupt 1 Interrupt is active D3 Int3 Interrupt occurred triggered by IRQ 4 4 line Register is cleared by write 1 0 no Interrupt 1 Interrupt is active 04 Int4 Interrupt occurred triggered by IRQ 5 4 line Register is cleared by write 1 0 no Interrupt 1 Interrupt is active Table 3 67 0 377 Board Interrupt Pending Register 2 ACTION D7 D6 D5 D4 D3 D2 D1 DO READ Int7 Int6 Int5 Int4 Int3 Int2 Inti Into WRITE wic w
96. flash environment area are overwritten USAGE 1 Display all VPD entities gt print response displays all VPD entities gt 2 Display ethladdr entity gt print ethladdr ethladdr 00 80 82 47 12 02 gt 3 Import eth1addr entity to environment gt import ethladdr import ethladdr 00 80 82 47 12 02 to environment gt 4 Import all VPD entities to environment gt import all params response displays all imported VPD entities format for each imported VPD entity as follows gt import name value to environment import name value to environment gt www kontron com COMe P2020 User Guide 6 4 U Boot Access and Startup Communication with U Boot is achieved via a serial console configured for 115200 baud 8N1 no hardware handshake Initially U Boot executes the commands defined in the environment variable preboot Then if not otherwise inter rupted U Boot pauses for the time defined in the environment variable bootdelay and then executes the statements stored in the environment variable bootcmd To gain access to the U Boot command prompt type in any single character during the boot delay time If required the boot delay function can be configured in such a way that even when the boot delay is set to 0 to have characters which are sent over the serial interface prior to the boot wait time be recognized to allow operator
97. he COM Express connector Table 4 1 Supply Voltages 10 8V 13 2V wee 12V nominal RTC 2 5V 3 3V The RTC voltage is not mandatory for operation 4 2 Power Supply Rise Time The input voltages shall rise from 10 of nominal to within the regulation ranges within 0 1ms to 20ms There must bea smooth and continuous ramp of each DC input voltage from 10 to 90 of its final set point as specified in the ATX specifi cation 4 3 Supply Voltage Ripple The supply voltage ripple must not be greater than 100 mV peak to peak 0 20 MHz 4 4 Power Consumption The maximum power consumption of the COMe cP2020 is a function of clock frequencies workload utilization tempera ture and component variations tolerances The following tables indicate the typical power consumption of the COMe cP2020 with 1 2 GHz core clock and 2GB DDR3 memory under various conditions Table 4 2 Workload Dependency APPLICATIONS POWER CONSUMPTION U Boot idle 7 4 W Linux idle 6 1W Linux with memtester 9 6W Table 4 3 Power Consumption vs Ambient Temperature Standard Board Variant AMBIENT AIR TEMPERATURE 12V RAIL LOAD POWER CONSUMPTION DE 0 72 8 6W 25 0 80 9 6W 60 0 83 10 0 W www kontron com COMe P2020 User Guide Table 4 4 Power Consumption vs Ambient Temperature Extended Temperature Board Variant SEINE 12V RAIL LOAD POWER CONSUMPTION 40
98. he carrier board and where appropriate attachment of the combined assembly to a chassis wall a heatpipe or other such devices The heatspreader of the COMe cP2020 has four threaded mounting holes for attaching cooling solutions as indicated in the figure below Screws used for mounting must not extend beyond the bottom side of the heatspreader when installed oth erwise damage to the COMe cP2020 will result The torque applied to these screws when assembling must not exceed 0 7 Nm www kontron com CORPORATE OFFICES Europe Middle East amp Africa Oskar von Miller Str 1 85386 Eching Munich Germany Tel 49 0 8165 77 777 Fax 49 0 8165 77 219 info kontron com North America 14118 Stowe Drive Poway CA 92064 7147 USA Tel 1 888 294 4558 Fax 1 858 677 0898 info us kontron com COMe P2020 User Guide Asia Pacific 17 Building Block 1 ABP 188 Southern West 4th Ring Road Beijing 100070 P R China Tel 86 10 63751188 Fax 86 10 83682438 info kontron cn www kontron com All data is for information purposes only and not guaranteed for legal purposes Subject to change without notice Information in this datasheet has been carefully checked and is believed to be accurate However no responsability is assumed for inaccurancies All brand or product names are trademarks or registered trademarks of their respective owners User Guide COMe cP2020
99. he eTSEC2 controller operates using the TBI protocol or RTBI if configured in reduced mode if not configured to operate in SGMII mode Register value is no more used to force CPU strapping but register is used for checksum calculation write Register value to 0x00 Equivalent CPU strapping is hard coded in CPLD depends on board vari ant value is 10b Table 3 14 0x00A User eTSEC3 Protocol Configuration Register ACTION D7 D6 D5 D4 D3 D2 D1 00 READ NU NU NU NU NU NU cfg tsec2 prto 0 1 WRITE NU NU NU NU NU NU cfg tsec2 prto 0 1 POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 01 00 00 Reserved 01 The eTSEC3 controller operates using the RMII protocol if not configured to operate in SGMII mode 10 The eTSEC3 controller operates using the RGMII protocol if not configured to operate in SGMII mode 11 The eTSEC3 controller operates using the RTBI protocol if not configured to operate in SGMII mode default Register value is no more used to force CPU strapping but register is used for checksum calculation write Register value to 0x00 Equivalent CPU strapping is hard coded in CPLD depends on board vari ant value is 10b www kontron com COMe P2020 User Guide Table 3 15 0 00 User RapidIO Device ID Register ACTION D7 D6 D5 04 03 02 bi 00 READ NU NU NU NU NU cfg device id 5 7 WRITE NU NU NU N
100. hrotate is lost after a reset To retain the environment permanently use the com mand saveenv which saves the complete environment to flash www kontron com COMe P2020 User Guide 6 5 4 2 Contacting the Server In addition to be able to transfer files from a tftp server to a module the module s IP address environment variable Spaddr and the IP address of the server must be set environment variable serverip Alternatively itis possible to use the dhcp or bootp commands They can be set using the setenv command Please note that these settings are lost after a reset To retain the environ ment permanently use the command saveenv which saves the complete environment to flash To transfer a file from a tftp server to memory the tftpboot command is used for example gt tftpboot 100000 filename gt 6 5 5 Using SD Cards SD cards are supported read only with the ext2 or fat file system In both cases the card must be rescanned first gt mmc rescan O0 gt After that the contents can be verified with gt ext21s mmc 0 gt in case of the ext2 file system or with gt fatls mmc 0 gt in case of the fat file system To load a file into memory the commands ext2load or fatload can be used for example gt ext2load mmc 0 100000 kernel bin gt which loads the file kernel bin from the SD card to memory address 0x100000 6 5 6 Using USB Dev
101. ic wic wic wic wic wic wic POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 Into Interrupt occurred triggered by CON_SMB_ALERT line Register is cleared by write to 1 0 no Interrupt 1 Interrupt is active 01 Inti Interrupt occurred triggered by LM73 TEMP ALERT line Register is cleared by write 1 0 no Interrupt 1 Interrupt is active D2 Int2 Interrupt occurred triggered by CON_THERM line Register is cleared by write to 1 0 no Interrupt 1 Interrupt is active D3 Int3 Interrupt occurred triggered by PWR OK line Register is cleared by write to 1 0 no Interrupt 1 Interrupt is active 04 Int4 Interrupt occurred triggered by CON BATLOW line Register is cleared by write to 1 0 no Interrupt 1 Interrupt is active D5 Int5 Interrupt occurred triggered by RTC_INT line Register is cleared by write to 1 0 no Interrupt 1 Interrupt is active D6 Init6 Interrupt occurred triggered by CON_WAKEO line Register is cleared by write to 1 0 no Interrupt 1 Interrupt is active D7 Init7 Interrupt occurred triggered by 1 line Register is cleared by write to 1 0 no Interrupt 1 Interrupt is active www kontron com Table 3 68 0x378 Board Interrupt Pending Register 3 COMe P2020 User Guide
102. ices USB devices are supported read only with the ext2 or fat file system In both cases the USB devices must be initialized first gt usb start gt www kontron com COMe P2020 User Guide After that the contents can be verified with gt ext21s usb 0 gt in case ofthe 2 file system or with gt fatls usb 0 gt in case of the fat file system To load a file into memory the commands ext2load or fatload can be used for example gt ext2 load usb 0 1000000 kernel bin gt which loads the file kernel bin from the USB device to memory address 0x1000000 6 5 7 Using the Onboard NAND Flash The onboard NAND Flash is supported with the ubi filesystem The access is read only Thus the filesystem and its con tents must be prepared with Linux first As a prerequisite the environment variables mtdids and mtdparts must be set correctly mtdids identifies the NAND chip to use while mtdparts defines the partitions Example gt setenv mtdids 0 gt setenv mtdparts mtdparts chipl all gt This defines the first NAND chip 0 to be used with the name chip1 The chip contains one partition all which occupies the whole chip The next command sets the partition all to be used with the ubi layer ubi part all gt Now an ubi volume can be mounted in this example volume boot ubif
103. implemented ACTION READ Scratchpad n WRITE Scratchpad n POWER UP OxXX BITFIELD DESCRIPTION 00 07 Scratchpad n Scratchpad registers 2 7 Table 3 57 0x330 Power Status Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 PStat4 PStat3 PStat2 PStat1 PStatO WRITE NU NU NU NU NU NU NU NU POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 5 0 V VCORE Power good status 0 Power is not good 1 Power is good 01 PStat1 V_1V2 Power good status 0 Power is not good 1 Power is good D2 PStat2 V_1V5 Power good status 0 Power is not good 1 Power is good D3 PStat3 V_2V5 Power good status 0 Power is not good 1 Power is good D4 PStat4 V 3V3 Power good status 0 Power is not good 1 Power is good Table 3 58 0x338 CPU Status Register ACTION READ ConfMode 0 0 0 0 Stat2 Stati Stato WRITE NU NU NU NU NU NU NU NU POWER UP 0 0 0 0 0 x x x BITFIELD DESCRIPTION 00 5 0 ASLEEP status bit 0 ASLEEP not asserted 1 ASLEEP asserted 01 PStat1 Core 0 Ready bit 0 Core 0 is not ready 1 0 is ready 02 PStat2 Core 1 Ready bit 0 Core 1 is not ready 1 Core 1 is ready D7 ConfMode Show status of CPU Configuration Mode 0 Default Mode is active 1 User Mode is active www kontron com COMe
104. ing the Program or a portion of it either verbatim or with modifica tions and or translated into another language Hereinafter translation is included without limitation in the term modification Each licensee is addressed as you Activities other than copying distribution and modification are not covered by this License they are outside its scope The act of running the Program 15 not restricted and the output from the Program is covered only if its con tents constitute a work based on the Program independent of having been made by running the Program Whether that is true depends on what the Program does 1 You may copy and distribute verbatim copies of the Program s source code as you receive it in any medium pro vided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and dis claimer of warranty keep intact all the notices that refer to this License and to the absence of any warranty and give any other recipients of the Program a copy of this License along with the Program You may charge a fee for the physical act of transferring a copy and you may at your option offer warranty protec tion in exchange for a fee www kontron com COMe P2020 User Guide 2 You may modify your copy or copies ofthe Program or any portion of it thus forming a work based on the Program and copy and distribute such modifications or work under the terms of Section 1 above provided that you also me
105. ion dhcp Boot image via network using DHCP TFTP protocol echo Echo args to console editenv Edit environment variable env Environment handling commands www kontron com COMe P2020 User Guide Table 6 1 Standard U Boot Commands Configured for the COMe cP2020 Continued COMMAND DESCRIPTION exit Exit script ext2load Load binary file from an Ext2 filesystem ext2ls List files in a directory default false Do nothing unsuccessfully fatinfo Print information about filesystem fatload Load binary file from a dos filesystem fatls List files in a directory default fdt Flattened device tree utility commands fsinfo Print information about filesystems fsload Load binary file from a filesystem image go Start application at address addr help Print command description usage i2c I2C subsystem iminfo Print header information for application image imxtract Extract a part of a multi image interrupts Enable or disable interrupts irqinfo Print information about IRQs itest Return true false on integer compare loadb Load binary file over serial line kermit mode loads Load S Record file over serial line loady Load binary file over serial line ymodem mode loop Infinite loop on address range ls List files in a directory default md Memory display mdio MDIO utility commands mii utility commands mm Memo
106. ive SPI boot flash SYNTAX flsw slr flsw command Issuing the command without arguments will indicate the currently active SPI boot flash Also returns true or false depending on the currently active flash s option standard Selects the standard SPI boot flash as the active flash r Option recovery Selects the recovery SPI boot flash as the active flash DESCRIPTION This command is used to determine the currently active SPI boot flash or to select either the Standard SPI boot flash or the Recovery SPI boot flash as the currently active flash In addition this command returns true if the Standard SPI boot flash is selected or false if the Recovery SPI boot flash is selected This is used in the update scripts to prevent the Recovery SPI boot flash from being updated Besides this command the currently active SPI boot flash may also be selected by the DIP Switch SW1 switch 2 For further information refer to Chapter 3 1 Table xx The output of this command always shows the current state USAGE 1 Query flash status gt flsw standard boot flash active gt 2 Select the standard SPI boot flash as currently active flash gt flsw s gt www kontron com COMe P2020 User Guide Table 6 4 kboardinfo Displays a summary of board and configuration information kboardinfo Command SYNTAX kboardinfo kboardinfo command inform
107. l5 Interrupt GPIO Multiplexer for UC_IRQ 11 line connected to 00 line is not used 01 CON_IRQ 5 line 10 IRQ header line 11 Watchdog line www kontron com COMe P2020 User Guide Table 3 76 0 390 Carrier Control Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 Cntrl4 Cntrl3 Cntrl2 Cntrl1 0 WRITE NU NU NU Cntrl4 Cntrl3 Cntrl2 Cntrl1 Cntro POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION 00 0 Control register for line con cb reset n 0 line is deasserted logic level is HIGH 1 line is asserted logic level is LOW 01 1 Control register for line con thermtrip n 0 line is deasserted logic level is HIGH 1 line is asserted logic level is LOW D2 Cntr2 Control register for line con sus stat n 0 line is deasserted logic level is HIGH 1 line is asserted logic level is LOW 03 Cntr3 Control register for line con sus s3 n 0 line is deasserted logic level is HIGH 1 line is asserted logic level 15 LOW D4 Cntr4 Control register for line con_sus_s4_n 0 line is deasserted logic level is HIGH 1 line is asserted logic level 15 LOW Control Register is set and reset by CPU www kontron com COMe P2020 User Guide 4 Power Considerations 4 1 Electrical Specifications 4 1 1 Supply Voltage Following supply voltage is specified at t
108. must be present 10 Extended 2 addressing mode is used Boot sequencer is enabled and loads configuration information from a ROM on the I2C1 interface A valid ROM must be present 11 Boot sequencer is disabled No I2C ROM is accessed Table 3 9 0x005 User SerDes Reference Clock Configuration Register ACTION T READ NU NU NU NU NU NU NU cfg_srds_refclk WRITE NU NU NU NU NU NU NU cfg_srds_refclk POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION D0 0 SerDes expects a 125 MHz reference clock frequency 1 SerDes expects a 100 MHz reference clock frequency www kontron com COMe P2020 User Guide Table 3 10 0 006 User eTSEC2 SGMII Mode Configuration Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ NU NU NU NU NU NU NU cfg_sgmii2 WRITE NU NU NU NU NU NU NU cfg_sgmii2 POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 00 0 eTSEC2 Ethernet interface operates in SGMII mode and uses SGMII SerDes lane 2 pins 1 eTSEC2 Ethernet interface operates in standard parallel interface mode and uses the TSEC2 pins Table 3 11 0 007 User eTSEC3 SGMII Mode Configuration Register ACTION D7 D6 D5 04 D3 D2 D1 DO READ NU NU NU NU NU NU NU cfg_sgmii3 WRITE NU NU NU NU NU NU NU cfg_sgmii3 POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 00 0 eTSEC3 Ethernet interface operates in SGMII
109. on line documentation of all of U Boot s standard features 6 2 Standard U Boot Commands U Boot is provided with a set of standard commands for which documentation is available on the DENX web site Some of the standard commands have sub groups which can be displayed when help for the main group command is requested Where relevant further information concerning the usage of standard commands is provided in this guide to assist users in performing specific functions The following table indicates the standard U boot commands configured for the COMe cP2020 The blue shaded table cells indicate standard U Boot commands tested by Kontron Only the standard U Boot commands relevant for the normal oper ation of the COMe cP2020 U Boot bootloader have been tested by Kontron Table 6 1 Standard U Boot Commands Configured for the COMe cP2020 COMMAND DESCRIPTION 2 Alias for help base Print or set address offset bdinfo Print board Info structure boot Boot default i e run bootcmd bootd Boot default i e run bootcmd bootelf Boot from an ELF image in memory bootm Boot application image from memory bootp Boot image via network using BOOTP TFTP protocol bootvx Boot vxWorks from an ELF image chpart Change active partition cmp Memory compare coninfo Print console devices and information cp Memory copy cpu Multiprocessor CPU boot manipulation and release crc32 Checksum calculat
110. parameter ascii string lt gt parameter for new base configuration val parameter ascii string lt gt value assigned to par clear option clear user config settings in glue logic and reboot save option saves the current settings undo option undo current changes not yet saved DESCRIPTION This command is used to configure external interfaces available on the COMe cP2020 s connectors The sconf info command shows the possible configurations as well as the currently selected configuration The active configuration is indicated by characters in the sconf info output messages To configure external interfaces select a base configuration via the sconf select command Then the parameters can be defined more exactly by the sconf set lt gt subcommands To apply the configuration invoke the sconf save command After having updated the configuration in the glue logic a module powercycle is performed automatically a hardware reset is not sufficient to activate the new configuration www kontron com COMe P2020 User Guide Table 6 6 sconf Command Continued USAGE 1 Display available configurations gt sconf info Default configuration active Listing available base configurations Serdes 0 Serdes 1 Serdes 2 Serdes 3 Config 0 OFF OFF OFF OFF lt 1 gt POCIEx4 82 5 R
111. r The P2020 SerDes lane routing is shown in the following table Table 2 6 P2020 SerDes Lane Routing P2020 SerDes COMe Connector Port CPLD CPLD Control Line Control Line Lane 1 SERDES_TX RX 1 SERDES_TX RX 4 Lane 2 SERDES_TX RX 2 SERDES_TX RX 10 Lane 3 SERDES_TX RX 3 SERDES_TX RX 11 The logical protocols which run on the SerDes lanes are specified by strapping options P2020 CPU read at system powerup To obtain a complete overview about all theoretical protocol combinations please refer to the Freescale P5020 QorIQ Integrated Multicore Communication Processor Family Reference Manual Chapter 3 5 11 SerDes Lane Assignments and Multiplexing To handle the SerDes configuration in a more comfortable way Kontron provides the configuration tool sconf sconf provides a very easy way to configure the functionality of the SerDes lanes Refer to Chapter 6 U Boot for further infor mation www kontron com COMe P2020 User Guide The following SerDes protocol combinations can be selected by using the sconf command Table 2 7 SerDes Protocol Mapping COMe CONNECTOR SERDES_ SERDES_ SERDES_ SERDES_ SERDES_ SERDES_ SERDES_ TX RX 0 TX RX 1 TX RX 2 TX RX 3 TX RX 4 TX RX 10 TX RX 11 1 off off off off off off off 2 PCIex1 off off off 1 2 3 2 off off off PC
112. r application use Pin B27 on the COM Express J1 connector offers a signal that can be asserted when a Watchdog timer has not been trig gered within time Tt can be configured to any of the 2 stages Deassertion of the signal is automatically done after reset If deassertion during runtime is necessary please contact Kontron for further assistance 2 5 Connectors 2 5 1 COM Express Connectors Table 2 1 Connector J1 Row A Pinout PIN SIGNAL oe TYPE TERMINATION COMMENT GROUP A1 GND PWR GND A2 GBEO_MDI3 GigE MDI DP I 0 eTSEC1 GBEO MDI3 GBEO_MDI3 GigE MDI DP I 0 eTSEC1_GBEO_MDI3 A4 GBEO_LINK100 GigE MDI 0 3 3 eTSEC1_GBEO_LINK100 5 GBEO_LINK1000 GigE MDI 0 3 3 eTSEC1_GBEO_LINK1000 A6 GBEO_MDI2 GigE MDI DP I 0 eTSEC1 GBEO MDI2 A7 GBEO_MDI2 GigE MDI DP I 0 eTSEC1_GBEO_MDI2 A8 GBEO_LINK GigE MDI 0 3 3 eTSEC1_GBEO_LINK A9 GBEO_MDI1 GigE MDI DP I 0 eTSEC1 GBEO 1 A10 GBEO_MDI1 GigE MDI DP I 0 eTSEC1_GBEO_MDI1 A11 GND PWR GND A12 GBEO MDIO GigE MDI DP I 0 eTSEC1 GBEO MDIO A13 GBEO_MDIO GigE MDI DP I 0 eTSEC1_GBEO_MDI0 A14 GBEO_CTREF GigE MDI Not applicable A15 505 534 BOARD CTRL 0 3 3 Undefined 16 SATAO_TX SATA N C A17 5 SATA N C 18 505 54 BOARD CTRL 0 3 3 Undefined A19 SATAO_RX SATA N C A20 SATAO_RX SATA N C A21 GND PWR GND A22 SATA2 TX SATA N C A23
113. r suitability for any given task remains that of the purchaser In no event will Kontron be liable for direct indirect or consequential damages resulting from the use of our hardware or software products or docu mentation even if Kontron were advised of the possibility of such claims prior to the purchase of the product or during any period since the date of its purchase Please remember that no Kontron employee dealer or agent is authorized to make any modification or addition to the above specified terms either verbally or in any other form written or electronically transmitted without the company s consent www kontron com COMe P2020 User Guide 1 Introduction 1 1 COMe cP2020 Overview The COMe cP2020 is a COM Express form factor compliant Power Architecture processor module based on Freescale s QorlQ 32 bit P2020 processor Designed in the COM Express basic 95 mm x 95 mm form factor the module incorporates the Freescale QorIQ P2020 dual core Power Architecture amp processor operating up to 1 2 GHz other processor versions P2010 P1020 and P1011 and operating speeds are available on request Featuring 32 bit technology it integrates up to 4 GByte of soldered DDR3 SDRAM at 667 MHz and ECC support 512 KBytes of shared second level cache facilitate core to core communications to minimize accesses to main memory Up to 2 GByte of NAND Flash as well as a socket for MicroSD card offer reliable storage space for appli
114. rations for information related to the power consumption of the COMe cP2020 Temperature Range Operational 0 C to 60 C Standard Version 40 C to 85 C Extended Temperature Version Storage 40 C to 70 C z Mechanical COM Express compact Dimensions 95 mm x 95 mm Board Weight 99 grams without heatspreader 220 grams with heatspreader Bootloader DENX U Boot Universal Boot Loader with Kontron specific modifications to E support the COMe cP2020 requirements lt m Operating Systems The board is offered with various Board Support Packages including VxWorks 4 and Linux operating systems For further information concerning the operat ing systems available for the COMe cP2020 please contact Kontron www kontron com 1 4 Standards COMe P2020 User Guide The COMe cP2020 complies with the requirements of the following standards Table 1 2 Standards COMPLIANCE STANDARD TEST LEVEL CE Emission EN55022 EN61000 6 3 Immission EN55024 EN61000 6 2 Electrical Safety EN60950 1 Railway Safety Electrical Safety EN50155 Mechanical Mechanical Dimensions COM Express com pact Environmental Vibration EN 50155 Class 1B and Health sinusoidal operating IEC 60068 2 6 Frequency 10 300 Hz Aspects Acceleration 5 g VITA 47 Class V1 5 to 100Hz 72g RMS Shock operating EN 50155 Class 1B Bump IEC Peak Accel 15 g Operating 60068 2 29 Shock Dur
115. re touching the product with his her hands or tools This is most easily done by touching a metal part of the system housing before touching the product 7 2 General Instructions on Usage In order to maintain Kontron s product warranty this product must not be altered or modified in any way Changes or mod ifications to the device which are not explicitly approved by Kontron and described in this manual or received from Kon tron s Technical Support as a special handling instruction will void your warranty This device should only be installed in or connected to systems that fulfill all necessary technical and specific environmen tal requirements This applies also to the operational temperature range of the specific board version which must not be exceeded 7 3 COM Express Module to Carrier Assembly Considerations The COMe cP2020 has been designed to the COM Express specification for form factor mechanical dimensions and mount ing hole layout Provisions have also been made for assembly of a heatspreaderheatspreader two dedicated mounting holes Kontron offers two standard cooling solutions as indicated in Chapter 5 Thermal on page 76 all of which cover the entire upper area of the board of the solutions have appropriate holes for mounting hardware screws standoffs etc As each cooling solution is a function of the application it is the responsiblity of the implementer to ensure proper assem bly of the COMe cP2020 with t
116. recycled Final disposition of this product after its service life must be accomplished in accordance with applicable country state or local laws or regulations General Instructions on Usage In order to maintain Kontron s product warranty this product must not be altered or modified in any way Changes or mod ifications to the device which are not explicitly approved by Kontron and described in this manual or received from Kon tron s Technical Support as a special handling instruction will void your warranty This device should only be installed in or connected to systems that fulfill all necessary technical and specific environmen tal requirements This applies also to the operational temperature range of the specific system version which must not be exceeded If batteries are present their temperature restrictions must be taken into account In performing all necessary installation and application operations please follow only the instructions supplied by the present manual Keep all the original packaging material for future storage or warranty shipments If it is necessary to store or ship the sys tem please re pack it as nearly as possible in the manner in which it was delivered Special care is necessary when handling or unpacking the product Please consult the special handling and unpacking instruction on the previous page of this manual Two Year Warranty Kontron grants the original purchaser of Kontron s products a TWO
117. red by an external master 01 e500 core 1 is allowed to boot without waiting for configuration by an external master while e500 core 0 is prevented from booting until configured by an external master or the other core 10 e500 core 0 is allowed to boot without waiting for configuration by an external master while e500 core 1 is prevented from booting until configured by an external master or the other core 11 Both e500 cores are allowed to boot without waiting for configuration by an external master Table 3 43 0 304 Default Boot ROM Location Configuration Register ACTION READ NU NU NU NU NU NU cfg_boot_seq 0 1 WRITE NU NU NU NU NU NU NU POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 20 01 00 Reserved 01 Normal I2C addressing mode is used Boot sequencer is enabled and loads configuration information from a ROM on the I2C1 interface A valid ROM must be present 10 Extended I2C addressing mode is used Boot sequencer is enabled and loads configuration information from a ROM on the I2C1 interface A valid ROM must be present 11 Boot sequencer is disabled No I2C ROM is accessed Table 3 44 0 305 Default SerDes Reference Clock Configuration Register ACTION D7 D6 D5 04 03 02 01 00 READ NU NU NU NU NU NU NU cfg srds refclk WRITE NU NU NU NU NU NU NU NU POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION D0 0 Ser
118. rties who have received copies or rights from you under this License will not have their licenses terminated so long as such parties remain in full compliance www kontron com COMe P2020 User Guide 5 You are not required to accept this License since you have not signed it However nothing else grants you per mission to modify or distribute the Program or its derivative works These actions are prohibited by law if you do not accept this License Therefore by modifying or distributing the Program or any work based on the Program you indicate your acceptance of this License to do so and allits terms and conditions for copying distributing or modifying the Program or works based on it 6 Each time you redistribute the Program or any work based on the Program the recipient automatically receives a license from the original licensor to copy distribute or modify the Program subject to these terms and condi tions You may not impose any further restrictions on the recipients exercise of the rights granted herein You are not responsible for enforcing compliance by third parties to this License 7 If as a consequence of a court judgment or allegation of patent infringement or for any other reason not limited to patent issues conditions are imposed on you whether by court order agreement or otherwise that contra dict the conditions of this License they do not excuse you from the conditions of this License If you cannot dis
119. ry modify auto incrementing address mmc MMC sub system mmcinfo Display MMC info mtdparts Define flash nand partitions mtest Simple RAM read write test mw Memory write fill www kontron com COMe P2020 User Guide Table 6 1 Standard U Boot Commands Configured for the COMe cP2020 Continued COMMAND DESCRIPTION nand NAND subsystem nboot Boot from NAND device nm Memory modify constant address pci List and access PCI Configuration Space ping Send ICMP ECHO REQUEST to network host printenv Print environment variables reginfo Print register information reset Perform RESET of the CPU run Run commands in an environment variable Saveenv Save environment variables to persistent storage saves Save S Record file over serial line setenv Set environment variables setexpr Set environment variable as the result of eval expression sf SPI flash subsystem showvar Print local hushshell variables sleep Delay execution for some time source Run script from memory test Minimal test like bin sh tftpboot Boot image via network using TFTP protocol true Do nothing successfully ubi ubi commands ubifsload Load file from an UBIFS filesystem ubifsls List files in a directory ubifsmount Mount UBIFS volume ubifsumount Unmount UBIFS volume usb USB sub system usbboot Boot from USB device version Print monitor compiler and link
120. s 3 Multiplexer selection 0 CPU Serdes Lane 3 is connected to Carrier Serdes Lane 3 1 CPU Serdes Lane 3 is connected to Carrier Serdes Lane 11 Table 3 21 ACTION 0x011 User Checksum Register READ Compare Byte 7 0 WRITE Compare Byte 7 0 POWER UP 1 1 1 1 1 1 1 1 BITFIELD DESCRIPTION 07 00 _ 7 0 Checksum Control Byte User Configuration is only valid if sum of all 16 CPU Configuration Registers 0x000 0x010 value of User Checksum Register 0x011 is equal 00h Ifthe addition of all 17 registers is not equal 00h CPLD forces automatically Default Configuration strappings to CPU Table 3 22 0 012 UFM Erase Control Register ACTION D7 D6 D5 D4 D3 D2 D1 DO READ 0 0 0 0 0 0 0 0 WRITE NU NU NU NU NU NU NU RstUfm POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION D0 RstUfm Reset UFM Memory set all memory cells to OxFF 0 no Reset 1 Reset UFM bit is set by register access and automatically reset by CPLD www kontron com COMe P2020 User Guide Table 3 23 0x013 UFM CPU Control and Status Register ACTION D7 06 05 04 03 02 01 00 READ UfmBusy 0 0 0 0 0 0 0 WRITE NU NU NU NU NU Sel2 Sell RstUfm POWER UP 0 0 0 0 0 0 0 0 BITFIELD DESCRIPTION D0 RstUfm Reset CPU and read User Flash Memory Configuration 0 no Read 1 Resets CPU and
121. s as an agent on PCI Express 3 100 P2020 acts as an agent on PCI Express 1 Serial RapidIO 2 P2020 acts as an agent on PCI Express 2 Serial RapidIO 1 P2020 acts as a host on PCI Express 3 101 P2020 acts as an agent on PCI Express 1 or host on Serial RapidIO 2 P2020 acts as a host on PCI Express 2 Serial RapidIO 1 P2020 acts as an agent on PCI Express 110 P2020 acts as a host on PCI Express 1 or agent on Serial RapidIO 2 P2020 acts as an agent on PCI Express 2 Serial RapidIO 1 P2020 acts as an agent on PCI Express 111 P2020 acts as the host processor root complex for all PCI Express Serial RapidIO interfaces www kontron com COMe P2020 User Guide Table 3 41 0x302 Default 1 0 Selection Register ACTION READ NU NU NU NU cfg io ports 0 3 WRITE NU NU NU NU NU POWER UP 1 1 1 1 0 1 1 0 BITFIELD DESCRIPTION D3 D0 0000 PCI Express 1 x1 2 5Gbps SerDes lane 0 SerDes lanes 1 3 powered down 0001 SerDes lanes 0 3 powered down 0010 PCI Express 1 x1 2 5 Gbps SerDes lane 0 PCI Express 2 x1 2 5 Gbps SerDes lane 1 PCI Express 3 x2 2 5 Gbps SerDes lanes 2 3 0011 Reserved 0100 PCI Express 1 x2 2 5 Gbps SerDes lanes 0 1 PCI Express 3 x2 2 5 Gbps SerDes lanes 2 3 0101 Reserved 0110 PCI Express 1 x4 2 5 Gbps SerDes lanes 0 3 0111 SRIO2 1x 3 125 Gbps SerDes lane 0 SRIO1 1x 3 125 Gbps SerDes lane 1 SerDes lanes 2 3
122. ses for most software are designed to take away your freedom to share and change it By contrast the GNU General Public License is intended to guarantee your freedom to share and change free software to make sure the software is free for all its users This General Public License applies to most of the Free Software Foundation s software and to any other program whose authors commit to using it Some other Free Software Foundation software is covered by the GNU Library General Public License instead You can apply it to your programs too When we speak of free software we are referring to freedom not price Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software and charge for this service if you wish that you receive source code or can get it if you want it that you can change the software or use pieces of it in new free programs and that you know you can do these things To protect your rights we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights These restrictions translate to certain responsibilities for you if you distribute copies of the software or if you modify it For example if you distribute copies of such a program whether gratis or for a fee you must give the recipients all the rights that you have You must make sure that they too receive or can get the source code And you must show them these terms so
123. smount boot gt www kontron com COMe P2020 User Guide After the volume is mounted its contents can be listed gt ubifsls gt or a file loaded in this case kernel bin to address 0x100000 gt ubifsload 100000 kernel bin gt 6 5 8 Using the SPI Flash for OS The SPI flash for OS is not used together with a file system itis used raw It does not contain any U Boot components and is completely free for user usage It s primary function is to store VxWorks boot ROMs and images Before making any changes to the flashes ensure that the correct flash is selected To select the SPI flash for OS execute the sf probe 3 command SPI flash for OS is routed to the processor s SPI controller chip select 3 The SPI flash must be erased before itis programmed To achieve this use the sf erase command To program an image to the SPI flash it must first be loaded to memory from an arbitrary source It can then be pro grammed with the sf write command Example Programming a test file test img from an SD card using the ext2 file system gt mmc rescan 0 gt ext2load mmc 0 100000 test img gt sf probe 3 gt sf erase 0 10000 gt deus L00000 0 S isst beste This example assumes that the size of test img is less than 64 kB The environment variable filesize is set automatically when a file is loaded to memory and can be used for convenience here 6 5 9 Booting an OS 6 5 9
124. stem binary image The special header defines various properties of the uImage file e g load address and entry point for the binary image in the data portion Both the header and the data portion of the uImage file are secured and checked against corruption by a CRC32 checksum at U Boot load time All VxWorks ROM able binary images will be converted to a uImage file at build time of the suited Wind River Workbench projects based on the dedicated Kontron VxWorks BSP Board Support Package This conversion will be carried out by the mkImage Kontron tool which is automatically invoked Wind River Workbench On successful build of the VxWorks binary ROM able image an additional uImage file containing the VxWorks ROM able binary image will be generated in the project default build folder with the following naming conventions Table 6 9 Naming Conventions U BOOT uImage NAME VXWORKS IMAGE NAME uImage bootrom bin bootrom bin uImage vxWorks rom bin vxWorks_rom bin ulmage vxWorks_romCompress bin vxWorks_romCompress bin Please note that the resulting uImage file contains all needed information for a proper U Boot load process and start of the contained VxWorks binary ROM able image Therefore it is strongly recommended to utilize the corresponding uIm age file listed above when using U Boot for booting VxWorks The uImage file and FDT are typically stored in and loaded from the SPI flash for O
125. terface Up to two serial ports e 2x 4 wire UART interfaces RxD TxD RTS CTS GPIO Interrupts Five GPIOs are shared with Interrupts Function depends on configuration Two 220 pin connectors for interfacing with a carrier board connector J4 for debugging Onboard Connectors Connectors microSD card Socket Standard microSD socket J9 accepts microSD and microSDHC cards DIP Switch Two DIP switches for board configuration SW1 SW2 consisting of two switches Switch Module Health Monitor CPLD HEALTY D4 indicates by blinking CPLD is active LEDs LEDO D5 indicates U Boot boot failure LED1 D6 indicates CPU reset is asserted LED2 D7 not used LED3 D3 indicates Power Good failure LEDs www kontron com COMe P2020 User Guide Table 1 1 COMe cP2020 Main Specifications Continued COMe cP2020 SPECIFICATIONS Watchdog Timer Software configurable two stage Watchdog with programmable timeout ranging from 125 ms to 4096 s in 16 steps Serves for generating IRQ or hardware reset E System Timer There are several timers implemented in the CPU For further information regarding these timers refer to the CPU reference manual from Freescale I lt Thermal Monitoring CPU and board temperature is provided by one onboard temperature sensor for monitoring the board temperature Power Consumption Refer to Chapter 5 Power Conside
126. they know their rights We protect your rights with two steps 1 copyright the software and 2 offer you this license which gives you legal per mission to copy distribute and or modify the software Also for each author s protection and ours we want to make certain that everyone understands that there is no warranty for this free software If the software is modified by someone else and passed on we want its recipients to know that what they have is not the original so that any problems introduced by others will not reflect on the original authors reputa tions Finally any free program is threatened constantly by software patents We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses in effect making the program proprietary To prevent this we have made it clear that any patent must be licensed for everyone s free use or not licensed at all The precise terms and conditions for copying distribution and modification follow GNU GENERAL PUBLIC LICENSE TERMS AND CONDITIONS FOR COPYING DISTRIBUTION AND MODIFICATION 0 This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License The Program below refers to any such program or work and a work based on the Program means either the Program or any derivative work under copyright law that is to say a work contain
127. tition on mmc mmc list lists available devices gt 6 7 Update The environment contains two scripts which allow an update of various components e g U Boot bootrom for VxWorks data in EEPROMs etc The script update checks for a U Boot script update in the directory update d0481 in the first partition of the SD card with ext2 or fat filesystem If unsuccessful the check continues with the first NAND chip volume boot and again U Boot searches in the subdirectory update d0481 for the script update If the script update is found it is loaded to memory and executed So to actually execute an update e g an SD card should be prepared with a directory update 00481 on the first parti tion Kontron provides an update e g for U Boot as a compressed archive zip tar bz2 tar gz which must be unpacked in the directory update After the SD card is inserted U Boot should be stopped at the console after power up To manually start the update enter the following command run update gt In the case of a U Boot update only the standard SPI boot flash is updated The script netupdate tries to load a U Boot script update d0481 update from the server If found it is loaded to mem ory and executed as in the case of the SD card www kontron com COMe P2020 User Guide As the script netupdate requires access to a server the environment variable serverip must be set correctly Alterna tively
128. uild a binary vector to display POST code during the pre boot phase In doing so the higher 4 bit nibble of the 8 bit POST code is displayed followed by the lower nibble followed by a pause Mode A LEDs controlled by CPU Beside the configurable functions described above the LEDs fulfill also a basic debug function during the power up phase as long as the first access to POST Code LOW Byte Register 0x080 is processed If a LED lights red and stays red then a basic error is present on the board The following debug functions are defined and displayed during this initialization phase Table 3 38 LED3 PGOOD failure Power Good status not reached LED2 not used LED1 CPU reset is asserted not asserted LEDO U Boot boot failure 0x291 LED Control Register ACTION 07 06 05 104 03 02 01 00 READ 0000 LED3 LED2 LED1 LEDO WRITE NU LED3 LED2 LED1 LEDO POWER UP 0000 0 0 0 0 BITFIELD DESCRIPTION 00 LEDO LED Control Register controls Board LED D5 0 LED is OFF 1 LED is ON 01 LED1 LED Control Register controls Board LED D6 0 LED is OFF 1 LED is ON D2 LED2 LED Control Register controls Board LED D7 0 LED is OFF 1 LED is ON D3 LED3 LED Control Register controls Board LED D3 0 LED is OFF 1 LED is ON www kontron com COMe P2020 User Guide Table 3 39 0x300 Default Boot ROM Location Configuration Register

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