UG-2832HSWEG04 Evaluation Kit User Guide
Contents
1. DH UG 2832HSWEG04 Evaluation Kit User Guide Writer Email Version Preliminary DH Contents 1 Em 3 2 EVK SCMOMAUIC i a S ae 4 3 Symbol define 2 iei eque 5 4 TIMMING 58 65 1 1211 6 4 1 SPI Series MPU parallel Interface eese 6 5 EVK Use introd ction eren it e ces cee na ope deor susu swak awas 7 6 Power down and Power up Sequence 9 7 How to use 5501306 2 nnne nnns 10 74 Initial Step Flow ee eter ntl been aaa a e daaa aa 10 fc EL 1 REVISION HISTORY APRA Date Page Contents Version 200X XX XX Preliminary Preliminary 0 0 2 EVK Schematic MI 2832HSWEG04 2 3B VDD VDD voc VDD IN VBAT DCDC VDD HV DCDCON FORPCB DCDC A CS C7 C6 C8 Ju 2 2uF 0 1uF DH 3 Symbol define SCLK The transmission if information in the bus is following a clock signal Each transmission of data bit is taken place during2. k pauk Fig 7 EVK with test platform It is OLED high voltage supply It is logic voltage supply Those are leading wire connect to control board Those are data pin DO D7 Those are leading wire connect to control board Those are control pin A0 CSB RDB WRB RSTB PH 6 Power down and Power up Sequence To protect OLED panel and extend the panel life time the driver IC power up down routine should include a delay period between high voltage and low voltage power sources during turn on off Such that panel has enough time to charge up or discharge before after operation Power up Sequence Power up Vpp Send Display off command Display on Driver IC Initial Setting Clear Screen Power up Vppu Delay 100ms when Vpp is stable Vpp Qu At dee pu uem Vss Ground 7 Send Display on command Power down Sequence _ Display off off Send Display off command 2 Power down 3 Delay 100ms when is reach 0 and panel is completely discharges 4 Power down Vpp Vss Ground vision SESE AIBA 24 7 How to use 5501306 module 7 1 Initial Step Flow Reset Driver IC RES 0 Delay 10ms RES 1 Driver IC Initial Code Suggest all register set again Display on Clear RAM Start Dispaly
3. RERED ARZT 4 TIMMING CHARACTERISTICS 4 1 SPI Series MPU parallel Interface Vss TE 65V to 3 3V TA 25 ka otom C Te 15 hates te ti tess Chip Select Setup Time ts tes Chip Select Hold Time 10 tw Write Data Setup Time 15 touw Write Data Hold Time Clock Low Time J m iux ClockHighTime 0 ns m te RseTim j ralTime 40 ns Table 4 1 4 wire Serial Interface Timing Characteristics Cu css CSH SCLK D 0 tr ta tpsw SDIN D 1 Valid Data D CS O ax f Lf LF LF LF LT LA LE T ED ps gt gt DX m gt m EY Figure 4 2 4 wire Serial interface characteristics Jnivision D 5 EVK use introduction UG 2832HSHEGO4 2009 05 14 UT 0206 P06 2832HSUEGO4 SSD1306 r IIIIIIII 91 2 3 4 7 Figure 5 and OLED Module UG 2832HSWEG01 is TAB FPC type module please refer to Fig5 Fig6 User can use leading wire to connect EVK with customer s system The example shows as Fig7 olg E 05006 060 h do 90 Figure 6 The combination of the module and EVK Note 1 Note 2 Note 3 Note 4 wd 2009705714 NETT il MNA aTa
4. a single clock period of this pin SDIN This pin acts as a communication channel The input data through SDIN are latched at the rising edge of SCLK in the sequence of MSB first and converted to 8 bit parallel data and handled at the rising edge of last serial clock SDIN is identified to display data or command by D C bit data at the rising of first SCLK D C This is Data Command control pin When it is pulled HIGH i e connect to VDD the data at D 7 0 is treated as data When it is pulled LOW the data at D 7 0 will be transferred to the command register RES This pin is reset signal input When the pin is pulled LOW initialization of the chip is executed Keep this pin HIGH i e connect to VDD during normal operation CS This pin is the chip select input active LOW Power supply for panel driving voltage This is also the most positive power voltage supply pin VDD Power supply pin for core logic operation VSS This is a ground pin VBAT Thisis the power supply pin for the internal buffer of the DC DC voltage converter It must be connected to external source when the converter is used It should be connected to VDD when the converter is not used VCOMH The pin for COM signal deselected voltage level A capacitor should be connected between this pin and VSS 1 C2N The charge pump capacitors are required between the terminals They must be floated when the converter is not used
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