ISL8117EVAL2Z User Guide
Contents
1. 3 R24 R U3 3 ES 20 die R19 i i 0 e Intersil sjoloje sioje OO ALL 1 888 INTERSIL FIGURE 25 BOTTOM LAYER FIGURE 26 SILKSCREEN BOTTOM Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that the document is current before proceeding For information regarding Intersil Corporation and its products see www intersil com Submit Document Feedback 10 intersil UGO20 0 March 17 20152. intersil User Guide 020 ISL8117EVAL2Z Evaluation Board User Guide Description The ISL8117EVAL2Z evaluation board shown in Figure 1 features the ISL8117 The ISL8117 is a GOV high voltage synchronous buck controller that offers external soft start independent enable functions and integrates UV OV OC OT protection Its current mode control architecture and internal compensation network keep peripheral component count minimal Programmable switching frequency ranging from 200kHz to 2MHz helps to optimize inductor size while the strong gate driver delivers up to 30A for the buck output Specifications The ISL8117EVAL2Z evaluation board is designed for high current applications The current rating of the ISL8117EVAL2Z is limited by the FETs and inductor selected The ISL8117 gate driver is capable of delivering up to 20A for the buck output as long as the proper FETs and inductor are provided The electrical ratings of ISLS117EVAL2Z are shown in Table 1 TABLE 1 ELECTRICAL RATING PARAMETER RATING Input Voltage 18V to 60V Switching Frequency 30OkHz Output Voltage 12V Output Current 20A OCP Set Point Minimum 25A at ambient room temperature Key Features e Wide input range 18V to 60V e High light load efficiency in pulse skipping DEM operation e Programmable soft start Optional DEM CCM operation Supports prebias output with SR soft start External frequency sync e PGOOD indicator e OCP OVP OT
3. CCM MODE LINE REGULATION 5 l Mk e ee a ie Dee PHASE 50V DIV U jenast disc aren CCM LGATE 5V DIV 0 5 p ea y anme p hicar Danaa AAA ke lt zZ mu pma ma L CLKOUT 5V DIV Y IACLKOUT calamidad AAA AAA A ne a er tn a cee A nt e Pe A e e 0 05 DEM gre TOR CURRENT li 5A DIV 0 005 PARRA RA DES ASAS A i 0 01 0 1 1 10 1us DIV lout A FIGURE 8 INPUT CURRENT COMPARISON WITH MODE CCM DEM FIGURE 9 PHASE LGATE CLKOUT AND INDUCTOR CURRENT WAVEFORMS Submit Document Feedback 4 intersil UGO20 0 March 17 2015 User Guide 020 Typical Evaluation Board Performance Curves Vin 48V unless otherwise noted Continued NO LOAD Vin 48V Vout 50mV DIV BAAN ANN ANDAN 20A LOAD Vin 48V Vour 50mV DIV LAA WA MWAN PRE V A AAA AAA A AA 4us DIV FIGURE 10 OUTPUT RIPPLE MODE CCM so Vour 5VIDIV i dv OUT BOOT CAP REFRESH EO kk LGATE 5V DIV din CLKOUT 5V DIV peor DIINDUCTOR CURREN DEM TO CCM TRANSITION l 10A DIV 4amsIDIV 7 FIGURE 12 START UP WAVEFORMS MODE CCM LOAD 0A Vin 48V a Vout 5V DIV SS 1V DIV EN 5V DIV FAZ PGOOD 5V DIV N A a a EL 20ms DIV FIGURE 14 START UP WAVEFORMS MODE CCM LOAD OA Vin 48V Submit Document Feedback 5 intersil _A gt gt a A A KA A A KA A A ka danl Vour 50mV DIV 1ms DIV 20A LOAD Vin 48V Vout 50mV DIV SAY AA AA 4us DIV A Ta FIGURE 11 OUTPUT RIPPLE MODE
4. DEM Vout 5V DIV BURST MODE OPERATION AVOUT BOOT CAP REFRESH EXTBIAS KICK IN LGATE 5V DIV mliGATI CLKOUT 5V DIV j O E INDUCTOR O O AAA li SAIDIV 4ms IDIV l FIGURE 13 START UP WAVEFORMS MODE DEM LOAD OA Vin 48V Vour 5V DIV SS 1V DIV i EN 5V DIV PGOOD 5V DIV EN AA AA 20ms DIV FIGURE 15 START UP WAVEFORMS MODE DEM LOAD OA Vin 48V UGO20 0 March 17 2015 User Guide 020 Typical Evaluation Board Performance Curves Vin 48V unless otherwise noted Continued Bte A AAA A A A A AA A AAA A A A A A A A AAA A A A A A A A a ae on SS 500mV DIV Vout 10V DIV 1 lss i al CUT PGOOD 5VIDIV KA nan ae kt 1ms DIV FIGURE 16 TRACKING Vin 48V LOAD OA MODE CCM Vour 500mV DIV la lour 10A DIV kouran 400us DIV FIGURE 18 LOAD TRANSIENT RESPONSE Vin 48V 2A TO 18A 1A ps STEP LOAD CCM MODE Submit Document Feedback 6 inter li 5A DIV bwen TE ZON ZE LGATE SVIDIV annan E SYNC 5V DIV g d er A PRA A CLKOUT 5V DIV iC EOI T es A AAA A A A SE e 800ns DIV FIGURE 17 FREQUENCY SYNCHRONIZATION Vin 48V LOAD OA DEFAULT fgy 300kHz SYNC fsw 400kHz RA Nour 10V DIV INDUC CURREN I 20A DIV SEEN RERE TT SS 2VIDIV er rr morena das 5 PGOOD 5V DIV 40ms DIV FIGURE 19 OCP RESPONSE OUTPUT SHORT CIRCUITED TO GROUND AN
5. ea R8 RES SMD 1206 DNP DNP DNP TF ROHS 1795 2 ea J1 J2 HDWARE TERMINAL M4 METRIC SCREW TH 4P SNAP FIT KEYSTONE ROHS 1798 2 ea J3 J4 HDWARE TERMINAL M4 METRIC SCREW TH 6P SNAP FIT KEYSTONE ROHS R25 1001002 4 ea Four corners STANDOFF M2 5 10mm METRIC F F HEX THREADED HARWIN INC ROHS 29301 4 ea Four corners SCREW M2 5 6mm METRIC PANHEAD SLOTTED STEEL KEYSTONE ROHS ISLS117EVAL2Z PCB Layout LI pan N 7 A N 000000 y O HHU O OYE Tes Due a O a ME O ne FOTDOOVOOO mm E LE ISABLE E FIGURE 21 SILKSCREEN TOP Submit Document Feedback 9 intersil FIGURE 22 TOP LAYER UGO20 0 March 17 2015 User Guide 020 ISL8117EVAL2Z PCB Layout Continued m Mou it Aa TTT ll ll pat pat LI pul yu e Fi az e ae L gt FIGURE 23 SECOND LAYER SOLID GROUND FIGURE 24 THIRD LAYER
6. magnitude of these voltage spikes There are three sets of critical components in a DC DC converter using the ISL8117 the controller the switching power components and the small signal components The switching power components are the most critical from a layout point of view because they switch a large amount of energy which tends to generate a large amount of noise The critical small signal components are those connected to sensitive nodes or those supplying critical bias currents A multilayer printed circuit board is recommended UGO20 0 March 17 2015 User Guide 020 Layout Considerations 1 Submit Document Feedback 3 The input capacitors upper FET lower FET inductor and output capacitor should be placed first Isolate these power components on the top side of the board with their ground terminals adjacent to one another Place the input high frequency decoupling ceramic capacitors very close to the MOSFETs Use separate ground planes for power ground and small signal ground Connect the SGND and PGND together close to the IC DO NOT connect them together anywhere else The loop formed by the input capacitor the top FET and the bottom FET must be kept as small as possible Ensure the current paths from the input capacitor to the MOSFET to the output inductor and the output capacitor are as short as possible with maximum allowable trace widths Place the PWM controller IC close to the lower FET T
7. D RELEASED CCM MODE Vin 48V NO LOAD TO SHORT AND RELEASE UGO20 0 March 17 2015 GTOZ ZT UDIEIN 0 ozO9nNn 4 7u 100V 4 7u 100V 4 7u 100V 4 7u 100V C14 C15 UN 21 Schematic 3 S 4 7uM00V 2 4 7u 100V 4 7u 100V 3 4 7u 100V SHST 6 C23 125 26 24 ay R4 0 1u 25V R5 gt 10u 10V m C5 90 9k 10k C4 gt E O 17 0 1u 100V x a 0 1u 100V R9 20 C21 vin N R24 0 vout 2 vcc5 D1 1A 100V mo 2 R19 M en T Wi 10k m C20 lt gt 0 1u 25V x CLKOUT J5 MOD SYNC ISL8117 op O O JMP F 0 l TP19 CON1 i i 0 047u 25V VCC5 TRACKING e R25 DNP R26 DNP TP18 CON1 TP5 TP6 TP10 TP11 dbabbbnabnnd TP12 TP13 TP14 TP15 TPI ou CON1 CON e CON1 CON1 CON1 CON1 CON1 CON1 CON1 CON1 CON1 CON1 CONI FIGURE 20 TP16 TP17 ISL8117EVAL2Z SCHEMATIC J1 LA 100u 100v VIN 4 7u 100V 4 7u 100V 100u 100V 018 16 GND C2 1u 25V TP2 J3 a vout a w CON1 104 50 Li tu 50V 10u 50V 10W 50V VOUT 330u 35V 3 3u 30A C22 10 C9 8 11 C7 R15 DNP 20 Ja TP3 a Re 220p 50V iE DNP C6 CONT ah R1 ban 43 2k 4ou sov 10u 50V da 10u 50V 10u 50V 10u 50V 10u 50V 10u 50V 10u 50V 10u 50V 0c0 SPINI 135N Bill of Materials User Guide 020 REFERENCE MANUFACTURER PART QTY UNITS DESIGNATOR DESCRIPTION MANUFACTURER ISL8117EVAL2ZREVBPCB 1 ea PWB PCB I
8. N BLACK GOLD ROHS SULLINS MBR1H100SFT3G 1 ea D1 DIODE RECTIFIER SMD 2P SOD 123FL 100V 1A ROHS ON SEMICONDUCTOR ISL80138IVEAJZ 1 ea U3 IC 40V LDO ADJ LINEAR REGULATOR 14P HTSSOP ROHS _ INTERSIL ISL8117FRZ 1 ea U2 IC 55V SWITCHING CONTROLLER 16P QFN ROHS INTERSIL BSCO67NO6LS3G 4 ea Q1 Q2 Q3 Q4 TRANSISTOR MOS N CHANNEL 8P PG TDSON 8 GOV 50A INFINEON ROHS TECHNOLOGY RK73H41JT10ROF 1 ea R18 RES SMD 0603 100 1 10W 1 TF ROHS KOA ERJ 3EKF20ROV 2 ea R9 R15 RES SMD 0603 200 1 10W 1 TF ROHS PANASONIC CROGO3 10W OOOT 9 ea R6 R11 R12 R13 RES SMD 0603 00 1 10W TF ROHS VENKEL R16 R17 R23 R24 R27 RK73H1JT1002F 3 ea R5 R19 R21 RES SMD 0603 10k 1 10W 1 TF ROHS KOA CROGO3 10W 1003FT 1 ea R14 RES SMD 0603 100k 1 10W 1 TF ROHS VENKEL RCOGO3FR O72K26L 1 ea R2 RES SMD 0603 2 26k 1 10W 1 TF ROHS YAGEO RCOGO3FR 0730K9L 1 ea R20 RES SMD 0603 30 9k 1 10W 1 TF ROHS YAGEO RCOGO3FR 0743K2L 1 ea R1 RES SMD 0603 43 2k 1 10W 1 TF ROHS YAGEO Pb free CRO603 10W 5101FT 2 ea R3 R7 RES SMD 0603 5 1k 1 10W 1 TF ROHS VENKEL Submit Document Feedback 8 intersil UGO20 0 March 17 2015 User Guide 020 Bi ll of Materials Continued REFERENCE MANUFACTURER PART QTY UNITS DESIGNATOR DESCRIPTION MANUFACTURER ERJ 3EKF9092V 1 ea R4 RES SMD 0603 90 9k 1 10W 1 TF ROHS PANASONIC 0 ea R22 R25 R26 RES SMD 0603 DNP PLACE HOLDER ROHS 0
9. P UVP protection e Back biased from output to improve efficiency References ISL8117 Datasheet Ordering Information PART NUMBER DESCRIPTION ISL8117EVAL2Z High Voltage PWM Step down Synchronous Buck Controller Evaluation Board 666660 O S aj i ki TH i a a a io av Ia A en j ed WE aa a i a a ETI M FIGURE 1 March 17 2015 1 UGO20 0 6000000 an an ISLS117EVAL2Z TOP SIDE CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 1 888 468 3774 Copyright Intersil Americas LLC 2015 All Rights Reserved Intersil and design is a trademark owned by Intersil Corporation or one of its subsidiaries All other trademarks mentioned are the property of their respective owners User Guide 020 Recommended Testing Equipment The following materials are recommended to perform testing e OV to GOV power supply with at least 30A source current capability e Electronic loads capable of sinking current up to 30A e Digital Multimeters DMMs e 100MHz quad trace oscilloscope Quick Test Guide 1 Jumper J5 provides the option to select CCM or DEM Please refer to Table 2 for the desired operating option Ensure that the circuit is correctly connected to the supply and electronic loads prior to applying any power Please refer to Figure 3 for proper set up 2 Turn on the power supply 3 A
10. SL8117EVAL2Z REVB ROHS IMAGINEERING INC COGO3X7R101 104KNE 2 ea C4 C21 CAP SMD 0603 0 1pF 100V 10 X7R ROHS VENKEL GRM39X7R104K025AD 2 ea C5 C20 CAP SMD 0603 O 1pF 25V 10 X7R ROHS MURATA C1608X5R1H105K 2 ea C2 C22 CAP SMD 0603 1pF 50V 10 X5R ROHS TDK ECJ 1VB1A106M 2 ea C1 C17 CAP SMD 0603 10pF 10V 20 X5R ROHS PANASONIC GRM188R71H221KA01D 1 ea C6 CAP SMD 0603 220pF 50V 10 X7R ROHS MURATA GRM188R71E473KA01D 1 ea C3 CAP SMD 0603 0 047pF 25V 10 X7R ROHS MURATA 0 ea C7 CAP SMD 0603 DNP PLACE HOLDER ROHS UMK325BJ106KM T 12 ea a C8 C9 C10 C32 CAP SMD 1210 10uF 50V 10 X5R ROHS TAIYO YUDEN C33 C34 C35 C36 C37 C38 UMK325BJ106KM T 0 ea b C39 C40 CAP SMD 1210 10pF 50V 10 XSR ROHS TAIYO YUDEN CGA6M3X7S2A475K200AB 10 ea C12 C13 C14 C15 CAP SMD 1210 4 7pF 100V 10 X7S ROHS TDK C23 C24 C25 C26 C30 C31 EEE FP1V331AP 1 ea C11 CAP SMD 10x10 2mm 330HF 35V 20 ALUM ELEC PANASONIC ROHS EMVH101GDA101MLHOS 2 ea C16 C18 CAP SMD 16x16 5mm 100uF 100V 20 ALUM ELEC UNITED CHEMI CON ROHS IHLP6767GZER3R3M11 1 ea L1 COIL PWR INDUCTOR SMD 17 15mm2 3 3pH 2096 35A VISHAY ROHS 5007 19 ea TP1 TP19 CONN COMPACT TEST PT VERTICAL WHT ROHS KEYSTONE 68000 236HLF 1 ea J5 CONN HEADER 1x3 BREAKAWY 1x36 2 54mm ROHS BERG FCI 69190 202HLF 1 ea J6 CONN HEADER 1X2 RETENTIVE 2 54mm 0 230 x 0 120 BERG FCI ROHS SPCO2SYAN 2 ea J5 J6 CONN JUMPER SHORTING 2PI
11. ack connection to the output capacitor is short and direct O lt O mr a FIGURE 3 PROPER TEST SET UP intersil UGO20 0 March 17 2015 User Guide 020 Typical Evaluation Board Performance Curves Vin 48V unless otherwise noted 100 100 oc SS 95 T T 90 90 f VIN 48V e VIN 48V S 85 85 gt Le Nw 60V Vin 36V yy 24V Vy 18V o lt Vin 60V Vin 36V Vy 24V Viy 18V ai 80 Z 80 O O LL 75 LL 75 Li Li 70 70 65 65 60 60 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 lour A lour A FIGURE 4 CCM EFFICIENCY vs LOAD FIGURE 5 DEM EFFICIENCY vs LOAD 12 20 12 20 12 18 12 18 12 16 MN Tey ie lo 0A 12 14 Vi 48V 12 14 1212 y 12 12 2 van Ne 5 12 10 a n Ge n n rro eee 12 06 12 06 Vin tc 12 04 12 04 lo 20A lo 10A 12 02 Vin 36V Vin 24V 12 02 12 00 12 00 0 2 4 6 8 10 12 14 16 18 20 18 23 28 33 38 43 48 53 58 lour A Vin V FIGURE 6 CCM MODE LOAD REGULATION FIGURE 7
12. djust input voltage Vi within the specified range and observe output voltage The output voltage variation should be within 3 4 Adjust load current within the specified range and observe output voltage The output voltage variation should be within 3 5 Use an oscilloscope to observe output voltage ripple and Phase node ringing For accurate measurement please refer to Figure 2 for proper test set up TABLE 2 DESIRED OPERATING OPTIONS JUMPER POSITION FUNCTION J5 CCM Pin 1 2 Continuous current mode DEM Pin 2 3 Diode emulation mode Disable the PWM J6 Pin 1 2 OUTPUT CAP OR MOSFET FIGURE 2 PROPER PROBE SET UP TO MEASURE OUTPUT RIPPLE AND PHASE NODE RINGING Submit Document Feedback 2 intersil Functional Description The ISL8117EVAL2Z is the same test board used by the Intersil application engineers and IC designers to evaluate the performance of the ISL8117 QFN IC The board is set to provide an easy and complete evaluation of all the IC and board functions As shown in Figure 3 on page 3 18V to 60V Vin is supplied to J1 and J2 The regulated 12V output on J3 and J4 can supply up to 20A to the load Due to the high thermal efficiency the evaluation board can run at 20A continuously without airflow under room temperature ambient conditions Test points TP1 through TP19 provide easy access to IC pin and external signal injection terminals As sho
13. he LGATE connection should be short and wide The IC can be best placed over a quiet ground area Avoid switching ground loop currents in this area Place VCC5V bypass capacitor very close to the VCC5V pin of the IC and connect its ground to the PGND plane Place the gate drive components optional BOOT diode and BOOT capacitors together near the controller IC 10 11 12 13 The output capacitors should be placed as close to the load as possible Use short wide copper regions to connect output capacitors to load in order to avoid inductance and resistances Use copper filled polygons or wide but short trace to connect the junction of the upper FET lower FET and output inductor Also keep the PHASE node connection to the IC short DO NOT unnecessarily oversize the copper islands for the PHASE node Since the phase nodes are subjected to very high dv dt voltages the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise Route all high speed switching nodes away from the control circuitry Create a separate small analog ground plane near the IC Connect the SGND pin to this plane All small signal grounding paths including feedback resistors current limit setting resistor soft starting capacitor and EN pull down resistors should be connected to this SGND plane Separate the current sensing trace from the PHASE node connection Ensure the feedb
14. wn in Table 2 connector J5 provides selection of either CCM mode shorting pin 1 and pin 2 or DEM mode shorting pin 2 and pin 3 Connector J6 provides an option to disable the converter by shorting its pin 1 and 2 Operating Range The input voltage range is from 18V to 60V for an output voltage of 12V If the output voltage is set to a lower value the minimum Vin can be reset to a lower value by changing the ratio of R and Rs The minimum EN threshold that V y can be set to is 4 5V The rated load current is 20A with the OCP point set at minimum 25A at room ambient condition The operating temperature range is from 40 C to 125 C Please note that airflow is needed for higher temperature ambient conditions PCB Layout Guideline Careful attention to layout requirements is necessary for successful implementation of an ISL8117 based DC DC converter The ISL8117 switches at a very high frequency and therefore the switching times are very short At these switching frequencies even the shortest trace has significant impedance Also the peak gate drive current rises significantly in an extremely short time Transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements These voltage spikes can degrade efficiency generate EMI and increase device overvoltage stress and ringing Careful component selection and proper PC board layout minimizes the
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