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Xilinx UG130 Spartan-3 Starter Kit Board User Guide

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1. Pressing a push button generates a logic High on the associated FPGA pin Again there is no active debouncing circuitry on the push button The left most button BIN3 is also the default User Reset pin BTNG electrically behaves identically to the other push buttons However when applicable BINS resets the provided reference designs Spartan 3 Starter Kit Board User Guide www xilinx com 21 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX LEDs 22 Chapter 4 Switches and LEDs The Spartan 3 Starter Kit board has eight individual surface mount LEDs located above the push button switches indicated by in Figure 1 2 The LEDs are labeled LED7 through LEDO LED is the left most LED LEDO the right most LED Table 4 3 shows the FPGA connections to the LEDs Table 4 3 LED Connections to the Spartan 3 FPGA LED LD7 LD6 LD5 LD4 LD3 LD2 LD1 LDO FPGA Pin P11 P12 N12 P13 N14 L12 P14 K12 The cathode of each LED connects to ground via a 270Q resistor To light an individual LED drive the associated FPGA control signal High which is the opposite polarity from lighting one of the 7 segment LEDs www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 SC XILINX Chapter 5 VGA Port The Spartan 3 Starter Kit board includes a VGA display port and DB15 connector indicated as in Figure 1 2 Connect this port directly to m
2. Red R Green G Blue B Resulting Color 0 0 0 Black 0 0 1 Blue 0 1 0 Green 0 1 1 Cyan 1 0 0 Red 1 0 1 Magenta 1 1 0 Yellow VGA signal timing is specified published copyrighted and sold by the Video Electronics Standards Association VESA The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode For more precise information or for information on higher VGA frequencies refer to documents available on the VESA website or other electronics websites e Video Electronics Standards Association http www vesa org e VGA Timing Information http www epanorama net documents pc vga timing html Signal Timing for a 60Hz 640x480 VGA Display CRT based VGA displays use amplitude modulated moving electron beams or cathode rays to display information on a phosphor coated screen LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal thereby changing light permitivity through the crystal on a pixel by pixel basis Although the following description is limited to CRT displays LCD displays have evolved to use the 24 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 Signal Timing for a 60Hz 640x480 VGA Display A XILINX Current through the horizontal deflection coil time same signal timings as CRT displays C
3. Signal FPGA Pin RXD T13 TXD R13 RXD A N10 TXD A T14 An auxiliary RS 232 serial channel from the Maxim device is available on two 0 1 inch stake pins indicated as J1 in the schematic and in Figure 1 2 The FPGA connections driving the Maxim device appear in Table 7 1 with signals RXD A and TXD A 36 www xilinx com 1 800 255 7778 Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 XILINX Chapter 8 Clock Sources The Spartan 3 Starter Kit board has a dedicated 50 MHz Epson SG 8002JF series clock oscillator source and an optional socket for another clock oscillator source Figure A 5 provides a detailed schematic for the clock sources The 50 MHz clock oscillator is mounted on the bottom side of the board indicated as 3 in Figure A 5 Use the 50 MHz clock frequency as is or derive other frequencies using the FPGAs Digital Clock Managers DCMs e Using Digital Clock Managers DCMs in Spartan 3 FPGAs http www xilinx com bvdocs appnotes xapp462 pdf The oscillator socket indicated as in Figure 1 2 accepts oscillators in an 8 pin DIP footprint Table 8 1 Clock Oscillator Sources Oscillator Source FPGA Pin 50 MHz IC4 T9 Socket IC8 D9 Spartan 3 Starter Kit Board User Guide www xilinx com 37 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Chapter 8 Clock Sources 38 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 U
4. 8 ANZ Nte Nne a 8131 T 3ueg uo Tg pue Tan I33 ISIN p 19905 uo 8 601 pue g z 3ueq q iesus 555 mmm o 2 2 DON pue z yueq G ieaus 555 ApA 08 042604 UG130 A 2x256Kx16 Fast Asynchronous SRAM Interface Figure A 8 65 www xilinx com 1 800 255 7778 Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 Appendix A Board Schematics XILINX T T 1884 eo0z 9 6 U 95 52 28 4ouing 6001 1 DUI Wertbig egoz zaoz 1UbT4hdoo 9 qe3 Butweuboug gbeip 21952 jo pue Jd ie paiaous ae zid Tid 6d 1910N E w ANT BT ATO amp umdzoal andT3I za 5 5 jor lt 5 o GZTZSZTIN ZTZMZETIN lt lt 1 LIZMZETN 6 9 5 231 AA Sa DH UG130 ApA 09 042604 Figure A 9 Digilent JTAG3 Low Cost JTAG Download Debug Cable Spartan 3 Starter Kit Board User Guide www xilinx com 66 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Appendix B Reference Material for Major Components Table B 1 lists the major components on the Spartan 3 Starter Kit Board including full part numbers and links to complete device data sheets Table B 1 Major Components and Data Sheet Links Device
5. ANT 3 19 6 6 3 6 6 4 198 ANIA 223 3 223 929 S23 danto 0 de Jnig a 6 gt lt 9223 699 Of I Dlx pe Le 1 1 16 ve 22 ge 123 292 SL 9223 8 34 6 6 219 813 3 16 3 16 1 lt 85 199 913 19 EI 6 VL 83 I Y All ET li AMATII oan DAS ER IF OOH 17 gs Y EERE BIS of DI 3 x 3 INIJIN INIJIN ANIJIN INIJIN ANIJIN INIJIN INIJIN Atddng emod EEFERREEREERERER L ol 06_042604 pA UG130 A Power Decoupling Capacitors Figure A 6 63 www xilinx com Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 1 800 255 7778 Appendix A Board Schemat
6. N8T1 8 4338 dZTl Em N9T1 E d101 NI TOI AIS 1 8 2 438 9 2 NBy 1 2 d6 1 9 NGC 9 dre 2 338 9 NLET 2 dec 2 NEZ 2 5 9 NZZ1 2 dlc 2 NIZI 9 dez 9 06 2 2 NETT 2 438 dZT1 9 NZTI 9 621 2 N9TI 97 21 2 101 2 58 1 Z j3un Z d r MOL c de 1 Z Z aa c j3un Z NEC aka Z MET dizi Z MIT c dezi N ZT deli N6T1 Z 338 2 1 Z ZC NSTI SCHON Z NI TOI 6 ueg 1 30zZ0089S 63 peie3 os 8 05 042604 pA UG130 A FPGA I O Connections Clock Sources Figure A 5 Spartan 3 Starter Kit Board User Guide www xilinx com 62 UG130 v1 0 April 26 2004 1 800 255 7778 23 XILINX 8 9 1eeUS 3 meg t4ouing 22 488utbu3 y90Z ZTI 8 eeQ 9599 70 000 4equnN 1ueun2og paeog ES 31111 DUI 610 00 z iubr4Rdoj3 p4eog 65 4 1 1 Ner 892 ka bd 479 879 083 ZT Kae hae I 653 ECH 3 TEI DCH 653 4316 416 o 4169 Q 4 198 889 269 169 962 689 anto 2 289 Jnig a 0 6 883 9823
7. N16 E SH HE P16 O OF O OO o el UG130_c3_01_042404 Figure 3 1 Seven Segment LED Digit Control Table 3 1 lists the FPGA connections that drive the individual LEDs comprising a seven segment character Table 3 2 lists the connections to enable a specific character Table 3 3 shows the patterns required to display hexadecimal characters Spartan 3 Starter Kit Board User Guide www xilinx com 17 UG130 v1 0 April 26 2004 1 800 255 7778 22 XILINX Chapter 3 Four Digit Seven Segment LED Display Table 3 1 FPGA Connections to Seven Segment Display Active Low Segment FPGA Pin A E14 B G13 C N15 D P15 E R16 F F13 G N16 DP P16 Table 3 2 Digit Enable Anode Control Signals Active Low Anode Control AN3 AN2 AN1 ANO FPGA Pin E13 F14 G14 D14 Table 3 3 Display Characters and Resulting LED Segment Control Values Character a b c q e f g 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 2 0 0 1 0 0 1 0 3 0 0 0 0 1 1 0 4 1 0 0 1 1 0 0 5 0 1 0 0 1 0 0 6 0 1 0 0 0 0 0 7 0 0 0 1 1 1 1 8 0 0 0 0 0 0 0 9 0 0 0 0 1 0 0 A 0 0 0 1 0 0 0 b 1 1 0 0 0 0 0 C 0 1 1 0 0 0 1 d 1 0 0 0 0 1 0 E 0 1 1 0 0 0 0 F 0 1 1 1 0 0 0 18 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 23 XILINX The LED contr
8. April 26 2004 Voltage Supply XILINX Voltage Supply Most modern keyboards and mice work equally well from a 3 3V or 5V supply The voltage supply for the PS 2 port is selectable via the JP2 jumper indicated as in Figure 1 2 located immediately above the PS 2 connector along the right edge The 3 3V setting is preferred as the FPGA s output signals operate from the 3 3V supply The JP2 jumper should be positioned as shown in Table 6 5 by default Table 6 5 PS 2 Port Supply Voltage Options PS 2 Port Jumper JP2 Supply Voltage Setting 3 3V gt JP2 CD Se gt 5V 2 0 gt WIL Some older keyboards and mice are 5V only Consequently the JP2 jumper should be set for 5V operation as shown in Table 6 5 The Spartan 3 FPGA can tolerate 5V signals due to the 2702series resistors on the PS 2 data and clock signals connected to the FPGA See the schematic in Figure A 7 for more details Spartan 3 Starter Kit Board User Guide www xilinx com 33 UG130 v1 0 April 26 2004 1 800 255 7778 22 XILINX Chapter 6 PS 2 Mouse Keyboard Port 34 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 XILINX Chapter 7 RS 232 Port The Spartan 3 Starter Kit board has an RS 232 serial port The RS 232 transmit and receive signals appear on the female DB9 connector labeled J2 indicated as in Figure 1 2 The connector is a DCE style port and connects to th
9. CCLK T15 M11 DIN FPGA CCLK Connects to A14 via 390Q resistor Spartan 3 Starter Kit Board User Guide www xilinx com 55 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Chapter 13 Expansion Connectors and Boards Expansion Boards Various expansion boards plug into the A1 A2 or B1 connectors as listed below e Spartan 3 Starter Kit Expansion Boards http www xilinx com s3boards e Digilent Expansion Boards https digilent us Sales boards cfm Peripheral e Digilent Breakout Probe Header TPH1 https digilent us Sales Product cfm Prod TPH1 e Digilent Breadboard DBB1 https digilent us Sales Product cfm Prod DBB1 e Digilent Wire wrap Board DWR1 https digilent us Sales Product cfm Prod DWR1 Digilent SPP EPP ECP Parallel Port PIO1 https digilent us Sales Product cfm Prod PIO1 56 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 SC XILINX Appendix A Board Schematics This appendix provides the schematics for the Spartan 3 Starter Kit Board Figure A 1 A1 A2 and B1 Expansion Connectors Figure A 2 Slide Switches Push Buttons LEDs and Four Character 7 Segment Display Figure A 3 Voltage Regulators JP2 Jumper Setting for PS 2 Port Voltage Figure A 4 FPGA Configuration Interface Platform Flash JTAG Connections Jumper JP1 Figure A 5 FPGA I O Connections Clock Sources Figure A 6 Power
10. 2 Bus Timing Waveforms The keyboard uses open collector drivers so that either the keyboard or the host can drive the two wire bus If the host never sends data to the keyboard then the host can use simple input pins A PS 2 style keyboard uses scan codes to communicate key press data Nearly all keyboards in use today are PS 2 style Each key has a single unique scan code that is sent whenever the corresponding key is pressed The scan codes for most keys appear in Figure 6 3 If the key is pressed and held the keyboard repeatedly sends the scan code every 100 ms or so When a key is released the keyboard sends a F0 key up code followed by the scan code of the released key The keyboard sends the same scan code regardless if a key has different shift and non shift characters and regardless whether the Shift key is pressed or not The host determines which character is intended Some keys called extended keys send an E0 ahead of the scan code and furthermore they may send more than one scan code When an extended key is released a EO FO key up code is sent followed by the scan code www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 Keyboard ESC 76 XILINX F1 F3 F4 F5 F6 F7 F8 F9 F11 F12 05 04 00 03 0B 83 0A 01 78 07 E075 EH 4 d K KE gt B EH 25 K gt E074 E i P Ba be x ES EE 2
11. 800 255 7778 Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 XILINX Chapter 3 Four Digit Seven Segment LED Display The Spartan 3 Starter Kit board has a four character seven segment LED display controlled by FPGA user I O pins as shown in Figure 3 1 Each digit shares eight common control signals to light individual LED segments Each individual character has a separate anode control input A detailed schematic for the display appears in Figure A 2 The pin number for each FPGA pin connected to the LED display appears in parentheses To light an individual signal drive the individual segment control signal Low along with the associated anode control signal for the individual character In Figure 3 1 for example the left most character displays the value 2 The digital values driving the display in this example are shown in blue The AN3 anode control signal is Low enabling the control inputs for the left most character The segment control inputs A through G and DP drive the individual segments that comprise the character A Low value lights the individual segment a High turns off the segment A Low on the A input signal lights segment a of the display The anode controls for the remaining characters AN 2 0 are all High and these characters ignore the values presented on A through G and DP ANS E13 AN2 F14 AN1 G14 ANO D14 E14 A B e F13 f G13 c
12. Decoupling Capacitors Figure A 7 RS 232 Serial Port VGA Port PS 2 Port Parallel Cable IV JTAG Interface Figure A 8 2x256Kx16 Fast Asynchronous SRAM Interface Figure A 9 Digilent JTAG3 Low Cost JTAG Download Debug Cable Spartan 3 Starter Kit Board User Guide www xilinx com 57 UG130 v1 0 April 26 2004 1 800 255 7778 Appendix A Board Schematics XILINX 8 1 199u 48eurbu3 006 6 6 sole sses sy 0 008 49QqunwN iueunoo p4eog 65 1 DUI 000 p4eog 65 0 6 8 2 S 2 T aar NW NIU 268 T Ca GEM 994 g r 694 aar 8 9U0 d 194 997 INI ZUN 12522 1 15777 25 1 2 1 HISU ZUN 00 60 00 01 EH ZHU HU ZUH OO6O00000000000000000000000000000000000000 QNO IO NON O Sul wer OQO0O00O000000000000000000000000000000000000 6 IO 80 IN OM UG130 ApA 01 042604 ion Connectors and B1 Expans 1 A1 A2 Figure A Spartan 3 Starter Kit Board User Guide www xilinx com 58 UG130 v1 0 April 26 2004 1 800 255 7778 23 XI
13. Guide www xilinx com UG130 v1 0 April 26 2004 1 800 255 7778 Table of Contents Preface About This Guide Guide Contents Additional Resources Conventions Typographical 0 en ecke Online Document are ene naeh Chapter 1 Introduction Key Components and Features oee ee een Component Locations reerde ce 4a rrr nrden E EE ed e Chapter 2 Fast Asynchronous SRAM Address Bus Connections eene eeen Write Enable and Output Enable Control Signals SRAM Data Signals Chip Enables and Byte Enables u a uunsnaanaa Chapter 3 Four Digit Seven Segment LED Display Chapter 4 Switches and LEDs Slide Switches Push Button Switches Chapter 5 VGA Port Signal Timing for a 60Hz 640x480 VGA Display VGA Signal TIMING aranka eee d ERO be Ee ER EE Chapter 6 PS 2 Mouse Keyboard Port Keyboard eee ee edi ee Mouse PEE Voltage Supply 456 0002 2 00 Eier deb Chapter 7 RS 232 Port Chapter 8 Clock Sources Chapter 9 FPGA Configuration Modes and Functions FPGA Configuration Mode Settings 0 0 0 cece eneen Spartan 3 Starter Kit Board User Guide ww
14. M E EO 65 5 ER u E EJ H 4 4 52 12 Ctrl 14 IB C V B M gt 1 A Shift 12 21 2A 32 4 1 3A 1 is 4A 59 Alt Space Ctrl 11 29 lo p E014 UG130 c6 03 042404 Figure 6 3 PS 2 Keyboard Scan Codes The host can also send data to the keyboard Table 6 3 provides a short list of some often used commands Table 6 3 Common PS 2 Keyboard Commands Command ED Turn on off Num Lock Caps Lock and Scroll Lock LEDs The keyboard acknowledges receipt of Description an ED command by replying with an FA after which the host sends another byte to set LED status The bit positions for the keyboard LEDs appear in Table 6 4 Write a 1 to the specific bit to illuminate the associated keyboard LED Table 6 4 Keyboard LED Control 7 6 5 4 3 2 1 0 and Caps Num Scroll en Lock Lock Lock EE Echo Upon receiving an echo command the keyboard replies with the same scan code EE F3 Set scan code repeat rate The keyboard acknowledges receipt of an F3 by returning an FA after which the host sends a second byte to set the repeat rate FE Resend Upon receiving a resend command the keyboard resends the last scan code sent Reset Resets the keyboard The keyboard sends data to the host only when both the data and clock lines are High the Idle state Because the host is the bus master the
15. crystal oscillator clock source bottom side of board see Figure 1 3 Socket for an auxiliary crystal oscillator clock source Gei FPGA configuration mode selected via jumper settings Push button switch to force FPGA reconfiguration FPGA configuration happens automatically at power on 7 LED indicates when FPGA is successfully configured i8 Three 40 pin expansion connection ports to extend and enhance the Spartan 3 Starter Kit Board 3 See www xilinx com s3board for compatible expansion cards Compatible with Digilent Inc peripheral boards https digilent us Sales boards cfm Peripheral FPGA serial configuration interface signals available on the A2 and 81 connectors PROG_B DONE INIT_B CCLK DONE JTAG port for low cost download cable Digilent JTAG download debugging cable connects to PC parallel port JTAG download debug port compatible with the Xilinx Parallel Cable IV and MultiPRO Desktop Tool AC power adapter input for included international unregulated 5V power supply Power on indicator LED Gei On board 3 3V 2 5V and1 2V regulators Component Locations Figure 1 2 and Figure 1 3 indicate the component locations on the top side and bottom side of the board respectively Spartan 3 Starter Kit Board User Guide www xilinx com 11 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Chapter 1 Introduction A1 Expansion Connector A2 Expansion Con
16. 0 v1 0 April 26 2004 lt XILINX Chapter 1 Introduction The Xilinx Spartan 3 Starter Kit provides a low cost easy to use development and evaluation platform for Spartan 3 FPGA designs Key Components and Features Figure 1 1 shows the Spartan 3 Starter Kit board which includes the following components and features 200 000 gate Xilinx Spartan 3 XC3S200 FPGA in a 256 ball thin Ball Grid Array package XC35200FI256 1 4 320 logic cell equivalents Twelve 18K bit block RAMs 216K bits Twelve 18x18 hardware multipliers Four Digital Clock Managers DCMs to 173 user defined I O signals 2Mbit Xilinx XCF02S Platform Flash in system programmable configuration PROM 1Mbit non volatile data or application code storage available after FPGA configuration Jumper options allow FPGA application to read PROM data or FPGA configuration from other sources 1M byte of Fast Asynchronous SRAM bottom side of board see Figure 1 3 2 Two 256Kx16 ISSI IS61LV25616AL 10T 10 ns SRAMs Configurable memory architecture Single 256Kx32 SRAM array ideal for MicroBlaze code images Two independent 256Kx16 SRAM arrays Individual chip select per device Individual byte enables 3 bit 8 color VGA display port 9 pin RS 232 Serial Port DB9 9 pin female connector DCE connector Maxim MAX3232 RS 232 transceiver translator Uses straight through serial cable to connect to compu
17. 00 255 7778 22 XILINX Chapter 11 JTAG Programming Debugging Ports J7 5 2 nm UG130 011 02 042504 Figure 11 2 Digilent JTAG Cable Provided with Kit Connects to the J7 Header The J7 header also supports the Xilinx Parallel Cable 3 PC3 download debugging cable when using the flying leaders Again make sure that the signals at the end of the JTAG cable align with the labels listed on the board Figure A 4 provides a detailed schematic of the J7 header and the JTAG programming chain Parallel Cable IV MultiPro Desktop Tool JTAG Header J5 The J5 header shown as in Figure 1 2 supports the Xilinx download debugging cables listed below e MultiPro Desktop Tool http www xilinx com bvdocs publications ds114 pdf e Parallel Cable IV PC IV http toolbox xilinx com docsan xilinx4 data docs pac cables6 html Use the 14 pin ribbon cable supplied with both cables to connect to the J5 header DO NOT use the flying leads that are also provided with some cables Although the MultiPro Desktop Tool and the Parallel Cable IV support multiple FPGA configuration modes the Spartan 3 Starter Kit board only supports the JTAG configuration method The header is designed for a keyed socket However the Spartan 3 Starter Kit uses only stake pins The outline of the keyed connector appears around the J5 header as shown in Figure 11 3 When properly inserted the keyed header matches the outline on the board and the ribbon cable cro
18. C2 G3 WE SRAM WE DB6 C1 K4 OE SRAM OE 52 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 Expansion Connectors XILINX Table 13 2 Pinout for A1 Expansion Connector Continued Schematic Name FPGA Pin Connector FPGA Pin Schematic Name DB7 B1 P9 CSA FPGA DOUT BUSY LSBCLK M7 M10 MA1 DB0 MA1 DB1 F3 G4 MA1 DB2 SRAM A6 SRAM A5 MA1 DB3 E3 F4 MA1 DB4 SRAM A8 SRAM A7 MA1 DB5 G5 E4 MA1 DB6 SRAM A10 SRAM A9 MA1 DB7 HA H3 MA1 ASTB SRAM A12 SRAM A11 MA1 DSTB J3 J4 MA1 WRITE SRAM A14 SRAM A13 MA1 WAIT K5 K3 MA1 RESET SRAM A16 SRAM A15 MA1 INT L3 JTAG Isolation JTAG Isolation SRAM A17 TMS C13 C14 TCK FPGA JTAG TMS FPGA JTAG TCK TDO ROM Platform Flash Header J7 pin 3 TDO A JTAG TDO The A1 expansion connector shares connections with the 256Kx16 SRAM devices specifically the SRAM address lines and the OE and WE control signals Similarly the JTAG chain is available on pins 36 through 40 Pin 20 is the FPGA DOUT BUSY configuration signal and toggles during the FPGA configuration process A2 Connector Pinout The A2 expansion connector is located along the top edge of the board on the right as Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 indicated by in Figure 1 2 Figure 13 3 provides the pinout for the A2 connector The FP
19. CLK output is three stated with a pull up resistor to Vecaux 2 5V The Platform Flash presents serial data on the FPGA s DIN pin pin M11 Spartan 3 FPGA Platform Flash py JP1 DIN DO 20 Flash Read INIT_B OE RESET DONE CE CCLK USER I O xx FPGA pin number UG130_c10_02_042504 Figure 10 2 Read Additional Data from Platform Flash by Setting the JP1 Jumper The resistor between the CCLK output and FPGA pin A14 prevents any accidental conflicts between the two signals 42 www xilinx com 1 800 255 7778 Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 Disable Option 22 XILINX Additional FPGA logic is required to read the Platform Flash data as described in the following application note e XAPP694 Reading User Data from Configuration PROMs http www xilinx com bvdocs appnotes xapp694 pdf Disable Option If the JP1 jumper is removed then the Platform Flash is disabled potentially allowing configuration via an expansion board connected to one of the expansion connectors Spartan 3 Starter Kit Board User Guide www xilinx com 43 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Chapter 10 Platform Flash Configuration Storage 44 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 XILINX Chapter 11 JTAG Programming Debugging Ports The Spartan 3 Starter Kit board includes a JTAG programming and debugging c
20. E pin goes High at the end of configuration the Platform Flash is disabled and placed in low power mode Spartan 3 Starter Kit Board User Guide www xilinx com 41 UG130 v1 0 April 26 2004 1 800 255 7778 Chapter 10 Platform Flash Configuration Storage Spartan 3 FPGA DIN DO INIT_B DONE CCLK Platform Flash JP1 m DO Default OE RESET CE CLK UG130_c10_01_042504 Figure 10 1 Default Platform Flash Option Flash Read Option The Spartan 3 Starter Kit Board includes a 2Mbit Platform Flash configuration PROM The XC35200 FPGA on the board only requires slightly less than 1Mbit for configuration data The remainder of the Platform Flash is available to store other non volatile data such as revision codes serial numbers coefficients an Ethernet MAC ID or code for an embedded processor such as MicroBlaze within the FPGA To allow the FPGA to read from Platform Flash after configuration the JP1 jumper must be properly positioned as shown in Figure 10 2 When the jumper is in this position the Platform Flash is always enabled After FPGA configuration completes the FPGA application drives the INIT_B pin High FPGA pin N9 Consequently the Platform Flash data pointer is not reset and points to the additional data following the FPGA configuration data To read any subsequent data the FPGA application generates additional clock pulses on the RCLK signal from FPGA pin A14 After configuration the FPGA s C
21. Figure 1 2 are on the top edge of the board Connector A1 is on the top left and A2 is on the top right The B1 connector indicated as in Figure 1 2 is along the left edge of the board A1 Expansion Connector Figure 13 1 A2 Expansion Connector 1 x E O oO 5 masma O 2 2 z l E y Li el mam mM ma UG130 c12 01 042504 Spartan 3 Starter Kit Board Expansion Connectors Table 13 1 summarizes the capabilities of each expansion port Port A1 supports a maximum of 32 user I O pins while the other ports provide up to 34 user I O pins Some pins are shared with other functions on the board which may reduce the effective I O count for specific applications For example pins on the A1 port are shared with the SRAM address signals and the SRAM OE and WE control signals Table 13 1 Expansion Connector Features Connector User I O SRAM Address JTAG Serial Configuration Parallel Configuration A1 32 i i A2 34 Bl 34 Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 www xilinx com 1 800 255 7778 51 XILINX Chapter 13 Expansion Connectors and Boards Each port offers some ability to program the FPGA on the Spartan 3 Starter Kit Board For example port A1 provides additional logic to drive the FPGA and Platform Flash JTAG chain Similarly ports A2 and B1 provide connections for Master or Slave Serial mode co
22. G130 v1 0 April 26 2004 SC XILINX Chapter 9 FPGA Configuration Modes and Functions FPGA Configuration Mode Settings In most applications for the Spartan 3 Starter Kit Board the FPGA automatically boots from the on board Platform Flash memory whenever power is applied or the PROG push button is pressed However the board supports all the available configuration modes via the J8 header indicated as Gei in Figure 1 2 Table 9 1 provides the available option settings for the J8 header Additionally the JP1 jumper setting is required when using Master Serial configuration mode as further described in Platform Flash Jumper Options OPI The default jumper settings for the board are e All jumpers in the J8 header are installed e The JP1 jumper is in the Default position Table 9 1 Header J8 Controls the FPGA Configuration Mode Configuration MO M1 M2 Mode jin i 2 Description lt M0 M1 M2 gt A Master Serial GND J8 JP1 DEFAULT The FPGA automatically boots from the Platform lt 0 0 0 gt TT u Flash 20 lg of MO M1 M2 JP1 JP1 The FPGA attempts to boot from a serial configuration source attached to either expansion connector A2 or B1 Slave Serial GND J8 JP1 Another device connected to either the A2 or B1 expansion lt 1 1 1 gt B 8 w connector provides serial data and clock to load the FPGA s Mo M1 M2 Master Parallel JP1 The FPGA attempts to boot fr
23. GA connections are specified in parentheses Most of the A2 expansion connector pins connect only with the FPGA and are not shared Pin 35 connects to the auxiliary clock socket if an oscillator is installed in the socket Pins 36 through 40 include the signals required to configure the FPGA in Master or Slave Serial mode www xilinx com 53 1 800 255 7778 XILINX Table 13 3 Pinout for A2 Expansion Connector Chapter 13 Expansion Connectors and Boards Schematic Name FPGA Pin GND Veco 3 3V Veco all banks PA IO2 D5 PA IO4 D6 PA IO6 E7 PA IO8 D7 PA IO10 D8 PA IO12 D10 PA IO14 B4 PA IO16 B5 PA IO18 B6 MA2 DB1 A7 MA2 DB3 A8 MA2 DB5 B10 MA2 DB7 B11 MA2 DSTB A12 MA2 WAIT A13 MA2 INT GCK4 D9 Oscillator socket DONE R14 FPGA DONE CCLK T15 FPGA CCLK Connects to A14 via 390Q resistor B1 Connector Pinout Connector FPGA Pin Schematic Name VU 5V E6 PA IO1 C5 PA IO3 C6 PA IO5 C7 PA IO7 C8 PA IO9 C9 PA IO11 A3 PA IO13 A4 PA IO15 A5 PA IO17 B7 MA2 DBO B8 MA2 DB2 A9 MA2 DB4 A10 MA2 DB6 B12 MA2 ASTB B13 MA2 WRITE B14 MA2 RESET B3 PROG B FPGA PROG B N9 INIT FPGA INIT B M11 DIN The B1 expansion connector is located on the right edge of the board as indicated by 9 in Figure 1 2 Table 13 4 prov
24. IE1 Soe 0 8 5 20 4 N ET 97 438 6 62 dez S N6Z1 N6Z1 20 97 d8z1 v d821 90 8 82 N8Z1 6 10 4 2 97 438 6 NZZ1 daz 67 8 N9Z1 57 Come d S2 8 d101 9 8 1 01 438 201 zor TOI TOI S UE 0 1 aueg 0 1 138 1 jet 38 8 NZE1 85199 T 9 199 8 dZET T di 1 9 338 T 338 NIET 9 T de 1 9 OCT T 9 NC 6 9 dez1 T N6Z1 9 N6Z1 T d8Z1 9 d821 T 9 N8Z1 T S 9 dZZ1 T 9 N221 T deri 8 651 T 43un T 9 NSZ1 Ide 9 T NI T 9 T 338 J3UN 0I 01 Q9 338 zol 501 101 101 T aueg 0 1 ueg 0 1 3rz0089S 91 pa4ap tos 338 d6 1 N6E1 dre NEZI dec NZZ1 die NIZI doc NOZI 61 338 NETT d2Tl NI 338 diet Z NIO1 TOI ueg 0 1 dar 328 5 6 E N6E 1 5 dre 6 5 5 328 dec NECI diZl NIZI 5 deci 5 NOZI
25. LINX 8 2 95 5 b QZ ZT E reet osesToq 40uing paeog ES 1 4 urbu3 99 DUI 00Z iubr4Rdoj3 p4eog ES ius AZ x N UG130 ApA 02 042604 Figure A 2 Slide Switches Push Buttons LEDs and Four Character 7 Segment Display 59 www xilinx com Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 1 800 255 7778 Appendix A Board Schematics XILINX B E SUS b QZ ZT E 53 esesToq 40uing paeog ES 1 4 urbu3 99 DUI 610 006 iubr4Rdoj3 608 ES ius SII ETN Mnz T LNIIAN 404 na z XNYIIN Xnu33n 0676 OJIN 1 5 5 a lo zdf 4edunf Arddns 4enod paeoghex 82980141 JnaT L 69 UG130 ApA 03 042604 Figure A 3 Voltage Regulators JP2 Jumper Setting for PS 2 Port Voltage Spartan 3 Starter Kit Board User Guide www xilinx com 1 800 255 7778 60 UG130 v1 0 April 26 2004 23 XILINX 8 4 199uS v Z ZI E Sieg esee and 3 meg 0 005 4equnN iueun2o 40uing 428508 ES 1 33 4 ur6u3 DUI Ue TIbIq 00 z iubr4Rdoj3 p4eog S ius 4 6 J 2v0 0 2 0 41 ZU 113 9123 WON sul buranbr uo2 ueum eponN eT4eS esAeIS 329195 Sr 30 T300N Pue 8300N uo perteisur eq pinoys 61 Puriaoug 62D Woa uo
26. PGA Pin 1 DATA PS2D M15 2 Reserved 3 GND GND 4 Voltage Supply 5 CLK PS2C M16 6 Reserved Both a PC mouse and keyboard use the two wire PS 2 serial bus to communicate with a host device the Spartan 3 FPGA in this case The PS 2 bus includes both clock and data Both a mouse and keyboard drive the bus with identical signal timings and both use 11 bit words that include a start stop and odd parity bit However the data packets are organized differently for a mouse and keyboard Furthermore the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard The PS 2 bus timing appears Table 6 2 and Figure 6 2 The clock and data signals are only driven when data transfers occur and otherwise they are held in the idle state at logic Spartan 3 Starter Kit Board User Guide www xilinx com 29 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Keyboard 30 Chapter 6 PS 2 Mouse Keyboard Port High The timings define signal requirements for mouse to host communications and bidirectional keyboard communications Table 6 2 PS 2 Bus Timing Symbol Parameter Min Max Tex Clock High or Low time 30 ps 50 us Tsy Data to clock setup time 5 us 25 us Tun Clock to data hold time 5 Us 25 us Tok Tok Edge 0 T gus 10 CLK PS2C t Tsu DATA PS2D AO Pe UG130 c6 02 042404 Figure 6 2 PS
27. Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 XILINX XILINX Xilinx and the Xilinx logo shown above are registered trademarks of Xilinx Inc Any rights not expressly granted herein are reserved CoolRunner RocketChips Rocket IP Spartan StateBENCH StateCAD Virtex XACT XC2064 XC3090 XC4005 and XC5210 are registered trademarks of Xilinx Inc The shadow X shown above is a trademark of Xilinx Inc ACE Controller ACE Flash A K A Speed Alliance Series AllianceCORE Bencher ChipScope Configurable Logic Cell CORE Generator CoreLINX Dual Block EZTag Fast CLK Fast CONNECT Fast FLASH FastMap Fast Zero Power Foundation Gigabit Speeds and Beyond HardWire HDL Bencher IRL J Drive JBits LCA LogiBLOX Logic Cell LogiCORE LogicProfessor MicroBlaze MicroVia MultiLINX NanoBlaze PicoBlaze PLUSASM PowerGuide PowerMaze QPro Real PCI RocketlO SelectlO SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch SMARTswitch System ACE Testbench In A Minute TrueMap UIM VectorMaze VersaBlock VersaRing Virtex ll Pro Virtex ll EasyPath Wave Table WebFITTER WebPACK WebPOWERED XABEL XACT Floorplanner XACT Performance XACTstep Advanced XACTstep Foundry XAM XAPP X BLOX XC designated products XChecker XDM XEPLD Xilinx Foundation Series Xilinx XDTV Xinfo XSI XtremeDSP and ZERO are trademarks of Xilinx Inc The Programmable Logic Company
28. This manual contains the following chapters Chapter 1 Introduction Chapter 2 Fast Asynchronous SRAM Chapter 3 Four Digit Seven Segment LED Display Chapter 4 Switches and LEDs Chapter 5 VGA Port Chapter 6 PS 2 Mouse Keyboard Port Chapter 7 RS 232 Port Chapter 8 Clock Sources Chapter 9 FPGA Configuration Modes and Functions Chapter 10 Platform Flash Configuration Storage Chapter 11 JTAG Programming Debugging Ports Chapter 12 Power Distribution Appendix A Board Schematics Appendix B Reference Material for Major Components Additional Resources For additional information go to http support xilinx com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL Tutorials Tutorials covering Xilinx design flows from design entry to verification and debugging http support xilinx com support techsup tutorials index htm Answer Browser Database of Xilinx solution records http support xilinx com xlnx xil ans browser jsp Spartan 3 Starter Kit Board User Guide www xilinx com 5 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Preface About This Guide Resource Description URL Application Notes Descriptions of device specific design techniques and approache
29. Vendor Part Number Description Data Sheet Link Xilinx Inc XC3S200 4FT256C Spartan 3 FPGA http www xilinx com bvdocs publications ds099 pdf Xilinx Inc XCF02SVO20C Platform Flash Configuration Flash PROM http www xilinx com bvdocs publications ds123 pdf Integrated Silicon IS61LV25616AL 10T 256Kx16 Fast Asynchronous SRAM Solutions Inc ISSI http www issi com pdf 61LV25616AL pdf Maxim MAX3232 Dual Channel RS 232 Voltage Translator http pdfserv maxim ic com en ds MAX3222 MAX3241 pdf Epson SG 8002 F 50 MHz Crystal Oscillator http www knap at de pdf kat 0o sg8002jf pdf Interex APA 101M 05 5V Switching Regulator National LM1086CS A DJ 3 3V Regulator Semiconductor http www national com pf LM LM1086 html Datasheet STMicroelectronics 7 2 5V Regulator http www st com stonline books pdf docs 2574 pdf 1 2V Regulator Spartan 3 Starter Kit Board User Guide www xilinx com 67 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Appendix B Reference Material for Major Components 68 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004
30. Y direction byte oft al of P Lo xopxr xepes axo xo 7 P X Start bit Idle state 32 ppp N e 4 Stop bit Stop bit Stop bit Start bit Start bit Idle state UG130 c6 04 042404 Figure 6 4 PS 2 Mouse Transaction As shown in Figure 6 5 a PS 2 mouse employs a relative coordinate system wherein moving the mouse to the right generates a positive value in the X field and moving to the left generates a negative value Likewise moving the mouse up generates a positive value in the Y field and moving down represents a negative value The XS and YS bits in the status byte define the sign of each value where a 1 indicates a negative value Y values YS 0 X values X values XS 1 XS 0 Y values YS 1 UG130 c6 05 042404 Figure 6 5 The Mouse Uses a Relative Coordinate System to Track Movement The magnitude of the X and Y values represent the rate of mouse movement The larger the value the faster the mouse is moving The XV and YV bits in the status byte indicate when the X or Y values exceed their maximum value an overflow condition A 1 indicates when an overflow occurs If the mouse moves continuously the 33 bit transmissions repeat every 50 ms or so The L and R fields in the status byte indicate Left and Right button presses A 1 indicates that the associated mouse button is being pressed www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0
31. ansion Connector refer to Expansion Connectors page 51 Table 2 2 External SRAM Control Signal Connections to Spartan 3 FPGA Signal FPGA Pin A1 Expansion Connector Pin OE K4 16 WE G3 18 SRAM Data Signals Chip Enables and Byte Enables The data signals chip enables and byte enables are dedicated connections between the FPGA and SRAM Table 2 3 shows the FPGA pin connections to the SRAM designated IC10 in Figure A 8 Table 2 4 shows the FPGA pin connections to SRAM IC11 Table 2 3 SRAM IC10 Connections Signal FPGA Pin 1015 R1 1014 P1 1013 L2 1012 J2 1011 H1 1010 F2 109 P8 108 D3 107 B1 106 Cl 105 C2 104 R5 103 T5 IO2 R6 IO1 T8 IO0 N7 CE1 chip enable IC10 P7 UB1 upper byte enable IC10 T4 LB1 lower byte enable IC10 P6 Spartan 3 Starter Kit Board User Guide www xilinx com UG130 v1 0 April 26 2004 1 800 255 7778 15 XILINX 16 Table 2 4 SRAM IC11 Connections Signal FPGA Pin IO15 N1 1014 M1 1013 K2 1012 C3 IO11 F5 1010 G1 IO9 E2 108 D2 IO7 D1 106 El 105 G2 104 1 103 K1 102 M2 IO1 N2 IO0 P2 CE2 chip enable IC11 N5 UB2 upper byte enable IC11 R4 LB2 lower byte enable IC11 P5 Chapter 2 Fast Asynchronous SRAM To disable an SRAM drive the associated chip enable pin High www xilinx com 1
32. ash Configuration Storage The Spartan 3 Starter Kit board has an XCFO2S serial configuration Flash PROM to store FPGA configuration data and potentially additional non volatile data including MicroBlaze application code To configure the FPGA from Platform Flash memory all three jumpers must be installed on the J8 header indicated as Gei in Figure 1 2 Platform Flash Jumper Options JP1 The Platform Flash has three optional settings controlled by the JP1 jumper which is located in the upper right hand corner of the board adjacent to the Platform Flash configuration PROM The JP1 jumper is indicated as in Figure 1 2 A detailed schematic is provided in Figure A 4 Table 10 1 summarizes the available options which are described in more detail below Table 10 1 Jumper JP1 Controls the Platform Flash Options Jumper JP1 Option Setting Description Default JP1 The FPGA boots from Platform Flash No additional data storage is available Flash Read JP1 The FPGA boots from Platform Flash which is permanently enabled The FPGA jg can read additional data from Platform Flash Disable Jumper removed Platform Flash is disabled Other configuration data source ee JP provides FPGA boot data Default Option For most applications this is the default jumper setting As shown in Figure 10 1 the Platform Flash is enabled only during configuration when the FPGA s DONE pin is Low When the DON
33. ctical refresh frequencies in the 60 Hz to 120 Hz range The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency VGA Signal Timing 26 The signal timings in Table 5 3 are derived for a 640 pixel by 480 row display using a 25 MHz pixel clock and 60 Hz 1 refresh Figure 5 3 shows the relation between each of the timing symbols The timing for the sync pulse width Tpw and front and back porch intervals Trp and Tgp are based on observations from various VGA displays The front and back porch intervals are the pre and post sync pulse times Information cannot be displayed during these times Table 5 3 640x480 Mode VGA Timing Vertical Sync Horizontal Sync Symbol Parameter Time Clocks Lines Time Clocks Ts Sync pulse time 16 7 ms 416 800 521 32 us 800 Tp sp Display time 15 36 ms 384 000 480 25 6 Us 640 Tpw Pulse width 64 us 1 600 2 3 84 us 96 Trp Front porch 320 us 8 000 10 640 ns 16 Tpp Back porch 928 us 23 200 29 1 92 us 48 T 14 Tdisp E T o Tow bp UG130_c5_03_042404 Figure 5 3 VGA Control Timing www xilinx com 1 800 255 7778 Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 VGA Signal Timing XILINX Generally a counter clocked by the pixel clock controls the horizontal timing Decoded counter values ge
34. d along the lower edge of the board toward the right edge The switches are labeled SW7 through SW0 Switch SW7 is the left most switch and SWO is the right most switch The switches connect to an associated FPGA pin as shown in Table 4 1 A detailed schematic appears in Figure A 2 Table 4 1 Slider Switch Connections Switch SW7 SW6 SW5 SW4 SW3 SW2 SW1 SWO FPGA Pin K13 K14 J13 J14 H13 H14 G12 F12 When in the UP or ON position a switch connects the FPGA pin to Vcco a logic High When DOWN or in the OFF position the switch connects the FPGA pin to ground a logic Low The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry although such circuitry could easily be added to the FPGA design programmed on the board A 4 7KQ series resistor provides nominal input protection Push Button Switches The Spartan 3 Starter Kit board has four momentary contact push button switches indicated as in Figure 1 2 These push buttons are located along the lower edge of the board toward the right edge The switches are labeled BIN3 through BTNO Push button switch BIN3 is the left most switch BTNO the right most switch The push button switches connect to an associated FPGA pin as shown in Table 4 2 A detailed schematic appears in Figure A 2 Table 4 2 Push Button Switch Connections Push Button BTN3 User Reset BTN2 BTN1 BTNO FPGA Pin L14 L13 M14 M13
35. e DB9 DTE style serial port connector available on most personal computers and workstations Use a standard straight through serial cable to connect the Spartan 3 Starter Kit board to the PC s serial port Figure 7 1 shows the connection between the FPGA and the DB9 connector including the Maxim MAX3232 RS 232 voltage converter indicated as in Figure 1 2 The FPGA supplies serial output data as LVTLL or LVCMOS levels to the Maxim device which in turn converts the logic value to the appropriate RS 232 voltage level Likewise the Maxim device converts the RS 232 serial input data to LVTLL levels for the FPGA A series resistor between the Maxim output pin and the FPGA s RXD pin protects against accidental logic conflicts A detailed schematic appears in Figure A 7 Hardware flow control is not supported on the connector The port s DCD DTR and DSR signals connect together as shown in Figure 7 1 Similarly the port s RTS and CTS signals connect together Pin 9 DB9 Serial Port Connector DB9 front view Connector Maxim MAX3232 Spartan 3 FPGA RS 232 Voltage Converter G ND UG130 c7 01 042404 Figure 7 1 RS 232 Serial Port Spartan 3 Starter Kit Board User Guide www xilinx com 35 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Chapter 7 RS 232 Port The FPGA connections to the Maxim RS 232 translator appear in Table 7 1 Table 7 1 Accessory Port Connections to the Spartan 3 FPGA
36. hain Both the Spartan 3 FPGA and the Platform Flash devices are part of the JTAG chain as shown in Figure 11 1 Additionally there are two JTAG headers for driving the JTAG signals from various supported JTAG download and debugging cables A Digilent JTAG3 low cost parallel to JTAG cable is included as part of the kit and connects to the J7 header Digilent Parallel JTAG3 Cable IV i Spartan 3 FPGA PlatformFlash Parallel MultiPro Cable 3 Desktop XC3S400FT256C XCF02S oo Header Header J7 J5 Header pin number x UG130_c11_01_042504 Figure 11 1 Spartan 3 Starter Kit Board JTAG Chain JTAG Header J7 This J7 JTAG header consists of 0 1 inch stake pins and is indicated as in Figure 1 2 located toward the top edge of the board directly below the two expansion connectors The Digilent low cost parallel port to JTAG cable fits directly over the J7 header stake pins as shown in Figure 11 2 When properly fitted the cable is perpendicular to the board Make sure that the signals at the end of the JTAG cable align with the labels listed on the board The other end of the Digilent cable connects to the PC s parallel port The Digilent cable is directly compatible with the Xilinx iMPACT software The schematic for the Digilent cable appears in Figure A 9 Spartan 3 Starter Kit Board User Guide www xilinx com 45 UG130 v1 0 April 26 2004 1 8
37. ics XILINX 8 2 199u8 002 61 6 Seet 9509 3 meg 0 009 4equnN 3 6 4ouinu paeog ES 1 4 urbua sur yu lIbIq 805 wubtaAdeg Dr i za14 paeog ES 5 61 0 10148 LINI IN ZX NS IN 9x0N9 NIG IQL SONS aNoG 0QL x0N9 3199 391 X N9 90Hd SWL EXONS 338 TONS 8 1 p I9lIe4ed BLZ w 9cu 6 8 5 6 1 QQQOQQOoQ 140d 52 256 Ir peor oN 0 TEZEXEN 1400 Tet4ss fiaose22e 40 pasn TO V TOI e3 E Ki 30178 g NIU INIH 11 2 z noa 4 1000 5 NO e NMO 10 SON OO TPE TE sag 51 5 5 4 390 A 07 042604 Figure A 7 5 232 Serial Port VGA Port PS 2 Port Parallel Cable IV JTAG Interface UG130 A UG130 v1 0 April 26 2004 Spartan 3 Starter Kit Board User Guide www xilinx com 1 800 255 7778 64 23 XILINX 8 8 1eeUS 3 Aad 13 22 488utbu3 I 3ueg uo Tg pue pue yueq G issus 55 vORE ZI E eeQ 9599 0 009 4equnN iueun2og P4eog ES 1 DUI Ue TIbIq 00 z iubr4Rdoj3 p4eog S ius 21 q q q z q 1 141 qj 4j HAHAHAHAHAHA pue z sueq G i us 855 8 40278 ANHO O 6 2 6 6 2
38. ides the pinout for the B1 connector The FPGA connections are specified in parentheses Most of the B1 expansion connector pins connect only with the FPGA and are not shared Pins 36 through 40 include the signals required to configure the FPGA in Master or Slave Serial mode These same pins plus pins 5 7 9 11 13 15 17 19 and 20 provide the signals required to configure the FPGA in Master or Slave Parallel mode 54 www xilinx com 1 800 255 7778 Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 Expansion Connectors XILINX Table 13 4 Pinout for B1 Expansion Connector Schematic Name FPGA Pin Connector FPGA Pin Schematic Name GND VU 5V PB DBO T3 E10 PB ADR1 FPGA RD WR 8 config PB DB1 N11 C11 PB ADR2 FPGA D1 config PB DB2 P10 D11 PB ADR3 FPGA D2 config PB DB3 R10 C12 PB ADR4 FPGA D3 config PB DB4 T7 D12 PB ADR5 FPGA D4 config PB DB5 R7 E11 PB WE FPGA D5 config PB DB6 N6 B16 PB OE FPGA D6 config PB DB7 M6 R3 PB CS FPGA D7 config FPGA CS B config PB CLK C15 C16 MB1 DB0 MB1 DB1 D15 D16 MB1 DB2 481 1 83 E15 E16 MB1 DB4 MB1 DB5 F15 G15 MB1 DB6 MB1 DB7 G16 H15 MB1 ASTB MB1 DSTB H16 J16 MB1 WRITE MB1 WAIT K16 K15 MB1 RESET MB1 INT L15 B3 PROG B FPGA PROG_B DONE R14 N9 INIT FPGA DONE FPGA INIT_B
39. is a service mark of Xilinx Inc All other trademarks are the property of their respective owners Xilinx Inc does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx Inc reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx Inc will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or information as one possible implementation of a feature application or standard Xilinx makes no representation that such implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation including but not limited to any warranties or representations that the implementation is free from claims of infringement as well as any implied warranties of merchantability or fitness for a particular purpose Xilinx Inc devices and products are protected under U S Patents Other U S and foreign patents pending Xilinx Inc does not represent that device
40. keyboard checks whether the host is sending data before driving the bus The clock line can be used as a clear to send signal If the host pulls the clock line Low the keyboard must not send any data until the clock is released The keyboard sends data to the host in 11 bit words that contain a 0 start bit followed by eight bits of scan code LSB first followed by an odd parity bit and terminated with a 1 stop bit When the keyboard sends data it generates 11 clock transitions at around 20 to 30 kHz and data is valid on the falling edge of the clock as shown in Figure 6 2 Spartan 3 Starter Kit Board User Guide www xilinx com 31 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Mouse Chapter 6 PS 2 Mouse Keyboard Port A mouse generates a clock and data signal when moved otherwise these signals remain High indicating the Idle state Each time the mouse is moved the mouse sends three 11 bit words to the host Each of the 11 bit words contains a 0 start bit followed by 8 data bits LSB first followed by an odd parity bit and terminated with a 1 stop bit Each data transmission contains 33 total bits where bits 0 11 and 22 are 0 start bits and bits 10 21 and 32 are 1 stop bits The three 8 bit data fields contain movement data as shown in Figure 6 4 Data is valid at the falling edge of the clock and the clock period is 20 to 30 kHz r Mouse status byte X direction byte 23
41. nector 31 LEE 2 e CSS 292 Im co m 2Mbit Dei PlatformFlash XILINX 18 XC3S200 DENE FPGA POWER POWER 26 ER e E NI 2 ooool Bring e ug130 01 02 042604 B1 Expansion Connector KE onn Dd Dd m Figure 1 2 Xilinx Spartan 3 Starter Kit Board Top Side 256Kx16 SRAM 256Kx16 ug130_c1_03_042604 Figure 1 3 Xilinx Spartan 3 Starter Kit Board Bottom Side 12 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 SC XILINX Chapter 2 Fast Asynchronous SRAM The Spartan 3 Starter Kit board has a megabyte of fast asynchronous SRAM surface mounted to the backside of the board The memory array includes two 256Kx16 ISSI IS61LV25616AL 10T 10 ns SRAM devices as shown in Figure 2 1 A detailed schematic appears in Figure A 8 ISSI 256Kx16 SRAM 10 ns see Table 2 3 IJ a O 15 0 A 17 0 CE C10 UB LB WE OE Spartan 3 FPGA ISSI 256Kx16 SRAM 10 ns see Table 2 4 see Table 2 1 gt xx FPGA pin number UG130_c2_01_042604 Figure 2 1 FPGA to SRAM Connections Spartan 3 Starter Kit Board User Guide www xilinx com 13 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Address Bus Connections 14 Chapter 2 Fast Asynchronous SRAM The SRAM array forms either a single 256Kx32 SRAM memory or two independent 256Kx16 ar
42. nerate the HS signal This counter tracks the current pixel display location on a given row A separate counter tracks the vertical timing The vertical sync counter increments with each HS pulse and decoded values generate the VS signal This counter tracks the current display row These two continuously running counters form the address into a video display buffer For example the on board fast SRAM is an ideal display buffer No time relationship is specified between the onset of the HS pulse and the onset of the VS pulse Consequently the counters can be arranged to easily form video RAM addresses or to minimize decoding logic for sync pulse generation Spartan 3 Starter Kit Board User Guide www xilinx com 27 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Chapter 5 VGA Port 28 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 XILINX Chapter 6 PS 2 MouselKeyboard Port The Spartan 3 Starter Kit board includes a PS 2 mouse keyboard port and the standard 6 pin mini DIN connector labeled J3 on the board and indicated as in Figure 1 2 Figure 6 1 shows the PS 2 connector and Table 6 1 shows the signals on the connector Only pins 1 and 5 of the connector attach to the FPGA A detailed schematic appears in Figure A 7 UG130 c6 01 042404 Figure 6 1 PS 2 DIN Connector Table 6 1 PS 2 Connections to the Spartan 3 FPGA PS 2 DIN Pin Signal F
43. nfiguration Finally port B1 also offers Master or Slave Parallel configuration mode Each 40 pin expansion header shown in Figure 13 2 uses 0 1 inch 100 mil DIP spacing Pin 1 on each connector is always GND Similarly pin 2 is always the 5V DC output from the switching power supply Pin 3 is always the output from the 3 3V DC regulator Pin 39 Pin 3 3 3V Pin 1 GND Pin 39 LEE BERET EXEJEJETE ETETEJETETETES ES SER ETE ETEJETETETETE CEO DIE n 9 9 9 n n nn Gn ER EJ GER E n cn E ERE ER E N Pin 4 Pin 2 VU Pin 40 5V O Pin 40 UG130_c12_02_042504 Figure 13 2 40 pin Expansion Connector The pinout information for each connector appears below The tables include the connections between the FPGA and the expansion connectors plus the signal names used in the detailed schematic in Figure A 1 A1 Connector Pinout The A1 expansion connector is located along the top edge of the board on the left as indicated by in Figure 1 2 Table 13 2 provides the pinout for the Al connector The FPGA connections are specified in parentheses Table 13 2 Pinout for A1 Expansion Connector Schematic Name FPGA Pin Connector FPGA Pin Schematic Name GND VU 5V Veco 3 3V Veco all banks N8 ADRO DBO N7 L5 ADR1 SRAM AO DB1 T8 N3 ADR2 SRAM A1 DB2 R6 M4 ADR3 SRAM A2 DB3 T5 M3 ADR4 SRAM A3 DB4 R5 L4 ADR5 SRAM A4 DB5
44. ol signals are time multiplexed to display data on all four characters as shown in Figure 3 2 Present the value to be displayed on the segment control inputs and select the specified character by driving the associated anode control signal Low Through persistence of vision the human brain perceives that all four characters appear simultaneously similar to the way the brain perceives a TV display Aas 0 A ff AN1 AB CDEFG DP DISP3 DISP2 DISP1 DISPO UG130 c3 02 042404 Figure 3 2 Drive Anode Input Low to Light an Individual Character This scanning technique reduces the number of I O pins required for the four characters If an FPGA pin were dedicated for each individual segment then 32 pins are required to drive four 7 segment LED characters The scanning technique reduces the required I O down to 12 pins The drawback to this approach is that the FPGA logic must continuously scan data out to the displays a small price to save 20 additional I O pins Spartan 3 Starter Kit Board User Guide www xilinx com 19 UG130 v1 0 April 26 2004 1 800 255 7778 22 XILINX Chapter 3 Four Digit Seven Segment LED Display 20 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 XILINX Chapter 4 Switches and LEDs Slide Switches The Spartan 3 Starter Kit board has eight slide switches indicated as in Figure 1 2 The switches are locate
45. om a parallel configuration source 11 0 attached to the B1 expansion connector Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 www xilinx com 39 1 800 255 7778 XILINX Chapter 9 FPGA Configuration Modes and Functions Table 9 1 Header J8 Controls the FPGA Configuration Mode Continued Configuration Mode i 2 Description lt M0 M1 M2 gt i Slave Parallel GND J8 JP1 Another device connected to the B1 expansion connector 01 1 B u BEE provides parallel data and clock to load the FPGA e Mo m1 M2 JTAG a JP1 The FPGA waits for configuration via the four wire JTAG lt 1 0 1 gt interface M0 M1 M2 Program Push Button DONE Indicator LED The Spartan 3 Starter Kit Board includes two FPGA configuration functions located near the VGA connector and the AC power input connector as shown in Figure 9 1 The PROG in Figure 9 1 drives the FPGA s PROG_B programming pin When pressed the PROG push button forces the FPGA to reconfigure and reload it configuration data The DONE LED shown as 8 in Figure 9 1 connects to the FPGA s DONE pin and lights 40 push button shown as up when the FPGA is successfully configured Figure 9 1 www xilinx com 1 800 255 7778 DONE PROG UG130_c9_03_042604 The PROG Button and the DONE LED Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 XILINX Chapter 10 Platform Fl
46. on 1 2V regulators Similarly the 3 3V supply feeds all the Veco voltage supply inputs to the FPGA s I O banks and powers most of the components on the board The 2 5V regulator powered by the 3 3V regulator supplies power to the FPGA s Vccayx supply inputs The Vccaux voltage input supplies power to Digital Clock Managers DCMs within the FPGA and supplies some of the I O structures In specific all of the FPGA s dedicated configuration pins such as DONE PROG B CCLK and the FPGA s JTAG pins are powered by VccAux The FPGA configuration interface on the board is powered by 3 3V Consequently the 2 5V supply has a current shunt resistor to prevent back current Finally a 1 2V regulator supplies power to the FPGA s VccINT voltage inputs which power the FPGA s core logic The board uses three discrete regulators to generate the necessary voltages However various power supply vendors are developing integrated solutions specifically for Spartan 3 FPGAs Figure A 3 provides a detailed schematic of the various voltage regulators Similarly Figure A 6 shows the power decoupling capacitors www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 ST XILINX Chapter 13 Expansion Connectors and Boards Expansion Connectors The Spartan 3 Starter Kit board has three 40 pin expansion connectors labeled A1 A2 and B1 The A1 and A2 connectors indicated as and Go respectively in
47. onsequently the following discussion pertains to both CRTs and LCD displays Within a CRT display current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a raster pattern horizontally from left to right and vertically from top to bottom As shown in Figure 5 2 information is only displayed when the beam is moving in the forward direction left to right and top to bottom and not during the time the beam returns back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass pixel 0 639 640 pixels are displayed each time the beam traverses the screen VGA Display Retrace No information pixel 479 0 pixel 479 639 is displayed during this time Stable current ramp Information is displayed during this time Total horizontal time perk retrace time Y Horizontal display time poles tess gt front porch 4 front porch sm Horizontal sync signal back porch sets the retrace frequency UG130_c5_02_042404 Figure 5 2 CRT Display Timing Example The size of the beams the frequency at which the beam traces across the display and the frequency at which the electron beam is modulated determine the display resolution Spartan 3 Starter Ki
48. ost PC monitors or flat panel LCD displays using a standard monitor cable Pin 5 Pin 10 Pin 15 DB15 VGA Connector DB15 front view Connector 2700 R AAA o R R13 G 2700 reen AAN oG T12 2700 BI MN o B R11 Horizontal Sync O HS R9 Vertical Sync vs T10 xx FPGA pin number GND UG130_c5_01_042604 Figure 5 1 VGA Connections from Spartan 3 Starter Kit Board Asshown in Figure 5 1 the Spartan 3 FPGA controls five VGA signals Red R Green G Blue B Horizontal Sync HS and Vertical Sync VS all available on the VGA connector The FPGA pins that drive the VGA port appear in Table 5 1 A detailed schematic is in Figure A 7 Spartan 3 Starter Kit Board User Guide www xilinx com 23 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Chapter 5 VGA Port Table 5 1 VGA Port Connections to the Spartan 3 FPGA Signal FPGA Pin Red R R12 Green G T12 Blue B R11 Horizontal Sync HS R9 Vertical Sync VS T10 Each color line has a series resistor to provide 3 bit color with one bit each for Red Green and Blue The series resistor uses the 75Q VGA cable termination to ensure that the color signals remain in the VGA specified OV to 0 7V range The HS and VS signals are TTL level Drive the R G and B signals High or Low to generate the eight possible colors shown in Table 5 2 Table 5 2 3 Bit Display Color Codes
49. owever in bus ngdbui ld option name specifications such as design name bus 7 0 they are required 6 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 Conventions 23 XILINX Convention Braces Meaning or Use A list of items from which you must choose one or more Example lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has been omitted IOB 1 IOB 2 Name Name QOUT CLKIN Horizontal ellipsis Repetitive material that has allow block block name been omitted loci loc2 locn Online Document The following conventions are used in this document Convention Meaning or Use Example See the section Additional Cross reference link to a Resources for details Blue text location in the current Ze document Refer to Title Formats in Chapter 1 for details Red eek Cross reference link to a See Figure 2 5 in the Virtex II location in another document Handbook i Go to http www xilinx com Blue underlined text Hyperlink to a website URL for the latest speed files Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 www xilinx com 1 800 255 7778 XILINX Preface About This Guide 8 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG13
50. rays Both SRAM devices share common write enable WE output enable OE and address A 17 0 signals However each device has a separate chip select CS control and individual byte enable controls to select the high or low byte in the 16 bit data word UB and LB respectively The 256Kx32 configuration is ideally suited to hold MicroBlaze instructions However it alternately provides high density data storage for a variety of applications such as digital signal processing DSP large data FIFOs and graphics buffers Both 256Kx16 SRAMs share 18 bit address control lines as shown in Table 2 1 These address signals also connect to the A1 Expansion Connector see Expansion Connectors page 51 Table 2 1 External SRAM Address Bus Connections to Spartan 3 FPGA Address Bit FPGA Pin A1 Expansion Connector Pin A17 L3 35 A16 K5 33 A15 K3 34 A14 J3 31 A13 J4 32 A12 H4 29 A11 H3 30 A10 G5 27 A9 E4 28 A8 E3 25 A7 F4 26 A6 F3 23 A5 G4 24 A4 L4 14 A3 M3 12 A2 M4 10 A1 N3 8 AO L5 6 www xilinx com 1 800 255 7778 Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 Write Enable and Output Enable Control Signals 23 XILINX Write Enable and Output Enable Control Signals Both 256Kx16 SRAMs share common output enable OE and write enable WE control lines as shown in Table 2 2 These control signals also connect to the A1 Exp
51. rieanbrjuo2 85 aui aui ssedhq oi Zdf Pue Idf 0 E Z surd uo pa jeis r ave s32o q 6 14609 5 4epeaH a2eja4aiu I 7 ey uey 4auie4 uorirsod paeoq ea4eudraed e uo4j ueArap bureg sue sjeubrs gylf eui uaum ureu2 aui aje duo2 oi uo 001 Igl 990190 pe reisur eq isnu buriaous y 18 pue zug 4012auuO2 OL 030 35 1411 3 N3 duMSH 8 8 1 dle 8 LINI NIET NZZ1 uote anb rjuo2 Teraes 8086 8 3193 alels j nejop 4edunf ou watjywog S910N sa dunr 123135 epo H d 191ON abe 4015 104 618 4edunf AIL SWL sSUOT gt UN4 1044409 4 uote ant pue 94 63 964 981 ecd 08 WW 824 eal ANW 208 JIN aN9 AIL 004 1011 SWL 4epeaH 5 25 4 5 A 04 042604 UG130_Ap FPGA Configuration Interface Platform Flash JTAG Connections Jumper JP1 Figure A 4 61 www xilinx com 1 800 255 7778 Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 ICS Board Schemati Appendix A XILINX 8 6 Hays 3 M 4ouing 33 148eurbu3 002 61 6 91eg s e I q 0 609 49qunwN 1ueunoo p4eog 65 1 DUI wertdig Yybrahdoy p4eog ES jue TIbIg ZX129 8 dz 1 3 109 8 MEET n 83109 amp dc 1 sr amp 0 8 dien 1129 5 MEET 0 8 N
52. s http support xilinx com apps appsweb htm Data Sheets Device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http support xilinx com xlnx xweb xil publications index jsp Problem Solvers Interactive tools that allow you to troubleshoot your design issues http support xilinx com support troubleshoot psolvers htm Tech Tips Latest news design tips and patch information for the Xilinx design environment http www support xilinx com xlnx xil tt home jsp Conventions This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and Courier font program files that the system speed grade 100 displays Courier bold Literal commands that you ngdbuild design name enter in a syntactical statement E that you select File Open Helvetica bold Keyboard shortcuts Ctrl C Variables in a syntax statement for which you must ngdbuild design_name supply values See the Development System Italic font References to other manuals Reference Guide for more information If a wire is drawn so that it Emphasis in text overlaps the pin of a symbol the two nets are not connected An optional entry or Square brackets parameter H
53. s shown or products described herein are free from patent infringement or from any other third party right Xilinx Inc assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made Xilinx Inc will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited The contents of this manual are owned and copyrighted by Xilinx Copyright 1994 2004 Xilinx Inc All Rights Reserved Except as stated herein none of the material may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of any material contained in this manual may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 The following table shows the revision history for this document Version Revision 04 26 04 1 0 Initial Xilinx release Spartan 3 Starter Kit Board User
54. sses over the top edge of the board The red colored lead indicates pin 1 on the cable and should be on the left side 46 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 Parallel Cable IV MultiPro Desktop Tool JTAG Header J5 XILINX Red trace m indicates pin 1 Notch on outline matches key on header Parallel Cable IV JTAG UG130_c11_03_042504 Figure 11 3 Use 14 Pin Ribbon Cable to Connect Parallel Cable IV or the MultiPro Desktop Tool to the J5 Header Spartan 3 Starter Kit Board User Guide www xilinx com 47 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Chapter 11 JTAG Programming Debugging Ports 48 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 lt XILINX Chapter 12 Power Distribution AC Wall Adapter The Spartan 3 Starter Kit includes an international ready AC wall adapter that produces a 5V DC output Connect the AC wall adapter to the barrel connector along the left edge of the board indicated as Gi in Figure 1 2 There is no power switch to the board To disconnect power remove the AC adapter from the wall or disconnect the barrel connector The POWER indicator LED shown as Gei in Figure 1 2 lights up when power is properly applied to the board If the jumpers in the J8 header and JP1 header are properly configured and there is a valid design in the Platform Flash memory then
55. t Board User Guide www xilinx com 25 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Chapter 5 VGA Port Modern VGA displays support multiple display resolutions and the VGA controller dictates the resolution by producing timing signals to control the raster patterns The controller produces TTL level synchronizing pulses that set the frequency at which current flows through the deflection coils and it ensures that pixel or video data is applied to the electron guns at the correct time Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location The Spartan 3 Starter Kit board uses three bits per pixel producing one of the eight possible colors shown in Table 5 2 The controller indexes into the video data buffer as the beams move across the display The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel As shown in Figure 5 2 the VGA controller generates the HS horizontal sync and VS vertical sync timings signals and coordinates the delivery of video data on each pixel clock The pixel clock defines the time available to display one pixel of information The VS signal defines the refresh frequency of the display or the frequency at which all information on the display is redrawn The minimum refresh frequency is a function of the display s phosphor and electron beam intensity with pra
56. ter or workstation serial port Second RS 232 transmit and receive channel available on board test points Spartan 3 Starter Kit Board User Guide www xilinx com 9 UG130 v1 0 April 26 2004 1 800 255 7778 XILINX 10 Chapter 1 Introduction Digilent Low Cost 23 Parallel Port to JTAG Included Cable Parallel Cable IV a Low Cost JTAG 22 MutliPro Desktop Tool Download Cable JTAG Connector Connector A1 Expansion XILINX XCFO2S 2Mbit Configuration A2 Expansion 69 PROM Header Bi Expansion 19 Header Configuration 18 DONE LED 1 PROGRAM 2 XILINX Il Push Button 8 color XC3S200 Configuration VGA Port Spartan 3 Mode Select FPGA Jumpers 6 RS 232 Port RS 232 Serial Port Driver Auxiliary 08 6 Oscillator Socket Oscillator D I 4 Character 7 t LED 4 Push Button 8 Slide Switches 4 8 LEDs vcco LED Regulator Regulator Regulator 5 VDC 2A Supply 100 240V AC Input 50 60 Hz 25 AC Wall Adapter Included UG130 c1 01 042504 Figure 1 1 Xilinx Spartan 3 Starter Kit Board Block Diagram e P5 2 style mouse keyboard port 9 Four character seven segment LED display 9 Eight slide switches Eight individual LED outputs Four momentary contact push button switches Gei www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 Component Locations 23 XILINX 50 MHz
57. the DONE indicator LED shown as 3 in Figure 1 2 also lights up The AC wall adapter is directly compatible for North America Japan and Taiwan locales Other locations might require a socket adapter to convert from the North American standard to the local power socket standard The AC wall adapter operates from 100V to 240V AC input at 50 or 60 Hz Voltage Regulators There are multiple voltages supplied on the Spartan 3 Starter Kit Board as summarized in Table 12 1 Table 12 1 Voltage Supplies and Sources Voltage Source Supplies 5V DC AC Wall Adapter 5V switching power supply 3 3V regulator in Figure 1 2 Optionally PS 2 port via jumper JP2 setting Pin 1 VU on A1 A2 B1 expansion connectors 3 3V DC National Semiconductor LM1086CS ADJ 3 3V 2 5V and 12V regulators regulator in Prose aa Veco supply input for all FPGA I O banks Most components on the board Pin 3 on A1 A2 B1 expansion connectors 25V DC STMicroelectronics LF25CDT 2 5V regulator Vccaux supply input to FPGA in Figure 1 2 1 2V DC 1 2V regulator in Figure 1 2 Vecint supply input to FPGA Spartan 3 Starter Kit Board User Guide UG130 v1 0 April 26 2004 Overall the 5V DC switching power supply that connects to AC wall power powers the board A 3 3V regulator powered by the 5V DC supply generates power for the 2 5V and www xilinx com 1 800 255 7778 49 XILINX 50 Chapter 12 Power Distributi
58. w xilinx com UG130 v1 0 April 26 2004 1 800 255 7778 XILINX Program Push Button DONE Indicator LED 22 0000 40 Chapter 10 Platform Flash Configuration Storage Platform Flash Jumper Options PU EN Default Dphon EE EE 41 Flash Read Option san a 42 Disable Optio ases task od roo eed seruo e ate ori deae da added 43 Chapter 11 JTAG Programming Debugging Ports JTAG Header 7 45 Parallel Cable IV MultiPro Desktop Tool JTAG Header J5 46 Chapter 12 Power Distribution AC Wall Adapter is ccce dod in e e ROT EE 49 Voltage Regulators carver arce ERE Rep Kan Exo Ee HR ERR ee 49 Chapter 13 Expansion Connectors and Boards Expansion Connectors de EE reb Rd repr bee siebe ated 51 AL Connector UInOut oret re Liv a aci des cete 52 A2 Connector Piriout o sate en pe wawas u Va E pate Vai ene ag 53 1 Conrnector Prout oes ait kee rir REI Sabaha 54 Expansion Boards NNN E e e weeen ep ERR ee eed 56 Appendix A Board Schematics Appendix B Reference Material for Major Components 4 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 0 April 26 2004 SC XILINX Preface About This Guide This user guide describes the components and operation of the Spartan 3 Starter Kit Board Guide Contents

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