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MSP430x1xx Family User's Guide (Rev. B)

1. ENC SHI 4 4 S As SAMPCON Ay Single channel f SAMPCON 4 4 Single channel ANT 4 2 13 4 Sequence of SAMPCON 4 4 Channel sic sic sic sic sic 1 2 3 4 2 3 4 Sequence of SAMPCON 1 LN t Channel sic 5 Sc sic sic sic sic Conversion Period Sample Period Figure 15 24 Use of MSC Bit With Repeated Modes ADC12CLK SHTO SHT1 1 Sampling SAMPCON Timer 4 5 0 SHI E FA X A X 4 CA A Repeat Single SAMPCON _ 47 Channel sic B MU Repeat Single SAMPCON 4 Of Sic Sic 5 Sic sic sic sic si 5 N 56 PR 2 3 V 1 _2 1221 Repeat Sequence SAMPCON 1 of Channels Sic Sic Sic sic 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 Repeat Sequence of hannels SIC sic sic 5 sce SC se SC sce Sc sc sic sic sic sic sic Conversion Period Sample Period 15 28 MSC 0 MSC 1
2. ENC su 3 F gt X X X fC TA ar al Repeat Single E SAMPCON 4 7 lt C enel MSC 0 sic Fa j LU Repeat Single SAMPCON 4 1 lt channel Mee Sic Sic Sc sic sic sic sic Sic sc sc sc 4 2 3 4 2 13 ET Repeat Sequence T SAMPCON 4 A 4 T 1 of Channel Med sic sic sic sic 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 Sequenc A 5 L of Channels MCF SIC sic Sic Sic Sc Sc Sc Sc Sc sic SIC sic sic sic Sic sic Conversion Period Sample Period 16 20 Sampling 16 6 4 Sample Timing Considerations The A D converter uses the charge redistribution method Thus when the inputs are internally switched to sample the input analog signal the switching action causes displacement currents to flow into and out of the analog inputs These current spikes or transients occur atthe leading and falling edges of the sample pulse and usually decay and settle before causing any problems because typically the external time constant is less than that presented by the internal effective RC Internally
3. USART Peripheral Interface UART Mode 1247 Control and Status Registers 12 5 2 Transmit Control Register UOTCTL U1TCTL The transmit control register shown in Figure 12 17 controls the USART hardware associated with the transmit operation Figure 12 17 Transmitter Control abd UOTCTL U1TCTL UOTCTL 071h U1TCTL 078h Bit 0 Bit 1 Bit 2 Bit 3 Bits 4 5 Bit 6 Bit 7 12 18 CKPL SSEL1 SSELO URXSE X rw 0 rw 0 rw 0 rw 0 rw 0 rw O rw O0 rw 1 The transmitter empty TXEPT flag is set when the transmitter shift register and UxTXBUF are empty and is reset when data is written to UXTXBUF It is set by a SWRST Unused The TXWake bit controls the transmit features of the multiprocessor communication modes Each transmission started by loading the UxTXBUF uses the state of the TXWake bitto initialize the address identification feature It must not be cleared the USART hardware clears this bit once it is transferred to the WUT a SWRST also clears the TXWake bit The receive start edge control bit if set requests a receive interrupt service For a successful interrupt service the corresponding enable bits URXIE and GIE must be set The advantage of this bit is that it starts the controller clock system including MCLK along with the interrupt service and keeps it running by modifying the mode control bits If the
4. 2 5 20 5 3 4 Short Form of Emulated Instructions 5 21 5 3 5 Miscellaneous eee e Let Lene ers eee 5 22 5 4 Instr ction Maps ec ses ere Ga ER Be e 5 23 Hardware Multiplier 6 1 6 14 Hardware Multiplier Module Support 6 2 6 2 Hardware Multiplier Operation 6 3 6 2 1 Multiply Unsigned 16 x16 bit 16 x8 bit 8 x 16 bit 8x8 bit 6 4 6 2 2 Multiply Signed 16 x16 bit 16 x8 bit 8 160 8 8 6 4 6 2 3 Multiply Unsigned and Accumulate 16 x16 bit 168 bit 8 x16 bit 8 x8 bit 6 5 6 2 4 Multiply Signed and Accumulate 16 x16 bit 16 x8 bit 8 x16 bit 8 x8 bit 6 5 6 3 Hardware Multiplier Registers 6 6 6 4 Hardware Multiplier Special Function Bits 6 7 65 Hardware Multiplier Software Restrictions 6 7 6 5 1 Hardware Multiplier Software Restrictions Address Mode 6 7 6 5 2 Hardware Multiplier Software Restrictions Interrupt Routines 6 8 6 5 3 Hardware Multiplier Software Restrictions MACS 6 9 Basic Clock Mod le 2 5 ir RE en
5. B 59 Interconnection of Flash Memory 5 C 2 Flash Memory Module1 Disabled Module2 Can Execute Code Simultaneously C 3 Flash Memory Module Example C 4 Segments in Flash Memory Module 4K Byte Example 5 Flash Memory Module Block C 6 Block Diagram of the Timing Generator in the Flash Memory Module C 7 Basic Flash EEPROM Module Timing During the Erase Cycle C 9 Basic Flash Memory Module Timing During Write Single Byte or Word Cycle C 11 Basic Flash Memory Module Timing During a Block Write Cycle C 11 Access Violation Non Maskable Interrupt Scheme in Flash Memory Module C 19 Signal Connections to MSP430 JTAG Pins C 22 Logd ot to PEL d gd db gd ld I O 200 10 C EN ons b 4 anni i O ON OU C1 Q1 O1 Oi QC Oi CO C C1 C1 O1 co 4o0o0i cCcon o Tables Interrupt Control Bits SFRS 3 11 MSP43
6. 11 9 New Period lt Old 11 10 Timer Continuous 11 10 Continuous Mode Flag Setting 11 11 Output Unit in Continuous Mode for Time Intervals 11 11 Timer Up Down Mode 1 11 12 Output Unit in Up Down Mode Il 11 12 Timer Up Down Direction 1 11 13 Up Down Mode Flag Setting 11 13 Altering TBCLO Timer in Up Down Mode 11 14 Gapture Gompare BIOCKS iieii deneraino etana bed ede ew ewe time RES mak pu 11 15 Capture Logic Input Signal 11 16 Capture Signal edi tede Meee edere eh eee dad 11 16 Capture Cycle kh nitens tede ed Res 11 17 Software Capture Example 2 11 19 Output Uni peregre 11 23 Output Control Block 11 25 Output Examples Timer in Up 11 27 Output Exam
7. OFFFFh CCRO CCR1 CCR2 Oh 4 gt Output Mode 6 PWM Toggle Set Output Mode 2 PWM Toggle Reset TAIFG EQU1 EQUI TAIFG EQUI EQUI Interrupt Events EQU2 EQUO EQU2 EQU2 EQUO EQU2 The count direction is always latched with a flip flop Figure 10 14 This is useful because it allows the user to stop the timer and then restart it in the same direction it was counting before it was stopped For example if the timer was counting down when the MCx bits were reset then it will continue counting in the down direction if it is restarted in up down mode If this is not desired the CLR bit in the TACTL register must be used to clear the direction Note that the CLR bit affects other setup conditions of the timer Refer to Section 10 6 fora discussion of the Timer_A registers Timer Up Down Direction Control POR CLR in TACTL Up Down For 16 Bit Timer TAR Low Down Direction High Up Direction Up Down Mode TAR gt CCRO Timer Clock Timer_A 10 11 Timer Modes In up down mode the interrupt flags CCIFGO and TAIFG are set at equal time intervals Figure 10 15 Each flag is set only once during the period but they are separated by 1 2 the timer period CCIFGO is set when the timer counts from CCRO 1 to CCRO and TAIFG is set when the timer completes counting down from 0001h to 0000h Each flag is capable of producing a CPU interrupt when enabled Figure 10
8. 12 A 12 Flash Control Registers Word 55 A 12 A 13 Hardware Multiplier Word Access A 13 A 14 Timer A Registers Word Access A 14 A 15 Timer B Registers Word Access A 16 Instruction Set Description B 1 BA instruction Set Overview iic cis d Ub RIA dashed Paved ig Ed Vbi bd B 2 Instruction Formats eco Ere t Reni e Ra B 4 B 1 2 Conditional and Unconditional Jumps Core Instructions B 5 1 3 Emulated Instructions 7 6 B 2 Instruction Set Description B 8 Flash Memory c i rie i Ie exa teehee Eee C 1 C 1 Flash Memory Organization C 2 C 1 1 Why Is a Flash Memory Module Divided Into Several Segments 5 C 2 Flash Memory Data Structure and Operation 5 C 2 1 Flash Memory Basic Functions C 6 C 2 2 Flash Memory Block Diagram C 6 1 Contents xii 4 5 C 2 3 Flash Memory Basic Operation
9. B 52 Borrow Is Treated as a NOT B 56 Borrow Is Treated as a NOT Carry B 57 Flash Memory Module s in MSP430 Devices C 2 xxiii xxiv Chapter 1 Introduction This chapter outlines the features and capabilities of the Texas Instruments MSP430x1xx family of microcontrollers The MSP430 employs a von Neumann architecture therefore all memory and peripherals are in one address space MSP430 devices constitute a family of ultralow power 16 bit RISC microcontrollers with an advanced architecture and rich peripheral set The architecture uses advanced timing and design features as well as a highly orthogonal structure to deliver a processor that is both powerful and flexible The MSP430 consumes less than 400 uA in active mode operating at 1 MHz in a typical 3 V system and can wake up from a lt 2 standby mode to fully synchronized operation in less than 6 us These exceptionally low current requirements combined with the fast wake up time enable a user to build a system with minimum current consumption and maximum battery life Additionally the MSP430x1xx family has an abundant mix of peripherals and memory sizes enabling true system on a chip designs The peripherals include a 12 bit A D slope A D multiple timers some wi
10. 13 13 Receive Interrupt State Diagram 13 13 Transmit Interrupt Operation 13 14 USART Control Register 7 13 16 Transmit Control Register UOTCTL UTTCTL 13 17 USART Clock Phase and Polarity 13 18 Receive Control Register UORCTL UTRCTL 13 18 USART Baud Rate Select Register 13 19 USART Modulation Control Register 13 19 Receive Data Buffer UURXBUF U1RXBUF 13 19 Transmit Data Buffer UOTXBUF U1TXBUF 13 20 Schematic of Comparator 14 2 RC Filter Response at the Output of the Comparator 14 4 A Interrupt 14 5 Transfer Characteristic and Power Dissipation in a CMOS Inverter Buffer 14 9 Transfer Characteristic and Power Dissipation in a CMOS Gate 14 9 Application Example With One Active Driving R3 and Three Passive Pins With Applied Analog 5
11. 12 15 USART1 Control and Status Registers 12 15 Interrupt Flag Set Conditions 12 20 Receive Data Buffer Characters 12 22 Commonly Used Baud Rates Baud Rate Data and Errors 12 29 USART Interrupt Control and Enable Bits SPI 13 9 USARTO Control and Status Registers 18 15 USART1 Control and Status Registers 13 15 Comparator Control Registers 14 6 Reference Voltage Configurations 15 5 Conversion Modes Summary 15 9 ADC12IV Interrupt Vector 15 38 Reference Voltage Configurations 16 5 Conversion Modes Summary 16 8 Maximum DTC Cycle Time 16 37 Control Bits for Write or Erase Operation C 8 Conditions to Read Data From Flash Memory C 12 12 4 12 2 12 3 12 4 16 1 16 2 Examples 4800 Baud usur bee
12. 16 11 16 4 4 Repeat Sequence of Channels Mode 16 13 16 4 5 Switching Between Conversion Modes 16 15 16 4 6 Power DOWrn eviter Ee s Y enses RUE deme RA CER ata 16 16 17 18 19 Contents 16 5 Conversion Clock and Conversion Speed 16 17 16 6 Sampling 2 eth d ADARE INE ER IUe A 16 18 16 6 1 Sampling 16 18 16 6 2 Sample Signal Input 16 19 16 6 3 Using the MSG Bit Dee enews 16 20 16 6 4 Sample Timing Considerations 16 21 16 7 ADC10 Control Registers 16 22 16 7 1 Control Registers ADC10CTLO and ADC10CTL1 16 22 16 7 2 Analog Input Enable Control Register 16 26 16 7 3 Conversion Memory Register ADC10MEM 16 27 16 8 Data Transfer Control High Speed Conversion Support 16 27 16 81 DTG Operation x ia 16 28 16 8 2 Data Transfer Control Registers in ADC10 16 35 16 8 3 Software Examples for Using
13. 15 7 15 3 3 Using the Temperature Diode 15 7 15 4 Conversion Memory 15 8 15 5 Conversion MOdeS c uis pt CEP bie oni 15 9 15 5 4 Single Channel Single Conversion Mode 15 10 15 5 2 Sequence of Channels Mode 15 12 15 5 8 Repeat Single Channel Mode 15 16 15 5 4 Repeat Sequence of Channels Mode 15 17 15 5 5 Switching Between Conversion Modes 15 19 15 5 6 Power DOWLD ous Esp Dep Dess LUE NAUES VOS 15 20 15 6 Conversion Clock and Conversion Speed 15 21 15 7 Samiplifigs et Eo eee o rr re Aes cae Nu Ue drive ead 15 22 15 7 1 Sampling 15 22 15 7 2 Sample Signal Input 15 23 15 7 8 Sampling Modes 15 24 15 7 4 Using the MSO Bt 2 ssteconisieeberterec be gere feb bei dade 15 27 15 7 5 Sample Timing Considerations 15 29 15 8 ADC12 Control Registers 15 30 15 8 1 Control Registers ADC12CTLO and ADC12CTL1
14. 4 7 Example of RAM Peripheral Organization 4 8 Program Counte eb eet EOD CERDO epa 5 2 System Stack Poltiter eec Rex EE de ERE 5 2 Stack Usage monumen ara E ete eee Lite Mamba iG toa Pian 5 3 PUSE SP and POP SP ore ec bise inetd ech er Lei bn eder 5 3 Status Register Bits orati ruei merri daO 5 4 Operand Fetch Operation 5 13 Double Operand Instruction Format 5 18 Single Operand Instruction Format 5 19 Conditional Jump Instruction 5 20 Core Instruction Map 5 23 Connection of the Hardware Multiplier Module to the Bus System 6 2 Block Diagram of the MSP430 16 x16 Bit Hardware 6 3 Registers of the Hardware Multiplier 6 6 Basic Clock Schematic 7 2 Principle of LEXA Oscillator dee 7 4 Off Signals for the LFXT1 Oscillator 7 5 Off Signals for Oscillator
15. 15 6 15 4 Conversion Memory 15 8 15 5wGonversion Modes 2008000 15 9 15 6 Conversion Clock and Conversion Speed 15 21 Urat wr 000007 15 22 15 8 ADC12 Control Registers 15 30 Introduction 15 1 Introduction The ADC12 12 bit analog to digital converter shown in Figure 15 1 has five main functional blocks that can be individually configured and optimized O O O O L Figure 15 1 ADC12 Schematic ADC core with sample and hold Conversion memory and configuration Reference voltage and configuration Conversion clock source select and control Sample timing and conversion control Internal Oscillator ADC120SC ACLK MCLK SMCLK REFON VeRER 25V INCH 0Ah gt e 4 VREF VREF on on ESTHER VREF Vepgr 1 5V or 2 5V 1 Reference ADC12CTLx 0 3 AVss Ref_X ol AVSS ADC12SSEL ad al d ADCi2CTLx4 6 Y AIC ADG12DIV a2 o 28 4 ADC12CLK Divide by a4 6 Analog 1 2 3 4 5 6 7 8 a5 Multiplexer Sample 12 1 gt and a6 gt Hold a7 SM Sampling SAMPCON Timer Lp a9 lt
16. 12 26 12 7 Baud Rate Considerations 12 26 12 7 1 Bit Timing in Transmit Operation 12 27 12 7 2 Typical Baud Rates and Errors 12 29 12 7 8 Synchronization 12 30 13 USART Peripheral Interface SPI Mode 13 1 13 1 USART Peripheral 13 2 13 2 USART Peripheral Interface SPI 13 3 13 2 1 SPI Mode Features 13 3 13 3 Synchronous Operation 13 4 13 3 1 Master SPI 13 7 13 3 2 Slave SPI Mode 13 8 13 4 Interrupt and Control Functions 13 9 13 4 1 USART Receive Transmit Enable Bit Receive Operation 13 9 13 4 2 USART Receive Transmit Enable Bit Transmit Operation 13 11 13 4 3 USART Receive Interrupt Operation 13 13 13 4 4 Transmit Interrupt Operation 13 14 13 5 Control and Status Registers 13 15 13
17. 12 7 12 3 5 Address Bit Multiprocessor Format 12 9 12 4 Interrupt and Enable Functions 12 11 12 4 1 USART Receive Enable Bit 12 11 12 4 2 USART Transmit Enable 12 12 12 4 8 USART Receive Interrupt Operation 12 13 12 4 4 USART Transmit Interrupt Operation 12 14 12 5 Control and Status Registers 12 15 12 5 1 USART Control Register UOCTL 12 16 12 5 2 Transmit Control Register UOTCTL 12 18 12 5 3 Receiver Control Register UORCTL UTRCTL 12 19 12 5 4 Baud Rate Select and Modulation Control Registers 12 21 12 5 5 Receive Data Buffer UORXBUF UTRXBUF 12 22 12 5 6 Transmit Data Buffer UOTXBUF UTTXBUF 12 22 viii Contents 12 6 Utilizing Features of Low Power 12 23 12 6 1 Receive Start Operation From UART Frame 12 23 12 6 2 Maximum Utilization of Clock Frequency vs Baud Rate UART Mode 12 25 12 6 3 Support of Multiprocessor Modes for Reduced Use of MSP430 Resources
18. LSB 0148h ro ro r ro All conversion result bits of type rw ADC12MEMS Unused Unused Unused Unused MSB Conversion Result LSB 0146h ro ro ro All conversion result bits of type rw ADC12MEM2 Unused Unused Unused Unused MSB Conversion Result LSB 0144h ro ro ro All conversion result bits of type rw ADC12MEM 1 Unused Unused Unused Unused MSB Conversion Result LSB 0142h ro ro r ro All conversion result bits of type rw ADC12MEMO Unused Unused Unused Unused MSB Conversion Result LSB 0140h ro ro ro ro All conversion result bits of type rw Peripheral File Map 9 ADC12 Registers Byte and Word Access A 9 ADC12 Registers Byte Word Access Continued Bit 15 14 3 12 11 0 9 1 1 8 ADC12IE ADC12IE 15 121 14 ADC12IE 13 ADC12IE 12 ADC12IE 11 ADC12IE 10 ADC12IE 9 ADC12IE 8 01A6h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IFG ADC12IFG 15 ADC12IFG 14 ADC12IFG 13 ADC12IFG 12 ADC12IFG 11 ADC12IFG 10 ADC12IFG 9 ADC12IFG 8 01A4h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12CTL1 CStartAdd 3T CStartAdd 2t CStartadd 1t CStartAdd ot SHs it sHs of SHPt ISSH 01A2h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12CTLO 5 1
19. 16 5 Offset Error of the Temperature 16 7 Powering Down Active 16 16 Considerations Before Turning the ADC10 and Voltage Reference On or Off 16 17 Availability of ADC10CLK During Conversion 16 18 Warning Modifying ADC Control Register During Active Conversion 16 26 DTC Transfer While ADC10 Is Busy 16 36 Asterisked Instructions B 3 Operations Using the Status Register SR for Destination B 4 Conditional and Unconditional Jumps B 6 Disable Interrupt s reote LR rete ird NRI oar M ER RR B 28 Enable Interr pt esd aah te BASU ee BI eec EE B 29 Emulating No Operation Instruction B 42 The System Stack Pointer B 43 The System Stack Pointer B 44 FILA SUBSTITUTION cor E BE e LE vu M eee B 47 REG and REG B Emulation Rer eee ir brad B 48 Borrow Is Treated as a NOT
20. C 6 C 2 4 Flash Memory Status During Code Execution C 8 C 2 5 Flash Memory Status During Erase C 8 C 2 6 Flash Memory Status During Write Programming C 10 Flash Memory Control Registers 13 C 3 1 Flash Memory Control Register 1 C 13 C 3 2 Flash Memory Control Register 2 C 15 C 3 3 Flash Memory Control Register C 16 Flash Memory Interrupt and Security Key Violation C 18 C 4 1 Example of an NMI Interrupt C 20 C 4 2 Protecting One Flash Memory Module Systems From Corruption C 20 Flash Memory Access via JTAG and Software C 22 C 5 1 Flash Memory Protection C 22 C 5 2 Program Flash Memory Module via Serial Data Link Using JTAG Feature C 22 C 5 3 Programming a Flash Memory Module via Controller Software C 22 Logd dod gl gd ra er idend TO a O ONO C wc B oa NOOO LL dg ONO CI m 7 3 7 4 7 5 7 6 Figures MSP430 System Configuration
21. 10 9 Output Unit in Continuous Mode for Time Intervals 10 10 Timer Up Down Mode 10 10 Output Unit in Up Down Mode Il 10 11 Timer Up Down Direction 10 11 Up Down Mode Flag Setting 10 12 Altering CCRO Timer in Up Down 10 12 Capture Compare Blocks 10 13 Capture Logic Input Signal 10 14 Capture Signals satis CERO P EC nter teh band be 10 15 Capture Cycle eee Ig datis 10 16 Software Capture Example 10 17 nde ey uen UN IR See ai EE colos 10 19 Output Control Block 10 21 Output Examples Timer in Up 10 23 Output Examples Timer in Continuous Mode 10 23 Output Examples Timer Up Down Mode l 10 24 Timer A Control Register TACTL 10 25 TAR hale
22. 16 36 16 8 4 DTC Transfer Cycle 16 38 16 9 Controlling the Current Consumption of the ADC10 Module 16 39 16 9 1 General Power Saving Features and 16 39 16 9 2 Current Consumption Scenarios 16 41 16 10 A D Grounding and Noise Considerations 16 44 Peripheral File Map 1 WEE TUA mm A 2 A 2 Special Function Register of MSP430x1xx Family Byte A 3 Digital Byte A 3 Digital O Byte Access Continued A 4 A 4 Basic Clock Registers Byte Access A 5 A 5 EPROM Control Register Byte Access A 5 6 Comparator A Registers Byte Access 5 A 7 USARTO USART1 UART Mode Sync 0 Byte A 6 A 8 USARTO USART1 SPI Mode Sync 1 Byte Access A 7 A 9 ADC12 Registers Byte and Word 5 A 8 A 10 ADC10 Registers Byte and Word ACCESS A 11 A 11 Watchdog Timer Word Access
23. B 2 B 2 Instruction Set Description B 8 B 1 Instruction Set Overview B 1 Instruction Set Overview The following list gives an overview of the instruction set Status Bits VNZC ADC W ADC B dst dst C dst S oW ium ADD W ADD B src dst src dst dst A ADDC W ADDC B src dst src dst C dst Ar UC a UR AND W AND B src dst src and dst dst 02 79 57227 BIC W BIC B src dst not src dst dst DAE BIS W BIS B src dst src or dst dst SS ees BIT W BIT B src dst src and dst Qe ce ot BR dst Branch to c CALL dst 2 stack dst PC CLR W CLR B dst Clear destination CLRC Clear carry bit 0 CLRN Clear negative bit 0 CLRZ Clear zero bit 0 CMP W CMP B src dst dst src TO e DADC W DADC B dst dst C dst decimal DADD W DADD B src dst src dst C dst decimal DEC W DEC B dst dst 1 dst amy DECD W DECD B dst dst 2 dst DELE DINT Disable interrupt E c EINT Enable interrupt eere INC W INC B dst Increment destination dst 1 dst ts 7 INCD W INCD B dst Double Increment destination dst 2 gt dst ae Pad INV W INV B dst Invert destination SS ape a JC JHS Label Jump to Label if Carry bit is set Sg oa JEQ JZ Label Jump to Label if Zero bit is set rect JGE Label Jump to La
24. PA Capture CETO 50 CCMx1 0 0 Disabled 0 1 Positive Edge 1 0 Negative Edge 1 1 Both Edges Set_CCIFGx Receive Data Path rE 7 Y SCCIx ce 2 DIC ee ey ee m OUTx Signal ransmit Data Pat T it D Path OMx2 OMx1 OMxO 0 0 1 Set EQUx set OUTx signal clock synchronized with timer clock 1 0 1 Reset EQUx resets OUTx signal clock synchronized with timer clock Ve en TEE CNET WE n C 22 10 34 Timer A UART One capture compare block is used when half duplex communication mode is desired Two capture compare blocks are used for full duplex mode Figure 10 34 illustrates the capture compare timing for the UART Figure 10 34 Timer UART Timing Capture Compare Receive Capture Compare Compare UTXD Signal Transmit Compare Compare A complete application note including connection diagrams and complete soft ware listing may be found at www ti com sc msp430 Timer A 10 35 10 36 Chapter 11 Timer B This section describes the basic functions of the MSP430 genera
25. 15 31 15 8 2 Conversion Memory Registers ADC12MEMXx 15 35 15 8 3 Control Registers ADC12MCTLx 15 35 15 8 4 ADC12 Interrupt Flags ADC12IFG x and Interrupt Enable Registers ADGT2IEINJ ciuem Re 15 37 15 8 5 ADC12 Interrupt Vector Register 121 15 37 15 9 A D Grounding and Noise Considerations 15 41 pg ejm 16 1 16 4 IntrOdlUCtlOn zou ee pem c Glens dd 16 2 16 2 ADC10 Description and Operation 16 4 1622 SADC Core ino imer xiu E MEE 16 4 16 2 2 rai Coe see nte E eub e BON SEE IP EROS te eed aber 16 5 16 3 Analog Inputs and Multiplexer 16 6 16 3 1 Analog Multiplexer 2 1 4 4 16 6 16 3 2 Input Signal Considerations 16 7 16 3 3 Using the Temperature Sensor 16 7 16 4 Conversion Modes 16 8 16 4 1 Single Channel Single Conversion Mode 16 8 16 4 2 Sequence of Channels Mode 16 9 16 4 8 Repeat Single Channel Mode
26. 8 7 Writing to Read Only Register 8 10 Function Select With PnSEL Registers 8 11 Watchdog Timer Changing the Time Interval 9 6 Capture With Timer Halted 22 2 10 16 Changing Timer A Control Bits 10 26 Modifying Timer A Register TAR 10 27 Simultaneous Capture and Capture Mode Selection 10 29 Writing to Read Only Register 10 31 Capture With Timer Halted 11 18 Changing Timer B Control Bits K 32 Modifying Timer B Register TBR K 32 Simultaneous Capture and Capture Mode Selection K 35 Writing to Read Only Register TBIV K 37 URXE Reenabled UART Mode 2 12 11 Writing to UxTXBUF UART Mode 12 12 Write to UXTXBUF Reset of Transmitter UART Mode 12
27. 16 40 ADC10 Current Consumption Without Internal Reference 16 41 ADC10 Current Consumption With Internal Reference On but not Routed ACA T 16 41 ADC10 Current Consumption With Internal Reference On Routed Externally and REFBurst 0 16 42 ADC10 Current Consumption With Internal Reference On Routed Externally and REFBurst 1 16 43 A D Grounding and Noise Considerations 16 44 Double Operand Instructions B 4 Single Operand Instructions B 5 Conditional and Unconditional Jump Instructions B 5 Decrement Overlap B 26 Main Program Interrupt 46 Destination Operand Arithmetic Shift Left 47 Destination Operand Carry Left Shift B 48 Destination Operand Arithmetic Right Shift B 49 Destination Operand Carry Right Shift B 51 Destination Operand Byte Swap B 58 Destination Operand Sign
28. p UENIT TUR ke M es E SEL S 1 ROM RAM TDI 4 TDO TDI i 16 Bit E YN gt CPU _ Test To Other Incl 16 Reg JTAG Peripheral Modules 5 16 Bit TMS TCK ei Flash Flash Test VPP Memory Memory p Optional Module 1 Module 2 Ss ee es ee E Independent modules such as Module1 and Module2 are intended to execute software code from one module while simultaneously programming or erasing another module LR _ Note Flash Memory Module s MSP430 Devices Different devices may have one or more flash memory modules A flash memory module can not be accessed while being programmed or erased Ifthe active software and thetarget programming location are inthe same flash memory module the program execution is halted flag BUSY 1 until the pro gramming cycle is completed flag BUSY 0 Then it proceeds with the next instruction The active software may also erase segments of the flash memory module The user should be careful not to erase memory locations that are necessary to execute the software correctly Figure 2 shows the flash memory Module1 in program or erase operation Durin
29. 7 20 8 Digital I O Configuration 8 1 8 1 INMOQUCIION s rat eee I MEAT eni es 8 2 8 2 Ports PT P2 CER THAN 8 3 8 2 4 Port P1 Port P2 Control Registers 8 4 8 2 2 Port PT Port P2 SchetriatiG iesdoseciecnesdveni llnsrbtunbo Late dss 8 7 8 23 Port P1 P2 Interrupt Control Functions 8 8 9 3 Ports B3 P445 P6 sd inte ee bct e t ci big oue d 8 9 8 3 1 Port P3 P6 Control Registers 8 9 8 3 2 Port PS P6 Schematic 8 11 9 Watchdog Timer 9 1 The Watchdog Timer xe hekessenihi skefteesDbERqsseRIa er pei 9 2 9 1 1 Watchdog Timer Register 9 3 9 1 2 Watchdog Timer Interrupt Control Functions 9 5 9 1 3 Watchdog Timer Operation 9 5 10 Timer A uui Sono Ss 10 1 1051 IntrodU ctlon talk ie 10 2 10 2 Timer A Operation kunenn 10 4 10 2 1 Time
30. Control Register CCTLx 15 0 CCTLx Capture Input 162h to 166h Select SCS SCCI Unused CAP OUTMODx CCIE OUT COV CCIFG rw 0 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw O rw 0 rw 0 rw 0 rw 0 rw 0 rw O rw 0 rw Bit 0 Capture compare interrupt flag CCIFGx Capture mode If set it indicates that a timer value was captured in the CCRx register Compare mode If set it indicates that a timer value was equal to the data in the CCRx register CCIFGO flag CCIFGO is automatically reset when the interrupt request is accepted CCIFG1 to CCIFG4 flags The flag that caused the interrupt is automatically reset after the TAIV word is accessed If the TAIV register is not accessed the flags must be reset with software No interrupt is generated if the corresponding interrupt enable bit is reset but the flag will be set In this scenario the flag must be reset by the software Setting the CCIFGx flag with software will request an interrupt if the interrupt enable bit is set Bit 1 Capture overflow flag COV Compare mode selected CAP 0 Capture signal generation is reset No compare event will set COV bit Capture mode selected CAP 1 The overflow flag COV is set if a second capture is performed before the first capture value is read The overflow flag must be reset with software It is not reset by reading the capture value Bit 2 The OUTx bit determines the value of the OUTx signal if t
31. ER GN BUNT NIB EPI DR MEE ELE 12 6 19 200 Baul rro era ea e tn 12 6 Error Example for 2400 Baud 12 28 Synchronization Error 2400 Baud Calculate the Maximum ADC10 Clock Frequency With the Following System Conditions 16 38 Calculate the Maximum ADC10 Clock Frequency With the Following System Conditions xxi Notes Cautions and Warnings Word Byte Operations 4 8 Status Register Bits V N 4 and C 5 5 Data iniBiegistets s ER E RR Rau xau Reve AURA RR 5 8 Instruction Format Il Immediate Mode 5 16 Destination Address 1 5 17 Instructions CMP and SUB 5 18 LFXT1 Oscillator Fault Signal 7 7 Control of DCOCLK Frequency 7 13 Writing to Read Only Registers P1IN 2 8 4 Port P1 Port P2 Interrupt Sensitivity 8 6 Function Select With PISEL 25
32. ecd e Eg egets ood ERR 10 26 Capture Compare Control Register CCTLX 10 27 Capture Compare Interrupt Flag 10 29 Schematic of Capture Compare Interrupt Vector Word 10 30 10 32 10 33 10 34 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 11 13 11 14 11 15 11 16 11 17 11 18 11 19 11 20 11 21 11 22 11 23 11 24 11 25 11 26 11 27 11 28 11 29 11 30 11 31 11 32 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 12 9 12 10 12 11 12 12 12 13 12 14 12 15 Contents Vector Word Register 10 30 UART Implementation 14 2 2 10 34 Timer A UART Timing 2 2 10 35 Timer Block 1 5 4 11 4 Mode Gontrol s 11 5 Schematic of 16 Bit Timer 11 6 Schematic of Clock Source Select and Input Divider 11 7 Timer erm EE aea Cep A 11 8 Up Mode Flag Setting Ex 11 8 New Period gt Old
33. see Notes 8 and 11 non maskable Eoo OFF 13 Eo P OFF 2 o _ me O UN UR OU DN 5 Port P2 eight flags P2IFG 0 to P2IFG 7 see Note 9 see Notes 8 and 9 Maskable OFFE6h P1IFG 0 to P1IFG 7 Port P1 flags see pm O 8 and 9 Maskable OFFE4h za OFFE2h NOTES 8 Multiple source flags 9 Interrupt flags are located in the module 10 There are eight Port P2 interrupt flags but only six Port P2 I O pins P2 0 5 are implemented on the 11x1 devices 11 Non maskable the individual interrupt enable bit can disable an interrupt event but the general interrupt enable cannot 12 MSP430x12x2 devices only 13 MSP430x12x1 devices only System Resets Interrupts and Operating Modes 3 21 Interrupt Processing Table 3 16 Interrupt Sources Flags and Vectors of MSP430x13x MSP430x14x Configurations INTERRUPT SOURCE INTERRUPT FLAG SYSTEM WORD PRIORITY INTERRUPT ADDRESS Power up WDTIFG Reset OFFFEh 15 highest External Reset KEYV Watchdog see Note 14 Flash memory NMI NMIIFG see Notes 14 and 16 Non maskable Oscillator Fault OFIFG see Notes 14 and 16 Non maskable OFFFCh Flash memory access violation ACCVIFG see Notes 14 and 16 Non maskable Timer B7 usanoreceive uroo 9 ee RB GN
34. 14 7 14 3 8 Comparator Port Disable Register CAPD 14 7 14 4 in Applications 14 9 14 4 1 Analog Signals at Digital 14 9 14 4 2 Comparator Used to Measure Resistive Elements 14 11 14 4 8 Measuring Two Independent Resistive Element Systems 14 13 14 4 4 Comparator Used to Detect a Current or Voltage Level 14 16 14 4 5 Comparator A Used to Measure a Current or Voltage Level 14 17 14 4 6 Measuring the Offset Voltage of _ 14 20 14 4 7 Compensating for the Offset Voltage of Comparator A 14 22 Contents 14 4 8 Adding Hysteresis to Comparator A 14 22 15 DC 12 2 rrt eM eec Lr MEE Mcd e Ee 15 1 15 4 IntrodUctlOD oue e erret rre tre t e et tena 15 2 15 2 ADC12 Description and Operation 15 4 15 2 ADC Cores sigh reser RD E Dc be dep bec tee 15 4 15 2 2 Beterence oro Res e Rib RI Ra Rx eg 15 5 15 3 Analog Inputs and Multiplexer 15 6 15 3 1 Analog Multiplexer 1 4 15 6 15 3 2 Input Signal Considerations
35. 7 17 Port P1 Port P2 Config ratlObi UR EG 8 3 Schematic of One Bit in 1 2 8 7 Ports P3 P6 Configuration 8 9 schematic of Bits esc osetbesrtibeseereevetedgehtesbstcsiRbecPabf elebere2ids 8 11 Schematic of Watchdog Timer 9 2 Watchdog Timer Control Register 9 3 Reading WDTGTL istrenebttegfitenseteugtenteiestesieisiUatel ebrbret fg 9 4 Writing to WDTGTE 25 cor eh erneuern EVER ERNEUT CELA 9 4 Timer A Block 10 3 Mode Control 252 6 coste einer Gin that qi ERES 10 4 Schematic of 16 Bit Timer 10 5 Schematic of Clock Source Select and Input Divider 10 5 Timer UpiMOde scontati Tage esi Reese RS AINE 10 7 Up Mode Flag Setting 10 7 New Period gt Old 10 8 New Period lt Old 10 8 Timer Continuous Mode 10 9 Continuous Mode Flag Setting
36. Introduction 10 1 Introduction 10 2 Timer A is an extremely versatile timer made up of Lj 16 bit counter with 4 operating modes Selectable and configurable clock source Lj Three or five independently configurable capture compare registers with configurable inputs Three or five individually configurable output modules with 8 output modes Timer A can support multiple simultaneous timings multiple capture compares multiple output waveforms such as PWM signals and any combination of these Also each capture compare register has hardware support for implementing serial communications such as UART protocol see section 10 7 Additionally Timer A has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers on captures or compares Each capture compare block is individually configurable and can produce interrupts on compares or on rising falling or both edges of an external capture signal The block diagram of Timer A is shown in Figure 10 1 Figure 10 1 Timer A Block Diagram Introduction r Timer Clock Dat 16 Bit Timer TPSSEL1 TREO ja TACLK 0 00 SMCLK EquO INCLK 9 o ID1 Carry Zero Set TAIFG Timer Bus J EE R E ouod ud 4 Capture Compare
37. 0 5xVcoc L 1o 20 o L20 eo o 025 VCAREF 3 2o E gt OV OV 14 2 The input and output pins of Comparator_A are often multiplexed with other pin functions on the MSP430 Additionally the internal connections to Comparator_Acan differ among MSP430 devices The data sheet of a desired device should always be consulted to determine the specific connection implementations Comparator A Description 14 2 Comparator A Description The comparator A peripheral module is comprised of several major blocks These blocks are described in this section 14 2 1 Input Analog Switches The input analog switches connect or disconnect the comparator input terminals to associated port pins using the P2CAO and P2CA1 control bits Both terminal inputs can be controlled individually 2 and 2 1 allow L Application of an external signal to the and terminals of the comparator or Routing of an internal reference voltage if applied to comparator input terminal as an output on an associated port pin In this way the internal reference voltage can be used to bias external circuitry Internally the input switch is constructed as a T switch to suppress distortion in the signal path When a comparator terminal is not connected to an external pin it should be connected to an internal reference voltage level EU SS waa 2 Note Comparator Input Connection Ensure that the comparator input terminal
38. PEDRO DCOCLK XT1CLK _ gt If Crystal Oscillator settled is am Crystal Oscillator Or 7 16 Features for Low Power Applications 7 4 5 Synchronization of Clock Signals The clock signals MCLK and SMCLK can be supplied by different clock sources While switching from one clock source to the other the switch is synchronized to avoid critical race conditions When another clock source is selected the following occurs in order 1 The current clock cycle continues until the next rising edge 2 Theclockthen remains high until the next rising edge of the newly selected clock 3 Nowthe new clock source is selected and continues with a full high period Figure 7 16 Select Another Clock Source Signal Example Switches From DCOCLK to LFXT1CLK for Clock MCLK Select LFXT1CLK Y DCOCLK LFXTICLK MCLK Wait for gt DCOCL EXT cui LFXT1CLK Basic Clock Module 747 Basic Clock Module Control Registers 7 5 Basic Clock Module Control Registers 7 5 1 The Basic Clock Module is configured using control registers DCOCTL BCSCTL1 and BCSCTL2 and four bits from the CPU status register SCG1 5 0 OscOff and CPUOFF User software can modify these control registers from their default condition at any time The Basic Clock Module control registers are located in the byte wide peripheral map and should be accessed with byte B instructions R
39. 10 ym SHI MSC all 12 bit SAR Conversion CTL v Ret X 0140h ADC12MEMO ADC12MCTLO 080h A 0142h ADC12MEM1 ADC12MCTL1 081h 0144h ADC12MEM2 ADC12MCTL2 082h 0146h ADC12MEM3 ADC12MCTL3 083h 0148h ADC12MEM4 ADC12MCTL4 084h 014Ah ADC12MEM5 ADC12MCTL5 085h 014Ch ADC12MEM6 ADC12MCTL6 086h A 014Eh ADC12MEM7 ADC12MCTL7 087h AVss 0150h ADC12MEM8 ADC12MCTL8 088h 0152h ADC12MEM9 ADC12MCTL9 089h 0154h ADC12MEM10 ADC12MCTL10 08Ah 0156h ADC12MEM11 ADC12MCTL11 08Bh 0158h ADC12MEM12 ADC12MCTL12 08Ch 015Ah ADC12MEM13 ADC12MCTL13 08Dh 015Ch ADC12MEM14 ADC12MCTL14 08Eh 015Eh ADC12MEM15 ADC12MCTL15 08Fh 16 x 12 bit 16 x 8 bit ADC Memory ADC Memory Control 15 2 ADC12SC Timer_A OUT1 Timer_B OUTO Timer_B OUT1 SHS The ADC12 can convert one of eight external analog inputs or one of four internal voltages The four internal channels are used for temperature measurement via on chip temperature diode and for measurement of Vcc via Vcc 2 and the positive and negative references applied on and Vngr Vengr The ADC12 can use its internal reference or it can use external reference s or a combination of internal and external reference voltage levels Introduction The ADC12 has versatile sample and hold circuitry giving the user many options for control of the sample timing The sample timing may be directly controlled by software via a control bit or any one of three internal or external signals depen
40. 16 4 16 3 Analog Inputs and Multiplexer 16 6 16 4 Gonversion Modes 16 8 16 5 Conversion Clock and Conversion Speed 16 17 16 69 Sampling 16 18 16 7 ADC10 Control Registers 16 22 16 8 Data Transfer Control High Speed Conversion Support 16 27 16 9 Controlling the Current Consumption of the ADC10 Module 16 39 16 10 A D Grounding and Noise Considerations 16 44 Introduction 16 1 Introduction The ADC10 10 bit analog to digital converter shown in Figure 16 1 has four main functional blocks that can be individually configured and optimized ADC core with sample and hold Reference voltage and configuration LJ Conversion clock source select and control Lj Sample timing and conversion control Figure 16 1 ADC10 Schematic REF Out REFBurst REFON INCH 0Ah on on Reference AVcc Ref X AVsS 7 lt gt Sref Q ADCiossEL Oscillator O ADC100N ADC10DIV VeRER VREF VREF VeREF 1 5V or 2 5V INCH ADC100SC Wee ADC10CLK Divide by ACLK Analog 1 2 3 4 5 6 7 8 MCLK Multiplexer SMCLK 12 1 10 bit A D Converter Core Convert Msc ISSH O ADC10SC d O TIMER A OUT1 SAMPCON Sampling and Conversion c SYNC AOUTO Control SHI
41. 8 rw 0 SSEL1 rw 0 SP rw 0 N A m wo m 9 29 5 IN 8 o m rw 0 SSEL1 rw 0 SP rw 0 4 23 BRK rw 0 SSELO rw 0 CHAR rw 0 2 N A 29 5 gt N BRK rw 0 SSELO rw 0 CHAR rw 0 i 3 mN 23 URXEIE rw 0 URXSE rw 0 Listen rw 0 2 m 2 gt o URXEIE rw 0 URXSE rw 0 Listen rw 0 GREI l i 2 N N 2 URXWIE rw 0 TXWAKE rw 0 SYNC rw 0 2 7 29 gt 28 URXWIE rw 0 TXWAKE rw 0 SYNC rw 0 N A rw m1 rw RXWake rw 0 Unused rw 0 MM rw 0 21 rw 21 r 29 rw 21 rw m1 rw RXWake rw 0 Unused rw 0 MM rw 0 N RXERR rw 0 E 2 SWRST 2 IN 3 o RXERR rw 0 TXEPT rw 1 SWRST rw 1 USARTO USART1 SPI Mode Sync 1 Byte Access 8 USARTO USART1 SPI Mode Syncz1 Byte Access Bit USART1 Transmit buffer UTXBUF1 07Fh USART1 Receive buffer URXBUF1 07Eh USART1 Baud rate UBR11 07Dh USART1 Baud rate UBRO1 07Ch USART1 Modulation control UMCTL1 07Bh USART1 Receive control URCTL1 07Ah USART1 Transmit control UTCTL1 079h USART1 USART control UCTL1 078h USARTO Transmit buffer UTXBUFO 077h USARTO Receive buffer URXBUFO 076h USARTO Baud rate U
42. TIMOVH Vector 10 TIMOV Flag INC TIMEXT Handle Timer Overflow 4 RETI 5 TIMMOD2 Vector 4 Module 2 ADD NN amp CCR2 Add time difference 5 ES Task starts here RETI Back to main program 5 i TIMMOD1 Vector 2 Module 1 ADD MM amp CCR1 Add time difference 5 ev Task starts here RETI Back to main program 5 If the CPU clock MCLK was turned off CPUOFF 1 then two or three additional cycles need to be added for synchronous start of the CPU The delta of one clock cycle is caused when clocks are asynchronous to the restart of CPU clock MCLK The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself as described Capture compare block CCRO 11 cycles Capture compare blocks CCR1 to CCR4 16 cycles Timer overflow TAIFG 14 cycles With the TAIV register and the previous software the shortest repetitive time distance between two events using a compare register is tcRmin ttaskmax 16 X teycle With ttaskmax Maximum worst case time to perform the task during the interrupt routine for example incrementing a counter Cycle time of the system frequency MCLK The shortest repetitive time distance between two events using a capture register is ttaskmax 16 X tcycle Timer A UART 10 7 Timer A UART The Timer A is uniquely capable
43. eie eire Rer 8 2 8 2 a Ports Pat B2 8 3 8 9 8 3 Ports P3 4 P5 P6 8 1 Introduction 8 1 8 2 Introduction The general purpose ports of the MSP430 are designed to give maximum flexibility Each I O line is individually configurable and most have interrupt capability There are two different types of I O port modules in the MSP430x1 xx family devices Ports P1 and P2 are of one type and ports P3 to P6 are of another type Both types have the capability to control input output direction and output level to read the level applied to a pin and to control if a port or module function is applied to a pin The port module for P1 and P2 have interrupt capability flag enable and edge sensitivity are available individually for each bit MSP430x11xx devices have ports P1 and P2 implemented MSP430x12xx devices have ports P1 to P3 implemented MSP430x13x and MSP430x14x have ports P1 to P6 implemented Ports P1 P2 8 2 Ports P1 P2 Each of the general purpose ports P1 and P2 contain 8 general purpose I O lines and all of the registers required to control and configure them Each I O line is capable of being controlled independently In addition each I O line is capable of producing an interrupt Separate vectors are allocated to ports P1 and P2 modules The pins for port P1 1 0 7 source one interrupt and the pins for port P2 P2 0 7 source another inter
44. 2 2 Bus Connection of Modules Peripherals 2 4 Power On Reset and Power Up Clear Schematic 3 2 Power On Reset Timing on Fast VCC Rise Time 3 3 Power on Reset Timing on Slow VCC Rise Time 3 3 Interrupt Priority 3 6 Block Diagram of NMI Interrupt Sources 3 7 RST NMI Mode Selection 3 8 Interrupt Processing nieri prre BGR Pa Seale HERE 3 10 Return From Interrupt o rrr e ho eh p ctos E GRO wea TR GRO ana ee 3 10 Stat s Register SR 0 nb be DEI VeDCU BO SEE 3 11 MSP430x1xx Operating Modes For Basic Clock System 3 26 Typical Current Consumption of 13x and 14x Devices vs Operating Modes 3 27 Memory of Basic Address Space 4 2 Memory Data BUS eek vx ER RR e RC Re MES 4 2 Bits Bytes and Words a Byte Organized 4 3 ROM Organization sac access peed RU eR Rena x pc ac a C pega ra 4 4 Byte and Word Operation 4 6 Register Byte Byte Register Operations
45. 7 0 An overflow occurs if dst gt 040h and dst lt OCOh before the operation is performed the result has changed sign N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Loaded from the MSB V Setif an arithmetic overflow occurs the initial value is 04000h lt dst lt 0C000h otherwise it is reset Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh otherwise it is reset OscOff CPUOff and GIE are not affected R7 is multiplied by 4 RLA R7 Shift left R7 x 2 emulated by ADD R7 R7 RLA R7 Shift left R7 x 4 emulated by ADD R7 R7 The low byte of R7 is multiplied by 4 RLA B R7 Shift left low byte of R7 x 2 emulated by ADD B R7 R7 RLA B R7 Shift left low byte of R7 x 4 emulated by ADD B R7 R7 Note RLA Substitution The assembler does not recognize the instruction RLA R5 nor RLAB R5 It must be substituted by ADD R5 2 R5 or ADD B R5 1 R5 Instruction Set Description B 47 Instruction Set Overview RLC W RLC B Syntax Operation Emulation Description Rotate left through carry Rotate left through carry RLC dst or RLC W dst RLC B dst MSB lt MSB 1 LSB 1 lt LSB lt C ADDC dst dst The destination operand is shifted left one position as shown in Figure B 7 The carry bit C is shifted into the LSB and the MSB is shifted into the carry bit C
46. 0 0 rw 0 rw 0 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC10SC ENC ADC10IFG ADC10IE ADC10ON REFON bito bit2 bit3 bit4 bit5 ADC10 Control Registers Sample and convert The ADC10SC bit can be used to control the conversion with software if ENC is set It is recommended to have ISSH 0 Setting ISSH 0 or resetting ISSH 1 the ADC10SC bit starts the sample and conversion operation When the A D conversion is complete BUSY 0 the ADC10SC bit is automatically set to the appropriate level for the next conversion All automatic sequence functions CONSEQ 1 2 3 and multiple sample and conversion functions MSC 1 are executed normally Therefore when using ADC10SC the software must ensure that the frequency of the timing of the ADC10SC bit meets the applicable timing requirements NOTE The start of a conversion by software SHS 0 in ADC10CTL1 is possible by setting both ENC and ADC10SC control bits within one instruction Enable conversion The software via ADC10SC or external signals can start a conversion only if the enable conversion bit ENC is set Most of the control bits in ADC10CTLO and ADC10CTL1 may be changed only if ENC is low 0 No conversion can be started This is the initial state 1 The first sample and conversion starts with the first rising edge of the SHI signal The selected operation proceeds as long as ENC is set CONSEQ 0 ADC10BUSY 1 E
47. AOUT2 ADC10SHT ADC10BUSY SHS ADC10DF Ref X o T AVsS The ADC10 can convert one of eight external analog inputs or one of four internal voltages The four internal channels are used to measure temperature via on chip temperature diode Vcc via Vcc 2 and the positive and negative references applied on Vengr and Vngr Vengr The ADC10 can use its internal reference or it can use external reference s or a combination of internal and external reference voltage levels The ADC10 has versatile sample and hold circuitry One sample takes four eight sixteen or sixty four ADC10CLKs and can be triggered by software ADC10SC or by one of the three signals ADC10l1 ADC1012 or 1013 Typically the internal timing signals come from other MSP430 timers such as Timer A 16 2 Introduction As with sample timing users have several choices for the ADC10 conversion clock The ADC10 conversion clock may use ACLK MCLK or SMCLK or may be selected from a dedicated oscillator contained in the ADC10 peripheral Also the chosen clock source may be divided by any factor from 1 to 8 The ADC10 has four operating modes It can be configured to perform a single conversion on a single channel or multiple conversions on a single channel The ADC10 can also be configured to perform conversions on a sequence of channels running through the sequence once or repeatedly The conversion result is stored i
48. BIS 8 SR NOP No operation MOV 0h 0h RET Return from subroutine MOV SP PC 5 3 5 Miscellaneous Instructions without operands such as CPUOff are not provided Their functions are switched on or off by setting or clearing the function bits in the status register or the appropriate I O register Other functions are emulated using dual operand instructions Some examples are as follows BIS 28h SR Enter OscOff mode Enable general interrupt GIE BIS 18h SR Enter CPUOff mode Enable general interrupt GIE 5 22 Instruction 5 4 Instruction The instruction map in Figure 5 10 is an example of how to encode instructions There is room for more instructions if needed See section 5 2 8 for information on number of code words and execution cycles per instruction Figure 5 10 Core Instruction Map 000 040 080 OCO 100 140 180 1CO 200 240 280 2 0 300 340 380 3 0 JNE JNZ JEQ JZ JNC a E o LL JGE JMP MOV MOV B ADD ADD B ADDC ADDC B SUBC SUBC B SUB SUB B CMP CMP B DADD DADD B BIT BIT B BIC BIC B BIS BIS B XOR XOR B AND AND B ooo UONE O PEN O 4 PADD ADB ADDGADDCB O SBE SUBS PSB SUB 2 DADDDADDB Z 94 O PIT BIB 2 BIS BIS 0 0 0 0 O o XORXORB 2 16 Bit CPU 5 03 5 24 Chapter 6 Hardware Multiplier The hardw
49. with ADC12SC reset ADC12SC set ADC12SC reset ADC12SC set ADC12SC reset ENC set start S amp C starts conversion starts sampling starts conversion starts sampling starts conversion SAMPCON TTT1 ria CDSA DAA DA DOA DA DO OA DA DOA vvvv vvvvvv T ER Sample Sample Conversion SR I a uum gt lt Single Conversion Single Conversion Single Conversion Single Conversion Single Conversion Time Time Time Time Time Single Period Single Period gt Single Period Single Period of Sequence of Sequence of Sequence of Sequence Period of Sequences Next Period of Sequences CL gt An active sequence may be stopped immediately by selecting single channel single conversion mode reset CONSEQ 1 bit and then resetting the enable conversion bit The data in memory register ADC12MEMXx is unpredictable and the interrupt flag ADC12IFG x may or may not be set This is generally not recommended but may be used as an emergency exit Each time a conversion is completed the results are loaded into the appropriate ADC12MEMXx register and the corresponding interrupt flag ADC12 Conversion Modes ADC12IFG xis set to indicate completion of the
50. 0 Use12 x ADC10CLK 1 x ADC10CLK Conversion Completed Result to ADC10MEM ADC1OIFG Is Set 16 4 3 Repeat Single Channel Mode The repeat single channel mode is identical to the single channel mode except that conversions are repeated on the chosen channel until stopped by software The conversion result is stored in register ADC10MEM each time a conversion is completed The interrupt flag ADC10IFG is set each time register ADC10MEM is loaded Additionally if the interrupt enable flag ADCAOIE is set an interrupt request is generated The conversion mode may be changed without first stopping the conversions When this is done the new mode takes effect after the current conversion completes see also the Switching Between Conversion Modes section ADC10 Conversion Modes 16 12 There are three ways to stop repeated conversions on a single channel 1 Select single channel mode instead of repeat single channel mode with the CONSEQ bits When this is done the current conversion is completed normally the result is loaded into ADC10MEM and interrupt flag ADC10IFG is set Reset the ENC bit ADC10CTLO 1 to stop conversions after the current conversion is completed Again the result is loaded into ADC10MEM and the associated interrupt flag ADC10IFG is set Select single channel mode instead of repeat single channel mode and then reset the enable conversion bit ENC When this is done the current con
51. 27 0 5 R 0 sense oO _ r o OV Vcc 0 41 P2CA0 gt CAON all cat o E P2CA1 p R meas CARSEL The equation for the current is Figure 14 15 Timing for Measuring a Current Source Vc 0 5 x Voc Ix R 14 18 o Voarer 1 0 5 t t uM 1 2 Voc X 1 e CAF 4 Set lote cv CAIFG t 2yus V Voc 40 1 CAON CAREF i 0 25 x Voc gt Phase I Phase Il Charge Up Charge Up Determine Tau RC Comparator A in Applications Figure 14 16 A D Converter for Voltage Sources CAREF eo 3 7 CARSEL 1o VoAner 5 6 025 o o 2 1 The equation for the voltage V meas is 1 0 5 _ R2 hitia V meas H x Voc X 1 e Figure 14 17 A D Converter for Voltage Sources Conversion Timing Vc gt lt Phase I Phase II Charge Up Charge Up Determine Tau RC Note During phase l control bit 2 1 and CAREF 0 During phase ll control bit 2 0 CARSEL 0 and CAREF 1 Comparator A 14 19 Comparator A in Applications 14 4 6 Measuring the Offset Voltage of Comparator A The input offset voltage of the comparator varies with each device and also with temperature supply voltage and input voltage If the input voltage is stable
52. CM41 40 CCIS41 CCIS40 SCS4 CCLD4 1 CCLD4 0 CAP4 rw 0 w 0 rw 0 rw 0 rw 0 rw 0 0 W 1 rw 0 r r r CM30 CCIS31 CCIS30 SCS3 CCLD3 1 CCLD3 0 CAP3 n rw 0 rw 0 rw 0 rw 0 r n 0 0 0 51 50 CCIS51 CCIS50 SCS5 CLLD5 1 CLLD5 0 CAP5 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 W W W 0 W 21 CM20 CCIS21 CCIS20 SCS2 CCLD2 1 CCLD2 0 CAP2 0 w 0 rw 0 rw 0 rw 0 rw 0 0 W 11 w 0 0 01 00 CCISO1 CCISO00 SCSO CCLDO 1 CCLDO O CAPO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ro rw Timer B control Unused TBCLGRP1 TBCLGRPO TBCNTL1 TBCNTLO Unused TBSSEL1 TBSSELO TBCTL 0180h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw rw t Registers are reserved on devices with Timer B3 n r r r CM10 CCIS11 CCIS10 SCS1 CCLD1 1 CCLD1 0 CAP1 n rw 0 rw 0 rw 0 rw 0 rw 0 r rw 8 8 8 8 8 8 0 0 0 0 0 0 0 0 0 0 0 A 16 Timer B Registers Word Access A 15 Timer B Registers Word Access Continued Bit Cap com register CCR6t 019Eh Cap com register CCR5t 019Ch Cap com register CCR4t 019Ah Cap com register 0198h Cap com register CCR2 0196h Cap com register CCR1 0194h Cap com register CCRO 0192h Timer B register TBR 0190h Cap com control 61 018Eh Cap com control CCTL5f 018Ch Cap com control 41 018Ah Cap com control 31 0188h
53. 4 10 16 BIt CPU IR WE I Cua eee ee 5 1 5al GPURegisters MEER 5 2 5 1 1 The Program Counter 1 5 2 5 1 2 The System Stack Pointer 5 2 5 1 3 The Status Register SR 5 4 5 1 4 The Constant Generator Registers CG1 and CG2 5 5 5 2 Addressing Modes 5 7 5 2 1 Register Modes Gre aena kets CIAM UD DOSE DONE 5 8 5 222 eicere hed Mie eee es peed 5 9 5 2 3 Symbolic Mode ors eene e P EY de dun 5 10 5 2 4 Absolute Mode tebesiebesrvtetesr lop ret es 5 11 5 25 Indirect Mode 5 12 5 2 6 Indirect Autoincrement 5 13 5 2 7 Immediate Mode 5 14 5 2 8 Clock Cycles Length of Instruction 5 15 5 3 Instruction Set Overview 5 17 5 3 1 Double Operand Format 1 Instructions 5 18 5 3 2 Single Operand Format Il Instructions 5 19 5 3 8
54. Figure B 7 Destination Operand Carry Left Shift Status Bits Mode Bits Example Example Example Example B 48 0 sees Byte 7 0 Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the MSB Set if arithmetic overflow occurs reset otherwise Set if OSFFFh lt dstinitiaj lt 0C000h reset otherwise Set if OSFh lt lt reset otherwise OscOff CPUOff and GIE are not affected R5 is shifted left one position RLC R5 R5 x 2 C R5 The input P11N 1 information is shifted into the LSB of R5 BIT B 2 amp 1 Information Carry RLC R5 0 1 LSB of R5 The MEM LEO content is shifted left one position RLC B LEO Mem LEO x 2 C Mem LEO The input P1IN 1 information is to be shifted into the LSB of R5 BIT B 2 amp 1 Information Carry RLC B R5 Carry POin 1 LSB of R5 High byte of R5 is reset Note RLC and RLC B Emulation The assembler does not recognize the instruction RLC QR5 It must be substituted by ADDC R5 2 R5 RRA W RRA B Syntax Operation Description Instruction Set Overview Rotate right arithmetically Rotate right arithmetically RRA dst or RRA W dst RRA B dst MSB MSB MSB MSB 1 LSB 1 LSB 15 gt The destination operand is shifted right one position as shown in Figure B 8 The MSB is shifted in
55. 3 6 3 4 277777272070 3 9 3 5 OperatingiModes 3 23 3 6 Basic Hints for Low Power Applications 3 29 3 1 System Reset Initialization 3 1 System Reset and Initialization 3 1 1 Introduction The MSP430 system reset circuitry shown in Figure 3 1 sources two internal reset signals power on reset POR and power up clear PUC Different events trigger these reset signals and different initial conditions exist depending on which signal was generated Figure 3 1 Power On Reset and Power Up Clear Schematic Spon ae 7 POR Delay Voc POR Detect OV RST MNI POR NMI WDTCTL 5 t gt b e Resetwd1 TMSELT WDTQnt WDTIFGt gt EQut gt Resetwd2 KEYV 1 PUC_DCO PUC from flash module MCLK t From watchdog timer peripheral module 3 2 A POR is a device reset It is only generated by the two following events 1 Powering up the device A low signal on the RST NMI pin when configured in the reset mode A PUC is always generated when a POR is generated but a POR is not generated by a PUC The following events trigger a PUC A POR signal Watchdog timer expiration in watchdog mode only A low signal on the RST NMI pin when configured in the reset mode n Watchdog timer securi
56. Additionally other ADC12 functions are automatically switched on and off as needed if possible to realize additional power savings even while the ADC12 is running Caution Powering Down the Converter Do not power down the converter or the reference generator while the converter is active Conversion results will be false It is possible to disable the reference generator and the ADC12 by resetting bits ADC120N and REFON before an active conversion or sequence of conversions has completed For example if the conversion mode is set to sequence of channels and software resets the ENC bit immediately after the sequence begins the ADC120N and REFON bits can then be reset before the sequence completes If this occurs the ADC12 will be powered down immediately and the conversion results will be false Conversion Clock and Conversion Speed Caution Turning the ADC12 and Voltage Reference On or Off The following must be considered when ADC12 turnon time when the ADC12 is turned on with the ADC120N bit the turnon time noted in the data sheet tApc120N must be observed before a conversion is started Otherwise the results will be false Reference voltage settling Time When the built in reference is turned on with the VREFON bit the settling timing noted in the data sheet must be observed before a conversion is started Otherwise the results will be false until the reference settles Once all internal and external r
57. CCIS11 CCIS10 A 15 OM12 11 10 0 Capture Compare 0 9 TRUE Register CCR1 GND 9 TBCL1 VEG 56 Comparator Latch CCM11 CCM10 Comparator 1 EQU1 EQUO a i E EA a a a a a a a a a a a a D a a a a e a 4 Module 2 Module 3 Module 4 Module 5 a ea a a See 1 i Capture Compare Register CCR6 CCIS61 CCIS60 5 OM62 OM61 OM60 0 CCI6A oo 1 Capture Register CCR6 x D 0 oupuunte TBCL6 Voc 9 Compare Latch CCI6 CCM61 CCM60 EQU6 EQUO E S 2 Timer B Operation 11 2 Timer B Operation The 16 bit timer has four modes of operation selectable with the MCO and MC1 bits in the TBCTL register and four selectable lengths also configured in the TBCTL register The timer increments or decrements depending on mode of operation with each rising edge of the clock signal The timer can be read or written to with software Additionally the timer can generate an interrupt with its ripple carry output when it overflows 11 2 1 Timer Length Timer Bis configurable to operate as a true 8 bit 10 bit 12 bit or 16 bit timer The length of the counter is configured in the TBCTL register Leading bits are read as zero in 8 bit 10 bit and 12 bit mode Data written to the TBR register in 8 bit 10 bit and
58. Figure 15 22 Timer B OUTO v Extended Sample Mode Example Timing ADC12CLK 4 t sample go lconvert t sync EEA a a a 15 7 4 Using the MSC Bit The multiple sample and conversion MSC control bit is not used if the sample signal SAMPCON is generated without the sampling timer However when the sampling timer is used to generate the SAMPCON signal and the operating mode is other than single channel single conversion CONSEQ gt 0 the MSC bit can be used to configure the converter to perform the successive conversions automatically and as quickly as possible If MSC 0 then a rising edge of the SHI signal is required to trigger each sample and conversion regardless of what mode the converter is in When MSC 1 and CONSEQ gt 0 the first rising edge of the SHI signal triggers the first conversion but successive conversions are triggered automatically as soon as the prior conversion is completed Additional rising edges on SHI are ignored until the sequence is completed or until the ENC bit is toggled depending on mode The function of the ENC bit is unchanged when using the bit See Figures 15 23 and 15 24 ADC12 Sampling Figure 15 23 q SAMPCON 210 Use of MSC Bit With Nonrepeated Modes ADC12CLK SHTO SHT1 4 SHP Sampling Timer SHI
59. I RR remm 7 1 7 4 Basic Clock Module 7 2 7 2 LFXT1 and XT2 Oscillators 7 4 7 2 4 EPH Osolllator Se He DEL ope tbe 7 4 12 2 XTZ Oscilator 0 Itt Ee eque e 7 5 7 2 8 Oscillator Fault Detection 7 6 Contents 7 2 4 Select DCO Oscillator for MCLK on XT Oscillator Fault 7 8 7 3 Digitally Controlled Oscillator DCO 7 10 7 31 Operation of the DCO Modulator 7 12 7 4 Basic Clock Module Operating Modes 7 14 7 41 Starting From Power Up Clear 7 14 7 4 2 Adjusting the Basic 7 14 7 4 3 Basic Clock Features for Low Power Applications 7 15 7 4 4 Selecting a Crystal Clock for 7 15 7 4 5 Synchronization of Clock Signals 7 17 7 5 Basic Clock Module Control Registers 7 18 7 5 1 Digitally Controlled Oscillator DCO Clock Frequency Control 7 18 7 5 2 Oscillator and Clock Control Register 7 18 7 5 8 Special Function Register Bits
60. Ne Ne Ne Ne Ne XOR 5 0 amp CCTLx 11 4 2 Capture Compare Block Compare Mode The compare mode is selected if the CAPx bit located in control word CCTLx is reset In compare mode all the capture hardware circuitry is inactive and the capture mode overflow logic is inactive The compare mode is most often used to generate interrupts at specific time intervals or used in conjunction with the output unit to generate output signals such as PWM signals The compare data is double buffered The software writes the compare data to the capture compare register but the data is transferred to the compare latch TBCLx to be compared by the compare logic The transfer of the compare data from the CCRx register to the compare latch is user selectable to be either immediate or dependent upon a timer event This double buffering allows the user to update multiple compare values simultaneously This is useful for example with PWM signals where the period or duty cycle of multiple signals needs to be updated simultaneously See section 11 4 2 1 for more discussion on how to use and configure the compare latches If the timer becomes equal to the value in compare latch TBCLx then Timer B 11 19 Timer Modes Interrupt flag CCIFGx located in control word CCTLx is set An interrupt is requested if interrupt enable bits CCIEx and GIE are set Signal EQUx is output to the output unit This signal affects the output OUT
61. SHT1 2t SHT1 1T sHT1 0f 5 SHTo 2t SHTO 1T sHTO of 01A0h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 t Only modifiable when ENC 0 Bit 7 6 5 4 3 2 1 0 ADC12IE ADCI2IE 7 ADC121E 6 ADC121E 5 ADC121E 4 ADC121E 3 ADC121E 2 ADC121E 1 ADC12IE 0 01A6h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IFG ADC12IFG 7 ADC12IFG 6 ADC12IFG 5 ADC12IFG 4 ADC12IFG 3 ADC12IFG 2 ADCi2IFG 1 ADC12IFG 0 01A4h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12CTL1 ADC1i2DIV2t ADCi2DIV 1f ADCi2DIVOf ADC12SSEL 1t ADC12SSEL oT CONSEQ 1 CONSEQ 0 ADC12BUSY 01A2h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 ADC12CTLO msct 2 5vt REFONT ADC120Nf ADC120VIE ADC12TOVIE ENC ADC12SC 01A0h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Only modifiable when ENC 0 A 10 ADC10 Registers Byte and Word Access A 10 ADC10 Registers Byte and Word Access Bit 4 15 14 13 12 11 10 9 8 ADC10CTL1 ADC10INCH 3t ADC10INCH 2t ADC10INCH 1t ADC10INCH ot ADC10SHS 1t ADC10SHS of ADC10DFT ADC10ISSHT 01B2h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC10CTLO ADC10Sref 2t ADC10Sref 1t ADC10Sref ot ADC10SHT 1t ADC10SHT OT ADC10SRt REF Outt REFBurstt 01 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 t Only modifiable when ENC 0 Bit 4 ADC10CTL1 ADC1OSSEL OT ADC10CON ADC10CON ADC10BUSY 01B2h rw 0 2 pa
62. When software is using the ADC10SC bit to initiate conversion successive conversions can be initiated by simply setting the ADC10SC bit the bit must already be set or can be set together with ADC10SC For the hardware trigger sources the bit must be toggled between each conversion All additional incoming sample input signals will be ignored until the ENC bit is reset and set again The conversion mode may be changed after the conversion begins but before ithas completed and the new mode will take effect after the current conversion has completed See also the Switching between Conversion Modes section Figure 16 4 illustrates the single channel single conversion mode Conversion Modes Figure 16 4 Single Channel Single Conversion Mode x INCH Wait for Enable SAMPCON 4 Eo SAMPCON 1 f Sample Input Channel ENC ot N SAMPCON Y N N 12 x ADC10CLK N S Convert Use 12 x ADC10CLK ENC ot 1 x ADC10CLK Conversion Ne Completed Result to ADC10MEM ADCAOIFG Is Set T Conversion result is unpredictable 16 4 2 Sequence of Channels Mode The sequence of channels mode converts a sequence of channels beginning with A INCH down to The sequence stops after the conversion result of is loaded into ADC10MEM Each conversion result is stored in register ADC10MEM each time a conversion is completed The interrupt flag ADC10IFG
63. and Vp VREF a0 using reference voltages Vg and Vp AVss a0 using reference voltages AVcc and Vp AVss using reference voltages AVcc and Vp Vengr VREF Figure 15 9 Sequence of Channels Mode Flow Define basic conversion conditions via control registers ADC12CTLO 1 x 6 CStartAdd 6 Define reference and channel in control registers ADC12MCTL6x ADC12MCTL6 ADC12MCTL7 015h ADC12MCTL8 057h ADC12MCTL9 Oh ADC12MCTL10 Oh ADC12MCTL11 0C3h P pmen lt Sample Conversion Sample and convert channel using ADC12MCTLx and store conversion result in ADC12MEMx EOS in ADC12MCTLx 1 Yes Stop conversion sequence ADC12 TE Conversion Modes Figure 15 10 Sequence of Channels Mode Example 0140h 0142h 0144h 0146h 0148h 014Ah gt Q14Ch gt 014Eh _ gt 0150h gt 0152h gt 0154h Sequence 140h 2 x CStartAdd E select Vng Vn Multiplexer ADC12MEMO ADC12MCTLO 080h ADC12MEM1 ADC12MCTL1 081h ADC12MEM2 ADC12MCTL2 082h ADC12MEM3 ADC12MCTL3 083h ADC12MEM4 ADC12MCTL4 084h ADC12MEMS5 ADC12MCTLS 085h 0 rr Conversion result 1 0 Conversion reswa a ADC12MEM12 ADC12MCTL12 08Ch A
64. 0 64 Were He rt ppp TEES Er TES 0 0 1 UCLK 1 1 1 1 1 uck Lee SIMO x 0 SOMI SIMO x 1 SOMI Bac Ie seio v TXBUF gui Receive Sample Points Previous Data Bit When operating with the CKPH bit set the USART synchronous mode makes the first bit of data available after the transmit shift register is loaded and before the first edge of the In this mode data is latched on the first edge of UCLK and transmitted on the second edge 13 5 3 Receive Control Register UURCTL UTRCTL The receive control register shown in Figure 13 18 controls the USART hardware associated with the receiver operation and holds error conditions Figure 13 18 Receive Control Register UORCTL U1RCTL 18 18 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 7 0 sese Te T U1RCTL 07Ah rw O0 rw 0 rw 0 rw 0 rw 0 rw 0 rw O0 rw 0 Undefined driven by USART hardware Undefined driven by USART hardware Unused Unused Undefined driven by USART hardware The overrun error flag bit OE is set when a character is transferred to UXRXBUF before the previous character is read The previous character is overwritten and lost OE is reset by a SWRST a system reset by reading the UxRXBUF or by an instruction Undefined driven by USART hardware Frame error The FE bit is set when fou
65. 7 ADC12MCTLx EOS 080h 08Fh rw 0 INCH bits 0 3 Sref bits4 6 EOS bit7 15 36 1 Sref source of reference INCH input channel a0 to a11 1 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 The INCH input channel bits select one of eight external or one of four internal analog signals for conversion 0 7 a0toa7 8 VeREF 9 VnEr VenEr 10 Temperature diode 11 15 AVgs 2 Note Selecting channel 10 automatically turns on the on chip reference generator for a voltage source for the temperature diode However it does not enable the output or effect the reference selections for the conversion The Sref bits select one of six reference voltage combinations used for conversion The conversion is done between the selected voltage range Vp and Vg 0 Vn AVcc and Vn AVss 1 Vn VREF and VR AVss 2 3 Vn VeREF and VR AVss 4 VR and Vp Vngr Vengr 5 VR VREF and Vp Vngr Vengr 6 7 VR Verner and Vp Vngr Vengr The end of sequence bit when set indicates the last conversion in a sequence of conversions Note A sequence will roll over from ADC12MEM15 ADC12MCTL15 to ADC12MEMO ADC12MCTLO if the EOS bit in ADC12MCTL 15 is not set Note If none of the EOS bits is set and sequence of channels CONSEQ 1 3 is selected resetting the ENC bit will not stop the sequence To stop the sequence first select a single cha
66. Figure 3 5 Block Diagram of NMI Interrupt Sources ACCV ACCVIFG FCTL1 1 ACCVIE IE1 5 Clear PUC RST NMI Flash Module Flash Module Flash Module lt NMIIE IE1 4 Clear PUC OSCFault OFIFG E IFG1 1 OFIE IE1 1 Clear NMI IRQA PUC IRQA Interrupt Request Accepted PUC System Reset Generator POR p NMIRS IES TMSEL NMI WDTQn EQU POR WDTIFG S IRQ IFG1 0 Clear WDT Counter POR IRQA TMSEL WDTIE IE1 0 Clear PUC Watchdog Timer Module System Resets Interrupts and Operating Modes 3 7 MSP430 Interrupt Priority Scheme Figure 3 6 RST NMI Mode Selection 3 3 1 3 8 WDTCTL 0120h 7 0 HOLD NMIES NMI TMSEL CNTCL SSEL rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 rw 0 BITS 0 4 7 Watchdog Timer chapter BIT 5 BIT 6 The NMI bit selects the function of the RST NMI input pin It is cleared after a PUC signal NMI 0 The RST NMI input works as reset input As long as the RST NMI pin is held low the internal PUC signal is active level sensitive NMI 1 The RST NMI input works as an edge sensitive nonmaskable interrupt input This bit selects the activating edge of the RST NMI input if the NMI function is selected It is cleared after a PUC signal NMIES 0 rising edge triggers an NMI interrupt NMIES 1 A falling edge
67. MSC 0 MSC 1 MSC 0 MSC 1 MSC 0 MSC 1 Sampling 15 7 5 Sample Timing Considerations The A D converter uses the charge redistribution method Thus when the inputs are internally switched to sample the input analog signal the switching action causes displacement currents to flow into and out of the analog inputs These current spikes or transients occur atthe leading and falling edges of the sample pulse and usually decay and settle before causing any problems because typically the external time constant is less than that presented by the internal effective RC Internally the analog inputs see an effective maximum nominal RC of a 30 pF C array capacitor in series with a 2 kO resistor Ron of switches However if the external dynamic source impedance is large then these transients may not settle within the allocated sampling time to ensure 12 bits of accuracy It is imperative that the proper sample timing be used for accurate conversions The next section discusses how to calculate the sample timing 15 7 5 1 Simplified Sample Timing Analysis Using the equivalent circuit shown in Figure 15 25 the time required to charge the analog input capacitance from 0 to VS within 1 2 LSB can be derived as follows Figure 15 25 Equivalent Circuit Vs VI MSP430 Input voltage at pin Ax fi Vs External driving source voltage Rg Source resistance must be real at input frequency ri Inpu
68. SREF 1 5 BGon Bandgap To Temp Sensor Ve REF 4 P2 4 TA2 A4 VREF VREF Vngr Ve REFS AVSS P2 3 TA1 AS VREF Buffer ADC10CTLO 13 15 SREF Bits V Controlling the Current Consumption of the ADC10 Module 16 9 2 Current Consumption Scenarios Four different current consumption scenarios for the ADC10 are discussed below The internal reference is not used The internal reference is used internally Sref 1 5 but not routed exter nally REF Out 0 Theinternalreference is routed externally to pin Vpgp andis continuously present REF OUT 1 REFBurst 0 O The internal reference is routed externally to pin VaEgr but is only present externally during the sample and conversion period burst mode REF Out REFBurst 1 The reference can be divided into three blocks which are active depending on the control bit settings The current consumed by the reference and the temperature sensor when on is named and the current taken by the reference buffer is The current used by the ADC core is If REFON O Vngr is always switched off However the temperature sensor is supplied with the reference during the sample and conversion period even if REFON 0 16 9 2 1 Internal Reference Not Used The reference voltage Vref is switched off and the internal signal REF X is on during the sample and conversion per
69. The URXD signal feeds into the USART module by first going into a deglitch circuit Glitches cannot trigger the receive start condition flag URXS which prevents the module from being started from small glitches on the URXD line Because glitches do not start the system or the USART module current consumption is reduced in noisy environments Figure 12 24 shows the accepted receive start timing condition Figure 12 24 Receive Start Timing Using URXS Flag Start Bit Accepted Majority Vote RC S URXS fo ERROR a eee URXS is Reset in the Interrupt Handler Using Control Bit URXSE The UART stops receiving a character when the URXD signal exceeds the deglitch time t but the majority vote on the signal fails to detect a start bit as shown in Figure 12 25 The software should handle this condition and return the system to the appropriate low power mode The interrupt flag URXIFG is not set Figure 12 25 Receive Start Timing Using URXS Flag Start Bit Not Accepted Majority Vote URXD T URXS 7 Fears Mf URXS is Reset in The Interrupt Handler Using Control Bit URXSE Glitches atthe URXD line are suppressed automatically and no further activity occurs in the MSP430 as shown in Figure 12 26 The data for the deglitch time t is noted in the corresponding device specification Figure 12 26 Receive Start Timing Using URXS Flag Glitch Suppression Majority Vote UR
70. The pin logic of each individual port P1 and port P2 signal is identical Each bit can be read and written to as shown in Figure 8 2 Figure 8 2 Schematic of One Bit in Port P1 P2 PnSEL x e PnDIR x Output Direction Control gt MUX From Module od PnOUT x Pad Logic bacs e gt Module X OUT J o PnIN x 4 e EN Module x IN Y 4 PnIRQ x Interrupt PnIFG x Flag Select PMG PnIES x Request PnSEL x Interrupt Pn 07 PnIRQ z X 0 to 7 according to bits O to 7 n 1 for Port P1 and 2 for Port P2 Digital I O Configuration 8 7 Ports P1 P2 8 2 3 Port P1 P2 Interrupt Control Functions 8 8 Ports P1 and P2 use eight bits for interrupt flags eight bits to enable interrupts eight bits to select the effective edge of an interrupt event one interrupt vector address for port P1 and one interrupt vector address for port P2 Each signal uses three bits for configuration and interrupt Interrupt flag P1IFG 0 to P1IFG 7 and P2IFG 0 to P2IFG 7 Interrupt enable bit P1IE 0 to P1IE 7 and P2IE 0O to P2IE 7 Interrupt edge select bit P1IES 0 to P1IES 7 and 21 5 0 to P2IES 7 The interrupt flags P1IFG 0 to P1IFG 7 source one interrupt and P2IFG 0 to P2IFG 7 source one interrupt Any interrupt event on one or more pins of P1 0 to P1 7 or P2
71. tdead ttimer X TBCL1 TBCL3 With tgeag Time during which both outputs need to be inactive ttimer Cycle time of the timer clock TBCLx Content of compare latch x oO The dead time is ensured by the ability to simultaneously load the compare latches Unit in Up Down Mode 11 TBR may TBCLO TBCL1 TBCL3 Oh b 4 b Dead Time Output Mode 6 PWM Toggle Set Output Mode 2 PWM Toggle Reset TBIFG EQU1 EQU1 TBIFG EQU1 Interrupt Events 11 12 EQU3 EQUO EQU3 EQU3 EQUO EQUS Timer Modes The count direction is always latched with a flip flop Figure 11 14 This is useful because it allows the user to stop the timer and then restart it in the same direction it was counting before it was stopped For example if the timer was counting down when the MCx bits were reset then it will continue counting in the down direction if it is restarted in up down mode If this is not desired the CLR bit in the TBCTL register must be used to clear the direction Note that the CLR bit affects other setup conditions of the timer Refer to Section 11 6 for a discussion of the Timer_B registers Figure 11 14 Timer Up Down Direction Control POR CLR in TBCTL Up Down For Timer TBR Low Down Direction High Up Direction Up Down Mode TBR gt TBCLO Timer Clock Inu
72. 14 10 Temperature Measurement Systems 14 11 Timing for Temperature Measurement Systems 14 12 Two Independent Temperature Measurement Systems 14 13 Temperature Measurement Via Temperature Sensor R1 meas 14 14 Temperature Measurement Via Temperature Sensor R2 meas 14 15 Detect a Voltage Level Using an External Reference Level 14 16 Detect a Current Level Using an Internal Reference Level 14 17 Measuring a Current 14 18 14 15 14 16 14 17 14 18 14 19 14 20 14 21 14 22 15 1 15 2 15 3 15 4 15 5 15 6 15 7 15 8 15 9 15 10 15 11 15 12 15 13 15 14 15 15 15 16 15 17 15 18 15 19 15 20 15 21 15 22 15 23 15 24 15 25 15 26 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 10 16 11 16 12 16 13 16 14 16 15 Contents Timing for Measuring a Current Source 14 18 A D Converter for Voltage Sources 14 19 A D Converter for Voltage Sources Conversion Timing 14 19 Measuring the Offset Voltage of the Comparator CAEX 20 14 20 Offset Voltage of the Comparator CAEX 0 14 20 Measuring
73. 62 Appendix Flash Memory This chapter describes the MSP430 flash memory module The flash memory module is electrically erasable and programmable Devices with a flash memory module are multiple time programmable devices MTP They can be erased and programmed off board or in a system via the MSP430 s JTAG pe ripheral module a bootstrap loader or via the processor s resources Software running on an MSP430 device can erase and program the flash memory module This active software may run in RAM in ROM or in the flash memory The flash memory may be a different memory module or the same memory module Topic Page C 1 Flash Memory Organization C 2 C 2 Flash Memory Data Structure and Operation 5 Flash Memory Control Registers C 13 C 4 Flash Memory Interrupt and Security Key Violation C 18 C 5 Flash Memory Access via JTAG and Software 22 1 Flash Memory Organization C 1 Flash Memory Organization The flash memory may have one or more modules of different sizes as shown in Figure 1 A module is a physical memory unit that operates independent from other modules In an MSP430 configuration with more than one flash memory module all modules are located in one linear address range Figure 1 Interconnection of Flash Memory Module s
74. A 2 Special Function Register of MSP430x1xx Family Byte Access URXE1 UTXE1 rw 0 URXEO usPiEo 0004h rw 0 Interrupt nae UTXIFG1 URXIFG1 UTXIFGOT URXIFGOt 0003h rw 1 rw 0 rw 1 rw 0 Interrupt flag 1 uTxiFGot URXIFGOt NMIIFG orira WDTIFG 0002h rw 1 rw 0 rw 0 rw 1 rw 0 Interrupt ae UTXIE1 URXIE1 UTXIEot URXIEO 0001h rw 0 rw 0 rw 0 rw 0 UTrxiEot uRxiEot ACCVIE NMIIE OFIE WDTIE oon ais ve E Lid iki T 12xx devices only 13 and 14x devices only Module enable 2 ME2 0005h Module enable 1 ME1 Note SFR bits are not implemented on devices without the corresponding peripheral Digital 1 0 Byte Access Bit 7 6 5 4 3 2 1 0 Function select PASEL P4SEL 7 PASEL 6 P4SEL 5 PASEL 4 P4SEL 3 PASEL 2 PASEL 1 PASEL O 001Fh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Direction register PADIR P4DIR 7 P4DIR 6 P4DIR 5 P4DIR 4 P4DIR 3 P4DIR 2 P4DIR 1 0 001Eh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Output register PAOUT PAOUT 7 PAOUT 6 PAOUT 5 4 PAOUT 3 PAOUT 2 PAOUT 1 PAOUT O 001Dh rw rw rw rw rw rw rw rw Input register PAIN P4IN 7 6 PAIN 5 P4IN 4 PAIN 3 P4IN 2 P4IN 1 PAIN O 001Ch r r r r r r r r Function select PSSEL P3SEL 7 PSSEL 6 PSSEL 5 PSSEL 4 PSSEL 3 P8SEL 2 P3SEL 1 P3SEL O 001Bh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Direction register PS
75. ADC10CLK Start Stop Sampling Stop Sampling Start Conversion Conversion Conversion Loaded to ADC10MEM lSample gt t i 4 8 16 or 64 x ADC10CLK Conversion and Hold TALL Figure 16 10 Sample and Conversion Basic Signal Timing SMCLK Selected for ADC10CLK Start Stop Sampling Stop Sampling Start Conversion Conversion Conversion Loaded m to ADC10MEM sR l Sample 71 gt t Conversion and Hold 4 8 16 or 64 x ADC10CLK ALLL LLL a From SMCLK AHLU LU LULULL Sample t Sample Starts With The First Leading Edge of ADC10CLK 16 18 Sampling The analog input signal must be valid and steady during the sampling period in order to obtain an accurate conversion It is also desirable not to have any digital activity on any adjacent channels during the whole conversion period to ensure that errors due to supply glitching ground bounce or crosstalk do not corrupt the conversion results In addition gains and losses in internal charge limit the hold time The user should ensure that the data sheet limits are not violated Otherwise the sampled analog voltage may increase or decrease resulting in false conversion values 16 6 2 Sample Signal Input Selection The leading edge of the sample signal input SHI triggers the sample 4 8 16 or 64 x ADC10CLK and conversion cycle 13 x ADC10CLK The sample signal input SHl is s
76. DCOR 3 Select DCO including Internal Resistor XT Oscillator Fails XT2 Is an internal signal XT2 0 Two oscillators MSP430x11xx and MSP430x12xx devices XT2 1 Three oscillators MSP430F13x and MSP430F14x devices IRQA Interrupt request accepted LFT XT OscFault Only applicable to LFXT1 oscillator in HF mode 7 6 The XT2 OscFault signal of the XT2 oscillator and the LFXT1 OscFault signal of the LFXT1 oscillator will set the oscillator fault interrupt flag OFIFG independently For two oscillator implementation the oscillator fault interrupt flag can be reset by software if the LFXT1_OscFault signal is a logic low For three oscillator implementation the oscillator fault interrupt flag can be reset by software only if both oscillator fault signals LFXT1 OscFault and XT2 OscFault are low LFXT1 and XT2 Oscillators Note LFXT1 Oscillator Fault Signal The LFXT1 OscFault signal is only applicable when the LFXT1 oscillator is used in HF mode There is no oscillator fault detection for the LFXT1 oscillator when it is configured in LF mode After applying Vcc the oscillator fault signal XT OscFault becomes active The XT OscFault signal becomes inactive when XT2CLK and or LFXT1CLK have been oscillating for approximately 50 us Figure 7 6 Oscillator Fault Signal XT2CL
77. POR A A i PUC 7 NMIIE WDTIFG meg E NI z m gt z isi o 2 IE1 4 IRQ Counter EN emat L oL IE1 0 Clear IE1 4 Clear A e Watchdog Timer Module PUC NMI pull ell celle EE IRQA Interrupt Request Accepted Flash Memory C 19 Flash Memory Interrupt and Security Key Violation C 4 1 Example of an NMI Interrupt Handler Start of NMI Interrupt Handler Reset by HW OFIE NMIE NMIIFG Reset OFIFG Reset NMIIFG User s Software User s Software User s Software Oscillator Fault Flash Access External NMI Handler Violation Handler Handler Optional Set NMIIE OFIE Example 1 ACCVIE Within One BIS NMIIE OFIE ACCVIE amp IE1 Instruction 71 Example 2 BIS Mask amp IE1 Mask enables only interrupt sources RETI End of NMI Interrupt Handler The NMI handlertakes care of all sources requesting a nonmaskable interrupt The NMI interrupt is a multiple source interrupt per MSP430 definition The hardware resets the interrupt enable flags the external nonmaskable interrupt enable NMIIE the oscillator fault interrupt enable OFIE and the flash memory access violation interrupt enable The individual software handlers reset the interrupt flags and reenables the interrupt enable
78. Reserved Reserved EMEX Lock WAIT ACCVIFG KEYV Busy 012Ch ro ro rw 0 rw 1 1 rw 0 rw 0 r w 0 FCTL2 SSEL1 SSELO FN5 FN4 FN3 FN2 FN1 FNO 012Ah rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 FCTL1 SEGWRT WRT Reserved Reserved Reserved MEras Erase Reserved 0128H rw 0 rw 0 ro ro ro rw 0 rw 0 ro A 12 Hardware Multiplier Word Access A 13 Hardware Multiplier Word Access Bit 1 9 8 Sum extend SumExt O13Eh r Result high word ResHI 013Ch Result low word ResLO 013Ah Second operand OP2 0138h MPYS ACC MACS 0136h MPY ACC MAC 0134h Multiply signed MPYS 0132h Multiply unsigned MPY 0130h Bit 6 5 3 0 Sum extend SumExt 013Eh Result high word ResHI 013Ch Result low word ResLO 013Ah Second operand OP2 0138h 5 MACS 0136h MPY ACC 0134h Multiply signed MPYS 0132h Multiply unsigned MPY 0130h T The Sum Extend register SumExt holds a 16x16 bit multiplication MPYS sign result or the overflow of the multiply and accu mulate MAC operation or the sign of the signed multiply and accumulate MACS operation Overflow and underflow of the MACS operation must be handled by software Peripheral File Map 13 Timer A Registers Word Access A 14 Timer A Registers Word Access Bit 017Eh 017Ch Cap com register CCRAT 017Ah Cap com register CCR3T 0178h Cap com register CCR2 0176h Cap com register CCR1 0174h Cap com register CCRO 0172h Timer A regis
79. TBR MAX Timer TBCLO XXX Timer Clock Figure 11 32 Vector Word Register 15 0 o o 0 0 r 0 rO r0 rO r0 ro ro r0 rO 0 roO rO r r TBIV 11Eh The flag with the highest priority generates a number from 2 to 14 in the TBIV register as shown in Table 11 9 If the value of the TBIV register is 0 no interrupt is pending This number can be added to the program counter to automatically enter the appropriate software routine without the need for reading and evaluating the interrupt vector The software example in section 11 6 4 3 shows this technique 11 36 Timer B Registers Table 11 10 Vector Register TBIV Description Interrupt Vector Register Priority Interrupt Source Short Form TBIV Contents Highestt Capture compare 1 CCIFG1 2 Capture compare 2 CCIFG2 4 Capture compare 3t CCIFG3 6 Capture compare 4t CCIFG4 8 Capture compare 5 CCIFG5 10 Capture compare 6t CCIFG6 12 Lowest Timer overflow TBIFG 14 No interrupt pending 0 T Highest pending interrupt other than CCIFGO CCIFGO is always the highest priority Timer B interrupt t 14x devices only Accessing the TBIV register automatically resets the highest pending interrupt flag If another interrupt flag is set then another interrupt will be immediately generated after servicing the initial interrupt For example if both CCIFG2 and CCIFG3 set when the interrupt service routine accesses the TBIV
80. Y lt 12 x ADC12CLK N qute Convert use 12 x ADC12CLK ENC ot 1 x ADC12CLK ET Conversion N Completed gt Result Stored Into ADC12MEMXx ADC12IFG x is Set TConversion result is unpredictable Conversion Modes An example of the conversion memory setup is shown in Figure 15 6 for single channel conversion The example uses the following conditions Single conversion of channel a4 ADC12MEM 1 L Internal reference voltage with Vp at AVcc and with Vp at Conversion result to be stored conversion memory register This means that control bit CStartAdd in ADC12CTLO is assigned a value of 1 The channel INCH 4 and reference voltages Sref 0 are selected via ADC12MCTL1 ADC12 Conversion Modes Figure 15 6 Example Conversion Memory Setup 140h 2 x CStartAdd I 5 Select VR VR Multiplexer 0140h ADC12MEMO ADC12MCTLO O80h gt orn O comprsion 1 0 0 0 0 1 0 0 o icone ADC12MEM2 ADC12MCTL2 16 x 12 bit 16 x 8 bit ADC Memory ADC Memory Controls 015Ch ADC12MEM14 ADC12MCTL14 O8Eh 015Eh ADC12MEM15 ADC12MCTL15 O8Fh 15 5 2 Sequence of Channels Mode 15 12 The sequence of channels mode converts a sequence of channels The CStartAdd bits in ADC12CTL1 point to the first conversion memory register used for the sequence The results of the remaining conversions in the sequence are stored in sequential convers
81. amp CCTL2 Software capture CCISO 0 Capture mode 3 11 6 4 Timer B Interrupt Vector Register Two interrupt vectors are associated with the 16 bit Timer B module CCRO interrupt vector highest priority TBIV interrupt vector for flags CCIFG1 CCIFGx and TBIFG 11 6 4 1 0 Interrupt Vector The interrupt flag associated with capture compare register CCRO as shown in Figure 11 30 is set if the timer value is equal to the compare register value Figure 11 30 Capture Compare Interrupt Flag Capture EQO IRQ Interrupt Service Requested TBCLO Timer CAP Timer Clock IRACC Interrupt Request Accepted Capture compare register 0 has the highest Timer B interrupt priority and uses its own interrupt vector Timer B 11 35 Timer B Registers 11 6 4 2 Vector Word TBIFG CCIFG1 to CCIFGx Flags The CCIFGx other than CCIFGO and TBIFG interrupt flags are prioritized and combined to source a single interrupt as shown in Figure 11 31 The interrupt vector register TBIV shown in Figure 11 32 is used to determine which flag requested an interrupt Figure 11 31 Schematic of Capture Compare Interrupt Vector Word cc CCIFG1 EQ1 CMP1 Timer Clock CCI2 EQ2 CMP2 Timer Clock Interrupt Service Request Module 3 Priority and Module 4 Vector Word Generator Module 5 Interrupt Vector Address CCIFG6 CCI6 EQ6 CMP6 Timer Clock
82. 0 rw 0 rO Note To start the DTC transfer the ADC10SA register must be written to even if the current contents of the ADC10SA register is the desired starting address Otherwise the DTC will not start Also any write to the ADC10SA register resets the DTC state machine See also the state diagrams shown in Figures 16 17 and 16 19 DTC Transfer While ADC10 Is Busy A DTC transfer must not be initiated while the ADC10 is busy When using single channel single conversion mode or sequence of channels mode software must ensure that no active conversion or sequence is in progress when the ADC10SA register is written to When using one of the repeated modes software must stop the ADC10 before writing to the ADC10SA register See applicable section for instructions on stopping the ADC10 16 8 3 Software Examples for Using DTC The following two examples show the one block transfer and the two block transfer 16 36 Data Transfer Control High Speed Conversion Support 16 8 3 1 One Block Transfer Software Example Initialize 10 DTC for one block transfer 8 conversion results are transferred to address range Beginning with address 0220h Setup CLR B amp ADCIODTCO OV B 08 10 OV W 0220h amp ADC10SA EINT PER RAAB ARE KB RIK CUR BRE KAR RAR KER LRG RRR oco esse ok Seno BARI Ko Mainloop Mainloop code would go here including 10 setu
83. 0 0 OscOff 0 0 CPU clocks are active Low power mode 0 LPMO SCG1 0 SCGO 0 OscOff 0 CPUOff 1 CPU is disabled MCLK is disabled SMCLK and ACLK remain active Low power mode 1 LPM1 SCG1 0 SCGO 1 OscOff 0 CPUOff 1 CPU is disabled MCLK is disabled DCO s dc generator is disabled if the DCO is not used for MCLK or SMCLK when in active mode Otherwise it remains enabled SMCLK and ACLK remain active 3 24 Operating Modes Low power mode 2 LPM2 SCG1 1 5 0 0 OscOff 0 CPUOff 1 CPU is disabled MCLK is disabled SMCLK is disabled DCO oscillator automatically disabled because it is not needed for MCLK or SMCLK DCO s dc generator remains enabled ACLK remains active Low power mode LPM3 SCG1 1 SCGO 1 OscOff 0 CPUOff 1 CPU is disabled MCLK is disabled SMCLK is disabled DCO oscillator is disabled DCO s dc generator is disabled ACLK remains active Low power mode 4 LPM4 SCG1 X SCGOzX OscOff 1 CPUOff 1 CPU is disabled ACLK is disabled MCLK is disabled SMCLK is disabled DCO oscillator is disabled DCO s dc generator is disabled Crystal oscillator is stopped o Note Peripheral operation is not halted by CPUOff Peripherals are controlled by their individual control registers System Resets Interrupts and Operating Modes 3 25 Operating Modes Table 3 17 Low Power Mode Logic Chart for Basic Clock System
84. 11 11 Addressing Mode Syntax Register mode Rn Indexed mode X Rn Symbolic mode ADDR Absolute mode amp ADDR Indirect register Rn mode Indirect Rn autoincrement Immediate mode N Description Register contents are operand Rn X points to the operand X is stored in the next word PC X points to the operand X is stored in the next word Indexed mode is used The word following the instruction contains the absolute address Rn is used as a pointer to the operand Rn is used as a pointer to the operand Rn is incremented afterwards The word following the instruction contains the immediate constant N Indirect autoincrement mode PC is used The seven addressing modes are explained in detail in the following sections Most of the examples show the same addressing mode for the source and destination but any valid combination of source and destination addressing modes is possible in an instruction 16 Bit CPU 57 Addressing Modes 5 2 1 Register Mode The register mode is described in Table 5 5 Table 5 5 Register Mode Description Assembler Code Content of ROM MOV R10 R11 MOV R10 R11 Length One or two words Operation Move the content of R10 to R11 R10 is not affected Comment Valid for source and destination Example MOV R10 R11 Before After Note Data in Registers The data in the register can be accessed using word or byte instructions If byte instructions are used
85. 12 9 Address Bit Multiprocessor Format 12 10 State Diagram of Receiver 12 11 State Diagram of Transmitter Enable 12 12 Receive Interrupt Operation 12 13 Transmit Interrupt Operation 12 14 XV Contents 12 16 12 17 12 18 12 19 12 20 12 21 12 22 12 23 12 24 12 25 12 26 12 27 12 28 12 29 13 1 13 2 13 3 13 4 13 5 13 6 13 7 13 8 13 9 13 10 13 11 13 12 13 13 13 14 13 15 13 16 13 17 13 18 13 19 13 20 13 21 13 22 14 1 14 2 14 3 14 4 14 5 14 6 14 7 14 8 14 9 14 10 14 11 14 12 14 13 14 14 xvi USART Control Register UOCTL 12 16 Transmitter Control Register UOTCTL 12 18 Receiver Control Register UORCTL 1 12 19 USART Baud Rate Select Register 12 21 USART Modulation Control 5 12 21 USARTO Receive Data Buffer UORXBUF UTRXBUF 12 22 Transmit Data Buffer UOTXBUF U1TXBUF 12 22 Receive Start Conditions 12 23
86. 15 Up Down Mode Flag Setting Timer Clock Timer Up Down Set CCIFGO Set TAIFG 10 3 4 1 Timer In Up Down Mode Changing the Value of Period Register CCRO Changing the period value while the timer is running in up down mode is even trickier than in up mode Like in up mode the phase of the timer clock when CCRO is changed affects the timer s behavior Additionally in up down mode the direction of the timer also affects the behavior If the timer is counting in the up direction when the new period is written to CCRO the conditions in the up down mode are identical to those in the up mode See Section 10 3 2 1 for details However if the timer is counting in the down direction when CCRO is updated it continues its descent until it reaches zero The new period takes effect only after the counter finishes counting down to zero See Figure 10 16 Figure 10 16 Altering CCRO Timer in Up Down Mode 10 12 Timer Register 0111213 E E ere E NB EN LL lil lil UUUUUUL 12111011201 4 514 3 21110 1 213 4 3 2111011 2 312111011211 0 1 2 3 4 5 AR CCRO 2 Timer Modes 10 4 Capture Compare Blocks Three or five depending on device identical capture compare blocks shown in Figure 10 17 provide flexible control for real time processing Any one of the blocks may be used to capture the timer data at an applied event
87. 16 6 3 Using the MSC Bit If the operating mode is other than single channel single conversion CONSEQ gt 0 the MSC bit can be used to configure the converter to perform the successive conversions automatically and as quickly as possible If MSC 0 then a rising edge of the SHI signal is required to trigger each sample and conversion regardless of what mode the converter is in When MSC 1 and CONSEQ gt 0 the first rising edge of the SHI signal triggers the first conversion but successive conversions are triggered automatically as soon as the prior conversion is completed Additional rising edges on SHI are ignored until the sequence is completed or until the ENC bit is toggled depending on mode The function of the ENC bit is unchanged when using the MSC bit See Figure 16 12 and Figure 16 13 Figure 16 12 Use of MSC Bit With Nonrepeated Modes 5 PP gr SAMPCON Single channel MSC 0 SAMPCON 4 41 Single channel MSC 1 ANI A 2 3 4 Sequence of SAMPCON 45 1 Pa Channel MSC 0 S C S C S C S C S C yi 2 3 4 2 3 4 Sequence of SAMPCON 4 4 channel MSC 1 S C sc sc sc sc sc sc sc S C Conversion Period Sample Period Figure 16 13 Use of MSC Bit With Repeated Modes
88. 2 7 5 Oscillator Fault Interrupt 7 6 Oscillator Fa lt Signal unies eru RERO RERUM ER Ru E er cR 7 7 xiii Figure 7 7 7 8 7 9 7 10 7 11 7 12 7 13 7 14 7 15 7 16 10 8 10 9 10 10 10 11 10 12 10 13 10 14 10 15 10 16 10 17 10 18 10 19 10 20 10 21 10 22 10 23 10 24 10 25 10 26 10 27 10 28 10 29 10 30 10 31 xiv Oscillator Fault in Oscillator Error Condition 7 7 Oscillator Fault in Oscillator Error Condition at Start Up 7 8 NMI OSCFault Interrupt Handler 7 9 DCO Schematic d Be D Dre e etse etre 7 10 Principle Period Steps of the 7 11 On Off Control 2 22 2 2 2 7 11 Operation of the DCO 7 12 Select Crystal Oscillator for MCLK Example Uses LFXT1 for MCLK 7 15 Timing to Select Crystal Oscillator for MCLK Example Uses LFXT1 in HF Mode f r MCEK oee ai enden PREDA 7 16 Select Another Clock Source Signal Example Switches From DCOCLK to LFXT1CLK for Clock MCLK
89. 35 TEXAS INSTRUMENTS MSP430x1xx Family User s Guide 2002 Mixed Signal Products SLAU049B IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or
90. 40 1 Ri meas lt R1 ref PED CAEX CAON e g al 1 Input of Timer A C1 0 _ gt 0 1 P2CA1 Vcc R2 meas 2 CAREF HI Q N CARSEL 0 1 e 025 Comparator 14 15 Comparator A in Applications 14 4 4 Comparator A Used to Detect a Current or Voltage Level Comparator_A can be used to detect current or voltage levels if they are below or above a reference level shown in Figure 14 12 The reference level can be selected from the internal reference voltage generator or by applying an external reference level Application software can poll the CAOUT bit for the status of the comparator or use the interrupt flag CAIFG to determine if the level of the current or voltage source has crossed the comparator threshold In Figure 14 12 two external voltages are compared Application software can poll the CAOUT bit CAOUT 0 V signal V ref CAOUT 1 V signal gt V ref Figure 14 12 Detect a Voltage Level Using an External Reference Level 0 0 i 0 CAOUT to V Signal 204 0 Voltage 9 15 0 External Pin CA1 dl Oo Set 2 1 CAIFG Reference V Voltage CAREF CARSEL 21 Vonner a 14 16 Voc Y long as CAOUT is reset 0 Vcc PeCA0 90 o
91. ACLK auxiliary clock The ACLK is the buffered LFXT1CLK clock source divided by 1 2 4 or 8 Software selects the division factor ACLK is software selectable for individual peripheral modules MCLK master clock MCLK is software selectable as LFXT1CLK XT2CLK if available or DCOCLK MCLK is divided by 1 2 4 or 8 Software selects the division factor MCLK is used by the CPU and system SMCLK submain clock SMCLK is software selectable as LFXT1CLK XT2CLK if available or DCOCLK SMCLK is divided by 1 2 4 or 8 Software selects the division factor SMCLK is software selectable for individual peripheral modules Basic Clock Module 73 LFXT1 and XT2 Oscillators 7 2 LFXT1 and 2 Oscillators The Basic Clock Module includes the LFXT1 oscillator and in some configurations a second 2 oscillator 7 2 4 LFXT1 Oscillator The LFXT1 oscillator starts operating on a valid PUC condition A valid PUC condition resets the OscOff bit in the status register which enables LFXT1 Software can disable LFXT1 by setting OscOff if this signal does not source SMCLK or MCLK The design of the LFXT1 oscillator shown in Figure 7 2 supports the low current consumption feature and the use of a 32 768 Hz watch crystal when in LF mode XTS 0 A watch crystal connects to the clock module via two terminals without any other external components Components necessary to stabilize the clock operation have been integrated into the MSP430
92. CAON CAF 0 Jo e o 4 Risense 0 ee all CAT T Set 7 2 1 L Sd CAIFG Optional T 2US R hyst OV Vcc 40 1 Px y CAON 2 CARSEL L 1o 0 VCAREF 2 e CAREF 0 5 x Voc 0 25 x Voc 14 4 5 Comparator A Used to Measure a Current or Voltage Level In addition to detecting levels the comparator can be used to measure currents or voltages To measure a voltage a known stable voltage source is used to charge up an RC combination The time required to charge the combination to a threshold value set by the voltage to be measured is then used to calculate the voltage level see Figure 14 16 can be used required stability and accuracy as the known stable voltage source if Vcc in the user s system meets the through a known resistance see Figure 14 14 A similar approach is used to measure a current A known stable voltage source is again used to charge an RC combination to a threshold value In this case the threshold voltage is created by passing the current to be measured Comparator A 14 17 In Figure 14 13 current is transferred to an input voltage by x R sense The current limit is set for example to 0 25 The current is below the limit as Figure 14 13 Detect a Current Level Using an Internal Reference Level Comparator A in Applications Comparator A in Applications Figure 14 14 Measuring a Current Source
93. Contents 10 6 3 Capture Compare Control Register CCTLx 10 27 10 6 4 Timer A Interrupt Vector Register 10 29 10 7 mmer AVARE e inue ue LE E dX E RAE ERE 10 33 1T Timer B iml elei eek eI pn itera c muda Leis oak aa 11 1 111 introductlon c o oes eese ear max eov ark asas E ask ks 11 2 11 1 1 Similarities and Differences From 11 2 112 Timer B 11 5 11 2 1 Mer LEO wis sux os Oe adu 11 5 11 2 2 Timer Mode 11 5 11 2 3 Clock Source Select and 11 6 11 2 4 Starting the Timer 11 7 TAS Timer MOOS oos ome eer oon es tr rt certe rebate odere PR ene 11 8 11 3 1 Timer Stop Mode 11 8 11 3 2 i rer sir Meu ad ee oR 11 8 11 3 3 Timer Continuous Mode 11 10 11 3 4 Timer Up Down Mode 11 12 11 4 Blocks 11 15 11 4 1 Capture Compare Block Capture Mode
94. If there is not a match the processor waits for the next address character to arrive USART Peripheral Interface UART Mode 12 9 Asynchronous Operation Figure 12 11 Address Bit Multiprocessor Format Block of Frames SSSR r E pe Idle Periods of No Significance pere TXD RXD Expanded UTXD URXD First Frame Within Block ADDR DATA Bit Is O Is an Address The for Data Within Block ADDR DATA Bit Is 1 Idle Time Is of No Significance In the address bit multiprocessor mode the address bit of a character can be controlled by writing to the TXWake bit The value of the TXWake bit is loaded into the address bit of that character each time a character is transferred from transmit buffer UxTXBUF to the transmitter The TXWake bit is then cleared by the USART 12 10 Interrupt and Enable Functions 12 4 Interrupt and Enable Functions The USART peripheral interface serves two main interrupt sources for transmission and reception Two interrupt vectors serve receive and transmit events The interrupt control bits and flags and enable bits of the USART peripheral interface are located in the SFR registers They are discussed in Table 12 1 See the peripheral file map in Appendix A for the exact bit locations Table 12 1 USART Interrupt Control and Enable Bits UART Mode Receive interrupt flag URXIFG Initial state reset by PUC SWRST Receive in
95. Instruction fetches from program memory are always 16 bit accesses whereas data memory can be accessed using word 16 bit or byte 8 bit instructions Any access uses the 16 bit memory data bus MDB and as many of the least significant address lines of the memory address bus MAB as required to access the memory locations Blocks of memory are automatically selected through module enable signals This technique reduces overall current consumption Program memory is integrated as programmable or mask programmed memory In addition to program code data may also be placed in the ROM section of the memory map and may be accessed using word or byte instructions this is useful for data tables for example This unique feature gives the MSP430 an advantage over other microcontrollers because the data tables do not have to be copied to RAM for usage Sixteen words of memory are reserved for reset and interrupt vectors at the top of the 64 kilobytes address space from OFFFFh down to OFFEOh 2 4 Data Memory The data memory is connected to the CPU through the same two buses as the program memory ROM the memory address bus MAB and the memory data bus MDB The data memory can be accessed with full word data width or with reduced byte data width Additionally because the RAM and ROM are connected to the CPU via the same busses program code can be loaded into and executed from RAM This is another unique feature of the MSP430 devices a
96. Oh At At At At At At At At At At At At Time intervals can be produced with other modes as well where CCRO is used as the period register Their handling is more complex since the sum of the old CCRx data and the new period can be higher than the CCRO value When the sum CCRxold plus At is greater than the CCRO data the CCRO value must be subtracted to obtain the correct time interval The period is twice the value in the CCRO register 10 3 4 Timer Up Down Mode Figure 10 12 10 10 The up down mode is used if the timer period must be different from the 65 536 clock cycles and if symmetrical pulse waveform generation is needed In up down mode the timer counts up to the content of compare register CCRO then back down to zero as shown in Figure 10 12 The period is twice the value in the CCRO register Timer Up Down Mode CCRO Figure 10 13 Figure 10 14 Timer Modes The up down mode also supports applications that require dead times between output signals For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the following example see Figure 10 13 the tgeag is tdead timer X CCR1 CCR2 With tgeag Time during which both outputs need to be inactive ttimer Cycle time of the timer clock CCRx Content of capture compare register x Output Unit in Up Down Mode 11
97. Operand 1 address defines operation Operand 1 Mode Accumulator ACC SumHi 13Ch SumLo 013Ah Hardware Multiplier 6 3 Hardware Multiplier Operation The sum extension register contents differ depending on the operation and on the results of the operation Table 6 1 Sum Extension Register Contents Register MPY MPYS MAC MACS see Notes Operand1 x OP1xOP2 OP1xOP2 OP1xOP2 OP1xOP2 S gt gt lt 2 Toc QOFFFFFFFFh OFFFFFFFFh 07FFFFFFFh 07FFFFFFFh SumExt 0000h 0000h OFFFFh 0000h 0001h OFFFFh 0000h Note The following two overflow conditions may occur when using the MACS function and should be handled by software or avoided 1 The result of a MACS operation is positive and larger than 7 FFFFh In this case the SumExt register contains OFFFFh and the ACC register contains a negative number 8000 0000h OFFFF FFFFh 2 Theresultof a MACS operation is negative and less than or equalto 07FFF FFFFh Inthis case the SumExt register contains 0000h and the ACC register contains a positive number 0000 0000h 07FFF FFFFh 6 2 1 Multiply Unsigned 16x16 bit 16x8 bit 8x 16 bit 8x8 bit The following is an example of unsigned multiplication 16x16 Unsigned Multiply MOV 01234h amp MPY Load first operand into appropriate register MOV 05678h amp OP2 Load 2nd operand Result is now available
98. Output register PSOUT 7 6 PSOUT 5 4 P5OUT 3 PSOUT 2 PSOUT 1 PSOUT O 0031h rw rw rw rw rw rw rw rw Input register P5IN 7 P5IN 6 P5IN 5 P5IN 4 P5IN 3 P5IN 2 P5IN 1 0 0030h r r r r r r r r or J Function select P2SEL P2SEL 7 P2SEL 6 P2SEL 5 P2SEL 4 P2SEL 3 P2SEL 2 P2SEL 1 P2SEL O 002Eh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Interrupt enable P2IE P2IE 7 P2IE 6 P2IE 5 21 4 P2IE 3 P2IE 2 P2IE 1 P2IE 0 002Dh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Interrupt edge select 21 5 P2IES 7 P2IES 6 P2IES 5 P2IES 4 21 5 3 P2IES 2 P2IES 1 21 5 0 002Ch rw rw rw rw rw rw rw rw Interrupt flags P2IFG P2IFG 7 P2IFG 6 P2IFG 5 P2IFG 4 P2IFG 3 P2IFG 2 P2IFG 1 P2IFG O 002Bh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Direction register P2EDIR P2DIR 7 P2DIR 6 P2DIR 5 P2DIR 4 P2DIR 3 P2DIR 2 P2DIR 1 P2DIR O 002Ah rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Output register PROUT P2OUT 7 P2OUT 6 P2OUT 5 P2OUT 4 P2OUT 3 P2OUT 2 P2OUT 1 P2OUT O 0029h rw rw rw rw rw rw rw rw Input register P2IN P2IN 7 P2IN 6 2 5 P2IN 4 P21N 3 2 2 P2IN 1 2 0 0028h r r r r r r r r DI c uc quse cos ccr s Function select PISEL P1SEL 7 P1SEL 6 PISEL 5 P1SEL 4 P1SEL 3 P1SEL 2 P1SEL 1 P1SEL O 0026h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Interrupt enable P1IE P1IE 7 P1IE 6 P1IE 5 P1I
99. POR signal or if bit CLR is set The CLR bit is automatically reset andis always read as zero The timer starts in the upward direction with the next valid clock edge unless halted by cleared mode control bits Not used Bits 4 5 Mode control Table 10 4 describes the mode control bits Table 10 4 Mode Control MC1 MCO Count Mode 0 EE gx 7 6 1 0 1 Stop Up to CCRO Continuous up Up down Description Timer is halted Timer counts up to CCRO and restarts at O Timer counts up to OFFFFh and restarts at 0 Timer continuously counts up to CCRO and back down to 0 Bits 6 7 Input divider control bits Table 10 5 describes the input divider control bits Timer A 10 25 Timer A Registers Table 10 5 Input Clock Divider Control Bits ID1 IDO Operation Description 0 0 1 Input clock source is passed to the timer 0 1 2 Input clock source is divided by two 1 0 4 Input clock source is divided by four 1 1 8 Input clock source is divided by eight Bits 8 9 Clock source selection bits Table 10 6 describes the clock source selections Table 10 6 Clock Source Selection SSEL1 SSELO O PSignal Comment 0 0 TACLK See data sheet device description 0 1 ACLK Auxiliary clock ACLK is used 1 0 SMCLK System clock SMCLK 1 1 INCLK See device description in data sheet Bits 10 to 15 Unused Te Note Changing Timer_A Control Bits If the timer operation is modified by the control bi
100. PUSH SIC SP 2 SP src SP SWPB dst Swap bytes CALL dst SP 2 gt SP 2 stack dst RETI TOS SR SP lt SP 2 X X X X TOS PC SP lt SP 2 SXT dst Bit 7 Bit 8 Bit 15 0 The status bit is affected status bit is not affected 0 The status bit is cleared 1 The status bit is set All addressing modes are possible for the CALL instruction If the symbolic mode ADDRESS the immediate mode N the absolute mode amp EDE or the indexed mode X RN is used the word that follows contains the address information 16 Bit CPU 5 19 Instruction Set Overview 5 3 3 Conditional Jumps Conditional jumps support program branching relative to the program counter The possible jump range is from 511 to 512 words relative to the program counter state of the jump instruction The 10 bit program counter offset value is treated as a signed 10 bit value that is doubled and added to the program counter None of the jump instructions affect the status bits The instruction code fetch and the program counter increment technique end with the formula 2 PCoffset x 2 Figure 5 9 shows the conditional jump instruction format Figure 5 9 Conditional Jump Instruction Format 1514 13 12 1 10 9 8 7 6 5 4 3 2 1 9 Table 5 19 describes these conditional jump instructions Table 5 19 Conditional Jump Instructions Mnemon
101. Peripheral modules that are mapped into the byte address space must be accessed with byte instructions MOV B 1 amp P1OUT The addressing of both is through the absolute addressing mode or the 16 bit working registers using the indexed indirect or indirect autoincrement addressing mode See Figure 4 7 for the RAM peripheral organization Figure 4 7 Example of RAM Peripheral Organization Address Function Access Hex 0 01 Timer Word 16 Bit Peripheral Modules 0100h OFFh USART Bi i Byte 8 Bit Peripheral Modules OFh Oh Special Function Registers SFR Byte 4 4 21 Word Modules Word modules are peripherals that are connected to the 16 bit MDB Word modules can be accessed with word or byte instructions If byte instructions are used only even addresses are permissible and the high byte of the result is always 0 The peripheral file address space is organized into sixteen frames with each frame representing eight words as described in Table 4 1 4 8 Table 4 1 Peripheral File Address Map Word Modules 4 4 2 2 Byte Modules Address 1F0h 1FFh 1E0h 1EFh 1DOh 1DFH 1 1CFH 1BOh 1BFH 1A0h 1AFH 190h 19FH 180h 18FH 170h 17FH 160h 16FH 150h 15FH 140h 14FH 130h 13FH 120h 12FH 110h 11FH 100h 10FH Description Reserved Reserved Reserved Reserved Reserved RA
102. TDI Figure C 11 Signal Connections to MSP430 JTAG Pins Level Shifter VCC TMS gt TMS TCK gt tle TCK EN1 TDI gt TDI TDO TDO TDI 1 SN74AHC244 MSP430Fxxx TCLK gt XOUT TCLK EN2 Test VPP gt TE tl Vcc DVcc gt Vss DVss C 5 3 Programming a Flash Memory Module via Controller Software No special external hardware is required to program a flash memory module The power supply at Vcc should supply sufficient current during write program and erase modes Please separate the device s data sheet for flash write end erase current The software algorithm is simple The embedded timing generator in the flash memory module controls the program and erase cycles Software can run in the same flash memory module where data is to be written on in other memory modules such as ROM RAM or another flash memory module Flash Memory Access via JTAG and Software C 5 3 1 Example Programming One Word Into a Flash Memory Module via Software Execution Outside This Module This example assumes that the code to program the flash location is not executed from the target flash memory module Disable all Interrupt Sources FXKEY set 03300 and Watchdog FWKEY set 0A500h No interrupt request may happen while the flash is programmed Test Busy1 BIT BUSY amp FCTL3 JNZ Test_Busy1 LOCK 0 WRT 1 MOV FWKEY amp FCTL3 Clear lock bit Write Data to Flas
103. TOS is moved to the destination The stack pointer is incremented by two afterwards Status bits are not affected The contents of R7 and the status register are restored from the stack POP R7 POP SR Restore R7 Restore status register The contents of RAM byte LEO is restored from the stack LEO low byte of the stack is moved to LEO The contents of R7 is restored from the stack R7 The low byte of the stack is moved to R7 the high byte of R7 is 00h The contents of the memory pointed to by R7 and the status register are restored from the stack O R7 low byte of the stack is moved to the the byte which is pointed to by R7 Example R7 203h Mem R7 low byte of system stack Example R7 2 20Ah 4 Mem R7 low byte of system stack POP SR S Note The System Stack Pointer The system stack pointer SP is always incremented by two independent of the byte suffix es Instruction Set Description B 43 Instruction Set Overview PUSH W PUSH B Syntax Operation Description Status Bits Mode Bits Example Example B 44 Push word onto stack Push byte onto stack PUSH src or PUSH W src PUSH B SIC SP 2 gt SP src gt SP The stack pointer is decremented by two then the source operand is moved to the RAM word addressed by the stack pointer TOS N Not affected Z Not affected C Not affected V Not affected
104. The USART module slave mode is selected when the MM bit is reset Bit 2 Peripheral module mode select The SYNC bit sets the function of the USART peripheral interface module Some of the USART control bits have different functions in UART and SPI modes SYNC 0 UART function is selected SYNC 1 SPI function is selected Bit 3 The listen bit determines the transmitted data to feed back internally to the receiver This is commonly called loopback mode Bit 4 Character length This register bit sets the length of the character to be transmitted as either seven or eight bits CHAR 0 7 bit data CHAR 1 8 bit data Bit 5 Unused Bit 6 Unused Bit 7 Unused Control and Status Registers 13 5 2 Transmit Control Register UOTCTL U1TCTL The transmit control register shown in Figure 13 16 controls the USART hardware associated with transmitter operations Figure 13 16 Transmit Control Register sae U1TCTL e om oom U1TCTL 079h Bit 0 Bit 1 Bit 2 Bit 3 Bits 4 5 Bits 6 7 Un rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw O0 rw 1 Master mode The transmitter empty flag TXEPT is set when the transmitter shift register and UXTXBUF are empty and reset when data written to UXTXBUF It is set again by a SWRST Slave mode The transmitter empty flag TXEPT is not set when the trans mitter shift register and UxTXBUF are empty The slave transmit control bit STC selects if the STE pin
105. The port pin is switched to output direction 8 2 1 4 Interrupt Flags P1IFG P2IFG Each interrupt flag register contains eight flags that reflect whether or not an interrupt is pending for the corresponding I O pin if the I O is interrupt enabled When Bit 0 No interrupt is pending Bit 1 An interrupt is pending due to a transition at the I O pin or from software setting the bit 2 6 Note Manipulating P1OUT and P1DIR as well as P2OUT and P2DIR can result in setting the P1IFG or P2IFG bits 1 Writing a zero to an interrupt flag resets it writing a one to an interrupt flag sets it and generates an interrupt Each group of interrupt flags P1FLG 0 to P1FLG 7 and P2FLG 0 to P2FLG 7 sources its own interrupt vector Interrupt flags P1IFG 0 to P1IFG 7 and P2IFG 0 to P2IFG 7 are not reset automatically when an interrupt from these events is serviced The software should determine the origin of the interrupt and reset the appropriate flag s E 1 Note Any external interrupt event should be at least 1 5 times MCLK or longer to ensure that it is accepted and the corresponding interrupt flag is set Digital I O Configuration 8 5 Ports P1 P2 8 2 1 5 Interrupt Edge Select P1IES P2IES Each interrupt edge sele
106. W DADD B src dst src dst C dst dec MOV W src dst src gt dst SUB W 50 src dst dst not src 1 dst SUBC W SUBC B src dst dst not src C dst XOR W XOR B src dst src dst dst Status Bits VN 7 1 Note Operations Using the Status Register SR for Destination All operations using Status Register SR for destination overwrite the SR contents with the operation result as described in that operation the status bits are not affected Example ADD 3 SR _ Operation SR 3 gt SR Instruction Set Overview B 1 1 2 Single Operand Instructions Core Instructions The instruction format using a single operand as shown in Figure 2 consists of two main fields to form a 16 bit code J operational code field nine bits with four MSBs equal to 1h L byte operation identifier one bit B W L destination field six bits destination register Ad The destination field is composed of two addressing bits and the four bit register number 0 15 The destination field bit position is the same as that of the two operand instructions The byte identifier B W indicates whether the instruction is executed as a byte B W 1 or as a word B W 0 Figure B 2 Single Operand Instructions 15 12 1 10 9 7 6 5 4 3 0 Operational Code Field Destination Field Status Bits VN ZC RRA W RRA B dst MSB MSB 15 Os te RRC W RRC B
107. available only during the same sample and conversion period Figure 16 24 ADC10 Current Consumption With Internal Reference On Routed Externally and REFBurst 1 2 4 NI IAVG IREF IREFB lADC10 lLoad X tS amp C tPeriod IRefB is only 5 consumed if 5 2 0 A Z7 ZZ Sample Sample Mice i 2 Conversion a tsac gt VREF 4 tPeriod gt Sref 0 2 4 OV 4 6 7 The average current consumed is lavG IREF IREFB 10 Load X ts amp c tPeriod li external load current ADC10 16 43 A D Grounding and Noise Considerations 16 10 A D Grounding and Noise Considerations As with any high resolution converter care and special attention must be paid to the printed circuit board layout and the grounding scheme to eliminate ground loops and any unwanted parasitic components effects and noise Industry standard grounding and layout techniques should be followed to reduce these unwanted effects Ground Loops are formed when return current from the A D flows through paths that are common with other analog or digital circuitry If care is not taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A D converter One way to avoid ground loops is to use star connection scheme for AVss shown in Figure 15 26 This way the ground current or
108. bit in each conversion memory control register marks the end of an automatic conversion sequence The EOS bit when set defines the end of a conversion sequence When cleared an internal conversion memory pointer not visible to software is incremented after the current conversion is completed and the conversion result is stored in the conversion memory The conversion memory pointer is then prepared to use the next conversion memory register to store the results of the next conversion The internal conversion memory pointer is incremented with each conversion until a set EOS bit is encountered Note that defining the end of a sequence is independent from defining the mode of operation see the Conversion Modes section and that the EOS bits are ignored when using single conversion mode or repeated conversion of a single channel mode Conversion sequences always use sequential conversion memory registers can start with any conversion memory register and do not necessarily require any EOS bit to be set For example if the CONSEQ bits define the mode of operation to be conversion of a sequence single or repeated the CStartAdd bits point to conversion memory register 14 and no EOS bits are set for any of the conversion memory registers then the conversion memory registers will be used in sequential order 14 15 0 1 2 14 15 0 1 2 etc for each consecutive conversion and the sequence of conversions will continue until sto
109. coupling between channels Channels that are not selected are isolated from the A D and the intermediate node is connected to analog ground AVss so that the stray capacitance is grounded to help eliminate crosstalk Figure 15 3 Analog Multiplexer Channel 15 6 R 1000hm ADC12MCTLx 0 3 ESD Protection Crosstalk can exist because there is always some parasitic coupling capacitance across the switch and between switches This can take several forms such as coupling from the input to the output of an off switch or coupling from an off analog input channel to the output of an adjacent on channel For high accuracy conversions crosstalk interference should be minimized by shielding and other well known printed circuit board PCB layout techniques Analog Inputs and Multiplexer 15 3 2 Input Signal Considerations During sampling the analog input signal is applied to the internal capacitor array of the A D core Therefore the charge of the capacitor array is supplied directly by the source The capacitor array has to be charged completely during the sampling period Therefore the external source resistances dynamic impedances and capacitance of the capacitor array must be matched with the sampling period so the analog signal can settle to within 12 bit accuracy Additionally source impedances also affect the accuracy of the converter The source signal can drop at the input of the device due to leakage cur
110. gt TBR max the counter operates as if it were configured for continuous mode It will not count down from TBR may to zero The timer clock can be sourced from internal clocks i e ACLK MCLK or SMCLK or from an external source TBCLK as shown in Figure 11 3 The clock source is selectable with the SSELO and SSEL1 bits in the TBCTL register It is important to note that when changing the clock source for the timer errant timings can occur For this reason stopping the timer before changing the clock source is recommended The selected clock source may be passed directly to the timer or divided by 2 4 or 8 as shown in Figure 11 4 The IDO and ID1 bits in the TBCTL register select the clock division Note that the input divider is reset by a POR signal or by setting the CLR bit in the TBCTL register see chapter 3 System Resets Interrupts and Operating Modes for more information on the POR signal Otherwise the input divider remains unchanged when the timer is modified The state of the input divider is invisible to software Figure 11 3 Schematic of 16 Bit Timer SSEL1 SSELO Timer Clock Data Lhe 15 0 0 A 186 16 Bit Timert 1 nput CLK Mode ACLK Oo Divider RC Control EquO SMCLK o ote Carry Zero d ID1 IDO MC1 MCO Set TBIFG POR CLR INCLK o 34 Pass 0 0 Stop Mode 0 1 1 2 0 1 Up Mode 1 0 1 4 1 0 Continuous Mode 1 1 1 8 1 1 Up Down Mode t Length is
111. or to generate time intervals Each time a capture occurs or a time interval is completed interrupts can be generated from the applicable capture compare register The mode bit CAPx in control word CCTLx selects the compare or capture operation and the capture mode bits CCMx1 and CCMx0 in control word CCTLx define the conditions under which the capture function is performed Both the interrupt enable bit CCIEx and the interrupt flag CCIFGx are used for capture and compare modes CCIEx enables the corresponding interrupt CCIFGx is set on a capture or compare event Thecapture inputs CCIxA and CCIxB are connected to external pins or internal signals MSP430x1xx devices may have different signals connected to CCIxA and CCIxB The data sheet should always be consulted to determine the Timer connections for a particular device Figure 10 17 Capture Compare Blocks CCISx1 CCISxO GG 026 05 o GND o Vcc o Overflow x _4 Capture Capture Compare Register CCRx Disabled Positive Edge Negative Edge Both Edges Timer Bus CAPx Capture Mode 1 0 0 1 1 Set CCIFGx Y SCCIx CCIx Timer A 10 13 Timer Modes 10 4 1 Capture Compare Block Capture Mode The capture mode is selected if the mode bit CAPx located in control word CCTLx is set The capture mode is used to fix time events It can be used fo
112. s complement ADC10DF 1 format Binary format Zero scale code 000h Vcode Vp Full scale code 3FFh Vcode Vg 1 LSB 2 s complement format Minus full scale code 08000h Vcode Vp Full scale code 07FCOh Vcode Vp 1 LSB ADC10 ADC10 Control Registers SHS bits Source select for the sample input signal 10 11 0 Control bit ADC10SC is selected 1 Timer A OUT1 2 Timer A OUTO 3 Timer A OUT2 INCH bits Input channel bits are used to select which ADC10 input channel is 12 15 converted Warning Modifying ADC Control Register During Active Conversion The enable conversion control bit ENC inthe ADC10CTLO register protects most bits from modification during an active conversion However some bits that are necessary for proper completion of active conversions and interrupt enable bits can be modified independenily of ENC The user must use caution when modifying theses bits to ensure an active conversion is not corrupted or to not use corrupted data To avoid corrupting any active conversions stop the conversion wait for the busy bit to be reset reset the ENC bit then modify the control bits 16 7 2 Analog Input Enable Control Register These control bits are implemented for two operational reasons 1 To stop any throughput current at the input buffers if an analog signal is applied 2 To prevent any feedback from the general purpose I O circuitry to the analog signal s sou
113. which is enabled and has the highest priority determines the interrupt vector word and is reset by hardware after accessing instruction ADD amp TADC12IV PC Flags ADC120V ADC12TOV and ADC12IFG x are reset by hardware ADC HND Interrupt latency 6 ADD amp ADC12IV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP ADC120V Vector 2 ADC overflow 2 JMP ADC12TOV Vector 4 ADC timing overflow 2 JMP ADC12MODO Vector 6 ADC12MEMO was loaded Nets subiicere Ye antudeces ADC12IFG 0 2 JMP 12 1 Vector 8 ADC12MEM1 was loaded rece area Por NEN ADC12IFG 1 2 JMP ADC12MOD13 Vector 34 ADC12MEM14 was loaded ADC12IFG 14 2 JMP ADC12MOD14 Vector 36 ADC12MEM15 was loaded ADC12IFG 15 2 Module 15 Handler for ADC12IFG 15 starts here Note a JMP instruction is not needed to get here because the PC is already here after the ADD amp ADC12IV PC instruction i ADC120V Vector 2 ADC120V Flag First instruction to handle ADC12 overflow condition i ADCIA2TOV 202 Vector 4 ADC120V Flag First instruction to handle ADC12 timing overflow condition ADC12MOD2 Vector 10 ADC12MEM2 was loaded ADC12IFG 2 MOV amp ADC12MEM2 R6 ADCI2IFG2 is reset due to access of ADC memory Task starts here ADC12 15 39 ADC12 Control Registers 15 40 RETI Back to main program 5 i ADC12MOD1 Vector 8 A
114. 1 50 153 290 253 31 and 32 The ADC10 incorporates two bits ADC10ON and REFON for power savings ADC10ON turns on the A D core and REFON turns on the reference generator Each bit is individually controllable by software The ADC10 is turned off completely if both bits are reset Register ADC10MEM is not affected by either of these bits and can be accessed and modified at any time see the ADC10 Control Registers section Note however that ADC10ON and REFON may only be modified if ENC 0 Additionally other ADC10 functions are automatically switched on and off as needed if possible to realize additional power savings even while the ADC10 is running Caution Powering Down Active Converter Do not power down the converter or the reference generator while the converter is active Conversion results will be false It is possible to disable the reference generator and the ADC10 by resetting bits ADC10ON and REFON before an active conversion or sequence of conversions has completed For example if the conversion mode is set to sequence of channels and software resets the ENC bit immediately after the sequence begins the ADC100ON and REFON bits can then be reset before the sequence completes If this occurs the ADC10 will be powered down immediately and the conversion results will be false Conversion Clock and Conversion Speed Caution Considerations Before Turning the ADC10 and Voltage Reference On or Off ADC10 turnon ti
115. 11 16 11 4 2 Capture Compare Block Compare Mode 11 19 11 5 Output Unit 11 23 11 5 2 Output Control 11 25 11 5 3 Outp t Examples 11 26 116 Timer B Registers 11 29 11 6 1 Timer B Control Register TBCTL 11 29 11 6 2 Timer B Register TBR 11 32 11 6 3 Capture Compare Control Register CCTLx 11 32 11 6 4 Timer B Interrupt Vector Register 11 35 12 USART Peripheral Interface UART Mode 12 1 12 1 USART Peripheral 12 2 12 2 USART Peripheral Interface UART 12 3 12 2 1 UART Serial Asynchronous Communication Features 12 3 12 3 Asynchronous Operation 12 4 12 3 1 Asynchronous Frame Format 12 4 12 3 2 Baud Rate Generation Asynchronous Communication Format 12 5 12 3 8 Asynchronous Communication Formats 12 7 12 3 4 ldle Line Multiprocessor
116. 12 bit representation and stores the results in the conversion memory The core uses two programmable selectable voltage levels and Vp to define the upper and lower limits of the conversion range and to define the full scale and zero scale readings The digital output is full scale when the input signal is equal to or higher than and zero when the input signal is equal to or lower than Vg The input channel and the reference voltage levels VR and are defined in the conversion control memory The conversion formula is Vin V 4095 x Figure 15 2 ADC Core Input Multiplexer Sample and Hold ADC12MCTLx 0 3 VeREF VREF Temperature 2 15 4 ADC12MCTLx 4 6 Y Y From Reference ADC120N ADC12CLK 12 bit A D Converter Core Analog Multiplexer 12 1 SAMPCON To ADC12MEMx Itis important to note that the 3 LSBs ofthe conversion are resolved resistively Therefore when the 3 LSBs are being resolved during a conversion approximately 200 uA will be required from the reference The user should keep this in mind when choosing and decoupling an external reference Refer to the device data sheet for more details on ADC12 specifications 15 2 2 Reference ADC12 Description and Operation Caution ADC12 Turnon Time When the ADC12 is turned on with the ADC120ON bit the turnon time noted in the data sheet
117. 12 bit mode will show leading Os The maximum count value TBR max for the various lengths is Timer B Configuration TBR max 16 bit OFFFFh 12 bit OFFFh 10 bit O3FFh 8 bit OFFh 11 2 2 Timer Mode Control The timer has four modes of operation as shown in Figure 11 2 and described in Table 11 1 stop up continuous and up down The operating mode is software selectable with the MCO and MC1 bits in the TBCTL register Figure 11 2 Mode Control Data 15 16 Bit Timert gt EquO Control Carry Zero Set TBIFG Stop Mode Up Mode Continuous Mode Up Down Mode POR t Length is selectable for 8 10 12 or 16 bit operation Timer B 11 5 Timer B Operation Table 11 1 Timer Modes Mode Control MC1 MCO Description 0 0 Stop The timer is halted 0 1 Up The timer counts upward until its value is equal to the value of compare latch TBCLO Note If TBCLO gt TBR max the counter counts to zero with the next rising edge of timer clock Continuous The timer counts upward continuously The maximum value of TBR TBR max is OFFFFh for 16 bit configuration OOFFFh for 12 bit configuration OOSFFh for 10 bit configuration OOOFFh for 8 bit configuration 1 1 Up Down The timer counts up until the timer value is equal E 11 2 3 Clock Source Select and Divider to compare latch 0 and then it counts down to zero Note If TBCLO
118. 16 15 The Conversion Clock ADC10CLK 16 17 Sample and Conversion Basic Signal Timing ADC10OSC Selected for museo ahd ah net ahaa up e d Dx cs rand DA Ute 16 18 Sample and Conversion Basic Signal Timing SMCLK Selected for ADCAOGLEK REDDE e EE d 16 18 Synchronized Sample and Conversion Signal With Enable Conversion 16 19 Use of MSC Bit With Nonrepeated Modes 16 20 Use of MSC Bit With Repeated Modes 16 20 Equivalent CIFGUll eren besoins ur rete dub bereiten re acuti ded 16 21 The EC Concepts uem edet Bus nba ore e 16 27 xvii Contents 16 16 16 17 16 18 16 19 16 20 16 21 16 22 16 23 16 24 16 25 B 1 B 2 D RO N CC ED Cot GaGa ere ee ee Co xviii One Block Transfer 2 tis ee ee Pate dri deir reg tn a tae 16 29 State Diagram for Data Transfer Control in One Block Transfer Mode 16 31 Two Block 16 32 State Diagram for Data Transfer Control in Two Block Transfer Mode 16 34 Detail Block Diagram of the Internal
119. 5 1 USART Control Register 13 16 13 5 2 Transmit Control Register UOTCTL 13 17 13 5 3 Receive Control Register UORCTL 13 18 13 5 4 Baud Rate Select and Modulation Control Registers 13 19 13 5 5 Receive Data Buffer UURXBUF U1RXBUF 13 19 13 5 6 Transmit Data Buffer UOTXBUF U1TXBUF 13 20 14 Comparator A 2 5 iai on ee reuse en e el 14 1 14 1 Comparator A Overview 14 2 14 2 Comparator_A Description 14 3 14 2 1 Input Analog Switches 14 3 14 2 2 Input 14 3 14 2 8 The 14 3 14 2 4 The Output Filler 14 3 14 2 5 The Voltage Reference Generator 14 4 14 2 6 Comparator A Interrupt Circuitry 14 5 14 3 Comparator A Control Registers 14 6 14 3 1 Comparator A Control Register CACTL1 14 6 14 3 2 Comparator A Control Register CACTL2
120. 6 Register Byte Byte Register Operations Register Byte Operation High Byte Low Byte Register Memory Byte Register Operation High Byte Low Byte The two following examples describe the register byte and byte register operations Example Register Byte Operation Example Byte Register Operation R5 0A28Fh R6 0203h Mem 0203h 012h ADD B R5 0 R6 08Fh 012h OAth Mem 0203h OA1h C 0 Z 0 N 1 Low byte of register Addressed byte gt Addressed byte R5 01202h R6 0223h Mem 0223h 05 ADD B R 6 R5 05Fh 002h Low byte of R5 00061h Store into R5 High byte is 0 R5 00061h C 0 Z 0 N 0 Addressed byte Low byte of register gt Low byte of register zero to High byte Memory 4 7 RAM and Peripheral Organization i Se SS 3 Note Word Byte Operations Word byte or byte word operations on memory data are not supported Each register byte or byte register is performed as a byte operation ee 4 4 2 Peripheral Modules Address Allocation Some peripheral modules are accessible only with byte instructions while others are accessible only with word instructions The address space from 0100 to 01FFh is reserved for word modules and the address space from 00h to OFFh is reserved for byte modules Peripheral modules that are mapped into the word address space must be accessed using word instructions for example MOV R5 amp WDTCTL
121. 7 ADD 2 dst INCD B dst Increment destination i ADD B 2 dst SBC W dst Subtract carry from destination _ SUBC 0 dst SBC B dst Subtract carry from destination si i SUBC B 0 dst Logical Instructions INV W dst Invert destination 0FFFFh dst INV B dst Invert destination 2 XOR B 1 5 RLA W dst Rotate left arithmetically ADD dst dst RLA B dst Rotate left arithmetically E ADD B dst dst RLC W dst Rotate left through carry d ADDC dst dst RLC B dst Rotate left through carry i ADDC B dst dst Data Instructions use CLR W Clear destination MOV 0 dst CLR B Clear destination MOV B 0 dst CLRC Clear carry bit 0 BIC 1 SR CLRN Clear negative bit 0 4 SR CLRZ Clear zero bit 0 BIC 2 SR POP dst from stack MOV SP dst SETC Set carry bit 5 1 SR SETN Set negative bit 1 BIS 4 SR 1 SETZ Set zero bit BIS 2 SR 16 Bit CPU 5 04 Instruction Set Overview Table 5 20 Emulated Instructions Continued Mnemonic Description Status Bits Emulation V N 2 Data Instructions use continued TST W dst Test destination 0 is 0 dst TST B dst Test destination 0 li i CMPB 0 dst Program Flow Instructions BR dst MOV dst PC DINT Disable interrupt BIC 8 SR EINT Enable interrupt
122. ADC10 Data Transfer Control High Speed Conversion Support 16 8 4 DTC Transfer Cycle Time As mentioned before the DTC transfer requires one CPU MCLK cycle to perform the data transfer and the CPU is halted for that one clock cycle The complete DTC transfer actually requires three or four CPU clock cycles because of setup synchronization etc but the CPU is only interrupted for one clock cycle The complete DTC cycle time is dependent on the MSP430 operating mode and clock system setup the DTC logic requires one or two clock cycles to synchronize one clock cycle to perform the transfer while the CPU is halted and one clock cycle of wait time In addition the DTC uses the DCOCLK so if the CPU is in a low power mode the maximum wake time for the DCOCLK lt 6 us see device data sheet also adds to the DTC cycle time Table 16 3 shows the maximum DTC cycle time for all the possible operating modes Table 16 3 DTC Cycle Time Maximum DTC Cycle Time CPU Operating Mode t DTCmax t The additional 6 us are needed to start the DCOCLK It is the parameter in the data sheet Users should refer to Table 16 3 and to the ADC10 settings to assure that the maximum DTC cycle time is allowed for between conversions The maximum cycle time required to complete one data transfer must be less than the shortest time between successive ADC10 conversions t DTCmax lt t ADC10period The general formula to
123. ADC10 is especially useful in digital signal processing applications that require high conversion throughput such as glass breakage sensors motion detectors signal prediction e g electronic fuses high quali ty voice processing etc The DTC concept is illustrated in Figure 16 15 Figure 16 15 The DTC Concept RAM Flash n th transferred data Address 2 2 n 1 th transferred data Address m 2n 4 ADC10 Peripheral DTC transfers data to any ADC10MEM Conversion Result address without SW resource 2nd transferred data Address 2 1st transferred data Address m ADC10 E Data Transfer Control High Speed Conversion Support Some applications may require the use of the DTC logic Others may simply employ it for convenience To determine if the use of DTC logic is required for an application users should calculate the maximum conversion rate through put required for the application An example of how to do this follows The example is based on the following assumptions and definitions The system clock period is 200 ns MCLK 5 MHz The maximum allowable CPU load for ADC conversion handling is 4 Lj Nis the number of clock cycles needed to transfer the conversion result to RAM using software The formula to calculate the maximum conversion rate is CRate CPULoad N x tycLK x 100 Example Interrupt handler without D
124. Address It Follows Idle Period of 10 Bits or More Idle Period Less Than 10 Bits USART Peripheral Interface UART Mode 12 7 Asynchronous Operation When two stop bits are used for the idle line as shown in Figure 12 8 the second one is counted as the first mark bit of the idle period The first character received after an idle period is an address character The RXWake bit can be used as an address tag for the character In the idle line multiprocessor format the RXWake bit is set when a received character is an address character and is transferred into the receive buffer Figure 12 8 USART Receiver Idle Detect Example One Stop Bit 4 10 Bit Idle Period gt Mark XXXX SP ST XXXXXXX Space Example Two Stop Bits 10 Bit Idle Period Mark XXXX SP SP ST XXXXXXX Space SP Stop Bit ST Start Bit Normally if the USART URXWIE bit is set in the receive control register characters are assembled as usual by the receiver They are not however transferred to the receiver buffer UXRXBUF nor are interrupts generated When an address character is received the receiver is temporarily activated to transfer the character to UxRXBUF and to set the URXIFG interrupt flag Applicable error status flags are set The application software can validate the received address If there is a match the application software further processes the data and executes the operation If there is no match the processor waits for the
125. CCTL5 Read write 18Ch POR reset Capture compare 5 CCR5 Read write 19Ch POR reset Capture compare 6 CCTL6 Read write 18Eh POR reset Capture compare 6 CCR6 Read write 19Eh POR reset Interrupt vector TBIV Read 11Eh POR reset 11 6 1 Timer B Control Register TBCTL The timer and timer operation control bits are located in the timer control register TBCTL shown in Figure 11 27 All control bits are reset automatically by the POR signal but are not affected by the PUC signal The control register must be accessed using word instructions Figure 11 27 Timer B Control Register TBCTL TBCTL 180h E TBCL Input Select Input Divider rw rw rw rw rw rw rw rw rw rw rw rw Ww rw rw 0 0 0 0 0 0 0 o o 0 0 0 0 0 0 0 Bit 0 TBIFG This flag indicates a timer overflow event Up mode TBIFG is set if the timer counts from TBCLO value to 0000h Continuous mode is set if the timer counts from TBR max to 0000h Up down mode TBIFG is set if the timer counts down from 0001h to 0000h Bit 1 Timer overflow interrupt enable TBIE bit An interrupt request from the timer overflow bit is enabled if this bit is set and is disabled if reset Timer_B 11 29 Timer B Registers Bit 2 Timer clear CLR bit The timer and input divider are reset with the POR signal or if bit CLR is set The CLR bit is automatically reset and is always read as zero The timer starts in the upward
126. Cap com control CCTL2 0186h Cap com control CCTL1 0184h Cap com control CCTLO 0182h Timer B control TACTL 0180h N d Sl Ay LAUA LAUA Ou pu Mod51 o oO t Registers are reserved on devices with Timer B3 Ou um rw um rw rw um rw A rw 2 0 rw rw Em Ou Ou Ou Ou Ou Ou a ato to ote am ot a ato to ote ao ot o ato to oe am ot ETESEAESE a ato fo ee am 529 121 mM rw 529 us oos rw Sos os rw coms 225 s ov rw cs cs cre rw cen Sm rw coms Sm ow Tu a frs Peripheral File Map A47 Timer B Registers Word Access A 15 Timer B Registers Word Access Continued Bit 4 15 14 13 12 11 10 9 8 Timer B interrupt vector 0 0 0 0 0 0 0 0 TBIV 11Eh ro ro ro ro ro ro ro ro Bit 4 2 1 0 7 6 5 4 3 Timer B interrupt vector 0 0 0 0 TBIV 0 TBIV 11Eh ro ro ro ro r 0 r 0 r 0 ro TBIV Vector Timer B5 five capture compare blocks integrated 0 Nointerrupt pending 2 CCIFG1 flag set interrupt flag of capture compare block 1 4 CCIFG2 flag set interrupt flag of capture compare block 2 CCIFG1 0 6 CCIFG3 flag set interrupt flag of capture compare block 3 CCIFG1 CCIFG2 0 8 CCIFGA flag set interrupt flag o
127. Capture Compare Blocks 11 15 The terere E 11 21 11 6 Timer B Registers 222770270000 2220770 11 27 Introduction 11 1 Introduction Timer B is an extremely versatile timer made up of 16 bit counter with 4 operating modes and four selectable lengths 8 bit 10 bit 12 bit or 16 bit Selectable and configurable clock source Up to seven independently configurable capture compare registers with configurable inputs and double buffered compare registers Up to seven individually configurable output modules with eight output modes Timer B can support multiple simultaneous timings multiple capture compares multiple output waveforms such as PWM signals and any combination of these In addition with the double buffering of compare data multiple PWM periods can be updated simultaneously Additionally Timer B has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers on captures or compares Each capture compare block is individually configurable and can produce interrupts on compares or on rising falling or both edges of an external capture signal The block diagram of Timer B is shown in Figure 11 1 11 1 1 Similarities and Differences From Timer A Timer Bis almost identical to Timer A except for a few enhancements noted below and operates iden
128. DIVA 1 2 DIVA 2 4 DIVA 3 8 BCSCTL1 057h rw 0 rw 1 rw 0 rw 0 Basic Clock Module Control Registers Bite XTS The LFXT1 oscillator operates with a low frequency clock crystal or with a high frequency crystal XTS 0 The low frequency oscillator is selected XTS 1 The high frequency oscillator is selected The oscillator selection must meet the external crystal s operating condition Bit7 XT2Off The XT2 oscillator is switched on or off XT2Off 0 the oscillator is on XT2Off 1 the oscillator is off if it is not used for MCLK or SMCLK BCSCTL2 is affected by a valid PUC or POR condition BCSCTL2 058h rw 0 rw 0 0 rw 0 0 rw 0 rw 0 rw 0 Bito DCOR The DCOR bit selects the resistor for injecting current into the dc generator Based on this current the oscillator operates if activated DCOR 0 Internal resistor on the oscillator can operate The fail safe mode is on DCOR 1 Internal resistor off the current must be injected externally if the DCO output drives any clock using the DCOCLK Bit1 Bit2 The selected source for SMCLK is divided by DIVS 1 DIVS 0 DIVS 20 1 DIVS 1 2 DIVS 2 4 DIVS 3 8 Bit3 SELS Selects the source for generating SMCLK SELS 0 Use the DCOCLK SELS 1 Use the XT2CLK signal in three oscillator systems or LFXT1CLK signal in two oscillator systems Bit4 Bit5 The selected source for MCLK is divided by DIVM O DIVM 1
129. DIVM 0 1 DIVM 1 2 DIVM 22 4 DIVM 3 8 Bit6 Bit7 Selects the source for generating MCLK SELM 0 SELM 1 SELM 0 Use the DCOCLK SELM 1 Use the DCOCLK SELM 2 Use the XT2CLK x13x and x14x devices or Use the LFXT1CLK x11xx and x12xx devices SELM 3 Use the LFXT1CLK Basic Clock Module 7 19 Basic Clock Module Control Registers 7 5 3 Special Function Register Bits 7 20 The Basic Clock Module affects two bits in the special function registers OFIFG and OFIE The oscillator fault interrupt enable bit OFIE is located in bit 1 of the interrupt enable register IE1 The oscillator fault interrupt flag bit OFIFG is located in bit 1 of the interrupt flag register IFG1 IE1 7 6 5 4 3 2 1 0 oh 1 1 EN rw 0 IFG1 7 6 5 4 3 2 1 0 oh 1 rw 1 The oscillator fault signal XT_OscFault sets the OFIFG as long as the oscillator fault condition is active The detection and effect of the oscillator fault condition is described in section 7 4 1 The oscillator fault interrupt requests a nonmaskable interrupt if the OFIE bit is set The oscillator interrupt enable bit is reset automatically if a non maskable interrupt is accepted The initial state ofthe OFIE bitis reset and no oscillator fault requests an interrupt even if a fault condition occurs Chapter 8 Digital Configuration This chapter describes the digital I O configuration Topic Page Introduction 222222
130. E RR 1 4 1 6 12x2 DeviCes epe rg 1 4 TTOXDOVICOS or moo RP o eeu 1 5 18 TAX Devices Loos cepe P ERPUCtRS aie DOT CREDO eU VES pred ES 1 5 Architectural Overview 2 1 2 1 Introduction 2 2 2 2 Central Processing Unit 2 2 2 3 Program Memory 2 3 2 4 Data Memory rs CRISE ete e e es 2 3 2 5 Operation Gontrol 2 3 2 6 lt ea etd Radia eR ERR ER EAR RE 2 4 2 7 Oscillator and Clock Generator 2 4 System Resets Interrupts and Operating Modes 3 1 3 1 System Reset and Initialization 3 2 SEAT dntrod ctlOn se eee ege reme 3 2 3 1 2 Device Initialization After System Reset 3 4 3 2 Global Interrupt Structure 3 5 3 3 MSP430 Interrupt Priority Scheme 3 6 3 31 Operation of Global Interrupt Reset NMI 3 8 3 3 2 Operation of Global Interrupt Oscillator Fault Control 3 9 3 4
131. EDE amp TONI Source address EDE OF016h dest address TONI 01114h Before After Address Register Address Register Space Space Oxxxxh PC OFF16h 01114h OFF16h 01114h OFF14h 0 016 OFF14h 0 016 OFF12h 04292h PC OFF12h 04292h OF016h 0A123h 0 016 0A123h 01114h 01234h 01114h 0A123h This address mode is mainly for hardware peripheral modules that are located at an absolute fixed address These are addressed with absolute mode to ensure software transportability for example position independent code 16 Bit CPU E Addressing Modes 5 2 5 Indirect Mode The indirect mode is described in table 5 9 Table 5 9 Indirect Mode Description Assembler Code Content of ROM MOV R10 0 R11 MOV R10 0 R11 Length One or two words Operation Move the contents of the source address contents of R10 to the destination address contents of R11 The registers are not modified Comment Valid only for source operand The substitute for destination operand is 0 Rd Example MOV B R10 0 R11 Before After Address Register Address Register Space Space Oxxxxh Oxxxxh PC OFF16h OFF 14h OFF12h 0000h R10 OFA33h OFF16h 0000h 10 OFA33h O4AEBh PC R11 002A7h OFF14h O4AEBh 11 002A7h OFA34h Oxxxxh OFA34h OFA32h 05BC1h OFA32h 05BC1h 002A8h 002A7h 002A6h 002A8h 002A7h 002A6h 5 12 Indirect Autoincrement Mode Addressing Modes The indirect autoincrement
132. EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 0083h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 0 0 0 0 0 0 0 0 0 2 p p p z pone 0 0 ADC12MCTL2t EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 0082h rw 0 rw rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTL1f EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 0081h rw 0 rw rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTLOf EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 0080h rw 0 rw rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 T All bits of ADC12MCTLx registers are only modifiable when 0 8 12 Registers Byte and Word Access 9 ADC12 Registers Byte and Word Access Continued Bit 15 14 12 1 11 0 ADC12MEM 15 Unused Unused Unused Unused MSB Conversion Result LSB 015Eh ro ro ro All conversion result bits of type rw ADC12MEM14 Unused Unused Unused Unused MSB Conversion Result LSB 015Ch ro ro ro All conversion result bits of type rw ADC12MEM13 Unused Unused Unused Unused MSB Conversion Result LSB 015Ah ro r ro conversion result bits of type rw 3 0 0 0 0 ADC12MEM 12 Unused Unused Unused Unused MSB Conversion R
133. MSP430 as Slave Three Pin PUC Mode USPIIE 0 No Clock at UCLK Not Completed Idle State Receive Enabled Receiver Collects Character USPIIE 1 External Clock Present Receive Disable Handle Interrupt Conditions Character USPIIE 1 Received USPIIE 0 Note USPIIE Reenabled SPI Mode After the receiver is completely disabled a reenabling of the receiver is asyn chronous to any data stream on the communication line Synchronization to the data stream is handled by the software protocol in three pin SPI mode 13 4 1 3 Receive Transmit Enable Bit MSP430 as Slave Four Pin Mode 18 10 In the four pin mode shown in Figure 13 9 the external SPI receive control signal applied to pin STE stops a started receive operation A PUC signal a software reset SWRST or a receive transmit enable USPIIE can stop a receive operation and reset the operation control state machine Whenever the STE signal is set to high the receive operation is halted Interrupt and Control Functions Figure 13 9 State Diagram of Receive Enable MSP430 as Slave Four Pin Mode No Clock at UCLK USPIIE 0 Not Completed USPIIE 1 USPIIE 1 ana STEA Idle State PIIE 1 Receiver Receive US Handle Interrupt Disabl Receiv
134. NMI Test Vpp Test TDO TDI TMS TCK Potential DVcc DVss Open Open DVss DVss DVss DVss Open Open DVcc or Vcc DVss DVss Open Open Open Open System Resets Interrupts and Operating Modes Comment 13x and 14x devices 13x and 14x devices Unused ports switched to port function and output direction Pullup resistor 100k 11x devices 11x1 devices 3 29 3 30 Chapter 4 Memory MSP430 devices are configured as a von Neumann architecture It has code memory data memory and peripherals in one address space As a result the same instructions are used for code data or peripheral accesses Also code may be executed from RAM Topic Page Introductiongd Tete eese 4 2 4 2 Data in the Memory 5514721211121 7010 4 3 4 3 Internal ROM Organization 4 4 4 4 Peripheral Organization 4 6 4 1 Introduction 4 1 Introduction All of the physically separated memory areas ROM RAM SFRs and peripheral modules are mapped into the common address space as shown in Figure 4 1 for the MSP430 family The addressable memory space is 64KB Future expansion is possible Figure 4 1 Memory Map of Basic Address Space Address Function Access Hex OFFFFh Interrupt Vector Table ROM Word Byte OFFEOh OFFDFh Program Memory Branch Control Tables ROM Word Byte Dat
135. Port 6 Registers Register Short Form Address Register Type Initial State Input 018h Read ony P4IN 01Ch Read ony 030h Read ony P6IN 034h Read ony Output P3OUT 019h Read write Unchanged PAOUT 01Dh Read write Unchanged P5OUT 031 Read write Unchanged P6OUT 035h Read write Unchanged Direction P3DIR 01Ah Read write Reset P4DIR 01Eh Read write Reset P5DIR 032h Read write Reset P6DIR 036h Read write Reset Port Select P3SEL 01Bh Read write Reset P4SEL 01Fh Read write Reset P5SEL 033h Read write Reset P6SEL 037h Read write Reset 8 3 1 1 Input Registers The input registers are read only registers that reflect the signal at the I O pins SS Sh Fo Chs T 4 Note Writing to Read Only Register Any attempt to write to these read only registers results in an increased current consumption while the write attempt is active 8 3 1 2 Output Registers The output registers show the information of the output buffers The output buffers can be modified by all instructions that write to a destination If read the contents of the output buffer are independent of the pin direction A direction change does not modify the output buffer contents 8 3 1 3 Direction Registers The direction registers contain eight independent bits that define the direction of each I O pin All bits are reset by the PUC signal When Bit 0 The port
136. R2 used as a source or destination register can be used in the register mode only The remaining combinations of addressing mode bits are used to support absolute address modes and bit processing without any additional code Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act like source only registers 16 Bit CPU 55 CPU Registers 5 6 The RISC instruction set ofthe MSP430 has only 27 instructions However the constant generator allows the MSP430 assembler to support 24 additional emulated instructions For example the single operand instruction CLR dst is emulated by the double operand instruction with the same length MOV R3 dst or the equivalent MOV 0 dst where 0 is replaced by the assembler and R3 is used with As 00 which results in LJ One word instruction No additional control operation or hardware within the CPU Lj Register addressing mode for source no additional fetch cycle for the constant 0 5 2 Addressing Modes Addressing Modes All seven addressing modes for the source operand and all four addressing modes for the destination operand can address the complete address space The bit numbers in Table 5 4 describe the contents of the As and Ad mode bits See Section 5 3 for a description of the source address As and the destination address Ad bits Table 5 4 Source Destination Operand Addressing Modes As Ad 00 0 01 1 01 1 01 1 10
137. Read write 01A4h Reset with POR ADC interrupt enable register ADC12IE Read write 01A6h Reset with POR ADC interrupt vector word ADC12IV Read 01A8h Reset with POR ADC memory 0 ADC12MEMO 0140h to Read Unchanged ADC memory 15 ADC12MEM15 015Eh ADC memory control 0 ADC12MCTLO 080h to Read Reset with POR ADC memory control 15 ADC12MCTL15 08Fh Note All registers may bea 15 30 ccessed by any instruction subject to register access restrictions ADC12 Control Registers 15 8 1 Control Registers ADC12CTLO and ADC12CTL1 ADC12CTLO 01A0h ADC12SC ENC control bits of ADC12CTLx are reset during POR Most of the control bits in registers ADC12CTLO ADC12CTL1 and ADC12MCTLx can only be modified if ENC is reset These bits are marked Ll All other bits can be modified at any time The control bits of control register ADC12CTLO ADC12CTL1 are 8 7 0 rw 0 bito REF 12 ADC12 ADC12 ADC12 2 5V rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Sample and convert The ADC12SC bit can be used to control the conversion with software if ENC is set It is recommended to ISSH 0 If the sampling signal SAMPCON is generated by the sampling timer SHP 1 changing the ADC12SC bit from 0 to 1 starts the sample and conversion operation When the A D conversion is complete BUSY 0 the ADC12SC bit is automatically reset If the sample signal is
138. Receive Data Buffer Characters URXEIE URXWIE Load UxRXBUF With PE FE BRK 0 1 Error free address characters 0 0 0 1 1 All address characters X X X 0 0 Error free characters 0 0 0 1 0 All characters X X X 12 5 6 Transmit Data Buffer UOTXBUF UTTXBUF The transmit data buffer shown in Figure 12 22 contains current data to be transmitted Figure 12 22 Transmit Data Buffer UOTXBUF UTTXBUF 7 0 UOTXBUF 077h wares Te Te Te T4 T4 T rw rw rw rw rw rw rw rw The UTXIFG flag indicates that the UxTXBUF buffer is ready to accept another character for transmission The transmission is initialized by writing data to UXTXBUF The data is moved to transmit shift register and transmission is started on the next bit clock after the transmit shift register is empty and UTXBUF is loaded qr UA Note Writing to UXTXBUF Writing data to the transmit data buffer must only be done if buffer UXTXBUF is empty otherwise an unpredictable character can be transmitted 12 22 Utilizing Features of Low Power Modes 12 6 Utilizing Features of Low Power Modes There are several functions or features of the USART that supportthe ultralow power architecture of the MSP430 These include Lj Support system start up from any processor mode by
139. Receive Start Timing Using URXS Flag Start Bit Accepted 12 24 Receive Start Timing Using URXS Flag Start Bit Not Accepted 12 24 Receive Start Timing Using URXS Flag Glitch Suppression 12 24 MSP430 Transmit Bit Timing 12 27 MSP430 Transmit Bit Timing Errors 12 27 Synchronization ETFOE cene metn hates adven Y vede as 12 30 Block Diagram of USART 13 2 Block Diagram of USART SPI Mode 13 3 MSP430 USART as Master External Device With SPI as Slave 13 5 Serial Synchronous Data Transfer 13 6 Data Transfer Cycle 13 6 MSP430 USART as Slave Three Pin or Four Pin Configuration 13 7 State Diagram of Receiver Enable Operation MSP430 as Master 13 10 State Diagram of Receive Transmit Enable MSP430 as Slave Three Pin Mode 13 10 State Diagram of Receive Enable MSP430 as Slave Four Pin Mode 13 11 State Diagram of Transmit Enable MSP430 as Master 13 11 State Diagram of Transmit Enable MSP430 as Slave 13 12 Receive Interrupt Operation
140. SCG1 SCGO OscOff CPUOff LPMO 0 0 0 1 LPM1 0 1 0 1 LPM2 1 0 0 1 LPMS 1 1 0 1 LPM4 1 1 1 1 These modes are illustrated in Figure 3 11 Figure 3 10 MSP430x1xx Operating Modes For Basic Clock System RST NMI Reset Active WDT Active Time Expired Overflow WDTIFG 0 WDTIFG 1 RST NMI i WDTIFG 1 ST is Reset Pin WDT Active Security Key Violation WDT is Active CPUOff 1 SCGO 1 0 LP Mode LPMO CPU Off MCLK Off SMCLK ACLK On RST NMI NMI Active CPUOff 1 OscOff 1 890 1 1 LP Mode LPM4 CPU Off MCLK Off DCO Off ACLK Off Active Mode CPU Is Active Various Modules Are Active CPUOff 1 SCGO 1 SCG1 0 LP Mode LPM1 CPU Off MCLK Off SMCLK ACLK On DC Generator Off CPUOff 1 SCG0 0 SCG0 1 1 SCG1 1 LP Mode LPM3 CPU Off MCLK Off SMCLK Off DCO Off ACLK On DC Generator Off LP Mode LPM2 CPU Off MCLK Off SMCLK Off DCO Off ACLK On DC Generator Off if DCO not used in active mode 3 26 Operating Modes Figure 3 11 Typical Current Consumption of 13x and 14x Devices vs Operating Modes 315 270 225 180 135 90 45 0 LPMO LPM2 LPM3 LPM4 Operating Modes The low power modes 1 4 enable or disable the CPU and the clocks In addition to the CPU and clocks enabling or disabling specific peripherals may further reduc
141. Segment7 can be erased individually or as a group SegmentA and SegmentB can be erased individually or as a group with segments 0 to 7 The segment structure is described in the device s data sheet The information memory can be located directly below the main memory s address or at a different address but will be in the same module i M1 Note Flash memory modules may have different numbers of segments Segment are numbered from 0 up to n e g segment 0 to segment n Flash Memory Data Structure and Operation Figure C 4 Segments in Flash Memory Module 4K Byte Example Flash Memory Flash Memory One Module One Module 4Kbyte 256Byte Several Segments FFFFh FFFFh SegmentO 4 kbyte FEOOh Main Memory FCOOh Segment Segment2 Segment3 FOOOh 010FFh 256 Byte 01000h Flash Information Memory SegmentA SegmentB C 1 1 Why Is a Flash Memory Module Divided Into Several Segments Once a bit in flash memory has been programmed it cannot be erased without erasing a whole segment For this reason the MSP430 flash memory modules have been heavily segmented to allow erasing and reprogramming of smaller memory segments C 2 Flash Memory Data Structure and Operation The flash memory can be read and written programmed in bytes
142. Settling Time When the built in reference is turned on with the REFON bit the settling timing noted in the data sheet must be observed before starting a conversion Otherwise the results will be false until the reference settles Once all internal and external references have settled no additional settling time is required when selecting or changing the conversion range for each channel ADC10 TEE Analog Inputs and Multiplexer 16 3 Analog Inputs and Multiplexer 16 3 1 Analog Multiplexer One of eight external analog input channels two external analog inputs shared with reference voltage inputs and two internal signals can be selected by the analog multiplexer as the channel for conversion Channel selection is made using INCH bits in register ADC10CTL1 for single channel conversions When in a sequence mode the INCH bits select the first channel of the sequence The input multiplexer is break before make type shown in Figure 16 3 to reduce input to input noise injection resulting from channel switching The input multiplexer is also a T switch to minimize the coupling between channels Channels that are not selected are isolated from the A D and the intermediate node is connected to analog ground so that the stray capacitance is grounded to help eliminate crosstalk Figure 16 3 Analog Multiplexer Channel 16 6 100 Q ADC10CTL1 12 15 ESD protection Crosstalk can
143. Synchronize with MCLK DTC Write to ADC10SA operation 1 x MCLK cycle 2 Transfer data to Address AD AD AD 2 ADC10TB 0 and ADC10CT 1 ADC10TB 0 ADC10CT 0 ADC10 em Data Transfer Control High Speed Conversion Support 16 8 1 2 Two Block Transfer Mode The DTC is enabled if 0 The block mode is set with the ADC10TB bit If this bit is set the DTC is in two block mode In two block mode the address range of the first block begins with the value in the ADC10SA register and ends at SA 2n 2 where SA is the value of the ADC10SA register and n is the number of data in the block also the value of the ADC10DTC1 register The address range for the second block is SA 2n to SA 4n 2 The two block transfer is shown in Figure 16 18 Figure 16 18 Two Block Transfer 16 32 Start Address n word address locations 7 A A 55 word address locations Like in one block mode the firstloading of ADC10MEM starts the data transfer operation into block one The DTC transfers the ADC10MEM data buffer to the word at address pointer SA Then the address pointer is incremented by two and the internal transfer counter initially set to n is decremented by one This operation repeats with each loading of ADC10MEM until the transfer counter becomes zero At that point the first block is full the ADC10IFG flag is set and the ADC10B1 bit is set to indicate that block one is full
144. The design of the LFXT1 oscillator also supports high speed crystals or resonators when in HF mode XTS 1 The crystal or resonator connects to the terminals and requires external capacitors on both terminals These capacitors should be sized according to crystal or resonator specifications Figure 7 2 Principle of LFXT1 Oscillator XIN LFXT1CLK lt OscOff i 2 4 Z5 F 1 Oscillator LFXT1_OscFault Fault Detect lo 1 lo J 4 lt Low Power 74 LF Oscillator XTS 0 The OscOff bit in the status register is used to turn off LFXT1CLK if this signal does not source MCLK or SMCLK and XT2 Oscillators Figure 7 3 Off Signals for the LFXT1 Oscillator XTS OscOff gt gt LFoff CPUOff SELM 0 2 Z gt XT1 off XT2 Is an Internal Signal XT2 0 MSP430x11xx MSP430x12xx devices SCG1 XT2 1 MSP430F13x MSP430F 14x devices Oscillator Active Clock Signal Needed for MCLK Clock Signal Needed for SMCLK T Two oscillators SELM x 3 Three oscillators SELM x 3 and 2 LFXT1CLK is switched off for all other bit combinations 7 2 2 XT2 Oscillator A second oscillator XT2 is available in MSP430F13x and MSP430F 14x de vices XT2 sources XT2CLK and its characteristics are identical to LFXT1 in HF mode The XT2Off control bit disables the XT2 oscillator
145. Toggle EQUx toggles OUTx signal Reset EQUx resets OUTx PWM toggle set EQUx toggles OUTx EQUO sets OUTx PWM reset set EQUx resets OUTx EQUx sets OUTx Note OUTx signal updates with rising edge of timer clock for all modes except mode 0 Modes 2 3 6 7 not useful for output unit 0 Timer_A 10 19 Timer Modes 10 5 1 Output Unit Output Modes The output modes are defined by the OMx bits and are discussed below The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit O Output mode 0 Output mode The output signal OUTx is defined by the OUTx bit in control register CCTLx The OUTx signal updates immediately upon completion of writing the bit information Output mode 1 Set mode The output is set when the timer value becomes equal to capture compare data CCRx It remains set until a reset of the timer or until another output mode is selected that controls the output Output mode 2 PWM toggle reset mode The output is toggled when the timer value becomes equal to capture compare data CCRx It is reset when the timer value becomes equal to CCRO Output mode 3 PWM set reset mode The output is set when the timer value becomes equal to capture compare data CCRx It is reset when the timer value becomes equal to CCRO Output mode 4 Toggle mode The output is toggled when the timer value becomes equal to capture compa
146. UxBR Em 100 Where baud rate is the required baud rate BRCLK is the input frequency selected for UCLK ACLK or MCLK i for the start bit 1 for data bit DO and so on UxBR is the division factor in registers UXBR1 and UxBRO Example 12 4 Synchronization Error 2400 Baud The following data are assumed Baud rate 2400 BRCLK 32 768 Hz ACLK UxBR 13 since the ideal division factor is 13 67 m 6Bh m7 0 m6 1 m5 1 m4 0 3 1 m2 0 m1 1 and 0 1 The LSB m0 of the modulation register is used first Start bit Error Daud rare x 2x 1 6 0 x UxBR 0 0 1 x 100 2 54 Data bit DO Error Paud rate x 2x 1 6 1 x UxBR 1 1 100 5 08 baud rate y tox 6 2 UxBR 1 1 2 en Data bit D1 Error 96 BROLK x 100 0 29 baud rate 6 3 UxBR 2 1 3 9 Data bit D2 Error 96 BRGLK x 100 2 838 baud rate y ox 1 6 4 UxBR 2 1 4 Data bit D3 Error x 100 1 95 baud rate 2x 1 6 5 x UxBR 3 1 5 Data bit D4 Error 96 BRGLK x 100 0 59 Data bit D5 Error 96 x 9 5 1 66 baud rate E x 2x 1 6 8 x UxBR 5 1 8 Data bit D7 Error x 100 0 88 baud rate BROlK 2x 1 6 9 x UxBR 6 1 9 baud rate 6 10 x UxBR 6 1 Parity bit Erro
147. XOR 5 8 86 1 EDE MOV RS5 EDE 1 amp EDE XOR QR5 amp EDE 11 Rn 0 Rm 2 ADD R5 R6 0 PC 3 BR 9 11 N 0 Rm 2 MOV 20 R9 0 PC 3 BR 2 11 Rn 1 x Rm 5 MOV 9 2 4 11 N 1 EDE 11 Rn 1 amp EDE 11 N ADD 33 EDE MOV R9 amp EDE ADD 33 amp EDE MNNNINNNIJ Table 5 13 shows a simple way to determine CPU instruction cycles for Format l double operand instructions Table 5 13 Execution Cycles for Double Operand Instructions Destination Addressing Mode x Rm Symbolic Source Addressing Mode Absolute amp Rn 4 Rn Rn N 5 x Rn Symbolic Absolute amp 6 t Add one cycle if Rm is the PC EXAMPLE the instruction ADD 500h 16 R5 needs 5 cycles for the execution 16 Bit CPU 5 15 Addressing Modes 5 2 8 2 Format ll Instructions Single Operand Table 5 14 describes the CPU format Il instructions and addressing modes Table 5 14 Instruction Format Ill and Addressing Modes No of Cycles RRA RRC Length of Address Mode SWPB PUSH Instruction A sid SXT CALL words Example 00 Rn 1 3 4 1 SWPB R5 01 X Rn 4 5 2 CALL 2 R7 01 EDE 4 5 2 PUSH EDE 01 amp EDE SXT amp EDE 10 Rn 3 4 1 RRC QR9 11 Rn 3 4 5 1 SWPB R10 see Note CALL 81H 11 N 2 Note Instruction Format Il Immediate Mode Do not use instructions RRA RRC SWPB and SXT with the immediate mode in the destination field Us
148. Y PC Y TONI PC EDE PC Move the contents of the source address EDE contents of PC X to the destination address TONI contents of PC Y The words after the instruction contain the differences between the PC and the source or destination addresses The assembler computes and inserts offsets X and Y automatically With symbolic mode the program counter PC is incremented automatically so that program execution continues with the next instruction Valid for source and destination MOV EDE TONI Address Register Space oso 14 0F102h 0A123h OFF16h 011FEh 01234h 01114h After OFF16h OFF14h OFF12h OF018h OF016h OF014h 01116h 01114h 01112h Address Space Oxxxxh PC Source address EDE OF016h dest address TONI 01114h Register Addressing Modes 5 2 4 Absolute Mode The absolute mode is described in Table 5 8 Table 5 8 Absolute Mode Description Assembler Code Content of ROM MOV amp EDE amp TONI MOV X 0 Y 0 X EDE Y Length Two or three words Operation Move the contents of the source address EDE to the destination address TONI The words after the instruction contain the absolute address of the source and destination addresses With absolute mode the PC is incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV amp
149. be reset Sample and conversion SAMPCOM signal can be reset and conversion started when appropriate and conversion started when appropriate 15 10 When the conversion is complete and the results are written to the selected conversion memory register the corresponding interrupt flag ADC12IFG x is set and if the appropriate interrupt enables are set an interrupt request is generated see the ADC12 Interrupt Vector Register 2 section When software is using the ADC12SC bit to initiate conversion successive conversions can be initiated by simply setting the ADC12SC bit the bit can remain set or may be set at the same time as ADC12SC However when any other trigger source is being used to start conversions the ENC bit must be toggled between each conversion All additional incoming sample input signals will be ignored until the ENC bit is reset and set again The conversion mode may be changed after the conversion begins but before ithas completed and the new mode will take effect after the current conversion has completed See also the Switching between Conversion Modes section An illustration of single channel single conversion mode is shown in Figure 15 5 Figure 15 5 Single Channel Single Conversion Mode CONSEQ 0 x CStartAdd Wait for Enable SAMPCON 4 p SAMPCON 1 95544 Sample Input Channel Defined in ot ADC12MCTLx SAMPCON
150. be set in time to indicate that a overflow situation occurred Software can detect it if it reads the conversion result and then tests for overflow condition The corresponding interrupt flag is reset if ADC12MEMx is accessed Warning Software Write to Register ADC12MEMx Typically software should not write to the conversion result registers ADC12MEMX If software writes to one of these registers while the ADC12 is attempting to write to the same register the data in the register will be unpredictable If software ensures that it is writing to a conversion result register that is not being accessed by the ADC12 then the write completes normally and the data is written correctly The associated interrupt flag is reset 15 8 3 Control Registers ADC12MCTLx Each conversion memory register ADC12MEMXx has its own control register ADC12CTLx The conversion memory registers hold the conversion results and the control register for each conversion memory register selects basic conversion conditions such as selecting the analog channel the reference voltage sources for and Vp_ and indicating the end of a sequence control bits in ADC12CTLx are reset during POR see Chapter 3 for POR details The control registers ADC12MCTL x can be modified only if the enable conversion control bit ENC is reset Any instruction that writes to an ADC12MCTL register while the ENC bit is set will have no effect ADC12 655 ADC12 Control Registers
151. bits according to the application needs After all software is processed the interrupt enable bits have to be set if another NMI event is to be accepted Setting the interrupt enable bits should be the last instruction before the return from interrupt instruction RETI If this rule is violated the stack can grow out of control while other NMI requests are already pending Setting the interrupt enable bits can be accomplished by using a bit set instruction BIS using immediate data or a mask The mask data can be modified anywhere via software for example in RAM this constitutes the nonmaskable interrupt processing C 4 2 Protecting One Flash Memory Module Systems From Corruption MSP430 configurations having one flash memory module use this module for program code and interrupt vectors When the flash memory module is in a Write erase or mass erase operation and the program accesses it an access violation occurs This violation will request an interrupt service but when the interrupt vector is read from the flash memory OSFFFh will be read independent of the data in the flash memory at the vector s memory location Flash Memory Interrupt and Security Key Violation To protect the software from this error situation all interrupt sources have to be disabled since all interrupt requests will fail The flash memory returns the vector OSFFFh Before the interrupt enable bits are modified they can be stored RAM to be restored when the
152. bits and the receive interrupt flag URXIFG Figure 13 21 Receive Data Buffer UORXBUF U1RXBUF 7 0 TT T2 T4 T2 T U1RXBUF 07Eh rw rw rw rw rw rw rw rw The MSB of the UxRXBUF is always reset in seven bit length mode USART Peripheral Interface SPI Mode Control and Status Registers 13 5 6 Transmit Data Buffer UOTXBUF UTTXBUF The transmit data buffer UXTXBUF shown in Figure 13 22 contains current data for the transmitter to transmit Figure 13 22 Transmit Data Buffer UOTXBUF UTTXBUF 13 20 7 7 0 UOTXBUF 077h s er ee P wager gt T2 rw rw rw rw rw rw rw rw The UTXIFG bit indicates that UXTXBUF is ready to accept another character for transmission In master mode the transmission is initialized by writing data to UxTXBUF The transmission of this data is started on the next bit clock if the transmit shift register is empty When seven bit character length is used the data moved into the transmit buffer must be left justified since the MSB is shifted out first 7 21 Note Writing to UXTXBUF Writing data to the transmit data buffer must only be done if buffer UXTXBUF is empty otherwise an unpredictable character can be transmitted 14 Comparator A The Comparator A peripheral module is used to compare analog signals to support various forms of analog to digital conversion
153. by comparing the thermistor s discharge time to that of a reference resistor See Figure 14 7 Figure 14 7 Temperature Measurement Systems Voc Voc OV Vcc R f 2 E CAON e g R eop E CAF Capture meas 0 Input of e 1 0 r limer 0 d sl T gt P2CA1 l E EM t 2yus 0 VcC 5 0 1 2 CAREF e CARSEL 5 L lo VCAREF 1 e 0 25x Vcc The resistive elements are compared using a capacitor charge discharge cycle as shown in Figure 14 8 This is based on a ratiometric conversion principle as the ratio of two capacitor discharge times is compared Absolute Vcc and the actual capacitor value are not critical as the ratiometric principle cancels these values out and the capacitor value should simply remain constant during the conversion V Rmeas X C x In ve Nmeas E CC N V rer R eX C X In va CC Nmeas _ Hmeas N R ref ref Nmeas Rmeas Pret X N ref Comparator A 14 11 Comparator A in Applications Figure 14 8 Timing for Temperature Measurement Systems Vc 0 25 x Vcc 14 12 Phase I Phase Il Phase Ill Phase IV t f suus M Charge Up Discharge C Charge Up Discharge e 4 trf meas gt MSP430 resources used to calculate the temperature sensed by R meas Digital 1 Two digital outputs to charge an
154. capture compare register to flag the user if a second capture is performed before data from the first capture was read successfully Bit COVx in register CCTLx is set when this occurs as shown in Figure 11 20 Figure 11 20 Capture Cycle Idle Capture Capture Read No Capture Read Capture E Capture Capture Capture Read and No Capture Capture Clear Bit COV in Register CCTL Second Capture Taken COV 1 Idle Timer_B 11 17 Timer Modes Overflow bit COVx is reset by the software as described in the following example Software example for the handling of captured data looking for overflow condition The data of the capture compare register CCRx are taken by the software and immediately with the next instruction the overflow bit is tested and a decision is made to proceed regularly or with an error handler CRx Int hand 3e Start of handler Interrupt MOV amp CCRx RAM Buffer BIT COV amp CCTLx JNZ Overflow_Hand correct capture data Overflow Hand BIC COV amp CCTLx reset capture overflow flag get back to lost synchronization Ne Ne Proceed RETI p e UOUAAX Note Capture With Timer Halted The capture should be disabled when the timer is halted The sequence to follow is stop the capture then stop the timer When the capture function is restarted the sequence shou
155. capture input signal with the timer clock 0 asynchronous capture 1 synchronous capture Input select CCISO and CCIS1 These two bits define the capture signal source These bits are not used in compare mode 0 Input CCIxA is selected 1 Input CCIxB is selected 2 GND 3 Vcc Timer A Registers Bits 14 15 Capture mode bits Table 10 8 describes the capture mode selections Table 10 8 Capture Compare Control Register Capture Mode Capture Mode Description 0 Disabled The capture mode is disabled 1 Positive Edge Capture is done with rising edge 2 Negative Edge Capture is done with falling edge 3 Both Edges Capture is done with both rising and falling edges Note Simultaneous Capture and Capture Mode Selection Captures must not be performed simultaneously with switching from compare to capture mode Otherwise the result in the capture compare register will be unpredictable The recommended instruction flow is 1 Modify the control register to switch from compare to capture 2 Capture For example BIS CAP amp CCTL2 Select capture with register CCR2 ZCCIS1 amp CCTL2 Software capture CCISO 0 Capture mode 3 LL 10 6 4 Timer A Interrupt Vector Register Two interrupt vectors are associated with the 16 bit Timer A module CCRO interrupt vect
156. clock ACLK is used 1 0 SMCLK System clock SMCLK 1 1 INCLK See device description in data sheet 11 30 10 Bits 11 12 Bits 13 14 Timer B Registers Unused Configure 16 bit timer TBR for 8 bit 10 bit 12 bit or 16 bit operation CNTL 0 16 bit length TBR max is OFFFFH CNTL 1 12 bit length TBR may is OFFFH CNTL 2 10 bit length TBR max is O3FFH CNTL 3 8 bit length TBR max is Load compare latches individually or in groups The load signal is controlled via the CLLDx bits located in the appropriate capture compare control register CCTLx TBCLGRP 0 load individually Load of the shadow registers is defined in each individual CCTLx register by bits CLLDx The CLLD bits in each CCTLx register define the operating mode for the shadow registers TBCLGRP 1 Three groups are selected TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 TBCL1 TBCL2 The CLLD bits in CCTL1 define the operating mode TBCL3 TBCL4 The CLLD bits in CCTL3 define the operating mode TBCL5 TBCL6 The CLLD bits in CCTL5 define the operating mode TBCLGRP 2 Two groups are selected TBCL1 TBCL2 TBCL4 TBCL5 TBCL6 TBCL1 TBCL2 TBCL3 The CLLD bits in CCTL1 define the operating mode TBCL4 TBCL5 TBCL6 The CLLD bits in CCTL4 define the operating mode TBCLGRP 3 One group is selected all TBCLx registers The CLLD bits in CCTL1 define the operating mode for all shadow reg
157. control for example when the clock source signal is lost Flash Memory C 9 Flash Memory Data Structure and Operation Note When the erase cycle is stopped before its normal completion by the hard ware the timing generator is stopped and erasure of the flash memory can be marginal An incomplete erasure can be verified But an erase level of 1 can be inconsistently read as valid when supply voltage temperature access time instruction execution data read and frequency vary C 2 6 Flash Memory Status During Write Programming The flash memory erase bit level is 1 Bits can only be written programmed to a 0 level Once a bit is programmed only the erase function can reset it back to the 1 level The byte or word 0 level can not be written programmed in one cycle Any bit can be programmed from 1 to 0 at any time but not from 0 to 1 Two slightly different write operations can be performed write a single byte or word of data or write a sequence of bytes or words A write sequence of bytes or words can be performed as multiple sequential or as a block write The block write is approximately twice as fast as a multiple sequential write algorithm The write program operation starts with the following sequence Setthe correct input clock frequency of the timing generator by selecting the clock source and predivider Reset the LOCK control bit if set Watch the BUSY bit Con
158. conversion Additionally If the appropriate interrupt enable flags are set an interrupt request is generated see the ADC12 Interrupt Vector Register ADC 12IV section An illustration of sequence of channels mode is shown in Figure 15 8 Figure 15 8 Sequence of Channels Mode CONSEQ 1 ADC120ON 1 4 x CStartAdd Wait for Enable SHS 0 and ENC 1 4 ADC12SC Wait for Trigger SAMPCON 47 1 Sample Input Channel Defined in ADC12MCTLx If x lt 15 thenx 2x amp 1 If x 15 thenx2x amp 1 else x 0 else x 0 SAMPCON lt 12 x ADC12CLK MSC 1 and Convert Use SHP 1 12 x ADC12CLK and EOS x20 1x ADC12CLK Conversion Completed Result Stored Into ADC12MEMXx ADC12IFG x is Set pointer to conversion memory register ADC12MEMO ADC12MEM15 conversion memory control register ADC12MCTLO ADC12MCTL15 15 14 Conversion Modes An example showing a sequence of conversions is shown and flow charted in Figures 15 9 and 15 10 The example shows the sequence a0 a5 a0 a0 a3 and uses ADC12MEM6 for storing the first conversion results The setup of each conversion in the sequence is O O O O O L a0 using reference voltages and Vp_ AVss a5 using reference voltages at VRef and Vp AVss using reference voltages Vp at
159. directly controlled by ADC12SC SHP 0 then the high level of the ADC12SC bit defines the sample time The conversion starts once it is reset All automatic sequence functions CONSEQ 1 2 3 and multiple sample and conversion functions MSC 1 are executed normally Therefore when using ADC12SC the software must ensure that the frequency of the timing of the ADC12SC bit meets the applicable timing requirements NOTE The start of a conversion by software SHS 0 in ADC12CTL1 is possible by setting both ENC and ADC12SC control bits within one instruction Enable conversion The software via ADC12SC or external signals can start a conversion only if the enable conversion bit ENC is high Most of the control bits in ADC12CTLO and ADC12CTL 1 and all bits in ADCMCTL x may be changed only if ENC is low 0 No conversion can be started This is the initial state 1 The first sample and conversion starts with the first rising edge of the SAMPCON signal The selected operation proceeds as long as ENC is set CONSEQ 0 ADC12BUSY 1 ENC 1 0 In this mode if ENC is reset the current conversion is immediately stopped The conversion results are unpredictable CONSEQx2zO0 ADC12BUSY x ENC 1 0 In these modes if ENC is reset the current conversion or sequence is completed and the conversion results are valid The conversion activities are stopped after the current conversion or sequence is completed ADC12 i531 ADC12 Control Regist
160. due to source impedance also apply to the output impedance of any external voltage reference source applied to The output impedance must be low enough to enable the transients to settle within 0 2 ADC10CLK and generate leakage current induced errors of 1 LSB See the Sampling section for more details on sample timing and sampling considerations 16 3 3 Using the Temperature Sensor To use the on chip temperature sensor the user simply selects the analog input channel to 10 Selecting the diode channel automatically turns on the on chip reference generator see Figure 16 1 as a voltage source for the temperature diode However itdoes not enable the output or affect the reference selections for the conversion so reference selections for the conversion are the same as with any other channel The conversion can start after the required settling time See the device data sheet for the temperature sensor specifications SS oS C EL RUE EA CUM Gu ot Note Offset Error of the Temperature Diode The offset error of the temperature diode can be large see the device data sheet and may require calibration to be used in an application ADC10 im Conversion Modes 16 4 Conversion Modes The ADC10 has four conversion modes Single channel single conversion 1 Single channel
161. edge This sequence provides false start bit rejection and also locates the center of the bits in the frame where the bits can be read on a majority basis The timing of X is 1 32 to 1 63 times that of the BRCLK depending on the division rate of the baud rate generator and provides complete coverage of at least two BRCLK periods Figure 12 4 shows an asynchronous bit format Figure 12 4 Asynchronous Bit Format Example for n or n 1 Clock Periods Falling Edge Majority Vote on UEXD Taken From Indicates Start bit URXD Data Line T n i n 1 2 3 n 2 x n 2 2 1 n n 1 1 2 P LFLPLPLPUT yg E aro YT IR Data Bit Period n or n 1 BRCLK Periods URXD L Data Period n or n 1 BRCLK Periods _ 12 4 Asynchronous Operation 12 3 2 Baud Rate Generation in Asynchronous Communication Format Baud rate generation in the MSP430 differs from other standard serial communication interface implementations 12 3 2 1 Typical Baud Rate Generation Typical baud rate generation uses a prescaler from any clock source and a fixed second clock divider that is usually divide by 16 Figure 12 5 shows a typical baud rate generation Figure 12 5 Typical Baud Rate Generation Other Than MSP430 0 7 0 7 UxBRO UxBR1 8 8 15 16 Bit P ler Divider Select Clock Source Clock1 Clockn BRSCLK Start H 1 2 83 4 5 6 7 8 9 1011 1
162. erase voltages and the flash memory itself Data and address are latched when execution of a write program or erase operation is in progress Figure C 5 Flash Memory Module Block Diagram Address Latch Data Latch Enable Address Latch Timing Generator Enable Data Latch Programming Voltage Generator C 2 3 Flash Memory Basic Operation The flash memory module normally works in read mode the address and data latch are transparent and the timing generator and programming voltage generator are off The flash memory module changes its mode of operation when data is written programmed to the module or when the flash memory or parts of it are erased In these situations flash control registers FCTL1 FCTL2 and FCTL3 need to be set up properly to ensure correct write or erase C 6 Flash Memory Data Structure and Operation operation Once these registers are set up and write or erase is started the timing generator controls the entire operation and applies all signals internally If the BUSY control signal is set it indicates that the timing generator is active and a write or erase cycle is active The block write mode also uses a second control bit WAIT There are three basic parts to a write or erase cycle preparation of program erase voltage control timing for the program or erase operation and the switch off sequence of the program erase voltage Once a write or erase function is starte
163. fgco 1 individually for each DCO cycle This is the highest possible rate that can be modulated between two discrete frequency steps The following example illustrates the main operation of the modulator Figure 7 13 Operation of the Modulator 7 12 Selected f3 f4 MOD 19 DCOCLK Error of tperiod Error of period Frequency Cycle Time Frequency Selected 1000 kHz 1000 ns 943 kHz 1060 ns 1042 kHz 960 ns fo fi fo fg f4 f5 fe f7 Modulation Period 1 0 ns 40 20 20 40 4 3 2 1 0 1 2 3 4 Digitally Controlled Oscillator The user should consider two factors when reviewing the timing accuracy gen erated from the DCOCLK signal Short term accuracy Each individual cycle is as inaccurate as the DCO steps Long term accuracy The accumulated average of many individual cycles reduces the relative error by less than 0 3396 assuming a step delta of 1096 and a modulation period of 32 Proper use of the modulation feature on the DCOCLK period increases the accuracy by averaging the periods The selected frequency set using the control bits in the DCO and the modulation fraction defined by the control bits in MOD sets the DCOCLK periods SF A Note Control of DCOCLK Frequency The frequency of the digitally controlled oscillator varies with temperature and voltage
164. for but not routed externally the average current consumed is lava IREF IREFB 10 X tsac tPeriod 16 9 2 3 Internal Reference is on and Routed Externally When the internal reference is on and routed externally to the pin REFON 1 REF Out 1 the REFBurst bit controls whether m The reference is continuously on REFBurst 0 or m The reference is on only during the sample and conversion period REFBurst 1 when the reference is used for SRef 1 5 16 42 Controlling the Current Consumption of the ADC10 Module Figure 16 23 ADC10 Current Consumption With Internal Reference On Routed Externally and 0 77 lAVG IREF lADC10 X tS amp C tPeriod Le A 7 Load VREF Sref 1 5 9 UR Pi ts amp c VREF tPeriod Sref 0 2 4 6 7 OV 4 The average current consumed by the ADC10 is lavG IREF lapcto X ts amp c tPeriod li external load current This is the highest current consumption scenario 16 9 2 4 Internal Reference is Selected on an External Pin With Burst Mode of VREF When the internal reference is on REFON 1 routed externally REF Out 1 and burst mode is selected REFBurst 1 the reference buffer is on only during the sample and conversion period in conversions that use the reference Sref 1 5 In this case the reference voltage is externally
165. further interrupts because the GIE bit is reset after entering the interrupt service routine Typically a multiplication operation that uses the entire data process occurs outside an interrupt routine and the interrupt routines are as short as possible A multiplication operation in an interrupt routine has some feedback to the multiplication operation in the main routine Interrupt Following an OP1 Transfer The two LSBs of the first operand address define the type of multiplication operation This information cannot be recovered by any later operation Therefore an interrupt must not be accepted between the first two steps move operand OP1 and OP2 to the multiplier 6 5 2 2 Interrupt Following an OP2 Transfer After the first two steps the multiplication result is in the corresponding registers RESLO RESHI and SUMEXT It can be saved on the stack using the PUSH instruction and can be restored after completing another multiplication operation using the POP instruction However this operation takes additional code and cycles in the interrupt routine You can avoid this by making an entire multiplication routine uninterruptible by disabling any interrupt DINT before entering the multiplication routine and by enabling interrupts EINT after the multiplication routine is completed The negative aspect of this method is that the critical interrupt latency is increased drastically for events that occur during this period 6 5 2 3 Ge
166. if signal XT2CLK is not used for MCLK or SMCLK If the CPUOff bit is reset and SELM 2 XT2CLK sources The XT2CLK sources SMCLK if SCG1 is reset and SELS 1 Figure 7 4 Off Signals for Oscillator XT2 XT20ff CPUOff SELM 1 J 4 P XT2Off Internal signal SELM 0 SELS Comment Oscillator Active Clock Signal Needed for MCLK Clock Signal Needed for SMCLK T XT2CLK is switched off in all other bit combinations Basic Clock Module 7 5 LFXT1 and XT2 Oscillators 7 2 3 Oscillator Fault Detection An analog circuit controls the operation of oscillators LFXT1 and XT2 and flags an oscillator fault when crystal cycles are not present for approximately 50 us The active OSCFault signal sets the oscillator fault interrupt flag OFIFG and requests a non maskable interrupt when the oscillator fault interrupt enable bit OFIE is set User software must clear the OFIFG flag Figure 7 5 Oscillator Fault Interrupt XT1off XT OscFault LFXT1 OscFault NMIFG NMRS XT2off OFIFG XT2 OscFault e gt IFG1 1 OFIE 1 1 1 Clear Oscillator Fault NMI RSS SSS Sen Tee al ae 25 15 1602 E XUL I ee a Oe Ee 71 XTS SELM 1 i XSELM 1 le SELM 0 e ys
167. in a table pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 with autoincrement BR X R5 Branch to the address contained in the address pointed to by R5 X e g table with address starting at X X can be an address or a label Core instruction MOV X R5 PC Indirect indirect R5 X CALL Syntax Operation Description Status Bits Example Instruction Set Overview Subroutine CALL dst dst tmp dst is evaluated and stored SP 2 SP PC SP PC updated to TOS tmp PC dst saved to PC A subroutine call is made to an address anywhere in the 64K address space All addressing modes can be used The return address the address of the following instruction is stored on the stack The call instruction is a word instruction Status bits are not affected Examples for all addressing modes are given CALL CALL CALL CALL CALL CALL CALL EXEC Callonlabel EXEC or immediate address e g 0A4h SP 2 5 SP 2 5 PC EXEC Call on the address contained in EXEC SP 2 2 SP PC 2 2 SP X PC gt PC Indirect address amp EXEC Call on the address contained in absolute address EXEC SP 2 2 SP PC 2 5 SP X PC PC Indirect address R5 Call on the address contained in R5 SP 2 gt SP 2 5 SP R5 5 PC Indirect R5 R5 Call on the address contained in the word pointed to by R5 SP 2 SP 2 gt S
168. in the SFRs The appropriate time interval is selected by setting bits SSEL ISO and IS1 accordingly Setting WDTCTL register bit TMSEL to 1 selects the timer mode This mode provides periodic interrupts at the selected time interval A time interval can also be initiated by writing a 1 to bit CNTCL in the WDTCTL register When the WDT is configured to operate in timer mode the WDTIFG flag is set after the selected time interval and it requests a standard interrupt service The WDT interrupt flag is a single source interrupt flag and is automatically reset when it is serviced The enable bit remains unchanged In interval timer mode the WDT interrupt enable bit and the GIE bit must be set to allow the WDT to request an interrupt The interrupt vector address in timer mode is different from that in watchdog mode RR Note Watchdog Timer Changing the Time Interval Changing the time interval without clearing the WDTCNT may result in an unexpected and immediate system reset or interrupt The time interval must be changed together with a counter clear command using a single instruction for example MOV 05A0Ah amp WDTCTL Changing the clock source during normal operation may result in an incorrect interval The timer should be halted before changing the clock source ee 9 1 3 3 Operation in Low Power Modes 9 6 The MSP430 devices have several low power modes Different clock signals are available in differ
169. is read The overflow flag must be reset with software It is not reset by reading the capture value The OUTx bit determines the value of the OUTx signal if the output mode is 0 Capture compare input signal CCIx The selected input signal CCIxA CCIxB Vcc or GND can be read by this bit See Figure 11 18 Interrupt enable CCIEx Enables or disables the interrupt request signal of capture compare block x Note that the GIE bit must also be set to enable the interrupt 0 Interrupt disabled 1 Interrupt enabled Output mode select bits Table 11 7 describes the output mode selections Timer B 11 33 Timer B Registers Table 11 8 Capture Compare Control Register Output Mode Vals Output Mode Description 0 Output only The OUTx signal reflects the value of the OUTx bit 1 Set EQUx sets OUTx 2 PWM EQUx toggles OUTx EQUO resets OUTx toggle reset 3 PWM set reset EQUx sets OUTx EQUO resets OUTx 4 Toggle EQUx toggles OUTx signal 5 Reset EQUx resets OUTx 6 PWM EQUx toggles OUTx EQUO sets OUTx toggle set 7 PWM reset set EQUx resets OUTx EQUO sets OUTx Note OUTx updates with rising edge of timer clock for all modes except mode 0 Modes 2 3 6 7 not useful for output unit 0 Bit 8 CAP sets capture or compare mode 0 Compare mode 1 Capture mode Bits 9 10 Select load source for compare latch TBCLx also see description of bits TBCLGRP 13 and 14 in TBCTL CLLD 0 Immediate CLLD 1 Load C
170. is set each time register ADC10MEM is loaded Additionally If the interrupt enable flag ADC10IE is set an interrupt request is generated When software is using the ADC10SC bit to initiate a sequence successive sequences can be initiated by simply setting the ADC10SC bit the ENC bit can remain set or may be set at the same time as ADC10SC However when other trigger source is being used to start a sequence the ENC bit must be toggled between each sequence All additional incoming sample input signals will be ignored until the ENC bit is reset and set again ADC10 ius Conversion Modes 16 10 The conversion mode may be changed after the conversion begins but before it has completed and the new mode will take effect after the current sequence has completed See also the Switching between Conversion Modes section If the conversion mode is changed after the sequence begins but before it has completed and the ENC bit is left high the sequence completes normally and the new mode takes effect after the sequence completes unless the new mode is single channel single conversion lf the new mode is single channel single conversion the current sequence of channels stops proceeding when no sample and conversion is active or after an active sample and conversion is completed The original sequence may not be completed but all completed conversion results are valid See also the Switching Between Conversion Modes section If the con
171. is switched off No power is consumed from the reference voltage generator 1 The internal reference voltage is switched The reference voltage generator consumes power When the reference generator is switched on the settling time of the reference voltage must be completed before the first sampling and conversion is started 2_5V bit6 Reference voltage level 0 The internal reference voltage is 1 5V if REFON 1 1 Theinternal reference voltage is 2 5V if REFON 1 MSC bit7 Multiple sample and conversion Valid only when the sample timer is selected to generate the SAMPCON signal SHP 1 and the A D mode is chosen as repeat single channel sequence of channel or repeat sequence of channels 5 0 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversion are performed automatically as soon as the prior conversion is completed without additional rising edges of SHI Additional rising edges of SHI are ignored until the sequence has completed or the ENC bit has been toggled depending on mode 15 32 ADC12 Control Registers SHTO bits Sample and hold TimeO These bits define the sample timing for 8 11 conversions whose results are stored in conversion memory registers ADC12MEMO to ADC12MEM7 The sample time is a multiple of the ADC12CLK x 4 tsample 4 X tADC1
172. k kv kx ko kk ok NOP MIN ONE CYCLES BETWEEN MOVING HE OPERAND2 TO HW MULTIPLIER AND PROCESSING THE RESULT WITH INDIRECT ADDRESS MODE ADD R5 amp RAM ADD LOW RESUL RA ADDC R5 amp RAM 2 ADD HIGH RESULT TO RAM 2 ADC amp RAM 4 ADD CARRY TO EXTENSION WORD ADC amp RAM 6 IF 64 BIT LENGTH IS USED POP R5 The previous example shows that the indirect or indirect autoincrement address modes when used to transfer the result of a multiplication operation to the destination need more cycles and code than the absolute address mode There is no need to access the hardware multiplier using the indirect addressing mode Hardware Multiplier 6 7 Hardware Multiplier Software Restrictions 6 5 2 Hardware Multiplier Software Restrictions Interrupt Routines 6 5 2 1 The entire multiplication routine requires only three steps 1 Moveoperand OP1 tothe hardware multiplier this defines the type of mul tiplication 2 Move operand OP2 to the hardware multiplier the multiplication starts 3 Process the result of the multiplication in the RESLO RESHI and SUMEXT registers The following considerations describe the main routines that use hardware multiplication If no hardware multiplication is used in the main routine multiplication in an interrupt routine is protected from
173. key is violated bit KEYV is set and a PUC is performed The KEYV bit can be used to determine the source that forced a start of the program at the reset vector s address The KEYV bitis not automatically reset and should reset by software Note Any key violation results PUC independent ofthe state ofthe KEYV bit To avoid endless software loops the flash memory control registers should not be written during a key violation service routine Note The software can set the KEYV bit A PUC is also performed if itis set by software ACCVIFG WAIT Lock bit2 012Ch bit3 012Ch bit4 Flash Memory Control Registers Access violation interrupt flag The access violation interrupt flag is set when the flash memory module is improperly accessed while a write or erase operation is active The violation situations are described in section C 2 When the access violation interrupt enable bit is set the interrupt service request is accepted and the program continues at the NMI interrupt vector address Reading the control registers will not set the ACCVIFG bit Note The proper interrupt enable bit ACCVIE is located in interrupt enable register IE1 of the special function register Software can set the ACCVIFG bit in this case an NMI is also executed Wait In the block write mode the WAIT bit indicates that the flash memory is ready to receive the next data for programming The WAIT bit is read only but a write to
174. levels and establish the upper and lower limits of the analog inputs to produce a full scale and zero scale reading respectively The values of Vn and the analog input should not exceed the positive supply or be lower than AVsg consistent with the absolute maximum ratings specified in the device data sheet The digital output is full scale when the input signal is equal to or higher than and zero when the input signal is equal to or lower than Vp ADC12 oe Analog Inputs Multiplexer Warning Reference Voltage Settling Time When the built in reference is turned on with the VREFON bit the settling timing noted in the data sheet must be observed before starting a conversion Otherwise the results will be false until the reference settles Once all internal and external references have settled no additional settling time is required when selecting or changing the conversion range for each channel 15 3 Analog Inputs and Multiplexer 15 3 1 Analog Multiplexer The eight external analog input channels and four internal signals are selected as the channel for conversion by the analog multiplexer Channel selection is made for each conversion memory register with the corresponding ADC12MCTLx register The input multiplexer is a break before make type shown in Figure 15 3 to reduce input to input noise injection resulting from channel switching The input multiplexer is also a T switch to minimize the
175. lost N Set if result is negative reset if positive 2 Set if dst contained 1 reset otherwise C Reset if dst contained 0 set otherwise V Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08000h otherwise reset Set if initial value of destination was 080h otherwise reset OscOff CPUOff and GIE are not affected Instruction Set Description B 25 Instruction Set Overview Example R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE 0FEh MOV EDE R6 MOV 255 R10 L 1 MOV B R6 TONI EDE 1 R6 DEC R10 JNZ L 1 Do not transfer tables using the routine above with the overlap shown in Figure 4 Figure B 4 Decrement Overlap EDE o TONI EDE 254 TONI 254 Example Memory byte at address LEO is decremented by one DEC B LEO Decrement MEM LEO Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE 0FEh MOV EDE R6 MOV B 255 LEO L 1 MOV B R6 TONI EDE 1 R6 DEC B LEO JNZ L 1 B 26 DECD W DECD B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example
176. next address character to arrive The URXWIE bit is not modified by the USART it must be modified manually to receive nonaddress or address characters In idle line multiprocessor format a precise idle period can be generated to create efficient address character identifiers The wake up temporary WUT flag is an internal flag and is double buffered with TXWake When the transmitter is loaded from UxTXBUF WUT is loaded from TXWake and the TXWake bit is reset as shown in Figure 12 9 Figure 12 9 Double Buffered WUT and TX Shift Register 12 8 TX Buffer UXTXBUF TX Shift Register TXWake Start Bit Parity Bit i TXSignal Asynchronous Operation The following procedure sends out an idle frame to identify an address character 1 Setthe TXWake bit and then write any word don t care to the UXTXBUF UTXIFG must be set When the transmitter shift register is empty the contents of UXTXBUF are shifted to the transmit shift register and the TXWake value is shifted to WUT 2 Set bit WUT which suppresses the start data and parity bits and transmits an idle period of exactly 11 bits as shown in Figure 12 10 The next data word shifted out of the serial port after the address character identifying idle period is the second word written to the UxTXBUF after the TXWake bit has been set The first data word written is suppressed while the address identifier is sent out and ignored thereafter Writing the f
177. not used As shown in Figure 15 20 the sampling period is active while SAMPCON is high Hold mode is active when SAMPCON is low The conversion starts with the falling edge of SAMPCON after a synchronization time tsync The conversion takes 13 x ADC12CLK tconyer Figure 15 20 Conversion Timing for Extended Sample Mode Sample Input Signal SAMPCON ADC12CLK 15 26 i sync The extended sample mode allows total control of the sampling period and the start of a conversion The extended sample mode is useful in applications that require an extended sampling period to accommodate different input source impedances or in applications where the maximum sampling period supplied by the internal sampling timer is insufficient An example of the extended sample mode configuration is shown in Figure 15 21 The selected input signal source is Timer B OUTO The timing for the example is shown in Figure 15 22 Figure 15 21 Sampling Extended Sample Mode Example Configuration Internal ADC12SSEL Oscillator ADC120N ADC12DIV m ADC120SC VR VR ADC12CLK Divide by 1 2 3 4 5 6 7 8 MCLK Analog Sample Input and 12 bit A D converter core SHTO SMCLK Signal Hold SHT1 SH SHP Sampling ADC12SC 44 SAMPCON olo Timer Timer A OUT1 4 Timer B OUTO SHI E Timer B OUT1 12 Bit SAR Conversion CTL
178. of implementing a UART function with the following features Automatic start bit detection even from ultralow power modes Hardware baud rate generation Hardware latching of RXD and TXD data Baud rates of 75 to 115 200 baud n n Full duplex operation This UART implementation is different from other microcontroller implementations where a UART may be implemented with general purpose and manual bit manipulation via software polling Those implementations require great CPU overhead and therefore increase power consumption and decrease the usability of the CPU The transmit feature uses one compare function to shift data through the output unit to the selected pin The baud rate is ensured by reconfiguring the compare data with each interrupt Timer A 10 33 Timer A UART The receive feature uses one capture compare function to shift pin data into memory through bit SCCIx The receive start time is recognized by capturing the timer data with the negative edge of the input signal The same capture compare block is then switched to compare mode and the receive bits are latched automatically with the EQUx signal The interrupt routine collects the bits for later software processing Figure 10 33 illustrates the UART implementation Figure 10 33 UART Implementation CCISx1 CCISxO Timer Bus 0 0 0
179. on chip DCO two crystal oscillators Watchdog Timer General Purpose Timer Timer_A3 16 bit timer with three capture compare registers and PWM output Timer_B7 16 bit timer with seven capture compare registers and PWM output Port1 2 8 I Os each all with interrupt Port3 4 5 6 Eight I Os each Comparator_A precision analog comparator ideal for slope A D conversion ADC12 12 bit A D USARTO USART1 Hardware Multiplier The 14x device family includes MSP430F 147 32KB 256B Flash 1KB RAM MSP430F 148 48KB 256B Flash 2KB RAM MSP430F 149 60KB 256B Flash 2KB RAM Introduction 1 5 Chapter 2 Architectural Overview This section describes the basic functions of an MSP430 based system The MSP430 devices contain the following main elements Central processing unit Lj Program memory Lj Data memory Operation control Lj Peripheral modules Oscillator and clock generator Topic Page 2 Iiintroductionss 20 2 2 2 200 2 2 2 32 Programi Memory e 2 3 2 a 250022227000 2 3 2 5 Operation Control sec isis cae Mee 22222222222 2 3 2 6 Peripherals 2 IUe SEI 2 4 2 7 Oscillator and Clock Generator 2 4 2 1 Introduction 2 1 Introduction The architecture of the MSP430 family is based on a memory to memory architecture a common address space for
180. or ADD W Src dst ADD B src dst src dst dst The source operand is added to the destination operand The source operand is not affected The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the result cleared if not V Set if an arithmetic overflow occurs otherwise reset OscOff CPUOff and GIE are not affected R5 is increased by 10 The jump to TONI is performed on a carry ADD 10 R5 JC TONI Carry occurred Joys No carry R5 is increased by 10 The jump to TONI is performed on a carry ADD B 10 R5 Add 10 to Lowbyte of R5 JC TONI Carry occurred if R5 gt 246 OAh 0F6h x No carry ADDC W ADDC B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Overview Add source and carry to destination Add source and carry to destination ADDC src dst or ADDC W src dst ADDC B src dst SIC dst C dst The source operand and the carry bit C are added to the destination operand The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif there is a carry from the MSB of the result reset otherwise V Setif an arithmetic overflow occurs otherwise reset OscOff CPUOff and GIE are not affected The 32 bit c
181. or words Bits can be written as Os once between erase cycles The read access does not differ from access to masked ROM or RAM Flash memory has restrictions in write operation Lj The default erased level for all bits is 1 Bits that are not programmed to 05 can be programmed to Os at any time The smallest memory portion to be erased is a segment No single byte or word erase is possible Access to a flash memory module is only possible when the module is not in a write or erase operation For example program code can not be executed in a module while it is processing a write or erase operation The access limitation has no critical impact on program execution but an access violation can be flagged in some situations see flash memory register section in this appendix Flash Memory 5 Flash Memory Data Structure and Operation C 2 4 Flash Memory Basic Functions The basic functions of flash memory are to Lj Supply program code and data during program execution Lj Erase under software or JTAG control parts of a module one segment multiple segments or an entire module Write data to a memory location under software or JTAG control A double speed programming sequence is implemented within a 64 byte section of the address range xxOOh to xx3fh C 2 2 Flash Memory Block Diagram The flash memory module has a minimum of three control registers a timing generator a voltage generator to supply program and
182. other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2002 Texas Instruments Incorporated About This Manual Preface Read This First The MSP430x1xx User s Guide is intended to assist the development of MSP430x1xx
183. own control word CCTLx shown in Figure 11 29 The POR signal resets all bits of CCTLx the PUC signal does not affect these bits Figure 11 29 Capture Compare Control Register CCTLx 1 0 IF 4 5 CCTLx Capture Input 0 rw 0 rw 0 rw O rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw O rw 0O 0 rw 0 11 32 Bit Bit 1 Bit 2 Bit 3 Bit 4 Bits 5 to 7 Timer B Registers Capture compare interrupt flag CCIFGx Capture mode If set it indicates that a timer value was captured in the CCRx register Compare mode If set it indicates that a timer value was equal to the data in the TBCLx latch CCIFGO flag CCIFGO is automatically reset when the interrupt request is accepted CCIFG1 to CCIFGx flags The flag that caused the interrupt is automatically reset after the TBIV word is accessed If the TBIV register is not accessed the flags must be reset with software No interrupt is generated if the corresponding interrupt enable bit is reset but the flag will be set In this scenario the flag must be reset by the software Setting the CCIFGx flag with software will request an interrupt if the interrupt enable bit is set Capture overflow flag COV Compare mode selected CAP 0 Capture signal generation is reset No compare event will set COV bit Capture mode selected CAP 1 The overflow flag COV is set if a second capture is performed before the first capture value
184. pin is switched to input direction Bit 1 The port pin is switched to output direction 8 10 Ports P3 P4 P5 P6 8 3 1 4 Function Select Registers PnSEL Ports P3 P6 pins are often multiplexed with other peripheral modules to reduce overall pin count on MSP430 devices see the specific device data sheet to determine which other peripherals also use the device pins Control registers PnSEL are used to select the desired pin function O port or other peripheral module Each register contains eight bits corresponding to each and each pin s function is individually selectable All bits in these registers are reset by the PUC signal The bit definitions are Bit 0 Port function is selected for the pin Bit 1 Other peripheral module function is selected for the pin EL OA LEUR E TU TE MMM Note Function Select With PnSEL Registers The interrupt edge select circuitry is disabled if control bit PnSEL x is set Therefore the input signal can no longer generate an interrupt When port pin is selected to be used as an input to a peripheral module other than the I O port PnSEL x 1 the actual input signal to the peripheral module is a latched representation of the signal at the device pin see Figure 8 4 schematic The latch uses the PnSEL x bit as its enable so while PNSE
185. q SAMPCON Timer Timer A OUT1 O Timer B OUTO SHI asc Timer B OUT1 12 Bit SAR je Conversion CTL v 15 7 1 Sampling Operation 15 22 The sample and hold circuitry samples the analog signal when the sampling signal SAMPCON see Figure 15 14 is high Conversion starts immediately with the falling edge of SAMPCON The sample and hold holds the signal value when SAMPCON is low Conversion takes 13 ADC12CLK cycles see Figure 15 15 Sampling Figure 15 15 Sample and Conversion Basic Signal Timing SAMPCON Start Stop Sampling Sampling Start Conversion Stop Conversion Y Y Y Sample Conversion and Hold The analog input signal must be valid and steady during the sampling period in order to obtain an accurate conversion It is also desirable not to have any digital activity on any adjacent channels during the whole conversion period to ensure that errors due to supply glitching ground bounce or crosstalk do not corrupt the conversion results In addition gains and losses in internal charge limit the hold time The user should ensure that the data sheet limits are not violated Otherwise the sampled analog voltage may increase or decrease resulting in false conversion values 15 7 2 Sample Signal Input Selection The SAMPCON signal which controls sample timing and the start of a conversion may be sourced by one of several signals SAMPCON may be sourced directly from one of the signals a
186. reference voltage it will not influence the offset voltage significantly To increase the precision of voltage measurements the comparator offset voltage can be measured by the following steps To simply compensate for the offset without measuring it see section 14 4 7 First execute a conversion with CAEX 0 is applied to the terminal of the comparator and is applied to the terminal of the comparator as shown in Figure 14 18 Figure 14 18 Measuring the Offset Voltage of the Comparator CAEX 0 0 VcC P2OA0 acy 50 rs CAON e g CAF cao 0 Supe 1 97 Q 9 6 P Timer A 09 0 1 P2CA1 Vref The Voffset in this configuration is in series with as shown in Figure 14 19 Vref Voffset Figure 14 19 Offset Voltage of the Comparator CAEX 0 0 Vcc 50 1 CAON e g Capture Input of Timer A m E Vref offset vov Next execute a conversion with CAEX 1 VcAo is applied to the terminal of the comparator and Vier is applied to the terminal of the comparator as shown in Figure 14 20 14 20 Comparator A in Applications Figure 14 20 Measuring the Offset Voltage of the Comparator CAEX 1 0 VcC s CAON e g a CAF Capture CAO 9 Input of P m Timer 09 P2CA1 Vref The Voffsetin this configuration is in se
187. repeated conversions Sequence of channels single sequence Sequence of channels repeated sequence Each mode is summarized in Table 16 2 and described in detail in the follow ing sections Table 16 2 Conversion Modes Summary CONVERSION MODE Single channel Sequence of channels Repeat single channel Repeat sequence of channels CONSEQ OPERATION 00 Single conversion on channel selected by INCH bits 01 A sequence of channels is converted The sequence starts with the channel selected by the INCH bits Each channel from A INCH down to is converted once 10 The conversion of channel A INCH is repeated until repeat is off or ENC is reset 11 The conversion of a sequence of channels is repeated until repeat is off or ENC is reset The sequence starts with A INCH and ends at 0 Note After completing a conversion the result is buffered in ADC10MEM then the interrupt flag ADC10IFG is set 16 4 1 Single Channel Single Conversion Mode 16 8 The single channel mode converts the channel selected by the INCH bits once When the conversion is complete the conversion result is stored in register ADC10MEM and the interrupt flag ADC10IFG is set If the interrupt enable is set an interrupt request is generated The conversion may be stopped immediately by resetting the enable conversion bit ENC located in ADC10CTLO but the conversion results will be unreliable or the conversion may not be performed
188. selected clock Source is activated then the receive operation starts even from low power modes Source select 0 and 1 The source select bit defines which clock source is used for baud rate generation SSEL1 SSELO 0 External clock UCLKI 1 ACLK 2 9 SMCLK Clock polarity CKPL The CKPL bit controls the polarity of the UCLKI signal CKPL 0 The UCLKI signal has the same polarity as the UCLK signal CKPL 2 1 The UCLKI signal has an inverted polarity to the UCLK signal Unused Control and Status Registers 12 5 3 Receiver Control Register UORCTL UTRCTL The receiver control register shown in Figure 12 18 controls the USART hardware associated with the receiver operation and holds error and wake up conditions modified by the latest character written to the receive buffer UxRXBUF Once any one of the bits FE PE OE BRK RXERR or RXWake is set none are reset by receiving another character The bits are reset by accessing the receive buffer by a USART software reset SWRST by a system reset PUC signal or by an instruction Figure 12 18 Receiver Control 2 UORCTL U1RCTL UORCTL 072h U1RCTL 07Ah Bit 0 Bit 1 Bit 2 Bit 3 T fom URXEIE URXWIE RXWake RXERR rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 The receive error bit RXERR indicates that one or more error flags FE PE OE or BRK is set It is not reset when the error flags are cleared by instruction Receiver wake up detect The RXW
189. show the necessary cycles for every instruction The example is written for continuous mode the time difference to the next interrupt is added to the corresponding compare register Software example for the interrupt part Cycles Interrupt handler for Capture Compare Module 0 The interrupt flag CCIFGO is reset automatically TIMMODO MS Start of handler Interrupt latency 6 RETI 5 Interrupt handler for Capture Compare Modules 1 to 6 The interrupt flags CCIFGx and TBIFG are reset by hardware Only the flag with the highest priority responsible for the interrupt vector word is reset TIM HND Interrupt latency 6 ADD amp TBIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP TIMMOD1 Vector 2 Module 1 2 JMP TIMMOD2 Vector 4 Module 2 2 RETI Vector 6 RETI Vector 8 RETI Vector 10 RETI Vector 12 Timer Overflow Handler the Timer Register is expanded into the RAM location TIMEXT MSBs TIMOVH Vector 14 TIMOV Flag INC TIMEXT Handle Timer Overflow 4 RETI 5 TIMMOD2 Vector 4 Module 2 ADD NN amp CCR2 Add time difference 5 25 0 Task starts here RETI Back to main program 5 The Module 1 handler shows a way to look if any other interrupt is pending 5 cycles have to be spent but 9 cycles may be saved if another interrupt is pending TIMMOD1 Vector 6 Module 3 ADD PP amp CCR1 Add time difference 5 aha Task starts
190. the analog inputs see an effective maximum nominal RC of a 30 pF C array capacitor in series with a 2 kO resistor Ron of switches However if the external dynamic source impedance is large then these transients may not settle within the allocated sampling time to ensure 10 bits of accuracy It is imperative that the proper sample timing be used for accurate conversions The next section discusses how to calculate the sample timing 16 6 4 1 Simplified Sample Timing Analysis Using the equivalent circuit shown in Figure 16 14 the time required to charge the analog input capacitance from 0 to VS within 1 2 LSB can be derived as follows Figure 16 14 Equivalent Circuit Vs VI MSP430 Input voltage at pin Ax fi Vs External driving source voltage Rg Source resistance must be real at input frequency ri Input resistance MUX on resistance Cj Input capacitance TS Vc Capacitance charging voltage 11 The capacitance charging voltage is given by NM tc 1 Vo Vgl 1 z 1 Where Ri Zi te Cycle time The input impedance Zi is 1 at 3 0 V and is higher 2 at 1 8 V The final voltage to 1 2 LSB is given by s 2 Vc 1 2LSB Vs 2048 Equating equation 1 to equation 2 and solving for cycle time tc gives V te 3 Ys acis x S ADC10 16 21 ADC10 Control Registers and the time to charge to
191. transmit interrupt flag UTXIFG or the receive interrupt flag URXIFG By using UTXIFG immediately after sending the shift register data to the slave the buffer data is transferred to the shift register and the transmission starts The slave receive timing should ensure that there is a timely pick up of the data The URXIFG flag indicates when the data shifts out and in completely The master can use URXIFG to ensure that the slave is ready to correctly receive the next data USART Peripheral Interface SPI Mode 13 7 Synchronous Operation 13 3 1 1 Four Pin SPI Master Mode The signal on STE is used by the active master to prevent bus conflicts with another master The STE pin is an input when the corresponding PnSEL bit in the registers selects the module function The master operates normally while the STE signal is high Whenever the STE signal is low for example when another device makes a request to become master the actual master reacts such that The pins that drive the SPI bus lines SIMO and UCLK are set to inputs The error bit FE and the interrupt flag URXIFG in registers UORCTL and U1RCTL respectively are set The bus conflict is then removed SIMO and UCLK do not drive the bus lines and the error flag indicates the system integrity violation to the software Pins SIMO and UCLK are forced to the input state while STE is in a low state and they return to the conditions defined by the corresponding control bi
192. violation interrupt flag ACCVIFG is set when the flash memory module is accessed while the Lock bit is set Flash Memory C 17 Flash Memory Interrupt and Security Key Violation EMEX 012Ch bit5 Emergency exit The emergency exit should only be used when a flash memory write or erase operation is out of control 0 No function 1 Stopsthe active operation immediately and shuts down all internal parts of the flash memory controller Current consumption immediately drops back to the active mode All bits in control register FCTL1 are reset Since the EMEX bitis automatically reset by hardware the software always reads EMEX as 0 C 4 Flash Memory Interrupt and Security Key Violation One NMI vector is used for three non maskable interrupt NMI events RST NMI oscillator fault OFIFG and flash access violation ACCVIFG The soft ware can determine the source of the interrupt request by testing interrupt flags NMIIFG OFIFG and ACCVIFG They remain setuntil reset by software Flash Memory Interrupt and Security Key Violation Figure C 10 Access Violation Non Maskable Interrupt Scheme in Flash Memory Module ACCV S ACCVIFG FCTL1 1 gt Flash Module Flash Module F Flash Module ACCVIE IE1 5 Clear v RST NMI be System Reset Generator 4 4 94 4 4 r L 4 NMIIFG 7 51 ole IFG1 4 ar 5 EQU
193. x x x x EQUx OO fH O Oo X OUTx bit OUTx no change 1 set OUTx no change OUTx toggle 0 reset 1 set OUTx no change 1 set 0 reset 1 set OUTx no change OUTx toggle OUTx no change 0 reset OUTx no change OUTx toggle 1 set 0 reset OUTx no change 0 reset 1 set 0 reset Figure 11 24 Output Examples Timer Up Mode TBR max Example EQU1 Used TBCLO TBCL1 Oh Du d Output Mode 1 Set RM Output Mode 2 PWM Toggle Reset ieri cm E Output Mode 3 PWM Set Reset mE Output Mode 4 Toggle ea 1 Output Mode 5 Reset Sas Output Mode 6 PWM Toggle Set Ium ho Output Mode 7 PWM Reset Set EQUO EQUi EQUO EQU1 EQUO Interrupt Events 11 5 3 2 Ouiput Examples Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCLO values depending on the output mode as shown in Figure 11 25 Figure 11 25 Output Examples Timer in Continuous Mode Output Mode 2 PWM Toggle Reset Output Mode 3 PWM Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 PWM Toggle Set Output Mode 7 PWM Reset Set TBR max TBCLO TBCL1 Oh TER Output Mode 1 Set TBOV EQU1 EQUO TBOV EQU1 EQUO Interrupt Events Timer B 11 27 11 5 3 3 Output Examples Timer Up Down M
194. 0 to P2 7 requests an interrupt when two conditions are met the appropriate individual bit PnIE x is set and the GIE bit is set Interrupt flags P1IFG 0 to P1IFG 7 or P2IFG 0 to P2IFG 7 are not automatically reset The software of the interrupt service routine should handle the detection of the source and reset the appropriate flag when it is serviced Ports P3 P4 P5 P6 8 3 Ports P3 P4 P5 P6 General purpose ports P3 P6 function as shown in Figure 8 3 Each pin can be selected to operate with the port function or to be used with a different peripheral module This multiplexing of pins allows for a reduced pin count on MSP430 devices Four registers control each of the ports see Section 8 3 1 Ports P3 P6 are connected to the processor core through the 8 bit MDB and the MAB They should be accessed with byte instructions using the absolute address mode Figure 8 3 Ports P3 P6 Configuration MDB MSB LSB Pn 7 0 8 3 1 Port P3 P6 Control Registers The four control registers of each port give maximum configuration flexibility of digital I O All individual I O bits are programmed independently Any combination of input is possible L Any combination of port or module function is possible The four registers for each port are shown in Table 8 3 They each contain eight bits and should be accessed with byte instructions Digital I O Configuration 8 9 Ports P4 P5 P6 Table 8 3
195. 0x11xx Interrupt Enable Registers 1 2 3 12 MSP430x12xx Interrupt Enable Registers 1 and 2 3 12 MSP430x13x Interrupt Enable Registers 1 2 3 13 MSP430x14x Interrupt Enable Registers 1 2 3 13 MSP430x11xx Interrupt Flag Registers 1 and 2 3 14 MSP430x12xx Interrupt Flag Registers 1 and 2 3 15 MSP430x13x Interrupt Flag Registers 1 and 2 3 16 MSP430x14x Interrupt Flag Registers 1 and 2 3 17 MSP430x11xx Module Enable Registers 1 2 3 18 MSP430x12xx Module Enable Registers 1 and 2 3 18 MSP430x13x Module Enable Registers 1 and 2 3 19 MSP430x14x Module Enable Registers 1 and 2 3 19 Interrupt Sources Flags and Vectors of MSP430x11xx Configurations 3 20 Interrupt Sources Flags and Vectors of MSP430x12xx Configurations 3 21 Interrupt Sources Flags and Vectors of MSP430x13x and MSP430x1 4x Configurations d UE Moi Eae te ae aac 3 22 Low Power Mode Logic Chart for Basic Clock System 3 26 Peripheral File Address Map Wor
196. 0x14x Interrupt Flag Registers 1 and 2 Bit Position Short Form IFG1 0 IFG1 1 IFG1 2 IFG1 3 IFG1 4 IFG1 5 IFG1 6 IFG1 7 IFG2 0 IFG2 1 IFG2 2 IFG2 3 IFG2 4 IFG2 5 IFG2 6 IFG2 7 Note WDTIFG OFIFG NMIIFG URXIFGO UTXIFGO URXIFG1 UTXIFG1 Initial State Set Or reset Set Reset Reset Set Reset Set Comments Set on watchdog timer overflow in watchdog mode or security key violation Reset with VCC power up or a reset condition at the RST NMI pin in reset mode Flag set on oscillator fault Not implemented Not implemented Set through the RST NMI pin Not implemented USARTO receive flag USARTO transmitter ready Not implemented Not implemented Not implemented Not implemented USART1 receive flag USART1 transmitter ready Not implemented Not implemented The configuration of some MSP430 devices may differ from those in above table Refer to specific device data sheets for individual configurations System Resets Interrupts and Operating Modes 3 17 Interrupt Processing Table 3 10 MSP430x11xx Module Enable Registers 1 and 2 Bit Position Short Form Initial State Comments 1 0 Reserved ME1 1 Reserved ME1 2 Reserved ME1 3 Reserved ME1 4 Reserved ME1 5 Reserved 1 6 Reserved ME1 7 Reserved ME2 0 Reserved ME2 1 Reserved ME2 2 Reserved ME2 3 Reserved ME2 4 Reserved ME2 5 Reserved ME2 6 Reserved ME2 7 Reserved Note The configuration of some MSP430 devices m
197. 1 dst i SUBC src dst dst not src C dst P 2 src dst dst src s z DADD src dst src dst C dst dec i AND src dst src and dst dst 0 7 BIT src dst src and dst 0 src dst hot src and dst dst BIS src dst src or dst dst XOR src dst src xor dst dst i li ii The status bit is affected The status bit is not affected 0 The status bit is cleared The status bit is set ROGO Note Instructions CMP and SUB The instructions CMP and SUB are identical except for the storage of the result The same is true for the BIT and AND instructions LLLLLLL MA 5 18 Instruction Set Overview 5 3 2 Single Operand Format Il Instructions Figure 5 8 illustrates the single operand instruction format See section 5 2 8 for information on number of code words and execution cycles per instruction Figure 5 8 Single Operand Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 5 18 describes the effects of an instruction on the single operand instruction status bits Table 5 18 Single Operand Instruction Format Results Mnemonic S Reg D Reg Operation StatusBits V N 2 C RRC dst MSB gt LSB C 5 dst MSB MSB gt LSB 0 A d
198. 1 Conversion start address CStartAdd is used to define which ADC12 conversion memory register ADC12MEMx is used for a single conversion or for the first conversion in a sequence of conversions The value of CStartAdd is 0 to OFh corresponding to ADC12MEMO to ADC12MEM 15 Since there is one corresponding conversion memory control register ADC12MCTLx for each conversion memory register ADC12MEMX CStartAdd also points to the corresponding ADC12MCTLx register Warning Modifying ADC Control Register During Active Conversion The enable conversion control bit ENC inthe ADC12CTLO register protects most bits from modification during an active conversion However some bits that are necessary for proper completion of active conversions and interrupt enable bits can be modified independently of ENC The user must use caution when modifying theses bits to ensure an active conversion is not corrupted or to not use corrupted data To avoid corrupting any active conversions stop the conversion wait for the busy bit to be reset reset the ENC bit then modify the control bits ADC12 Control Registers 15 8 2 Conversion Memory Registers ADC12MEMx ADC12MEM 0140h 015Eh ADC12MEMO to ADC12MEM 15 bits There are sixteen conversion memory registers ADC12MEMXx as follows Conversion results The 12 bit conversion results are right justified and 0 15 the four MSBs are always read as 0 The ADC120OV interrupt flag will
199. 1 2 LSB minimum sampling time is ten 1 2 LSB Ry x Cj x In 2048 Where In 2048 7 625 Therefore with the values given the time for the analog input signal to settle is ten 1 2 LSB Rg 1 x Cj x 7 625 4 This time must be less than the sampling time The maximum ADC10CLK frequency is 24 5 ADC10CLK max ton 2LSB This frequency must not exceed the maximum ADC10CLK frequency specified in the data sheet 16 7 ADC10 Control Registers Register ADC input enable ADC control register 0 ADC control register 1 ADC memory Two control registers and one conversion memory register are used to configure the ADC10 Short Form Register Type Address Initial State ADC10AE Read write 04Ah Reset with POR ADC10CTLO Read write 01BOh Reset with POR ADC10CTL1 Read write 01B2h Reset with POR ADC10MEM Read 01B4h Unchanged Note These registers may be accessed by any instruction subject to register access restrictions 16 7 1 Control Registers ADC10CTLO and ADC10CTL1 ADC10CTLO 15 01B0h rw 0 16 22 All control bits of ADC10CTLO and ADC10CTL 1 are reset during POR Most of the control bits in registers ADC10CTLO and ADC10CTL1 can only be modified if ENC is reset These bits are marke 1 All other bits can be modified at any time The control bits of control register ADC10CTLO and ADC10CTL1 are 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC10 ADC10 REF REF REF ADC10 ADC10 ADC10 ADC10 0 rw 0
200. 1 3 1 Timer Stop Mode Stopping and starting the timer is done simply by changing the mode control bits MCx The value of the timer is not affected When the timer is stopped from up down mode and then restarted in up down mode the timer counts in the same direction as it was counting before it was stopped For example if the timer is in up down mode and counting in the down direction when the bits are reset when they are set back to the up down direction the timer starts counting in the down direction from its previous value If this is not desired in an application the CLR bit in the TBCTL register can be used to clear this direction memory feature 11 3 2 Timer Up Mode The up mode is used if the timer period must be different from the TBR max clock cycles of the continuous mode periods The capture compare register CCRO data defines the timer period The counter counts up to the content of compare latch TBCLO as shown in Figure 11 5 When the timer value and the value of compare latch TBCLO are equal or if the timer value is greater than the TBCLO value the timer restarts counting from zero Figure 11 5 Timer Up Mode TBR max TBCLO Oh Flag CCIFGO is set when the timer equals the TBCLO value The TBIFG flag is set when the timer counts from TBCLO to zero All interrupt flags are set independently of the corresponding interrupt enable bit but an interrupt is requested only if the corresponding interrupt e
201. 12 Mark and Space 12 17 Receive Status Control Bits 12 20 Break Detect BRK Bit With Halted UART Clock 12 25 USART Synchronous Master Mode Receive Initiation 13 7 USPIIE Reenabled SPI Mode 13 10 Writing to UXTXBUF SPI Mode 13 12 Writing to UXTXBUF Reset of Transmitter SPI 13 12 Caution ADCT2 T rnon Time sso sebienshtedencisetesotefertebeereleriebhnrebereebus 15 5 Warning Reference Voltage Settling Time 15 6 Availability of ADC12CLK During Conversion 15 22 Warning Modifying ADC Control Register During Active Conversion 15 34 Warning Software Write to Register ADC12MEMX 15 35 xxii Contents Writing to Read Only Register 2 15 38 Basic Clock System ni Sevarice once Ar aoe L REPRE Whe IER 15 40 Caution ADC10 Turnon Time 16 4 Warning Reference Voltage Settling Time
202. 16 19 State Diagram for Data Transfer Control in Two Block Transfer Mode n 0 ADC10DTC1 DTC reset ADC10B1 0 ADC10TB 1 nzo Wait for write to ADC10SA Initialize Start Address in ADC10SA Write to ADC10SA If ADC10B1 0 then AD SA n is latched in counter x Write to ADC10SA or Wait until ADC10MEM n 0 is written Write to ADC10MEM completed Write to ADC10SA Synchronize CPU ready with MCLK x gt 0 Write to ADC10SA 1 x MCLK cycle 2 Transfer data to Address AD AD AD 2 1 ADC10B1 1 or ADC10CT 1 ADC10B1 0 ADC10IFG 1 Toggle ADC10B1 16 34 Prepare DTC DTC operation Data Transfer Control High Speed Conversion Support 16 8 2 Data Transfer Control Registers in ADC10 Three registers are used by the DTC section of the ADC10 module Register Short Form Register Type Address Initial State ADC data transfer control register O ADC10DTCO Read write 048h Reset with POR ADC data transfer control register 1 ADC10DTC1 Read write 049h Reset with POR ADC data transfer start address ADC10SA Read write 01BCh 0200h 16 8 2 1 Data Transfer Control Registers ADC10DTCO ADC10DTC1 Bit 0 Bit 1 Bit 2 Bit 3 The data transfer control register ADC10DTCO contains control bits for block 1 or 2 identification continuous data transfer mode and two block mode ADC10DTCO
203. 2 13 14 15 16 1 BRSCLK L n 1 Take Majority Vote of Receive Bit BITCLK L4 Baud rate BRCLK n x 16 Typical baud rate schemes often require specific crystal frequencies or cannot generate some baud rates required by some applications For example division factors of 18 are not possible nor are noninteger factors such as 13 67 12 3 2 2 MSP430 Baud Rate Generation The MSP430 baud rate generator uses one prescaler divider and a modulator as shown in Figure 12 6 This combination works with crystals whose frequencies are not multiples of the standard baud rates allowing the protocol to run at maximum baud rate with a watch crystal 32 768 Hz This technique results in power advantages because sophisticated MSP430 low power operations are possible USART Peripheral Interface UART Mode 12 5 Asynchronous Operation Figure 12 6 MSP430 Baud Rate Generation Example for n or n 1 Clock Periods 0 7 UxBRO 1 7 SSEL1 SSELO UCLKI o o 9 o SMCLK o SMCLK o o 34 0 7 UxBR1 Start 8 15 BRCLK L 15 Bit Prescaler Divider Q1 Q15 Compare 0 or 1 Shift Modulation Register Data lt Shift out Shift in BITCLK m 0 7 Modulation Register UOMCTL or UTMCTL H Start L BRCLK Counter 2 1102 11 022 1 1 n n2 1 21 1 1 2 1 2 2 1 0 2 n 2 1 1 1 az
204. 2CLK X N ERE EHE EIE SHT1 bits Sample and hold Time1 These bits define the sample timing for 12 15 conversions whose results are stored in conversion memory registers ADC12MEM8 to ADC12MEM15 The sample time is a multiple of the ADC12CLK x 4 tsample 4 X tADC12CLK X N ER BEER ES 15 8 7 0 ADC12CTL1 I i m CSStartAdd SHS SHP issu ADC12DIV ADC12SSEL CONSEQ 01 2 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 ADC12BUSY bito The ADC12BUSY bit indicates an active sample or conversion operation It is used specifically when the conversion mode is single channel single conversion because if the ENC bit is reset in this mode the conversion stops immediately and the results are invalid Therefore the ADC12BUSY bit should be tested to verify that it is 0 before resetting the ENC bit when in single channel single conversion mode The busy bit is not useful in all other operating modes because resetting the ENC bit does not immediately affect any other mode 0 No operation is active 1 Asample period conversion or conversion sequence is active CONSEQ bits The CONSEQ bits select the conversion mode Repeat mode is on if the 1 2 CONSEQ 1 is set 0 Single channel single conversion mode One single channel is
205. 60h POR reset Timer register TAR Read write 170h POR reset Cap com control 0 CCTLO Read write 162h POR reset Capture compare 0 CCRO Read write 172h POR reset Cap com control 1 CCTL1 Read write 164h POR reset Capture compare 1 CCR1 Read write 174h POR reset Cap com control 2 CCTL2 Read write 166h POR reset Capture compare 2 CCR2 Read write 176h POR reset 10 24 10 6 1 Timer A Control Register TACTL Timer A Registers The timer and timer operation control bits are located in the timer control register TACTL shown in Figure 10 27 All control bits are reset automati cally by the POR signal but are not affected by the PUC signal The control register must be accessed using word instructions Figure 10 27 Timer A Control Register TACTL 15 0 TACTL Input Input Mode Un rw rw rw rw rw rw rw w rw rw rw rw rw rw 0 0 0 0 Bit 0 Bit 1 Bit 2 Bit 3 rw rw 0 0 0 0 0 0 0 9 0 TAIFG This flag indicates a timer overflow event Up mode Continuous mode Up down mode TAIFG is set if the timer counts from CCRO value to 0000h TAIFG is set if the timer counts from OFFFFh to 0000h TAIFG is set if the timer counts down from 0001h to 0000h Timer overflow interrupt enable TAIE bit An interrupt request from the timer overflow bit is enabled if this bit is set and is disabled if reset Timer clear CLR bit The timer and input divider are reset with the
206. 8x8 Unsigned Multiply MOV B 4012h amp MPY Load first operand into appropriate register MOV B 034h amp OP2 Load 2nd operand Result is now available 6 2 2 Multiply Signed 16x16 bit 16 8 bit 8x16 bit 8x8 bit The following is an example of signed multiplication 16x16 Signed Multiply MOV 01234h amp MPYS Load first operand into appropriate register MOV 05678h amp OP2 Load 2nd operand Result is now available 8x8 Signed Multiply MOV B 4012h amp MPYS Load first operand into appropriate register SXT amp MPYS Sign extend first operand MOV B 034h amp OP2 Load 2nd operand SXT amp OP2 Sign extend 2nd operand triggers 2nd multiplication Result is now available Hardware Multiplier Operation 6 2 3 Multiply Unsigned and Accumulate 16x16 bit 16x8 bit 8x16 bit 8x8 bit The following is an example of unsigned multiply and accumulate 16x16 Unsigned Multiply and Accumulate MOV 01234h amp MAC Load first operand into appropriate register MOV 05678h amp OP2 Load 2nd operand Result is now available 8x8 Unsigned Multiply and Accumulate MOV B 4012h amp MAC Load first operand into appropriate register MOV B 034 6 2 Load 2nd operand Result is now available 6 2 4 Multiply Signed and Accumulate 16x16 bit 16x8 bit 8x16 bit 88 bit The following is an example of signed multiply and accumulate 16x16 Signed Multip
207. 9 1 Schematic of Watchdog Timer See Interrupt WDTCNT WDTCTL MSB Definition Bourne Password Cmp Pulse Generator 16 PUC Write Enable Low Byte RW SMCLK ACLK 4 LSB Watchdog Timer Control Register Features of the Watchdog Timer include d d d 9 2 Eight software selectable time intervals Two operating modes as watchdog or interval timer Expiration of the time interval in watchdog mode which generates a system reset or in timer mode which generates an interrupt request Safeguards which ensure that writing to the WDT control register is only possible using a password Support of ultralow power using the hold mode The Watchdog Timer 9 1 1 Watchdog Timer Register watchdog timer counter WDTCNT is a 16 bit up counter that is not directly accessible by software The WDTCNT is controlled through the watchdog timer control register WDTCTL shown in Figure 9 2 which is a 16 bit read write register located at the low byte of word address 0120h Any read or write access must be done using word instructions with no suffix or w suffix In both operating modes watchdog or timer it is only possible to write to WDTCTL using the correct password Figure 9 2 T Timer Control ia WDTCTL rw 0 rw 0 rw 0 rw 0 rO w rw O0 rw 0 rw 0 WDTCTL 4 069h Read WDTCTL Write 4 05Ah Bits 0 1 Bits ISO and 161 sele
208. Additionally since the ADC10IFG flag is set an interrupt request is executed if both the general interrupt enable bit GIE and the ADC1OIE bit are set Next the transfer counter is loaded with n again and the DTC waits for the ADC10MEM buffer to be loaded again Upon the next load of the ADC10MEM buffer the DTC begins transferring conversion results to block two in the same manner as described before Again after n transfers have completed block two is full so Data Transfer Control High Speed Conversion Support the ADC10IFG flag is set and an interrupt is requested is GIE and ADC10IE are set and bit ADC10B1 is cleared Bit ADC10B1 being cleared indicates that the transfers to block two have completed and block two is full of data The ADC10B1 bit indicates to software which block is full of data so the application software can process the data in either of the blocks while the other block is being loaded simultaneously The state diagram for the two block mode is shown in Figure 16 19 In two block mode when the control bit ADC10CT continuous mode is set indicating continuous mode the DTC circuity does not pause or stop after the second block is finished Transfers into the first block begin with the next ADC10MEM buffer load after the second block is filled If bit ADC10CT is reset the DTC transfers cease after both block transfers have completed ADC10 Data Transfer Control High Speed Conversion Support Figure
209. BR10 075h USARTO Baud rate UBROO 074h USARTO Modulation control UMCTLO 073h USARTO Receive control URCTLO 072h USARTO Transmit control UTCTLO 071h USARTO USART control UCTLO 070h 2 n 2 r 2 2 2 Q A 70 2 hue 7 7 w 7 r w 7 rw rw 7 rw 7 t rw 7 rw w 7 7 2 2 rw 0 CKPH rw 0 Unused rw 0 m r Unused 6 PEMA d IN 8 Undef rw 0 CKPL rw 0 Unused rw 0 26 rw 26 r 3 o CKPL rw 0 Unused rw 0 5 OE rw 0 SSEL1 rw 0 Unused rw 0 gt a 8 rw 0 SSEL1 rw 0 Unused rw 0 m 4 279 n aM m4 rw Undef rw 0 SSELO rw 0 CHAR rw 0 24 rw Undef rw 0 SSELO rw 0 CHAR rw 0 3 2 1 m2 r rw rw Unused Unused Undef rw 0 rw 0 rw 0 Unused Unused STC rw 0 rw 0 rw 0 Listen SYNC MM rw 0 rw 0 rw 0 23 22 rw rw rw r w Unused rw 0 m2 rw rw Unused Undef rw 0 rw 0 Unused Unused STC rw 0 rw 0 rw 0 Listen SYNC MM rw 0 rw 0 rw 0 Peripheral File Map 3 o Undef rw 0 TXEPT 2 Undef rw 0 TXEPT rw 1 SWRST rw 1 A 7 ADC12 Registers Byte and Word Access A 9 ADC12 Registers Byte and Word Access Bit 4 7 6 5 4 3 2 1 0 ADC12MCTL15 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 008Fh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTL14T EOS Sref 2 Sref 1
210. CAPD 7 CAPD 6 CAPD 5 CAPD 4 CAPD 3 CAPD 2 CAPD 1 CAPD O 005Bh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Comparator A control reg 2 2 CACTL2 7 CACTL2 6 CACTL2 5 CACTL2 4 CA1 CAO CAF CAOUT 005Ah rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 Comparator control reg 1 CACTL1 CAEX CARSEL CAREF1 CAREFO CAON CAIES CAIE CAIFG 0059h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Peripheral File Map A 5 USARTO USART1 UART Mode Sync 0 Byte Access A 7 USARTO USART1 UART Mode Sync 0 Byte Access Bit USART1 Transmit buffer UTXBUF1 07Fh USART1 Receive buffer URXBUF1 07Eh USART1 Baud rate UBR11 07Dh USART1 Baud rate UBRO1 07Ch USART1 Modulation control UMCTL1 07Bh USART1 Receive control URCTL1 07Ah USART1 Transmit control UTCTL1 079h USART1 USART control UCTL1 078h USARTO Transmit buffer UTXBUFO 077h USARTO Receive buffer URXBUFO 076h USARTO Baud rate UBR10 075h USARTO Baud rate UBROO 074h USARTO Modulation control UMCTLO 073h USARTO Receive control URCTLO 072h USARTO Transmit control UTCTLO 071h USARTO USART control UCTLO 070h A 6 rw FE rw 0 Unused rw 0 PENA rw 0 27 rw 27 r 215 rw 27 rw m7 rw FE rw 0 Unused rw 0 PENA rw 0 6 8 rw 0 CKPL rw 0 PEV rw 0 26 2 oO 2 gt oO 8 79 rw 0 CKPL rw 0 PEV rw 0 5
211. CCISOO SCSO SCCIO Unused rw rw rw 0 rw 0 rw rw 0 r Unused Unused Unused Unused Unused SSEL2 SSEL1 rw rw rw 0 rw 0 rw rw 0 rw 0 0 0 0 0 0 0 t Registers are reserved on devices with Timer_A3 N 2 rw rw rw rw rw rw N N N 4 rw CAP3 rw CAP2 rw CAP1 rw CAPO rw 8 SSELO 0 0 0 0 0 0 0 0 0 0 0 rw 0 Timer A Registers Word Access A 14 Timer A Registers Word Access Continued Bit 7 6 5 4 3 2 1 0 Cap com register CCR4t 27 26 25 24 23 22 21 20 017Ah rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Cap com register 27 26 25 24 23 22 21 20 0178h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Cap com register CCR2 27 26 25 24 23 22 21 20 0176 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Cap com register CCR1 27 26 25 24 23 22 21 20 0174h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Cap com register CCRO 27 26 25 24 23 22 21 20 0172h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Timer A register TAR 27 26 25 24 23 22 21 20 0170 E a 016Eh 016Ch SS E S Cap com control 41 utMod42 OutMod41 utMod40 ol a ig 016Ah rw 0 rw rw rw Cap com control TR Ou
212. COCTL Decrease DCOCLK Features for Low Power Applications 7 4 3 Basic Clock Features for Low Power Applications Conflicting requirements typically exist in battery powered MSP430x1xx applications Low clock frequency for energy conservation and time keeping High clock frequency for fast reaction to events and fast burst processing capability The Basic Clock Module addresses the above conflicting requirements by allowing the design engineer to select from the three available clock signals ACLK MCLK and SMCLK For optimal low power performance the ACLK can be configured to oscillate with a low 32 786 Hz watch crystal frequency providing a stable time base for the system and low power stand by operation The MCLK can be configured to operate from the on chip DCO which is only activated when requested by events The SMCLK can be configured to operate from either the watch crystal or the DCO depending on peripheral requirements A flexible clock distribution and divider system is provided to fine tune the individual clock requirements All basic clock module configurations are under full software control 7 4 4 Selecting a Crystal Clock for MCLK After power up the Basic Clock Module uses the DCO clock for the system clock MCLK The LFXT1 oscillator starts in the low frequency mode XTS 0 Regardless of the configuration of the clock system the application uses if all initial conditions are set the software execution is ens
213. CPU Registers V7 1 Note Status Register Bits V N Z and C The status register bits V N Z and C are modified only with the appropriate instruction For additional information see the detailed description of the instruction set in Appendix B 5 1 4 The Constant Generator Registers CG1 CG2 Commonly used constants are generated with the constant generator registers R2 and R3 without requiring an additional 16 bit word of program code The constant used for immediate values is defined by the addressing mode bits As as described in Table 5 3 See Section 5 3 for a description of the addressing mode bits As Table 5 3 Values of Constant Generators CG1 CG2 Register As Constant Remarks R2 00 Register mode R2 01 0 Absolute address mode R2 10 00004h 4 bit processing R2 11 00008h 8 bit processing R3 00 00000h 0 word processing R3 01 00001h 1 10 00002h 2 bit processing R3 11 OFFFFh 1 word processing The major advantages of this type of constant generation are Li No special instructions required Reduced code memory requirements no additional word for the six most used constants Reduced instruction cycle time no code memory access to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as a source operand in the immediate addressing mode The status register SR
214. CRx data to TBCLx when TBR counts to 0 CLLD 2 UP DOWN mode load CCRx data to TBCLx when TBR counts to TBCLO or to 0 Continuous mode or UP mode load CCRx data to TBCLx when TBR counts to 0 CLLD 3 CCRx data are loaded to TBCLx when TBR counts to TBCLx Bit 11 SCSx bit This bit is used to synchronize the capture input signal with the timer clock 0 asynchronous capture 1 synchronous capture Bits 12 13 Input select CCISO and CCIS1 These two bits define the capture signal source These bits are not used in compare mode 0 Input CCIxA is selected 1 Input CCIxB is selected 2 GND 3 Vcc Bits 14 15 Capture mode bits Table 11 8 describes the capture mode selections 11 34 Timer B Registers Table 11 9 Capture Compare Control Register Capture Mode tie Capture Mode Description 0 Disabled The capture mode is disabled 1 Pos Edge Capture is done with rising edge 2 Neg Edge Capture is done with falling edge 3 Both Edges Capture is done with both rising and falling edges 2 aA 5 a tS Se ih Note Simultaneous Capture and Capture Mode Selection Captures must not be performed simultaneously with switching from compare to capture mode Otherwise the result in the capture compare register will be unpredictable The recommended instruction flow is 1 Modify the control register to switch from compare to capture 2 Capture For example BIS CAP amp CCTL2 Select capture with register CCR2 CCIS1
215. DC12MEM1 was loaded ADC12IFG 1 ADD amp ADC12MEM1 R6 ADC12IFG1 is reset due to access of ADC memory Task starts here RETI Back to main program 5 The Module 3 handler shows a way to look if any other interrupt is pending 5 cycles have to be spent but 9 cycles may be saved if another interrupt is pending i ADC12MODO Vector 6 ADC12MEMO was loaded ADCI2IFG 0 First instruction to be executed x Task starts here JMP ADC12 HND With this instruction the software does not leave the handler it looks for pending ADC12 interrupts 2 Note Basic Clock System If the CPU clock MCLK is turned off CPUOff 1 then two or three additional cycles need to be added for synchronous start of the CPU system The delta of one clock cycle is caused when clocks are asynchronous to the restart of CPU clock MCLK A D Grounding and Noise Considerations 15 9 A D Grounding and Noise Considerations As with any high resolution converter care and special attention must be paid to the printed circuit board layout and the grounding scheme to eliminate ground loops and any unwanted parasitic components effects and noise Industry standard grounding and layout techniques should be followed to reduce these unwanted effects Ground Loops are formed when return current from the A D flows through paths that are common with other analog or digital circuitry If care is n
216. DC12MEM13 ADC12MCTL13 08Dh ADC12MEM14 ADC12MCTL14 08Eh ADC12MEM15 ADC12MCTL15 08Fh 15 5 3 Repeat Single Channel Mode The repeat single channel mode is identical to the single channel mode except that conversions are repeated on the chosen channel until stopped by software Each time a conversion is completed the results are loaded into the appropriate ADC12MEMXx register and the corresponding interrupt flag ADC12IFG xis set to indicate completion of the conversion Additionally If the appropriate interrupt enable flags are set an interrupt request is generated see the ADC12 Interrupt Vector Register ADC 12IV section The conversion mode may be changed without first stopping the conversions When this is done the new mode takes effect after the current conversion completes see also the Switching Between Conversion Modes section There are three ways to stop repeated conversions on a single channel 1 15 16 Select single channel mode instead of repeat single channel mode with the CONSEQ bits When this is done the current conversion is completed normally the result is loaded into ADC12MEM x and the associated interrupt flag ADC12IFG x is set Reset the ENC bit ADC12CTLO 1 to stop conversions after the current conversion is completed Again the result is loaded into ADC12MEMx and the associated interrupt flag ADC12IFG x is set Select single channel mode instead of repeat single channel mode and then r
217. DIR P3DIR 7 P3DIR 6 PSDIR 5 P3DIR 4 PSDIR 3 P3DIR 2 P3DIR 1 P3DIR O 001Ah rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Output register PSOUT 7 P3OUT 6 P3OUT 5 4 PSOUT 3 PSOUT 2 PSOUT 1 PSOUT O 0019h rw rw rw rw rw rw rw rw Input register PSIN PSIN 7 6 P3IN 5 P3IN 4 PSIN 3 2 PSIN 1 0 0018h r r r r r r r r _ 0016h Peripheral File Map A 3 Digital I O Byte Access Digital I O Byte Access Continued Bit 7 6 5 4 3 2 1 0 Function select PeSEL PeSEL 7 P6SEL 6 PeSEL 5 PeSEL 4 P6SEL 3 PeSEL 2 PeSEL 1 PeSEL O Int edge select P1IES P1IES 7 P1IES 6 P1IES 5 P1IES 4 P1IES 3 P1IES 2 P1IES 1 P1IES O Direction register PEDIR P6DIR 7 PeDIR 6 P6DIR 5 PeDIR 4 P6DIR 3 P6DIR 2 PeDIR 1 PeDIR O 0036h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Output register PeOUT PeOUT 7 PeOUT 6 PeOUT 5 PeOUT 4 PeOUT 3 2 PeOUT 1 PEeOUT O 0035h rw rw rw rw rw rw rw rw Input register P6IN P6IN 7 P6IN 6 P6IN 5 P6IN 4 P6IN 3 P6IN 2 P6IN 1 P6IN O 0034h r r r r r r r r Function select PSSEL PS5SEL 7 PBSEL 6 P6SEL 5 P5SEL 4 P5SEL 3 55 2 P5SEL 1 PBSEL O 0033h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Direction register PSDIR P5DIR 7 P5DIR 6 P5DIR 5 P5DIR 4 P5DIR 3 P5DIR 2 P5DIR 1 P5DIR O 0032h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0
218. Digital I O port P1 and P2 control Digital I O port and P4 control Special function 4 4 3 Peripheral Modules Special Function Registers SFRs 4 10 The system configuration and the individual reaction of the peripheral modules to the processor operation is configured in the SFRs as described in Table 4 3 The SFRs are located in the lower address range and are organized by bytes SFRs must be accessed using byte instructions only RAM and Peripheral Organization Table 4 3 Special Function Register Address Map Address 000Fh 000Eh 000Dh 000Ch 000Bh 000Ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h Data Bus Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Module enable 2 ME2 2 Module enable 1 ME1 1 Interrupt flag reg 2 IFG2 x Interrupt flag reg 1 IFG1 x Interrupt enable 2 IE2 x Interrupt enable 1 IE1 x The system power consumption is influenced by the number of enabled modules and their functions Disabling a module from the actual operation mode reduces power consumption while other parts of the controller remain fully active unused pins must be tied appropriately or power consumption will increase see Basic
219. E 1 and 0 Priority Valid URXIFG 0 USART Peripheral Interface SPI Mode 13 13 Interrupt and Control Functions 13 4 4 Transmit Interrupt Operation In the transmit interrupt operation shown in Figure 13 14 the transmit interrupt flag UTXIFG is set by the transmitter to indicate that the transmitter buffer UXTXBUF is ready to accept another character This bit is automatically reset if the interrupt request service is started or a character is written to the UxTXBUF This flag activates a transmitter interrupt if bits USPIIE and GIE are set The UTXIFG is set after a system reset PUC signal or removal of SWRST Figure 13 14 Transmit Interrupt Operation 13 14 USPIIE 1 1 pose PUC or SWRST Request UTXIFG Interrupt Service Character Moved From Buffer to Shift Register SWRST UxTXBUF Written Into Transmit Shift Register IRQA The transmit interrupt enable bit UTXIE controls the ability of the UTXIFG to request an interrupt but does not prevent the UTXIFG flag from being set The USPIIE is reset with a PUC signal or a SWRST The UTXIFG bit is set after a system reset PUC signal or a SWRST but the USPIIE bit is resetto ensure full interrupt control capability Control and Status Registers 13 5 Control and Status Registers The USART registers shown in Table 13 2 are byte structured and should be accessed using byte instructions Table 13 2 USAHTO Control and Sta
220. E 4 P1IE 3 P1IE 2 P1IE 1 P1IE O 0025h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Interrupt flags P1IFG P1IFG 7 P1IFG 6 P1IFG 5 P1IFG 4 P1IFG 3 P1IFG 2 P1IFG 1 P1IFG O 0023h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Direction register PIDIR P1DIR 7 P1DIR 6 P1DIR 5 P1DIR 4 P1DIR 3 P1DIR 2 P1DIR 1 P1DIR O 0022h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Output register PIOUT P1OUT 7 P1OUT 6 P1OUT 5 PIOUT 4 P1OUT 3 PIOUT 2 P1OUT 1 P1OUT O 0021h rw rw rw rw rw rw rw rw Input register P1IN P1IN 7 1 6 5 P1IN 4 P1IN 3 2 P1IN 1 0 0020h r r r r r r r r 4 Basic Clock Registers Byte Access A 4 Basic Clock Registers Byte Access Bit 4 7 6 5 4 3 2 1 0 BCSCTL2 SELM 1 SELM O DIVM 1 DIVM O SELS DIVS 1 DIVS 0 DCOR 0058h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 BCSCTL1 XT2OFF XTS DIVA 1 DIVA O XT5V Rsel 2 Rsel 1 Rsel 0 0057h rw 1 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 rw 0 DCOCTL DCO 2 DCO 1 MODA MOD 3 MOD 2 MOD 1 MOD 0 0056h rw 0 1 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 A 5 EPROM Control Register Byte Access Bit 4 7 6 5 4 3 2 1 0 EPROM control registert ro 0 0 0 0 0 E 0054h t Non EPROM devices may use this register for other control purposes A 6 Comparator A Registers Byte Access Bit 7 6 5 4 3 2 1 0 Comparator_A Port Disable CAPD
221. E E D Timer A3 CCIFG2 Maskable OFFEAh TAIFG see Notes 14 and 15 P1IFG 0 see Notes 14 and 15 I O port P1 eight flags To Maskable OFFE8h P1IFG 7 see Notes 14 and 15 USARTI receive URXIFG1 see Note 17 Maskable OFFEh USART1 transmit UTXIFG1 see Note 17 Maskable OFFE4n 2 P2IFG 0 see Notes 14 and 15 port P2 eight flags To Maskable OFFE2h P2IFG 7 see Notes 14 and 15 OFFEOh 0 lowest NOTES 14 Multiple source flags 15 Interrupt flags are located in the module not available on 5 430 1351 devices 16 Non maskable the individual interrupt enable bit can disable an interrupt event but the general interrupt enable can not disable it 17 MSP430x14x devices only Note Some MSP430 devices have different implementations See device datasheet for details 3 4 2 1 External Interrupts All eight bits of ports P1 and P2 are designed for interrupt processing of external events All individual I O bits are independently programmable Any combinations of inputs outputs and interrupt conditions are possible This allows easy adaptation to different I O configurations See the I O Ports chapter for more details on I O ports 3 22 Operating Modes 3 5 Operating Modes The MSP430 family was developed for ultralow power applications and uses different levels of operating modes The MSP430 operating modes shown in Figure 3 10 give advanced support to various requirements for ultralow power
222. EN Comment x 0 0 x x on on DCO Clock Needed for MCLK x 0 0 Clock Needed for SMCLK 0 0 1 see Note A off on DCO Clock Is Not Needed 0 1 X off on For MCLK and SMCLK 0 see Note B 0 1 off on Clock 15 Not Needed 0 1 x off on For SMCLK and MCLK 1 Note C off off DCO Clock Is Not Needed Note C SCGO Bit Switches Off DCOGEN NOTES A SMCLK does not need the DCOCLK signal if SMCLK is switched off SCG1 1 or DOCCLK is not selected for SMCLK SELS 0 B MCLK does not need the DCOCLK signal if MCLK is switched off CPUOff 1 or DOCCLK is not selected for MCLK SELM 1 1 C MCLK and SMCLK does not need the DCOCLK signal if The control bit SCGO in the status register can switch off SCGO 1 the DCOGEN Basic Clock Module 741 Digitally Controlled Oscillator 7 3 1 Operation of the DCO Modulator The modulator is intended to reduce a long accumulating period variation by mixing adjacent DCO periods On average a longer period variation can be minimized by mixing DCO periods The modulator accumulates a period of 32 DCOCLK clock cycles The MOD control bits define the mixing ratio of the DCO 1 period The remaining 32 MOD time slots use the DCO period If the modulation constantis 0 the DCO data in the control register defines the peri od The following formula defines the accumulating periods 32 MOD x tpco MOD x tpco 4 The modulator selects fqco or
223. Error Example for 2400 Baud The following data are assumed Baud rate 2400 BRCLK 32 768 Hz ACLK UxBR 13 since the ideal division factor is 13 67 m 6Bh m7 0 m6 1 m5 1 m4z0 13 1 m2 0 m1 1 and m0 1 The LSB m0 of the modulation register is used first 6 baud rate ur 9 Start bit Error 96 Daud rele BRCLK 0 1 x UxBR 1 1 x 100 2 54 Data bit DO Error Baud rate x 1 1 x UxBR 2 2 x 100 5 08 Data bit D1 Error Baud rate x 2 1 x UxBR 2 3 x 100 0 29 Data bit D2 Error Baud rate x 1 x UxBR 3 4 x 10096 2 8396 Data bit Error baud rale x 4 1 x UxBR 3 5 x 100 1 95 Data bit D4 Error baud tale x s 1 x UxBR 46 x 100 0 59 Data bit D5 Error Daud Fale x 6 1 x UxBR 5 7 100 3 13 Data bit D6 Error Baud Fale x 7 1 x UxBR 5 8 x 100 1 66 Data bit D7 Error Daud Tale x x UxBR 6 9 x 100 0 88 Parity bit Error 94 Baud x 9 x UxBR 7 10 x 10096 3 4296 Stop bit 1 Error Baud Fale x 10 1 x UxBR 221 x 100 1 37 Stop bit 2 Error Baud rate x 11 1 x UxBR 8 12 100 1 17 12 28 Baud Rate Considerations 12 7 2 Typical Baud Rates and Errors The standard baud rate data needed for the baud rate registers and the modulation register are listed in Table 12 6 for the 32 768 Hz watch crystal ACLK and MCLK ass
224. FFFh reset otherwise Set if dst contained 07Fh reset otherwise OscOff CPUOff and GIE are not affected The status byte of a process STATUS is incremented When it is equal to 11 a branch to OVFL is taken INC B STATUS CMPB 11 5 05 JEQ OVFL INCD W INCD B Syntax Operation Emulation Emulation Example Status Bits Mode Bits Example Example Instruction Set Overview Double increment destination Double increment destination INCD dst or INCD W dst INCD B dst dst 2 dst ADD 2 dst ADD B 2 dst The destination operand is incremented by two The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFEh reset otherwise Set if dst contained OFEh reset otherwise C Set if dst contained OFFFEh or OFFFFh reset otherwise Set if dst contained OFEh or OFFh reset otherwise V Set if dst contained O7FFEh or 07FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise OscOff CPUOff and GIE are not affected The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation which is stored in the system stack INCD SP Remove TOS by double increment from stack Do not use INCD B SP is a word aligned register RET The byte on the top of the stack is incremented by two INCD B 0 SP Byte on TOS is increment by two Instruction Set Description B 31 Instr
225. H BITCLK 27 n Even m 0 Divide By n Odd or n Even m 1 1 The modulation register LSB is first used for modulation which begins with the start bit A set modulation bit increases the division factor by one Example 12 1 4800 Baud Assuming a clock frequency of 32 768 Hz for the BRCLK signal and a required baud rate of 4800 the division factor is 6 83 The baud rate generation in the MSP430 USART uses a factor of six plus a modulation register load of 6Fh 0110 1111 The divider runs the following sequence 7 7 7 7 6 7 7 6 so The sequence repeats after all eight bits of the modulator are used Example 12 2 19 200 Baud Assuming a clock frequency of 1 04 MHz 32 x 32 768 Hz for the BRCLK signal and a required baud rate of 19 200 the division factor is 54 61 The baud rate generation in the MSP430 USART uses a factor of 54 36h plus a modulation register load of OD5h The divider runs the following sequence 55 54 55 54 55 54 55 55 and so on The sequence repeats after all eight bits of the modulator are used 12 6 Asynchronous Operation 12 3 3 Asynchronous Communication Formats The USART module supports two multiprocessor communication formats when asynchronous mode is used These formats can transfer information between many microcomputers on the same serial link Information is transferred as a block of frames from a particular source t
226. Hints for Low Power Applications in section 3 6 Memory 4 11 4 12 5 16 Bit CPU The MSP430 von Neumann architecture has RAM ROM and peripherals in one address space both using a single address and data bus This allows using the same instruction to access either RAM ROM or peripherals and also allows code execution from RAM Topic Page Gell CPU Registers 5 5 2 5 2 Addressing Modes ea e a 5 7 5 3 Instruction Set Overview 5 17 5 4xuinstructloniMapiter 2 5 23 5 1 CPU Registers 5 1 CPU Registers Sixteen 16 bit registers RO R1 and R4 to R15 are used for data and addresses and are implemented in the CPU They can address up to 64 Kbytes ROM RAM peripherals etc without any segmentation The complete CPU register set is described in Table 5 1 Registers RO R1 R2 and R3 have dedicated functions which are described in detail later Table 5 1 Register by Functions 5 1 1 Status register SR Constant generator CG1 Working register R5 Working register R13 R13 Working register R14 Working register R15 R15 The Program Counter PC The 16 bit program counter points to the next instruction to be executed Each instruction uses an even number of bytes two four or six and the program counter is incremented accordingly Instruction accesses are performed on word boundaries a
227. ISR The RETI return from interrupt instruction has no effect on the individual enable bits of the non maskable interrupts So the software must set the corresponding interrupt enable bit in the ISR before execution of the RETI instruction for the interrupt to be re enabled after the ISR A non maskable NMI interrupt can be generated by an edge on the RST NMI pin if NMI mode is selected an oscillator fault occurs if the oscillator fault interrupt is enabled or an access violation to the flash memory takes place if the access violation interrupt is enabled System Resets Interrupts and Operating Modes 3 5 MSP430 Interrupt Priority Scheme 3 3 MSP430 Interrupt Priority Scheme The interrupt priority of the modules as shown in Figure 3 4 is defined by the arrangement of the modules in the connection chain the nearer a module is to the CPU NMIRS the higher the priority Figure 3 4 Interrupt Priority Scheme Priority High Low Module m 1 PUC PUC Circuit OSCfault Flash ACCV Reset NMI WDT Security Key T Flash Security Key 4 5LSBs Reset and NMI as shown in Figure 3 5 only be used as alternative interrupts because they usethe same input pin The associated control bits are located in the watchdog timer control register shown in Figure 3 6 and are password protected 3 6 MSP430 Interrupt Priority Scheme
228. Instruction Set Overview Double decrement destination Double decrement destination DECD dst or DECD W dst DECD B dst dst 2 dst SUB 2 dst SUB B 2 dst The destination operand is decremented by two The original contents are lost N Set if result is negative reset if positive Z Set if dst contained 2 reset otherwise C Reset if dst contained 0 or 1 set otherwise V Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset OscOff CPUOff and GIE are not affected R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 words from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address must not be within the range EDE to EDE 0FEh Example MOV EDE R6 MOV 510 R10 L 1 MOV R6 TONI EDE 2 R6 DECD R10 JNZ L 1 Memory at location LEO is decremented by two DECD B LEO Decrement MEM LEO Decrement status byte STATUS by two DECD B STATUS Instruction Set Description B 27 Instruction Set Overview DINT Syntax Operation Emulation Description Status Bits Mode Bits Example B 28 Disable general interrupts DINT 0 GIE or OFFF7h AND SR SR NOT src AND dst dst BIC 8 SR All interrupts are disabled The co
229. Instruction Set Overview Jump if carry not set Jump if lower JNC label JNC label if C 0 PC 2 x offset gt PC if C 1 execute following instruction The status register carry bit C is tested If itis reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If C is set the next instruction following the jump is executed JNC jump if no carry lower is used for the comparison of unsigned numbers 0 to 65536 Status bits are not affected The result in R6 is added in BUFFER If an overflow occurs an error handling routine at address ERROR is used ADD R6 BUFFER BUFFER R6 BUFFER JNC CONT No carry jump to CONT Error handler start Continue with normal program flow Branch to STL2 if byte STATUS contains 1 or 0 CMPB 2 STATUS JLO STL2 STATUS lt 2 T STATUS gt 2 continue here Instruction Set Description B 39 Instruction Set Overview JNE JNZ Syntax Operation Description Status Bits Example B 40 Jump if not equal jump if not zero JNE label JNZ label If Z 0 PC 2x offset PC If Z 2 1 execute following instruction The status register zero bit Z is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is set the next instruction following the jump is executed Status bits are not affected Jump to address TONI if R7 and R8 have different c
230. JNZ Test_Busy1 Segment Erase Erase 1 or Mass Erase MEras 1 MOV FWKEY Erase amp FCTL1 select segment erase CLR amp 0F000h Dummy Write yes Test_Busy2 BIT BUSY amp FCTL3 JNZ Test_Busy2 End of Erase or XOR FXKEY LOCK amp FCTL3 Mass Erase C 5 3 5 Example Erase Flash Memory Segment Module in the Same Flash Memory Module via Software Disable all interrupt sources Disable all possible interrupt sources and watchdog and Watchdog MOV FWKEY Eras amp FCTL1 Enable Erase of Flash CLR amp OFAO0h Dummy Write to Flash Erase Segment 2 Program execution in information memory if MEras 1 Eras 0 FXKEY Lock amp FCTL3 Change Lock bit to 1 LOCK 1 The erase bit Eras is automatically reset Restore or Enable Required Enable those interrupt sources that should be accepted Interrupt Sources and Watchdog C 5 3 6 Code for Write Program Erase and Mass Erase LOCK 0 Eras 1 or MEras 1 Dummy Write to Flash Address in the Target Segment Software that controls write erase or mass erase can be located in the flash memory module and copied during execution into RAM In this case the code should be written position independent and should be loaded for instance to RAM before it is used The algorithm runs in RAM during the programming sequence to avoid conflict when the flash memory is written or erased O 26 Flash Memory Access via JTAG and Software In the f
231. K Input Channel Ax Use 4 8 16 or 64 ADC10CLKs If x 0 then x INCH else x x 1 If x 0 then x INCH 12 x ADC10CLK ENC 0 else x x 1 and Convert Use 5 0 0 12 x ADC10CLK MSC 1 and ENC 1 1 x ADC10CLK x 20 Conversion Completed Result to ADC10MEM ADC1OIFG Is Set 16 4 5 Switching Between Conversion Modes Changing the mode of operation of the ADC10 while the converter is not actively running is done simply by selecting the new mode of operation with the CONSEQ bits However if the conversion mode is changed while the converter is actively running intermediate and undesirable modes can be accidentally selected if both CONSEQ bits are changed in a single instruction Therefore the following mode changes should be avoided while the converter is running 0 gt 3 15 2 25 1 0 ADC10 Conversion Modes 16 4 6 Power Down 16 16 The intermediate modes are caused by the asynchronous clocks for the CPU and the ADC10 These intermediate modes can be avoided simply by changing only one CONSEQ bit per instruction For example to change from mode 0 to mode 3 while the converter is actively running the following instructions could be used BIS CONSEQ_0 amp ADC1OCTL1 Example 0 3 first C step is 0 1 BIS CONSEQ_1 amp ADC1OCTLI1 second step is 1 gt 3 Acceptable sequence modifications are 0 gt 1 05 2
232. K LFXT1CLK Start Up XT OscFault XT OscFault becomes active after XT2CLK and or LFXT1CLK stop oscilating The delay associated with the XT OscFault signal is approximately 50 us Figure 7 7 Oscillator Fault in Oscillator Error Condition Oscillator Error XT OscFault The oscillator fault signal returns to a logic low if the oscillator starts operating again The delay is typically 50 us When an XT oscillator has stopped and is then restarted the oscillator fault signal XT OscFault remains active until the oscillator starts operating and becomes inactive after a delay of typically 50 us Basic Clock Module 7 7 LFXT1 and XT2 Oscillators Figure 7 8 Oscillator Fault in Oscillator Error Condition at Start Up XT1Off XT2Off 85 E aA AN XT OscFault 7 2 4 Select DCO Oscillator for MCLK on XT Oscillator Fault 7 8 The DCO oscillator is selected automatically for MCLK if either one of the oscillators LFXT1 in HF mode only or XT2 is selected for MCLK source and this oscillator fails Since the DCO oscillator is now selected the NMI requested by the oscillator fault can be processed The DCO oscillator is switched on and the DCOCLK is switched to be the source for MCLK An NMI is processed even if the CPU is switched off CPUOFF 1 The 5 430 ultralow power system allows any enabled interrupt to be serviced from any
233. L x 1 the internal input signal simply follows the signal at the pin However if the PnSEL x bit is reset then the output of the latch and therefore the input to the other peripheral module represents the value of signal at the device pin just prior to the bit being reset 8 3 2 Port P3 P6 Schematic The pin logic of each individual port signal is shown in Figure 8 4 Figure 8 4 Schematic of Bits Pn x PnSEL x PnDIR x Direction Control From Module PnOUT x Module x OUT PnIN x Module x IN e Output MUX E eA Pad Logic gt Output zu a fece 4 o AL n 3 for Port3 4 for Port P4 5 for Port P5 and 6 for Port P6 X 0 to 7 according to bits O to 7 Digital I O Configuration 8 11 8 12 Chapter 9 Watchdog Timer This chapter discusses the Watchdog Timer Topic Page 9 The Watchdog Timer Ieri 9 2 9 1 The Watchdog Timer 9 1 The Watchdog Timer The primary function of the watchdog timer module WDT is to perform a controlled system restart after a software problem occurs If the selected time interval expires a system reset is generated If the watchdog function is not needed in an application the module can work as an interval timer to generate an interrupt after the selected time interval The WDT diagram is shown in Figure 9 1 Figure
234. L1 SSELO 0 Baud Rate Generator UCLKS UCLKI m ary ACLK e 2 Baud Rate Register SMCLK o 3 UOBR or U1BR SMCLK o Baud Rate Generator MR LSB First Transmit Shift Register gt e gt UTXD Transmit Buffer TXWake UOTXBUF or U1TXBUF CKPL UCLKI UCLKS Clock Polarity UCLK USART Peripheral Interface UART Mode 12 3 Asynchronous Operation 12 3 Asynchronous Operation In the asynchronous mode the receiver synchronizes itself to frames but the external transmitting and receiving devices do not use the same clock source the baud rate is generated locally 12 3 1 Asynchronous Frame Format The asynchronous frame format shown in Figure 12 3 consists of a start bit seven or eight data bits an even odd no parity bit an address bit in address bit mode and one or two stop bits The bit period is defined by the selected clock source and the data in the baud rate registers Figure 12 3 Asynchronous Frame Format Mark ST DO D6 PA SPjSP DIR 2nd Stop Bit SP 1 Parity Bit PENA 1 Address Bit MM 1 Optional Bit Condition 8th Data Bit CHAR 1 The receive RX operation is initiated by the receipt of a valid start bit It begins with a negative edge at URXD followed by the taking of a majority vote from three samples where two of the samples must be zero These samples occur at 2 n 2 and n 2 X of the BRCLK periods following the negative
235. M and Peripheral Organization ADC12 control and interrupt Timer B Timer B Timer A Timer A ADC12 conversion ADC12 conversion Multiplier Watchdog Timer Flash control Reserved Reserved Byte modules are peripherals that are connected to the reduced eight LSB MDB Access to byte modules is always by byte instructions The hardware in the peripheral byte modules takes the low byte the LSBs during a write operation Byte instructions operate on byte modules without any restrictions Read access to peripheral byte modules using word instructions results in unpredictable data in the high byte Word data is written into a byte module by writing the low byte to the appropriate peripheral register and ignoring the high byte The peripheral file address space is organized into sixteen frames as described in Table 4 2 Memory 4 9 RAM and Peripheral Organization Table 4 2 Peripheral File Address Map Byte Modules Address OOFOh OOFFh OOEOh OOEFh O0DOh 00DFh 00COh 00CFh 00BOh OOBFh 00AO0h OOAFh 0090h 009Fh 0080h 008Fh 0070h 007Fh 0060h 006Fh 0050h 005Fh 0040h 004Fh 0030h 003Fh 0020h 002Fh 0010h 001Fh 0000h 000Fh Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved ADC12 memory control USARTO USART1 Reserved System clock generator Comparator A Reserved Digital I O port P5 digital I O port P6
236. MCLK x f MCLK CPU Operating Mode SHT 0 0 SHT 1 SHT 2 5 3 Active mode NL 67 7 0 9 67 ELM 67 MCLK DCOCLK Active mode 6 7 25 67 MCLK LFXT1CLK Low power mode LPMO0 1 19 25 MCLK DCOCLK Low power mode LPM3 4 Calculation of f apc10CLk required because of 6 us wake time MCLK DCOCLK Low power mode LPMO0 1 19 25 MCLK LFXT1CLK Low power mode LPM3 4 Calculation of f apc10CLk required because of 6 us wake time MCLK LFXT1CLK 16 9 Controlling the Current Consumption of the ADC10 Module The initial setting of the control bits after a PUC turns off the entire ADC10 Once the ADC10 is powered up it consumes current in three blocks the ADC core the ADC voltage reference and the ADC voltage reference buffer 16 9 1 General Power Saving Features and Tips The ADC core and ADC voltage reference blocks can be switched on or off independently using control bits ADC10ON and REFON Some general power saving tips are listed below and discussed in more detail in the following sections ADC10 Controlling the Current Consumption of the ADC10 Module When using the internal reference when it is not routed externally the reference buffer automatically powers on when needed forthe sample and conversion cycle and powers off at the end of the conversion This reduces the total system power consumption When using AVcc and AVgg as reference voltages the internal reference can be powered off completely wit
237. MSP430F122 4KB 256 Flash 256B RAM MSP430F123 8KB 256 Flash 256B RAM 1 6 12x2 Devicest The 12x2 devices contain the following peripherals Basic Clock System on chip DCO one crystal oscillator Watchdog Timer General Purpose Timer Timer 16 bit timer with three capture compare registers PWM output Port1 2 Eight l Os each all with interrupt I O Port3 8 I Os each ADC10 10 bit A D USARTO COGO The 12x2 device family includes MSP430F 1222 4KB 256B Flash 256B RAM MSP430F 1232 8KB 256B Flash 256B RAM TAdvanced information future devices 1 7 13x Devices 1 8 14x Devices 13x Devices The 13x devices contain the following peripherals CO Basic Clock System two crystal oscillators Watchdog Timer General Purpose Timer Timer A3 16 bit timer with three capture compare registers and PWM output Timer 16 bit timer with three capture compare registers PWM output Port1 2 8 I Os each all with interrupt Port3 4 5 6 Eight I Os each Comparator_A precision analog comparator ideal for slope A D conversion ADC12 12 bit A D Not in MSP430C1351 USARTO The 13x device family includes MSP430F133 8KB 256 Flash 256B RAM MSP430F135 16KB 256 Flash 512B RAM MSP430F 1351 16KB ROM 512B RAM The 14x devices contain the following peripherals LDDD D OL Basic Clock System
238. NC 1 0 Inthis mode if ENC is reset the current conversion is immediately stopped The conversion results are unpredictable CONSEQz 0 ADC10BUSY x ENC 1 0 In these modes if ENC is reset the current conversion or sequence is completed and the conversion results are valid The conversion activities are stopped after the current conversion or sequence is completed ADC10 interrupt flag The ADC10IFG is set if register ADC10MEM has been loaded with the conversion result It is automatically reset when the interrupt service starts It may also be reset by software such as BIC ADC10IFG amp ADC10CTLO ADC10 interrupt enable An ADC10 interrupt request ADC10IFG 1 is accepted if the ADC1 OIE bit and the general interrupt enable bit GIE are set Turns on the 10 bit ADC core Settling time constraints must be met when the ADC10 core is powered up 0 Power consumption of the core is off No conversion will be started 1 ADC core is supplied with power If no A D conversion is needed ADC10ON can be reset to conserve power Reference voltage ON 0 The internal reference voltage is switched off No power is consumed from the reference voltage generator 1 The internal reference voltage is switched on The reference voltage generator consumes power When the reference generator is switched on the settling time of the reference voltage must be completed before the first sampling and conversion is started ADC10 ba ADC10 Con
239. OMI is input if STE is set high Interrupt and Control Functions 13 4 Interrupt and Control Functions The USART peripheral interface serves two main interrupt sources for transmission and reception Two interrupt vectors serve receive and transmit interrupt events The interrupt control bits and flags and enable bits of the USART peripheral interface are located in the SFR address range The bit functions are described below in Table 13 1 See the peripheral file map in Appendix A for the exact bit locations Table 18 1 USART Interrupt Control and Enable Bits SPI Mode Receive interrupt flag URXIFG Initial state reset by PUC SWRST Receive interrupt enable URXIE Initial state reset by PUC SWRST Receive transmit enablet USPIIEt Initial state reset by Transmit interrupt flag UTXIFG Initial state set by PUC SWRST Transmit interrupt enable UTXIEt Initial state reset PUC SWRST 1 Different for UART mode see Chapter 12 t Suffix 0 for USARTO and 1 for USART1 The USART receiver and transmitter operate in parallel and use the same baud rate generator in synchronous master mode In synchronous slave mode the external clock applied to UCLK is used for the receiver and the transmitter The receiver and transmitter are enabled and disabled together with the USPIIE bit 13 4 1 USART Receive Transmit Enable Bit Receive Operation The receive transmit enable bit USPIIE enables or disables collection of the bit s
240. Ob TBCLOh TBCLOa Oh TBR max Interrupt Events Time intervals can be produced with other modes as well where capture compare block 0 is used to determine the period Their handling is more complex since the sum of the old CCRx data and the new period can be higher than the TBCLO value When the sum CCRxold plus At is greater than the TBCLO data the old CCRO value must be subtracted to obtain the correct time interval Timer_B 11 11 Timer Modes 11 3 4 Timer Up Down Mode The up down mode is used if the timer period must be different from the TBR max clock cycles and if symmetrical pulse waveform generation is needed In up down mode the timer counts up to the content of compare latch TBCLO then back down to zero as shown in Figure 11 12 The periodis twice the value in the TBCLO latch Note If TBCLO gt TBR may the counter operates as if it were configured for continuous mode It will not count down from TBR max to zero LLLLLL Figure 11 12 Timer Up Down Mode Figure 11 13 Output TBCLO Oh The up down mode also supports applications that require dead times between output signals For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the following example see Figure 11 13 the tgeag is
241. Only EQUO delayed is used in up mode not EQUO EQUO is active high when TAR CCRO EQUO delayed is active high when TAR 0 Timer_A 10 21 Timer Modes Table 10 2 State of OUTx at Next Rising Edge of Timer Clock Mode EQUO EQUx D 0 X X X OUTx bit 1 X 0 OUTx no change X 1 1 set 2 0 0 OUTx no change 0 1 OUTx toggle 1 0 0 reset 1 1 1 set 3 0 0 OUTx no change 0 1 1 set 1 0 0 reset 1 1 1 set 4 X 0 OUTx no change x 1 OUTx toggle 5 0 OUTx no change X 1 0 reset 6 0 0 OUTx no change 0 1 OUTx toggle 1 0 1 set 1 1 0 reset 7 0 0 OUTx no change 0 1 0 reset 1 0 1 set 1 1 0 reset 10 5 3 Output Examples The following are some examples of possible output signals using the various timer and output modes 10 5 3 1 Output Examples Timer in Up Mode The OUTx signal is changed when the timer counts up to the CCRx value and rolls from CCRO to zero depending on the output mode as shown in Figure 10 24 10 22 Figure 10 24 Output Examples Timer Up Mode Timer Modes OFFFFh Example EQU1 Used CCRO CCR1 Oh ID d Output Mode 1 Set S Output Mode 2 PWM Toggle Reset i 5 2 Output Mode 3 PWM Set Reset im eem im mE Output Mode 4 Toggle oceani Output Mode 5 Reset Sas m Output Mode 6 PWM Toggle Set ER ho Output Mode 7 PWM Reset Set EQUO EQU1 EQUO EQUi EQUO Interrupt Events 10 5 3 2 Output Examples Ti
242. OscOff CPUOff and GIE are not affected The contents of the status register and R8 are saved on the stack PUSH SR save status register PUSH R8 save R8 The contents of the peripheral TCDAT is saved on the stack PUSH B amp TCDAT save data from 8 bit peripheral module address TCDAT onto stack XL SO Note The System Stack Pointer The system stack pointer SP is always decremented by two independent of the byte suffix O C ACA Syntax Operation Emulation Description Status Bits Return from subroutine RET SP 5 2 gt 5 MOV SP PC Instruction Set Overview The return address pushed onto the stack by a CALL instruction is moved to the program counter The program continues at the code address following the subroutine call Status bits are not affected Instruction Set Description B 45 Instruction Set Overview RETI Syntax Operation Description Status Bits Mode Bits Example Return from interrupt RETI TOS SR SP 2 SP TOS PC SP 2 SP The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents The stack pointer SP is incremented by two The program counter is restored to the value at the beginning of interrupt service This is the consecutive step after the
243. P R5 gt PC Indirect indirect R5 R5 Call on the address contained in the word pointed to by R5 and increment pointer in R5 The next time S W flow uses R5 pointer it can alter the program execution due to access to next address in a table pointed to by R5 SP 2 5 SP 2 5 GSP R5 gt PC Indirect indirect R5 with autoincrement X R5 Call on the address contained in the address pointed to by R5 X e g table with address starting at X X be an address or a label SP 2 2 SP PC 2 5 SP X R5 2 PC Indirect indirect R5 X Instruction Set Description B 17 Instruction Set Overview CLR W CLR B Syntax Operation Emulation Description Status Bits Example Example Example Clear destination Clear destination CLR dst CLR W dst CLR B dst 0 dst MOV 0 dst MOV B 0 dst The destination operand is cleared Status bits are not affected RAM word TONI is cleared CLR TONI 0 gt Register R5 is cleared CLR R5 RAM byte TONI is cleared CLR B TONI 0 gt CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Overview Clear carry bit CLRC 0 gt BIC 1 SR The carry bit C is cleared The clear carry instruction is a word instruction N Not affected Z Not affected C Cleared V Not affected OscOff CPUOff and GIE are not affected The 16 bit decimal coun
244. PUOff and GIE are not affected The zero bit in the status register is cleared CLRZ Instruction Set Description B 21 Instruction Set Overview CMPI W CMP B Syntax Operation Description Status Bits Mode Bits Example Example Example B 22 Compare source and destination Compare source and destination CMP src dst or CMP W src dst CMP B src dst dst NOT src 1 or dst src The source operand is subtracted from the destination operand This is accomplished by adding the 1s complement of the source operand plus 1 The two operands are not affected and the result is not stored only the status bits are affected N Set if result is negative reset if positive src gt dst Z Set if result is zero reset otherwise src dst C Set if there is a carry from the MSB of the result reset otherwise V Set if an arithmetic overflow occurs otherwise reset OscOff CPUOff and GIE are not affected R5 and R6 are compared If they are equal the program continues at the label EQUAL CMP R5 R6 R5 R6 JEQ EQUAL YES JUMP Two RAM blocks are compared If they are not equal the program branches to the label ERROR MOV NUM R5 number of words to be compared L 1 amp BLOCK1 amp BLOCK2 Are Words equal JNZ ERROR No branch to ERROR DEC R5 Are all words compared JNZ L 1 No another compare The RAM bytes addressed by EDE and TONI are compared If they are equal the pr
245. Peripheral Interface UART Mode 12 11 Interrupt and Enable Functions 12 4 2 USART Transmit Enable Bit The transmit enable bit UTXE shown in Figure 12 13 enables or disables a character transmission on the serial data line If this bit is reset the transmitter is disabled but any active transmission does not halt until the data in the transmit shift register and the transmit buffer are transmitted Data written to the transmit buffer before UTXE has been reset may be modified or overwritten even after UTXE is reset until it is shifted to the transmit shift register For example if software writes a byte to the transmit buffer and then resets UTXE the byte written to the transmit buffer will be transmitted and may be modified or overwritten until it is transferred into the transmit shift register However after the byte is transferred to the transmit shift register any subsequent writes to UxTXBUF while UTXE is reset will not result in transmission but UXTXBUF will be updated with the new value Figure 12 13 State Diagram of Transmitter Enable 12 12 Transmit Disable UTXE 0 UTXE 0 And Last Buffer No Data Written to Transmit Buffer ud Completed UTXE 1 Data Written to Idle State Transmitter Enabled Handle Interrupt Conditions Character Transmitted Entry Is Transmitted When UTXE is reset and the current transmission is completed new data written to the t
246. Processing Table 3 6 MSP430x11xx Interrupt Flag Registers 1 and 2 Bit Position Short Form Initial State Comments IFG1 0 WDTIFG Set Set on watchdog timer overflow in watchdog mode or security key violation Or reset Reset with VCC power up or a reset condition at the RST NMI pin in reset mode IFG1 1 OFIFG Set Flag set on oscillator fault IFG1 2 Not implemented IFG1 3 Not implemented IFG1 4 NMIIFG Reset Set through the RST NMI pin IFG1 5 Not implemented IFG1 6 Not implemented IFG1 7 Not implemented IFG2 0 Not implemented IFG2 1 Not implemented IFG2 2 Not implemented IFG2 3 Not implemented IFG2 4 Not implemented IFG2 5 Not implemented IFG2 6 Not implemented IFG2 7 Not implemented Note Theconfiguration of some MSP430 devices may differ from those in above table Refer to specific device data sheets for individual configurations 3 14 Interrupt Processing Table 3 7 MSP430x12xx Interrupt Flag Registers 1 and 2 Bit Position Short Form IFG1 0 IFG1 1 IFG1 2 IFG1 3 IFG1 4 IFG1 5 IFG1 6 IFG1 7 IFG2 0 IFG2 1 IFG2 2 IFG2 3 IFG2 4 IFG2 5 IFG2 6 IFG2 7 Note WDTIFG OFIFG NMIIFG URXIFGO UTXIFGO Initial State Set Or reset Set Reset Reset Set Comments Set on watchdog timer overflow in watchdog mode or security key violation Reset with VCC power up or a reset condition at the RST NMI pin in reset mode Flag set on oscillator fault Not implemented Not imple
247. Px 0 EQUx ue 0 0 4 ES 0 Set CCIFGx GND i G Vcc Timer Synchronize ae CCMx1 CCMx0 Clock Capture SCSx apture 0 0 Disabled 0 1 Positive Edge 1 0 Negative Edge 1 1 Both Edges CCIx The capture signal can also be synchronized with the timer clock to avoid race conditions between the timer data and the capture signal This is illustrated in Figure 11 19 The bit SCSx in capture compare control register CCTLx selects the capture signal synchronization Figure 11 19 Capture Signal Timer Clock Timer CCIx gt CCIFGx 11 16 Timer Modes Applications with slow timer clocks can use the nonsynchronized capture signal In this scenario the software can validate the data and correct it if necessary as shown in the following example Software example for the handling of asynchronous capture signals The data of the capture compare register CCRx are taken by the software in the according interrupt routine they are taken only after CCIFG was set The timer clock is much slower than the system clock MCLK CCRXx Int hand Start of interrupt handler CMP amp CCRx amp TBR Test if the data CCRX TBR JEQ Data Valid MOV amp TBR amp CCRx The data in CCRx is wrong use the timer data Valid ae T The data in CCRx are valid RETI Overflow logic is provided with each
248. R counts toO TBR counts 0 TBR counts toO TBR counts toO TBR counts toO TBR counts to 0 orto TBCLO orto TBCLO orto TBCLO orto TBCLO orto TBCLO orto TBCLO orto TBCLO TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBCLO TBCL1 TBCL2 TBCL4 TBCL5 TBCL6 TBCL1 TBCL2 updated TBCL4 updated TBCL5 TBCL6 updated TBR counts to 0 simultaneously when TBR counts simultaneously when TBR counts simultaneously when TBR counts to 0 to 0 to 0 TBCL1 TBCL2 updated TBCL3 TBCL4 updated TBCL5 TBCL6 updated TBR counts to 0 simultaneously when TBR simultaneously when simultaneously when counts to 0 TBR counts to 0 TBR counts to 0 TBR counts to 0 TBCL1 TBCL2 updated TBCL3 TBCL4 updated TBCL5 TBCL6 updated orto TBCLO simultaneously when TBR counts to simultaneously when TBR counts to simultaneously when TBR counts to 0 or to TBCLO O orto TBCLO Oorto TBCLO 02 Jo 2 3 TBCL1 TBCL2 loaded immediately TBCL3 TBCL4 loaded immediately TBCL5 TBCL6 loaded immediately 0 3 Immediate when the corresponding TBCCRx when the corresponding TBCCRx when the corresponding TBCCRx register is loaded register is loaded register is loaded 2 TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBCLO TBCL1 TBCL2 TBCL4 TBCL5 TBCL6 t Timer B3 has only three CCR blocks TBCCRO TBCCR1 and TBCCR2 The load conditions for TBCL3 4 5 6 are
249. RBUET ADDRESS PRIORITY Power up external reset WDTIFG Note1 R FFFEh 15 highest watchdog KEYV see Note 1 eset 2199 NMIIFG see Notes 1 and 4 on maskable NMI oscillator fault flash access violation ORIF Gi s66 Noles T and4 ron 109 308 OFEEGR y ACCVIFG see Notes 1 4 and 5 non maskable LL LLL Lw I 9 orn te mera or scenes stave 9 Oana CCIFG2 DEM 0010 I O Port P2 eight flags P2IFG 0 to P2IFG 7 see Note 3 see Notes 1 and 2 maskable OFFE6h P1IFG 0 to P1IFG 7 Port P1 flags C 1 and 2 OFFE4h OFFE2h NOTES Multiple source flags Interrupt flags are located in the module There are eight Port P2 interrupt flags but only six Port P2 I O pins P2 0 5 are implemented on the 11x1 devices non maskable the individual interrupt enable bit can disable an interrupt event but the general interrupt enable cannot Nonmaskable neither the individual nor the general interrupt enable bit will disable an interrupt event Flash devices only MSP430x11x1 devices only MSP430x11x2 devices only PONE NO 3 20 Interrupt Processing Table 3 15 Interrupt Sources Flags and Vectors of MSP430x12xx Configurations SYSTEM WORD INTERRUPT SOURCE INTERRUPT FLAG INTERRUPT ADDRESS PRIORITY Power up external reset WDTIFG see Note 8 watchdog KEYV see Note 8 Reset OFFFEh 15 highest maskabl Nl esi eu fash S INI
250. Register CCRO 501 CCIS00 OM02 01 OMOO CCIOA ooh m Capture 720e HRP GND utput Unit EQUO CCIO CCM01 CCMOO ILL Capture Compare Register CCIS11 CCIS10 4 15 0 12 OM11 OM10 Capture Compare bars Register CCR1 o CCHB 9 Capture u GND Mode Output Unit 1 TE EQU1 CCIT 11 CCM10 4 1 lI Capture Compare Register Le USUS PS 0 CCI2A 0 0 NE Register CCR2 o Capt Qut2 apture GND 9 EQU2 2 CCM21 CCM20 EU CR a a ILC INSCR Sa Ss ee P EUR M 4 Timer_A 10 3 Timer A Operation 10 2 Timer A Operation The 16 bit timer has 4 modes of operation selectable with the MCO and MC1 bits in the TACTL register The timer increments or decrements depending on mode of operation with each rising edge of the clock signal The timer can be read or written to with software Additionally the timer can generate an interrupt with its ripple carry output when it overflows 10 2 1 Timer Mode Contr
251. Reserved ADC10 ADC10 ADC10 ADC10 048h TB CT B1 Fetch ro ro r 0 0 ro ro rw 0 rw 0 rw The ADC10Fetch bit is for debugging purposes only If set it delays the data transfer until the present CPU software instruction is completed This bit should normally be reset The ADC10B 1 indicates if block 1 or block 2 is filled with ADC10 conversion results The initial state is reset The ADC10B1 bitis valid only after the ADC10IFG has been set the first time during opera tion of the DTC Writing the start address ADC10SA register resets the ADC10IFG flag 1 Block 1 SA to SA 2n 2 is filled with ADC10 conversion results 2 Block 2 SA 2n to SA 4n 2 is filled with ADC10 conversion results Note Bit ADC10B1 is useful only in two block mode ADC10TB 1 The ADC10CT bit enables the DTC to transfer data continuously 0 The data transfer stops after the block is transferred in one block mode or after both blocks are transferred in two block mode 1 The data is transferred continuously DTC operation is stopped only if the ADC10CT bit is reset or if any data is written into the start address register ADC10SA Note that ifthe ADC10CT bitis reset during a block transfer the block transfer is completed suc cessfully in one block mode and both block transfers are completed successfully in two block mode See also the state diagrams shown in Figures 16 17 and 16 19 ADC10TB the operation of the DTC writes the data into one o
252. S RRA B SP TOS x 0 5 0 5 x R5 x 0 5 0 25 x R5 TOS ADD B SP R5 5 0 5 5 0 25 0 75 x R5 R5 RRC W RRC B Syntax Operation Description Instruction Set Overview Rotate right through carry Rotate right through carry RRC dst or RRC W dst RRC dst C MSB MSB 1 LSB 1 gt LSB gt The destination operand is shifted right one position as shown in Figure 6 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit C Figure B 9 Destination Operand Carry Right Shift Status Bits Mode Bits Example Example Word 15 0 ue Byte 7 0 N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Loaded from the LSB V Setif initial destination is positive and initial carry is set otherwise reset OscOff CPUOff and GIE are not affected R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC R5 R5 2 8000h R5 R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC B R5 R5 2 80h R5 low byte of R5 is used Instruction Set Description B 51 Instruction Set Overview SBC W SBC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Subtract borrow from destination Subtract borrow from destination SBC dst or SBC W dst SBC B dst dst OFFFFh C d
253. SP as an argument to the PUSH and POP instructions are described below Figure 5 4 PUSH SP and POP SP PUSH SP POP SP ann feel SP SP4 SP2 SP4 The stack pointer is changed after The stack pointer is not changed after a PUSH SP POP a PUSH SP instruction SP instruction sequence The POP SP instruction places SP1 into the stack pointer SP SP2 SP1 After the sequence PUSH SP SP1 is stack pointer after this instruction POP SP SP2 is stack pointer after this instruction The stack pointer is two bytes lower than before this sequence 16 Bit CPU 5 4 CPU Registers 5 1 3 The Status Register SR The status register SR contains the following CPU status bits uv Overflow bit SCG1 System clock generator control bit 1 Li SCGO System clock generator control bit 0 OscOff Crystal oscillator off bit Jg CPUOff CPU off bit GIE General interrupt enable bit g N Negative bit uz Zero bit g C Carry bit Figure 5 5 shows the SR bits Figure 5 5 Status Register Bits 15 9 8 7 0 OSC CPU Reserved For Future Enhancements SCG1 SCGO rw 0 Table 5 2 describes the status register bits Table 5 2 Description of Status Register Bits Bit Description V Overflow bit Set if the result of an arithmetic operation overflows the signed variable range bit is valid for both data formats byte and word ADD B ADDC B Set when Positive Positive Negative Negat
254. SY Shae erased tena ur Mass Erase 5296 fx Segment Erase t erase 4817 fx The erase cycle completes successfully when none of the following restrictions is violated The selected clock source is available until the cycle is completed Lj The predivider should not be modified during the operation No further access to the flash memory module is performed while BUSY is set B Noread of data from this block B write into this block B No further erase of this block An access will result in setting the KEYV bit and requesting an NMI interrupt The NMI interrupt routine should handle such violations Lj The supply voltage should be within the devices electrical specifications defined in the respective data sheet however slight variations can be tolerated Control bit BUSY indicates an active erase cycle It is set immediately after a dummy write starts the timing generator It remains set until the entire erase cycle is completed and the erased segment or block is ready to be accessed again The BUSY bit can not be set by software But it can be reset In case of emergency set the emergency exit EMEX bit and the erase operation will be stopped immediately BUSY bit is reset One example of stop erase by soft ware is when the supply voltage drops drastically and the operating conditions of the controller are exceeded Another example is when the timing of the erase cycle gets out of
255. Sref 0 INCH 3 INCH 2 INCH 1 INCH O 008bEh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 pu ADC12MCTL13T EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 008Dh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTL12T EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 008Ch rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTL117 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 008Bh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTL10T EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 008Ah rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTL9T EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 0089h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTL8T EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 0088h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTL7T EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 0087h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTL6T EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 0086h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTL5T EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 0085h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTL4T EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 INCH O 0084h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12MCTLS3T
256. TC CPU clock cycles ADC10Int 6 MOV amp ADC10MEM 0 Rx 6 INCD Rx 1 RETI 5 N 18 The interrupt handler only moves the data to memory This SW example needs to have register Rx reserved only for the ADC10 Maximum conversion rate CRate 4 18 x 200E 9 x 100 CRate 11 1 ksps Using DTC CPU clock cycles DTC requires 1 MCLK 1 Ihe data transfer stops the CPU for 1 clock cycle to transfer the data to the destination Maximum conversion rate CRate 4 1 x 200E 9 x 100 CRate 200 ksps 16 8 1 DTC Operation 16 28 A DTC data transfer is triggered each time a conversion result is loaded into the ADC10MEM buffer if DTC is enabled and properly initialized When the DTC operation is employed the ADC10IFG flag is not set with each update of the ADC10MEM buffer Instead it is set after a complete block of results has been transferred The DTC supports transfers of one or two blocks of n conversion results see description of bit ADC10TB in the DTC register description The two block Data Transfer Control High Speed Conversion Support transfer mode allows for CPU operation on one block of data while the other block is being transferred In addition the DTC has a one time through the block s mode or a continuous transfer mode When the continuous transfer mode is enabled ADC10CT 1 the DTC continuously transfers ADC10 con version results in either one block mode or two block mode un
257. The Comparator A module includes Comparator with on off capability and no input hysteresis Internal analog voltage reference generator Internal reference levels available externally Input multiplexer to exchange the comparator terminals Software selectable RC filter at the comparator output One interrupt vector O O O O O L The Comparator_A is implemented in MSP430x11x1 MSP430x12x MSP430x13x and MSP430x14x devices Topic Page 14 4 Comparator A 14 2 14 2 Comparator A Description 14 3 14 3 Comparator A Control Registers 14 6 14 4 Comparator in Applications 14 9 14 1 Comparator A Overview 14 1 Comparator A Overview The primary function of the comparator module is to support precision A D slope conversion applications battery voltage supervision and monitoring of external analog signals The comparator is controlled via twelve control bits in registers CACTL1 and CACTL2 Figure 14 1 Schematic of Comparator A CAOUT to Internal Module CAOUT to External Pin Lp Set CAIFG Flag 0 Voc iid CAEX O _ CAON T 9 ol cao 4 Low Pass Filter CA0 96 S07 0 Q Q 0 Ao olo o OM 16 e Q caist i So 0 o_o 0v P2CA1 T 2 0 us 21
258. Until the SWRST bit is reset all affected logic is held in the reset state This implies that after a system reset the USART must be reenabled by resetting this bit The receive and transmit enable flags URXE and UTXE are not altered by SWRST The SWRST bit resets the following bits and flags URXIE UTXIE URXIFG RXWAKE TXWAKE RXERR PE and FE The SWRST bit sets the following bits UTXIFG TXEPT 7 Note The USART initialization sequence should be Initialize per application requirements while leaving SWRST 1 Clear SWRST Enable interrupts if desired Bit 1 Bit 2 Multiprocessor mode address idle line wake up Two multiprocessor protocols idle line and address bit are supported by the USART module The choice of multiprocessor mode affects the operation of the automatic address decoding functions MM 0 Idle line multiprocessor protocol MM 1 Address bit multiprocessor protocol The conventional asynchronous protocol uses MM bit reset Mode or function of USART module selected The SYNC bit selects the function of the USART peripheral interface module Some of the USART control bits have different functions in UART and SPI mode SYNC 0 UART function is selected SYNC 1 SPI function is selected Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Control and Status Registers The listen bit selects if the transmitted data is fed back internally to the receiver Liste
259. V POR t K Delay If power to the chip is cycled the supply voltage Vcc must fall below the V min see Figure 3 3 to ensure that another POR signal occurs when Vcc is powered up again If Voc does not fall below V mis during a cycle or a glitch a POR is not generated and power up conditions do not set correctly Figure 3 3 Power on Reset Timing on Slow Voc Rise Time V V POR V min e Vec N No POR POR RES POR System Resets Interrupts and Operating Modes 3 3 System Reset and Initialization 3 1 2 Device Initialization After System Reset 3 4 After a device reset POR PUC combination the initial system conditions are d d Lj d d I O pins switched to input mode I O flags are cleared as described in the I O chapter Other peripherals and registers are initialized as described in their respective chapters Status register is reset Program counter is loaded with address contained at reset vector location OFFFEh CPU execution begins at that address After a system reset the user program can evaluate the various flags to determine the source of the reset and take appropriate action The initial state of registers and peripherals is discussed in each applicable section of this manual Each register is shown with a key indicating the accessibility of the register and the initial condition for example rw 0 or rw 0 In these e
260. V R5 Invert this result back to 0 9 R5 NOT R5 06012h SETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 10000 R5 1 R6 R6 R5 1 4137 06012 1 1 0150 0150 Instruction Set Description B 53 Instruction Set Overview SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1 gt BIS 4 SR The negative bit N is set N Set Z Not affected C Not affected V Not affected OscOff CPUOff and GIE are not affected Instruction Set Overview SETZ Set zero bit Syntax SETZ Operation 1 gt 2 Emulation BIS 2 SR Description The zero bit Z is set Status Bits N Not affected Z Set C Not affected V Not affected Mode Bits OscOff CPUOff and GIE are not affected Instruction Set Description B 55 Instruction Set Overview SUBLW SUB B Syntax Operation Description Status Bits Mode Bits Example Example Subtract source from destination Subtract source from destination SUB src dst or SUB W src dst SUB B src dst dst NOT src 1 gt dst or dst src dst The source operand is subtracted from the destination operand by adding the source operand s 1s complement and the constant 1 The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif t
261. WIE w Error Address After a Character Is Received 0 O O O Bit 4 Bit 5 Bit 6 Bit 7 X 1 X Unchanged Set Unchanged Set Set Receives all characters Unchanged 0 1 1 0 1 1 Set X 0 1 X 0 1 lt x x The break detect bit BRK is set when a break condition occurs and the URXEIE bit is set The break condition is recognized if the RXD line remains continuously low for at least 10 bits beginning after a missing first stop bit It is not cleared by receipt of a character after the break is detected but is reset by a SWRST a system reset or by reading the UxRXBUF The receive interrupt flag URXIFG is set if a break is detected The overrun error flag bit OE is set when a character is transferred into the UXRXBUF before the previous character is read out The previous character is overwritten and lost OE is reset by a SWRST a system reset or by reading the UXRXBUF The parity error flag bit PE is set when a character is received with a mismatch between the number of 1s and its parity bit The parity checker includes the address bit used in the address bit multiprocessor mode in the calculation The flag is disabled if parity generation and detection are not enabled In this case the flag is read as 0 It is reset by SWRST a system reset or by reading the UxRXBUF The framing error flag bit FE is set when a character is received with 0 stop bit and is loaded into the rece
262. WM capability Slope A D conversion all devices Integrated USART s Watchdog Timer Multiple with extensive interrupt capability Integrated programmable oscillator 32 kHz crystal oscillator all devices 450 kHz 8 MHz crystal oscillator selected devices Powerful easy to use development tools including Simulator including peripheral and interrupt simulation C compiler Assembler Linker Emulators Flash emulation tool Device programmer Application notes Example code 1 2 11x Devices 1 3 11x1 Devices 11x Devices Lj Versatile ultralow power device options including Masked ROM OTP in system programmable Flash in system programmable EPROM UV erasable in system programmable 40 C to 85 C operating temperature range Up to 64K addressing space Memory mixes to support all types of applications The 11x devices contain the following peripherals Lj Basic Clock System on chip DCO one crystal oscillator Watchdog Timer General Purpose Timer Lj Timer 16 bit timer with three capture compare registers and PWM output J 1O Port 2 Eight l Os each all with interrupt The 11x device family includes MSP430C111 2KB ROM 128B RAM MSP430C112 4KB ROM 256B RAM MSP430P112 4KB OTP 256B RAM PMS430E112 4KB EPROM 256B RAM MSP430F110 1KB 128 Flash 128B RAM MSP430F112 4KB 256B Flash 256B RAM The 11x1 devices contain the following peripherals Basic Clock System on chip DCO
263. XD URXS L LLL a The interrupt handler must reset the URXSE bit in control register UxCTL to prevent further interrupt service requests from the URXS signal and to enable the basic function of the receive interrupt flag URXIFG 12 24 Utilizing Features of Low Power Modes ck ck ck ck ck kk ck ck kk Ck ck ck ck KKK ck kk Ck Ck ko ck kk Ck Ck ck ck ck kk ck ck ck kk Ck ck Sk ko Mk Mk Sk kc k ko ko ko kock ok Interrupt handler for frame start condition and Character receive Acc kk ck ck ck ck ck ck ck ck ck 0k 00k ck kk kk ck ck ck ck ck ck ck ck ck Ck Ck Ck UORX Int BIT B URXIFGO amp IFG2 test URXIFG signal to JNE ST COND check if frame start condition ST COND BIC B 4URXSE amp UOTCTL clear ff signal URXS stop further interrupt requests BIS B 4URXSE amp UOTCTL Prepare FF URXS for next frame start bits and set the conditions to run the clock needed for UART RX Ne Ne Ne Note Break Detect BRK Bit With Halted UART Clock If the UART operates with the wake up on start condition mode and switches off the UCLK whenever a character is completely received a communication line break cannot be detected automatically by the UART hardware The break detection requires the baud rate generator BRSCLK but it is stopped upon the missing UCLK 12 6 2 Maximum Utilization of Clock Frequency vs Baud Rate UART Mode The current consumpt
264. a Tables 0200h Data Memory RAM Word Byte 01 Timer Word 16 Bit Peripheral Modules ADC 0100h OFFh 1 0 LCD Bi i 8 Bit Peripheral Modules 8bT C yte OFh Oh Special Function Registers SFR Byte The memory data bus MDB is 16 or 8 bits wide For those modules that can be accessed with word data the width is always 16 bits For the other modules the width is 8 bits and they must be accessed using byte instructions only The program memory ROM and the data memory RAM can be accessed with byte or word instructions Figure 4 2 Memory Data Bus Address Range 0000h 00 8 Bit Peripheral Modules Byte Word 16 Bit Peripheral Modules Byte Access Access Word Access 4 2 Data in the Memory 4 2 Data in the Memory Bytes are located at even or odd addresses as shown in Figure 4 3 However words are only located at even addresses Therefore when using word instructions only even addresses may be used The low byte of a word is always at an even address The high byte of a word is at the next odd address after the address of the word For example if a data word is located at address xxx2h then the low byte of that data word is located at address xxx2h and the high byte of that word is located at address xxx3h Figure 4 3 Bits Bytes and Words a Byte Organized Memory xxxAh xxx9h xxx8h xxx7h xxx6h Word High Byte xxx5h Word Low Byte xxx4h Mem
265. ake bit is set when a received character is an address character and is transferred into the receive buffer Address bit multiprocessor mode RXWake is set when the address bit is set in the character received Idle line multiprocessor mode RXWake is set if an idle URXD line is detected 11 bits of mark level in front of the received character RXWake is reset by accessing the receive buffer UxRXBUF by a USART software reset or by a system reset PUC signal The receive wake up interrupt enable bit URXWIE selects the type of character to set the interrupt flag URXIFG URXWIE 0 Each character received sets the URXIFG URXWIE 1 Only characters that are marked as address characters set the interrupt flag URXIFG It operates identically in both multiprocessor modes The wake up interrupt enable feature depends on the receive erroneous character feature See also Bit 3 URXEIE The receive erroneous character interrupt enable bit URXEIE selects whether an erroneous character is to set the interrupt flag URXIFG URXEIE 0 Each erroneous character received does alter the interrupt flag URXIFG URXEIE 1 All characters can set the interrupt flag URXIFG as described in Table 12 4 depending on the conditions set by the URXWIE bit USART Peripheral Interface UART Mode 12 19 Control and Status Registers Table 12 4 Interrupt Flag Set Conditions 12 20 Char Char Description Flag URXIFG URXEIE URX
266. ake up interrupt feature in the receive operation and sends wake up conditions along with a transmission Avoiding activity on insignificant characters reduces consumption of MSP430 resources and the system can remain in the most efficient power conserving mode In addition to the multiprocessor modes rejecting erroneous characters saves 5 430 resources This practice prevents interrupt handling of the erroneous characters The processor waits in the most efficient power conserving mode until a character is processed 12 7 Baud Rate Considerations 12 26 The MSP430 baud rate generator uses a divider and a modulator A given crystal frequency and a required baud rate determines the required division factor N N BRCLK baud rate The required division factor N usually has an integer part and a fraction The divider in the baud rate generator realizes the integer portion of the division factor N and the modulator meets the fractional part as closely as possible The factor N is defined as n i N UxBR 15 mi n Where N Target division factor UxBR 16 bit representation of registers UXBR1 and UxBRO Actual bit the frame n Number of bits in the frame mj Data of the actual modulation bit Band aas BRCLK _ BRCLK UxBR m 0 Baud Rate Considerations 12 7 1 Bit Timing in Transmit Operation The timing for each individual bit in one frame or character is the sum of the actual bit timings as shown in Figu
267. al modules that are word oriented are mapped into the address space from 100h up to 01FFh Random Access Memory RAM can be used for both code and data memory Code accesses are always performed on even byte addresses The instruction mnemonic suffix defines the data as being word or byte data Example MOV B TXDATA amp UTXBUFO Byte access ADD R5 SUM_A ADD W R5 SUM Word access ADDC SUM B ADDC W SUM A Word access A word consists of two bytes a high byte bit 15 to bit 8 and a low byte bit 7 to bit as shown in Figure 4 5 It must always align to an even address Figure 4 5 Byte and Word Operation 4 6 ADD B Byte1 Byte2 Byte 012h XXX9h Byte 012h 034h 046h Byte2 034h xxx8h Word1 High Byte 056h xxx7h Word1 Low Byte 078h xxx6h ADD W Word Word2 2 Low Byte OBCh xxx4h All operations on the stack and PC are word operations and use even aligned memory addresses Inthe following examples word to word and byte to byte operations show the results of the operation and the status bit information Example Word Word Operation R5 OF28Eh EDE EQU 0212h Mem 0F28Eh OFFFEh Mem 0212h 00112h ADD R5 amp EDE Mem 0212h 00110h C 1 Z 0 N 0 Example Byte Byte Operation R5 0223h EDE EQU 0202h Mem 0223h O5Fh Mem 0202h 043h ADD B R5 amp EDE Mem 0202h 2 C 0 Z 0 N 1 Figure 4 6 shows the register byte and byte register operations Figure 4
268. all functional blocks and a reduced instruction set applicable to all functional blocks as illustrated in Figure 2 1 See specific device data sheets for complete block diagrams of individual devices Figure 2 1 MSP430 System Configuration Oscillator ACLK System Program Data Port V O Port VO Port Clock MCLK MAB 16 Bit MDB 16 Bit Misc Logic gt Module Select Comparator 2 2 Central Processing Unit 2 2 The CPU incorporates a reduced and highly transparent instruction set and a highly orthogonal design It consists of a 16 bit arithmetic logic unit ALU 16 registers and instruction control logic Four of these registers are used for special purposes These are the program counter PC stack pointer SP status register SR and constant generator CGx All registers except the constant generator registers R3 CG2 and part of R2 CG1 can be accessed using the complete instruction set The constant generator supplies instruction constants and is not used for data storage The addressing mode used on CG1 separates the data from the constants The CPU control over the program counter the status register and the stack pointer with the reduced instruction set allows the development of applications with sophisticated addressing modes and software algorithms 2 3 Program Memory
269. ally with the first access of ADC12IV and ADC12TOVIFG will be reset automatically with the next access to the ADC12lV assuming ADC12OVIFG was not set again However flags ADC12IFG x must be reset by software or reset by accessing the corresponding conversion memory register ADC12MEMx Also note that the flags ADC12OVIFG ADC12TOVIFG can not be ac cessed by software They are visible only via the interrupt vector word ADC12IV data Table 15 3 ADC12lV Interrupt Vector Values 1 ee Note Writing to Read Only Register ADC12IV When a write to vector word register ADC12IV occurs the highest pending interrupt flag is reset Therefore the interrupt event is missed 15 38 ADC12 Control Registers 15 8 5 1 ADC Interrupt Vector Register Software Example The following software example shows the use of vector word ADC12IV and the associated software overhead The numbers at the right margin show the cycles required for every instruction The example shows a basic interrupt handler structure that can be adopted to individual application requirements The software overhead for the different interrupt sources including interrupt latency and return from interrupt cycles but not the task handling itself is ADC12IFG 0 to ADC121FG 14 ADC12OV 16 cycles ADC12IFG 15 14 cycles Interrupt handler for the 12 bit ADC The flag
270. alue becomes equal to TBCLO 11 5 2 Output Control Block The output control block prepares the value of the OUTx signal which is latched into the OUTx flip flop with the next positive timer clock edge as shown in Figure 11 23 and Table 11 3 The equal signals EQUx and EQUO are sampled during the negative level of the timer clock as shown in Figure 11 23 Figure 11 23 Output Control Block OUTx Output EQUO Control EQUx Block Timer Clock 2 OMx1 The timer is Incremented with the rising edge of the timer clock meds E OUTx Signal Timer W m V V V V TBRmag V V V UAR o XX eee Xe A o TBR n EQUx TBCLx n EQUO TBR 0 or TBR TBCLO EQUO Delayed Used in Up Mode Only EQUO delayed is used in up mode not EQUO EQUO is active high when TBR TBCLO EQUO delayed is active high when TBR 0 Timer_B 11 25 Table 11 3 State of OUTx at Next Rising Edge of Timer Clock Mode 0 1 11 5 3 Output Examples 11 5 3 1 Output Examples Timer in Up Mode 11 26 The following are some examples of possible output signals using the various timer and output modes The OUTx signal is changed when the timer counts up to the TBCLx value and rolls from TBCLO to zero depending on the output mode as shown in Figure 11 24 EQUO 00 00 xx x 0o0 00
271. amp Flash Y 55 31 313 3 EE gt gt 4 gt Programming Operation Active Remove Programming Voltage Programming Voltage Entire Programming Cycle Timing gt Time of Increased Current Consumption From Supply VCC BUSTI 000 I lt W prog all lt 25Ms _ WAIT I 1 30 fx liprog2 20 fx Uprog2 20 fx The block write can be used on sequential addresses of the memory module One block is 64 bytes long starting at Oxx00h 40 0xx80h or OxxCOh and ending at Oxx3Fh Oxx7Fh OxxBFh or OxxFFh Examples of sequential block addresses are l prog3 5 fx OF000h to OFO3Fh OF040h to OF07Fh 0F080h to OFOBFh OFOCOh to OFOFFh OF100 to OF13Fh The block write program operation at the 64 byte boundaries needs special software support test of address Oxx3Fh Oxx7Fh OxxBFh or OxxFFh was successful Lj Waituntil the WAIT bitis set indicating that the write of the last byte or word was completed g Reset control bit BLKWRT The BUSY bit remains set until the programming voltage is removed from the flash memory module and overstress is avoided L Wait the recovery time before another block write is started Flash Memory C 11 Flash Memory Data Structure and Operation The write cycle is successfully completed if none of the following restrictions is violated set Lj The p
272. an NMI interrupt is requested The NMI interrupt routine should handle such violations Mass erase Segment0 to Segmenin are erased together Segnmentn is highest numbered segment of the device but not the information segments 0 No erase is started 1 Erase of SegmentO to Segmentn is enabled When a dummy write into any address in SegmentO to Segmentn is executed mass erase is started The MEras bit is automatically reset when the erase operation is completed Note Instruction fetch access during mass erase is allowed Any other access to the flash memory during erase results in setting the ACCVIFG bit and an NMI interrupt is requested The NMI interrupt routine should handle such violations The bit WRT should be set to get a successful write execution If bit WRT is reset and write access to the flash memory is performed an access violation occurs and ACCVIFG is set Note Instruction fetch access during erase is allowed Any other access to the flash memory during erase results in setting the ACCVIFG bit and an NMI interrupt is requested The NMI interrupt routine should handle such violations Bit BLKWRT can be used to reduce total programming time The block write bit BLKWRT is useful if larger sequences of data have to be programmed If programming of one block is completed a reset and set sequence should be performed to enable access to the next block The WAIT bit should be high before the next write instruction is
273. and is different for each individual sample The frequency can be controlled by software if an external reference such as the ACLK signal is used to measure the difference and to readjust the DCO frequency LLLLS S S R OO Basic Clock Module 7 13 Basic Clock Module Operating Modes 7 4 Basic Clock Module Operating Modes 7 4 1 Control bits SCGO SCG1 OscOff and CPUOff in the status register configure the operating mode as discussed in Chapter 3 System Hesets Interrupts and Operating Modes The digitally controlled oscillator is disabled when not used for MCLK or SMCLK The dc generator must be switched off separately but is switched on automatically when the DCOCLK signal is used either for MCLK or SMCLK Starting From Power Up Clear PUC On a valid PUG the internal resistor is selected for the dc generator Rgg 4 and 3 allowing the oscillator to operate at a medium frequency and independently from external conditions ACLK is sourced from LFXT1 in the LF mode and configured to operate with a watch crystal MCLK and SMCLK are sourced from DCOCLK Because the CPU executes code from MCLK which is sourced from the fast starting DCO code execution from PUC is fast typically less than 6 us After a PUC user software selects the best basic clock configuration for the application 7 4 2 Adjusting the Basic Clock 7 14 The control
274. and the original source for MCLK should be used again the SELM 1 bit needs to be reset Int OscError BIC B SELM1 amp BCSCTL2 Use DCOCLK for MCLK BIC B 4 OFIFG amp IFGI Try to clear oscillator error flag BIT B OFIFG amp IFG1 Test if oscillator error gone JC Continue Oscillator fault still valid BIS B SELM1 amp BCSCTL2 Return to original source for Basic Clock Module Digitally Controlled Oscillator Continue 7 3 Digitally Controlled Oscillator DCO The DCO is an integrated RC type oscillator in the Basic Clock Module The DCO frequency can be tuned by software using the DCO MOD and RSEL bits The DCO is absolutely monotonic As with any RC type oscillator frequency varies with temperature voltage and from device to device The digital control of the oscillator allows frequency stabilization despite its RC type characteristics Figure 7 10 DCO Schematic 77 Voc Dco Mop CPUOff Sca XSELM 1 SELS Rsel 0 1 2 SCGO DCOCLK 5 o EIL 1 The dc generator when switched off requires some minimal start up time 4 microsecond range due to its low current design Once the current is switched on the resistor injects current in the microampere range into the dc generator the internal and external parasitic capacitances introduce the delay in the microsecond range No delay occurs in operating modes that
275. and ultralow energy consumption This support is combined with an intelligent management of operations during the different module and CPU states An interrupt event wakes the system from each of the various operating modes and the RETI instruction returns operation to the mode that was selected before the interrupt event The ultralow power system design which uses complementary metal oxide semiconductor CMOS technology takes into account three different needs Lj The desire for speed and data throughput despite conflicting needs for ultra low power LJ Minimization of individual current consumption Lj Limitation of the activity state to the minimum required by the use of low power modes There are four bits that control the CPU and the main parts of the operation of the system clock generator CPUOff OscOff SCGO SCG1 These four bits support discontinuous active mode AM requests to limit the time period of the full operating mode and are located in the status register The major advantage of including the operating mode bits in the status register is that the present state of the operating condition is saved onto the stack during an interrupt service request As long as the stored status register information is not altered the processor continues after RETI with the same operating mode as before the interrupt event Another program flow may be selected by manipulating the data stored on the stack or the stack pointer Bein
276. annel converters uses an interrupt request to signal the end of the conversion and requires the conversion data to be moved to another location before another conversion can be performed However the ADC12 incorporates 16 conversion memory registers ADC12MEMx see Figure 15 1 allowing the A D converter to run multiple conversions without software intervention This increases the system performance by reducing software overhead Additionally each of the 16 conversion memory registers has an associated control register ADC12MCTLx allowing total flexibility for each conversion The memory control registers allow the user to specify the channel and reference s used for each individual conversion All other control bits that configure the other operating conditions of the ADC12 such as conversion modes sample and conversion control signal ADC clock and sample timing are located in control registers ADC12CTLO and ADC12CTL1 Each conversion memory register is individually accessible by software in the address range 0140h 015Eh Using the conversion memory involves control bits in two places First the CStartAdd bits located in ADC12CTL1 point to the conversion memory register to be used for single channel conversions or the first conversion memory register to be used for a sequence The conversion start address CStartAdd can be any value from Oh OFh and points to ADC12MEMO ADC12MEM15 respectively Second the end of sequence EOS
277. aracter was received but the start detect interrupt was not Because the interrupt software handler for the receive start detection resets the URXSE bit this clears the URXS bit and prevents further interrupt requests from URXS The URXIFG should already be reset since no set condition was active during URXIFG latch time USART Peripheral Interface UART Mode 12 13 Interrupt and Enable Functions 12 4 4 USART Transmit Interrupt Operation In the transmit interrupt operation shown in Figure 12 15 the transmit interrupt flag UTXIFG is set by the transmitter to indicate that the transmitter buffer UXTXBUF is ready to accept another character This bit is automatically reset if the interrupt request service is started or a character is written into the UxTXBUF This flag asserts a transmitter interrupt if the local UTXIE and general interrupt enable GIE bits are set The UTXIFG is set after a system reset signal or removal of a SWRST Figure 12 15 Transmit Interrupt Operation PUC or SWRST Request UTXIFG Interrupt Service Character Moved From SWRST Buffer to Shift Register IRQA UxRXBUF Written Into Transmit Shift Register The transmit interrupt enable UTXIE bit controls the ability of the UTXIFG to request an interrupt but does not prevent the flag UTXIFG from being set The UTXIE is reset with a PUC signal or a software reset SWRST bit The UTXIFG bit is set after a sys
278. are multiplier is a 16 bit peripheral module It is not integrated into the CPU Therefore it requires no special instructions and operates independent of the CPU To use the hardware multiplier the operands are loaded into registers and the results are available the next instruction no extra cycles are required for a multiplication Topic Page 6 1 Hardware Multiplier Module 6 2 6 2 Hardware Multiplier Operation 6 3 6 3 Hardware Multiplier 6 7 6 4 Hardware Multiplier Special Function 6 8 6 5 Hardware Multiplier Software Restrictions 6 8 6 1 Hardware Multiplier Module Support 6 1 Hardware Multiplier Module Support The hardware multiplier module expands the capabilities of the MSP430 family without changing the basic architecture Multiplication is possible for 16x16 bits Lj 16x8 bits Lj 8x16 bits 8x8 bits The hardware multiplier module supports four types of multiplication unsigned multiplication MPY signed multiplication MPYS unsigned multiplication with accumulation MAC and signed multiplication with accumulation MACS Figure 6 1 shows how the hardware multiplier module interfaces with the bus system to support multiplication operations Figure 6 1 Connection of the Hardware Multiplier Module to the Bus Syst
279. are shown in Figure 11 25 In continuous mode the timer starts counting from its present value The counter counts up to TBR max and restarts by counting from zero as shown in Figure 11 9 The maximum value of TBR TBR may in continuous mode is OFFFFh for 16 bit configuration OOFFFh for 12 bit configuration 003FFh for 10 bit configuration OOOFFh for 8 bit configuration Figure 11 9 Timer Continuous Mode 11 10 Timer Modes The TBIFG flag is set when the timer counts from TBR max to zero The interrupt flag is set independently of the corresponding interrupt enable bit as shown in Figure 11 10 An interrupt is requested if the corresponding interrupt enable bit and the GIE bit are set Figure 11 10 Continuous Mode Flag Setting Timer Clock Timer TBR may 1 Set Interrupt Flag TBIFG 11 3 3 1 Timer Use of the Continuous Mode The continuous mode can be used to generate time intervals for the application software Each time an interval is completed an interrupt can be generated In the interrupt service routine of this event the time until the next event is added to capture compare register CCRx and subsequently compare latch TBCLx as shown in Figure 11 11 Up to seven independent time events can be generated using all seven capture compare blocks Figure 11 11 Output Unit in Continuous Mode for Time Intervals TBCLOf TBCLOI TBCLOe TBCLOk TBCLOd TBCLOj TBCLOc TBCLOi TBCL
280. are subtracted LSBs are in R13 and R10 MSBs are in R12 and R9 SUB W R13 R10 16 bit part LSBs SUBC B R12 R9 8 bit part MSBs The 16 bit counter pointed to by R13 is subtracted from a 16 bit counter in R10 and R11 MSD SUB B R13 R10 Subtract LSDs without carry SUBC B R13 R11 Subtract MSDs with carry resulting from the LSDs Note Borrow Is Treated as a NOT Carry The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 Instruction Set Description B 57 Instruction Set Overview SWPB Syntax Operation Description Status Bits Mode Bits Swap bytes SWPB dst Bits 15 to 8 lt gt bits 7 to 0 The destination operand high and low bytes are exchanged as shown in Figure 10 N Not affected Z Not affected C Not affected V Not affected OscOff CPUOff and GIE are not affected Figure 10 Destination Operand Byte Swap Example Example 15 8 7 0 MOV 040BFh R7 0100000010111111 R7 SWPB R7 1011111101000000 in R7 The value in R5 is multiplied by 256 The result is stored in R5 R4 SWPB R5 MOV R5 R4 the swapped value to R4 BIC 0FF00h R5 Correct the result BIC 800FFh R4 Correct the result SXT Syntax Operation Description Status Bits Mode Bits Instruction Set Overview Extend Sign SXT dst Bit 7 Bit 8 Bit 15 The sign ofthe low byte is extended into the high byte as shown in Figure B 11 N Setif result is
281. are the transmit receive of the next character USART Peripheral Interface SPI Mode 13 5 Synchronous Operation H Second character is finished and sets the interrupt flag I Master receives 2Ah and slave receives 74h right justified Figure 13 4 Serial Synchronous Data Transfer 0 CDEF G HI dici Emus n HHHH SIMO From co ordeo prodest espe pm pe Ier ees re SOMI From Slave ERO UIN STE P Master Interrupt s Hee 1 4 L UTXIFG ld Slave Interrupt Shift Data Out LLL iq ici ft yt Shift Data In Figure 13 5 Data Transfer Cycle MSB LSB MSB LSB CN 100110 ojoj S B BOh gt UxTXBUF 1 0110000 0101 1000 A 98h DSR C F UxRXBUF M C D DSR from Initial State CN 0101101 ofo 5 G E8h UxTXBUF 00101010 DSR T In 7 bit mode the MSB of RXBUF is always read as 0 S Slave M Master E 54h DSR UXxRXBUF 13 6 Synchronous Operation Figure 13 6 illustrates the USART module functioning as a slave in a three or four pin SPI configuration Figure 13 6 MSP430 USART as Slave in Three Pin or Four Pin Configuration MASTER MSB COMMON SPI SPI Receive Buffer Receive Buffer UXRXBUF Receive Shift Register MSP430 USART 13 3 1 Master SPI Mode The m
282. ase Operation FUNCTION PERFORMED BLKWRT WRT Meras Erase BUSY WAIT Lock Write word or byte 0 1 0 0 0 0 0 Write word or byte in same block block write 1 1 0 0 0 1 0 mode Erase one segment by writing to any address 0 0 0 1 0 0 0 in the target segment 0 to n or A or B Erase all segments 0 to n but not the infor 0 0 1 0 0 0 0 mation memory SegmentA and SegmentB Erase all segments 0 to n and A and B by 0 0 1 1 0 0 0 writing to any address in the flash memory module Note write to flash memory performed with any other combination of bits BLKWRT WRT Meras Eras BUSY WAIT and Lock will result in an access violation ACCVIFG is set and an NMI is requested if ACCVIE 1 C 2 4 Flash Memory Status During Code Execution The flash memory module delivers data for code execution in the same manner as any masked ROM or RAM The flash memory module should be in read mode with no write programming or erase operation active By default power on reset POR puts the flash memory into read mode No control bits need to be defined in the flash memory control registers after POR for code execution C 2 5 Flash Memory Status During Erase C 8 The default bit level of the flash memory is 1 Any successful erase sets all bits of a segment or a block to this default level Once a bit is programmed to the 0 level only the erase function can reset it back to 1 Erase can be performed for one segment a group of segments or for an
283. aster mode is selected when the master mode bit MM in control register UXCTL is set The USART module controls the serial communication network by providing UCLK at the UCLK pin Data is output on the SIMO pin during the first UCLK period and latched from the SOMI pin in the middle of the corresponding UCLK period The data written to the transmit buffer UXTXBUF is moved to the transmit shift register as soon as the shift register is empty This initiates the data transfer on the SIMO pin starting with the most significant bit At the same time received data is shifted into the receive shift register and upon receiving the selected number of bits the data is transferred to the receive buffer UxRXBUF setting the receive interrupt flag URXIFG Data is shifted into the receive shift register starting with the most significant bit It is stored and right justified in the receive buffer UXRXBUF When previous data is not read from the receive buffer UxRXBUF the overrun error bit OE is set p Note USART Synchronous Master Mode Receive Initiation The master writes data to the transmit buffer UxTXBUF to receive a character The receive starts when the transmit shift register is empty and the data is transferred to it Receive and transmit operations always take place together at opposite clock edges The protocol can be controlled using the
284. ause the first sampling period is too short ADC12 1653 Sampling To prevent this problem synchronization logic is implemented in the sample input selection switch This ensures that the first sample and conversion cycle begins with the first rising edge of the sample input signal applied after the ENC bit is set Additionally the last sample and conversion begins with the first rising edge of the sample input signal after ENC has been reset Figure 15 16 Synchronized Sample and Conversion Signal With Enable Conversion Enable Conversion ENC 252 HU ooo tENC Input SHI tssync tesync n Pug Au x Sample and conversions Trigger signal enabled 15 7 3 Sampling Modes The sampling circuitry has two modes of operation pulse sampling mode and extended sampling mode In pulse sampling mode the sample signal input selected by the SHS bits in ADC12CTL1 is used to trigger the internal sampling timer and the actual sample timing signal SAMPCON is then generated by the sampling timer and is an integer multiple of the ADC12CLK signal In extended sampling mode the sampling signal input bypasses the sample timer and is used to source SAMPCON directly therefore completely controlling the sample timing asynchronously to ADC12CLK Note that 13 ADC12CLK cycles are still required to complete one conversion 15 7 3 1 Pulse Sample Mode 15 24 In the pulse sample mode the sample input signal
285. ay differ from those in above table Refer to specific device data sheets for individual configurations Table 3 11 MSP430x12xx Module Enable Registers 1 and 2 Bit Position Short Form Initial State Comments ME1 0 Reserved ME1 1 Reserved ME1 2 Reserved ME1 3 Reserved ME1 4 Reserved ME1 5 Reserved ME1 6 Reserved ME1 7 Reserved ME2 0 URXEO Reset USARTO receiver enable UART mode USPIEO Reset USARTO transmit and receive enable SPI mode ME2 1 UTXEO Reset USARTO transmit enable UART mode ME2 2 Reserved ME2 3 Reserved ME2 4 Reserved ME2 5 Reserved ME2 6 Reserved ME2 7 Reserved Note The configuration of some MSP430 devices may differ from those in above table Refer to specific device data sheets for individual configurations 3 18 Interrupt Processing Table 3 12 MSP430x13x Module Enable Registers 1 and 2 Bit Position Short Form _ Initial State ME1 0 ME1 1 ME1 2 ME1 3 ME1 4 ME1 5 ME1 6 ME1 7 ME2 0 ME2 1 ME2 2 2 3 2 4 2 5 2 6 2 7 Note URXEO Reset USPIEO Reset UTXEO Reset Comments Reserved Reserved Reserved Reserved Reserved Reserved USARTO receiver enable UART mode USARTO transmit and receive enable SPI mode USARTO transmit enable UART mode Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved The configuration of some MSP430 devices may differ from those in above table Refer to specific device data sheets for individual config
286. bel if N XOR V 20 JL Label Jump to Label if N XOR V 1 JMP Label Jump to Label unconditionally JN Label Jump to Label if Negative bit is set JNC JLO Label Jump to Label if Carry bit is reset DE JNE JNZ Label Jump to Label if Zero bit is reset e B 2 MOV W MOV B NOP POPLW POPB PUSH W PUSH B RETI RET RLA W RLA B RLC W RLC B RRA W RRA B RRC W RRC B SBC W SBC B SETC SETN SETZ SUB W SUB B SUBC W SUBC B SWPB SXT TSTLWI TST B XOR W XOR B src dst dst src dst dst dst dst dst src dst src dst dst dst dst src dst Instruction Set Overview Status Bits src gt dst No operation Item from stack SP 2 SP SP 2 SP src gt SP Return from interrupt TOSS SR SP 2 gt SP TOS 5 PC SP 2 SZP Return from subroutine TOSS PC SP 2 gt SP Rotate left arithmetically Rotate left through carry MSB MSB LSB gt C 2 MSB LSB gt Subtract carry from destination Set carry bit Set negative bit Set zero bit dst not src 1 dst dst not src gt dst swap bytes Bit7 Bit8 Bit15 Test destination src xor dst dst V N 2 c M Note Asterisked Instructions Asterisked instructions are emulated They are replaced with core instructions by the assemble
287. ble buffers for receiving and transmitting Has clock frequency control in master mode n n n Has clock polarity and clock phase control n Supports a character length of seven or eight bits per character Figure 13 2 shows the USART module in SPI mode Figure 13 2 Block Diagram of USART SPI Mode SYNC 1 Receive Buffer SLM RES Receive Status U1RXBUF or UORXBUF T m pd SOMI i Q e o Receive Shift Register MSB First A UCLKI 2 SMCLK oJ T MSB First Transmit Shift Register ES gt SIMO 0 Transmit Buffer U1TXBUF or UOTXBUF CKPH SYNC CKPL UCLKI UCLKS USART Peripheral Interface SPI Mode 13 3 Synchronous Operation 13 3 Synchronous Operation 13 4 In USART synchronous mode data and clock signals transmit and receive serial data The master supplies the clock and data The slaves use this clock to shift serial information in and out The four pin SPI mode also uses a control line to enable a slave to receive and transmit data The line is controlled by the master Three or four signals are used for data exchange SIMO Slave in master out The direction is defined by SIMODIR SIMODIR 0 input direction SIMODIR SYNC and MM and STC or STE Output direction is selected when SPI Master Mode is selected When 4 pin SPI is selected STC 0 input direction is forced by a low level on external STE pi
288. block that holds program code ensures that the active program will not access the flash memory module Two types of access are visible execute program code or read and write data on this flash memory module Flash Memory C 23 Flash Memory Access via JTAG and Software C 5 3 2 Example Programming One Word Into the Same Flash Memory Module via Software The program execution waits after the write to flash instruction MOV 123h amp 0FF1Eh until the busy bit is reset again If no other write to flash instruction method is used the BUSY bit test may not be needed to ensure correct flash write handling Disable all interrupt sources FXKEY set 03300h and Watchdog FWKEY set OA500h No interrupt request may happen while the flash is programmed LOCK 0 WRT 1 Write Data to Flash Address MOV FWKEY amp FCTL3 LOCK 0 MOV FWKEY WRT amp FCTL1 Enable Write to flash MOV 123h 80FF1Eh Write a word to flash WRT 0 LOCK 1 MOV FWKEY amp FCTL1 Reset Write bit XOR s FXKEY LOCK amp FCTL3 Change Lock bit to 1 Restore or Enable Required Interrupt Sources and Enable those interrupt sources that should be accepted Watchdog Flash Memory Access via JTAG and Software C 5 3 3 Example Programming Byte Sequences Into a Flash Memory Module via Software Sequences of data bytes or words can use the block write feature This reduces the programming time by about one half FXKEY set 03300h FWKEY set 0A500h FRKEY
289. chdog mode is selected Active if watchdog timer is configured as general purpose timer Oscillator fault interrupt enable Not implemented Not implemented NMI interrupt enable Flash access violation enable USARTO receive interrupt enable USARTO transmit interrupt enable Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented t The initial state is the logical state after the PUC signal Table 3 5 MSP430x14x Interrupt Enable Registers 1 and 2 Bit Position Short Form IE1 0 IE1 1 IE1 2 IE1 8 IE1 4 IE1 5 IE1 6 IE1 7 IE2 0 IE2 1 IE2 2 IE2 3 IE2 4 IE2 5 IE2 6 IE2 7 WDTIE OFIE NMIIE ACCVIE URXIEO UTXIEO URXIE1 UTXIE1 Initial Statet Comments Reset Reset Reset Reset Reset Reset Reset Reset Watchdog timer enable signal Inactive if watchdog mode is selected Active if watchdog timer is configured as general purpose timer Oscillator fault interrupt enable Not implemented Not implemented NMI interrupt enable Flash access violation enable USARTO receive interrupt enable USARTO transmit interrupt enable Not implemented Not implemented Not implemented Not implemented USART1 receive interrupt enable USART1 transmit interrupt enable Not implemented Not implemented t The initial state is the logical state after the PUC signal System Resets Interrupts and Operating Modes 3 13 Interrupt
290. chronized Sample and Conversion Signal With Enable Conversion 15 24 Conversion Timing Pulse Sample Mode 15 25 Pulse Sample Mode Example Configuration 15 25 Pulse Sample Mode Example Timing 15 26 Conversion Timing for Extended Sample Mode 15 26 Extended Sample Mode Example 15 27 Extended Sample Mode Example Timing 15 27 Use of MSC Bit With Nonrepeated Modes 15 28 Use of MSC Bit With Repeated Modes 15 28 Equivalent CIFGUIU oo su r pet P Uni OLtubPUpnABDILnbbP Yee neveu 15 29 A D Grounding and Noise Considerations 15 41 ADCO Schematic Ree eee acetals doit mE EL mL ER EE 16 2 ADC Core Input Multiplexer and Sample and Hold 16 4 Analog Multiplexer Channel 16 6 Single Channel Single Conversion Mode 16 9 Sequence of Channels 16 11 Repeat Single Channel Mode 16 13 Repeat Sequence of Channels Mode
291. control register by the Sref bits The conversion result is stored in conversion memory register ADC12MEMXx pointed to by the CStartAdd bits The conversion may be stopped immediately by resetting the enable conversion bit ENC located in ADC12CTLO but the conversion results will be unreliable or the conversion may not be performed This is illustrated in Figure 15 4 Figure 15 4 Stopping Conversion With ENC Bit ENC and ADC12SC ENC and ADC12SC may be set together may be set together ENC JHA hhh 7 TET DOCU SAMPCON Jd ga Operational Mode Sample Period Conversion Period J Sample Period Conversion Period ENC is reset before conversion period is completed ENC is reset after conversion period is completed no conversion executed or unreliable conversion result conversion is executed regularly Sample and conversion SAMPCOM signal can be reset Sample and conversion signal can be reset and conversion started when appropriate and conversion started when appropriate ENC SAMPCON 7 h Operational Mode Sample Period Conversion Period Sample Period M Conversion Period ENC is reset before conversion period is completed ENC is reset after conversion period is completed no conversion executed or unreliable conversion result conversion is executed regularly Sample and conversion SAMPCOM signal can
292. converted once 1 Sequence of channels mode A sequence of conversions is executed once 2 Repeatsingle channel mode Conversions on a single channel are repeated until CONSEQ is set to O or 1 3 Repeat sequence of channels A sequence of conversions is repeated until CONSEQ is set to 0 or 1 See also section Conversion Modes for additional information ADC12 ADC12 Control Registers ADC12SSEL ADC12DIV ISSH SHP SHS CStartAdd 15 34 bits 3 4 bits bit8 bit9 bits 10 11 bits 12 15 Select the clock source for the converter core 0 ADC12 internal oscillator ADC120SC 1 ACLK 2 MCLK 3 SMCLK Select the division rate for the clock source selected by ADC12SSEL bits Oto 7 Divide selected clock source by 1 to 8 The divider s output signal name is ADC12CLK Thirteen of these clocks are required for a conversion Invert sample input signal 0 The sample input signal is not inverted 1 The sample input signal is inverted The SHP bit selects the source of the sampling signal SAMPCON to be either the output of the sampling timer or the sample input signal directly 0 SAMPCOM signal is sourced directly from the sample input signal 1 SAMPCON signal is sourced from the sampling timer The rising edge of the sample input signal triggers the sampling timer Source select for the sample input signal 0 Control bit ADC12SC is selected 1 Timer A OUT1 2 Timer B OUTO 3 Timer B OUT
293. cribed BRSCLK BRCLK for N lt 1F BRSCLK BRCLK 2 for 20h lt N lt 3Fh BRSCLK BRCLK 4 for 40h lt N lt 7Fh BRSCLK BRCLK 8 for 80h lt N lt FFh BRSCLK BRCLK 16 for 100 lt N lt 1FF BRSCLK BRCLK 32 for 200 lt N lt 3FFh BRSCLK BRCLK 64 for 400 lt N lt 7FFh BRSCLK BRCLK 128 for 800h lt lt FFFh BRSCLK BRCLK 256 for 1000h lt lt 1FFFh BRSCLK BRCLK 512 for 2000h lt N lt SFFFh BRSCLK BRCLK 1024 for 4000h lt N lt 7FFFh BRSCLK BRCLK 2048 for 8000h lt N lt FFFFh Figure 12 29 Synchronization Error target 0 1 2 to ty 2 4 6 7 1213 14 1 2 3 4 5 6 7 8 121 141 2 3 4 516 7 URXD ST DO D2 URXDS ST DO D2 lactual to ty to 9 Synchronization Error 0 5x BLSCLK Sample URXDS Int UxBR 2 m0 UxBR m1 1341 14 UxBR m2 1340 13 Int 13 2 1 6 1 7 12 30 pls Majority Vote Taken Majority Vote Taken Majority Vote Taken Baud Rate Considerations The target start bit detection baud rate timing is half the baud rate timing tpaug rate because the bit is tested in the middle of its period The target baud rate timing trargetifor all of the other succeeding bits is the baud rate timing tbaud rate 1 tactualy trargety tactual 2 arget 100 0 5 x trargety lrarget Error OR Error x x mO int UxBR 2 x
294. ct one of four taps from the WDTCNT as described in Table 9 1 Assuming forystal 32 768 Hz fsystem 1 MHz the following intervals are possible Table 9 1 WDTCNT Taps SSEL IS1 ISO Interval ms 0 1 1 0 064 tock x 28 0 1 0 0 5 x 29 1 1 1 1 9 tACLK x 28 0 0 1 8 x 218 1 1 0 16 0 tacui x 29 0 0 0 32 X 21 lt Value after PUC reset 1 0 1 250 213 1 0 O 1000 1 215 Bit 2 The SSEL bit selects the clock source for WDTONT SSEL 0 WDTONT is clocked by SMCLK SSEL 1 WDTCNT is clocked by ACLK Bit 3 Counter clear bit In both operating modes writing a 1 to this bit restarts the WDTCNT at 00000h The value read is not defined Bit 4 The TMSEL bit selects the operating mode watchdog or timer TMSEL 0 Watchdog mode TMSEL 1 Interval timer mode Watchdog Timer 9 3 The Watchdog Timer Bit 5 The NMI bit selects the function of the RST NMI input pin It is cleared by the PUC signal NMI 0 The RST NMI input works as reset input As long as the RST NMI pin is held low the internal signal is active level sensitive NMI 1 The RST NMI input works as an edge sensitive nonmaskable interrupt input Bit 6 If the NMI function is selected this bit selects the activating edge of the RST NMI input It is cleared by the PUC signal NMIES 2 0 A rising edge triggers an NMI interrupt NMIES 1 A falling edge triggers NMI interrupt CAUTION Cha
295. ct register contains a bit for each corresponding I O pin to select what type of transition triggers the interrupt flag When Bit 0 The interrupt flag is set with a low to high transition Bit 1 The interrupt flag is set with a high to low transition _ _ _ Note Changing the P1IES and P2IES bits can result in setting the associated interrupt flags PnIES x PnIN x PnIFG x 0 1 0 Unchanged 0 1 1 be set 10 0 May be set 10 1 Unchanged 8 2 1 6 Interrupt Enable P2IE Each interrupt enable register contains bits to enable the interrupt flag for each I O pin in the port Each of the sixteen bits corresponding to pins P1 0 to P1 7 and P2 0 to P2 7 is located in the P1IE and P2IE registers When Bit 0 The interrupt request is disabled Bit 1 The interrupt request is enabled E Wo Qm A GEM m UE Oooo Note Port P1 Port P2 Interrupt Sensitivity Only transitions not static levels cause interrupts If an interrupt flag is still set when the RETI instruction is executed for example a transition occurs during the interrupt service routine an interrupt occurs again after RETI is completed This ensures that each transition is acknowledged by the software 8 2 1 7 Function Select Registers P1SEL P2SEL 8 6 P1 and P2 port pins are often multiplexed with other peripheral modules to
296. cted 2 0 50 Vcc reference is selected 3 Diode reference is selected The diode reference varies with each individual device temperature and supply voltage See device data sheet Comparator A Control Registers CARSEL bite The internal reference selected CAREF bits is applied to the terminal or terminal 0 Reference is selected to the terminal CAEX 0 or terminal CAEX 1 1 Reference is selected to the terminal CAEX 0 or terminal CAEX 1 CAEX bit7 The inputs of the comparator are exchanged This is used to measure or compensate for the offset of the comparator 14 3 2 Comparator A Control Register CACTL2 The control register CACTL2 is shown and described below CACTL2 05Ah rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 CAOUT bit0 comparator output Writing to this bit for example when writing a new register value has no affect or negative impact CAF bit1 The comparator output filter is bypassed CAF 0 or switched into the output path CAF 1 P2CAQ bit2 Pin to CAO 0 The external pin signal is not connected to the Comparator A 1 The external pin signal is connected to the Comparator A P2CA1 bit3 Pin to CA1 0 The external pin signal is not connected to the Comparator A 1 The external pin signal is connected to the Comparator A Bits 4 7 See device data sheet for implementation 14 3 3 Comparator A Port Disable Regi
297. cuitry on the associated digital I O port pins to allow the input buffers to be disabled see Figure 14 5 The buffers are enabled or disabled with the CAPD x bits see section 14 3 3 Note that the circuitry is added to all pins of the associated port not just the pins for the Comparator_A inputs Disabling the input buffer for a specific pin will disable the parasitic current flow and therefore reduce overall current consumption It is important to disable the buffer for any I O pin that is not being actively driven if current consumption is critical see Figure 14 6 Comparaltor 14 9 14 10 _ in Applications With Applied Analog Signals Figure 14 6 Application Example With One Active Driving R3 and Three Passive Pins Control1 0 vs CAPD x 0 Control2 0 Ya CAPD x 0 Control3 1 1 Pr Ya CAPD x 00r 1 Control4 0 4 gt Ya CAPD x 1 The specific implementation which digital inputs outputs can be controlled by CAPD x varies with each MSP430 device configuration Refer to the specific device s data sheet to see which I O port is associated with Comparator Comparator A in Applications 14 4 2 Comparator A Used to Measure Resistive Elements The Comparator_A can be used to measure resistive elements For example temperature can be converted into digital data via a thermistor
298. d 4 9 Peripheral File Address Map Byte Modules 4 10 Special Function Register Address 4 11 Register by Functions 5 2 Description of Status Register Bits 5 4 Values of Constant Generators CG1 2 5 5 Source Destination Operand Addressing Modes 5 7 Register Mode Description 5 8 Indexed Mode 5 9 Symbolic Mode 5 10 Absolute Mode Description 5 11 Indirect Mode Description 2 1 5 12 Indirect Autoincrement Mode Description 5 13 Immediate Mode Description 5 14 Instruction Format and Addressing 5 15 Execution Cycles for Double Operand Instructions 5 15 Instruction Format Il and Addressing Modes 5 16 Execution Cycles for Single Operan
299. d Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented t The initial state is the logical state after the PUC signal Table 3 3 MSP430x12xx Interrupt Enable Registers 1 and 2 Bit Position Short Form IE1 0 IE1 1 IE1 2 IE1 3 IE1 4 IE1 5 IE1 6 IE1 7 IE2 0 IE2 1 IE2 2 IE2 3 IE2 4 IE2 5 IE2 6 IE2 7 WDTIE OFIE NMIIE ACCVIE URXIEO UTXIEO Initial Statet Comments Reset Reset Reset Reset Reset Reset Watchdog timer enable signal Inactive if watchdog mode is selected Active if watchdog timer is configured as general purpose timer Oscillator fault interrupt enable Not implemented Not implemented NMI interrupt enable Flash access violation enable Not implemented Not implemented USARTO receive interrupt enable USARTO transmit interrupt enable Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented T The initial state is the logical state after the PUC signal 3 12 Interrupt Processing Table 3 4 MSP430x13x Interrupt Enable Registers 1 and 2 Bit Position Short Form IE1 0 IE1 1 IE1 2 IE1 8 IE1 4 IE1 5 IE1 6 IE1 7 IE2 0 IE2 1 IE2 2 2 3 IE2 4 IE2 5 IE2 6 IE2 7 WDTIE OFIE NMIIE ACCVIE URXIEO UTXIEO Initial Statet Comments Reset Reset Reset Reset Reset Reset Watchdog timer enable signal Inactive if wat
300. d the software should not access the flash memory until the BUSY signal indicates with 0 that it can be accessed again In critical situations where flash programming or erase should be immediately stopped the emergency exit bit EMEX can be set The current operation may be incomplete or the result may be incorrect Different clock sources ACLK MCLK or SMCLK can be selected to clock the timing generator The connected clock sources applied to the timing generator may vary with the device see data sheet for details The clock source selected should be active from the beginning of write or erase until the operation is fully completed Figure C 6 Block Diagram of the Timing Generator in the Flash Memory Module Write 1710 SSEL1 FNS FNO PUC EMEX SSELO ACLK MCLK 1 Reset SMCLK O Flash Timing Generator SMCLK Busy Wait The selected clock source should be divided to meet the frequency require ment fx of the flash timing generator If the clock signals are not available throughout the duration of the write or erase operation or their frequencies change drastically the result of the write or erase may be marginal or the flash memory module may be stressed above the limits of reliable operation Table 1 shows all useful combinations of control bits for proper write and erase operation Flash Memory C 7 Flash Memory Data Structure and Operation Table C 1 Control Bits for Write or Er
301. d Instructions 5 16 Miscellaneous Instructions or Operations 5 17 Double Operand Instruction Format Results 5 18 Single Operand Instruction Format Results 5 19 Xix Contents TAG lab ok oo xo Exec T m qme N qu CD Pp WDD T p 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 12 1 12 2 12 3 12 4 12 5 12 6 13 1 13 2 13 3 14 1 15 1 15 2 15 3 16 1 16 2 16 3 C 1 2 Conditional Jump Instructions 5 20 Emulated Instructions 5 21 Sum Extension Register Contents 6 4 Hardware Multiplier Registers 1 6 6 Port P1 Registers 2 22 2222 dos Rer oy Red Rosie 8 4 Port P2 HegistersS occ ien ER tated bre Rede Bee RR A RR Rd 8 4 Port P3 P6 Registers Denke ERR IDEE D E 8 10 WDIGCNT Taps 3 ckiv iki eT DR 9 3 Timer ModS us ie abel 10 4 State of OUTx at Next Rising Edge of Timer Clock 10 22 Timer A Reg
302. d discharge the capacitor Port pins are set to provide a Vcc output charge a capacitor reset to discharge a capacitor and switched to high impedance including correct state of CAPD x bit when not in use One output discharges the capacitor via reference resistor R ref the other output discharges it via R meas Comparator The terminal is connected to a reference level for example 0 25 x Vcc The terminal is connected to the positive terminal of the capacitor c CAOUT or CAIFG utilized to measure the discharge time n The output filter should be used to minimize multiple switching when the voltages at the comparator inputs are close together If CAOUT is available as an input to a timer capture register such as Timer A the capacitor discharge time can be measured very precisely without software polling for a change of CAOUT by using the timer capture function N Rmeas Pref X meas Tmeas f Rmeas ref Comparator A in Applications 14 4 3 Measuring Two Independent Resistive Element Systems Itis possible to measure two independent systems with one comparator The input multiplexer which is controlled via CAEX allows the two independent systems to be isolated See Figure 14 9 An example could be if temperature sensor has a resistor range of 10 kO to 200 The other sensor is in the range of 1 kO to 1 5 kO Two independent measurement paths are used to optimize individual measurement perf
303. define the upper and lower limits of the conversion range and to define the full scale and zero scale readings The digital output is full scale when the input signal is equal to or higher than Vp and zero when the input signal is equal to or lower than Vg The input channel and the reference voltage levels and are defined in the conversion control memory The conversion formula is Vin Vp V 1023 x Figure 16 2 ADC Core Input Multiplexer and Sample and Hold INCH Sref Bits Y Y From Reference Pass or Autoscan ADC100N VR ADC10CLK Analog Multiplexer d 10 Bit A D Converter Core 12 1 Convert VeREF VenEF VREF Temperature 2 SAMPCON ADC10MEM Caution ADC10 Turnon Time When the ADC10 is turned on with the ADC10ON bit the turnon time noted in the data sheet must be observed before a conversion is started Otherwise the results will be false 16 4 16 2 2 Reference ADC10 Description and Operation The ADC10 A D converter contains a built in reference with two selectable reference voltage levels 1 5 V and 2 5 V Either of these reference voltages may be applied to Vp of the A D core and also may be available externally on pin Vref check device data sheet for availability of VRgf pin Additionally an external reference may be supplied for Vg through pin Vengr check data sheet
304. ding on device configuration see Sampling section and check the data sheet for details Typically the internal timing signals come from other MSP430 timers such as Timer A Additionally the sample timing may be programmed as a multiple of the ADC12 conversion clock As with sample timing the user has several choices for the ADC12 conversion clock The ADC12 conversion clock may be chosen from any available internal MSP430 clock or may be selected from a dedicated oscillator contained in the ADC12 peripheral Additionally the chosen clock source may be divided by any factor from 1 to 8 The ADC12 has four operating modes It can be configured to perform a single conversion on a single channel or multiple conversions on a single channel The ADC12 can also be configured to perform conversions on a sequence of channels running through the sequence once or repeatedly When performing conversions on a sequence of channels the sequence is completely definable by the user For example a possible sequence of channels could be ai a3 a1 a6 a2 etc In addition each channel may be individually configured for which reference s are to be used for the conversion Conversion results are stored in 16 conversion memory registers Each of these registers has its own configuration and control register allowing the user to select the input channel and the reference s used for the conversion result that is stored in that register Some key a
305. direction with the next valid clock edge unless halted by cleared mode control bits Bit 3 Not used Bits 4 5 Mode control Table 11 5 describes the mode control bits Table 11 5 Mode Control MC1 MCO Count Mode Description 0 0 Stop Timer is halted 0 1 Up to CCRO Timer counts up to TBCLO and restarts at O Note If TBCLO gt TBR max the counter counts to zero with the next rising edge of timer clock 1 0 Continuous up Timer counts up to TBR max and restarts at 0 The maximum value of TBR TBR max is OFFFFh for 16 bit configuration OOFFFh for 12 bit configuration 003FFh for 10 bit configuration OOOFFh for 8 bit configuration 1 1 Up down Timer continuously counts up to CCRO and back down to 0 Note If CCRO gt TBR max the counter operates as if it were configured for continuous mode It will not count down from max to zero Bits 6 7 Input divider control bits Table 11 6 describes the clock divider bits Table 11 6 Input Clock Divider Control Bits ID1 IDO Operation Description 0 0 Input clock source is passed to the timer 0 1 2 Input clock source is divided by two 1 0 4 Input clock source is divided by four 1 1 8 Input clock source is divided by eight Bits 8 9 Clock source selection bits Table 11 7 describes the clock source selections Table 11 7 Clock Source Selection SSEL1 SSELO O PSignal Comment 0 0 TBCLK See data sheet device description 0 1 ACLK Auxiliary
306. do not require to switch off the dc generator current An internal or external resistor is connected to the dc generator which determines the operating fundamental frequency of the DCOCLK The frequency of DCOCLK is set by the following functions The current injected into the dc generator DCGEN by either the internal or external resistor defines the fundamental frequency Control bit DCOR selects the internal or external resistor Control bits Rsel2 Rsel1 and RselO divide the fundamental frequency into eight nominal frequency ranges These ranges are defined for an individual device in the appropriate data sheet J The three control bits to DCO2 adjust the DCOCLK frequency J The five modulation bits MODO to MODA switch between the frequency selected by the bits and the next higher frequency set by 1 7 10 Digitally Controlled Oscillator The clock period of the DCOCLK signal changes approximately ten percent for each step of the control bit DCO Figure 7 11 Principle Period Steps of the DCO DCOCLK Nominal 0 14 2 3 4 5 6 7 DCO Five bits SCGO CPUOff SELM 1 SCG1 and SELS control the operation of the DCO Figure 7 12 On Off Control of DCO CPUOff DCOCLK on XSELM 1 e 1 on SCG1 0 off SELS D DCOCLK gt CL SMCLK PoR _ SCGO 1 on 0 off SCGO CPUOff SELM 1 SCG1 SELS DCOCLK DCO G
307. dst LSB gt C M PUSH W PUSH B dst SP 2 gt SP src SP 5 SWPB dst swap bytes mE CALL dst 2 dst PC RETI dst TOSS SR SP 25 SP VEA S TOS gt PC SP 2 gt SP SXT dst Bit 7 Bit 8 Bit 15 Qm ow os B 1 2 Conditional and Unconditional Jumps Core Instructions The instruction format for conditional and unconditional jumps as shown in Figure B 3 consists of two main fields to form a 16 bit code Lj operational code op code field six bits Lj jump offset field ten bits The operational code field is composed of the op code three bits and three bits according to the following conditions Figure B 3 Conditional and Unconditional Jump Instructions 15 13 312 10 9 0 OP Code Jump On Cone Sign Offset Operational Code Field Jump Offset Field Conditional jumps jump to addresses in the range of 511 to 4512 words relative to the current address The assembler computes the signed offsets and inserts them into the op code Instruction Set Description B 5 Instruction Set Overview JC JHS JEQ JZ JGE JL JMP JN JNC JLO JNE JNZ Label Label Label Label Label Label Label Label Jump to label if carry bit is set Jump to label if zero bit is set Jump to label if N XOR V 2 0 Jump to label if N XOR V 1 Jump to label unconditionally Jump to label if negative bit is set Jump to label if carry bit is reset Jump to label
308. dware serves the highest priority within the empowered interrupt source 3 4 4 Interrupt Control Bits Special Function Registers SFRs Most of the interrupt control bits interrupt flags and interrupt enable bits are collected in SFRs under a few addresses as shown in Table 3 1 The SFRs are located in the lower address range and are implemented in byte format SFRs must be accessed using byte instructions Table 3 1 Interrupt Control Bits SFRs Address 7 000Fh Not yet defined or implemented 0 000Eh 000D 000Ch 000A 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h Interrupt enable 1 IE1 x The Module Enable bits Interrupt Enable bits and Interrupt flags contained in the SFRs are shown in the following tables System Resets Interrupts and Operating Modes 3 11 Interrupt Processing Table 3 2 MSP430x11xx Interrupt Enable Registers 1 and 2 Bit Position Short Form IE1 0 IE1 1 IE1 2 IE1 3 IE1 4 IE1 5 IE1 6 IE1 7 IE2 0 IE2 1 IE2 2 IE2 3 IE2 4 IE2 5 IE2 6 IE2 7 WDTIE OFIE NMIIE ACCVIE Initial Statet Comments Reset Reset Reset Reset Watchdog timer enable signal Inactive if watchdog mode is selected Active if watchdog timer is configured as general purpose timer Oscillator fault interrupt enable Not implemented Not implemented NMI interrupt enable Flash access violation enable flash devices only Not implemented Not implemente
309. e Collects Conditions SEP Enabled External Clock Character Present Character Received USPIIE 1 PUC USPIIE 0 13 4 2 USART Receive Transmit Enable Bit Transmit Operation The receive transmit enable bit USPIIE shown in Figures 13 10 and 13 11 enables or disables the shifting of a character on the serial data line If this bit is reset the transmitter is disabled but any active transmission does not halt until all data previously written to the transmit buffer is transmitted If the transmission is completed any further write operation to the transmitter buffer does not transmit When the UxTXBUF is ready any pending request for transmission remains which results in an immediate start of transmission when USPIIE is set and the transmitter is empty A low state on the STE signal removes the active master four pin mode from the bus It also indicates that another master is requesting the active master function 13 4 2 1 Receive Transmit Enable MSP430 as Master Figure 13 10 shows the transmit enable activity when the MSP430 is master Figure 13 10 State Diagram of Transmit Enable MSP430 as Master No Data Written to Transfer Buffer USPIIE 1 Data Written to Transmit Buffer USPIIE 0 Not Completed USPIIE 1 USPIIE 1 Idle State Transmitter Enabled Handle Interrupt Conditions Transmission Active Transmit Disable Charac
310. e Map Appendix B Instruction Set Description Appendix C Flash Memory Notational Conventions This document uses the following conventions Program listings program examples and interactive displays are shown ina special typeface similar to a typewriter s Here is a sample program listing 0011 0005 0001 field 1 2 0012 0005 0003 field 3 4 0013 0005 0006 field 6 3 0014 0006 Related Documentation From Texas Instruments FCC Warning For related documentation see the web site http Awww ti com sc msp430 This equipmentis intended for use in a laboratory test environment only It gen erates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other en vironments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference 1 Contents uigefelITei OT n 1 1 1 1 Features and Capabilities 1 2 1 2 TCR peg Rr RR re gore a b ie 1 3 1 2 E DeVIC6S E b etu thu ee ses 1 3 T Jdx2JD6vices ons etest uper RERO SERE PU EGO LED Debo Lee ees 1 4 1 5 d2X Devices ce Ce eer
311. e Sampling section and Figure 15 14 Thirteen conversion clocks ADC12CLK are required to complete a conversion The conversion time is tconversion 13 x ADC12DIV fApc12CLK Where ADC12DIV is any integer from 1 to 8 The ADC12CLK frequency must not exceed the maximum and minimum frequencies specified in the data sheet Either violation may result in inaccurate conversion results Note Availability of ADC12CLK During Conversion Users must ensure that the clock chosen for ADC12CLK remains active until the ADC12 can complete its operation If the clock is removed while the ADC12is active the operation can not be completed and the end of conver sion feedback to the program is not possible The ADC12 sample and hold S H circuitry shown in Figure 15 14 is flexible and configurable The configuration is done by software via control bits in the ADC12CTLO and ADC12CTL1 registers Configuration and operation of the S H circuitry is discussed in this section Figure 15 14 The Sample and Hold Function Signal Sample and Hold SiH 12 bit A D Converter Core Internal ADC12SSEL Oscillator ADC120N ADC12DIV ADC120SC ADC12CLK Divide by ACLK 1 2 3 4 5 6 7 8 MCLK SMCLK Sampling ADC12SC
312. e appropriate interrupt enable bit and general interrupt enable GIE bit are set the interrupt service routine becomes active as follows 1 CPU active The currently executing instruction is completed 2 CPU stopped The low power modes are terminated 3 The program counter pointing to the next instruction is pushed onto the stack 4 The status register is pushed onto the stack 5 The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service 6 The appropriate interrupt request flag resets automatically on single source flags Multiple source flags remain set for servicing by software 7 The GIE bit is reset the CPUOff bit the OscOff bit and the SCG1 bit are cleared the status bits V N Z and C are reset SCGO is left unchanged System Resets Interrupts and Operating Modes 3 9 Interrupt Processing 8 The content of the appropriate interrupt vector is loaded into the program counter the program continues with the interrupt handling routine at that address The interrupt latency is six cycles starting with the acceptance of an interrupt request and lasting until the start of execution of the appropriate interrupt service routine first instruction as shown in Figure 3 7 Figure 3 7 Interrupt Processing SP The interrupt handling routine terminates with the instruction which performs the following actions Before In
313. e instruction may be used for the elimination of instructions during the software check or for defined waiting times Status bits are not affected The NOP instruction is mainly used for two purposes To hold one two or three memory words To adjust software timing Note Emulating No Operation Instruction Other instructions can emulate the NOP function while providing different numbers of instruction cycles and code words Some examples are Examples MOV 0 R4 0 R4 6 cycles 3 words MOV R4 0 R4 5 cycles 2 words BIC 0 EDE R4 4 cycles 2 words JMP 2 2 cycles 1 word BIC 0 R5 1 cycle 1 word However care should be taken when using these examples to prevent unintended results For example if MOV 0 R4 0 R4 is used and the value in R4 is 120h then a security violation will occur with the watchdog timer address 120h because the security key was not used POP W Syntax Operation Emulation Emulation Description Status Bits Example Example Example Example Instruction Set Overview Pop word from stack to destination Pop byte from stack to destination POP dst SP temp SP 2 gt SP temp gt dst MOV SP dst or MOV W SP dst MOV B SP dst The stack location pointed to by the stack pointer
314. e is when the supply voltage drops drastically and the controller s operating conditions may be exceeded Another case is when the flash memory timing gets out of control as when the clock source signal is lost Note Whenever the write cycle is stopped before its normal ending by the hard ware the timing generator is stopped and the data written in flash memory may be marginal Data reading may be inconsistently valid when varying the supply voltage the temperature the access time instruction execution data read or the time Flash Memory Control Registers Defining the correct control bits of three control registers enables write program erase or mass erase All three registers should be accessed using word instructions only The control registers are protected against false write or erase cycles via a key word Any violation of this keyword sets the KEYV bit and requests a nonmaskable interrupt NMI The keyword is different to the keyword used with the Watchdog Timer All control bits are reset during PUC PUC is activated after Vcc is applied a reset condition is applied to the RST NMI pin or watchdog or a flash operation was not performed normally C 3 1 Flash Memory Control Register FCTL1 Any write to control register FCTL1 during erase mass erase or write programming w
315. e of these in the immediate mode will result in an unpredictable program operation Table 5 15 shows a simple way to determine CPU instruction cycles for Format ll single operand instructions Table 5 15 Execution Cycles for Single Operand Instructions Instruction Addressing Mode Rn x Rn Symbolic Absolute amp Example the instruction PUSH 500h needs 4 cycles for the execution 5 2 8 3 Format lll Instructions Jump Format lll instructions are described as follows Jxx all instructions need the same number of cycles independent of whether a jump is taken or not Clock cycle Two cycles Length of instruction word 5 2 8 4 Miscellaneous Format Instructions Table 5 16 describes miscellaneous format instructions 5 16 Instruction Set Overview Table 5 16 Miscellaneous Instructions or Operations Activity Clock Cycle RETI 5 cycles 1 wordt Interrupt 6 cycles WDT reset 4 cycles Reset RST NMI 4 cycles T Length of instruction 5 3 Instruction Set Overview This section gives a short overview of the instruction set The addressing modes are described in Section 5 2 Instructions are either single or dual operand or jump The source and destination parts of an instruction are defined by the following fields src The source operand defined by As and S reg dst The destination operand defined by Ad and D reg As The addressing bits responsible for the addressing mode used
316. e total current consumption of the individual modes The activity state of each peripheral is controlled by the control registers for the individual peripherals In addition the SFRs include module enable bits that may be used to enable or disable the operation of specific peripheral modules see Table 3 4 3 5 1 Low Power Mode 0 and 1 LPMO and LPM1 Low power mode 0 or 1 is selected if bit CPUOff in the status register is set Immediately after the bit is set the CPU stops operation and the normal operation of the system core stops The operation of the CPU halts and all internal bus activities stop until an interrupt request or reset occurs The system clock generator continues operation and the clock signals MCLK SMCLK and ACLK stay active depending on the state of the other three status register bits SCGO SCG1 and OscOff The peripherals are enabled or disabled with their individual control register settings and with the module enable registers in the SFRs All I O port pins and RAM registers are unchanged Wake up is possible through all enabled interrupts The following are examples of entering and exiting LPMO The method shown is applicable to all low power modes The following example describes entering into low power mode 0 program flow with switch to CPUOff Mod BIS 18h SR Enter LPMO enable general interrupt CPUOff 1 GIE 1 The PC is incremented during execution of this instruc
317. ed for the conversion clock when accurate conversion timing is required Figure 16 8 The Conversion Clock ADC10CLK Internal Oscillator ADC10SSEL ADADO ADC10DIV Vp Vn ADC10CLK Divide by ADC1005C 1 2 3 4 5 6 7 8 ACLK 10 Bit A D Converter Core MOGLIE SMCLK To Pin To Sample and Hold ADC10 16 17 Sampling The conversion starts after the sample period is completed see the Sampling section A total of thirteen conversion clocks ADC10CLK are required to complete a conversion 12 ADC10CLKs and store the result in ADC10MEM 1 ADC10CLK The conversion time is tconversion 13 x ADC10DIV fApc10CLK Where ADC10DIV is any integer from 1 to 8 The ADC10CLK frequency must not exceed the maximum and minimum frequencies specified in the data sheet Either violation may result in inaccurate conversion results _ Note Availability of ADC10CLK During Conversion Users must ensure that the clock chosen for ADC10CLK remains active until the ADC10 can complete its operation If the clock is removed while the ADC10is active the operation can not be completed and the end of conver sion feedback to the program is not possible 1 16 6 Sampling 16 6 1 Sampling Operation The sample and hold circuitry samples the analog signal with the 4 8 16 or 64 ADC10CLKs prior to the conversion Figure 16 9 Sample and Conversion Basic Signal Timing ADC10OSC Selected for
318. eferences have settled no additional settling time is required when selecting or changing the conversion range for each channel Settling time of external signals external signals must be settled before performing the first conversion after turning on the ADC12 Otherwise the conversion results will be false 15 6 Conversion Clock and Conversion Speed The conversion clock for the ADC12 ADC12CLK shown in Figure 15 13 can be selected from several sources and can be divided by any factor from 1 8 The ADC12CLK is used for the A D conversion and to generate the sampling period if pulse sampling mode is selected SHP 1 Possible clock sources are the internal oscillator ADC120SC MCLK and SMCLK The internal oscillator generates the ADC12OSC signal and is in the 5 MHz range see device data sheet for specifications The internal oscillator frequency will vary with individual devices supply voltage and temperature A stable clock source should be used for the conversion clock when accurate conversion timing is required Figure 15 13 The Conversion Clock ADC12CLK VR 12 bit A D converter core ADC12SSEL Internal Oscillator ADGIZON ADC12DIV ADC120SC ADC12CLK Divide by ACLK 1 2 3 4 5 6 7 8 MCLK SMCLK To Sample and Hold ADC12 15 21 Sampling 15 7 Sampling The conversion starts with the falling edge of the sample signal SAMPCON see th
319. egister Short Form Register Type Address Initial State DCO control DCOCTL Read write 056h 060h register Basic clock BCSCTL1 Read write 057h 084h System control 1 Basic clock BCSCTL2 Read write 058h reset System control 1 Digitally Controlled Oscillator DCO Clock Frequency Control DCOCTL is loaded with a value of 060h with a valid PUC condition DCO 2 DCO 1 DCO 0 MOD 4 MOD 3 MOD 2 MOD 1 MOD O rw 0 rw i 1 rw 0 rw 0 rw 0 rw 0 rw 0 DCOCTL 056h MOD 0 MOD 4 The MOD constant defines how often the discrete frequency fpco 1 is used within a period of 32 DCOCLK cycles During the remaining clock cycles 32 MOD the discrete frequency fpcoisused Whenthe DCO constantis setto seven no modulation is possible since the highest feasible frequency has then been selected DCO 0 DCO 2 The DCO constant defines which one ofthe eight discrete frequencies is selected The frequency is defined by the current injected into the dc generator 7 5 2 Oscillator and Clock Control Register 7 18 BCSCTL1 is affected by a valid PUC or POR condition XT2Off DIVA 1 DIVA 0 XT5V rw 1 rw 0 rw 0 rw BitO to Bit2 The internal resistor is selected in eight different steps Rsel 0 to Rsel 2 The value of the resistor defines the nominal frequency The lowest nominal frequency is selected by setting Rsel 0 Bit3 XT5V XT5V should always be reset Bit4 to Bitb selected source for ACLK is divided by DIVA 0 1
320. elected by the SHS bits in ADC10CTL1 There are four choices for the sample signal input ADC10SC Timer A OUTO Timer A OUT1 and Timer A OUT2 The polarity of the sample signal input may be selected by the ISSH bit see Figure 16 1 The sample signal input can be asynchronous to a conversion enable and is synchronized and enabled by the ENC bit Without synchronization the first sampling period after the ENC bit is set could be erroneous depending on where the ENC bit is set within the cycle of the input signal In Figure 16 11 for example note that the ENC bit is set in the middle of a high pulse from the sample signal input If the sample input signal were simply passed directly to the S H the first conversion of the example would be erroneous because the first sampling period is too short To prevent this problem synchronization logic is implemented in the sample input selection switch This ensures thatthe first sample and conversion cycle begins with the first rising edge of the sample input signal applied after the ENC bit is set Additionally the last sample and conversion begins with the first rising edge of the sample input signal after ENC has been reset Figure 16 11 Synchronized Sample and Conversion Signal With Enable Conversion Enable si GU am e ENC tENC Sample Signal Poa te ome oe ae Input tesync a es ys ago ug so Sample and conversions Trigger signal enabled ADC10 ee Sampling
321. em 6 2 TDI TDO MAB 16 Bit CPU Test Incl 16 Reg JTAG MDB 16 Bit _ _ r TMS TCK Hardware Multiplier Operation 6 2 Hardware Multiplier Operation The hardware multiplier has two 16 bit registers for both operands and three registers to store the results of the multiplication The multiplication is executed correctly when the first operand is written to the operand register 1 prior to writing the second operand to OP2 Writing the first operand to the applicable register selects the type of multiplication Writing the second operand to OP2 starts the multiplication Multiplication is completed before the result registers are accessed using the indexed address mode for the source operand When indirect or indirect autoincrement address modes are used another instruction is needed between the writing of the second operand and accessing the result registers Both operands OP1 and OP2 utilize all seven address mode capabilities No instruction is necessary for the multiplication as a result the real time operation does not require additional clock cycles and the interrupt latency is unchanged The multiplier architecture is illustrated in Figure 6 2 Figure 6 2 Block Diagram of the MSP430 16x16 Bit Hardware Multiplier 15 rw 0 0 15 rw 0 Operand 2 138h
322. en URXEIE is reset URXIFG is unchanged All types of characters URXWIE 0 or only address characters URXWIE 1 set the interrupt flag URXIFG When URXEIE is set erroneous characters can also set the interrupt flag URXIFG Figure 12 14 Receive Interrupt Operation SYNC Valid Start Bit URXS Receiver Collects Character d URXSE e From URXD eee 6 05 Erroneous Character Will Not Set Flag URXIFG URXIE Request BRK SYNC Interrupt Service URXEIE URXIFG URXWIE RXWake SWRST Each Character or Address Character Received L Will Set Flag URXIFG 1 or unie m n a SS Break Detected URXSE IRQA URXIFG is reset by a system reset PUC signal or with a software reset SWRST URXIFG is reset automatically if the interrupt is served URXSE 0 or the receive buffer UxRXBUF is read A set receive interrupt flag URXIFG indicates that an interrupt event is waiting to be served A set receive interrupt enable bit URXIE enables serving a waiting interrupt request Both the receive interrupt flag URXIFG and the receive interrupt enable bit URXIE are reset with the PUC signal and a SWRST Signal URXIFG can be accessed by the software whereas signal URXS cannot When both interrupt events character receive action and receive start detection are enabled by the software the flag URXIFG indicates that a ch
323. ent low power modes The requirements of the user s application and the type of clocking circuit on the MSP430 device determine how the Watchdog Timer and clocking signals should be configured Review the device data sheet and clock system chapter to determine the clocking circuit clock signals and low power modes available For example the WDT should not be configured in watchdog mode with SMCLK as its clock source if the user wants to use low power mode 3 because SMCLK is not active in LPMS therefore the WDT would not function properly The WDT hold condition can also be used to support low power operation The hold condition can be used in conjunction with low power modes when needed The Watchdog Timer 9 1 3 4 Software Example The following example illustrates the watchdog reset operation After RESET or power up the WDTCTL register and WDTCNT are cleared and the initial operating conditions are watchdog mode with a time interval of 32 ms As long as watchdog mode is selected watchdog reset has to be done periodically through an instruction e g MOV WDTPW WDTCNTCL amp WDTCTL To change to timer mode and a time interval of 250 ms the following instruction sequence can be used MOV WDTPW WDTCNTCL WDTTMSEL WDTISO amp WDTCTL Clear WDTCNT and select 250 ms and timer mode Note The time interval and clear of WDTCNT should be modified within one instruction to avoid 5 u
324. entire module This can vary for each device configuration and the exact implementation should be noted in the data sheet The erase operation starts with the following sequence 1 Setthe correct input clock frequency of the timing generator by selecting the clock source and predivider 2 Reset the LOCK control bit if set 3 Watch the BUSY bit Continue to the next steps only if the BUSY bit is reset 4 Setthe erase control bit Erase to erase a segment or 5 Setthe mass erase control bit MEras to erase all numbered segments 6 Set the mass erase MEras and erase Erase control bits to erase all flash memory segments 7 Execute a dummy write to any address in the range to be erased Flash Memory Data Structure and Operation The dummy write starts the erase cycle An example of dummy write is CLR amp 0F012h Note that a dummy write is ignored in a segment where the selected operation can not be executed successfully An example of such a situation can take place when Segment 1 is to be erased the control bits are set properly but the dummy write is sent to the information memory No flag indicates this unsuccessful erase situation Figure C 7 Basic Flash EEPROM Module Timing During the Erase Cycle gt lt gt lt Erase Operation Active Generate Remove Erase Voltage Entire Erase Cycle Timing Prase Voltage amp Time of Increased Current Consumption From Supply BU
325. er peripheral file address range where all byte modules are located and should be accessed with byte instructions suffix B Table 14 1 Comparator A Control Registers Short Initial Register Form Register Type Address State e control register 1 CACTL1 Read write 059h Reset C Acontrol register 2 CACTL2 Read write 05Ah Reset e C A port dissipation reg CAPD Read write 05Bh Reset 14 3 1 Comparator A Control Register 1 14 6 The control register CACTL1 is shown and described below 7 0 CACTL1 CA CA CA 059h CAEX RSEL REF1 REFO CAON CAIES CAIE CAIFG rw 0 CAIFG bitO CAIE bit1 CAIES bit2 CAON bit3 CAREF bit4 5 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 The Comparator_A interrupt flag The Comparator_A interrupt enable The Comparator_A interrupt edge select bit 0 The rising edge of the comparator output sets the Comparator_A interrupt flag CAIFG 1 The falling edge of the comparator output sets the Comparator_A interrupt flag CAIFG The comparator is switched on or off When off the current consumption of the comparator is stopped The current consumption of the reference circuitry is enabled or disabled independently 0 The comparator is disabled current consumption is stopped and the output of the comparator is low 1 The comparator is enabled and active 0 Internal reference is switched off An external reference can be applied 1 0 25 Vcc reference is sele
326. er Byte Access A 5 6 Comparator A Registers Byte Access A 5 A 7 USARTO USART1 UART Mode Sync 0 Byte Access A 6 A 8 USARTO USART1 SPI Mode Sync 1 Byte Access A 7 A 9 ADC12 Registers Byte and Word Access A 8 10 ADC10 Registers Byte and Word Access A 11 A 11 Watchdog Timer Word Access A 12 A 12 Flash Control Registers Word ACCeSS A 13 13 Hardware Multiplier Word Access A 14 14 Timer A Registers Word ACCESS A 14 15 Timer B Registers Word lt 5 A 16 A 1 Overview A 1 Overview A 2 Bit accessibility and or hardware definitions are indicated following each bit symbol EI ob E ES LEE A D DO UL rw r r0 r1 w 0 wi Read write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented writing a 1 results in a pulse The register bit is always read as 0 Cleared by hardware Set by hardware Condition after PUC signal active Condition after POR signal active The tables in the following sections describe byte access to each peripheral file according to the previously described definitions Special Function Register of MSP430x1xx Family Byte Access
327. er from 2 to 12 in the TAIV register as shown in Table 10 9 If the value of the TAIV register is 0 no interrupt is pending This number can be added to the program counter to automatically enter the appropriate software routine without the need for reading and evaluating the interrupt vector The software example in section 10 6 4 3 shows this technique 10 30 Timer A Registers Table 10 9 Vector Register TAIV Description Interrupt Vector Register Priority Interrupt Source Short Form TAIV Contents Highestt Capture compare 1 CCIFG1 2 Capture compare 2 CCIFG2 4 Reserved 6 Reserved 8 Timer overflow TAIFG 10 Reserved 12 Lowest Reserved 14 No interrupt pending 0 T Highest pending interrupt other than CCIFGO CCIFGO is always the highest priority Timer interrupt Accessing the TAIV register automatically resets the highest pending interrupt flag If another interrupt flag is set then another interrupt will be immediately generated after servicing the initial interrupt For example if both CCIFG1 and CCIFG2 set when the interrupt service routine accesses the TAIV register either by reading it or by adding it directly to the PC CCIFG1 will be reset automatically After the RETI instruction of the interrupt service routine is executed the CCIFG2 flag will generate another interrupt V7 1 Note Writing to Read Only Register TAIV Register TAIV should not be written to If a write operation to TAIV is performed t
328. erial communication with MSB is shifted first BIT B RCV RCCTL Bit info into carry RLC B RECBUF Carry gt LSB of RECBUF XXXX XXXC SS repeat previous two instructions 8 times CCCC CCCC sl LSB MSB Instruction Set Description B 15 Instruction Set Overview BR BRANCH Syntax Operation Emulation Description Status Bits Example Branch to destination BR dst dst PC MOV dst PC An unconditional branch is taken to an address anywhere in the 64K address space All source addressing modes can be used The branch instruction is a word instruction Status bits are not affected Examples for all addressing modes are given BR Branch to label EXEC or direct branch e g 0A4h Core instruction MOV PC PC BR EXEC Branch to the address contained in EXEC Core instruction MOV X PC PC Indirect address BR amp EXEC Branch to the address contained in absolute address EXEC Core instruction MOV 0 Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC Indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer in R5 afterwards The next time S W flow uses R5 pointer it can alter program execution due to access to address
329. ers ADC12TOVIE bit2 Conversion time overflow interrupt enable The timing overflow happens if another sample and conversion is requested while the current conversion is not completed This is independent of the conversion modes selected by CONSEQ If the timing overflow vector is generated and the timing overflow interrupt enable flag ADC12TOVIE and the general interrupt enable bit GIE are set an interrupt service is requested There is no individual interrupt flag See the ADC12 Interrupt Vector Register ADC 121V section for more information on ADC12 interrupts ADC12OVIE Overflow interrupt enable Individual enable for the overflow interrupt vector The overflow happens if a conversion result is written into an ADC memory ADC12MEMXx but the previous result was not read An interrupt service is requested if the overflow vector is generated the overflow interrupt enable flag ADC12OVIE is set and the general interrupt enable bit GIE is set There is no individual interrupt flag See the ADC12 Interrupt Vector Register ADC 12IV section for more information on ADC12 interrupts ADC120N bit4 Turn on the 12 bit ADC core Settling time constraints must be met when the ADC 12 core is powered up 0 Power consumption of the core is off No conversion will be started 1 ADC core is supplied with power If no A D conversion is needed ADC12ON can be reset to conserve power REFON bit5 Reference voltage ON 0 The internal reference voltage
330. eset the enable conversion bit ENC When this is done the current conversion stops immediately However the data in memory register ADC12MEMx is unpredictable and the associated interrupt flag ADC12IFG x or may not be set This method is generally not recommended Conversion Modes An illustration of repeat single channel mode is shown in Figure 15 11 Figure 15 11 Repeat Single Channel Mode CONSEQ 2 ADC120N 1 x CStartAdd Wait for Enable SHS 0 and ENC 10r4 and ADC12SC Wait for Trigger ENC 0 SAMPCON 47 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx SAMPCON Y lt 12 x ADC12CLK MSC 1 and SHP 1 and ENC 1 Convert Use 12 x ADC12CLK 1 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMXx ADC12IFG x is Set 15 5 4 Repeat Sequence of Channels Mode The repeat sequence of channel mode is identical to the sequence of channel mode except the sequence is repeated continuously until stopped by software Each time a conversion is completed the results are loaded into the appropriate ADC12MEMXx register and the corresponding interrupt flag ADC12IFG x is set to indicate completion of the conversion Additionally If the appropriate interrupt enable flags are set an interrupt request is generated see the ADC12 Interrupt Vector Register ADC 12IV section The conversion mode
331. esses to address the same register The different address information is decoded and defines the type of multiplication operation used Figure 6 3 Registers of the Hardware Multiplier 6 6 15 130 132 MAC 134h MACS 136h bos nd OP2 138h Operand 2 OP2 ResLo 13Ah Result Low Word ResLo ResHi 13Ch Result High Word ResHi SumExt 13Eh Sum Extension Word SumExt The multiplication result is located in two word registers result high RESHI and result low RESLO The sum extend register SumExt holds the result sign of a signed operation or the overflow of the multiply and accumulate MAC operation See Section 6 5 3 for a description of overflow and underflow when using the MACS operations All registers have the least significant bit LSB at bitO and the most significant bit MSB at bit7 byte data or bit15 word data Hardware Multiplier Special Function Bits 6 4 Hardware Multiplier Special Function Bits Because the hardware multiplier module completes all multiplication operations quickly without interrupt intervention no special function bits are used 6 5 Hardware Multiplier Software Restrictions 6 5 1 Two restrictions require attention when the hardware multiplier is used The indirect or indirect autoincrement address mode used to process the result The hardware multiplier used in an interrupt routine Hardware Multiplier Software Restricti
332. esult LSB 0158h ro ro 0 ro All conversion result bits of type rw ADC12MEM 11 Unused Unused Unused Unused MSB Conversion Result LSB 0156h ro ro 0 ro conversion result bits of type rw ADC12MEM 10 Unused Unused Unused Unused MSB Conversion Result LSB 0154h ro ro 0 ro All conversion result bits of type rw 12 9 Unused Unused Unused Unused MSB Conversion Result LSB 0152h ro ro 0 ro All conversion result bits of type rw ADC12MEM8B Unused Unused Unused Unused MSB Conversion Result LSB 0150h ro ro 0 ro All conversion result bits of type rw 0 0 0 0 0 0 0 2 p p ADC12MEM7 Unused Unused Unused Unused MSB Conversion Result LSB 014Eh ro ro r ro All conversion result bits of type rw ADC12MEM6 Unused Unused Unused Unused MSB Conversion Result LSB 014Ch ro ro r ro All conversion result bits of type rw ADC12MEM5 Unused Unused Unused Unused MSB Conversion Result LSB 014Ah ro ro r ro All conversion result bits of type rw ADC12MEM4 Unused Unused Unused Unused MSB Conversion Result
333. et Function select P1SEL Read write 026 Reset Table 8 2 Port P2 Registers Short Register Register Form Type Address Initial State Input P2IN Read only 028 Output P2OUT Read write 029h Unchanged Direction P2DIR Read write 2 Reset Interrupt flags P2IFG Read write O2Bh Reset Interrupt edge select P2IES Read write 02 Unchanged Interrupt enable P2IE Read write 02Dh Reset Function select P2SEL Read write O2Eh Reset These registers contain eight bits and should be accessed using byte instructions in absolute address mode 8 2 1 1 Input Registers P1IN P2IN Both Input registers are read only registers that reflect the signals at the I O pins Note Writing to Read Only Registers P2IN Writing to these read only registers results in increased current consumption while the write attempt is active 8 4 Ports P1 P2 8 2 1 2 Output Registers P1OUT 2 0 Each output register shows the information of the output buffer The output buffer can be modified by all instructions that write to a destination If read the contents of the output buffer are independent of pin direction A direction change does not modify the output buffer contents 8 2 1 3 Direction Registers P1DIR P2DIR The direction registers contain eight independent bits that define the direction of the I O pin All bits are reset by the PUC signal When Bit 0 The port pin is switched to input direction 3 state Bit 1
334. executed See also paragraph C 1 1 and Figure C 9 0 No block write accelerate is selected 1 Block write is used This bit needs to be reset and set between borders of blocks Flash Memory Control Registers C 3 2 Flash Memory Control Register FCTL2 A PUC resets the flash timing generator The generator is also reset if the emergency exit bit EMEX is set The timing generator generates the timing necessary to write erase and mass erase from a selected clock source Two control bits SSELO and SSEL1 in control register FCTL2 can select one of three clock sources The clock source selected should be divided to meet the frequency requirements for fy as specified in the device s data sheet Writing to control register FCTL2 should not be attempted if the BUSY bit is set otherwise an access violation will occur ACCVIFG 1 Read access to FCTL2 is possible at any time without restrictions FCTL2 012Ah FCTL2 read 096h W 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw i rw O0 FCTL2 write 0 5 gt control bits are FNO 012Ah bitO These six bits define the division rate of the clock signal The division to rate can be 1 to 64 depending on the digital value of FN5 to FNO FN5 012Ah bit5 Plus one SSELO 012Ah Determine the clock source SSEL1 0124Ah bit6 bit 7 0 ACLK 1 MCLK 2 3 SMCLK Flash Memory C 15 Flash Memory Control Registers C 3 3 Flash Memory Control Register FCTL3 There are no restr
335. exist because there is always some parasitic coupling capacitance across the switch and between switches This can take several forms such as coupling from the input to the output of an off switch or coupling from an off analog input channel to the output of an adjacent on channel For high accuracy conversions crosstalk interference should be minimized by shielding and other well known printed circuit board PCB layout techniques Analog Inputs and Multiplexer 16 3 2 Input Signal Considerations During sampling the analog input signal is applied to the internal capacitor array of the A D core Therefore the charge of the capacitor array is supplied directly by the source The capacitor array has to be charged completely during the sampling period Therefore the external source resistances dynamic impedances and capacitance of the capacitor array must be matched with the sampling period so the analog signal can settle to within 10 bit accuracy Additionally source impedances also affect the accuracy of the converter The source signal can drop at the input of the device due to leakage current or averaged dc input currents due to input switching currents For a 10 bit converter the error in LSBs due to leakage current is Error LSBs 1024 x uA of leakage current x of source resistance VR Vn For example a 50 nA leakage current with a 10 kQ source resistance and a 1 5 V Vngr gives 1 3 LSBs of error These errors
336. f capture compare block 4 CCIFG1 CCIFG2 CCIFG3 0 10 CCIFG5 flag set interrupt flag of capture compare block 5 CCIFG1 CCIFG2 CCIFG3 CCIFG4 0 12 CCIFG6 flag set interrupt flag of capture compare block 6 CCIFG1 CCIFG2 CCIFG3 CCIFG4 CCIFG5 0 14 TBIFG flag set interrupt flag of Timer B register counter CCIFG1 CCIFG2 CCIFG3 CCIFG4 CCIFG5 CCIFG6 0 TBIV Vector Timer_B3 three capture compare blocks integrated 0 No interrupt pending 2 CCIFG1 flag set interrupt flag of capture compare block 1 4 CCIFG2 flag set interrupt flag of capture compare block 2 CCIFG1 0 6 Reserved 8 Reserved 10 Reserved 12 Reserved 14 TBIFG flag set interrupt flag of Timer B register counter CCIFG1 CCIFG2 0 A 18 Appendix B Instruction Set Description The MSP430 core CPU architecture evolved from a reduced instruction set with highly transparent instruction formats Using these formats core instructions are implemented into the hardware Emulated instructions are also supported by the assembler Emulated instructions use the core instructions with the built in constant generators CG1 and CG2 and or the program counter PC The core and emulated instructions are described in detail in this section The emulated instruction mnemonics are listed with examples Program memory words used by an instruction vary from one to three words depending on the combination of addressing modes Topic Page B 1 Instruction Set Overview
337. f it were configured for continuous mode It will not count down from TBR may to zero Figure 11 16 Altering TBCLO Timer in Up Down Mode Timer Register 5 4 3 Tin ES Hl lil lil 0 11213 415 413121110 112131413121110 1 213 2111011111011 213 4151413121110111211 TBCLO 2 11 14 Timer Modes 11 4 Capture Compare Blocks Seven identical capture compare blocks shown in Figure 11 17 provide flexible control for real time processing Any one of the blocks may be used to capture the timer data at an applied event or to generate time intervals Each time a capture occurs or a time interval is completed interrupts can be generated from the applicable capture compare register The mode bit CAPx in control word CCTLx selects the compare or capture operation and the capture mode bits CCMx1 and in control word CCTLx define the conditions under which the capture function is performed Both the interrupt enable bit CCIEx and the interrupt flag CCIFGx are used for capture and compare modes CCIEx enables the corresponding interrupt CCIFGx is set on a capture or compare event Thecapture inputs CCIxA and CCIxB are connected to external pins or internal signals Different MSP430 devices may have different signals connected to CCIxA and CCIxB The data sheet should always be consulted to determine the Timer B connections for a particular dev
338. family products by assembling together and presenting hardware and software information in a manner that is easy for engineers and programmers to use This manual discusses modules and peripherals of the MSP430x1 xx family of devices Each discussion presents the module or peripheral in a general sense Not all features and functions of all modules or peripherals are present on all devices In addition modules or peripherals may differ in their exact implementation between device families or may not be fully implemented on an individual device or device family Therefore a user must always consult the data sheet of any device of interest to determine what peripherals and modules are implemented and exactly how they are implemented on that particular device How to Use This Manual This document contains the following chapters Chapter 1 Introduction Chapter 2 Architectural Overview Chapter 3 System Resets Interrupts and Operating Modes Chapter 4 Memory Chapter 5 16 Bit CPU Chapter 6 Hardware Multiplier Chapter 7 Basic Clock Module Chapter 8 Digital I O Configuration Chapter 9 Watchdog Timer Chapter 10 Timer A Chapter 11 Timer B Chapter 12 USART Peripheral Interface UART Mode Chapter 13 USART Peripheral Interface SPI Mode Related Documentation From Texas Instruments Chapter 14 Comparator A Chapter 15 ADC12 Chapter 16 ADC10 Appendix A Peripheral Fil
339. ferent output modes of each output unit are useful to capture timer data based on external events or to generate various different types of output signals Examples of the different output modes used with timer continuous mode are shown in Figure 10 25 In continuous mode the timer starts counting from its present value The counter counts up to OFFFFh and restarts by counting from zero as shown in Figure 10 9 Figure 10 9 Timer Continuous Mode OFFFFh Oh The TAIFG flag is set when the timer counts from OF FFFh to zero The interrupt flag is set independently of the corresponding interrupt enable bit as shown in Figure 10 10 An interrupt is requested if the corresponding interrupt enable bit and the GIE bit are set Figure 10 10 Continuous Mode Flag Setting Timer Clock Timer Set Interrupt Flag TAIFG Timer_A 10 9 Timer Modes 10 3 3 1 Timer Use of the Continuous Mode The continuous mode can be used to generate time intervals for the application software Each time an interval is completed an interrupt can be generated In the interrupt service routine of this event the time until the next event is added to capture compare register CCRx as shown in Figure 10 11 Up to five independent time events can be generated using all five capture compare blocks Figure 10 11 Output Unit in Continuous Mode for Time Intervals Interrupt Events OFFFFh CCROf CCROI CCRO0e CCROd CCROc CCROb CCR0a
340. flash memory is ready for access again The following interrupt enable bits should be reset to stop all interrupt service requests GIE 0 NMIIE ACCVIE OFIE 0 Additionally the watchdog should be halted to prevent its expiration when flash memory is busy WDTHOLD 1 When the flash memory is ready the interrupt sources can be enabled again Before they are enabled critical interrupt flags should be checked and if necessary served or reset by software GIE 1 or left disabled or be restored to the previous level NMIIE ACCVIE OFIE 1 or left disabled or be restored to the previous level J WDTHOLD 0 or left disabled or be restored to the previous level Flash Memory C 21 Flash Memory Access via JTAG and Software C 5 Flash Memory Access via JTAG and Software C 5 1 Flash Memory Protection Flash memory access via the serial test and programming interface JTAG can be inhibited when the security fuse is activated The security fuse is activated via serial instructions shifted into the JTAG Activating the fuse is not reversible and any access to the internal system is disrupted The bypass function described in the IEEE1149 1 standard is active C 5 2 Program Flash Memory Module via Serial Data Link Using JTAG Feature The hardware interconnection to the JTAG pins is done via four separate pins plus the ground or Vss reference level The JTAG pins are TMS TDI VPP and TDO
341. for availability of pin The reference voltage level for can be selected to be AVss or may be supplied externally through the Vngr Vepmgr pin check device data sheet for Vngr Vengr pin If the Vagp Vepgr pin is not available then Vp is connected to AVss Configuration of the reference voltage s is done with the Sref bits bits 13 14 and 15 in the ADC10CTLO register Up to six combinations of positive and negative reference voltages are supported as described in Table 16 1 If only external references are used the internal reference generator can be turned off with the REFON bit to conserve power Table 16 1 Reference Voltage Configurations Sref Voltage at Voltage at Vp 0 AVcc AVss 1 VREFf internal AVSS 2 3 Vengr external AVss 4 AVcc VngEr Veger internal or external 5 VREF4 internal VREF Veger internal or external 6 7 Vengr external Vngr Veger internal or external The voltage levels Vg and Vp establish the upper and lower limits of the analog inputs to produce a full scale and zero scale reading respectively The values of Vn and the analog input should not exceed the positive supply or be lower than AVgg consistent with the absolute maximum ratings specified in the device data sheet The digital output is full scale when the input signal is equal to or higher than and zero when the input signal is equal to or lower than Vp Warning Reference Voltage
342. for the appropriate pin on which the reference voltage is available Maximum sample rate selection of the ADC10 0 Maximum sample rate is 200 ksps 1 Reduced sample rate is 50 ksps Reducing the maximum sampling rate of the ADC10 reduces the current consumption of the internal reference buffer Select the slower sampling rate to save system power consumption See the device data sheet for actual sampling rate data Selects the number of ADC10CLKs for the sample time 0 4 x ADC10CLKs 1 8 x ADC10CLKs 2 16 x ADC10CLKs 3 64 x ADC10CLKs The Sref bits select one of six reference voltage combinations used for conversion The conversion is done between the selected voltage range Vn and Vn 0 Vn AVcc and Vn AVss 1 Vn VREF and VR AVss 2 3 Vn VeREF and VR AVss 4 VR and Vp Vngr Vengr 5 VR VREF and Vn VREF Vengr 6 7 VR Verner and Vp Vngr VenEgr ADC10 Control Registers rw 0 rw rw l ADC10CTL1 ADC10 ADC10 0 0 rw 0 0 rw 0 rw 0 0 rw 0 0 0 rw 0 ADC10BUSY bito CONSEQ ADC10SSEL ADC10DIV ISSH ADC10DF rw 0 bits 1 2 bits 3 4 bits bit8 bit9 rw 0 rw 0 rw rw 0 rw The ADC10BUSY bit indicates an active sample or conversion operation It is used specifically when the conversion mode is single channel single conversion because if the ENC bit is reset in this mode the conversion stops immedia
343. for the source src S reg The working register used for the source src Ad The addressing bits responsible for the addressing mode used for the destination dst D reg The working register used for the destination dst B W Byte or word operation 0 word operation 1 byte operation DET Ls Se eS gt Note Destination Address Destination addresses are valid anywhere in the memory map However when using an instruction that modifies the contents of the destination the user must ensure the destination address is writeable For example a masked ROM location would be a valid destination address but the contents are not modifiable so the results of the instruction would be lost 16 Bit CPU 5 17 Instruction Set Overview 5 3 1 Double Operand Format 1 Instructions Figure 5 7 illustrates the double operand instruction format See section 5 2 8 for information on number of code words and execution cycles per instruction Figure 5 7 Double Operand Instruction Format 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Table 5 17 describes the effects of an instruction on double operand instruction status bits Table 5 17 Double Operand Instruction Format Results Mnemonic S Reg D Reg Operation Status Bits V N 2 src dst Src dst ADD src dst src dst dst X 2 ADDC src dst src dst C dst E i SUB src dst dst not src
344. g able to access the stack and stack pointer with the instruction set allows the program structures to be individually optimized as illustrated in the following program flow Enter interrupt routine The interrupt routine is entered and processed if an enabled interrupt awakens the MSP430 B TheSRandPC are stored on the stack with the content present at the interrupt event B Subsequently the operation mode control bits OscOff SCG1 and CPUOff are cleared automatically in the status register System Resets Interrupts and Operating Modes 3 23 Operating Modes Return from interrupt Two different modes are available to return from the interrupt service routine and continue the flow of operation B Return with low power mode bits set When returning from the interrupt the program counter points to the next instruction The instruction pointed to is not executed since the restored low power mode stops CPU activity B Return with low power mode bits reset When returning from the interrupt the program continues at the address following the instruction that set the OscOff or CPUOff bit in the status register To use this mode the interrupt service routine must reset the OscOff CPUOff SCGO and SCG1 bits on the stack Then when the SR contents are popped from the stack upon RETI the operating mode will be active mode AM There are six operating modes that the software can configure Lj Active mode AM SCG1 0 5
345. g this operation the module is disconnected from the memory address 2 Flash Memory Organization bus and memory data bus When a second module here Module2 is implemented program code in this module can be executed while Modulet1 is disconnected Figure 2 Flash Memory Module1 Disabled Module2 Can Execute Code Simultaneously e DM oe SEIT UU ete 1 ROM RAM TDI 4 TDO TDI lt 16 Bit 2 2 CPU _ Test To Other Incl 16 Reg JTAG Peripheral Modules NZ NZ X 16 Bit TMS TCK Flash Flash Test VPP Optional Module 1 Module 2 P HEP RN E One MSP430 flash memory module will have in addition to its code segments extra flash memory called information memory Flash Memory C 3 Flash Memory Organization Figure 3 Flash Memory Module Example ONE module Flash Memory 4Kbyte 256Byte 4 FFFFh FOOOh 010FFh 256 Byte 01000h Flash Memory A module has several segments The information memory has two segments of 128 bytes each In the example in Figure C 4 the 4 kB module has eight segments of 512 bytes Segment0 to Segment7 and two 128 byte segments SegmentA and SegmentB SegmentO0 to
346. ge and shifted into the receive shift register on the opposite edge For the slave the data shifting operation is the same and uses one common register for transmitting and receiving data Master and slave send and receive data at the same time Whether the data is meaningful or dummy data depends on the application software Master sends data and slave sends dummy data Master sends data and slave sends data Lj Master sends dummy data and slave sends data Figures 13 4 and 13 5 show an example of a serial synchronous data transfer for a character length of seven bits The initial content of the receive shift register is 00 The following events occur in order A Slave writes 98h to the data shift register DSR and waits for the master to shift data out B Master writes BOh to UxTXBUF which is immediately transferred to the transmit shift register and starts the transmission C First character is finished and sets the interrupt flags D Slave reads 58h from the receive buffer right justified E Slave writes 54h to the DSR and waits for the master to shift out data F Master reads 4Ch from the receive buffer UXRXBUF right justified G Master writes E8h to the transmit buffer UxTXBUF and starts the transmission Note If USART is in slave mode no UCLK is needed after D until G However in master mode two clocks are used internally not on UCLK signal to end transmit receive of first character and prep
347. h Address MOV FWKEY WRT amp FCTL1 Enable write to flash MOV 1H23h amp 0FF1Eh Write a word to flash Test Busy2 BIT BUSY amp FCTL3 still busy JNZ Test_Busy2 yes repeat busy test MOV FWKEY amp FCTL1 Reset write bit XOR FXKEY LOCK amp FCTL3 Change lock bit to 1 Restore or Enable Required Enable those interrupt sources that should be accepted Interrupt Sources and Watchdog The BUSY bit can be tested before the write to the flash memory module is don e or after write program starts For flash memory locations that hold data it is a good practice to test the BUSY bit before the write is executed This has some time benefits since the write process is executed via the flash memory timing generator with out further CPU intervention It is important that the clock source remains active until BUSY is reset by the flash memory hardware The power or clock management responsible for entering low power modes has to make sure that it does not switch off the clock source used by the flash controller For flash memory blocks that hold program code it is a good practice to test the BUSY bit after the write is executed The program can only proceed if the module can be accessed again No special attention is needed during execution of software code Every write to the flash memory module has to leave the programming cycle with the BUSY bit reset Testing the BUSY bit before writing to a flash memory
348. h automatically clears the appropriate system register bits This results in a system configuration for the WDTCTL bits where the WDT is set into the watchdog mode and the RST NMI pin is switched to the reset configuration After a power on reset or a system reset the WDT module automatically enters the watchdog mode and all bits in the WDTCTL register and the watchdog counter WDTCNT are cleared The initial conditions at register WDTCTL cause the WDT to start running at a relatively low frequency due to the range of the digitally controlled oscillator DCO automatically being set in these situations Since the WDTONT is reset the user software has ample time to set up or halt the WDT and to adjust the system frequency Users must refer to the specific data sheets and the clock system chapter of this manual to determine the details of the clocking circuit on the MSP430 device chosen Watchdog Timer 9 5 The Watchdog Timer 9 1 3 2 Timer Mode When the module is used in watchdog mode the software should periodically reset the WDTCNT by writing a 1 to bit CNTCL of WDTCTL to prevent expiration of the selected time interval If a software problem occurs and the time interval expires because the counter is no longer being reset a system reset is generated and a system PUC signal is activated The system restarts atthe same program address that follows a power up The cause of reset can be determined by testing bit O of interrupt flag register 1
349. h bit REFON 0 to reduce power consumption When using an external reference the internal reference can be powered off completely but the current consumption of the external reference must be taken into account for the application When the internal reference is used the maximum conversion rate can be reduced to about 50Ksps see device data sheet with bit ADC10SR This reduces the current consumption of the internal reference and reference buffer When the internal reference voltage is routed externally with bit REF Out users may choose to have it continuously present externally or to have it externally present only during the sample and conversion period This choice is made with bit REFBurst When both REF Out and REFBurst bits are set the reference is present externally only during the sample and conversion period When bit REF Out is set and bit REFBurst is cleared the reference voltage is continuously present externally see Figure 16 20 Note that the bits control the enabling or disabling of the reference voltage buffer Therefore when the reference voltage is continuously preset externally the reference buffer remains continuously on and increases the current consumption of the system regardless of the presence of a load on the pin or not Figure 16 20 Detail Block Diagram of the Internal Reference AVCC REF AVSS 16 40 S amp C a10 Selected r L REFON REFBurst REF Out S amp C
350. he output mode is 0 Timer A 10 27 Timer A Registers Bit 3 Bit 4 Bits 5 to 7 Capture compare input signal CCIx The selected input signal CCIxA CCIxB Vcc or GND can be read by this bit See Figure 10 18 Interrupt enable CCIEx Enables or disables the interrupt request signal of capture compare block x Note that the GIE bit must also be set to enable the interrupt 0 Interrupt disabled 1 Interrupt enabled Output mode select bits Table 10 7 describes the output mode selections Table 10 7 Capture Compare Control Register Output Mode 10 28 vals Output Mode Description 0 Output only The OUTx signal reflects the value of the OUTx bit 1 Set EQUx sets OUTx 2 PWM toggle reset EQUx toggles OUTx EQUO resets OUTx 3 PWM set reset EQUx sets OUTx EQUO resets OUTx 4 Toggle EQUx toggles OUTx signal 5 Reset EQUx resets OUTx 6 PWM toggle set EQUx toggles OUTx EQUO sets OUTx 7 PWM reset set EQUx resets OUTx EQUO sets OUTx Note OUTx updates with rising edge of timer clock for all modes except mode 0 Modes 2 3 6 7 not useful for output unit 0 Bit 8 Bit 9 Bit 10 Bit 11 Bits 12 13 CAP sets capture or compare mode 0 Compare mode 1 Capture mode Read only always read as 0 SCCIx bit The selected input signal CCIxA CCIxB Vcc or GND is latched with the EQUx signal into a transparent latch and can be read via this bit SCSx bit This bit is used to synchronize the
351. he Switching Between Conversion Modes section ADC10 Conversion Modes 16 14 There are four ways to stop repeat sequence of channels conversions 1 Select sequence of channels mode CONSEQ 1 instead of repeated sequence of channels mode CONSEQ 3 When this is done the current sequence of conversions is completed normally and no further conversions take place The conversion result is loaded into register ADC10MEM and interrupt flag ADC10IFG is set Reset bit ENC ADC10CTLO 1 This stops the conversions after the current sequence is completed The conversion result is stored in register ADC10MEM and interrupt flag ADC10IFG is set Select repeat single channel mode CONSEQ 2 instead of the repeat sequence of channel mode and then select single channel mode The current conversion is completed normally The current conversion result is loaded into register ADC10MEM and interrupt flag ADC10IFG is set Select single channel mode CONSEQ 0 and reset enable conversion bit ENC The current conversion is stopped immediately The data in memory register ADC10MEM is unpredictable and interrupt flag ADC10IFG may may not be set This method is generally not recommended Figure 16 7 illustrates the repeat sequence of channels mode Conversion Modes Figure 16 7 Repeat Sequence of Channels Mode x INCH Wait for Enable SHS 0 and ENC 1or amp and ADC10SC lt 4 8 16 64 x ADC10CL
352. he input divider is reset by a POR signal see chapter 3 System Resets Interrupts and Operating Modes for more information on the POR signal or by setting the CLR bit in the TACTL register Otherwise the input divider remains unchanged when the timer is modified The state of the input divider is invisible to software Figure 10 3 Schematic of 16 Bit Timer SSEL1 SSELO Timer Clock Data o TACLK 0 0 Input Mode ACLK Divider Control Equo SMCLK 2 MES ID1 IDO y MC1 MCO Set_TAIFG POR CLR INCLK o3 0 0 Pass 0 0 Stop Mode 0 1 1 2 0 1 Up Mode 1 0 1 4 1 0 Continuous Mode 1 1 1 8 1 1 Up Down Mode Figure 10 4 Schematic of Clock Source Select and Input Divider SSEL1 SSELO TACLK 0 0 0 Input Divider 16 Bit Timer Clock INCLK o 63 Timer A 10 5 Timer A Operation 10 2 3 Starting the Timer 10 6 The timer may be started or restarted in a variety of ways m m Release Halt Mode The timer counts in the selected direction when a timer mode other than stop mode is selected with the MCx bits Halted by CCRO 0 restarted by CCRO gt 0 when the mode is either up or up down When the timer mode is selected to be either up or up down the timer may be stopped by writing to capture compare register 0 CCRO The timer may then be restarted by writing a nonzero value to CCRO In this scenario the timer starts incrementing in the up d
353. he interrupt flag of the highest pending interrupt is reset Therefore the requesting interrupt event is missed Additionally writing to this read only register results in increased current consumption as long as the write operation is active 10 6 4 3 Timer Interrupt Vector Register Software Example The following software example describes the use of vector word TAIV and the handling overhead The numbers at the right margin show the necessary cycles for every instruction The example is written for continuous mode the time difference to the next interrupt is added to the corresponding compare register Software example for the interrupt part Cycles Interrupt handler for Capture Compare Module 0 The interrupt flag CCIFGO is reset automatically IMMODO Js Start of handler Interrupt latency 6 RETI 5 Interrupt handler for Capture Compare Modules 1 to 4 The interrupt flags CCIFGx and TAIFG are reset by hardware Only the flag with the highest priority responsible for the interrupt vector word is reset TIM HND 5 Interrupt latency 6 ADD amp TAIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP TIMMOD1 Vector 2 Module 1 2 Timer_A 10 31 Timer A Registers 10 6 4 4 Timing Limits 10 32 JMP TIMMOD2 Vector 4 Module 2 2 RETI Reserved 2 RETI Reserved 2 Module 5 Timer Overflow Handler the Timer Register is expanded into the RAM location TIMEXT MSBs
354. he low byte TOM If the result is zero a branch is taken to label TONI AND B 0A5h TOM mask Lowbyte TOM with R5 JZ TONI Result is not zero BIC W BIC B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Overview Clear bits in destination Clear bits in destination BIC src dst or BIC W src dst BIC B src dst NOT src AND dst dst The inverted source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected N Not affected Z Not affected C Not affected V Not affected OscOff CPUOff and GIE are not affected The six MSBs of the RAM word LEO are cleared BIC 0FC00h LEO Clear 6 MSBs in MEM LEO The five MSBs of the RAM byte LEO are cleared BIC B 0F8h LEO Clear 5 MSBs in Ram location LEO Instruction Set Description B 13 Instruction Set Overview BIS W Set bits in destination BIS B Set bits in destination Syntax BIS src dst BIS W src dst BIS B src dst Operation src OR dst dst Description The source operand and the destination operand are logically ORed The result is placed into the destination The source operand is not affected Status Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OscOff CPUOff and GIE are not affected Example The six LSBs of the RAM word TOM are set BIS 003Fh TOM set the six LSBs in RAM
355. here JMP TIM HND Look for pending interrupts 2 Ifthe FLL on applicable devices is turned off then two additional cycles need to be added for a synchronous start of the CPU and system clock MCLK If the CPU clock MCLK was turned off in devices with the Basic Clock Module CPUOFF 1 then 2 or 3 additional cycles need to be added for synchronous start of the CPU The delta of one clock cycle is caused when clocks are asynchronous to the restart of CPU clock MCLK Timer B 11 39 Timer B Registers The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself as described Capture compare block CCRO 11 cycles Capture compare blocks CCR1 to CCR6 16 cycles Li Timer overflow TBIFG 14 cycles 11 6 4 5 Timing Limits 11 40 With the TBIV register and the previous software the shortest repetitive time distance tcRmin between two events using a compare register is tcRmin ttaskmax 16 X tcycle With ttaskmax Maximum worst case time to perform the task during the interrupt routine for example incrementing a counter Cycle time of the system frequency MCLK The shortest repetitive time distance between two events using a capture register is ttaskmax 16 X teycle Chapter 12 USART Peripheral Interface UART Mode The universal synchronous asynchronous receive transmit USART seria
356. here is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Setif an arithmetic overflow occurs otherwise reset OscOff CPUOff and GIE are not affected See example at the SBC instruction See example at the SBC B instruction _ Note Borrow Is Treated as a NOT The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 SUBC W SBB W SUBC B SBB B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Overview Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SUBC src dst or SUBC W src dst or SBB src dst or SBB W src dst SUBC B src dst or SBB B src dst dst NOT src C gt dst or dst src 1 C dst The source operand is subtracted from the destination operand by adding the Source operand s 1s complement and the carry bit C The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Setif an arithmetic overflow occurs reset otherwise OscOff CPUOff and GIE are not affected Two floating point mantissas 24 bits
357. iInterr pt Processing suce exerc ene RARO ERG RR 3 9 3 4 4 Interrupt Control Bits Special Function Registers SFRs 3 11 3 4 2 Interrupt Vector 4 3 20 315 2 Operating MOdeSs cs hie abre Paris UD PL LEES Ed 3 23 3 5 1 Low Power Mode 0 and 1 LPMO 1 3 27 3 5 2 Low Power Modes 2 and LPM2 and 3 28 3 5 8 Low Power Mode 4 4 3 28 3 6 Basic Hints for Low Power 3 29 ee E 4 1 4 1 c 4 2 42 Dataunthe Memory cus edes RR RR e RR 4 3 Contents vi 4 3 Internal ROM Organization 4 4 4 3 1 Processing of ROM 4 4 4 3 2 Computed Branches and Calls 4 5 4 4 RAM and Peripheral Organization 4 6 4 4 1 Random Access 4 6 4 4 2 Peripheral Modules Address Allocation 4 8 4 4 3 Peripheral Modules Special Function Registers
358. iated with all P2 pins P2 x may have the capability to be disabled with the CAPD register 7 0 CAPD 7 CAPD 6 CAPD 5 CAPD 4 CAPD 3 CAPD 2 CAPD 1 CAPD 0 CAPD 05Bh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 CAPD x 0 The input buffer for the pin enabled 1 The input buffer for the pin is disabled Comparator A in Applications 14 4 Comparator A in Applications The Comparator A can be used to Measure resistive elements Detect external voltage or current levels Measure external voltage and current sources Measure the voltage of a battery used in the system 14 4 1 Analog Signals at Digital Inputs Typically Comparator A inputs are multiplexed with digital I O pins When analog signals are applied to these digital CMOS gates parasitic current can flow from the positive terminal Vpp Vcc to the negative terminal Vss GND See Figure 14 4 This parasitic current occurs if the input voltage is around the transition level of the input gate Figure 14 4 Transfer Characteristic and Power Dissipation in a CMOS Inverter Buffer loc Vo VI v 0 Vcc Vss Figure 14 5 Transfer Characteristic and Power Dissipation in a CMOS Gate VI er Vo lcc lcc v Z VI V gt 0 Lo 1 Vss MSP430 devices with the Comparator A module have additional cir
359. ic S Reg D Reg Operation JEQ JZ Label Jump to label if zero bit is set JNE JNZ Label Jump to label if zero bit is reset JC Label Jump to label if carry bit is set JNC Label Jump to label if carry bit is reset JN Label Jump to label if negative bit is set JGE Label Jump to label if N XOR V 0 JL Label Jump to label if N XOR V 1 JMP Label Jump to label unconditionally 5 20 Instruction Set Overview 5 3 4 Short Form of Emulated Instructions The basic instruction set together with the register implementations of the program counter stack pointer status register and constant generator form the emulated instruction set these make up the popular instruction set The status bits are set according to the result of the execution of the basic instruction that replaces the emulated instruction Table 5 20 describes these instructions Table 5 20 Emulated Instructions Mnemonic Description Status Bits Emulation V N 2 ADC W dst Add carry to destination DADC B dst Add carry decimal to destination DADD B 0 dst DEC W dst Decrement destination i SUB 311 dst DEC B dst Decrement destination SUB B 1 dst DECD W dst Double decrement destination T SUB 2 dst dst H 1 J ADDC 0 dst DECD B Double decrement destination SUB B 2 dst INC W dst Increment destination ADD 311 dst INC B dst Increment destination 7 ADD B 1 dst INCD W dst Increment destination
360. ice Figure 11 17 Capture Compare Blocks CCISx1 5 0 0 0 74 o GND o Vcc 0 3 CCMx1 CCMxO 0 0 0 1 1 0 1 1 Overflow x CAPx Capture Mode Capture Compare Register CCRx Reset CCMx1 Disabled CLLDO m Reset Positive Edge CLLD1 Compare Latch TBCLx Negative Edge Both Edges 1 High Comparator x Zero Up Down EQUX 0 1 Set CCIFGx Timer B 11 15 Timer Modes 11 4 1 Capture Compare Block Capture Mode The capture mode is selected if the mode bit CAPx located in control word CCTLx is set The capture mode is used to fix time events It can be used for speed computations or time measurements The timer value is copied into the capture register CCRx with the selected edge positive negative or both of the input signal Captures may also be initiated by software as described in section 11 4 1 1 If a capture is performed The interrupt flag CCIFGx located in control word CCTLx is set An interrupt is requested if both interrupt enable bits CCIEx and GIE set The input signal to the capture compare block is selected using control bits CCISx1 and 5 0 as shown in Figure 11 18 The input signal be read at any time by the software by reading bit CCIx Figure 11 18 Capture Logic Input Signal CCISx1 CCISx0 CA
361. ictions on modifying this control register The control bits are reset or set WAIT by a PUC but key violation bit KEYV is reset by POR FCTL3 012Ch FCTL3 read 4 096h rO ro rw 0 rw 1 r 1 rw O rw 0 r w O FCTL3 write 0A5h gt BUSY 0128h bitO The bit BUSY shows if an access to the flash memory is possible BUSY 0 or if an access violation can occur The BUSY bit is read only but a write operation is allowed The BUSY bit should be tested before each write and erase cycle The flash timing generator hardware immediately sets the BUSY bit after the start of a write operation a block write operation a segment erase or a mass erase Once the timing generator has completed its function the BUSY bit is reset by hardware The program and erase timing are shown in Figures 7 8 and C 9 0 Flash memory is not busy Read write erase and mass erase are possible without any violation of the internal flash timing The BUSY bit is reset by POR and by the flash timing generator 1 Flash memory is busy Remains in busy state if block write function is in wait mode The conditions for access to the flash memory during BUSY 1 are described in paragraph C 2 6 KEYV 012Ch bit1 Key Violated 0 Key 0 5 high byte was not violated 1 Key 0A5h high byte was violated Violation occurs when a write access to register FCTL1 FCTL2 or FCTL3 is executed and the high byte is not equal to OA5h If the security
362. if zero bit is reset f SS Ep See Note Conditional and Unconditional Jumps Conditional and unconditional jumps do not affect the status bits A jump that is taken alters the PC with the offset PCnew POold 2 2 offset A jump that is not taken continues the program with the ascending instruction B 1 3 Emulated Instructions B 6 The following instructions can be emulated with the reduced instruction set without additional code words The assembler accepts the emulated instruction mnemonic and inserts the applicable core instruction op code Instruction Set Overview The following list describes the emulated instruction short form Mnemonic Description Status Bits Emulation VNZC Arithmetical instructions ADC W dst Add carry to destination ye qu ADDC 0 dst ADC B dst Add carry to destination ADDC B 0 dst DADC W dst Add carry decimal to destination DADD 0 dst DADC B dst Add carry decimal to destination DADD B 0 dst DEC W dst Decrement destination 17 e SUB 1 dst DEC B dst Decrement destination po Fy bee SUB B 1 dst DECD W dst Double decrement destination 4 4 2 SUB 2 dst DECD B dst Double decrement destination dE UR SUB B 2 dst INC W dst Increment destination E MENS ADD 1 dst INC B dst Increment destination ADD B 1 dst INCD W dst Increment destination R R ADD 2 dst INCD B dst Inc
363. ill end in an access violation with ACCVIFG 1 In an active segment write mode the control register can be written if wait mode is active WAIT 1 In an active block write mode and while WAIT 0 writing to control register FCTL1 will also end an access violation with ACCVIFG 1 Read access is possible at any time without restrictions Any write to control register FCTL1 during erase mass erase or write programming will end in an access violation with ACCVIFG 1 In an active segment write mode the control register can be written if wait mode is active WAIT 1 In an active block write mode and while WAIT 0 writing to control register FCTL1 will also end in an access violation with ACCVIFG 1 Flash Memory C 13 Flash Memory Control Registers Read access is possible at any time without restrictions The control bits of control register FCTL1 are 096h w 0 rw 0 10 ro ro rw 0 rw 0 10 FCTL1 read 4 FCTL1 write Erase 0128h bit1 MEras 0128h bit2 WRT 0128h bit6 BLKWRT 0128h bit7 0 5 gt Erase a segment 0 No segment erase is started 1 Erase of one segment is enabled The segment n to be erased is defined by a dummy write into any address within the segment The Erase bit is automatically reset when the erase operation is completed Note Instruction fetch access during erase is allowed Any other access to the flash memory during erase results in setting the ACCVIFG bit and
364. instruction following the jump is executed JC jump if carry higher or same is used for the comparison of unsigned numbers 0 to 65536 Status bits are not affected The 1 signal is used to define or control the program flow BIT 01h amp P1IN State of signal gt Carry JC PROGA If carry 1 then execute program routine A Carry 0 execute program here R5 is compared to 15 If the content is higher or the same branch to LABEL CMP 15 R5 JHS LABEL Jump is taken if R5 gt 15 zii Continue here if R5 15 Instruction Set Description B 33 Instruction Set Overview JEQ JZ Syntax Operation Description Status Bits Example Example Example B 34 Jump if equal jump if zero JEQ label JZ label 2 1 PC 2x offset PC If Z 0 execute following instruction The status register zero bit Z is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is not set the instruction following the jump is executed Status bits are not affected Jump to address TONI if R7 contains zero TST R7 Test R7 JZ TONI if zero JUMP Jump to address LEO if R6 is equal to the table contents CMP R6 Table R5 Compare content of R6 with content of MEM table address content of R5 JEQ LEO Jump if both data are equal de No data are not equal continue here Branch to LABEL if R5 is O TST R5 JZ LABEL Sy
365. internal reference and achieve accurate results without an absolute Vcc Vcc needs to be stable but not necessarily known The accuracy of ratiometric measurements is determined by the accuracy of the known resistor or capacitor value Absolute measurement principles require a stable Vcc to ensure that the voltage reference generated produces accurate reference voltage levels Comparator A Description 14 2 6 Comparator A Interrupt Circuitry One interrupt and one interrupt vector are associated with the Comparator A see Figure 14 3 The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output The interrupt edge select bit CAIES determines which edge of the output signal sets the CAIFG flag The interrupt enable bit CAIE along with the general interrupt enable bit GIE control if the CAIFG bit generates a CPU interrupt If both the CAIE and the GIE bits are set then the CAIFG flag will generate a CPU interrupt request The CAIFG flag is automatically reset when the CPU interrupt request is serviced The CAIFG CAIES and CAIE bits are all located in the CACTL1 register Figure 14 3 Comparator A Interrupt System CAIE POR IRACC Interrupt Request Accepted Comparaltor 14 5 Comparator A Control Registers 14 3 Comparator A Control Registers The Comparator A module is configured with three module registers as shown in Table 14 1 The module registers are mapped into the low
366. interrupt vector word is reset TIM HND DD ETI P CQ C C C X Do tu tu UU CU UU amp TBIV PC TIMMOD1 TIMMOD2 TIMMOD3 TIMMOD4 TIMMOD5 TIMMOD6 Module 7 Timer Overflow Handler expanded into the RAM location TIMEXT TIMOVH INC RETI TIMMOD2 ADD RETI TIMMOD1 ADD RETI The Module 3 interrupt is TIMMOD3 ADD JMP TIMEXT NN amp CCR2 amp CCR1 5 Interrupt latency 6 Add offset to Jump table 3 Vector 0 No interrupt 5 Vector 2 Module 1 2 Vector 4 Module 2 2 Vector 6 Module 3 2 Vector 8 Module 4 2 Vector 10 Module 5 2 Vector 12 Module 6 2 the Timer Register is MSBs Vector 14 pending 5 cycles hav 9 cycles may be saved if another interrupt is pending TIMOV Flag Handle Timer Overflow 4 5 Vector 4 Module 2 Add time difference 5 Task starts here Back to main program 5 Vector 2 Module 1 Add time difference 5 Task starts here Back to main program 5 handler shows a way to look if any other to be spent but Vector 6 Module 3 Add time difference 5 amp TIM HND Task starts here Look for pending interrupts 2 Timer B Registers 11 6 4 4 Timer Interrupt Vector Register Software Example Timer B3 The following software example describes the use of vector word TBIV of Timer and the handling overhead The numbers at the right margin
367. interrupted program flow Restoration is performed by replacing the present PC contents with the TOS memory contents The stack pointer SP is incremented N restored from system stack Z restored from system stack C restored from system stack V restored from system stack OscOff CPUOff and GIE are restored from system stack Figure B 5 illustrates the main program interrupt Figure B 5 Main Program Interrupt B 46 PC 6 4 Interrupt Request 2 2 Interrupt Accepted v gt PC 2 PC 2 is Stored PC PCi Onto Stack PC 4 PCi 2 PC 6 PCi 4 PC 8 e v PCi n 4 PCi 2 PCi n RETI pal 225 RLA W RLA B Syntax Operation Emulation Description Instruction Set Overview Rotate left arithmetically Rotate left arithmetically RLA dst or RLA W dst RLA B dst MSB lt MSB 1 LSB 1 LSB 0 ADD dst dst ADD B dst dst The destination operand is shifted left one position as shown in Figure 6 The MSB is shifted into the carry bit C and the LSB is filled with 0 The RLA instruction acts as a signed multiplication by 2 An overflow occurs if dst gt 04000h and dst lt 0C000h before operation is performed the result has changed sign Figure B 6 Destination Operand Arithmetic Shift Left Status Bits Mode Bits Example Example Word 15 0
368. iod only if channel a10 is selected Figure 16 21 ADC10 Current Consumption Without Internal Reference lAVG IREF lADC10 X tS amp C tPeriod tPeriod gt The average current consumed when converting any channel other than a10 while the internal reference is off is lava apcio X tsac tPeriod The average current consumed when the internal reference is off but the selected channel is a10 internal temperature sensor is lAVG Inet 10 X tsac tPeriod ADC10 eer Controlling the Current Consumption of the ADC10 Module 16 9 2 2 Internal Reference is on But Not Routed Externally When the internal reference is not routed externally REFON 1 REF Out 0 and is used for Vp the reference buffer is automatically enabled during the sample and conversion period and disabled otherwise to save current consumption If the reference is on and not routed externally but is not used for Vp for a conversion the reference buffer is not enabled during the sample and conversion period Figure 16 22 ADC10 Current Consumption With Internal Reference On but not Routed Externally E ZZ et 222222222 22 2 2 2 2 2 2 TT tsac gt s VREF 4 tPeriod ref 0 2 4 OV 6 7 If the reference is on not used for and not routed externally the average current consumed is lAVG IRet lapcto X ts amp c tPeriod If the reference is on used
369. ion The use of as many OPLA terms as needed no restriction on n terms OTP version automatically includes OPLA programmability Computed table accessibility for example for a bar graph display Coc O Table supported program flows Internal ROM Organization 4 3 2 Computed Branches and Calls Computed branches and subroutine calls are possible using standard instructions The call and branch instructions use the same addressing modes as the other instructions The addressing modes allow indirect indirect addressing that is ideally suited for computed branches and calls This programming technique permits a program structure that is different from conventional 8 and 16 bit microcontrollers Most of the routines can be handled easily by using software status handling instead of flag type program flow control The computed branch and subroutine calls are valid throughout the entire ROM space Memory 4 5 RAM and Peripheral Organization 4 4 RAM and Peripheral Organization 4 4 1 The entire RAM can be accessed with byte or word instructions using the appropriate instruction suffix The peripheral modules however are located in two different address spaces and must be accessed with the appropriate instruction length The SFRs byte oriented and mapped into the address space from Oh up to OFh Peripheral modules that are byte oriented are mapped into the address space from 010h up to OFFh Peripher
370. ion increases linearly with the clock frequency It should be kept to the minimum required to meet application conditions Fast communication speed is needed for calibration and testing in manufacturing processes alarm responses in critical applications and response time to human requests for information 5 430 USART can generate baud rates up to one third of the clock frequency An additional modulation of the baud rate timing adjusts timing for individual bits within a frame The timing is adjusted from bit to bit to meet timing requirements even when a noninteger division is needed Baud rates up to 4800 baud can be generated from a 32 768 Hz crystal with maximum errors of 11 percent Standard UARTs even with the worst maximum error 714 6 percent can obtain maximum baud rates of 75 baud USART Peripheral Interface UART Mode 12 25 Baud Rate Considerations 12 6 3 Support of Multiprocessor Modes for Reduced Use of MSP430 Resources Communication systems can use multiprocessor modes with multiple character idle line or address bit protocols The first character can be a target address a message identifier or can have another definition This character is interpreted by the software and if it is of any significance to the application the succeeding characters are collected and further activities are defined An insignificant first character would stop activity for the processing device This application is supported by the w
371. ion memory registers For example if a sequence is three conversions long and the CStartAdd bits point to conversion memory register 4 then when the sequence is started the first conversion result is stored in ADC12MEM4 the second result is stored in ADC12MEMS5S and the third result is stored in ADC12MEM6 When performing sequences of conversions the channels and references for each conversion are individually configurable via the conversion memory control register associated with the each conversion memory register used in the sequence For example if a sequence of conversions uses ADC12MEM3 ADC12MEM6 then the channel and reference s for each conversion are individually configurable with ADC12MCTL3 ADC12MCTL6 The end of a sequence is marked by the end of sequence bit EOS in the last conversion memory control register used in the sequence Each conversion memory control register contains an EOS bit All EOS bits of the conversion memory control registers used in a sequence must be reset except for the last one in the sequence For example if a sequence starts with ADC12MEM7 and ends with ADC12MEM12 then the EOS bit of registers ADC12MCTL7 ADC12MCTL11 must be reset and the EOS bit of ADC12MCTL12 must be set Conversions stop when the end of a sequence is reached When software is using the ADC12SC bit to initiate a sequence successive sequences can be initiated by simply setting the ADC12SC bit the ENC bit can remain set o
372. irection from zero Setting the CLR bit in TACTL register Setting the CLR bit in the TACTL register clears the timer value and input clock divider value The timer increments upward from zero with the next clock cycle as long as stop mode is not selected with the bits TAR is loaded with 0 When the counter register is loaded with zero with a software instruction the timer increments upward from zero with the next clock cycle as long as stop mode is not selected with the MCx bits 10 3 Timer Modes Timer Modes 10 3 1 Timer Stop Mode Stopping and starting the timer is done simply by changing the mode control bits MCx The value of the timer is not affected When the timer is stopped from up down mode and then restarted in up down mode the timer counts in the same direction as it was counting before it was stopped For example if the timeris in up down mode and counting in the down direction when the bits are reset when they are set back to the up down direction the timer starts counting in the down direction from its previous value If this is not desired in an application the CLR bit in the TACTL register can be used to clear this direction memory feature 10 3 2 Timer Up Mode The up mode is used if the timer period must be different from the 65 536 16 bit clock cycles of the continuous mode period The capture compare register CCRO data define the timer period The counter counts up to the conte
373. irst don t care word to UxTXBUF is necessary to shift the TXWAKE bit to WUT and generate an idle line condition Figure 12 10 USART Transmitter Idle Generation Example Bi One Tope M 11 Bit Idle Period Mark XXXX SP ST XXXXXXX Space Example Two Stop Bits 11 Bit Idle Period Mark XXXX SP SP XXXXXXX Space SP Stop Bit ST Start Bit 12 3 5 Address Bit Multiprocessor Format In the address bit multiprocessor format shown in Figure 12 11 characters contain an extra bit used as an address indicator The first character in a block of data carries an address bit which indicates that the character is an address The RXWake bit is set when a received character is an address character It is transferred into the receive buffer receive conditions are true Usually if the USART URXWIE bit is set data characters are assembled by the receiver but are not transferred to the receiver buffer UXRXBUF nor are interrupts generated When a character that has an address bit set is received the receiver is temporarily activated to transfer the character to UXRXBUF and to set the URXIFG Error status flags are set as applicable The application software processes the succeeding operation to optimize resource handling or reduce current consumption The application software can validate the received address If there is a match the processor can read the remainder of the data block
374. is used for master and slave mode STC 0 The four pin mode of SPI is selected The STE signal is used by the master to avoid bus conflicts or is used in slave mode to control transmit and receive enable STC 1 The three pin SPI mode is selected STE is not used in master or slave mode Unused Unused Source select 0 and 1 The source select bits define which clock source is used for baud rate generation only when master mode is selected SSEL1 SSELO 0 External clock UCLK selected 1 Auxiliary clock ACLK selected 2 3 SMCLK In master mode MM 1 an external clock at UCLK cannot be selected since the master supplies the UCLK signal for any slave In slave mode bits SSEL1 and SSELO are not relevant The external clock UCLK is always used Clock polarity CKPL and clock phase CKPH The CKPL bit controls the polarity of the SPICLK signal CKPL 0 The inactive level is low data is output with the rising edge of UCLK input data is latched with the falling edge of UCLK CKPL 1 The inactive level is high data is output with the falling edge of UCLK input data is latched with the rising edge of SPICLK The CKPH bit controls the polarity of the SPICLK signal as shown in Figure 13 17 CKPH 0 Normal UCLK clocking scheme CKPH 1 UCLK is delayed by one half cycle USART Peripheral Interface SPI Mode 13 17 Control and Status Registers Figure 13 17 USART Clock Phase and Polarity
375. isters Bit 15 Unused Timer_B 11 31 Timer B Registers 7 1 Note Changing Timer Control Bits If the timer operation is modified by the control bits in the TBCTL register the timer should be halted during this modification Critical modifications are the input select bits input divider bits and the timer clear bit Asynchronous clocks input clock and system clock can result in race conditions where the timer reacts unpredictably The recommended instruction flow is 1 Modify the control register and stop the timer with one instruction 2 Start the timer operation For example MOV 0286h amp TBCTL ACLK 8 timer stopped timer cleared BIS 410h amp TBCTL _ Start timer with up mode 11 6 2 Timer B Register TBR The TBR register is the value of the timer Figure 11 28 TBR Register 15 0 TER Timer Val 190h imer Value rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw O rw 0 rw 0 rw 0 1 Note Modifying Timer B Register TBR When ACLK SMCLK or the external clock TBCLK or INCLK is selected for the timer clock any write to timer register TBR should occur while the timer is not operating otherwise the results may be unpredictable In this case the timer clock is asynchronous to the CPU clock MCLK and critical race conditions exist 11 6 3 Capture Compare Control Register CCTLx Each capture compare block has its
376. isters noise eei Lese ERIGI 10 24 Mode Motel 10 25 Input Clock Divider Control Bits 10 26 Clock Source Selection 10 26 Capture Compare Control Register Output 10 28 Capture Compare Control Register Capture Mode 10 29 Vector Register TAIV Description 10 31 Timer Modes eer T E 11 6 Compare Latch Operating Modes 11 21 State of OUTx at Next Rising Edge of Timer Clock 11 26 Timer B Reglsters v ke ene Cep bes aed aed ERE be 11 29 Mode GontroL ED TEMERE ERES 11 30 Input Clock Divider Control Bits 11 30 Glock Source Selection 11 30 Capture Compare Control Register Output Mode 11 34 Capture Compare Control Register Capture Mode 11 35 Vector Register TBIV 11 37 USART Interrupt Control and Enable Mode 12 11 USARTO Control and Status Registers
377. isters to be updated simultaneously This is useful for example when there is a need to change the period or duty cycle of multiple PWM signals simultaneously It is useful to note that in Timer B s default condition the compare data is immediately transferred from each CCRx register to the corresponding compare latch Therefore in the default condition the compare mode of Timer B functions identically to the compare mode of Timer A Timer B 11 3 Introduction Figure 11 1 Timer B Block Diagram 16 Bit Timer TPSSEL1 TPSSELO Timer Clock Data TBCLK o o 2 a 15 0 1 mes 0 Input 16 Bit Timer Mode ivi CLK1 RC E o 28 H E90 101 IDO INCLK o o gt Carry Zero POR CLR y MC1 Mco Set TBIFG HT EM RUD NR Lin e 4 ICE ye MERE NU MU ENSEM T NECI 4 1 Capture Compare Register CCRO 501 00 15 OM02 01 OMOO 0 ccioa 1 Register CCRO CCIOB 9 Capture 0 ut GND Mode SUE Output Unit 0 Voc 9 Compare Latch Comparator 0 EQUO EQUO ncc tl a Vl E E 4 a ah a me ee Pe te T ae On yt q Capture Compare Register CCR1
378. ith three or four external pins Figure 12 1 shows the USART peripheral interface module Figure 12 1 Block Diagram of USART Receive Buffer R eceive Status UORXBUF or UtRXBUF SYNC RXE Listen MM SYNC Jr en SOMI Receive Shift Register o eto 1 0 SYNC SSEL1 SSELO Dio prese 910 ine UCLKI X STE ACLK o ius aH 3 SMCLK o o UTXD e gt 2 15 SIMO lt gt 0 TXWake CKPH SYNC CKPL UCLKI UCLKS 12 2 USART Peripheral Interface UART Mode 12 2 USART Peripheral Interface UART Mode The USART peripheral interface is a serial channel that shifts a serial bit stream of 7 or 8 bits in and out of the MSP430 The UART mode is chosen when control bit SYNC in the USART control register UOCTL for USARTO or U1CTL for USART1 is reset 12 2 1 UART Serial Asynchronous Communication Features Some of the UART features include Asynchronous formats that include idle line address bit communication protocols Two shift registers that shift a serial data stream into URXD and out of UTXD Data that is transmitted received with the LSB first Programmable transmit and receive bit rates Status flags Figure 12 2 shows the USART in UART mode Figure 12 2 Block Diagram of USART UART Mode 58653 UORXBUF or U1TRXBUF RXE sm qaae 0 lt 1 URXD Receive Shift Register Receive Status SSE
379. ive Negative Positive otherwise reset SUB B SUBC B CMP B Set when Positive Negative Negative Negative Positive Positive otherwise reset SCG1 SCGO These bits control four activity states of the system clock generator and therefore influence the operation of the processor system OscOFF If set the crystal oscillator enters off mode all activities cease however the RAM contents the port and the registers are maintained Wake up is possible only through enabled external interrupts when the GIE bit is set and from the NMI CPU Off If set the CPU enters off mode program execution stops However the RAM the port registers and especially the enabled peripherals for example Timer UART etc stay active Wake up is possible through all enabled interrupts GIE If set all enabled maskable interrupts are handled If reset all maskable interrupts are disabled The bit is cleared by interrupts and restored by the RETI instruction as well as by other appropriate instructions N Set if the result of an operation is negative Word operation Negative bit is set to the value of bit 15 of the result Byte operation Negative bit is set to the value of bit 7 of the result 2 Set if the result of byte or word operation is 0 cleared if the result is not 0 C Setifthe result of an operation produced a carry cleared if no carry occurred Some instructions modify the carry bit using the inverted zero bits 5 4
380. ive buffer Only the first stop bitis checked when more than one is used The missing stop bit indicates that the start bit synchronization is lost and the character is incorrectly framed FE is reset by a SWRST a System reset or by reading the UXRXBUF n C Note Receive Status Control Bits The receive status control bits FE PE OE BRK and RXWake are set by the hardware according to the conditions of the characters received Once the bits are set they remain set until the software resets them directly or there is a reading of the receive buffer False character interpretation or missing interrupt capability can result in uncleared error bits S O47w9OrxcC OON Control and Status Registers 12 5 4 Baud Rate Select and Modulation Control Registers The baud rate generator uses the content of the baud rate select registers UxBRO and UxBR1 shown in Figure 12 19 with the modulation control register to generate the serial data stream bit timing Figure 12 19 USART Baud Rate Select Register 7 0 UOBRO 074h rw rw rw rw rw rw rw rw 7 0 UOBR1 075h wines rw rw rw rw rw rw rw rw BRCLK Baud rate 7 3 with UxBR UxBR1 UxBRO UxBR 52 mi The baud rate control register range is 3 lt UxBR lt OFFFFh Note Unpredictable receive and transmission occur if UxBR 3 The modulation control register
381. l communication peripheral supports two serial modes with one hardware configuration These modes shift a serial bit stream in and out of the MSP430 at a programmed rate or at a rate defined by an external clock The first mode is the universal asynchronous receive transmit UART communication protocol the second is the serial peripheral interface SPI protocol discussed in Chapter 13 Bit SYNC in control register UCTL UOCTL for USARTO or U1CTL for USART1 selects the required mode SYNC 0 UART asynchronous mode selected SYNC 1 SPI synchronous mode selected The 12xx and 13x have one USART named USARTO The 14x has two USARTs implemented USARTO and USART1 This chapter addresses the UART mode Topic Page 12 1 USART Peripheral Interface 12 2 12 2 USART Peripheral Interface UART Mode 12 3 12 3 Asynchronous Operation 12 4 12 4 Interrupt and Enable Functions 12 11 12 5 Control and Status Registers 12 15 12 6 Utilizing Features of Low Power Modes 12 23 12 7 Baud Rate Considerations 12 26 12 1 USART Peripheral Interface 12 1 USART Peripheral Interface The USART peripheral interface connects to the CPU as a byte peripheral module It connects the MSP430 to the external system environment w
382. l purpose 16 bit Timer B Timer B implementation differs among MSP430 devices Always check the device s data sheet to determine the connections and the number of identical capture compare registers Also the data sheets use additional nomenclature to indicate the number of capture compare registers implemented for a specific device For example if Timer is discussed in a data sheet then that device s implementation of Timer B contains 3 capture compare registers In its default condition Timer B operates identically to Timer A except the SCCI bit is not implemented on Timer gt x aE Note Use of the Word Count Throughout this chapter the word countis used in the text As used in these instances it refers to the literal act of counting It means that the counter must be in the process of counting for the action to take place If a particular value is directly written to the counter then the associated action will nottake place For example the CCRO interrupt flag is set when the timer counts up tothe value in CCRO compare latch TBCLO The counter must count from TBCLO 1 to TBCLO If the TBCLO value were simply written directly to the timer with software the interrupt flag would not be set even though the values in the timer and TBCLO would be the same introduction ceea aa gere ee eee 11 2 11 2 Timer B Operation 1 e E 11 5 11 3 TimerrModes e E 11 8 11 4
383. ld 2 Register TBCLOnew 3 555655552 11 9 Timer Modes Figure 11 8 New Period Old Period Timer Timer Register TBCLOold 5 Register TBCLOnew 2 TBCLOold 5 TBCLOnew 2 OI 0120 2 3 45012 3 401 2 5 TBCLO Loaded With 2 During Low Clock Phase 1 TBCLO Timer Clock Timer Clock 4 Timer Timer Xn X nu X_Oornt 1 TBCLO TBCLold TBCLnew TBCLO TBCLold TBCLnew Load New TBCLO Load New TBCLO During High Phase of Clock During Low Phase of Clock T Up mode 0 up down mode n 1 Up mode 0 up down mode n 11 3 3 Timer Continuous Mode The continuous mode is used if the timer period of TBR max clock cycles is used for the application A typical application of the continuous mode is to generate multiple independent timings In continuous mode the capture compare block 0 works in the same way as the other capture compare blocks The capture compare blocks and different output modes of each output unit are useful to capture timer data based on external events or to generate various different types of output signals Examples of the different output modes used with timer continuous mode
384. ld be start the capture then start the timer 11 4 1 1 Capture Compare Block Capture Mode Capture Initiated by Software 11 18 In addition to internal and external signals captures can be initiated by software This is useful for various purposes such as To measure time used by software routines measure time between hardware events To measure the system frequency Two bits CCISx1 and 5 0 and the capture mode selected by bits CCMx1 and are used by the software to initiate the capture The simplest realization is when the capture mode is selected to capture on both edges of and bit CCISx1 is set Software then toggles bit CCISxO to switch the capture signal between Vcc and GND initiating a capture each time the input is toggled as shown in Figure 11 21 Timer Modes Figure 11 21 Software Capture Example i itm uc C E Rao c EIL Ro ipte mt CCISx0 CCIx Capture CCISx1 CCISx0 Bos I Capture GND o Mode 3 Vee o o 90 CClx CCMx1 Both Edges Selected 1 1 The following is a software example of a capture performed by software The data of capture compare register CCRx are taken by the software It is assumed that CCMx1 0 and CCISx1 bits are set Bit 50 selects the CCIx signal to be high or low
385. location TOM Example The three MSBs of RAM byte TOM are set BIS B 0E0h TOM set the 3 MSBs in RAM location TOM BIT W BIT B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Overview Test bits in destination Test bits in destination BIT src dst or BIT W src dst src AND dst The source and destination operands are logically ANDed The result affects only the status bits The source and destination operands are not affected N Set if MSB of result is set reset otherwise Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Reset OscOff CPUOff and GIE are not affected If bit 9 of R8 is set a branch is taken to label TOM BIT 0200h R8 bit 9 of R8 set JNZ TOM Yes branch to TOM No proceed If bit 3 of R8 is set a branch is taken to label TOM BIT B 8 R8 JC TOM A serial communication receive bit RCV is tested Because the carry bit is equal to the state of the tested bit while using the BIT instruction to test a single bit the carry bit is used by the subsequent instruction the read information is shifted into register RECBUF Serial communication with LSB is shifted first XXXX XXXX XXXX BIT B RCV RCCTL Bit info into carry RRC RECBUF Carry gt MSB of RECBUF CXXX XXXX ds repeat previous two instructions m 8 times CCCC MSB LSB S
386. location being erased no access violation indicates this situation After erase no executable code is available and an unpredictable situation occurs 4 Any software located in a flash memory module can not use the BLKWRT mode to program the same flash memory module Using the byte or word programming mode allows programming data in the flash memory module holding the software code currently executing 5 The access violation sets the LOCK bit to 1 Setting the LOCK bit allows completion of the active block write operation in the normal manner Flash Memory Control Registers Thesupply voltage should be within the devices electrical conditions and can only vary slightly as specified in the applicable data sheet The control bit BUSY indicates that the write or block write cycle is active It is set by the instruction that writes data to the flash memory module and starts the timing generator It remains set until the write cycle is completed and the programming voltage is removed In the write mode the BUSY bit indicates if the flash memory is ready for another write operation In block write mode the WAIT bit indicates if the flash memory is ready for another write operation and the BUSY bit indicates the block write operation is completed In case of emergency the emergency exit bit EMEX is set and stops the write cycle immediately The programming voltage is switched off One situation where the write cycle should be stopped by softwar
387. lock XT20ff MCLKGEN ey lt XT2 DCOCLK xr20UT Oscillator EIL mi m Ced ants Ci umm ea J SCGO DCO MOD SELS DIVS SCG1 Digital Controlled Oscillator 1 2 4 18 Off SMCLK Modulator MOD Sub System If the external resistor function is shared on a digital terminal the DCOR control bit defines if the digital port of the DCO generator is connected to that terminal Pn x Note The XT2 oscillator is implemented in MSP430F13x and MSP430F 14x devices The LFXT1 signal is used instead of XT2CLK signal MSP430x11xx and MSP430x12xx devices without XT2 oscillator 7 2 The Basic Clock Module includes two or three clock sources LFXT1CLK low frequency high frequency clock source One oscillator that can be used with low frequency watch crystals standard crystals resonators or external clock sources See the device data sheet for the exact operating frequency range XT2CLK high frequency clock source This optional high frequency oscillator can also use standard crystals resonators or external clock sources in the 450 kHz to 8 MHz range See the device data sheet for the exact operating frequency range and availability of this optional oscillator DCOCLK clock source One digitally controlled oscillator DCO with RC type characteristics Three clock signals are available from the Basic Clock Module
388. low power mode including LPM4 MCLK automatically becomes active inside of an interrupt service routine An NMI interrupt routine written by the user which handles the oscillator fault has some important steps that should be used for proper handling of the fault situation First if the NMI interrupt routine detects the oscillator fault and selects the DCO as clock source for the system clock MCLK Second the user programs a proper algorithm to detect if the XT oscillator is working again and reselects an XT oscillator for the system clock MCLK if desired Figure 7 9 NMI OSCFault Interrupt Handler Start of NMI Interrupt Handler Reset by HW OFIE NMIE ACCIE Yes Yes Select DCO For MCLK Reset ACCVIFG SELM 1 0 User s Software Oscillator Fault User s Software Flash Access Violation Handler Handler Reselect Failed XT Oscillator Optional LFXT1 and XT2 Oscillators No Yes Reset NMIIFG User s Software External NMI Handler y y y Set NMIE OFIE Example1 ACCVIE Within One BIS B NMIIE OGIE ACCVIFG amp IEl Instruction Example2 RETI End of NMI Int Handler Note Example for MSP430F1xx device BIS B Mask 6 Mask Enables Only Interrupt Sources That are Needed If an oscillator error forces the DCO on and uses the DCOCLK for MCLK the clock source for MCLK should be selected to DCOCLK with SELM 1 0 If the oscillator error disappears
389. ly and Accumulate MOV 01234h amp MACS Load first operand into appropriate register MOV 05678h amp OP2 Load 2nd operand Result is now available 8x8 Signed Multiply and Accumulate OV B 012h amp MPYS Load first operand into appropriate register SXT amp MPYS Sign extend first operand OV B 034h R5 Temporary location for 2nd operand SXT amp 2 Sign extend 2nd operand OV R5 amp OP2 Load signed extended 2nd operand 16 bit value Result is now available Hardware Multiplier 6 5 Hardware Multiplier Registers 6 3 Hardware Multiplier Registers Hardware multiplier registers are word structured but can be accessed using word or byte processing instructions Table 6 2 describes the hardware multiplier registers Table 6 2 Hardware Multiplier Registers Register Short Form Register Type Address Initial State Multiply Unsigned Operand1 MPY Read write 0130h Unchanged Multiply Signed 1 MPYS Read write 0132h Unchanged Multiply Accumulate Operand1 MAC Read write 0134h Unchanged Multiply Signed Accumulate Operand1 MACS Read write 0136h Unchanged Second Operand OP2 Read write 0138h Unchanged Result Low Word ResLo Read write 013Ah Undefined Result High Word ResHi Read write 013Ch Undefined Sum Extend SumExt Read 01 Undefined Two registers are implemented for both operands OP1 and OP2 as shown in Figure 6 3 Operand 1 uses four different addr
390. ly set to n is decremented by one This operation repeats with each loading of ADC10MEM until the transfer counter becomes zero After the last transfer of ADC10MEM has completed the ADC10IFG is set An interrupt is executed if the general interrupt enable bit and the ADC10 interrupt enable bit ADC10IE are both set No software intervention is required during the block transfer The function of the one block mode is shown in Figure 16 17 as a state diagram In one block mode when the control bit ADC10CT continuous mode is set indicating continuous mode the DTC circuitry does not pause or stop after the block is finished The address pointer and the transfer counter are reset and begin transfers again with the next ADC10MEM buffer load In this configuration the application must have read all values in the block before the DTC begins filling the block again Otherwise some conversion results will be overwritten If bit ADC10CT is reset the DTC transfers cease after the block has been transferred Data Transfer Control High Speed Conversion Support Figure 16 17 State Diagram for Data Transfer Control in One Block Transfer Mode n 0 ADC10DTC1 nz Wait for write to ADC10SA Initialize Prepare Start Address ADC10SA DTC 5 ll Write to ADC10SA n is latched in counter Write to ADC10SA or n 0 Wait until ADC10MEM is written Write to ADC10MEM completed Write to ADC10SA
391. m r 0 ADC10CTLO 01BOh t Only modifiable when ENC 0 Bit 4 7 6 5 4 3 2 1 0 ADC1OAE ADC10AE 7 ADC10AE 6 ADC10AE 5 ADC10AE 4 ADC10AE 3 ADC10AE 2 ADC10AE 1 ADC10AE 0 04Ah rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC10DTC1 049h rw 0 ADC10DTCO rud jc cus Reserved ADC1 on ADC1 d ADC1 a ADC1 ae 080h rw 0 rw 0 r 0 rw 0 Bit 14 9 0 ADC10MEMT Not Not Not Not Not Not Conversion Result 01B4h Used Used Used Used Used Used All conversion result bits of type rw Bit 15 6 0 ADC10MEMt A Not Not Not Not Not Not Conversion Result 01B4h All conversion result bits of type rw Used Used Used Used Used ro ro ro ro T ADC1ODF 1 Bit 15 1 0 ADC10SA lt Data Transfer Start Address gt 0 01BCh rw 0200h ro Peripheral File Map 11 Watchdog Timer Word Access A 11 Watchdog Timer Word Access Bit 4 15 8 Watchdog Timer Read as 069h Control register WDTCTL Written as 05Ah 120h Bit 4 7 6 5 4 3 2 1 0 Watchdog Timer 1 HOLD NMIES NMI TMSEL CNTCL SSEL IS1 150 A 12 Flash Control Registers Word Access Bit 15 14 13 12 11 10 9 8 FCTL3 Read as 096h 012Ch Written as 0A5h FCTL2 Read as 096h 012Ah Written as 0A5h FCTL1 Read as 096h 0128H Written as 0A5h Bit 7 6 5 4 3 2 1 0
392. may be changed without first stopping the conversions When this is done the new mode takes effect after the current sequence ADC12 4637 Conversion Modes 15 18 completes except when the new mode is repeat single channel In this case the sequence does not complete and the new mode takes effect immediately see also the Switching Between Conversion Modes section There are four ways to stop repeat sequence of channels conversions 1 Select sequence of channels mode CONSEQ 1 instead of repeated sequence of channels mode CONSEQ 3 When this is done the current sequence of conversions is completed normally and no further conversions take place The conversion results are loaded into registers ADC12MEMXx and the corresponding interrupt flags ADC12IFG x are set 2 Reset ENC bit ADC12CTLO 1 This stops the conversions after the current sequence is completed The conversion results of all conversions in the sequence are stored in their appropriate ADC12MEMXx register and the associated interrupt flags ADC12IFG x are set 3 Select repeat single channel mode CONSEQ 2 instead of the repeat sequence of channel mode and then select single channel mode The current conversion is completed normally The current conversion result is loaded into register ADC12MEMx and the associated interrupt flags ADC12IFG x are set The data for x is somewhere between CStartAdd and the last register of the sequence 4 Select single channel m
393. me when the ADC10 is turned on with the ADC100N bit the turnon time noted in the data sheet t 4pc100N must be observed before a conversion is started Otherwise the results will be false Reference voltage settling Time When the built in reference is turned on with the REFON bit the settling timing noted in the data sheet must be observed before a conversion is started Otherwise the results will be false until the reference settles Once all internal and external references have settled no additional settling time is required when selecting or changing the conversion range for each channel Settling time of external signals external signals must be settled before performing the first conversion after turning on the ADC10 Otherwise the conversion results will be false 16 5 Conversion Clock and Conversion Speed The conversion clock for the ADC10 ADC10CLK shown in Figure 16 8 be selected from several sources and can be divided by any factor from 1 8 The ADC10CLK is used for the A D conversion and to generate the sampling period if pulse sampling mode is selected SHP 1 Possible clock sources are the internal oscillator ADC10OSC ACLK MCLK and SMCLK The internal oscillator generates the ADC10OSC signal and is in the 5 2 range see device data sheet for specifications The internal oscillator frequency will vary with individual devices supply voltage and temperature A stable clock source should be us
394. me between hardware events To measure the system frequency Two bits CCISx1 and 5 0 and the capture mode selected by bits CCMx1 and are used by the software to initiate the capture The simplest realization is when the capture mode is selected to capture on both edges of and bit CCISx1 is set Software then toggles bit CCISxO to switch the capture signal between Vcc and GND initiating a capture each time the input is toggled as shown in Figure 10 21 Figure 10 21 Software Capture Example CCISX1 ___________________________ CCISx0 CCIx Capture CCISx1 CCISx0 9 9 7 I CCIxB Capture Capture GND Mode 3 Vcc o o CClx CCMx1 Both Edges Selected 1 1 The following is a software example of a capture performed by software The data of capture compare register CCRx are taken by the software It is assumed that CCMx1 0 and CCISx1 bits are set Bit 50 selects the CCIx signal to be high or low Ne Ne Ne Ne Ne XOR 5 0 amp CCTLx Timer_A 10 17 Timer Modes 10 4 2 Capture Compare Block Compare Mode 10 18 The compare mode is selected if the bit located in control word CCTLx is reset In compare mode all the capture hardware circuitry is inactive and the capture mode overflow logic is inactive The compare mode is most often used to generate interrupts at specific
395. me examples serve as explanations and others as application hints The suffix W or no suffix in the instruction mnemonic results in a word operation The suffix B at the instruction mnemonic results in a byte operation B 8 ADC W ADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Overview Add carry to destination Add carry to destination ADC dst or ADC W dst ADC B dst dst C dst ADDC 0 dst ADDC B 0 dst The carry bit C is added to the destination operand The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if dst was incremented from OFFFFh to 0000 reset otherwise Set if dst was incremented from OFFh to 00 reset otherwise V Set if an arithmetic overflow occurs otherwise reset OscOff CPUOff and GIE are not affected The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed to by R12 ADD R13 0 R12 Add LSDs ADC 2 R12 Add carry to MSD The 8 bit counter pointed to by R13 is added to a 16 bit counter pointed to by R12 ADD B R13 0 R12 Add LSDs ADC B 1 R12 Add carry to MSD Instruction Set Description B 9 Instruction Set Overview ADD W ADD B Syntax Operation Description Status Bits Mode Bits Example Example Add source to destination Add source to destination ADD src dst
396. mented Set through the RST NMI pin Not implemented Not implemented Not implemented USARTO receive flag USARTO transmitter ready Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented The configuration of some MSP430 devices may differ from those in above table Refer to specific device data sheets for individual configurations System Resets Interrupts and Operating Modes 3 15 Interrupt Processing Table 3 8 MSP430x13x Interrupt Flag Registers 1 and 2 Bit Position Short Form IFG1 0 IFG1 1 IFG1 2 IFG1 3 IFG1 4 IFG1 5 IFG1 6 IFG1 7 IFG2 0 IFG2 1 IFG2 2 IFG2 3 IFG2 4 IFG2 5 IFG2 6 IFG2 7 WDTIFG OFIFG NMIIFG URXIFGO UTXIFGO Initial State Set Or reset Set Reset Reset Set Comments Set on watchdog timer overflow in watchdog mode or security key violation Reset with VCC power up or a reset condition at the RST NMI pin in reset mode Flag set on oscillator fault Not implemented Not implemented Set through the RST NMI pin Not implemented USARTO receive flag USARTO transmitter ready Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Note Theconfiguration of some MSP430 devices may differ from those in above table Refer to specific device data sheets for individual configurations 3 16 Interrupt Processing Table 3 9 MSP43
397. mer in Continuous Mode The OUTx signal is changed when the timer reaches the CCRx and CCRO values depending on the output mode as shown in Figure 10 25 Figure 10 25 Output Examples Timer in Continuous Mode Output Mode 2 PWM Toggle Reset Output Mode 3 PWM Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 PWM Toggle Set Output Mode 7 PWM Reset Set OFFFFh CCRO CCR1 Oh TER Output Mode 1 Set TAOV EQU1 EQUO TAOV EQU1 EQUO Interrupt Events Timer A 10 23 Timer A Registers 10 5 3 3 Output Examples Timer Up Down Mode The OUTx signal changes when the timer equals CCRx in either count direction and when the timer equals CCRO depending on the output mode as shown in Figure 10 26 Figure 10 26 Output Examples Timer in Up Down Mode 1 OFFFFh CCRO CCR2 Oh 25 Output Mode 1 Set d 3 Output Mode 2 PWM Toggle Reset ah Output Mode 3 PWM Set Reset L loOutput Mode 4 Toggle Output Mode 5 Reset E Output Mode 6 PWM Toggle Set zs es Output Mode 7 PWM Reset Set TIMOV EQUO gg TIMOV eguz EQUO pouz Interrupt Events 10 6 Timer A Registers The Timer_A registers described in Table 10 3 are word structured and must be accessed using word instructions Table 10 3 Timer A Registers Register Short Form Register Type Address Initial State Timer control TACTL Read write 1
398. mode is described in Table 5 10 Table 5 10 Indirect Autoincrement Mode Description Assembler Code MOV R10 0 R11 Length One or two words Operation Content of ROM MOV R10 0 R11 Move the contents of the source address contents of R10 to the destination address contents of R11 Register R10 is incremented by 1 for a byte operation or 2 for a word operation after the fetch it points to the next address without any overhead This is useful for table processing Comment Valid only for source operand The substitute for destination operand is O Rd plus second instruction INCD Rd Example Before Address Space Register OFF18h OFF16h OFF 14h OFF12h OFA34h OFA32h OFA30h 010AAh 010A8h 010A6h MOV R10 0 R11 Address Space Pc Register OFF18h OFF16h OFF14h OFF12h R10 OFA34h R11 010A8h OFA34h OFA32h OFA30h 010AAh 010A8h 010A6h The autoincrementing of the register contents occurs after the operand is fetched This is shown in Figure 5 6 Figure 5 6 Operand Fetch Operation Instruction Address 16 Bit CPU 5 13 Addressing Modes 5 2 7 Immediate Mode The immediate mode is described in Table 5 11 Table 5 11 Immediate Mode Description Assembler Code Content of ROM MOV 45h TONI MOV PC X PC 45 X TONI PC Length Two or three words It is one word less if a constant of CG1 or CG2 can be u
399. n SOMI Slave out master in The direction is defined by SOMIDIR SIMODIR 0 input direction SOMIDIR SYNC and not MM or STC or not STE Output direction is selected when SPI Slave Mode is selected When 4 SPI is selected STC 0 input direction is forced by a low level on external STE pin UCLK USART clock The master drives this signal and the slave uses it to receive and transmit data The direction is defined by UCLKDIR UCLKDIR O input direction UCLKDIR SYNC and MM and STC or STE Output direction is selected when SPI Master Mode is selected When 4 SPI is selected STC 0 input direction is forced by a low level on external STE pin OV STE Slave transmit enable Used in four pin mode to control more than one slave in a multiple master and slave system The interconnection of the USART in synchronous mode to another device s serial port with one common transmit receive shift register is shown in Figure 13 3 where MSP430 is master or slave The operation of both devices is identical Synchronous Operation Figure 13 3 MSP430 USART as Master External Device With SPI as Slave Receive Buffer UXRXBUF Transmit Buffer UXTXBUF SPI Receive Buffer Receive Shift Register LSB MSB MASTER MSP430 USART COMMON SPI The master initiates the transfer by sending the UCLK signal For the master data is shifted out of the transmit shift register on one clock ed
400. n 0 No feedback Listen 1 Transmit signal is internally fed back to the receiver This is commonly known as loopback mode Character length This register bit selects the length of the character to be transmitted as either 7 or 8 bits 7 bit characters do not use the eighth bit in UXRXBUF and UxTXBUF This bit is padded with 0 CHAR 0 7 bit data CHAR 1 8 bit data Number of stop bits This bit determines the number of stop bits transmitted The receiver checks for one stop bit only SP 0 one stop bit SP 1 two stop bits Parity odd even If the PENA bit is set parity bit is enabled the PEV bit defines odd or even parity according to the number of odd or even 1 bits in both the transmitted and received characters the address bit address bit multiprocessor mode and the parity bit PEV 0 odd parity PEV 1 even parity Parity enable If parity is disabled no parity bit is generated during transmission or expected during reception A received parity bit is not transferred to the UxRXBUF with the received data as it is not considered one of the data bits In address bit multi processor mode the address bit is included in the parity calculation PEN 0 Parity disable PEN 1 Parity enable So OOOO OO Note Mark and Space Definitions The mark condition is identical to the signal level in the idle state Space is the opposite signal level the start bit is always space
401. n register ADC10MEM Some key and unique features of the ADC10 are L 200 ksps maximum conversion rate 10 bit converter with 1LSB differential nonlinearity DNL and 1LSB integral nonlinearity INL Built in sample and hold On chip dedicated RC oscillator Integrated sensor for temperature measurement D D UL Up to ten analog inputs Two inputs are shared with external applied refer ence voltages the number of available analog inputs may differ between devices Four internal channels for conversion of temperature and external references On chip reference voltages 1 5 V or 2 5 V selected by software Selectable internal or external sources for both positive and negative reference voltage levels selectable for each channel independently Conversion clock source ADC10OSC RC oscillator in ADC10 ACLK MCLK or SMCLK Versatile conversion modes including single channel repeated single channel sequence and repeated sequence One register buffer loaded after each conversion with the conversion result Lj ADC core and reference voltage powered down separately ADC10 iu ADC10 Description and Operation 16 2 ADC10 Description and Operation 16 2 1 ADC Core The ADC core shown in Figure 16 2 converts the analog input to its 10 bit representation and stores the results in the ADC10MEM register The core uses two programmable selectable voltage levels and Vp to
402. nable bit and the GIE bit are set Figure 11 6 shows the flag set cycle Figure 11 6 Up Mode Flag Setting Timer Clock Timer Set Flag TBIFG Set Flag CCIFGO Timer Modes 11 3 2 1 Timer in Up Mode Changing the Period Register TBCLO Value Immediate Mode for TBCLO Changing the timer period register TBCLO while the timer is running and when the transfer mode from CCRO is immediate can be a little tricky When the new period is greater than or equal to the old period the timer simply counts up to the new period and no special attention is required see Figure 11 7 However when the new period is less than the old period the phase of the timer clock during the TBCLO update affects how the timer reacts to the new period If the new smaller period is transferred from CCRO to TBCLO during a high phase of the timer clock then the timer rolls to zero or begins counting down when in the up down mode on the next rising edge of the timer clock However if the new smaller period is written during a low phase of the timer clock then the timer continues to increment with the old period for one more clock cycle before adopting the new period and rolling to zero or beginning counting down This is shown in Figure 11 8 5 27 7 17 7 1 Note If TBCLO gt TBR max the counter rolls to zero with the next rising edge of timer clock Figure 11 7 New Period Old Period Timer TBCLOo
403. nabled interrupts coming from active peripherals or RST NMI 3 5 3 Low Power Mode 4 LPM4 In low power mode 4 all activities cease only the RAM contents I O ports and registers are maintained Wake up is only possible by enabled external interrupts Before activating LPM4 the software should consider the system conditions during the low power mode period The two most important conditions are environmental that is temperature effect on the DCO and the clocked operation conditions The environment defines whether the value of the frequency integrator should be held or corrected A correction should be made when ambient conditions are anticipated to change drastically enough to increase or decrease the system frequency while the device is in LPM4 3 28 3 6 Basic Hints for Low Power Applications Basic Hints for Low Power Applications There are some basic practices to follow when current consumption is a critical part of a system application d d L LDLIDDODLDLDU OA C C O C O O L Switch off analog circuitry when possible Select the lowest possible operating frequency for the core and the individual peripheral module Use the interrupt driven software the program starts execution rapidly Tie all unused inputs to an applicable voltage level The list below defines the correct termination for all unused pins Pin AVcc AVss Xout VREF VeREF VreF VereEF XIN XT2IN XT20UT Px 0 to Px 7 RST
404. nd provides valuable easy to use debugging capability 2 5 Operation Control The operation of the different MSP430 members is controlled mainly by the information stored in the special function registers SFRs The different bits in the SFRs enable interrupts provide information about the status of interrupt flags and define the operating modes of the peripherals By disabling peripherals that are not needed during an operation total current consumption can be reduced The individual peripherals are described later in this manual Architectural Overview 2 3 Peripherals 2 6 Peripherals Peripheral modules are connected to the CPU through the MAB MDB and interrupt service and request lines The MAB is usually a 5 bit bus for most of the peripherals The MDB is an 8 bit or 16 bit bus Most of the peripherals operate in byte format Modules with an 8 bit data bus are connected by bus conversion circuitry to the 16 bit CPU The data exchange with these modules must be handled with byte instructions The SFRs are also handled with byte instructions The operation for 8 bit peripherals follows the order described in Figure 2 2 Figure 2 2 Bus Connection of Modules Peripherals Interrupt Request Interrupt Bus Grant MAB MDB Interrupt Request Module Peripheral Interrupt Bus Grant PUC 2 7 Oscillator and Clock Generator 2 4 The LFXT1 oscillator is designed for the commonly used 32 768 Hz low current consump
405. nd the program counter is aligned to even addresses Figure 5 1 shows the program counter bits Figure 5 1 Program Counter 15 1 0 Program Counter Bits 15 to 1 5 1 2 The System Stack Pointer SP The system stack pointer must always be aligned to even addresses because the stack is accessed with word data during an interrupt request service The system SP is used by the CPU to store the return addresses of subroutine calls and interrupts It uses a predecrement postincrement scheme The advantage of this scheme is that the item on the top of the stack is available The SP can be used by the user software PUSH and POP instructions but the user should remember that the CPU also uses the SP Figure 5 2 shows the system SP bits Figure 5 2 System Stack Pointer 5 2 15 1 0 System Stack Pointer Bits 15 to 1 CPU Registers 5 1 2 1 Examples for System SP Addressing Refer to Figure 5 4 OV SP R4 SP R4 OV SP R5 Item TOS gt R5 OV 2 SP R6 Item I2 gt R6 OV R7 0 SP Overwrite TOS with R7 OV R8 4 SP Modify item I1 PUSH R12 Store R12 in address Oxxxh 6 SP points to same address POP R12 Restore R12 from address Oxxxh 6 SP points to Oxxxh 4 OV SP R5 Item gt R5 popped from stack same as POP instruction Figure 5 3 shows stack usage Figure 5 3 Stack Usage 5 1 2 2 Special Cases PUSH SP and POP SP The special cases of using the
406. nd unique features of the ADC12 are 1 200 ksps maximum conversion rate 12 bit converter with 1LSB differential nonlinearity DNL and 1LSB integral nonlinearity INL Lj Built in sample and hold with selectable sampling periods controlled by software via a control bit a sampling timer or by other MSP430 timers On chip dedicated RC oscillator used as an option for sample and conversion timing Integrated diode for temperature measurement Eightindividually configurable channels for conversion of external signals LJ Four internal channels for conversion of temperature and external references On chip reference voltages 1 5 V or 2 5 V selected by software Selectable internal or external sources for both positive and negative reference voltage levels selectable for each channel independently Selectable conversion clock source ADC12 je ADC12 Description and Operation Versatile conversion modes including single channel repeated single channel sequence and repeated sequence Li Sixteen 12 bit registers for storage of conversion results Each register is individually accessible by software and individually configurable to define the channel and references for its conversion result ADC core and reference voltage powered down separately 15 2 ADC12 Description and Operation 15 2 1 ADC Core The ADC core shown in Figure 15 2 converts the analog input to its
407. negative reset if positive Z Setif result is zero reset otherwise C Setif result is not zero reset otherwise NOT Zero V Reset OscOff CPUOff and GIE are not affected Figure B 11 Destination Operand Sign Extension Example 15 8 7 0 R7 is loaded with the P1IN value The operation of the sign extend instruction expands bit 8 to bit 15 with the value of bit 7 R7 is then added to R6 MOV B amp P1IN R7 P1IN 080h 1000 0000 SXT R7 R7 OFF80h 1111 1111 1000 0000 ADD R7 R6 add value of EDE to 16 bit ACCU Instruction Set Description B 59 Instruction Set Overview TST W TST B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Test destination Test destination TST dst TST W dst TST B dst dst OFFFFh 1 dst OFFh 1 CMP 0 dst CMP B 0 dst The destination operand is compared with zero The status bits are set accord ing to the result The destination is not affected N Set if destination is negative reset if positive Z Set if destination contains zero reset otherwise C Set V Reset OscOff CPUOff and GIE are not affected R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS a R7 is positive but not zero R7NEG R7 is negative R7ZERO R7 is zero The low byte of R7 is
408. neral Recommendation 6 8 In general one should avoid a hardware multiplication operation within an interrupt routine when a hardware multiplication is already used in the main program This will depend upon the application specific software applied libraries and other included software The methods previously discussed have some negative implications therefore the best practice is to keep interrupt routines as short as possible Hardware Multiplier Software Restrictions 6 5 3 Hardware Multiplier Software Restrictions MACS The multiplier does not automatically detect underflow or overflow in the MACS mode An overflow occurs when the sum of the accumulator register and the result of the signed multiplication exceed the maximum binary range The binary range of the accumulator for positive numbers is 0 to 231 1 7FFF FFFFh and for negative numbers is 1 OFFFF FFFFh to 231 8000 0000h An overflow occurs when the sum of two negative numbers yields a resultthat is in the range given above for a positive number An under flow occurs when the sum of two positive numbers yields a result that is in the range for a negative number The maximum number of successive MACS instructions without underflow or overflow is limited by the individual application and should be determined us ing a worst case calculation Care should then be exercised to not exceed the maximum number or to handle the conditions accordingly Hardware Multiplie
409. nexpected reset or interrupt Watchdog Timer 9 7 9 8 Chapter 10 Timer A This section describes the basic functions of the MSP430 general purpose 16 bit Timer A All capture compare blocks are identical All MSP430x1xx devices have three CCRs Timer A3 implemented M d Note Use of the Word Count Throughout this chapter the word countis used in the text As used in these instances it refers to the literal act of counting It means that the counter must be in the process of counting for the action to take place If a particular value is directly written to the counter then the associated action will nottake place For example the CCRO interrupt flag is set when the timer counts up tothe value in CCRO The counter must countfrom CCRO 1 to CCRO If the CCRO value were simply written directly to the timer with software the interrupt flag would notbe set even though the values in the timer and the CCRO registers are the same Hoo RFRFRrereR wnm po SHHEewspa a EBEBEFZ7I_ Topic Page 38 MIMtrOCUCtI ON 10 2 10 2 Operation 2222 2 10 4 10 35 Timer Modes 10 7 10 4 Capture Compare Blocks 10 13 10 5 The Output Unit wos os ce senean ee eren eerie we eee sole 10 19 10 6 sTimerZA Registers 222222222 10 24 TO Z5TimerseASUARTI E year E ai 10 33
410. nging the NMIES bit with software can generate an NMI interrupt Bit 7 This bit stops the operation of the watchdog counter The clock multiplexer is disabled and the counter stops incrementing It holds the last value until the hold bit is reset and the operation continues It is cleared by the PUC signal HOLD 0 The WDT is fully active HOLD 1 The clock multiplexer and counter are stopped 9 1 1 1 Accessing the WDTCTL Watchdog Timer Control Register The WDTCTL register can be read or written to As illustrated in Figure 9 3 WDTCTL can be read without the use of a password A read access is performed by accessing word address 0120h The low byte contains the value of WDTCTL The value of the high byte is always read as 069h Figure 9 3 Reading WDTCTL 15 8 7 0 WDTCTL 0120h 0 1 1 0 1 0 0 1 Read Data rrr r rr rr rw x w Write access to WDTCTL illustrated in Figure 9 4 is only possible using the correct high byte password To change register WDTCTL write to word address 0120h The low byte contains the data to write to WDTCTL The high byte is the password which is 05Ah A system reset PUC is generated if any value other than 05Ah is written to the high byte of address 0120h Figure 9 4 Writing to WDTCTL 9 4 15 8 7 0 WDTCTL w w w w w w w w rw x w A The Watchdog Timer 9 1 2 Watchdog Timer Interrupt Control Functions The Watchdog Timer WDT uses two bits in the SFRs for inter
411. nnel mode CONSEQ 0 2 and then reset ENC See also the ENC bit description ADC12 Control Registers 15 8 4 ADC12 Interrupt Flags ADC12IFG x and Interrupt Enable Registers ADC12IEN x There are 16 ADC12IFG x interrupt flags 16 ADC12IE x interrupt enable bits and one interrupt vector word The interrupt flags and enable bits are associated with the 16 ADC12MEMX registers All interrupt flags and interrupt enable bits are reset during POR ADC12IFG 01A4h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IFG x bits 0 15 ADC12IFG x interrupt flag is set if a conversion result register ADC12MENMXx is loaded with the result of a conversion The range for x is 15 The interrupt flags are reset if their corresponding ADC12MEMx conversion result register is accessed To enable correct handling of overflow conditions they are not reset by accessing the interrupt vector word ADC12IV The overflow condition exists if another conversion result is written to ADC12MEMXx and the corresponding ADC12IFG x is not reset ADC12IE ADC ADC 01A6h 1 12 IE 10 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADCi2IE x bits 0 15 ADC12IE x interrupt enable bit enables or disables the interrupt request service generated if the corresponding interrupt flag ADC121FG x is set The range f
412. nored until the prior sample and conversion cycle is completed Figure 15 17 Conversion Timing Pulse Sample Mode SAMPCON ep Xe sr er tsample tconvert t sync An example of the pulse sample mode configuration is shown in Figure 15 18 The selected input signal source is Timer B OUTO The timing for the example is shown in Figure 15 19 Figure 15 18 Pulse Sample Mode Example Configuration Internal ADC12SSEL Oscillator ADC120N ADC12DIV T ADC120SC Vp VR ADC12CLK Divider by ACLK 1 2 3 4 5 6 7 8 MCLK Analog Sample us Sonal and 12 bit A D Converter Core SHTO SMCLK Hold SHT1 D _ SHP B Sampling TT ADC12SC q SAMPCON Lo Timer 4 O lt 1 EVE Timer A OUT1 SHI 5 Timer B OUTO Misc Timer_B OUT1 12 Bit SAR Conversion CTL ENC v SHS ADC12 15 25 Sampling Figure 15 19 Pulse Sample Mode Example Timing Timer B OUTO Additional edges are ignored until after conversion completes SAMPCON ADC12CLK Rasy Se Geter ey ee ee ees tsync tsample gt lt tconvert Next sync and sample 15 7 3 2 Extended Sample Mode In extended sample mode the input signal selected by the SHS bits is used to control the sampling SAMPCON signal directly The internal sampling timer is
413. not relevant and can be ignored gaw ect Table 11 2 Compare Latch Operating Modes Continued 2t i CLLDx From Lowest Counter TBCCTLx in Mode ooo testers oad TBCCR data to compare laen TBODY __ __ Group see MCx Note 1 0 3 diat TBCL1 TBCL2 TBCL3 loaded immediately when the TBCL4 TBCL5 TBCL6 loaded immediately when the corresponding TBCCRx register is loaded corresponding TBCCRx register is loaded 1 3 TBR ts to O TBCL1 TBCL2 TBCL3 updated simultaneously when TBCL4 TBCL5 TBCL6 updated simultaneously when E SOHO TBR counts to 0 TBR counts to 0 12 TBR ts to 0 TBCL1 TBCL2 TBCL3 updated simultaneously when TBCL4 TBCL5 TBCL6 updated simultaneously when counts to TBR counts to 0 TBR counts to 0 1 2 Load Conditions load TBCCRx data to compare latch TBCLx TBR counts to 0 TBCL1 TBCL2 TBCL3 updated simultaneously when TBCL4 TBCL5 TBCL6 updated simultaneously when or to TBCLO TBR counts to 0 or to TBCLO TBR counts to 0 or to TBCLO TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 Loaded immediately when the corresponding TBCCRx register is loaded TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 updated simultaneously when TBR counts to 0 TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 16 updated simultaneously when TBR co
414. not useful for output unit O Output mode 0 Output mode 1 Output mode 2 Output mode 3 Output mode 4 Output mode 5 Output mode 6 Output mode 7 Output mode The output signal OUTx is defined by the OUTx bit in control register CCTLx The OUTx signal updates immediately upon completion of writing the bit information Set mode The output is set when the timer value becomes equal to compare data TBCLx Itremains set until a reset of the timer or until another output mode is selected and controls the output PWM toggle reset mode The output is toggled when the timer value becomes equal to compare data TBCLx It is reset when the timer value becomes equal to TBCLO PWM set reset mode The output is set when the timer value becomes equal to compare data TBCLx It is reset when the timer value becomes equal to TBCLO Toggle mode The output is toggled when the timer value becomes equal to compare data TBCLx The output period is double the timer period Reset mode The output is reset when the timer value becomes equal to compare data TBCLx It remains reset until another output mode is selected and controls the output PWM toggle set mode The output is toggled when the timer value becomes equal to compare data TBCLx It is set when the timer value becomes equal to TBCLO PWM toggle set mode The output is reset when the timer value becomes equal to compare data TBCLx It is set when the timer v
415. nstant 08h is inverted and logically ANDed with the status register SR The result is placed into the SR N Not affected Z Not affected C Not affected V Not affected GIE is reset OscOff and CPUOff are not affected The general interrupt enable GIE bit in the status register is cleared to allow a nondisrupted move of a 32 bit counter This ensures that the counter is not modified during the move by any interrupt DINT All interrupt events using the GIE bit are disabled NOP MOV COUNTHI R5 Copy counter MOV COUNTLO R6 EINT All interrupt events using the GIE bit are enabled Ss Note Disable Interrupt If any code sequence needs to be protected from interruption the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence or should be followed by an NOP ee EINT Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Overview Enable general interrupts EINT 1 GIE or 0008h OR SR SR NOT src OR dst dst BIS 8 SR All interrupts are enabled The constant 08h and the status register SR are logically ORed The result is placed into the SR N Not affected Z Not affected C Not affected V Not affected GIE is set OscOff and CPUOff are not affected The general interrupt enable GIE bit in the status register is set Interrupt routine of ports P1 2 to P1 7 P1IN is the addre
416. nt for the first group and the CLLDx bits for TBCL4 determine the load event for the second group The CLLDx bits in CCTL2 CCTL3 CCTL5 and CCTL6 are unused When all compare latches are grouped together TBCLGRP 3 then the CLLDx bits in TBCL1 determine the load event When using groups two conditions must exist for the compare latches to be loaded First all CCRx registers of the group must be updated except when using immediate mode second the load event must occur This means that ifa user intends to retain any CCRx register data of a group when updating the group the old data must be written to the CCRx register again Otherwise the compare latches will not be updated The CLLDx bits in the applicable CCTLx register select the load event There are four choices for the load event Immediate When TBR counts to 0 Continuous mode or up mode when TBR counts to 0 Up down mode when TBR counts to TBCLO or counts to 0 When TBR counts TBCLx gaw Le LH The groupings and load conditions are summarized below in Table 11 2 Table 11 2 Compare Latch Operating Modes iam ooume TBCLGRP TBCCTLx in Mode Group see MCx Note 1 TBR counts 0 TBR counts toO TBR counts 0 TBR counts toO TBR counts toO TBR counts toO TBR counts to 0 TBR counts toO TBR counts toO TBR counts 0 TBR counts toO TBR counts toO TBR counts toO TBR counts to 0 TBR counts 0 TB
417. nt of compare register CCRO as shown in Figure 10 5 When the timer value and the value of compare register CCRO are equal or if the timer value is greater than the CCRO value the timer restarts counting from zero Figure 10 5 Timer Up Mode OFFFFh CCRO Oh Flag CCIFGO is set when the timer equals the CCRO value The TAIFG flag is set when the timer counts from CCRO to zero All interrupt flags are set independently of the corresponding interrupt enable bit but an interrupt is requested only if the corresponding interrupt enable bit and the GIE bit are set Figure 10 6 shows the flag set cycle Figure 10 6 Up Mode Flag Setting Timer Clock Timer Set Flag TAIFG Set Flag CCIFGO Timer_A 10 7 Timer Modes 10 3 2 1 Timer in Up Mode Changing the Period Register CCRO Value Changing the timer period register CCRO while the timer is running can be a little tricky When the new period is greater than or equal to the old period the timer simply counts up to the new period and no special attention is required see Figure 10 7 However when the new period is less than the old period the phase of the timer clock during the CCRO update affects how the timer reacts to the new period If the new smaller period is written to CCRO during a high phase of the timer clock then the timer rolls to zero or begins counting down when in the up down mode on the next rising edge of the timer clock However if the new smaller
418. ntax Operation Description Status Bits Example Instruction Set Overview Jump if greater or equal JGE label If N XOR V 0 then jump to label PC 2 x offset gt PC If N XOR V 1 then execute the following instruction The status register negative bit N and overflow bit V are tested If both N and V are set or reset the 10 bit signed offset contained the instruction LSBs is added to the program counter If only one is set the instruction following the jump is executed This allows comparison of signed integers Status bits are not affected When the content of R6 is greater or equal to the memory pointed to by R7 the program continues at label EDE CMP QR7 R6 R6 gt R7 compare on signed numbers JGE EDE Yes R6 R7 cr No proceed Instruction Set Description B 35 Instruction Set Overview JL Jump if less Syntax JL label Operation If N XOR V 1 then jump to label PC 2 x offset PC If N XOR V 2 0 then execute following instruction Description The status register negative bit N and overflow bit V are tested If only one is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If both N and V are set or reset the instruction following the jump is executed This allows comparison of signed integers Status Bits Status bits are not affected Example When the content of R6 is less than the memory pointed to by R7 the
419. o one or more destinations The USART has features that identify the start of blocks and suppress interrupts and status information from the receiver until a block start is identified In both multiprocessor formats the sequence of data exchanged with the USART module is based on data polling or on the use of the receive interrupt features Both of the asynchronous multiprocessor formats idle line and address bit allow efficient data transfer between multiple communication systems They can also minimize the activity of the system to save current consumption or processing resources The control register bit MM defines the address bit or idle line multiprocessor format Both use the wake up on transfer mode by activating the TXWake bit address feature function and RXWake bit The URXWIE and URXIE bits control the transmit and receive features of these asynchronous communication formats 12 3 4 Idle Line Multiprocessor Format In the idle line multiprocessor format shown in Figure 12 7 blocks of data separated by an idle time An idle receive line is detected when ten or more 1s in a row are received after the first stop bit of a character Figure 12 7 Idle Line Multiprocessor Format Block of Frames HER a dB N g H ENSE Oe ce ES EST SE SIS t t es Idle Periods of 10 Bits or More UTXD URXD Expanded UTXD URXD ee R First Frame Within Block Frame Within Block Frame Within Block Is
420. o the transmit shift register on the next bit clock after the shift register is ready MOV B 14 amp U0TXBUF BIC B 5 0 6 2 If BITCLK SMCLK then the transmitter might be stopped before the buffer is loaded into the transmitter shift register Interrupt and Control Functions 13 4 3 USART Receive Interrupt Operation In the receive interrupt operation shown in Figure 13 12 the receive interrupt flag URXIFG is set each time a character is received and loaded into the receive buffer Figure 13 12 Receive Interrupt Operation SYNC r 1 SYNC 1 Valid Start Bit URXS Eu DEM Receiver Collects Character URXSE From URXD PE URXIE Request FE Interrupt Service BRK URXEIE URXIFG URXWIE e RXWake e SWRST Character Received PUC or UxRXBUF Read Master Overrun USPIIE IRQA URXIFG is reset by a system reset PUC signal or by a software reset SWRST UxRXIFG is reset automatically if the interrupt is served or the receive buffer UxRXBUF is read The receive interrupt enable bit USPIIE if set enables a CPU interrupt request as shown in Figure 13 13 The receive interrupt flag bits URXIFG and USPIIE are reset with a PUC signal or a SWRST Figure 13 13 Receive Interrupt State Diagram Wait For Next Start USPIIE 1 SWRST 1 USPIIE 0 Interrupt 2 USPIIE 1 and Service Started Completed GI
421. ode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCLO depending on the output mode as shown in Figure 11 26 Figure 11 26 Output Examples Timer in Up Down Mode 1 TBR max TBCLO TBCL3 Oh Output Mode 1 Set Output Mode 2 PWM Toggle Reset ah Output Mode 3 PWM Set Reset L loOutput Mode 4 Toggle Output Mode 5 Reset E Output Mode 6 PWM Toggle Set EN Output Mode 7 PWM Reset Set TIMOV EQUO EqusTIMOV EQUO boug Interrupt Events 11 28 Timer B Registers 11 6 Timer B Registers The Timer B registers described in Table 11 4 are word structured and must be accessed using word instructions Table 11 4 Timer B Registers Register Short Form Register Type Address Initial State Timer control TBCTL Read write 180h POR reset Timer B register TBR Read write 190h POR reset Cap com control 0 CCTLO Read write 182h POR reset Capture compare 0 CCRO Read write 192h POR reset Cap com control 1 CCTL1 Read write 184h POR reset Capture compare 1 CCR1 Read write 194h POR reset Cap com control 2 CCTL2 Read write 186h POR reset Capture compare 2 CCR2 Read write 196h POR reset Cap com control 3 CCTL3 Read write 188h POR reset Capture compare 3 CCR3 Read write 198h POR reset Cap com control 4 CCTL4 Read write 18Ah POR reset Capture compare 4 CCR4 Read write 19Ah POR reset Capture compare 5
422. ode CONSEQ 0 and reset enable conversion bit ENC The current conversion is stopped immediately The data in memory register ADC12MEMXx is unpredictable and the interrupt flag ADC12IFG x or may not be set This method is generally not recommended Conversion Modes An illustration of repeat sequence of channels mode is shown in Figure 15 12 Figure 15 12 Repeat Sequence of Channels Mode CONSEQ 3 ADC120N 1 x CStartAdd Wait for Enable SHS 0 ENC 1 4 ADC12SC Wait for Trigger ENC 0 EOS x 1 SAMPCON 4 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx If EOS x 1 then x CStartAdd else if x lt 15 thenx 2 x 1 else x 0 SAMPCON Y If EOS x 1 then x CStartAdd else if x lt 15 then x 1 12 x ADC12CLK Convert Use else x 0 12 x ADC12CLK MSC 1 and SHP 1 1 x ADC12CLK 1 Conversion ENC 1 Completed Result Stored Into ADC12MEMXx ADC12IFG x is Set or EOS x 0 x pointer to conversion memory register ADC 12MEM0 ADC12MEM15 conversion memory control register ADC12MCTLO ADC12MCTL15 15 5 5 Switching Between Conversion Modes Changing the mode of operation of the ADC12 while the converter is not actively running is done simply by selecting the new mode of operation with the CONSEQ bits However if
423. ogram continues at the label EQUAL EDE TONI MEM EDE MEM TONI JEQ EQUAL YES JUMP DADC W DADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Overview Add carry decimally to destination Add carry decimally to destination DADC dst or DADC W src dst DADC B dst dst C dst decimally DADD 0 dst DADD B 0 dst The carry bit C is added decimally to the destination N Set if MSB is 1 Z Set if dst is 0 reset otherwise C Set if destination increments from 9999 to 0000 reset otherwise Set if destination increments from 99 to 00 reset otherwise V Undefined OscOff CPUOff and GIE are not affected The four digit decimal number contained in R5 is added to an eight digit deci mal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD R5 0 R8 Add LSDs DADC 2 R8 Add carry to MSD The two digit decimal number contained in R5 is added to a four digit decimal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD B R5 0 R8 Add LSDs C DADC 1 R8 Add carry to MSDs Instruction Set Description B 23 Instruction Set Overview DADD W DADD B Syntax Operation Description Status Bits Mode Bits Example Example B 24 Source and carry added decimally to destination Source and carry added decimally
424. ol The timer has four modes of operation as shown in Figure 10 2 and described in Table 10 1 stop up continuous and up down The operating mode is software selectable with the MCO and MC1 bits in the TACTL register Figure 10 2 Mode Control Data 16 Bit Timer CLK Timer Clock Eu Control EquO Carry Zero a MC1 Set TAIFG POR 0 0 Stop Mode 0 1 Up Mode 1 0 Continuous Mode 1 1 Up Down Mode Table 10 1 Timer Modes Mode Control MC1 MCO Mode Description 0 0 Stop The timer is halted 0 1 Up The timer counts upward until value is equal to value of compare register CCRO 1 0 Continuous The timer counts upward continuously 1 1 Up Down The timer counts up until the timer value is 10 4 equal to compare register 0 and then it counts down to zero Timer A Operation 10 2 2 Clock Source Select and Divider The timer clock can be sourced from internal clocks i e ACLK or SMCLK or from an external source TACLK as shown in Figure 10 3 The clock source is selectable with the SSELO and SSEL1 bits in the TACTL register It is important to note that when changing the clock source for the timer errant timings can occur Forthis reason stopping the timer before changing the clock source is recommended The selected clock source may be passed directly to the timer or divided by 2 4 or 8 as shown in Figure 10 4 The IDO and ID1 bits in the TACTL register select the clock division Note that t
425. ollowing example a subroutine moves the programming code sequence to another memory such as RAM Start of Subroutine Load Flash Routine Source Start Address of The Code Sequence R7 Destination Start Address of The Code Sequence R10 Move One Word R7 R10 Increment Source and Destination Pointer in R7 and R10 End of Source Code End of Subroutine RET Definitions used in Subroutine Move programming code sequence into RAM load flash routine Flash ram set 0222h Start address of flash program in the RAM program in the RAM Prg source start set Oxxxxh Start address of code in the flash to be prg ed Prg source end Oyyyyh End address of code in the flash to be prg ed Prg dest start Set Flash ram load flash routine The code of the program which moves push push mov mov Flash access code write erase starts st r9 10 Prg source start R9 Prg dest start R10 load flash prg mov incd incd cmp jne pop pop ret QR9 0 R10 R10 R9 Prg source end R9 load flash prg T9 10 label load flash routine load pointer source load pointer destination move a word destination pointer 2 source pointer 2 compare to end_of_code Flash Memory C 27
426. one crystal oscillator Watchdog Timer General Purpose Timer Timer 16 bit timer with three capture compare registers and PWM output Port1 2 Eight I Os each all with interrupt Comparator_A precision analog comparator ideal for slope A D conversion Uo OOL The 11x1 device family includes MSP430C1111 2KB ROM 128B RAM MSP430C1121 4KB ROM 256B RAM MSP430F1101 1KB 128 Flash 128B RAM MSP430F1111 2KB 256B Flash 256B RAM MSP430F 1121 4KB 256 Flash 256B RAM Introduction 1 3 11x2 Devicest 1 4 11x2 Devicest 1 5 12x Devices The 11x2 devices contain the following peripherals Basic Clock System one crystal oscillator Watchdog Timer General Purpose Timer Timer 16 bit timer with three capture compare registers and PWM output Port1 2 Eight l Os each all with interrupt ADC10 10 bit A D OULU The 11x2 device family includes MSP430F 1122 4KB 256B Flash 256B RAM MSP430F 1132 8KB 256B Flash 256B RAM The 12x devices contain the following peripherals Basic Clock System on chip DCO one crystal oscillator Watchdog Timer General Purpose Timer Timer_A3 16 bit timer with three capture compare registers and PWM output I O Port1 2 Eight I Os each all with interrupt I O Port3 Eight I Os each Comparator_A precision analog comparator ideal for slope A D conversion USARTO The 12x device family includes
427. ons Address Mode The result of the multiplication operation can be accessed in indexed indirect or indirect autoincrement mode The result registers may be accessed without any restrictions if you use the indexed address mode including the symbolic and absolute address modes However when you use the indirect and indirect autoincrement address modes to access the result registers you need atleast one instruction between loading the second operand and accessing one of the result registers ck KKK kk Ck Ck ck ck kk Ck ck Ck kk ck ck ck kk Ck ck ck ck kk ck ck ck kk Ck ck ck ko Mk Mk Sk kc k ko kx ko ko ko k EXAMPLE MULTIPLY OPERAND1 AND OPERAND2 ck ck KKK KEK KKK Ck Ck ck ck Sk Ck Ck ck Ck kk Ck ck ck kk Ck Ck ck ck ok kk ck ck ck kk Ck ck Sk ko Mk ko Sk Sk kA kv kx ko kock ok PUSH R5 R5 WILL HOLD THE ADDRESS MOV RESLO R5 THE RESLO REGISTER MOV amp amp MPY LOAD 1ST OPERAND DEFINES ADD UNSIGNED MULTIPLY MOV amp OPER2 amp OP2 LOAD 2ND OPERAND AND START ULTIPLICATION ck ck ck kk kk ck ck kk Ck ck ck kk Ck Ck ck Ck kk Ck kk kk Ck Ck ck ck ck kk ck ck ck kk Ck ck ck ko Mk ko Sk kc k ko ko ko kocko k is EXAMPLE TO ADD THE RESULT OF THE HARDWARE ULTIPLICATION THE RAM DATA 64 5 KKK KKK KKK ck ck ck kk kk ck KKK Ck Ck ck KKK Ck ck ck kk Ck Ck ck ck ck kk ck ck ck kk Ck ck ck ko Mk ko Sk Sk
428. ontents CMP R7 R8 COMPARE R7 WITH R8 JNE TONI if different jump zh if equal continue MOV W MOV B Syntax Operation Description Status Bits Mode Bits Example Loop Example Loop Instruction Set Overview Move source to destination Move source to destination MOV src dst or MOV W 9 src dst MOV B src dst src gt dst The source operand is moved to the destination The source operand is not affected The previous contents of the destination are lost Status bits are not affected OscOff CPUOff and GIE are not affected The contents of table EDE word data are copied to table TOM The length of the tables must be 020h locations MOV EDE R10 Prepare pointer MOV 020h R9 Prepare counter MOV R10 TOM EDE 2 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter z 0 continue copying NS Copying completed The contents of table EDE byte data are copied to table TOM The length of the tables should be 020h locations MOV EDE R10 Prepare pointer MOV 020h R9 Prepare counter MOV B QR10 TOM EDE 1 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter z 0 continue copying Copying completed Instruction Set Description B 41 Instruction Set Overview NOP Syntax Operation Emulation Description Status Bits B 42 No operation NOP None MOV 0 R3 No operation is performed Th
429. or highest priority TAIV interrupt vector for flags CCIFG1 CCIFGx and TAIFG 10 6 4 1 0 Interrupt Vector The interrupt flag associated with capture compare register CCRO as shown in Figure 10 30 is set if the timer value is equal to the compare register value Figure 10 30 Interrupt Flag Capture EQUO Interrupt Service Requested CCRO Timer CAP Timer Clock IRACC Interrupt Request Accepted Capture compare register 0 has the highest Timer A interrupt priority and uses its own interrupt vector Timer A 10 29 Timer A Registers 10 6 4 2 Vector Word TAIFG CCIFG1 to CCIFG4 Flags The CCIFGx otherthan CCIFGO and TAIFG interrupt flags are prioritized and combined to source a single interrupt as shown in Figure 10 31 The interrupt vector register TAIV shown in Figure 10 32 is used to determine which flag requested an interrupt Figure 10 31 Schematic of Capture Compare Interrupt Vector Word CCIFG1 CMP1 Timer Clock CCI2 EQ2 CMP2 Timer Clock Interrupt Service Request gt CCI3 EQ3 Priority and Vector Word Timer Clock Generator Interrupt Vector Address Figure 10 32 Vector Word Register 15 0 rewa o 0 0 r 0 rO 0 10 rO roO ro r0 rO 0 rO rO r r TAIV 12Eh The flag with the highest priority generates a numb
430. or x is O to 15 15 8 5 ADC12 Interrupt Vector Register ADC12IV The 12 bit ADC has one interrupt vector to assist the handling of the 18 possible interrupt flags Each of the 18 interrupt flags is prioritized and a unique vector word is generated according to the highest pending interrupt The priorities and corresponding vector word values are shown in Table 15 3 Overflow flag ADC12OVIFG has the highest priority followed by timing overflow flag ADC12TOVIFG and then by the interrupt flags for each conversion memory register ADC121FG 0 to ADC12IFG 15 The highest pending interrupt flag generates a number from 0 no interrupt is pending to 36 This encoded number can be added to the program counter to automatically enter the software routine for handling each specific interrupt see software example section 15 8 5 1 An interrupt request is immediately generated if an interrupt flag is pending ADC121Vz0 if the corresponding interrupt enable bit ADC12OVIE ADC12TOVIE or ADC12IE x is set and if the general interrupt enable bit GIE is set When an interrupt request is generated the service is requested by the highest priority interrupt that is enabled ADC12 15 37 ADC12 Control Registers It is important to note that ADC12OVIFG and ADC12TOVIFG are reset automatically when either is the highest pending interrupt and the ADC12IV register is accessed For example if both are pending simultaneously ADC120OVIFG will be reset automatic
431. ormance The conversion principle is identical to the one described in the previous section Figure 14 9 Two Independent Temperature Measurement Systems a o _ 0 VcC 0 1 2CA Rimess Caps cao 2 0 Input of gt i 6 1 r limer 1 0 0 CA1 1 2 1 R2 meas R2 ret CAREF e CARSEL __1 VCAREF UIN 0 25 Comparator A 14 13 Comparator A in Applications In Figure 14 10 the active signal paths are shown when the upper independent system is selected for conversion This example uses the 0 25 internal reference and shows the software selectable RC filter as active Figure 14 10 Temperature Measurement Via Temperature Sensor H meas p 0 2 F 2 e g Capture CAO o Input of e mn 9 1 0 ES 0 7 CA1 P2CA1 CAREF CARSEL O 1 o VCAREF em 1 e 0 25x 14 14 Comparator A in Applications Figure 14 11 shows the active signal paths for the lower independent system This example uses the 0 25 internal reference and shows the software selectable RC filter as active Figure 14 11 Temperature Measurement Via Temperature Sensor R2meas OV Vcc
432. ory 4 3 Internal ROM Organization 4 3 Internal ROM Organization Various sizes of ROM OTP masked ROM EPROM or FLASH are available within the 64 kB address space as shown in Figure 4 4 The common address space is shared with SFRs peripheral module registers data and code memory The SFRs and peripheral modules are mapped into the address range starting with 0 and ending with 01FFh The remaining address space 0200h to OFFFFh is shared by data and code memory The start address for ROM depends on the amount of ROM present The interrupt vector table is mapped into the the upper 16 words of ROM address space with the highest priority interrupt vector at the highest ROM word address OFFFEh See the individual data sheets for specific memory maps Figure 4 4 ROM Organization OFFFEh vx Vectors Vectors Vectors i d OFO00h _ OEFFFh e e e O0DOO0h OCFFFh e e e 08000h 4 3 1 Processing of ROM Tables 4 4 The MSP430 architecture allows for the storage and usage of large tables in ROM without the need to copy the tables to RAM before using them This ROM accessing of tables allows fast and clear programming in applications where datatables are necessary This offers the flexible advantages listed below and saves on ROM and RAM requirements To access these tables all word and byte instructions can be used ROM storage of an output programmable logic array for display character convers
433. ot taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A D converter One way to avoid ground loops is to use a star connection scheme for AVgg shown in Figure 15 26 This way the ground current or reference currents do not flow through any common input leads eliminating any error voltages In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result The ripple can become more dominant by reducing the value of the conversion voltage range Vn therefore reducing the value of the LSB and the noise margin Thus a clean noise free setup becomes even more important to achieve the desired accuracy Adding carefully placed bypass capacitors returned to the respective ground planes can help in reducing ripple in the supply current and minimizing these effects Figure 15 26 A D Grounding and Noise Considerations 10 50 1 uF Jl 0 1 uF ADC12 15 42 Chapter 16 ADC10 The ADC10 10 bit analog to digital converter is a high speed versatile ana log to digital converter implemented on the MSP430x11x2 and MSP430x12x2 This chapter discusses the ADC10 and how to use it Topic Page no iintroductiongs a E 16 2 16 2 ADC10 Description and Operation
434. ounter pointed to by R13 is added to a 32 bit counter eleven words 20 2 2 2 above the pointer in R13 ADD R13 20 R13 ADD LSDs with no carry in ADDC 13 20 13 ADD MSDs with carry resulting from the LSDs The 24 bit counter pointed to by R13 is added to a 24 bit counter eleven words above the pointer in R13 ADD B R13 10 R13 ADD LSDs with carry in ADDC B 13 10 13 ADD medium Bits with carry ADDC B 13 10 13 ADD MSDs with carry resulting from the LSDs Instruction Set Description B 11 Instruction Set Overview AND W AND B Syntax Operation Description Status Bits Mode Bits Example Example Source AND destination Source AND destination AND src dst or AND W src dst AND B src dst src AND dst dst The source operand and the destination operand are logically ANDed The result is placed into the destination N Setif result MSB is set reset if not set Z Setif result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Reset OscOff CPUOff and GIE are not affected The bits set in R5 are used as a mask OAA55h for the word addressed by TOM If the result is zero a branch is taken to label TONI MOV 0AA55h R5 Load mask into register R5 AND R5 TOM mask word addressed by TOM with R5 JZ TONI ae Result is not zero or AND 0AA55h TOM JZ TONI The bits of mask 40A5h are logically ANDed with t
435. p and conversion start None shown for this example EERE KERR AIR KK BRK RR ERE RRR SKK col ne iK SEO BER e EER c KK RR interrupt Service Routine for the ADC10 DTC ADC1ODTC ISR The transfers are now complete The ISR can return the CPU to active mode operate on the data or whatever the application requires RETI 16 8 3 2 Two Block Transfer Software Example With Continuous Mode Enabled Initialize ADC10 DTC for two block transfer Transfer 8 conversion results to each of the blocks The first block is 220h to 22Eh The Second block is 230h to 23Eh DTC Setup OV B ADC1OTB ADC10CT amp ADCIODTCO OV B 08h amp ADC10DTCI OV 0220h amp ADC10SA EINT ING BNR IEA AI Mainloop Mainloop code would go here including 10 setup and conversion start None shown for this example i A M uc Acl uos Aa t ANNI A UE AA OS Interrupt Service Routine for the ADC10 DTC ADC10DTC_ISR MOV amp ADC10SA Rx Start address of Blockl is in Rx BIT B SADCIOB1 amp ADCIODTCO Test which block is loaded JC Block 1 If set Block 1 is full Block 2 ADD 2Xn Rx Adjust SA w offset 2n SA in Rx Operate on the data Here code would either process the data or move it to another location for future processing RETI
436. p down mode the interrupt flags CCIFGO and TBIFG are set at equal time intervals Figure 11 15 Each flag is set only once during the period but they are separated by 1 2 the timer period CCIFGO is set when the timer counts from TBCLO 1 to TBCLO and TBIFG is set when the timer completes counting down from 0001h to 0000h Each flag is capable of producing a CPU interrupt when enabled Figure 11 15 Up Down Mode Flag Setting Timer Clock Timer Up Down Set CCIFGO Set TBIFG 11 3 4 1 Timer In Up Down Mode Changing the Value of Period Register TBCLO Immediate Mode for TBCLO Changing the period value while the timer is running in up down mode and the transfer mode for TBCLO is immediate is even trickier than in up mode Like in up mode the phase of the timer clock when TBCLO is changed affects the timer s behavior Additionally in up down mode the direction of the timer also affects the behavior If the timer is counting in the up direction when the new period is transferred from CCRO to TBCLO the conditions in the up down mode are identical to Timer B 11 13 Timer Modes those in the up mode See Section 11 3 2 1 for details However if the timer is counting in the down direction when TBCLO is updated it continues its descent until it reaches zero The new period takes effect only after the counter finishes counting down to zero See Figure 11 16 Note If TBCLO gt TBR may the counter operates as i
437. path driven by the comparator output is constantly charged and discharged O The software receives constant requests for service either via interrupt service requests or after successful polling of CAOUT or CAIFG Comparator A in Applications Figure 14 22 shows how to add hysteresis to the comparatorto prevent output oscillation Figure 14 22 Use CAOUT at an External Pin to Add Hysteresis to the Reference Level 1 It Feedback is Possible 2 5 R1 R2 CAO 1 4 e b o 1 Reference 0 Voltage 5 6 0 1 amp cat Set 2 1 pc CAIFG t 2yus 0 Signal 59 41 Wy Voltage CAON 32 10 CAREF CARSEL RN 0 5x VCG o 2 1 0 25 x Vcc 3 Adding hysteresis can only be done if CAOUT is available externally Refer to the device s data sheet to determine if CAOUT is available at an external pin The hysteresis can be calculated as follows E H2 Vinyst Hr cc Comparaltor 14 23 14 24 Chapter 15 ADC12 The ADC12 12 bit analog to digital converter is a high speed extremely versatile analog to digital converter implemented 5 430 13 and MSP430x14x devices This chapter discusses the ADC12 and how to use it Topic Page i5 iuintroductiongs 15 2 15 2 ADC Description and Operation 15 4 15 3 Analog Inputs and Multiplexer
438. period is written during a low phase of the timer clock then the timer continues to increment with the old period for one more clock cycle before adopting the new period and rolling to zero or beginning counting down This is shown in Figure 10 8 Figure 10 7 New Period Old Period Timer CCROold 2 Register CCROnew 3 ORR ESR RRR RID 5555550 Figure 10 8 New Period lt Old Period 10 8 Timer Timer Register CCROold 5 Register CCROold 5 5 CCROnew 2 CCROnew 2 4 4 3 3 2 2 1 1 0 0 011213141510112 314011201 1201 CCRO CCRO 5 x 2 Timer Clock h Timer Clock N Timer Timer X n n 1 Oornt X 1 1 T T CCRO CCRoldX CCRnew CCRO CCRold X CCRnew mad Load New CCRO Load New CCRO During High Phase of Clock During Low Phase of Clock T Up mode 0 up down mode n 1 T Up mode 0 up down mode n Timer Modes 10 3 3 Timer Continuous Mode The continuous mode is used if the timer period of 65 536 clock cycles is used for the application A typical application of the continuous mode is to generate multiple independent timings In continuous mode the capture compare register CCRO works in the same way as the other compare registers The capture compare registers and dif
439. ples Timer in Continuous Mode 11 27 Output Examples Timer in Up Down Mode 1 11 28 Timer B Control Register TBCTL 11 29 TER REBIO NEYAQE es 11 32 Capture Compare Control Register CCTLx 11 32 Capture Compare Interrupt Flag 11 35 Schematic of Capture Compare Interrupt Vector Word 11 36 Vector Word Register 11 36 Block Diagram of USART 12 2 Block Diagram of USART UART Mode 12 3 Asynchronous Frame 12 4 Asynchronous Bit Format Example for n or n 1 Clock Periods 12 4 Typical Baud Rate Generation Other Than 5 430 12 5 MSP430 Baud Rate Generation Example for n or n 1 Clock Periods 12 6 Idle Line Multiprocessor 12 7 USART Receiver Idle Detect 12 8 Double Buffered WUT and TX Shift 12 8 USART Transmitter Idle Generation
440. pped by software This is useful for example in an application that must take advantage of the buffering supplied by the conversion memory but requires more than 16 repeated conversions of a single channel In this instance the user should set up each memory control register identically specifying the same channel and reference s for each conversion and all Conversion Modes EOS bits must be cleared Once the converter is started it will continue to run until stopped by software 15 5 Conversion Modes The ADC12 has four conversion modes Single channel single conversion Lj Single channel repeated conversions Sequence of channels single sequence Sequence of channels repeated sequence Each mode is summarized in Table 15 2 and described in detail in the follow ing sections Table 15 2 Conversion Modes Summary CONVERSION MODE Single channel Sequence of channels Repeat single channel Repeat sequence of channels CONSEQ 00 01 10 OPERATION Single conversion from a selected channel X CStartAdd points to the conversion start address Result is in ADC12MEMx interrupt flag is ADC121FG x Channel INCH and reference voltage Sref are selected in ADC12MCTLx A sequence of channels is converted x CStartAdd points to the conversion start address The last channel in a sequence y is marked with EOS 1 ADC12MCTLx 7 all other EOS bits ADC12MCTLx ADC12MCTL x 1 ADC12MCTL
441. program continues at label EDE CMP R7 R6 R6 R7 compare on signed numbers JL EDE Yes R6 lt R7 proceed B 36 JMP Syntax Operation Description Status Bits Hint Instruction Set Overview Jump unconditionally JMP label PC 2 x offset PC The 10 bit signed offset contained in the instruction LSBs is added to the program counter Status bits are not affected This one word instruction replaces the BRANCH instruction in the range of 511 to 512 words relative to the current program counter Instruction Set Description B 37 Instruction Set Overview JN Jump if negative Syntax JN label Operation if N 2 1 PC 2x offset PC if N 2 0 execute following instruction Description The negative bit N of the status register is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If N is reset the next instruction following the jump is executed Status Bits Status bits are not affected Example The result of a computation in R5 is to be subtracted from COUNT If the result is negative COUNT is to be cleared and the program continues execution in another path SUB R5 COUNT COUNT R5 COUNT JN L 1 If negative continue with COUNT 0 at PC L 1 pe Continue with gt 0 L 1 CLR COUNT B 38 JNC JLO Syntax Operation Description Status Bits Example ERROR CONT Example
442. pture Capture Read and No Capture Capture Clear Bit COV in Register CCTL Second Capture Taken COV 1 Idle Overflow bit COVx is reset by the software as described in the following example Software example for the handling of captured data looking for overflow condition The data of the capture compare register CCRx are taken by the software and immediately with the next instruction the overflow bit is tested and a decision is made to proceed regularly or with an error handler CCRx Int hand Sere Start of handler Interrupt MOV amp CCRx RAM Buffer BIT COV amp CCTLx JNZ Overflow_Hand Overflow_Hand BIC COV amp CCTLx reset capture overflow flag get back to lost Synchronization RETI ee OV ETT zt Note Capture With Timer Halted The capture should be disabled when the timer is halted The sequence to follow is stop the capture then stop the timer When the capture function is restarted the sequence should be start the capture then start the timer Timer Modes 10 4 1 1 Capture Compare Block Capture Mode Capture Initiated by Software In addition to internal and external signals captures can be initiated by software This is useful for various purposes such as To measure time used by software routines To measure ti
443. r baud rate y ox 6 6 x UxBR 4 1 6 x 100 3 13 x 100 3 42 1 Stop bit 1 Error 96 0 x 100 1 37 BROLK Data bit D6 Error 96 Paud rate rate y 6 7 x UxBR 4 1 7 paud rate rate X 2x 1 6 11 x UxBR 7 1 11 x 100 1 1796 Stop bit 2 Error BRCLK USART Peripheral Interface UART Mode 12 31 12 32 Chapter 13 USART Peripheral Interface SPI Mode The universal synchronous asynchronous receive transmit USART serial communication peripheral supports two serial modes with one hardware configuration These modes shift a serial bit stream in and out of the MSP430 at a programmed rate or at a rate defined by an external clock The first mode is the universal asynchronous receive transmit UART communication protocol discussed in Chapter 12 the second is the serial peripheral interface SPI protocol Bit SYNC in control register UOCTL for UARTO and U1CTL for USART1 selects the required mode SYNC 0 UART asynchronous mode selected SYNC 1 SPI synchronous mode selected This chapter describes the SPI mode Topic Page 13 1 USART Peripheral Interface 13 2 13 2 USART Peripheral Interface SPI Mode 13 3 13 3 Synchronous Operation 13 4 13 4 Interrupt and Control Functions 13 9 13 5 Control and Status Register
444. r 6 10 Chapter 7 Basic Clock Module This chapter discusses the Basic Clock Module used in the MSP430x1xx families Topic Page 73 Basic Clock Modulen 222227 7 2 7 2 and XTZ O0scillators 222222222222 7 4 7 3 Digitally Controlled Oscillator DCO 7 10 7 4 Basic Clock Module Operating Modes 7 14 7 5 Basic Clock Module Control Registers 7 18 7 1 7T 1 Basic Clock Module The Basic Clock Module shown in Figure 7 1 follows the major targets of low System cost and low power consumption Using three internal clock signals the design engineer can select the best balance of performance and low power consumption The Basic Clock Module can be configured to operate without any external components with one external resistor with one or two external crystals with resonators or with clock sources using any combination of the above The Basic Clock Module is accessible to the CPU as a byte wide peripheral module Figure 7 1 Basic Clock Schematic DIVA LFXT1CLK e ACLK Auxiliary Clock 1 12 14 8 OscOff XTS LFXT1 Oscillator ACLKGEN SELM DIVM CPUOff gt lt 4 DCOMOD SMCLKGEN XOUT 1 Mc DENT E 9 Main System C
445. r LLLLLLL D AA Instruction Set Description B 3 Instruction Set Overview B 1 1 Instruction Formats The following sections describe the instruction formats B 1 1 1 Double Operand Instructions Core Instructions The instruction format using double operands as shown in Figure 1 consists of four main fields to form a 16 bit code L operational code field four bits op code source field six bits source register As L byte operation identifier one bit BW destination field five bits dest register Ad The source field is composed of two addressing bits and a four bit register number 0 15 The destination field is composed of one addressing bit and a four bit register number 0 15 The byte identifier B W indicates whether the instruction is executed as a byte B W 1 or as a word instruction B W 0 Figure B 1 Double Operand Instructions B 4 15 12 11 8 7 6 5 4 3 0 OP Code Source Register Destination Register Operational Code Field ADD W ADD B src dst src dst dst ADDC W ADDC B src dst src dst C dst AND W AND B src dst src and dst dst BIC W BIC B src dst not src dst dst BISL W BIS B src dst src or dst dst BIT W BITB srcdst src dst CMP W src dst dst src DADD
446. r speed computations or time measurements The timer value is copied into the capture register CCRx with the selected edge positive negative or both of the input signal Captures may also be initiated by software as described in section 10 4 1 1 If a capture is performed The interrupt flag CCIFGx located in control word CCTLx is set An interrupt is requested if both interrupt enable bits CCIEx and GIE set The input signal to the capture compare block is selected using control bits CCISx1 and CCISxO as shown in Figure 10 18 The input signal can be read at any time by the software by reading bit CCIx The input signal may also be latched with compare signal EQUx see SCCIx bit below when in compare mode This feature was designed specifically to support implementing serial communications with Timer A See section 10 7 for more details on using Timer A as a UART Figure 10 18 Capture Logic Input Signal CCISx1 CCISx0 CAPx M 0 Mp EQUx e 2o 0 0 I 0 Set CCIFGx GND j Synchronize 1 SCSx apture 0 0 Disabled 0 1 Positive Edge 1 O Negative Edge 1 1 Both Edges EN d egok A CCIx 10 14 The capture signal can also be synchronized with the timer clock to avoid race conditions between the timer data and the capture signal This is illustrated in Figu
447. r Mode 10 4 10 2 2 Clock Source Select and 10 5 10 2 3 Starting thie TIm Or s sucia Monet perd aa ease D CERO 10 6 10 3 Immer MOTOS aeai EEA erc ee Ree Rl ee RU Ce ee ur cues 10 7 10 3 1 Timer Stop Mode 10 7 10 3 2 Timer Up Mode 10 7 10 3 8 Timer Continuous Mode 10 9 10 3 4 Timer Up Down Mode 10 10 10 4 Capture Compare Blocks 10 13 10 4 1 Capture Compare Block Capture Mode 10 14 10 4 2 Capture Compare Block Compare Mode 10 18 10 5 The Output Unit een v e neon an bay tere ener ees 10 19 10 5 1 Output Unit Output 10 20 10 5 2 Output Control 10 21 10 5 3 Output Examples 10 22 10 6 Registers 10 24 10 6 1 Timer A Control Register TACTL 10 25 10 6 2 Timer A Register TAR 10 26 vii
448. r may be set at the same time as ADC 12SC However when any other trigger source is being used to start a sequence the ENC bit must be toggled between each sequence All additional incoming sample input signals will be ignored until the ENC bit is reset and set again The conversion mode may be changed after the conversion begins but before ithas completed and the new mode will take effect after the current sequence has completed See also the Switching between Conversion Modes section Conversion Modes If the conversion mode is changed after the sequence begins but before it has completed and the ENC bit is left high the sequence completes normally and the new mode takes effect after the sequence completes unless the new mode is single channel single conversion If the new mode is single channel single conversion the current sequence of channels stops proceeding when no sample and conversion is active or after an active sample and conversion is completed The original sequence may not be completed but all completed conversion results are valid See also the Switching Between Conversion Modes section If the conversion mode is changed after the sequence begins but before it has completed and the ENC bit is toggled then the original sequence completes normally and the new mode takes effect and is started after the original sequence completes unless the new mode is single channel single conversion lf the new mode is single channel
449. r pin mode is selected and a bus conflict stops an active master by applying a negative transition signal to pin STE FE is reset by a SWRST a system reset by reading the UxRXBUF or by an instruction Control and Status Registers 13 5 4 Baud Rate Select and Modulation Control Registers The baud rate generator uses the content of baud rate select registers UXBR1 and UxBRO shown in Figure 13 19 to generate the serial data stream bit timing The smallest division factor is two Figure 13 19 USART Baud Rate Select Register 7 0 mess TEE ET U1BRO 07Ch rw rw rw rw rw rw rw rw 7 0 wes TTT U1BR1 07Dh rw rw rw rw rw rw rw rw Baud rate BRCLK _ with UxBR UxBR1 UxBRO UxBR iXmi The maximum baud rate that can be selected for transmission in master mode is half of the clock input frequency of the baud rate generator In slave mode the rate is determined by the external clock applied to UCLK The modulation control register shown in Figure 13 20 is not used for serial synchronous communication It is best kept in reset mode bits mO to m7 0 Figure 13 20 USART Modulation Control Register 7 0 ee e e e eee U1MCTL 07Bh rw rw rw rw rw rw rw rw 13 5 5 Receive Data Buffer UORXBUF U1RXBUF The receive data buffer UxRXBUF shown in Figure 13 21 contains previous data from the receiver shift register UxRXBUF is cleared with a SWRST signal Reading UxRXBUF resets the receive error
450. r two blocks of n words Us ing two destination blocks enables software to process one block while conversion pro ceeds and the DTC fills the other block with conversion results 0 One block transfer mode The address range for the block is SA to SA 2n 2 1 Two blocks transfer mode The address ranges for the blocks are Block 1 SA to SA 2n 2 Block 2 SA 2n to SA 4n 2 ADC10 TET Data Transfer Control High Speed Conversion Support The ADC10DTC1 register bits define the number of transfers in each block 7 0 ADC10DTC1 n 049h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 n 0 No data transfer is enabled The DTC state machine remains in the reset state goes back to the reset state or stops operation when an active transfer operation is com pleted See also the state diagrams in Figures 16 17 and 16 19 110255 Data transfer is enabled and n defines the number of data transfers per block Note that a write to the ADC10SA register must be performed to start the DTC transfer even if the ADC10SA register contains the desired starting address value 16 8 2 2 Start Address Register for Data Transfer ADC10SA The start address for the DTC is contained in the ADC10SA register and is restricted to even address word aligned since the ADC10 data is word only data 15 0 PEOR Data Transfer Start Address SA rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw
451. ransmit buffer will not be transmitted Once the UTXE bit is set the data in the transmit buffer are immediately loaded into the transmit shift register and character transmission is started C O eee Note Writing to UXTXBUF UART Mode Data should never be written to transmit buffer UXTXBUF when the buffer is not ready UTIFG 0 and when the transmitter is enabled UTXE is set Otherwise the transmission may have errors aa Note Write to UXTXBUF Reset of Transmitter UART Mode Disabling the transmitter should be done only if all data to be transmitted has been movedtothe transmit shift register Data is moved from UTXBUF to the transmit shift register on the next bit clock after the shift register is ready MOV B amp U0TXBUF BIC B UTXE 0 amp ME2 If BITCLK MCLK then the transmitter might be stopped before the buffer is loaded into the transmitter shift register Interrupt and Enable Functions 12 4 3 USART Receive Interrupt Operation In the receive interrupt operation shown in Figure 12 14 the receive interrupt flag URXIFG is set or is unchanged each time a character is received and loaded into the receive buffer Erroneous characters parity frame or break error do not set interrupt flag URXIFG wh
452. rasitic effects and cross coupling on and between signal lines power supply lines and other parts of the system are responsible for this behavior see Figure 14 2 The comparator output oscillation reduces accuracy and resolution of the comparison result Selecting the output filter can reduce errors associated with comparator oscillation Figure 14 2 RC Filter Response at the Output of the Comparator 4 Terminal Terminal EE III Comparator Inputs Comparator Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT 14 2 5 The Voltage Reference Generator 14 4 The voltage reference generator is used to generate VcAnEr can be applied to either of the comparator input terminals Control bits CAREFO and CAREF1 control the output of the voltage generator Control bit CARSEL selects the comparator terminal to which VcAngr is applied If external signals are applied to the comparator input terminals the internal reference generator should be shut off to reduce current consumption The divider in the voltage reference generator can generate a fraction of the device s or a fixed transistor threshold voltage This threshold voltage tolerance is specified in the specific device s data sheet Ratiometric measurement principles that compare unknown values such as resistive or capacitive sensors with a known value such as a precision resistor or capacitor can use an
453. rce When using a particular analog input the corresponding ADC 10AE x bist must be set 7 0 ADC10AE ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 O4Ah AE7 6 AES 4 AE3 AE2 AE 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 5 0 7 ADC analog input enable 0 The ADC analog input is disabled 1 The ADC analog input is enabled 16 26 Data Transfer Control High Speed Conversion Support 16 7 3 Conversion Memory Register ADC10MEM One register ADC10MEM is loaded after a conversion is completed with uni polar binary ADC10MEM 01B4h ro ro ro ro ro ro rw rw rw rw rw rw rw rw rw rw or with 2 s complement data format 15 6 5 0 ADC10MEM MSB LSB 01B4h rw rw rw rw rw rw rw rw ro ro ro ro ro ro ro rw 16 8 Data Transfer Control High Speed Conversion Support The ADC10 includes data transfer control DTC logic DTC logic is used to automatically transfer the ADC10 conversion results to other memory loca tions typically RAM Often in microcontroller applications an end of conver sion flag or an interrupt flag is polled or an interrupt service request is used to handle the result of A D conversions With the DTC logic hardware of the ADC10 the conversion result can be automatically transferred to a selected destination No software intervention is required until the predefined amount of conversion data has been transferred The DTC logic of the
454. re 10 19 The bit SCSx in capture compare control register CCTLx selects the capture signal synchronization Figure 10 19 Capture Signal Timer Timer Modes Clock ae NNNM Timer CCIx Capture Set CCIFGx Applications with slow timer clocks can use the nonsynchronized capture signal In this scenario the software can validate the data and correct it if necessary as shown in the following example Software example for the handling of asynchronous capture signals The data of the capture compare register CCRx are taken by the software in the according interrupt routine F they are taken only after a CCIFG was set The timer clock is much slower than the system clock SMCLK CCRXx Int hand Data Valid RETI F amp CCRx amp TAR Data Valid amp TAR amp CCRx Start of interrupt handler Test if the data CCRX The data in CCRx is wrong use the timer data The data in CCRx are valid Overflow logic is provided with each capture compare register to flag the user if a second capture is performed before data from the first capture was read successfully Bit COVx in register CCTLx is set when this occurs as shown in Figure 10 20 Timer A 10 15 Timer Modes Figure 10 20 Capture Cycle 10 16 Idle Capture Capture Read No Capture Taken Read Taken Capture Capture Taken Ca
455. re 12 27 The baud rate generation error shown in Figure 12 28 in relation to the required ideal timing is calculated for each individual bit The relevant error information is the error relative to the actual bit not the overall relative error Figure 12 27 MSP430 Transmit Bit Timing i 01112 31 4 516 718 9 10111112 UU UU UU DU UU DU UD UU DU ti ltolt ts te ts te t te tojtiojtn TES Mar 570 6 j pj Spats ____ 2nd Stop Bit SP 1 Parity Bit PE 1 Address Bit MM 1 8th Data Bit Char 1 Figure 12 28 MSP430 Transmit Bit Timing Errors fee o du 8 amp a ttarget to ty tg tg 80 81 terror Mark URXD ST DO D7 PA 0 e t to Even small errors per bit relative errors can result in large cumulative errors They must be considered to be cumulative not relative The error of an individual bit can be calculated by n i n i 2 factual gt Error x 10096 rato Or Error baud rate i 1 x UxBR X i 1 x 100 BRCLK With baud rate Required baud rate BRCLK Input frequency selected for UCLK ACLK or MCLK i 0 for the start bit 1 for the data bit DO and so on UxBR Division factor in registers UXBR1 and UxBRO USART Peripheral Interface UART Mode 12 27 Baud Rate Considerations Example 12 3
456. re data CCRx The output period is double the timer period Output mode 5 Reset mode The output is reset when the timer value becomes equal to capture compare data CCRx It remains reset until another output mode is selected that controls the output Output mode 6 PWM toggle set mode The output is toggled when the timer value becomes equal to capture compare data CCRx It is set when the timer value becomes equal to CCRO Output mode 7 PWM toggle set mode The output is reset when the timer value becomes equal to capture compare data CCRx It is set when the timer value becomes equal to CCRO 10 20 Timer Modes 10 5 2 Output Control Block The output control block prepares the value of the OUTx signal which is latched into the OUTx flip flop with the next positive timer clock edge as shown in Figure 10 23 and Table 10 2 The equal signals EQUx and EQUO are sampled during the negative level of the timer clock as shown in Figure 10 23 Figure 10 23 Output Control Block OUTx OUTx Signal Output a Control Timer Clock 4 x Block 2 OMx1 OMx0 The timer is Incremented with the rising edge of the timer clock UNE eile Ne Timer W m V x V V V V V V mp A X ot KX Am A A TAR n EQUx CCRx n EQUO TAR 0 or TAR CCRO EQUO Delayed Used in Up Mode
457. redivider is not modified Lj The selected clock source is available until the cycle is completed The access to the flash memory module is restricted as long as BUSY is The conditions to read data from the flash memory with and without access violation are listed in Table 2 Table C 2 Conditions to Read Data From Flash Memory Flash Operation Instruction BUSY WAIT Data on Memory Data Action Fetch Bus MDB see Note 1 Byte word program No Access violation cycle see Note 2 Yes 3FFF JMP Nothing Flash read mode Memory contents from PC PC 2 applied address Page erase cycle No 3FFF Access violation see Note 3 Yes 3FFF JMP Nothing Mass erase cycle No 3FFF Access violation see Note 3 Yes 3FFF JMP Nothing All erase mass and in No 3FFF Access violation formation memory Yes 3FFF JMP Nothing Block write N A 3FFF Access violation and see Note 4 LOCK see Note 5 No 3FFF Nothing Yes 3FFF Access violation and LOCK see Note 5 Notes 1 Instruction fetch refers to the fetch part of an instruction and reads one word The instruction fetch reads the first word of instructions with more than one word The JMP instruction has one word The data fetched 8FFFh is used by the CPU as an instruction 2 Ensure that the programmed data does not result in unpredictable program execution such as destruction of executable code sequences 3 If the PC points to the memory
458. reduce overall pin count on MSP430 devices see the specific device data sheet to determine which other peripherals also use the device pins Control registers P1SEL and P2SEL are used to select the desired pin function l O port or other peripheral module Each register contains eight bits corresponding to each pin and each pin s function is individually selectable All bits in these registers are reset by the PUC signal The bit definitions are Bit 0 Port P1 or P2 function is selected for the pin Bit 1 Other peripheral module function is selected for the pin Ports P1 P2 Note Function Select With P1SEL P2SEL The interrupt edge select circuitry is disabled if control bit PnSEL x is set Therefore the input signal can no longer generate an interrupt When a port pin is selected to be used as an input to a peripheral module other than the I O port PNSEL x 1 the actual input signal to the peripheral module is a latched representation of the signal at the device pin see Figure 8 2 schematic The latch uses the PnSEL x bit as its enable so while PNSEL x 1 the internal input signal simply follows the signal at the pin However if the PnSEL x bit is reset then the output of the latch and therefore the input to the other peripheral module represents the value of the signal at the device pin just prior to the bit being reset 8 2 2 Port P1 Port P2 Schematic
459. reference currents do not flow through any common input leads eliminating any error voltages In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result The ripple can become more dominant by reducing the value of the conversion voltage range VR Vp therefore reducing the value ofthe LSB and the noise margin Thus a clean noise free setup becomes even more important to achieve the desired accuracy Adding carefully placed bypass capacitors returned to the respective ground planes can help in reducing ripple in the supply current and minimizing these effects Figure 16 25 A D Grounding and Noise Considerations 16 44 t mn Sx 0 1 uF t Y x 0 1 uF Appendix Peripheral File This appendix summarizes the peripheral file PF and control bit information into a single location for reference Each PF register is presented as arow of boxes containing the control or status bits belonging to the register The register symbol e g POIN and the PF hex address are to the left of each register Topic Page A Overview ue Cone A 2 A 2 Special Function Register of MSP430x1xx Family Byte Access A 3 3 Digitali O Byte ACCESS III mmm A 3 4 Basic Clock Registers Byte Access A 5 A 5 EPROM Control Regist
460. register either by reading it or by adding it directly to the PC CCIFG2 will be reset automatically After the RETI instruction of the interrupt service routine is executed the CCIFG3 flag will generate another interrupt Note Writing to Read Only Register TBIV Register TBIV should not be written to If a write operation to TBIV is performed the interrupt flag of the highest pending interrupt is reset Therefore the requesting interrupt event is missed Additionally writing to this read only register results in increased current consumption as long as the write operation is active 11 37 Timer B Registers 11 6 4 3 Timer Interrupt Vector Register Software Example Timer B7 11 38 The following software example describes the use of vector word TBIV of Timer and the handling overhead The numbers at the right margin show the necessary cycles for every instruction The example is written for continuous mode the time difference to the next interrupt is added to the corresponding compare register Software example for the interrupt part Cycles Interrupt handler for Capture Compare Module 0 The interrupt flag CCIFGO is reset automatically TIMMODO RETI Start of handler Interrupt latency 6 Interrupt handler for Capture Compare Modules 1 to 6 The interrupt flags CCIFGx and TBIFG are reset by hardware Only the flag with the highest priority responsible for the
461. registers of the Basic Clock are under full software control If clock requirements other than those of the default from PUC are necessary the Basic Clock can be configured or reconfigured by software at any time during program execution ACLKGEN from LFXT1 crystal resonator or external clock source and divided by 1 2 4 or 8 If no LFXTCLK clock signal is needed in the application the OscOff bit should be set in the status register SCLKGEN from LFXTCLK DCOCLK or XT2CLK x13x and x14x only and divided by 1 2 4 or 8 The SCG1 bit in the status register enables or disables SMCLK MCLKGEN from LFXTCLK DCOCLK or XT2CLK x13x and x14x only and divided by 1 2 4 or 8 When set the CPUOff bit in the status register enables or disables MCLK DCOCLK frequency is adjusted using the RSEL DCO and MOD bits The DCOCLK clock source is stopped when not used and the dc generator can be disabled by the SCGO bit in the status register when set XT2 oscillator sources XT2CLK 13 and x14x only by clearing the XT2Off bit User software can modify the Basic Clock to meet the system requirements at any time using the full MSP430 instruction set A few examples follow bis b 007h amp BCSCTL1 RSEL 7 mov b 081h amp BCSCTL1 XT20ff RSEL 1 bis b 4 070h amp BCSCTL1 ACLK high speed XTAL 8 bis b 008h amp BCSCTL2 SMCLK LFXT1 inc b amp DCOCTL Increase DCOCLK dec b amp D
462. rement destination mee se XR ADD B 2 dst SBC W dst Subtract carry from destination SUBC 0 dst SBC B dst Subtract carry from destination dE NE SUBC B 0 dst Logical instructions INV W dst Invert destination e ey em XOR 0OFFFFh dst INV B dst Invert destination ty XOR B 0FFFFh dst RLA W dst Rotate left arithmetically xU ZUM ADD dst dst RLA B dst Rotate left arithmetically T mS SA ADD B dst dst RLC W dst Rotate left through carry Te NS ADDC dst dst RLC B dst Rotate left through carry ADDC B dst dst Data instructions common use CLR W Clear destination 0 dst CLR B Clear destination MOV B 0 dst CLRC Clear carry bit 0 BIC 1 SR CLRN Clear negative bit 0 BIC 4 SR CLRZ Clear zero bit 0 BIC 2 SR POP dst Item from stack MOV SP dst SETC Set carry bit 1 BIS 1 SR SETN Set negative bit 1 BIS 4 SR SETZ Set zero bit 1 BIS 2 SR TSTLW dst Test destination Q0 1 CMP 0 dst TST B dst Test destination Q0 1 CMP B 0 dst Program flow instructions BR dst Branch to dst PC DINT Disable interrupt BIC 8 SR EINT Enable interrupt BIS 8 SR NOP No operation MOV 0h 0h RET Return from subroutine SP PC Instruction Set Description B 7 Instruction Set Overview B 2 Instruction Set Description This section catalogues and describes all core and emulated instructions in alphabetical order So
463. rent or averaged dc input currents due to input switching currents For a 12 bit converter the error in LSBs due to leakage current is Error LSBs 4 096 x uA of leakage current x of source resistance VR Vn For example a 50 nA leakage current with a 10 kO source resistance and a 1 5 V Veer gives 1 4 LSBs of error These errors due to source impedance also apply to the output impedance of any external voltage reference source applied to Veper The output impedance must be low enough to enable the transients to settle within 0 2 ADCLK and generate leakage current induced errors of lt lt 1LSB See the Sampling section for more details on sample timing and sampling con siderations 15 3 3 Using the Temperature Diode To use the on chip temperature diode the user simply selects the analog input channel to 10 Any other configuration is done as if an external channel was selected including reference selection conversion memory selection etc Selecting the diode channel automatically turns on the on chip reference generator see Figure 15 1 as a voltage source for the temperature diode However itdoes not enable the Vngr outputor affect the reference selections for the conversion so reference selections are the same as with any other channel See the device data sheet for the temperature diode specifications ADC12 ee Conversion Memory 15 4 Conversion Memory 15 8 A typical approach in single ch
464. ries with as shown in Figure 14 21 Vref Votfset VCAO Vref Voffset Figure 14 21 Offset Voltage of the Comparator CAEX 1 e g Capture Input of r Timer A Vref 7 1 Finally calculate from the below formulas offset N1 Rycag X Cx In V X fosc V eV N2 Rycap X C x In lt 01881 CC This leads to agonia Vottset Yoo X CC Mae timer counts Comparator A 14 21 Comparator A in Applications 14 4 7 Compensating for the Offset Voltage of Comparator A Another way to improve the accuracy is to compensate for the effect of input offset voltage without actually measuring it When CAEX 0 the Voffset is in series with Vref Vcao Vref Voffset When CAEX 1 the Voffset is in series with Vref Voffset Vref Vottset Adding the result of two conversions one with each input configuration and dividing by two will cancel the effect of the offset voltage Voao Vret Vottset Vret Vottset N2 _ Conversion without offset Timer count 2x 2 V ref 14 4 8 Adding Hysteresis to Comparator A 14 22 When the voltage level applied to the terminal is close to the voltage level at the terminal the output of the comparator may oscillate This can cause the following two situations The current consumption increases since the signal
465. rupt Seven registers are used to control the port I O pins see Section 8 2 1 Ports P1 and P2 are connected to the processor core through the 8 bit MDB and the MAB They should be accessed using byte instructions in the absolute address mode Figure 8 1 Port P1 Port P2 Configuration MDB n 1 020h n 2 028h 1 021 Direction Register n 2 029h PnDIR n 1 022h n 2 02Ah 1 023h Interrupt Edge Select n 2 02Bh PnIES Interrupt Enable PnIE R W Function Select PnSEL n 1 026h n 2 02 MSB LSB Pn 7 0 Digital I O Configuration 8 3 Ports P1 P2 8 2 1 Port P1 Port P2 Control Registers The seven control registers give maximum digital input output configuration flexibility All individual I O bits are independently programmable Lj Any combination of input output and interrupt condition is possible 1 Interrupt processing of external events is fully implemented for all eight bits of ports P1 and P2 The seven registers for port P1 and the seven registers for port P2 are shown in Table 8 1 and Table 8 2 respectively Table 8 1 Port P1 Registers Short Register Register Form Type Address Initial State Input Read only 020h Output P1OUT Read write 021 Unchanged Direction P1DIR Read write 022h Reset Interrupt flags P1IFG Read write 023h Reset Interrupt edge select P1IES Read write 024h Unchanged Interrupt enable P1IE Read write 025h Res
466. rupt control The WDT interrupt flag WDTIFG located in IFG1 0 initial state is reset The WDT interrupt enable WDTIE located in IE1 0 initial state is reset When using the watchdog mode the WDTIFG flag is used by the reset interrupt service routine to determine if the watchdog caused the device to reset If the flag is set then the Watchdog Timer initiated the reset condition either by timing out or by a security key violation If the flag is cleared then the PUC was caused by a different source See chapter 3 for more details on the PUC and POR signals When using the Watchdog Timer in interval timer mode the WDTIFG flag is set after the selected time interval and a watchdog interval timer interrupt is requested The interrupt vector address in interval timer mode is different from that in watchdog mode In interval timer mode the WDTIFG flag is reset automatically when the interrupt is serviced The WDTIE bit is used to enable or disable the interrupt from the Watchdog Timer when it is being used in interval timer mode Also the GIE bit enables or disables the interrupt from the Watchdog Timer when it is being used in interval timer mode 9 1 3 Watchdog Timer Operation The WDT module can be configured in two modes watchdog and the interval timer modes 9 1 3 1 Watchdog Mode When the WDT is configured to operate in watchdog mode both a watchdog overflow and a security violation trigger the PUC signal whic
467. s 13 15 13 1 13 1 USART Peripheral Interface The USART peripheral interface connects to the CPU as a byte peripheral module It connects the MSP430 to the external system environment with three or four external pins Figure 13 1 shows the USART peripheral interface module Figure 13 1 Block Diagram of USART Receive Buffer U1RXBUF or UORXBUF Receive Status SYNC RXE Listen MM SYNC Leho SOMI Receive Shift Register 0 49 gt URXD SSEL1 SSELO SYNC a 0 Baud Rate Generator 0 UCLKI ES STE ACLK 2 Baud Rate Register lt _ SMCLK o 3 U1BR or UOBR SMCLK o o gt Boum UTXD Ir 5 gt Baud Rate Generator UCLKS Transmit Shift Register 4 5 SIMO OX 207 TXWake CKPH SYNC Transmit Buffer U1TXBUF or UOTXBUF UCLKI Clock Phase and Polarity UCLKS 13 2 13 2 USART Peripheral Interface SPI Mode The USART peripheral interface is a serial channel that shifts a serial bit stream of 7 or 8 bits in and out of the MSP430 The SPI mode is chosen when control bit SYNC in the USART control register UOCTL for UARTO and U1CTL for USART1 is set 13 2 1 SPI Mode Features The features of the SPI mode are Supports three pin and four pin SPI operations via SOMI SIMO UCLK and STE Master or slave mode Separate shift registers for receive UxRXBUF and transmit UXTXBUF Dou
468. s are connected to signal power or ground level Otherwise floating levels may cause unexpected interrupts and current consumption may increase 14 2 2 Input Multiplexer Control bit CAEX controls the input multiplexer to select which input signals are connected to the comparator s and terminals Additionally when the comparator terminals are exchanged the output signal from the comparator is inverted This allows the user to determine or compensate for the comparator offset 14 2 3 The Comparator The comparator compares the analog voltages at the and input terminals If the terminal is more positive than the terminal the comparator output will be high note that the value of signal CAOUT also depends on the value of CAEX The comparator can be switched on or off using control bit CAON The comparator should be switched off when not in use to stop its current consumption When the comparator is switched off the output is low note that the value of CAOUT still depends on the value of CAEX even when the comparator is off 14 2 4 The Output Filter The output of the comparator can be used with or without internal filtering When control bit CAF is set the output is filtered with an chip RC filter The filter is bypassed when CAF is reset Comparator_A 14 3 Comparator A Description A comparator output will oscillate if the voltage difference across the input terminals is small Internal and external pa
469. sed Operation Move the immediate constant 45h which is contained in the word following the instruction to destination address TONI When fetching the source the program counter points to the word following the instruction and moves the contents to the destination Comment Valid only for a source operand Example MOV 45h TONI Before After Address Register Address Register Space Space OFF18h PC OFF16h 01192h OFF16h 01192h OFF14h 00045h OFF14h 00045h OFF12h 040B0h PC OFF12h 040BOh OFF16h 010AAh 01192h 010AAh 010A8h 01234h 010A8h 00045h 5 14 Addressing Modes 5 2 8 Clock Cycles Length of Instruction The operating speed of the CPU depends on the instruction format and addressing modes The number of clock cycles refers to the MCLK 5 2 8 1 Format l Instructions Double Operand Table 5 12 describes the CPU format l instructions and addressing modes Table 5 12 Instruction Format and Addressing Modes Address Mode No of Length of Example As Ad Cycles Instruction 00 Rn 0 Rm 1 MOV R5 R8 0 PC 2 BR R9 00 Rn 1 x Rm ADD 5 3 6 1 EDE XOR 8 1 amp EDE MOV R5 amp EDE 01 0 3 MOV 2 R5 R7 01 EDE AND EDE R6 01 amp EDE MOV amp EDE R8 01 x Rn 1 x Rm 6 ADD 3 4 6 9 01 EDE 1 TONI 01 amp EDE 1 amp TONI CMP EDE TONI MOV 2 R5 amp TONI ADD EDE amp TONI 10 Rn 0 Rm 2 AND R4 R5 10 QRn 1 5
470. selectable for 8 10 12 or 16 bit operation Timer B Operation Figure 11 4 Schematic of Clock Source Select and Input Divider SSEL1 SSELO TBCLK 9 9 73 INCLK o 3J Input Divider 0 16 Bit Timer Clock ID1 IDO POR CLR 0 0 Pass 0 1 1 2 1 0 1 4 1 1 1 8 11 2 4 Starting the Timer The timer may be started or restarted in a variety of ways m Release Halt Mode The timer counts the selected direction when a timer mode other than stop mode is selected with the bits Halted by TBCLO 0 restarted by TBCLO gt 0 when the mode is either up or up down When the timer mode is selected to be either up or up down the timer may be stopped by loading 0 in compare latch 0 TBCLO via capture compare register CCRO The timer may then be restarted by loading a nonzero value to TBCLO In this scenario the timer starts incrementing in the up direction from zero Setting the CLR bit in TBCTL register Setting the CLR bit in the TBCTL register clears the timer value and input clock divider value The timer increments upward from zero with the next clock cycle as long as stop mode is not selected with the bits TBR is loaded with 0 When the counter TBR register is loaded with zero with a software instruction the timer increments upward from zero with the next clock cycle as long as stop mode is not selected with the MCx bits Timer B 11 7 Timer Modes 11 3 Timer Modes 1
471. selected by the SHS bits triggers the sampling timer with its rising edge The sampling timer then generates the sample timing The sampling time is programmable by the SHTO or SHT1 bits located in ADC12CTLO When conversion memory registers ADC12MEMO to ADC12MEM7 are selected to store the conversion result s the SHTO bits are used to program the sampling time When conversion memory registers ADC12MEM8 to ADC12MEM15 are selected for the conversion data the SHT1 bits are used to program the sampling timing Therefore it is possible to program two different sampling times for a sequence of conversions by using both upper and lower conversion memory registers in the sequence This feature is useful when different external source impedance conditions exist and require different sample timings Sampling In pulse sampling mode sampling time is a multiple ofthe ADC12CLK x4 and is calculated by tsample 4 x tapc42cLk X SHTx SHTx is determined by bits SHTO or SHT1 see table in Control Registers ADC12CTLO and ADC12CTL 1 section The sampling signal SAMPCON remains in the sampling state high for the synchronization time and the selected sample time tsample as shown Figure 15 17 The conversion takes 13 x ADC12CLK cycles tconyer It is important to note that after a sample and conversion cycle has been triggered by the sample input signal additional triggers via a rising edge on the sample input signal will be missed ig
472. sensing of UART frame start condition Use the lowest input clock frequency for the required baud rate Support multiprocessor modes to reduce use of MSP430 resources 12 6 1 Receive Start Operation From UART Frame The most effective use of start detection in the receive path is achieved when the baud rate clock runs from SMCLK In this configuration the MSP430 can be put into a low power mode with SMCLK disabled The receive start condition is the negative edge from the signal on pin URXD Each time the negative edge triggers the interrupt flag URXS it requests a service when enable bits URXIE and GIE are set This wakes the MSP430 and the system returns to active mode supporting the USART transfer Figure 12 23 Receive Start Conditions SYNC Valid Start Bit d URXS Receiver Collects Character URXSE e From URXD CA UU ETAT PE URXIE Request_ BRK Interrupt_Service LIII URXWIE RXWake e SWRST PUC UxRXBUF Read J URXSE IRQA Three character streams do not set the interrupt flag URXIFG Erroneous characters URXEIE 0 Address characters URXWIE 1 Invalid start bit detection The interrupt software should handle these conditions USART Peripheral Interface UART Mode 12 23 Utilizing Features of Low Power Modes 12 6 1 1 Start Conditions
473. set 09600h Ensure that neither Watchdog Timer nor sinterrupts nor Low Power Modes may corrupt proper execution RAM2FLASH MOV Start_Ptr Rx MOV Ptr Ry MOV FWKEY amp FCTL3 Test Busy1 BIT BUSY amp FCTL3 JNZ Test 1 Set Pointer for Start and End Clear Lock Bit Test WAIT1 BIT WAIT amp FCTL3 JNE Test WAIT1 Rx Ry JZ End Seg Write BIT 03Fh Rx JNZ Test_Wait1 Block border yes Test Wait2 BIT WAIT amp FCTL3 JZ Test_Wait2 MOV FWKEY amp FCTL1 JMP Test_busy1 End_Seg_Write MOV FWKEY amp FCTL1 Test_Busy2 BIT BUSY amp FCTL3 JNZ Test Busy2 FXKEY LOCK amp FCTL3 no End of Block Write MOV FWKEY WRT BLKWRT amp FCTL3 Clear lock bit Flash busy BLKWRT ended Block write All data programmed Program data in this example one byte MOV B Rx Flash_Start_Ptr Start_ptr 1 Rx Block border Test if data written Stop block write Block write ends if busy 0 All data are programmed Stop block write Block write ended Change Lock bit to 1 Flash Memory C 25 Flash Memory Access via JTAG and Software C 5 3 4 Example Erase Flash Memory Segment or Module via Software Execution Outside This Flash Module The following sequence can be used to erase a segment or mass erase of segments Erase or Mass Erase BIC FWKEY LOCK amp FCTL3 Reset lock bit Test_Busy1 BIT BUSY amp FCTL3
474. shown in Figure 12 20 ensures proper timing generation with the UXBRO and UxBR1 even with crystal frequencies that are not integer multiples of the required baud rate Figure 12 20 USART Modulation Control Register 7 0 UOMCTL 073h U1MCTL 07Bh m7 m6 m5 m4 m3 m2 m1 0 rw rw rw rw rw rw rw rw The timing of the running bit is expanded by one clock cycle of the baud rate divider input clock if bit mj is set Each time a bit is received or transmitted the next bit in the modulation control register determines the present bit timing The first bittime in the protocol the start bit time is determined by UxBR plus m0 the next bit is determined by UxBR plus m1 and so on The modulation sequence is m0 m1 m2 m3 m4 m5 m6 m7 m0 m2 USART Peripheral Interface UART Mode 12 21 Control and Status Registers 12 5 5 Receive Data Buffer UORXBUF U1RXBUF The receive data buffer shown in Figure 12 21 contains previous data from the receiver shift register Reading the receive data buffer resets the receive error bits the RXWake bit and the interrupt flag URXIFG Figure 12 21 USARTO Receive Data Buffer UORXBUF U1RXBUF 7 0 UORXBUF 076h r r r r r r r r In seven bit length mode the MSB of the UxRXBUF is always reset The receive data buffer is loaded with the recently received character as described in Table 12 5 when receive and control conditions are true Table 12 5
475. single conversion then the original sequence stops when no sample and conversion is active or after an active sample and conversion is completed or when the ENC bit is reset whichever comes first Then the single conversion begins when the ENC bit is set again See also the Switching Between Conversion Modes section Figure 15 7 ENC Does Not Effect Active Sequence ENC SAMPCON and ADC128C ADC12SC reset ADC12SC set ADC12SC reset ADC12SC set ADC12SC reset may be set together starts conversion starts sampling starts conversion starts sampling starts conversion vYvvvvvv T irrrrrrrrrrrrrmnrrrrrrrrrrrrrrrrrrri TTTTTTTTITTTTTTA TTTTTTTTTTTTTTTT UU Un nt Sample Sample Sample Sample Sample it gt lt gt gt gt lt gt lt Single Conversion Single Conversion Single Conversion Single Conversion Single Conversion Time Time Time Time Time Single Period gt Single Period f Single Period Single Period of Sequence of Sequence of Sequence of Sequence Peri f n Next Peri f n le eriod of Sequences gt lt ext Period of Sequences S First
476. ss of the register where all port bits are read P1IFG is the address of the register where all interrupt events are latched MaskOK PUSH B amp 1 BIC B SP amp P1IFG Reset only accepted flags EINT Preset port 0 interrupt flags stored on stack other interrupts are allowed BIT Mask SP JEQ MaskOK Flags are present identically to mask jump BIC Mask SP INCD SP Housekeeping inverse to PUSH instruction at the start of interrupt subroutine Corrects the stack pointer RETI Note Enable Interrupt The instruction following the enable interrupt instruction EINT is always executed even if an interrupt service request is pending when the interrupts are enable LLLLLL AIiISDUILA Instruction Set Description B 29 Instruction Set Overview INC W INC B Syntax Operation Emulation Description Status Bits Mode Bits Example B 30 Increment destination Increment destination INC dst or INC W dst INC B dst dst 1 dst ADD 1 dst The destination operand is incremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise V Set if dst contained O7
477. st dst OFFh C dst SUBC 0 dst SUBC B 0 dst The carry bit C is added to the destination operand minus one The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Reset if dst was decremented from 0000 to OFFFFh set otherwise Reset if dst was decremented from 00 to OFFh set otherwise V Set if initially 0 and dst 08000h Set if initially C 0 and dst 080h OscOff CPUOff and GIE are not affected The 16 bit counter pointed to by R13 is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 Subtract LSDs SBC 2 R12 Subtract carry from MSD The 8 bit counter pointed to by R13 is subtracted from a 16 bit counter pointed to by R12 SUB B R13 0 R12 Subtract LSDs SBC B 1 R12 Subtract carry from MSD Note Borrow Is Treated as a NOT The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 SETC Syntax Operation Emulation Description Status Bits Mode Bits Example DSUB Instruction Set Overview Set carry bit SETC 1 gt 5 1 SR The carry bit C is set N Not affected Z Not affected C Set V Not affected OscOff CPUOff and GIE are not affected Emulation of the decimal subtraction Subtract R5 from R6 decimally Assume that R5 3987 and R6 4137 ADD 6666h R5 Move content R5 from 0 9 to 6 0Fh R5 03987 6666 09FEDh IN
478. stal oscillator 3 3 2 1 Oscillator Fault Control in the Basic Clock System The oscillator fault signal is triggered when the LFXT1 oscillator is configured to run in HF mode butis not running stops running after being operational or is switched off The oscillator fault signal is also triggered under the same conditions for the XT2 oscillator present in some devices Note that a PUC signal can trigger an oscillator fault because the PUC switches the LFXT1 to LF mode therefore switching off the HF mode The PUC signal also switches off the XT2 oscillator The oscillator fault signal can be enabled to generate an NMI by bit OFIE in the SFRs The interrupt flag OFIFG in the SFRs can then be tested by the interrupt service routine to determine if the NMI was caused by an oscillator fault See Basic Clock Module chapter for more details on the operation of the crystal oscillators LFXT1 and XT2 3 4 Interrupt Processing The MSP430 programmable interrupt structure allows flexible on chip and external interrupt configurations to meet real time interrupt driven system requirements Interrupts may be initiated by the processor s operating conditions such as watchdog overflow or by peripheral modules or external events Each interrupt source can be disabled individually by an interrupt enable bit or all maskable interrupts can be disabled by the general interrupt enable GIE bit in the status register Whenever an interrupt is requested and th
479. ster CAPD Typically the comparator input and output functions are multiplexed with digital I O port pins to save pin count on a device Also slope A D applications often utilize multiple digital I O ports for charging and discharging to provide multiple channels of slope A D conversion In these multichannel applications a useful feature of the digital I O pins is the ability to disable the input buffer Typically all channels except the one being converted are disabled providing a high impedance input and avoiding current consumption caused by throughput current See section 14 4 1 The typical digital I O ports on MSP430 do not have the ability to disable the input buffer However on devices with the Comparator A the capability has been added and is controlled with the CAPD x bits Comparaltor 14 7 Comparator A Control Registers 14 8 The control bits 0 to CAPD 7 are initially reset enabling all the input buffers for the associated port The port input buffer is disabled if the according CAPD x bit is set See device data sheet for port associations The ability to disable the input buffer for the device pin applies to up to eight inputs of the associated digital I O port check device data sheet for implementation details For example the x11x1 devices have CA1 multiplexed on pin P2 4 and CAO multiplexed on pin P2 3 so the A is associated with port P2 On this device all input buffers assoc
480. t interrupt flag of Timer register counter CCIFG1 CCIFG2 CCIFG3 CCIFG4 0 Peripheral File Map A 15 Timer B Registers Word Access A 15 Timer B Registers Word Access 2 215 0 0190 Cap com control CCTL6f 018Eh Cap com control 018Ch Cap com control CCTL4T 018Ah Cap com control CCTL3f 0188h Cap com control CCTL2 0186h Cap com control CCTL1 0184h Cap com control CCTLO 0182h W rw 0 rw 0 rw 0 0 r W 0 0 0 0 0 0 0 0 0 0 0 0 0 w 0 0 CM60 CCIS61 CCIS60 Scse CLLD6 1 CLLD6 O rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw rw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 215 214 213 212 211 210 29 2 otgen 40 rw 0 rw 0 rw 0 rw 0 rw 0 rw rw Eee ncm 215 214 213 212 211 210 29 2 o19ch 700 0 rw 0 rw 0 rw 0 rw 0 rw w 214 213 212 211 210 29 28 oigan 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw rw epo edet 214 213 212 211 210 29 2 0198 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw rw prece EC 214 213 212 211 210 29 2 o196h 0 0 rw 0 rw 0 rw 0 rw 0 rw rw ete 214 213 212 211 210 29 2 0194h 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw rw EAS 214 213 212 211 210 29 2 0192h 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw rw Ce 214 213 212 211 210 2 n n w
481. t resistance MUX on resistance Cj Input capacitance TS Vc Capacitance charging voltage 11 The capacitance charging voltage is given by NM tc 1 Vo Vgl 1 z 1 Where Ri Zi te Cycle time The input impedance Zi is 1 at 3 0 V and is higher 2 at 1 8 V The final voltage to 1 2 LSB is given by S 2 Vc 1 2LSB Vs 8192 Equating equation 1 to equation 2 and solving for cycle time tc gives V MEL CM 3 Yg S ADC12 15 29 ADC12 Control Registers and the time to charge to 1 2 LSB minimum sampling time is ten 1 2 LSB Ry x Cj x In 8192 Where In 8192 9 011 Therefore with the values given the time for the analog input signal to settle is ten 1 2 LSB Rg 1 x Cj x 9 011 4 This time must be less than the sampling time If the pulse sampling mode is used the maximum ADC12CLK frequency is max f ADC12CLK 0172058 5 C This frequency must not exceed the maximum ADC12CLK frequency specified in the data sheet 15 8 ADC12 Control Registers Five control registers sixteen conversion memory registers and sixteen conversion memory control registers are used to configure the ADC12 Register Short Form Register Type Address Initial State control register 0 ADC12CTLO Read write 01A0h Reset with POR ADC control register 1 ADC12CTL1 Read write 01A2h Reset with POR ADC interrupt flag register ADC12IFG
482. tApc4120N must be observed before conversion is started Otherwise the results will be false The ADC12 A D converter contains a built in reference with two selectable reference voltage levels 1 5 V and 2 5 V Either of these reference voltages may be applied to Vp of the A D core and also may be available externally on VRef check device data sheet for availability of Vp gp pin Additionally an external reference may be supplied for Vp through pin Venger check data sheet for availability of Vengr pin The reference voltage level for Vp can be selected to be AVss or be supplied externally through the Vngr Vepmgr pin check device data sheet for Vngr Vengr pin If the VaEgr Vengr pin is not available then Vp is connected to AVss Configuration of the reference voltage s is done with the Sref bits bits 4 5 and 6 in the ADC12MCTLx registers Up to six combinations of positive and negative reference voltages are supported as described in Table 15 1 If only external references are used the internal reference generator can be turned off with the REFON bit to conserve power Table 15 1 Reference Voltage Configurations Sref Voltage at Voltage at Vp 0 AVcc AVss 1 Vrer internal AVSS 2 3 Vengr external AVss 4 Vngr internal or external 5 Vrer internal Vngr Veggr internal or external 6 7 Vengr external Vngr Veger internal or external The voltage
483. tMod31 Tc oes ru s ov cs 0168h rw 0 rw rw rw Cap com control CCTL2 TH OutMod21 cele as ov 0166h rw 0 rw rw rw Cap com control CCTL1 OutMod11 een oun 0164h rw 0 rw rw rw rw Cap com control CCTLO 01 coms ech m ow 0162h rw rw rw rw rw Timer A control TACTL D e m psc am 0160h rw rw rw rw rw rw rw t Registers are reserved on devices with Timer A3 Bit 4 15 14 13 12 11 10 9 8 Timer interrupt vector 0 0 0 0 0 0 0 0 TAIV 12Eh ro ro ro ro ro ro ro ro Bit 4 2 1 0 Timer interrupt vector TAIV 0 TAIV 12 r 0 r 0 ro Vector Timer A5 five capture compare blocks integrated 0 Nointerrupt pending 2 CCIFG1 flag set interrupt flag of capture compare block 1 4 CCIFG2 flag set interrupt flag of capture compare block 2 CCIFG1 0 6 CCIFG3 flag set interrupt flag of capture compare block CCIFG1 CCIFG2 0 8 flag set interrupt flag of capture compare block CCIFG1 CCIFG2 CCIFG3 0 10 TAIFG flag set interrupt flag of Timer A register counter CCIFG1 CCIFG2 CCIFG3 CCIFG4 0 TAIV Vector Timer A3 three capture compare blocks integrated 0 Nointerrupt pending 2 CCIFG1 flag set interrupt flag of capture compare block 1 4 CCIFG2 flag set interrupt flag of capture compare block 2 CCIFG1 0 6 Reserved 8 Reserved 10 TAIFG flag se
484. tely and the results are invalid Therefore the ADC10BUSY bit should be tested to verify that it is 0 before resetting the ENC bit when in single channel single conversion mode The busy bit also indicates if sequence or repeat mode is still active even if the end of these modes is already started by resetting the ENC bit 0 No operation is active 1 Asample period conversion or conversion sequence is active The CONSEQ bits select the conversion mode Repeat mode is on if the CONSEQ 1 is set 0 Single channel single conversion mode One single channel is converted once 1 Sequence of channels mode A sequence of conversions is executed once 2 Repeat single channel mode Conversions on a single channel are repeated until CONSEQ is set to O or 1 3 Repeat sequence of channels A sequence of conversions is repeated until CONSEQ is set to 0 or 1 NOTE See also the Conversion Modes section Select the clock source for the converter core 0 ADC10 internal oscillator ADC100SC 1 ACLK 2 MCLK 3 SMCLK Select the division rate for the clock source selected by ADC10SSEL bits Oto 7 Divide selected clock source by 1 to 8 The divider s output signal name is ADC10CLK Eleven of these clocks are required for a conversion Invert sample input signal 0 The sample input signal is not inverted 1 The sample input signal is inverted The conversion data format in ADC10MEM is either unipolar straight binary ADC10DF 0 or 2
485. tem reset PUC signal or software reset SWRST but the UTXIE bit is reset to ensure full interrupt control capability 12 14 Control and Status Registers 12 5 Control and Status Registers The USART control and status registers are byte structured and should be accessed using byte processing instructions suffix B Table 12 3 lists the registers and their access modes Table 12 2 USAHTO Control and Status Registers Short Register Register Form Type Address Initial State USART control UOCTL Read write 070h See section 12 5 1 Transmit control UOTCTL Read write 071h See section 12 5 2 Receive control UORCTL Read write 072 See section 12 5 3 Modulation control UOMCTL Read write 073 Unchanged Baud rate 0 UOBRO Read write 074 Unchanged Baud rate 1 UOBR1 Read write 075 Unchanged Receive buffer UORXBUF Read write 076h Unchanged Transmit buffer UOTXBUF Read 077h Unchanged Table 12 3 USAHT1 Control and Status Registers Short Register Register Form Type Address Initial State USART control U1CTL Read write 078 See section 12 5 1 Transmit control U1TCTL Read write 079 See section 12 5 2 Receive control U1RCTL Read write 07Ah See section 12 5 3 Modulation control U1MCTL Read write 07Bh Unchanged Baud rate 0 U1BRO Read write 07Ch Unchanged Baud rate 1 U1BR1 Read write 07Dh Unchanged Receive buffer U1RXBUF Read write 07Eh Unchanged Transmit buffer U1TXBUF Read 07Fh Unchanged All bits are random after a PUC signal unless o
486. ter Transmitted PUC USPIIE 0 And Last Buffer Entry Is Transmitted USART Peripheral Interface SPI Mode 13 11 Interrupt and Control Functions 13 4 2 2 Receive Transmit Enable MSP430 is Slave Figure 13 11 shows the receive transmit enable bit activity when the MSP430 is slave Figure 13 11 State Diagram of Transmit Enable MSP430 as Slave 18 12 USPIIE 0 No Clock at UCLK Not Completed USPIIE 1 USPIIE 1 Idle State Transmitter Enabled Transmit S Disable Transmission Active Handle Interrupt Conditions External Clock Present Character USPIIE 1 Transmitted PUC USPIIE 0 When USPIIE is reset any data can be written regularly into the transmit buffer but no transmission is started Once the USPIIE bit is set the data in the transmit buffer are immediately loaded into the transmit shift register and character transmission is started 5 Note Writing to UXTXBUF SPI Mode Data should never be written to transmit buffer UXTXBUF when the buffer is not ready UTXIFG 0 and the transmitter is enabled USPIIE is set Otherwise the transmission may have errors Note Writing to UXTXBUF Reset of Transmitter SPI Mode Disabling of the transmitter should be done only if all data to be transmitted have been moved to the transmit shift register Data is moved from UTXBUF t
487. ter TAR 0170h 016Eh 016Ch Cap com control CCTL4T 016Ah Cap com control 0168h Cap com control CCTL2 0166h Cap com control CCTL1 0164h Cap com control CCTLO 0162h Timer_A control TACTL 0160h 1 14 13 12 11 10 9 OMi 211 210 wm wo 215 214 213 212 211 210 wo wo wo wo wo wo ee n n W W W W W W 215 214 213 212 211 210 wo wo wo wo wo 215 214 213 212 wo SE RES n n n n N 5 0 0 0 w 0 0 0 0 w 0 0 0 w 0 0 w 0 rw 0 rw 0 w 0 40 rw 0 EE 215 214 218 212 211 210 vo wo wo wm ee 215 214 218 212 211 210 we wo wo wo wo wo ee O 0 0 w 0 w 0 0 0 w 0 w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw W 2 W W 2 W 2 W 2 W 9 9 0 9 0 9 0 CM41 40 CCIS41 CCIS40 5 54 SCCI4 Unused rw rw rw 0 rw 0 n n ro CM31 CM30 CCIS31 CCIS30 SCS3 SCCI3 Unused rw rw rw 0 rw 0 n n ro 0 ro 0 0 0 0 0 W W W W W W 215 214 213 212 211 210 W rw 0 r W W W W W W W 21 CM20 CCIS21 CCIS20 SCS2 SCCI2 Unused rw rw rw 0 rw 0 rw rw CM11 CM10 CCIS11 CCIS10 SCS1 SCCI1 Unused rw rw rw 0 rw 0 rw rw 0 r CMO1 00 501
488. ter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C 0 defines start DADD R13 0 R12 add 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter Instruction Set Description B 19 Instruction Set Overview CLRN Syntax Operation Emulation Description Status Bits Mode Bits Example SUBR SUBRET B 20 Clear negative bit CLRN 0 or NOT src AND dst gt dst BIC 4 SR The constant 04h is inverted OFFFBh and is logically ANDed with the destination operand The result is placed into the destination The clear negative bit instruction is a word instruction N Reset to 0 Z Not affected C Not affected V Not affected OscOff CPUOff and GIE are not affected The Negative bit in the status register is cleared This avoids special treatment with negative numbers of the subroutine called CLRN CALL SUBR JN SUBRET If input is negative do nothing and return RET CLRZ Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Overview Clear zero bit CLRZ 0 2 or NOT src AND dst dst BIC 2 SR The constant 02h is inverted OFFFDh and logically ANDed with the destination operand The result is placed into the destination The clear zero bit instruction is a word instruction N Not affected Z Resetto 0 C Not affected V Not affected OscOff C
489. terrupt Item1 Item2 TOS SP After Interrupt Item1 Item2 PC SR TOS RETI return from an interrupt service routine 1 The status register with all previous settings pops from the stack previous settings of GIE CPUOFF etc are now in effect regardless of the settings utilized during the interrupt service routine 2 The program counter pops from the stack and begins execution at the point where it was interrupted The return from the interrupt is illustrated in Figure 3 8 Figure 3 8 Return From Interrupt SP Before After Return From Interrupt Item1 Item1 Item2 SP Item2 PC PC SR TOS SR TOS A RETI instruction takes five cycles Interrupt nesting is activated if the GIE bit is set inside the interrupt handling routine The GIE bit is located in status register SR R2 which is included in the CPU as shown in Figure 3 9 Interrupt Processing Figure 3 9 Status Register SR 15 8 7 0 OSC CPU Reserved For Future Enhancements SCG1 SCGO rw 0 Apart from the GIE bit other sources of interrupt requests can be enabled disabled individually or in groups The interrupt enable flags are located together within two addresses of the special function registers SFRs The program flow conditions on interrupt requests can be easily adjusted using the interrupt enable masks The har
490. terrupt enable URXIEt Initial state reset by PUC SWRST Receive enablet URXEt Initial state reset by PUC Transmit interrupt flag UTXIFGt Initial state set by PUC SWRST Transmit interrupt enable UTXIEt Initial state reset PUC SWRST Transmit enablet UTXEt Initial state reset by 1 Different for SPI mode see Chapter 13 t Suffix 0 for USARTO and 1 for USART1 The USART receiver and transmitter operate independently but use the same baud rate 12 4 1 USART Receive Enable Bit The receive enable bit URXE shown in Figure 12 12 enables or disables receipt of the bit stream on the URXD data line Disabling the USART receiver stops the receive operation after completion of receiving the character or stops immediately if no receive operation is active Start bit detection is also disabled Figure 12 12 State Diagram of Receiver Enable No Valid Start Bit URXE 0 Not Completed URXE 1 Valid Start Bit Idle State Receiver Enabled Receiver Collects Character Receive Handle Interrupt Disable Conditions Character Received Note URXE Reenabled UART Mode Because the receiver is completely disabled reenabling the receiver is asynchronous to any data stream on the communication line Synchronization can be performed by looking for an idle line condition before receiving a character USART
491. tested If itis negative continue at R7NEG if it is positive but not zero continue at R7POS TST B R7 Test low byte of R7 JN R7NEG Low byte of R7 is negative JZ R7ZERO Low byte of R7 is zero R7POS J Low byte of R7 is positive but not zero R7NEG Low byte of R7 is negative R7ZERO Low byte of R7 is zero XOR W XOR B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Overview Exclusive OR of source with destination Exclusive OR of source with destination XOR src dst or XOR W src dst XOR B src dst src XOR dst dst The source and destination operands are exclusive ORed The result is placed into the destination The source operand is not affected N Set if result MSB is set reset if not set Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Set if both operands are negative OscOff CPUOff and GIE are not affected The bits set in R6 toggle the bits in the RAM word TONI XOR R6 TONI Toggle bits of word TONI on the bits set in R6 The bits set in R6 toggle the bits in the RAM byte TONI XOR B R6 TONI Toggle bits in word TONI on bits set in low byte of R6 Reset to 0 those bits in low byte of R7 that are different from bits in RAM byte EDE XOR B EDEH7 Set different bit to 1s INV B R7 Invert Lowbyte Highbyte is Oh Instruction Set Description B 61
492. th capture compare registers and PWM output capability on chip clock generation H W multiplier USART s Watchdog Timer GPIO and others See hitp www ti com for the latest device information and literature for the MSP430 family Topic Page 1 1 Features and Capabilities 1 2 Devices 1 3 13 DEVICES 02202222427 7 1 3 TANX Devices 1 4 1 57 Devices eere aene MET IET Ie 1 4 s12x2 Devicesq eSI INDE II I 1 4 lat TSX Devices Tester 1 5 18714x Devices S 1 5 Features and Capabilities 1 1 Features and Capabilities The TI MSP430x1xx family of controllers has the following features and capabilities Ultralow power architecture 0 1 250 nominal operating current 91 MHz 1 8 V 3 6 operation 2 5 5 5 V for C11x 11 and E11x devices 6 us wake up from standby mode Extensive interrupt capability relieves need for polling Flexible and powerful processing capabilities Seven source address modes Four destination address modes Only 27 core instructions Prioritized nested interrupts No interrupt or subroutine level limits Large register file Ram execution capability Efficient table processing Fast hex to decimal conversion Extensive memory mapped peripheral set including Integrated 12 bit A D converter Integrated precision comparator Multiple timers and P
493. the Offset Voltage of the Comparator CAEX 1 14 21 Offset Voltage of the Comparator 1 14 21 Use CAOUT at an External Pin to Add Hysteresis to the Reference Level 14 23 ADGA2 Schematic 25 4 0 det tede oif obe iu e 15 2 ADC Core Input Multiplexer and Sample and Hold 15 4 Analog Multiplexer Channel 15 6 Stopping Conversion With ENC Bit 15 10 Single Channel Single Conversion Mode 15 11 Example Conversion Memory 15 12 ENC Does Not Effect Active Sequence 15 13 Sequence of Channels 15 14 Sequence of Channels Mode Flow 15 15 Sequence of Channels Mode Example 15 16 Repeat Single Channel Mode 40 15 17 Repeat Sequence of Channels 15 19 The Conversion Clock ADC12CLK 15 21 The Sample and Hold Function 15 22 Sample and Conversion Basic Signal Timing 15 23 Syn
494. the WAIT bit is allowed The WAIT bit is automatically reset if the BLKWRT bit is reset or the LOCK bitis set Block write operation is completed and then the WAIT bit returns to 1 Condition BLKWRT 1 see Figure 9 After each successful write operation the BUSY bit is reset to indicate that another byte or word can be written programmed The BUSY bit does not indicate the condition when the timing generator has completed the entire programming The high voltage portion and voltage generator remain active The maximum time should not be violated 0 Block write operation has started and programming is in progress 1 Block write operation is active and programming of data is completed Waiting for the next data to be programmed The Lock bit can be set during any write erase of a segment or mass erase request The active sequence is completed normally In block write mode if the Lock bit is set and BLKWRT and WAIT set the BLKWRT and WAIT bits are reset and the mode ends normally The WAIT bit is 1 after block write mode has ended Software or hardware can control the Lock bit If an access violation occurs see conditions described in paragraph C 1 1 the ACCVIFG and the Lock bit are set 0 Flash memory can be read programmed erased and mass erased 1 Flash memory can be read but not programmed erased or mass erased A current program erase or mass erase operation is completed normally The access
495. the control registers can have different functions in the two modes All bits are described with their function in the synchronous mode SYNC 1 Their function in the asynchronous mode is described in Chapter 12 USART Peripheral Interface SPI Mode 13 15 Control and Status Registers 13 5 1 USART Control Register The information stored in the control register shown in Figure 13 15 determines the basic operation of the USART module The register bits select the communication mode and the number of bits per character All bits should be programmed to the desired mode before resetting the SWRST bit Figure 13 15 USART Control Register 18 16 UOCTL 070h CHAR Li SYNC MM SWRST U1CTL 078h Unused Unused Unused isten rw 0 rw 0 rw 0 rw 0 rw 0 rw O0 rw O0 rw 1 Bit 0 The USART state machines and operating flags are initialized to the reset condition URXIFG USPIIE 0 UTXIFG 1 if the software reset bit is set Until the SWRST bitis reset all affected logic is held in the reset state This implies that after a system reset the USART must be reenabled by resetting this bit I a C 43 Note The USART initialization sequence should be Initialize per application requirements while leaving SWRST 1 Clear SWRST Enable interrupts if desired X Bit 1 Master mode is selected when the MM bit is set
496. the conversion mode is changed while the converter is actively running intermediate and undesirable modes can be accidentally selected if both CONSEQ bits are changed in a single instruction ADC12 deci Conversion Modes 15 5 6 Power Down 15 20 Therefore the following mode changes should be avoided while the converter is running 0 gt 3 1 2 2 1 0 The intermediate modes are caused by the asynchronous clocks for the CPU and the ADC12 These intermediate modes can be avoided simply by changing only one CONSEQ bit per instruction For example to change from mode 0 to mode 3 while the converter is actively running the following instructions could be used BIS CONSEQ_0 amp ADC12CTL1 Example 0 3 first aay ada siya ara la BEd ie MRT You s step is0 1 BIS CONSEQ_1 amp ADC12CTL1 second step is 1 gt 3 Acceptable sequence modifications are 0 gt 1 05 2 1 50 153 290 23 3 gt 1 2 The ADC12 incorporates two bits ADC12ON REFON for power savings ADC12ON turns on the A D core and REFON turns on the reference generator Each bit is individually controllable by software The ADC12 is turned off completely if both bits are reset The ADC12 registers are not affected by either of these bits and can be accessed and modified at any time see the ADC12 Control Registers section Note however that ADC12ON and REFON may only be modified if ENC 0
497. the high byte is always 0 in the result The status bits are handled according to the result of the byte instruction 5 8 Addressing Modes 5 2 2 Indexed Mode The indexed mode is described in Table 5 6 Table 5 6 Indexed Mode Description Content of ROM MOV X R5 Y R6 Assembler Code MOV 2 R5 6 R6 X22 Y 6 Length Two or three words Operation Move the contents of the source address contents of R5 2 to the destination address contents of R6 6 The source and destination registers R5 and R6 are not affected In indexed mode the program counter is incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV 2 R5 6 R6 Before After Address Register Address Register Space Space Oxxxxh PC OFF16h 00006h R5 01080h OFF16h 00006h R5 01080h OFF14h 00002h R6 0108Ch OFF14h 00002h R6 0108Ch OFF12h 04596h PC OFF12h 04596h 0108Ch 01094h 0006h 01094 01092h 05555h 01092h oiooon 01234h 01080h 01082h 01234h o togen 01082h 01234h 16 Bit CPU 5 9 Addressing Modes 5 2 3 Symbolic Mode The symbolic mode is described in Table 5 7 Table 5 7 Symbolic Mode Description 5 10 Length Operation Comment Example Before OFF16h OFF14h OFF12h OF018h OF016h OF014h 01116h 01114h 01112h Assembler Code MOV EDE TONI Two or three words Content of ROM MOV X PC
498. therwise noted by the detailed functional description The reset of the USART peripheral interface is performed by a PUC signal or a SWRST After a PUC signal the SWRST bit remains set and the USART interface remains in the reset condition until it is disabled by resetting the SWRST bit The USART module operates in asynchronous or synchronous mode as defined by the SYNC bit The bits in the control registers can have different functions in the two modes All bits in this section are described with their functions in the asynchronous mode SYNC 0 Their functions in the synchronous mode are described in Chapter 13 USART Peripheral Interface SPI Mode USART Peripheral Interface UART Mode 12 15 Control and Status Registers 12 5 1 USART Control Register UOCTL U1CTL The information stored in the USART control register UOCTL for USARTO and U1CTL for USART1 shown in Figure 12 16 determines the basic operation of the USART module The register bits select the communications protocol communication format and parity bit All bits must be programmed according to the selected mode before resetting the SWRST bit to disable the reset Figure 12 16 USART Control UOCTL U1CTL 12 16 UOCTL 070h U1CTL 078h Bit 0 n 5 w 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 The USART state machines and operating flags are initialized to the reset condition URXIFG URXIE UTXIE 0 UTXIFG 1 if the software reset bit is set
499. tically to Timer A in its default condition Timer B is different from Timer A in the following ways 1 Thelength of Timer B is programmable to be 8 10 12 or 16 bits where as Timer A is only a 16 bit timer 2 The SCCI bit functionality of the capture compare registers of Timer is not implemented in Timer B 3 The function of the capture compare registers for the compare mode of Timer B has changed slightly 4 On some devices a pin is implemented to put all Timer B outputs into a high impedance state Check the device data sheet for the presence of this pin On Timer A the capture compare register CCRx holds the data for the comparison to the timer value On Timer B each CCRx acts as a buffer for a compare latch and the compare latch holds the data used for the comparison So compare data is written to each CCRx in both timers however in Timer B the compare data is then transferred to the compare latch for the comparison The timing of the transfer of the compare data from Introduction each CCRx register to the corresponding compare latch TBCLx is user selectable to be either immediate or on a timer event See section 11 4 2 1 for a complete discussion on using and configuring the compare latches The addition of the compare latch gives the user more control over when exactly a compare period updates In addition multiple compare latches may be grouped together allowing the compare period of multiple compare reg
500. til the the con tinuous mode is disabled ADC10CT 0 or until the block starting address is modified in the ADC10SA register If the continuous mode is not enabled the DTC stops transferring ADC10 conversions after the complete block has been transferred one block mode or both blocks have been transferred two block mode Each DTC transfer requires one CPU clock MCLK During the DTC transfer the CPU is halted for the one clock cycle required for the transfer The DTC operates regardless of the mode the CPU is in at the time of transfer active mode or one of the low power modes 16 8 1 1 One Block Transfer Mode The DTC is enabled if 0 The block mode is set with the ADC10TB bit If this bit is cleared the DTC is in one block mode In one block mode the address range of the block begins with the value in the ADC10SA register and ends at SA 2n 2 where SA is the value of the ADC10SA register and is the number of data in the block also the value of the ADC10DTC1 register The one block transfer is illustrated in Figure 16 16 Figure 16 16 One Block Transfer Start Address 36 ADC10 n word address locations 16 29 Data Transfer Control High Speed Conversion Support 16 30 The first loading of ADC10MEM starts the data transfer operation The DTC transfers the ADC10MEM data buffer to the word at address pointer SA Next the address pointer is incremented by two and the internal transfer counter initial
501. time intervals or used in conjunction with the output unit to generate output signals such as PWM signals If the timer becomes equal to the value in compare register x then Interrupt flag CCIFGx located in control word CCTLx is set interrupt is requested if interrupt enable bits CCIEx and GIE are set Signal EQUx is output to the output unit This signal affects the output OUTx depending on the selected output mode The EQUO signal is true when the timer value is greater or equal to the CCRO value The EQU1 to EQUA signals are true when the timer value is equal to the corresponding CCR1 to CCR4 values 10 5 The Output Unit Each capture compare block contains an output unit shown in Figure 10 22 The output unit is used to generate output signals such as PWM signals Each output unit has 8 operating modes that can generate a variety of signals based on the EQUO and EQUx signals The output mode is selected with the OMx bits located in the CCTLx register Figure 10 22 Output Unit EQUO EQUx Timer Modes OUTx OMx2 OMx1 OMx0 4 0 Output Control 0 1 0 1 0 1 0 1 OUTx Signal Timer Clock j4 OUTx Output mode OUTx signal reflects the value of the OUTx bit Set mode OUT x signal reflects the value of signal EQUx PWM toggle reset EQUx toggles OUTx EQUO resets OUTx PWM set reset EQUx sets OUTx EQUO resets OUTx
502. tinue with the next steps only if the BUSY bit is reset Set the write control bit WRT when a single byte of word data is to be written LJ Set the write WRT and BLKWRT control bits when block write is chosen to write multiple bytes or words to the flash memory module L Writing the data to the selected address starts the timing generator The data is written programmed while the timing generator proceeds Note Whenever the write cycle is stopped before its normal ending by the hard ware the timing generator is stopped and the data written to the flash memory can be marginal The data may be incorrect which can be verified or the data are verified to be correct but the programming is marginal Reading of the data may be inconsistently valid when varying the supply volt age the temperature the access time instruction execution data read or the time LLL 3 Flash Memory Data Structure and Operation Figure C 8 Basic Flash Memory Module Timing During Write Single Byte or Word Cycle 4 gt lt gt lt Programming Operation Active Generate Remove Programming Voltage Entire Programming Cycle Timing Programming Voltage 4 Time of Increased Current Consumption From Supply BUSY 33 fx Figure C 9 Basic Flash Memory Module Timing During a Block Write Cycle BLKWRT bit Write to Flash e g MOV 123h
503. tion and points to the consecutive program step E program continues here if the CPUOff bit is reset during the interrupt service routine Otherwise the PC retains its value and the processor returns to LPMO System Resets Interrupts and Operating Modes 3 27 Operating Modes The following example describes clearing low power mode 0 Interrupt service routin Se dean CPU is active while handling interrupts BIC 10h 0 SP Clears the CPUOff bit in the SR contents that were stored on the stack RETI RETI restores the CPU to the active state because the SR values that are stored on the stack were manipulated This occurs because the SR is pushed onto the stack upon an interrupt then restored from the Stack after the RETI instruction 3 5 2 Low Power Modes 2 and 3 LPM2 and LPM3 Low power mode 2 or is selected if bits CPUOff and SCG1 in the status register are set Immediately after the bits are set CPU MCLK and SMCLK operations halt and all internal bus activities stop until an interrupt request or reset occurs Peripherals that operate with the MCLK or SMCLK signal are inactive because the clock signals are inactive Peripherals that operate with the ACLK signal are active or inactive according with the individual control registers and the module enable bits in the SFRs All I O port pins the RAM registers are unchanged Wake up is possible by e
504. tion clock crystal or to be used with a high speed crystal All analog components for the 32 768 Hz oscillator are integrated into the MSP430 only the crystal needs to be connected with no other external components required When using the LFXT1 oscillator with a high speed crystal additional load capacitors are required Some MSP430 devices have an additional high speed crystal oscillator LFXT2 Refer to the clock chapter and the specific device data sheets for details In addition to the crystal oscillator s all MSP430 devices contain a digitally controlled RC oscillator DCO The DCO is different from RC oscillators found on other microcontrollers because it is digitally controllable and tuneable Clock source selection for peripherals and CPU is very flexible Most peripherals are capable of using the 32768 Hz crystal oscillator clock the high speed crystal oscillator clock where applicable or the DCO clock The CPU is capable of executing from the DCO clock or from either of the two crystal oscillator clocks See Chapter 7 for details on the clock system Chapter 3 System Resets Interrupts and Operating Modes This chapter discusses the MSP430x1xx system resets interrupts and operating modes Topic Page 3 4 System Reset and Initialization 3 2 3 2 Global Interrupt Structure 3 5 3 3 MSP430 Interrupt Priority
505. to destination DADD src dst or DADD W src dst DADD B src dst src dst C dst decimally The source operand and the destination operand are treated as four binary coded decimals BCD with positive signs The source operand and the carry bit C are added decimally to the destination operand The source operand is not affected The previous contents of the destination are lost The result is not defined for non BCD numbers N Setif the MSB is 1 reset otherwise Z Setif result is zero reset otherwise C Setif the result is greater than 9999 Set if the result is greater than 99 V Undefined OscOff CPUOff and GIE are not affected The eight digit BCD number contained in R5 and R6 is added decimally to an eight digit BCD number contained in R3 and R4 R6 and R4 contain the MSDs CLRC CLEAR CARRY DADD R5 R3 add LSDs DADD R6 R4 add MSDs with carry JC OVERFLOW If carry occurs go to error handling routine The two digit decimal counter in the RAM byte CNT is incremented by one CLRC clear Carry DADD B 1 CNT increment decimal counter Or SETC DADD B 80 CNT DADC B CNT DEC W DEC B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Instruction Set Overview Decrement destination Decrement destination DEC dst or DEC W dst DEC B dst dst 1 dst SUB 1 dst SUB B 1 dst The destination operand is decremented by one The original contents are
506. to the MSB the MSB is shifted into the MSB 1 and the LSB 1 is shifted into the LSB Figure B 8 Destination Operand Arithmetic Right Shift Word 15 0 Status Bits Mode Bits Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the LSB Reset OscOff CPUOff and GIE are not affected Instruction Set Description B 49 Running Title Attribute Reference Example OR Example OR R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 RRA R5 R5 2 R5 The value in R5 is multiplied by 0 75 0 5 0 25 PUSH R5 hold R5 temporarily using stack RRA R5 R5x0 5 R5 ADD SP R5 R5x05 R5 1 5xR5 R5 RRA R5 1 5x R5 x 0 5 0 75 x R5 R5 RRA R5 5 0 5 R5 PUSH R5 R5x0 5 TOS RRA SP TOS x 0 5 0 5 x R5 x 0 5 0 25 x R5 TOS ADD SP R5 R5x0 5 R5 0 25 0 75 x R5 R5 The low byte of R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 RRA B R5 R5 2 R5 operation is on low byte only High byte of R5 is reset The value in R5 low byte only is multiplied by 0 75 0 5 0 25 PUSH B R5 hold low byte of R5 temporarily using stack RRA B R5 R5x0 5 R5 ADD B SP R5 R5x05 R5 1 5xR5 R5 RRA B R5 1 5 x R5 x 0 5 0 75 x R5 R5 RRA B R5 R5x0 5 R5 PUSH B R5 R5x0 5 TO
507. tream on the URXD SOMI data line Disabling the USART receiver USPIIE 0 stops the receive operation after completion or stops a pending operation if no receive operation is active In synchronous mode UCLK does not shift any data into the receiver shift register 13 4 1 1 Receive Transmit Enable Bit MSP430 as Master The receive operation functions identically for three pin and four pin modes as shown in Figure 13 7 when the MSP430 USART is selected to be the SPI master USART Peripheral Interface SPI Mode 13 9 Interrupt and Control Functions Figure 13 7 State Diagram of Receiver Enable Operation MSP430 as Master No Data Written to UXTXBUF USPIIE 0 Not Completed USPIIE 1 Idle State Receiver Enabled Receiver Collects Character Receive USPIIE 1 Disable Handle Interrupt Conditions USPIIE 0 Character Received PUC USPIIE 0 13 4 1 2 Receive Transmit Enable Bit MSP430 as Slave Three Pin Mode The receive operation functions differently for three pin and four pin modes when the MSP430 USART module is selected to be the SPI slave In the three pin mode shown in Figure 13 8 no external SPI receive control signal stops an active receive operation A PUC signal a software reset SWRST orareceive transmit enable USPIIE signal can stop a receive operation and reset the USART Figure 13 8 State Diagram of Receive Transmit Enable
508. triggers an NMI interrupt Operation of Global Interrupt Reset NMI Ifthe RST NMI pin is set to the reset function the CPU is held in the reset state as long as the RST NMI pin is held low After the input changes to a high state the CPU starts program execution at the word address stored in word location OFFFEh reset vector If the RST NMI pin is set to the NMI function a signal edge selected by the NMIES bit will generate an interrupt if the NMIIE bit is set When accepted program execution begins at the address stored in location OFFFCh The RST NMI flag in the SFR IFG1 4 is also set ET Note When configured in the NMI mode a signal generating an NMI event should not hold the RST NMI pin low When a PUC is generated see section 3 1 1 the PUC resets the bits in the WDTCTL register This results in the RST NMI pin being configured in the reset mode If the signal on the RST NMI pin that generated the NMI event holds the pin low the processor will be held in the reset state When NMI mode is selected and the NMI edge select bit is changed an NMI can be generated depending on the actual level at the RST NMI pin When the NMI edge select bit is changed before selecting the NMI mode no NMI is generated The NMI interrupt is maskable by the NMIIE bit Interrupt Processing 3 3 2 Operation of Global Interrupt Oscillator Fault Control The oscillator fault signal warns of a possible error condition with the cry
509. trol Registers 2_5V MSC REFBurst REF Out ADC10SR ADC10SHT Sref 16 24 bit6 bit7 bit8 bit9 bit 10 bits11 12 bits 13 15 Reference voltage level 0 The internal reference voltage is 1 5V if REFON 1 1 The internal reference voltage is 2 5V if REFON 1 Multiple sample and conversion Valid only when the A D mode is chosen as repeat single channel sequence of channel or repeat sequence of channels CONSEQz0 0 The sampling timer starts with a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversion are performed automatically as soon as the prior conversion is completed without additional rising edges of SHI Additional rising edges of SHI are ignored until the sequence has completed or the ENC bit has been toggled depending on mode The internal reference voltage is externally available only during the sample and conversion period if REFBurst 1 and REF Out 1 This reduces system current consumption The internal reference voltage is continuously available externally if REFBurst 0 and REF Out 1 The internal reference voltage is available externally see device data sheet for pin details 0 The internal reference voltage is not available externally 1 The internal reference voltage is available externally Note that the corresponding ADC10AE bit must also be set
510. ts in the TACTL register the timer should be halted during this modification Critical modifications are the input select bits input divider bits and the timer clear bit Asynchronous clocks input clock and system clock can result in race conditions where the timer reacts unpredictably The recommended instruction flow is 1 Modify the control register and stop the timer 2 Start the timer operation For example MOV 01C6 amp TACTL ACLK 8 timer stopped timer cleared BIS 10h amp TACTL Start timer with up mode 10 6 2 Timer_A Register TAR The TAR register is the value of the timer Figure 10 28 TAR Register 15 0 170h imer Value rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw O rw 0 rw 0 rw 0 10 26 Timer A Registers X EA EEE EE Note Modifying Timer A Register TAR When ACLK SMCLK or the external clock TACLK or INCLK is selected for the timer clock any write to timer register TAR should occur while the timer is not operating otherwise the results may be unpredictable In this case the timer clock is asynchronous to the CPU clock MCLK and critical race conditions exist 10 6 3 Capture Compare Control Register CCTLx Each capture compare block has its own control word CCTLx shown in Figure 10 29 The POR signal resets all bits of CCTLx the PUC signal does not affect these bits Figure 10 29
511. ts when STE returns to a high state In the three pin mode the STE input signal is not relevant 13 3 2 Slave SPI Mode The slave mode is selected when bit MM of the control register is reset and synchronous mode is selected The UCLK pin is used as the input for the serial shift clock supplied by an external master The data transfer rate is determined by this clock and not by the internal bit rate generator The data loaded into the transmit shift register through the transmit buffer UxTXBUF before the start of UCLK is transmitted on the SOMI pin using the UCLK supplied from the master Simultaneously the serial data applied to the SIMO pin are shifted into the receive shift register on the opposite edge of the clock The receive interrupt flag URXIFG indicates when the data is received and transferred into the receive buffer The overrun error bit is set when the previously received data is not read before the new data is written to the receive buffer 13 3 2 1 Four Pin SPI Slave Mode 13 8 In the four pin SPI mode the STE signal is used by the slave to enable the transmit and receive operations It is applied from the SPI master The receive andtransmit operations are disabled when the STE signalis high and enabled when it is low Whenever the STE signal becomes high any receive operation in progress is halted and then continues when the STE signal is low again The STE signal enables one slave to access the data lines The S
512. tus Registers Register E we Address Initial State USART control UOCTL Read write 070h See Section 13 5 1 Transmit control UOCTL Read write 071h See Section 13 5 2 Receive control UORCTL Read write 072h See Section 13 5 3 Modulation control UOMCTL Read write 073 Unchanged Baud rate 0 UOBRO Read write 074h Unchanged Baud rate 1 UOBR1 Read write 075 Unchanged Receive buffer UORXBUF Read write 076h Unchanged Transmit buffer UOTXBUF Read 077h Unchanged Table 13 3 USAHT1 Control and Status Registers Register et Address Initial State USART control U1CTL Read write 078h See Section 13 5 1 Transmit control U1TCTL Read write 079h See Section 13 5 2 Receive control U1RCTL Read write 07Ah See Section 13 5 3 Modulation control U1MCTL Read write 07Bh Unchanged Baud rate 0 U1BRO Read write 07 Unchanged Baud rate 1 U1BR1 Read write 07Dh Unchanged Receive buffer U1RXBUF Read write 07Eh Unchanged Transmit buffer U1TXBUF Read 07Fh Unchanged All bits are random following the signal unless otherwise noted by the detailed functional description Reset ofthe USART module is performed by the PUC signal or a SWRST After a PUC signal the SWRST bit remains set and the USART module remains in the reset condition It is disabled by resetting the SWRST bit The SPI mode is disabled after the PUC signal The USART module operates in asynchronous or synchronous mode as defined by the SYNC bit The bits in
513. ty key violation n c A Flash memory security key violation FE Note Software PUC If desired software can cause a PUC by simply writing to the watchdog timer control register with an incorrect password System Reset and Initialization p A oM Note Generation ofthe POR PUC signals does not necessarily generate a system reset interrupt Anytime a POR is activated a system reset interrupt is generated However when a PUC is activated a system reset interrupt may or may not be generated Instead a lower priority interrupt vector may be generated depending on what action caused the PUC Each device data sheet gives a detailed table of what action generates each interrupt This table should be consulted for the proper handling of all interrupts LLLLS S S EAUAAAAXAMMMA When the Vcc supply provides a fast rise time as shown in Figure 3 2 the POR delay provides enough active time on the POR signal to allow the signal to initialize the circuitry correctly after power up When the rise time is slow as shown in Figure 3 3 the POR detector holds the POR signal active until has risen above the level This also ensures a correct initialization Figure 3 2 Power On Reset Timing on Fast Voc Rise Time
514. uction Set Overview INVLW INV B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Example B 32 Invert destination Invert destination INV dst INV B dst NOT dst dst XOR 0OFFFFh dst XOR B 0FFh dst The destination operand is inverted The original contents are lost N Setif result is negative reset if positive Z Setif dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C result is not zero reset otherwise NOT Zero Set if result is not zero reset otherwise NOT Zero V Setif initial destination operand was negative otherwise reset OscOff CPUOff and GIE are not affected Content of R5 is negated twos complement MOV 00Aeh R5 R5 000AEh INV R5 Invert R5 R5 OFF51h INC R5 R5 is now negated R5 OFF52h Content of memory byte LEO is negated MOV B SOAEh LEO MEM LEO INV B LEO Invert LEO MEM LEO 051h INC B LEO MEM LEO is negated MEM LEO 052h JC JHS Syntax Operation Description Status Bits Example Example Instruction Set Overview Jump if carry set Jump if higher or same JC label JHS label If C 1 PC 2x offset gt PC If C 2 0 execute following instruction The status register carry bit C is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If C is reset the next
515. umed to be 32 times the ACLK frequency The error listed is calculated for the transmit and receive paths In addition to the error for the receive operation the synchronization error must be considered Table 12 6 Commonly Used Baud Rates Baud Rate Data and Errors Divide Divide by ACLK 32 768 Hz MCLK 1 048 576 Hz Synchr Max s Baud TX RX RX TX RX Rate ACLK MCLK UxBR1 UxBRO UxMCTL Error 96 Error 96 Error 96 UxBR1 UxBRO UxMCTL Error Error i oe Y EE EE is i 1 9 5 3 The maximum error is calculated for the receive and transmit modes The receive mode error is the accumulated time versus the ideal scanning time in the middle of each bit The transmit error is the accumulated timing error versus the ideal time of the bit period The MSP430 USART peripheral interface allows baud rates nearly as high as the clock rate It has a low error accumulation as a result of modulating the individual bit timing In practice an error margin of 2096 to 3096 supports standard serial communication USART Peripheral Interface UART Mode 12 29 Baud Rate Considerations 12 7 3 Synchronization Error The synchronization error shown in Figure 12 29 results from the asynchronous timing between the URXD pin data signal and the internal clock system The receive signal is synchronized with the BRSCLK clock The BRSCLK clock is sixteen to thirty one times faster than the bit timing as des
516. unts to 0 TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 updated simultaneously when TBR counts to 0 or to TBCLO 3 3 1 3 TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to 22 TBCLO TBCL1 TBCL2 TBCL4 TBCL5 TBCL6 t Timer B3 has only three CCR blocks No triple group is possible with 3 CCR s If TBCLGRP 2 then it is treated as TBCLGRP 1 t Timer B3 has only three CCR blocks TBCCRO TBCCR1 and 2 are one group TBCLGRP 3 CLLDx 0 1 2 Notes 1 2 3 When using groups load mode for the group is selected with the bits of the lowest numbered TBCCTLx register in the group except when TBCLGRP 3 For example when grouped by 2 the CLLDx bits of TBCCTL3 determine the load mode for TBCL3 and TBCL4 When grouped by 3 the bits of TBCCTL4 determine the load mode for TBCL4 TBCL5 and TBCL6 etc When TBCLGRP 3 the CLLDx bits from TBCTL1 are used When using groups all TBCCRx registers must be updated with new data before the load will take place except when using immediate mode even if new data old data When using immediate mode each compare latch is updated immediately when its corresponding TBCCRx register is updated When using groups different load modes may be selected for each group For example when grouped by 3 immediate mode may be selected via CLLDx bits in TBCCTL1 for TBCL1 TBCL2 and TBCL3 and mode 2 may be selected via CLLD
517. urations Table 3 13 MSP430x14x Module Enable Registers 1 and 2 Bit Position Short Form Initial State 1 0 ME1 1 1 2 1 3 1 4 1 5 1 6 1 7 2 0 ME2 1 ME2 2 2 3 2 4 2 5 2 6 2 7 Note URXEO Reset USPIEO Reset UTXEO Reset URXE1 Reset USPIE1 Reset UTXE1 Reset Comments Reserved Reserved Reserved Reserved Reserved Reserved USARTO receiver enable UART mode USARTO transmit and receive enable SPI mode USARTO transmit enable UART mode Reserved Reserved Reserved Reserved USART1 receiver enable UART mode USART1 transmit and receive enable SPI mode USART1 transmit enable UART mode Reserved Reserved The configuration of some MSP430 devices may differ from those in above table Refer to specific device data sheets for individual configurations System Resets Interrupts and Operating Modes 3 19 Interrupt Processing 3 4 2 Interrupt Vector Addresses The interrupt vectors and the power up starting address are located in the address range OFFFFh OFFEOh as described in Tables 3 14 through 3 16 The vector contains the 16 bit address of the appropriate interrupt handler instruction sequence The interrupt vectors for 1xx devices are shown in the following tables See also the specific device s data sheet Table 3 14 Interrupt Sources Flags and Vectors of MSP430x11xx Configurations SYSTEM WORD INTERRUPT SOURCE INTERRUPT FLAG TE
518. ured by the integrated DCO Finally the application may use a crystal for further software execution Figure 7 14 Select Crystal Oscillator for MCLK Example Uses LFXT1 for MCLK SELM DCOCLK 1 I2 14 8 XT2CLK MCLKGEN DIVM CPUOff MCLK Main System Clock The sequence to switch the MCLK source from the DCO clock to the crystal clock LFXT1CLK or XT2CLK should be 1 Switch on the crystal oscillator OscOff 0 XTS is reset LF mode is selected or set HF mode is selected BIS B XTS amp BCSCTL1 Set XTS bit to select LFXT1 oscillator BIC OSCOFF SR Turn on LFXT1 oscillator Basic Clock Module 7 15 Features for Low Power Applications b Inx13x and x14x devices the XT2 oscillator can also be used XT2Off is reset BIC B XT20ff amp BCSCTL1 Reset XT2Off to turn on LFXT1 oscillator 2 Clear the OscFault flag 3 Wait the required delay 4 Test the OscFault flag 5 Repeat steps 2 through 4 until the OscFault flag remains cleared L1 BIC B OFIFG amp IFG1 Clear OscFault flag MOV OFFFh R15 Move delay value to register L2 DEC R15 Decrement delay value JNZ L2 Repeat until zero BIT B OFIFG amp IFG1 Test OscFault flag JNZ L1 Repeat if necessary Figure 7 15 Timing to Select Crystal Oscillator for MCLK Example Uses LFXT1 in HF Mode for MCLK Turn on the Crystal Oscillator DCOCLK ids
519. vailable at the input selection switch see Figure 15 16 further called sample signal input or from the integrated sampling timer When the sampling timer is used to source SAMPCON the sample signal input is used to trigger the sampling timer The sample signal input is selected by the SHS bits in ADC12CTL1 There are four choices for the sample signal input ADC12SC Timer A OUTI1 Timer B OUTO and Timer B OUT1 The polarity of the sample signal input may be selected by the ISSH bit see Figure 15 16 Also the sample signal input is passed to the sampling timer or to the SAMPCON signal under control of the ENC bit This is discussed in detail further ahead ADC12SC is a control bit located in ADC12CTLO Its value is set by software Depending on the selected sampling mode this bit allows the software to either start a sample and conversion S C cycle SHP 1 or to completely control the sampling period SHP 0 The sample signal input can be asynchronous to a conversion enable and is synchronized and enabled by the ENC bit Without synchronization the first sampling period after the ENC bit is set could be erroneous depending on where the ENC bit is set within the cycle of the input signal In Figure 15 18 for example note that the ENC bit is set in the middle of a high pulse from the sample signal input If the sample input signal were simply passed directly to the S H the first conversion of the example would be erroneous bec
520. verify the above inequality is MaxDTCCycles x 1 MaxWakeTime lt SampleClocks 13 x VftADC10CLK Where MaxDTCCycles is the maximum number of DTC clock cycles required for the transfer see Table 16 3 MaxWakeTime is the maximum wake time from a low power mode SampleClocks is the number of sample clocks for the ADC10 operation set with the SHT bits in register ADC10CTLO Example 16 1 Calculate the Maximum ADC10 Clock Frequency With the Following System Conditions Lj CPU in active mode Minimum MCLK frequency of 1 MHz SHT bits set to 0 ADC10 sample period 4 ADC10CLK cycles 16 38 Controlling the Current Consumption of the ADC10 Module The inequality reduces to 3 x 1 1 106 lt 4 13 x 1 f ADC10CLK Which further reduces to f ADC10CLK lt 17x106 3 or f ADC10CLK lt 5 67 MHz Example 16 2 Calculate the Maximum ADC 10 Clock Frequency With the Following System Conditions LJ CPU in LPM3 MCLK DCOCLK Minimum MCLK frequency of 1 MHz SHT bits set to 2 ADC10 sample period 16 ADC10CLK cycles The inequality reduces to 4 x 1 1 106 60S lt 1613 x 1 f ADC10CLK Which reduces to 4 us 6 us lt 29 f ADC10CLK Of 1 lt 29 10 us or ffADC10CLK lt 2 9 MHz Using the above formula and examples a table can be constructed to show the maximum frequency of ADC10CLK in relation to MCLK for the operating modes shown Maximum f ADC10CLK Relative to
521. version mode is changed after the sequence begins but before it has completed and the ENC bit is toggled then the original sequence completes normally and the new mode takes effect and is started after the original sequence completes unless the new mode is single channel single conversion lf the new mode is single channel single conversion then the original sequence stops when no sample and conversion is active or after an active sample and conversion is completed or when the ENC bit is reset whichever comes first Then the single conversion begins when the ENC bit is set again See also the Switching Between Conversion Modes section An active sequence may be stopped immediately by selecting single channel single conversion mode reset CONSEQ 1 bit and then resetting the enable conversion bit ENC The data in register ADC10MEM is unpredictable and the interrupt flag ADC10IFG may or may not be set This is generally not recommended but may be used as an emergency exit Figure 16 5 illustrates the sequence of channels mode Conversion Modes Figure 16 5 Sequence of Channels Mode If x gt 0 then x x 1 x INCH Wait for Enable SHS 0 and ENC 10r 4 and ADC10SC 5 Wait for Trigger SAMPCON 4 nae lt 4 8 16 64 x ADC10CLK Sample Input Channel Ax Use 4 8 16 or 64 ADC10CLKs If x gt 0 then x 2 x 1 SAMPCON Y lt 12 x ADC10CLK em Convert
522. version stops immediately However the data in memory register ADC10MEM is unpredictable and interrupt flag ADC10IFG may or may not be set This method is generally not recommended Figure 16 6 illustrates the repeat single channel mode Conversion Modes Figure 16 6 Repeat Single Channel Mode CONSEQ 2 ADC100ON 1 ENC 4 x INCH Wait for Enable SHS 0 and ENC 1 or 4 and ADC10SC 4 Wait for Trigger SAMPCON 4 lt 4 8 16 64 x ADC10CLK ENC 0 Sample Input Channel Ax Use 4 8 16 or 64 ADC10CLKs lt 12 x ADC10CLK MSC 1 Convert Use and 12 x ADC10CLK ENC 1 1 x ADC10CLK Conversion Completed Result to ADC10MEM ADC1OIFG Is Set 16 4 4 Repeat Sequence of Channels Mode The repeat sequence of channels mode is identical to the sequence of channels mode except the sequence is repeated continuously until stopped by software Each time a conversion is completed the results are loaded into register ADC10MEM and interrupt flag ADC10IFG is set Additionally If the interrupt enable flag ADC10IE is set an interrupt request is generated The conversion mode may be changed without first stopping the conversions When this is done the new mode takes effect after the current sequence completes except when the new mode is repeat single channel In this case the sequence does not complete and the new mode takes effect immediately see also t
523. x depending on the selected output mode The EQUO signal is true when the timer value is greater or equal to the TBCLO value The EQU1 to EQUx signals are true when the timer value is equal to the corresponding TBCL1 to TBCLx values 11 4 2 1 Capture Compare Block Compare Mode Compare Latch TBCLx 11 20 The compare logic uses the data in the compare latch for its comparison with the timer value The compare data is first written by software to the capture compare register CCRx and then automatically transferred to the compare latch on a user selectable load event The load event is selected with the CLLDx bits in each CCTLx register In addition the compare latches may be grouped together so that each compare latch in a group is updated simultaneously on the load event All compare latches may be grouped together in a single group or they may be grouped in groups of two or three compare latches The grouping is configured with the TBCLGRP bits in the TBCTL register When using groups the CLLDx bits of the lowest numbered CCRx register in the group determine the load event for each compare latch of the group except when all 7 compare latches are grouped together TBCLGRP 3 For example if a user selects the compare latches to be grouped in threes then there are two groups of three TBCL1 TBCL2 and TBCL3 form one group and TBCL4 TBCL5 and TBCL6 form the other group In this scenario the CLLDx bits for TBCL1 determine the load eve
524. x bits in TBCCTL4 for TBCL4 TBCL5 and TBCL6 11 5 The Output Unit The Output Unit Each capture compare block contains an output unit shown in Figure 11 22 The output unit is used to generate output signals such as PWM signals Each output unit has 8 operating modes that can generate a variety of signals based on the EQUO and EQUx signals The output mode is selected with the OMx bits located in the CCTLx register Figure 11 22 Output Unit EQUO EQUx OUTx OMx2 OMx1 OMx0 4 0 Output Control 0 1 0 1 0 1 0 1 OUTx Signal Timer Clock j4 OUTx Output mode OUTx signal reflects the value of the OUTx bit Set mode OUT x signal reflects the value of signal EQUx PWM toggle reset EQUx toggles OUTx EQUO resets OUTx PWM set reset EQUx sets OUTx EQUO resets OUTx Toggle EQUx toggles OUTx signal Reset EQUx resets OUTx PWM toggle set EQUx toggles OUTx EQUO sets OUTx PWM reset set EQUx resets OUTx EQUO sets OUTx Note OUTx signal updates with rising edge of timer clock for all modes except mode 0 Modes 2 3 6 7 not useful for output unit 0 Timer B 11 23 11 5 1 11 24 Output Unit Output Modes The output modes are defined by the OMx bits and are discussed below The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are
525. xamples the r indicates read the w indicates write and the value after the dash indicates the initial condition If the value is in parenthesis the initial condition takes effect only after a POR a PUC alone will not effect the bit s If the value is not in parenthesis it takes effect after a PUC alone or after a POR PUC combination Some examples follow Type Description rw 0 Read write reset with POR rw 0 Read write reset with POR or PUC r 1 Read only set with POR or PUC r Read only no initial state Write only no initial state Global Interrupt Structure 3 2 Global Interrupt Structure There are four types of interrupts System reset Maskable Non maskable 1 Non maskable System reset POR PUC is discussed in section 3 1 Maskable interrupts are caused by A watchdog timer overflow if timer mode is selected Other modules with interrupt capability Non maskable interrupts are not maskable in any way No individual interrupt enable bit is implemented for them and the general interrupt enable bit GIE has no effect on them Non maskable interrupts are not masked by the general interrupt enable bit GIE but are individually enabled or disabled by an individual interrupt enable bit When a non maskable interrupt is accepted the corresponding interrupt enable bit is automatically reset therefore disabling the interrupt for execution of the interrupt service routine
526. y 1 are reset Result is in ADC12MEMx ADC12MEM x 1 ADC12MEMy Interrupt flags are ADC12IFG x ADC12IFG x 1 ADC12IFG y More than one sequence is possible Channel INCH and reference voltage Sref are selected in ADC12MCTLx The conversion of one single channel is permanently repeated until repeat is off or ENC is reset x CStartAdd points to the conversion start address Result is in ADC12MEMx interrupt flag is ADC121FG x Channel INCH and reference voltage Sref are selected in ADC12MCTLx The conversion of a sequence of channels is permanently repeated until repeat is off or ENC is reset x CStartAdd points to the conversion start address The last channel in a sequence y is marked with EOS 1 ADC12MCTL 7 all other EOS bits in ADC12MCTLx ADC12MCTL x 1 ADC12MCTL y 1 are reset Result is in ADC12MEMx ADC12MEMx 1 interrupt flag is ADC12IFG x ADC12IFG x 1 More than one sequence is possible Channel INCH and reference voltage Sref are selected in ADC12MCTLx ADC12 Conversion Modes 15 5 1 Single Channel Single Conversion Mode The single channel mode converts a single channel once The channel to be converted is selected by the INCH bits in the conversion memory control regis ter ADC12MCTLx associated with the conversion memory register pointed to by the CStartAdd bits located in ADC12CTL1x The conversion range Vp is configured in the same conversion memory

MSP430x1xx Family User's Guide (Rev. B)

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