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rtVAX 300 Hardware User's Guide

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1. 001 001 E 001 lt 00 E a 2 gt 02H 2 MSZ T T 001 001 9 9 91H 1 9 1 S T 5 Y 05 lt 21 gt 0 6 lt gt VXH lt gt Zt lt 02 gt lt gt 2 lt 01 gt 2 vXH lt 62 gt 9v g St 109 St lt 6 gt lt 2 gt 1 0 vt y lt 92 gt 1 0 109 vv v lt 8 gt 2 Ir lt t t H lt gt lt 2 gt 1 0 6 lt 2221 0 Op 6 __ _ lt 9 gt lt 12 gt 1 0 J lt 0221 0 LINX 8 lt
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4. 4 L T 00L eu H VTO ure L 2 1 m ig 1 59959 za sq 99154545 s rH za ra 8 5 1 507 28 8 lt EE 99505 6 2 2 2 a 7 Todes vi x i x 4758 544505 5 2 L aj T WOH3O 99 0 NVHSO 02 29 AS lt gt 12 64 ZOL 168 H 1 WNOHSOS amp E onu _ vel Wd AHOW3W Wd pesn 1 00 9 ans Wd 129195 WOY WY 1 XOF 1 9915450 e 18 2 1 50460 001 1454 11 y Y 11195 52187 1 5 lt gt 0 450 1 gt gt lt gt 30585 108 EXE eo ez T3IIHMd o il 185 6 SEE REREI l 1 862136 vi 5H pi LOW H HSOJSOHGIVI 31 259 Fm H 8519 1 a ie 9 74H43 H BSOXVAHOLY saa 87
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6. 627700 T3L1lHMAVHG 1 lt 0 gt 5 1 lt gt lt gt lt gt lt gt lt gt lt gt lt 9 gt lt 4 gt lt gt lt 6 gt 001 ji L gl 9 9 1 lt 0 gt 59 lt 0 gt 1 lt gt lt 2 gt 7 lt 2 lt gt 1 H lt 9 gt 7 lt 9 gt 7 gt lt 0 gt 0 VH lt gt lt gt sv S NVH 9 NvH Z NVH 1 lt gt 1 lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt 4 gt lt gt lt 6 gt 001 i L 9 8
7. 1200 1220 lt gt lt 61 62 gt 1 lt 6 62 gt 1 4 318vN3 318VN3 lt 6 gt 4050 p ino 1nO NI 8 lt 01 gt 4059 Ano 319984 5 z ddso S 2 eseg 920 1120 5 WOW pue PIOM lt gt 8915450 lt 0 gt 1 045 lt 1 gt 105592014 4 00 919 GtdNHSINIS 8LOADQVdH HIOAOQV3H GILOAOQV3H 88300 1 18 Ssngslvdo3d 91815 gScQV3HHSINIH 4 dgsdiuassv vno WIdAHSINIS _ _ 91915 VednHSINId ia a d vSngivaoau vsnaivaoau vsnalvaoau DDOI DDD 1 viva Emm H lt 0 L gt 1v
8. amie eden ra a Q Ea AEE RIET ER ES lt DE ET eee N a n o 5 5 zs 1 70 es eno me 1 lt a N a T T T 1 1 1 c gt gt N e 5 a lt lt a a e ao o o lt a a e v ui a a V 2 M lt lt lt gt gt lt 2 amp lt IDLE MLO 006388 P READCYC Y STARTACCESS READCYC IDLE STARTACCESS READCYC IDLE IDLE time during an octaword read cycle Sample timing for the octaword read cycle is shown in Figure 5 6 The timing relationships are similar to those of the The memory system must be able to transfer four successive longwords at a longword read timing Memory System Interface 5 24 Figure 5 6 Sample Design Memory Controller Octaword Read Cycle Timing mlo 004433 ps turnpage Memory System Interface 5 25 Table 5 7 DRAM Timing Parameters for 80 ns Page Mode 1M x 1 Minimum Time Maximum Parameter Name ns Time ns Row address setup time 0 Row address hold time 15 Column address setup ti
9. 1 18538 a iv 7 3 2 uM 284 ow 8r 08 ps T ozz Ly NN d 1 H lt gt 7 4 n VOXH s WOXY lt 088 T F g0 09 Hw 28 lt 6896 p 5 21 09 L ozz lt e gt Tva 91 5 60 T FORO lt p gt Yd o za z cr vi d 601H lt gt sa zd 98H koa Te UV o 5 Eco Te 1uvna 307 1 IN Dr 5998 _ Za 08 lt gt m 0273 Leid 093 080 T 4995 UAQNUL 1HV1Q 022 epo 2 i 2 NAP 66H zii Hgy 388 lt 6 gt lt gt lt lt gt lt gt lt gt or LA pr eA AS 894 zi 413 vvoS WA ISALA w eo 397 6 IA 51 2 St Zt 413 bres WA JOAUq gt dar Jojejeuec 0020 10199A 157700 44444202 01 00000202 ssejppy 10 63000 68 d3AN8X 8 9 j lt 2 8 9 59 H
10. lt 0 gt SVO lt 0 gt 181 lt 1 gt 6 lt gt 91 lt gt lt gt Svo 9 49 W410 A8 0041 HUNDw an 1 ysy ONAS 55 94 4 O24 OF 24 Lot 1 XVAL3S3H 1 159519 ZA 931 i ot 001 5 99 295 SUAE 61 2 i uo 1 usejeu 8 ___ MOVI a 9 SI dea ar SVHONAS 6l 259 0464 4 OLI 1 5 gt 0 HOQv1 YU eg H EHgOvANI DEBE ENNIO EFEHOQVANL 518246 1 DA0ASH siao Jy 5 1 ergs dE 18v 25234 v TS 5 11SH 901528 9014 9114 9915 4 21901 pesn 1940208 JON IS H PL HH WTO E 2 p M 224 H SVHONAS al v SV 170939 6 H 579 ro 1 SVH al vL gr do dii Jeziuougou sS 5 sseJppy
11. Y FINISHIACK ROMCYC4 IOREADY ENBCONDATA ENBCONDATA READCYC4 o ROMCYCG lt a No Y Y FINISHWRITE FINISHREAD Yes ENBCONDATA ENBCONDATA FINISHUP1 IOREADY IOREADY No ENBCONDATA IOREADY Y FINISHROM FINISHUP2 FINISHUP3 WRITE ACCESS LWRITE amp LBM lt lt 0 lt gt amp CONE amp SYNCHAS READ ACCESS ILWRITE amp LBM lt lt 0 lt gt 8 CONE amp SYNCHAS IACK CYCLE CONIACK CPUST amp SYNCHAS ROM ACCESS LWRITE amp SELROM amp SYNCHAS MLO 004442 The ENBVECTOR signal is asserted when DS asserts driving the vector onto the DAL bus When in the IDLE state and CONIACK is asserted the console state machine jumps to the state and to ACKCYC2 The state machine checks the state of P3P4 to synchronize with the rtVAX 300 and asserts IOREADY ending the cycle The rtVAX 300 reads the vector that was driven onto the DAL bus and uses it as an offset into the system control block SCB to determine the location of the interrupt service routine for the console Console and Boot ROM Interface 6 5 Figure 6 3 Sample Design Interrupt Acknowledge Cycle Timing P2 P2 P2 P1 P2 P2 P1 P2 CLKA H
12. 5 8 Memory Management Unit 5 9 Memory System Design 5 9 1 Address Decoder 5 9 2 Address Eatches 5 9 3 DRAM Memory 5 9 4 DRAM Row and Column Address Multiplexer 5 9 5 4M Byte DRAM Array 5 9 6 DRAM Terminating Resistors 5 9 7 DRAM Data Latches 5 9 8 Memory Controller State 5 10 Memory Timing 5 5 10 1 Calculating Memory Access 5 10 2 State Machine Input Setup 4 34 4 36 4 36 4 41 4 41 4 41 4 42 4 42 4 43 4 43 4 44 4 44 4 44 4 44 4 45 4 46 4 48 4 50 4 50 eat et ea 1 ny 5 22 5 10 3 5 10 3 1 5 10 3 2 5 10 3 3 5 10 3 4 5 10 4 5 10 4 1 5 10 4 2 5 10 5 5 10 6 5 10 7 5 11 5 11 1 5 11 2 Memory Subsystem Longword and Quadword Read Cyde is Po du Ae ae oso Calculating DRAM Row Address Setup Time Calculating DRAM Row Address Hold Time Calculating DRAM Column Address Setup Time
13. MLO 004463 meets the 500 VAC RMS isolation requirement of Standards IEEE 802 3 and ECMA 97 general more than one value may be required and two to six parts may have to be connected in parallel to achieve a low enough impedance at all frequencies of interest total capacitance must not exceed the limit imposed by IEEE 802 3 0 01 This requires some experimentation and testing at the EMC test sites The etch used to connect the BNC shield contact and the chassis ground to these capacitors must be very thick and very short for the capacitors to be effective The 1M resistor required by the IEEE 802 3 10Base 2 ThinWire Standard between isolated ground and chassis earth ground removes static electricity buildup but does not protect from ESD effects The best solution for ESD protection is two 400 VDC bidirectional transorbs similar to back to back zener diodes in series This retains the required 500 VAC RMS isolation but protects against ESD voltages above 800 VDC The connection requirements for the transorbs are similar to those for the capacitors that is very short and very thick etch 7 18 Network Interconnect Interface 7 6 3 3 Power Ethernet interface requires two supply voltages 12V and 9V The following are the specific requirements for each supply 12V The 12V supply must be between 11 28V and 15 75V This supply is referenced to AUI voltage return This 12
14. 14 DMRL request 17 RST Reset A18 HLTL Halt processor A19 PWRFL L Indicates loss of AC power A24 A21 IRQ lt 3 0 gt L User defined interrupt request lines A25 L 26 L 1 0 2 27 ERRL 1 0 7 28 DSL O Z Data strobe A29 WRL O Z Read Write A30 ASL O Z Address strobe continued on next page Technical Specification 2 9 Table 2 2 Cont rtVAX 300 Processor Pin Description Pin Signal Definition Function A36 XMT Thickwire transmit data A38 Thickwire transmit data A40 RCV Thickwire receive data A42 RCV Thickwire receive data 44 COL Thickwire collision detect A46 COL Thickwire collision detect B1 CLKIN System dock input B2 CLKA Clock A output B3 CLK20 20 MHz clock output B4 CLKB Clock B output B10 B7 CSDP lt 3 0 gt L 1 0 7 Control status and parity information 11 CSDP lt 4 gt O Z Ethernet interrupt acknowledge cyde B12 DPEL 1 0 7 Data Parity Enable B48 B33 DAL lt 31 00 gt 1 0 2 Data and address multiplexed bus B30 B15 H Note TTL inputs have an internal 2K 2 pull up except CLKIN Signal designations are as follows Signal Designation Meaning Input O Output OD Open drain bidirectional 2 Tri stateable bidirectional outputs are driven by the ACTQ 244 or ACTQ 245 buffers 2 10 Techni
15. lt gt lt gt lt 4 gt lt gt lt 6 gt 001 i L 8 1 lt gt daso lt gt lt 2 gt 1 lt 92 gt 1 0 lt gt lt 82 gt 1 0 lt 62 gt 1 H lt 06 gt 1 0 lt 16 gt 1 1 lt 6 gt lt gt lt 2 0 gt lt gt 62 NvH lt 0 gt lt gt VH 001 287 00 T T 1 4136 1 HOIOSASN3 doi oa 2 NIINI va 10 0d 2 SVHONAS 19 150 ang pad 4 uspe za TEAN ONAS 5058 __ 1158 ZA 9 3 05 lt 2 gt 1 4 80 OvIOI k eva zi A m T 869139
16. lt 6 gt 001 T 2 L gl 8 1 lt 0 gt 59 lt 0 gt 1 lt gt lt 2 gt lt 2 lt gt 1 lt 9 gt 7 lt gt gt 1 lt 0 gt 4 0 NVH lt gt lt gt lt gt lt gt VH lt 9 gt Z NVH T3llHMAVHG gt 1 lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt 4 gt lt gt lt 6 gt 001 L 8 8 al 7 4 gt 59 8194 lt 6 gt 1 H lt 0 gt lt gt lt gt lt gt H lt t gt va H 1 lt 1 gt lt 8 gt lt 6 gt lt 0 gt VH lt gt lt 2 gt I NVH H lt t lt SL gt WVY pesn 1 spuedep JO 10 16 900 O IN T31lHMAVHG lt gt 1
17. with the consequent reduction of memory system performance The rtVAX 300 octaword access always requires at least two 5 for each longword that is transferred memory performance and longword read cycles are not improved by these latches 5 9 8 Memory Controller State Machine Figure 5 4 shows a memory controller state machine diagram This machine has the following responsibilities e Arbitrate between refresh requests and memory access refresh requests have priority Execute refresh requests by cyding the REFCYC ENBCAS and RAS lines e Execute memory access cycles by cycling RAS ENBCAS DRAMREADY INVADDR 3 27 Memory System Interface 5 17 e Provide the precise timing that is required on the DRAM RAS and CAS lines Refer to Figure 5 4 for the following discussion Every 12 8 us the refresh counter asserts its TC L output This sets the refresh request latch shown in Figure 5 12 The latch asserts the REFREQ input of the memory controller The controller now jumps to the STARTREFRESH state and asserts ENBCAS and REFCYC asserting every DRAM CAS line The assertion of REFCYC clears the refresh request latch deasserting REFREQ Next the memory controller asserts RAS waits one clock tick and deasserts ENBCAS and REFCYC The state machine now jumps into the FINISHUP state and deasserts RAS so the refresh cycle is now finished The AS signal of the rtVAX 300 is synchronize
18. 0 0 0 1 1 0 1 1 Alignment error Translation Not Valid When set indicates that a translation error occurred when the Ethernet coprocessor was translating a VAX virtual buffer address It will only set if RDES1 30 was set Reception process remains in the running state and attempts to acquire the next descriptor Frame Type When set indicates the frame is an Ethernet type frame Frame Length Field gt 1500 When clear indicates the frame is an IEEE 802 3 type frame Meaningless for Runt frames 14 bytes Collision Seen When set indicates the frame was damaged by a collision that occurred after the 64 bytes following the SFD Frame Too Long When set indicates the frame length exceeds the maximum Ethernet specified size of 1518 bytes Note Frame Too Long is only a frame length indication and does not cause any frame truncation Last Segment When set indicates that this buffer contains the last segment of a frame and status information is valid First Segment When set indicates that this buffer contains the first segment of a frame continued on next page Hardware Architecture 3 69 Table 3 30 Cont RDESO Fields Bit Name Description 10 11 13 12 14 15 30 16 31 LE ES OW Buffer overflow When set indicates that the frame has been truncated due to a buffer too small to fit
19. 1 lt gt 9 lt 6l 2 821 01022 AN gana nab E 1 avauWou diHO N3 D 92 ps ve avaduWou lt gt sae lt 91 gt 7 OH ps HW 6 H Ns 8 8 1 Heady H sgeudavi v C 8 H amp HdQv1 eo iani C j H lt gt Li 2 H szi Haavi EO H lt gt 387 9 uaavi 9 8 gt 8X8Z L 2 lt gt 1 L WOHdAR J rz lt 0 gt 71 PvIvaWou si I ova LA lt gt si a Ws ev1vaWou 2 izva lt gt lt S gt VLVGNOH 6 vici lt 9 gt 02 eed TOO H PvivdWod 1 p Ast dd zL naor B 2 5 nnd EE ve 1 B lt gt lt 221 0
20. 2708 lt 9 gt 14374 2 9 22 1 2 25 z uaavi lt gt lt gt lt gt lt lt e uaavi lt gt lt 9 gt lt gt lt lt 6 gt 1 lt gt 2 lt gt SVH 42 lt 8 gt 2 lt gt 22 lt 6 gt wu lt 6 gt H lt 6 gt 0r2Haav1i 02 uaavi lt gt 127HQQV1 1 5 2 1374 LL SYO 31IHM SVH INVHG 827700 ET H WvHTIS il 13 49 ai gi H 159 LO gi are uoje1 Apeoy 1 3dd11998N3 v 6 T3 5 28 gi L 7850S 1190 2 EM di 1 3NO9 ai 1 eu s 1 00484 SIOAUG Jda 1199 8 025 1 SVHONAS L
21. Sample Design ROM Read Cyde Timing Sample Design Processor Status Display Sample Design Console Interface Sample Design User Boot ROM Bank 1 with Drivers Sample Design User Boot ROM Bank 2 Application Module Address Decoder Memory Map Network Interconnect Controller Block Diagram Network Interconnect Isolation Transformer and lino c TD Network Interconnect Ethernet Interface Block Diagram 4 42 4 49 5 6 5 10 5 14 5 19 5 24 5 25 5 29 5 31 5 33 5 35 5 36 5 37 5 39 5 40 5 41 6 13 6 15 6 16 6 17 6 20 6 22 6 24 6 26 6 27 7 3 7 4 7 6 7 4 7 5 Network Interconnect Network Interconnect Network Interconnect Network Interconnect Network nterconnect Device Interfacing Device Interfacing Device Interfacing Device Interfacing Q22 bus Map Register DP8392 Chip Block Diagram Transceiver BNC Connector and Conector t DC DC Converter Layout of ThinWire Medium Interfaces roues tt dA eb due Heat Spreader Address Latches Address Decoding Block Diagram Interrupt Daisy Chain Block vues Bee Rab bats bee os DMA Read CycleTiming Q22 bus to Main Memory Address Translation Device Interfacing DSP and
22. 7 4 7 6 Hardware mplementation Example 7 5 7 6 1 Ethernet Interface An 7 5 7 6 1 1 Functions of the Ethernet Interface 7 6 7 6 1 2 DP8392 Transceiver 7 7 7 6 1 2 1 Transceiver Chip 7 7 7 6 1 2 2 Interface sls e D RR E RMDE 7 8 7 6 2 Implementation of Design 7 9 7 6 2 1 ThinWire 7 9 7 6 2 2 Layout 5 7 11 7 6 2 3 Typical Ethernet Board Parts 15 7 11 7 6 2 4 DC DC 7 12 7 6 3 Ethernet Interface Detailed Design Considerations 7 14 7 6 3 1 Differential Signals 7 14 7 6 3 2 DP8392 7 14 7 6 3 2 1 External lt 7 14 7 6 3 2 2 Layout 5 7 15 7 6 3 2 3 Additional ThinWire Application Hints 7 17 7 6 3 3 POWER ou uda I oe Y greco Rte ER od en A 7 19 7 6 3 4 Grounding 7 20 7 6 3 5 Isolation 7 21 8 Device Interfacing 8 1 Device 8 1 8
23. lt 0 gt lt 0 gt 1 V8ON3O vV8ON3O 54 Otz Diz vaNd tz SVON3O SVON3O 07 SvN3E SVN3OTL ov p ov ov o og g EP 08 og E Y iV Woy ig ig zv V gt 5 gt s gt v gt 9 Em 8 o va 8i va va SV Dy Sv SV gt 9 9V 9v N 3 98 98 98 LY Dr lv 193 i 63 199 z 579397 HAOSNUL HAOSNUL 1220 PO 1220 488 Jag 488 FP Sv 9v 49 753 HAOSNuL LV lt 8 Gl gt vlvddSd 388 m 1 001 994 88 700 1
24. z Ws ge H 2 Heady 3 devi seva 9 Mey 82 eH Lady gt Xe wa l HOQvi lt agr C 66 lt 8XA8Z L lt gt Na Dar gi Mp lt 8 gt 1 6 v1vdWou 7 Iv og OH seva LA 0l VIVdWOH 5 Us lt 2 lt 6 gt lt 21 gt 1 8 lt gt 1 P v1vaWo m lt gt 02 EO mevv AY 0l 8L 9 Pd 0 1g 0 Na 22 EU v 1 0 5 gt LA 9L H lt 6 H gt s 8 LL H 39 H lt gt s 6 Hdavi A 8 H gt IE Aey brzdy lt 2 gt 8 i Hdavi lt gt dav lt 0 gt
25. 2 Jeyng 1120 lt 1Svu 1 Jeyng 8120 SVO PU 31IHM SVH 22 1 1109135 98 1 2 H 2HQQVANI B vl lt 2 gt 90 1 lt 0 gt y lt gt varfe H gt 984 5 9 vl lt 6 gt amp a0 995 lt gt lt zz Lo p lt gt lt gt lt n H rr udavi zz Liga s uaavi lt lt 2 sr uaavi 300 lt 9 gt H lt gt 22 193 lt gt 8 2 9 lt 91 gt AS H lt gt 22 lt gt H lt gt lt gt H lt 9 gt 22 H lt 8 gt H lt 9 gt lt gt lt 4 gt 22 H lt 6 gt gt H lt 6 gt lt 8 gt 2
26. H va i 1A0v3udsa P t Bm iyd bd zd hd Ed Sd bd ird 4 24 14 74 69 2911 8 pd Ed Ld idi Ed 2919 1294 Ld ird 64 29 19 Ld ird 9 29 bd vd 14 vd 14 vd Ed Zd 14 bd Ed Zd 14 td Ed 14 bd Ed Zd 14 bd Ed 14 Zd 14 bd Ed 14 vd Ed Zd 14 bd d id td d 14 Y6 900 O1N lt gt lt 0 gt 7 lt gt lt 8 9 gt gt lt gt lt lt 2 16 gt 1 0 v 81 8 lt 30 8 lt 8 lt 30 v lt lt lt lt dett v 81 8 v 30 V 8 30 318vN3 318VN3 00 NI 110 zrna 400 MP 0 gt lt zena 100 lt gt 110 M
27. lt 0 gt 182 pesn 944 uo spuedep JO 10 lt 6 gt 001 L 0 00 lt 91 gt 7 E 19 Hua vL al H ei va TWVHSTSVNS lt 6 gt 7 9 5 023 8r oz iva TSM PERS H SVHONAS HEIN lt 22 gt 7 lt gt lt 0 gt lt 0 gt 4 50 lt 2 gt 7 lt gt 1 lt 1 gt 4 50 lt gt 1 lt 2 gt 1 2 daso 92 1va 1 lt gt 1 lt gt 4 lt gt lt 82 gt 774 lt 62 gt 1 lt gt 1e 1va 388 215122 7 19 8 388 215121 10 8 388 lt 91 gt 1 gt lt 8 gt lt 6 gt lt 02 gt Ic WNVH ee WNvd 71 AQUIN lt gt lt gt lt 92 gt lt gt lt gt lt 0 gt 1 lt gt lt gt lt gt lt gt lt gt 1 lt 9 gt 1 lt gt lt 8 gt 1 lt 6 gt 1 017
28. 1 lt 1 gt 40592 lt 8 gt 1 0 lt 6 gt 1 H lt gt lt gt lt gt lt 6 gt lt t gt va H 1 lt 1 gt lt 8 gt lt 6 gt lt 01 gt lt gt eI NVH I NVH lt gt SL VH 08 700 lt 2 gt 5 1 lt gt lt gt lt gt lt gt lt gt lt gt lt 9 gt lt 4 gt lt gt lt 6 gt 001 ji L gl 8 1 lt gt 4 82 lt gt lt gt H lt gt 1 lt 12 gt 1 ee va lt 62 gt 1 0 1 lt 2 gt ZI NVH 8I NVH lt 6 gt 9 lt gt ee WvdH lt gt 1 lt gt lt gt lt gt lt gt lt gt
29. lt S gt VLVddSd lt 9 gt VLVddSd lt 4 gt 1 lt 8 gt e v1vadsa lt 01 gt 1 45 lt gt lt 21 gt 1 45 lt gt lt gt lt 4 gt o 1 5 1 lt 0 gt gt lt gt lt gt lt 7 gt lt gt lt 9 gt lt gt lt 8 gt lt 6 gt H 01 lt gt 487700 175024155 oA 1 lt gt 4 si lt 2 gt 4065 vip A i e 21 4 lt 6 gt 4069 Jay lt 0 Le gt 3 054 08237 N39 lt 8 gt 1 5 293 08cdvZ N3O HVd N3 aaea 2199 4ayng 1220 lt 8 gt 1 0450 001 288 lt gt
30. 1 The actual contents at the location 20040000 is a branch instruction FIRMWARE 4 5 4 2 System Firmware Entry The firmware checks for a power on entry to see if it should execute the power on self test If the firmware finds no power on entry it passes control to the dispatch code shown in Example 4 1 which examines and dispatches according to the halt code set by the hardware at entry the halt action fields stored internally and the restart in progress and bootstrap in progress bits Example 4 1 Firmware Dispatch Code if halt then elseif halt code external halt then halt else endif 4 6 FIRMWARE code power on CPMBX hlt act 03 CPMBX hlt swx 03 BOOTDEV lt 2 0 gt BOOT lt 2 0 gt if user_init code present then call user_init code if BOOTDEV lt 2 0 gt 0 then halt else boot according to BOOTDEV lt 2 0 gt endif case CPMBX lt hlt_act gt 0 CPMBX lt hlt_act gt CPMBX lt hlt_swx gt restart 1 CPMBX lt hlt_act gt CPMBX lt hlt_swx gt restart 2 CPMBX lt hlt_act gt CPMBX lt hlt_swx gt 3 CPMBX hlt act CPMBX hlt swx halt continued on next page Example 4 1 Firmware Dispatch Code restart if restart in progress then display restart error message boot else set restart in progress do restart endif boot if bootstrap in progress then display boot error message halt else set bootstrap in
31. 9 1 Wess 9 sn 821 9 m 1 7 vo 5 OSHS HSV 9 S 1 SV gi 703 er 1 XWALSaH L bl Sc 155 gr Q gr yc IE HQdv1 H 0 HOQVY1 955 ec HOIQVAN 11909 z Ee H 990 8r 1 vL ES 3949438 shag Obs Add pue 1199 8 pZ H SVHONAS v 7 154 wg HONNOS 9014 9114 91815 4 1 SVO8N3 9Jeu 194205 JON WIS 0 SVO 1 lt 0 gt 81 5 0 vL zr 004 2 al id gi OF E gt i 004 0048 lt 4 gt 5 0 94 Ps 1 H SVHONAS 9 D SES gi HLOH al 1 102136 c b o 3 SvH 7 1 SVH lt gt 5 0 a vL 004 9 lt gt 9 vL Jeziuoujou S al 4 4 Svo 06 900 O IN T31lHMAVHG lt 0 gt 5 1 lt gt lt gt lt gt lt gt lt gt lt gt lt 9 gt lt 4 gt lt gt
32. 78 994 0 254 3 110 in 0 010 in MLO 004497 Physical Electrical and Environmental Characteristics 5 Figure 4 rtVAX 300 Side View 5 842 mm 0 127 mm 0 230 in 0 005 in 2 286 mm 0 127 mm 2 536 mm 0 127 mm 0 090 in 0 005 in 0 090 in 0 005 in 8 636 mm 0 254 mm 0 340 in 0 010 in MLO 004498 A 6 Physical Electrical and Environmental Characteristics A 2 Electrical Characteristics The following tables summarize the rtVAX 300 processor s electrical characteristics Table A 1 Recommended operating conditions Table A 2 DC characteristics Table A 3 AC characteristics Table A 1 Recommended Operating Conditions Symbol Parameter Minimum Typical Maximum Units Vcc Power supply voltage 4 75 5 0 5 25 VDC Vi Input voltage 0 Vcc VDC Vo Output voltage 0 Vcc VDC Ta Operating free air temperature 0 25 0 70 01 C 1 To operate at temperatures up to 60 C the 300 requires an airflow of at least 508 mm s 100 across the processor to operate at temperatures above 60 C the rtVAX 300 requires an airflow of at least 1000 mmys 200 LFM across the processor Table A 2 DC Characteristics Symbol Parameter Minimum Maximum Units Vih High level input 2 00 V Vil Low level input 0 8 V Voh High level output Ioh 24 mA 3 76 V Vol Low level output Ioh 24 mA 0 36 V li Input leakage current 0 1 10
33. LADDR 16 H LADDR 15 lt 14 gt LADDR 13 H LADDR 12 LADDR lt 11 gt H LADDR lt 10 gt H LADDR lt 31 gt LADDR lt 30 gt ASL LADDR lt 9 gt LADDR lt 8 gt LADDR 7 LADDR lt 6 gt LADDR lt 5 gt LADDR lt 4 gt LADDR 3 LADDR 2 lt 3 gt L lt 2 gt L BM lt 1 gt L lt 0 gt L DAL lt 31 gt DAL lt 30 gt DAL lt 21 gt DAL lt 20 gt DAL lt 19 gt DAL lt 18 gt Address Latches 8BF 8 Bit Latch 74F373 8 Bit Latch 74F373 5 36 Memory System Interface LAD LAD LAD LAD LAD LAD LBM lt 3 gt L LBM lt 2 gt L LBM lt 1 gt L LBM lt 0 gt L LWRITE L DR lt 31 gt H DR lt 30 gt H DR lt 21 gt H DR lt 20 gt H DR lt 19 gt H DR lt 18 gt H MLO 004436 Figure 5 12 Sample Design Memory Controller mlo 006376 ps fol dout Memory System Interface 5 37 5 38 Memory System Interface Figure 5 13 Sample Design DRAM Memory Array 1 mlo 006390 ps turnpage Memory System Interface 5 39 Figure 5 14 Sample Design DRAM Memory Array 2 mlo 006391 ps turnpage 5 40 Memory System Interface Figure 5 15 Sample Design RAM Data Latches mlo 004440 ps turnpage Memory System Interface 5 41 5 11 2 Memory Subsystem Sequencer State Machine PAL The memory subsystem sequencer
34. Calculating DRAM Column Address Hold Time Memory Subsystem Octaword Write Cycle Timing Calculating Data In Setup Time Calaulating Data In Hold Time Memory Subsystem Refresh RAS Precharge Time DAL Bus Turnoff Memory System Illustrations and Programmable Array Logic Application Module Address Decoder PAL Memory Subsystem Sequencer State Machine PAL 6 Console and Boot ROM Interface 6 1 6 1 1 6 1 2 6 1 3 6 1 4 6 1 4 1 6 1 4 2 6 1 4 3 6 1 4 4 6 1 5 6 1 6 6 1 7 6 2 6 2 1 6 2 2 6 2 3 6 2 4 6 2 5 6 2 6 6 2 7 6 2 8 6 3 6 4 Console System Console 55 Console State Console Interrupt Acknowledge Cycles Console Timing 5 Console Address Setup and Hold Times Console Data Turn Off Time Console Read Cycle Timing Analysis Console Write Cycle and Data In Setup and Hold Timing Analysis HL ERU UR GR PLE ConsoleOsdllator Line Drivers and Receivers Console Break Key Support Boo
35. L longword Address qualifiers V virtual memory P physical memory internal register G general purpose register M machine register 4 12 FIRMWARE Miscellaneous qualifiers N lt COUNT gt repeat count U unprotect the absence of an access or address qualifier the previous qualifier 15 used Specification of conflicting qualifiers is an error and an appropriate error message is displayed the command is ignored The effect of miscellaneous qualifiers U and N does not persist beyond the command in which they are typed The U unprotect qualifier allows access to almost any address Without the U switch a protected deposit or examine can only access memory that is reflected in the PFN map or physical addresses between 20000000 and 3FFFFFFF Address The address is specified in hexadecimal A missing address is treated as a Supported symbolic addresses are as follows is the location last referenced in an examine or deposit operation 015 location addressed by the last location referenced in examine or deposit operation This reference cannot be to a general register 15 the location immediately following the last location referenced an examine or deposit operation For references to physical or virtual memory spaces the location referenced is the last address plus the size of the last reference 1 for byte 2 for word 4 for longword s th
36. MRA2 Channel A dock select register CSRA Channel A command register CRA Channel A transmit holding register THRA Auxiliary control register ACR Channel A B interrupt mask register IMR Counter timer interval register upper CTUR Counter timer interval register lower CTLR Channel B mode register MRB1 MRB2 Channel B dock select register CSRB Channel B command register CRB Channel B transmit holding register THRB Reserved register Output port configuration register OPCR Set output port bits command register Reset output port bits command register 3 5 3 Memory System Control Status Register To support systems with multiple processors sharing the same memory the rtVAX 300 s automatic memory system testing can be disabled Digital recommends that the memory testing be enabled so that the firmware can build a realistic page frame bitmap Disabling the memory tests has the advantage that self tests will finish very quickly however the disadvantage of doing this is that the page frame bitmap that is built lists all pages as good The firmware will not have tested each page and bad pages will not have been Hardware Architecture 3 43 found and might be used by the VAXELN kernel In addition if parity or ECC memory has been implemented read cydes to locations that have not been written to will cause parity error machine checks An external memory system control sta
37. ig V Si VIVdWou ig V ez vivaWou ig V ie vivdWou ig v 013 EU 013 013 NOH dAn 344444202 00008202 yueg 1009 1957 587700 2 ZHN 00 pue 10 SPIOM 9 8H 8 2110919 gr 1099 1110919 a ONAS 1 HONAS 1 S2 Ogr Os PAVHSO Dr 1 sI AVHSO 15 onpi 581 ooi 58 5 0 E IMP IMO MOr IMP 7 lt gt 1101980 m 1 0v ov ov ov ivi LV 5 Iv IBI Ws eS We wes 9 ge 9 v g 51958 gt 698 2 194 Sry 9 9 9 1 Sadsa 8c gt Why 1 Sv Sv Sv Sv
38. lt 20 gt lt 19 gt lt 18 gt lt 17 gt lt 16 gt MRDY L DAL 31 DAL 30 DAL 29 DAL lt 28 gt DAL 27 H DAL 26 DAL 25 DAL 24 L 23 H L 22 H L 21 H L 20 H L 19 L 18 lt 17 gt H L 16 lt 3 gt L lt 2 gt lt 1 gt L lt 0 gt L MRDYL SYNCHAS H LWRITEL SELRAM H IACK L CLKA H 74 Foo 2 E1 CSDP lt 3 gt L CSDP lt 2 gt L CSDP lt 1 gt L CSDP lt 0 gt L 1B DRIVERAM L MLO 004481 Device Interfacing 8 35 8 36 Device Interfacing Figure 8 19 l O Device Interfacing Console Interface mlo 004482 ps fol dout Device Interfacing 8 37 8 38 Device Interfacing Figure 8 20 Device Interfacing User Boot ROM Bank 1 with Drivers mlo 004483 ps fol dout Device Interfacing 8 39 8 40 Device Interfacing Figure 8 21 l O Device Interfacing User Boot ROM Bank 2 mlo 004484 ps fol dout Device Interfacing 8 41 8 42 Device Interfacing Figure 8 22 Device Interfacing DSP and Private RAM mlo 004485 ps fol dout Device Interfacing 8 43 8 44 Device Interfacing Figure 8 23 Device Interfacing DSP Loader ROM
39. lt 62 gt 1 lt 9 gt 1 lt 1 gt 0 lt 22 gt 1 0 v1vdWOH 0 PvIVdWog mz x H SI VIVdWOH p eB ee vivdWod a AY H Ie vivaWou z on NOYAN IWOwdAn 44444202 01 00008202 sseuppy 68 700 dav 44028 919 T 4909 819 xg9 2 994 lt 7 Leu ea 9 961 L 96L 8 bo Z 8 81H sq lt 3 4189 gt 20 12944 g600 930 LO ZO santo 999 M 029 d 68 001 ADS 229 612 _ P T A 2081991 19410 0 punoJ5 e Ajddns samod M 9160 pe1oeuuoo punog e MS SO ON 497700 ZdMHSINI4 zdnHSINI sviH3sSsv gi 1949553995 1040558007 290797
40. mee lt gt S lt y lt gt JONA v aS lala E lt gt 62 H lt gt 62 lt gt H zZi Hdavi 38v gH iS lt 81 gt 2 gi NONE gt Sog H lt gt NOYAN NOYAN lt 8 gt 71 i Ov lt b gt VIVGNOH i 0A H 0A Na 6 e vIVaWoH vi gea 6 H lt 25 1 vi RR H XOPVIVONOH 51 MET lt 925 1 ST 1 62 n e lt gt 1 Zi zy I vIVaNod zi ees gH 80 6 sk H SVG E EPVIVOWOH 8i 6 SP VIVOWOH 8i m ERAI EPVIVdWOH 62 VIVOWOH 61 158 H lt 02 H lt gt 02 A 5 SPVIVaNOH v H lt revivawod OY 290 873 ERO 183 9x3iget dar WWoudanl dar gt
41. write the data into main memory if it exists and cause the second longword of the quadword to be written into the longword of the cache data array that corresponds to the address of the first longword of the destination irrespective of whether or not a cache hit occurred The data in the longword of the cache data array that corresponds to the address of the second longword of the destination remains unaltered addition errors generated during write references which would normally cause a machine check are ignored they do not generate a machine check trap or prevent data from being stored in the cache Hardware Architecture 3 37 Diagnostic mode is intended to allow the internal cache tag store to be fully tested without requiring 512M bytes of main memory This mode makes it possible for the tag block in a particular cache entry to be written with any pattern by executing a instruction with bits 28 9 of the destination address equal to the desired pattern Two instructions one with a quadword aligned destination address and one with the next longword aligned destination address are required to write to both longwords in the data block of a cache entry Diagnostic mode does not affect read references Note At least one read reference must occur between all write references made in diagnostic mode Diagnostic mode should be selected when one and only one of the two sets is enabled Operation of
42. 3 66 Hardware Architecture Note The Ethernet coprocessor first reads the descriptors ignoring all unused bits regardless of their state The only word that the Ethernet coprocessor writes back is the first word XDESO of each descriptor Unused bits in xDESO are written as 0 Unused bits in xDES1 xDES2 and xDES3 may be used by the port driver and the Ethernet coprocessor will never disturb them A data buffer can contain an entire frame or part of a frame but it cannot contain more than a single frame Buffers contain only data buffer status is contained in the descriptor The term data chaining refers to frames spanning multiple data buffers Data chaining can be enabled or disabled in reception through CSR6 072 Data buffers reside VAX memory space either physical or virtual Notes 1 The virtual to physical address translation is based on the assumption that PTEs are locked in the rtVAX 300 memory during time the Ethernet coprocessor owns the related buffer 2 For best performance in virtual addressing mode PPTE Processor Page Table Entry vectors must not cross a page of the PPTE table 3 6 2 1 Receive Descriptors Figure 3 28 shows the format of Receive Descriptors Table 3 30 through Table 3 33 describe the RDESx bit structures The RDESO word contains received frame status length and descriptor ownership information Hardware Architecture 3 67 Figure 3 28 Receive Descriptor Format
43. Ne Se Se Ne 5e e sbttl Module Declarations INCLUDE FILES kermac library symbol definitions Scpu300def define rtVAX 300 specific offsets registers etc starlet library symbol definitions Sdscdef define memory bitmap descriptor D 2 User Boot Diagnostic ROM Sample 5 macro to define rom code or read only data program section usrom share psect alignment long psect usrom zcode pic rd nowrt quad list meb align psect alignment endm usrom share EQUATED SYMBOLS rtVAX 300 board level test flagword fields vield 300 0 lt btf_testcmd 1 m gt lt btf_powerup 1 m gt lt btf_fatlerr 1 m gt upon failure lt btf_consdev 1 m gt lt btf_dsply Sdef Sdef Sdef Sdef Sdef Sdef Sdef Sdef Sdef Sdef Sdef Sdef 5 lt 1 gt define test flagword fields explicitly invoked by TEST command test invoked by power up sequence test returns control immediately console slu is present led display is present reserved always read as 0 5 rtVAX 300 console program read write data offsets 300 b cpmbx 0 console program mailbox _300Sb_cpflg 1 console program flags 300 b bootdev 2 default boot device rtVAX 300 user boot diagnostic ROM offsets ini _300Susrom LOCAL 0 30051 usrom res
44. Rr ome 3 6 4 Serial Interface 3 6 4 1 Transmit 3 6 4 2 Receive 3 6 5 Diagnostics and Testing 3 6 5 1 Error Reporting uerius le RIDE RP 3 6 5 2 On Chip Diagnostics 3 6 5 2 1 Internal 3 6 5 2 2 Loopback 3 6 5 2 3 Time Domain 4 FIRMWARE 4 1 System Firmware ROM 4 1 1 System ROM Part Format 4 1 2 System ROM Set Format 4 2 System Firmware 4 2 1 Restart e Baca inca eee d ele 4 2 2 BOOD sis SIS E did 4 2 3 Haltia haee Bade ahah Gace ae ewe tede eset ds vi 4 2 4 2 4 4 4 6 4 7 4 7 4 8 4 3 4 3 1 4 3 2 4 3 3 4 3 4 4 3 5 4 3 6 4 3 6 1 4 3 6 2 4 3 6 3 4 3 6 4 4 3 6 5 4 3 6 6 4 3 6 7 4 3 6 8 4 3 6 9 4 3 6 10 4 3 6 11 4 3 6 12 4 3 6 13 4 3 6 14 4 3 6 15 Console Program Entering the Console Program Compatible Console Interface Entering and Exiting from Console Mode Console Kays saires ini kidsa a ia Console Command Syntax Conso
45. Signal Meaning 45V 5V power supply ASL Address strobe lt 3 0 gt Byte masks BOOT lt 3 0 gt Boot select pins BTREQL Ethernet coprocessor boot request signal CCTL L Cache control for cache invalidation and selective caching CLK20 20 MHz dock output CLKA CLKB CPU dock outputs CLKIN System dock input signal COL 4COL Ethernet collision detect differential pair CSDP lt 4 0 gt Control status data parity DAL 31 007 Data and address lines DMGL Direct memory grant DMRL Direct memory request DPE L Data parity enable DSL Data strobe ERRL Bus error input GND 5V ground return HLT L Halt processor interrupt INTIM 10 ms timer 100 Hz 50 duty cycle output IRQ lt 3 0 gt L Interrupt request PWRFL L P owerfail RCV RCV Ethernet receive data differential pair 2 8 Technical Specification continued on next page Table 2 1 Cont Bus Interface Signals Signal Meaning L Bus ready input RSTL Reset input WRL Read write XMT 4XMT Ethernet transmit data differential pair Table 2 2 rtVAX 300 Processor Pin Description Pin Signal Oui Definition Function 1 15 A31 GND 5V ground return B14 B32 B50 A2 16 A32 B5 5V 5V DC power B13 B31 B49 A6 A3 BOOT 30 L Defines the boot device A7 BTREQL OD Remote Ethernet boot request from the coprocessor A8 INTIM 100 Hz interval timer clock output A12 A9 BM lt 3 0 gt L O Z Byte masks 1 DMG L
46. Storage 10 to 95 noncondensing Altitude Operating and storage as they relate to altitude standard atmosphere and standard gravity are as follows Operating The rtVAX 300 can operate at an altitude of up to 2 4 km Storage The rtVAX 300 is not mechanically or electrically damaged at altitudes of up to 4 9 km e Shock and vibration N onoperating tolerances as follows Mechanical shock 30 G 11 ms 1 2 sine pulses Vibration sine 5 G peak up to 2000 Hz Vibration random 0 032 g Hz up to 2000 Hz where 9 the gravitational acceleration constant squared where the gravitational constant is 9 8 meters sec sec 32 2 feet sec sec e Contamination The rtVAX 300 should be stored and used in noncaustic environment A 10 Physical Electrical and Environmental Characteristics Acronyms This appendix defines the acronyms used most frequently in this guide Acronym Definition 5V 5 V DC power 20MHz 20 MHz clock output ACR DUART auxiliary control register AS Address strobe bus interface signal ASTLVL AST level internal processor register BM Byte masks BOOT Boot select setup pins BTREQ Request reboot output from Ethernet controller signal CADR Cache disable internal processor register CAS Column address strobe CCTL Cache control bus interface signal CFPA 5 floating point coprocessor CLKA CPU dock outputs bus interface signal CLKB CPU dock outputs bu
47. Technical Specification 2 43 Figure 2 17 illustrates the octaword cache invalidate cycle Figure 2 18 illustrates the quadword cache invalidate cycle Figure 2 17 Octaword Cache Invalidate Cycle CLKA P1 P1 P3 P1 P1 CLKB P4 P2 P4 4 DAL ADD MLO 006379 2 44 Technical Specification Figure 2 18 Quadword Cache Invalidate Cycle CLKA P1 P3 1 1 P3 P1 P3 P3N 4 P2 P4 P2 CLKB DMA DAL ADD MLO 006329 Technical Specification 2 45 3 Hardware Architecture This chapter discusses the hardware architecture features of the rtVAX 300 processor The VAX Architecture Reference Manual discusses VAX hardware architecture in general and in detail The rtVAX 300 processor implements a compatible subset of the VAX architecture Visible machine state consists of virtual and physical memory 16 general purpose registers the processor status word and 16 system registers The instruction set architecture responds to all 304 native mode VAX instructions Of these 251 are implemented in the microprocessor and the remaining 53 instructions may be implemented through software emulation of which 21 are assisted by the chip s microcode data types are recognized Of these nine are implemented in the microprocessor byte word longword and quadword integers variable length bit fields variable length character str
48. lt gt lt gt lt gt lt gt lt gt lt gt lt 9 gt lt 4 gt lt gt 8 9 1 lt 2 gt 40592 lt gt H lt 81 gt 7 H lt 02 gt 7 H lt 12 gt 1 lt 22 gt 7 ec 1 lt 2 gt lt 9 gt lt 41 gt NVH 8I NVH lt 61 gt lt e gt WVd ee WvdH lt gt lt 6 gt 001 T L T3llHMAVHG SVONWVHG 1 lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt 4 gt lt gt 8 9 1 lt 6 gt 40592 lt 2 gt 1 lt 92 gt 1 0 Ze lt 62 gt 1 H lt gt 1 lt 16 gt 1 lt gt lt gt lt gt lt 92 gt lt 2 0 lt gt
49. 1 0 7 form a time multiplexed bidirectional bus that transfers address data and other information during bus cydes During the address portion of a bus cyde the following occurs DAL 31 30 provide information on the type of cycle as indicated in Table 2 3 Technical Specification 2 11 e DAL 29 H is asserted when the rtVAX 300 processor accesses 1 space otherwise it is deasserted e DAL lt 28 02 gt provide the physical address of the device being accessed DAL 01 005 are reserved Table 2 3 DAL Lines DAL s Description 0 1 Longword read write 1 0 Quadword read Quadword writes do not occur 1 1 Octaword read write During the data portion of a bus cycle the DAL lines carry data to or from the user hardware 2 4 2 Ethernet Connections The rtVAX 300 processor allows you to to Ethernet by means of standard Thickwire connections through a 75 UH isolation transformer as shown in Figure 2 5 Connection to ThinWire is also straightforward For more information refer to Chapter 7 Signals are as follows e Collision Detect COL COL non TTL This differential pair of wires connects through a user supplied isolation transformer to a user supplied 15 pin D sub connector when the rtVAX 300 processor is connected to a media attachment unit MAU with a transceiver cable See Figure 2 5 These two signals are used for the collision detect The rtV
50. 41 H Pam 001 615 1 HSOXVAHOI 1 YSOdSCHOLV1 LV 0 VIVG aSa lt gt lt gt lt gt lt gt 1 0 lt 4 gt 1 0 lt 9 gt 1 01 lt gt dSQ 0I XVA 6 00 i 7 158 Na DEE 0819 LL Pap 9 1 9 a T xovidsa e 663 vh v 3 9 plete vL 9014 ag Iz 1 HSOXVASN3 v al v _ H 2 lt E 1 2 2 0 0012 L a 6 1 1 1 lt 0 gt 6 lt gt eu al or 0915 9M 0 d31 2 T 8 aye 1 6 21 1 xis SM o H Pam a 1 1 S 7 4 6 vl al v Suid exeis YSI OML
51. DC converter and a signal isolation transformer The layout must maintain a sufficient spacing between any two conductors on opposite sides of the boundary The requirement for a low impedance at 3 MHz is met by the use of the bypassing block Note that the design uses a capacitance of 4700 pF to provide the RF shunt At 3 MHz this capacitance has an impedance of 11 3 2 This leaves budget of 3 7 2 15 11 3 for connection between the chassis ground on the PC board and the earth ground of the station Network Interconnect Interface 7 21 8 Device Interfacing This chapter discusses the following topics e O device mapping Section 8 1 e Interrupt structure Section 8 2 Bus interfacing techniques Section 8 3 device mapping registers Section 8 4 e rtVAX 300 to digital signal processor application example Section 8 5 e Reset power up Section 8 6 e Halting the processor Section 8 7 e 1 0 system illustrations Section 8 8 8 1 l O Device Mapping The rtVAX 300 processor supports 8 bit 16 bit and 32 bit 1 0 devices that located in the rtVAX 300 processor 5 510M bytes of I O space This space is accessed with the same read and write cycles used for memory access however address bit 29 is set for 1 0 access and cleared for memory access The 1 0 space of the rtVAX 300 is at physical locations 20000000 to 3FFFFFFF 8 1 1 Address Latch The rtVAX 300 uses time multiplexed data and
52. LBM 2 L SYNCHASH 5 DAL 3 LADDR lt 3 gt BM lt 1 gt L LBM lt 1 gt L DAL lt 2 gt H LADDR lt 2 gt H BM lt 0 gt L LBM lt 0 gt L pia 12 ASL zs CLKB MLO 004448 RPA Aecess Time Total Read Time ns Needed Cycle Time ns continued on next page 6 16 Console and Boot ROM Interface Figure 6 8 Sample Design ROM Read Cycle Timing P1 P2 P2 P2 P1 P2 P2 P2 P2 P2 CLKA H P1 P2 P3 2 2 P3 PA P1 P2 P3 PTTP2TPS 2 P3 PT P2 PST 2 IPS FN PN PN PN PN PN PN YN PN i LONGWDRD READ DAL 31 0 H i WRITE BYTE i DATA LWRITEL SELROMH ROMREADL IOREADYL IDLE IDLE ROMCYC2 ROMCYCA ROMCYC6 IDLE IDLE IDLE IDLE ROMCYC1 ROMCYC3 ROMCYC5 FINISHROM IDLE IDLE IDLE MLO 004446 Table 6 2 Cont Typical ROM Access Time Maximum ROM Access Wait States Total Read Time ns Needed Cycle Time ns 84 1 300 184 2 400 284 3 500 384 4 600 These wait states are inserted by holding off the assertion of the RDY L signal input of the rtVAX 300 This RDY L signal is controlled by the console state machine The machine jumps to the state when the EN
53. Network Interconnect Interface 7 5 Figure 7 3 Network Interconnect Ethernet Interface Block Diagram Bypassing 777 MV 12V DC to DC TXO 12V RTN Converter DP8932 V 300 Isolation Boundary COL AUI_XMIT 2 12V 12V RTN MLO 006370 7 6 1 1 Functions of the Ethernet Interface At the heart of all Ethernet interconnect systems are three basic components e TheMAU e Manchester data encoder decoder sometimes called an e Thelocal area network controller The MAU is incorporated in the user module if direct media attachment to ThinWire is required the other two components are implemented within the rtVAX 300 The MAU allows access to the medium and handles certain critical timing and amplitude level conversions The DP8392 CTI chip performs the MAU functions for the ThinWire medium 7 6 Network Interconnect Interface Table 7 1 MAU Signals Description Signal Description Inputs from MAU Interface Collision Collision These are signals of 1V on a 78 2 differential pair Receive Receive These are signals of 1V 78 2 differential pair Outputs to MAU Interface Transmit Transmit Differential Manchester encoded drive 78 2 differential No pulldown resistors 7 6 1 2 DP8392 Transceiver Chip The following sections describe the transceiver chip and its interface functions F
54. The CSDP 4 signal is used only to indicate an internal cycle and not as a parity bit 5 7 Internal Cache Control The rtVAX 300 provides the CCTL L signal to allow external control of the 1K internal cache If this line is asserted driven low during the data transfer of a quadword read cyde the data read is not stored in the internal cache In addition the rtVAX 300 aborts the quadword read cycle after the first longword has been read when the CCTL L line is asserted If this line is unasserted driven high during the data transfer of a quadword read cyde the data read is stored in the internal cache To improve processor performance this line should be driven high during a memory read cyde to allow read references to be internally cached 1 0 devices generally drive this line low during read cycles to prevent internal caching of volatile 1 data Reads from the 1 0 space 20000000 to 3F FFFFFF not cached internally regardless of the state of CCTL L applications containing multiple processors or a secondary cache the CCTL L line is manipulated to maintain internal cache consistency The designer may want to segment system RAM into cacheable and noncacheable address ranges This can be accomplished through the manipulation of the CCTL L line after the address is decoded When external devices perform DMA to the rtVAX 300 private external memory the internal cache entries corresponding to modified memory locatio
55. pig 1514 uua Sv 98 900 O IN OA0d3H d 9Ielg d 111929 1159 e ua pue 1199 00 01 08438 HdlMOVI SseJppv 109195 100735 ssoippy o t svowvug 595 SEEN 5 136 1 E 1 lt 0 6 gt JeziuouuouAS SVHONAS 99015 5591 PPV ILUM 0 LE HdQV1 lt gt V X19 9014 9114 154 Sv lt 0 7 gt 4050 lt 62 gt SY Sv gt 1 lt z 001 ee 1 lt 0 gt 1 lt gt 2 L S 1 lt 1 gt 1 lt gt 2 1 lt gt 1 lt gt 2 L ee 1 lt gt 5 2 1 lt 6 gt 2 lt 5
56. 00000000 00XXXX 20200000 202FFFFF 1100000 0010 XXXX XXXXXXXX XXXXXX 201FFFFE 201FFFFF 100000 00011111 11111111 111111 MLO 004453 Console and Boot ROM Interface 6 27 Table 6 4 Decoder Equations Line Equals UPCONE D DAL29 amp DAL28 amp DAL27 amp IDAL26 amp IDAL25 6 DAL24 amp DAL23 DAL22 amp IDAL21 amp DAL20 amp DAL19 amp DAL18 amp IDAL17 amp IDAL16 amp DAL15 amp DAL14 amp DAL 13 UPCONE AR CYCRES SELROM D DAL29 amp DAL28 amp DAL27 amp DAL26 amp IDAL25 amp 24 amp DAL23 amp IDAL22 amp DAL21 amp DAL20 SELROM AR CYCRES UPCPUST D DAL29 amp DAL28 amp DAL27 amp DAL26 amp IDAL25 amp DAL24 amp DAL23 amp DAL22 amp DAL21 amp DAL20 amp DAL19 amp DAL18 amp DAL17 amp DAL 16 DAL15 amp DAL14 amp DAL 13 UPCPUST AR CYCRES CYCRES AS amp UPCPUST SELROM UPCONE 6 28 Console and Boot ROM Interface 6 4 2 Console Sequencer State Machine PAL The console sequence state machine PAL sequences the ENBCONDATA and I OREADY lines for console and ROM access Table 6 5 lists pins settings and comments Table 6 5 Console Sequencer State Machine PAL Pin Setting Comment 1 CLKA 2 SYNCHAS 3 IDS 5 IL WRITE 6 ICONE 7 ILBMO 8 ICONIACK 9 ENBROM 10 IRST This is the rtVAX 3005 A phase of the CVAX clock It is used to trigger all state transitions This signal is
57. 12 Machine check during machine check exception 13 Machine check during kernel stack not valid exception 19 PSL 26 24 101 during interrupt or exception 1A PSL 26 24 110 during interrupt or exception 1B PSL 26 24 111 during interrupt or exception 1D PSL 26 24 101 during REI 1E PSL 26 24 110 during REI PSL lt 26 24 gt 111 during REI 3 28 Hardware Architecture 3 1 13 System Identification 3 1 14 3 1 14 1 The system identification register SID IPR 62 is a 32 bit read only register implemented in the CVAX chip as specified in the VAX Architecture Reference Manual This register identifies the processor type and its microcode revision level Figure 3 6 shows the system identification register Table 3 9 describes its fields Figure 3 6 System Identification Register 31 2423 08 07 00 Microcode MLO 004410 Table 3 9 System Identification Register Fields Data Bit Definition lt 31 24 gt Processor type TYPE This field always reads as A 16 indicating that the processor is implemented using the CVAX chip lt 23 08 gt Reserved for future use 07 007 Microcode revision MICROCODE This field reflects the microcode revision level of the CVAX chip CPU References All references by the CVAX processor can be classified into one of three groups Request instruction stream read references Demand data stream read references e Write references
58. 16 3316 and 0016 e Checksum last byte E ach ROM byte contains a simple additive checksum in its last word The system adds all bytes modulus 256 and stores the negative value of the sum for each ROM FIRMWARE 4 3 4 1 2 System ROM Set Format The following data are meaningful only within the context of the collated set of ROMs information in the system firmware ROM memory is position independent Figure 4 3 shows the ROM set data Figure 4 3 System ROM Set Data 31 16 15 00 Processor Restart Address SYS TYPE Vers Vers Vers Vers 20040008 Byte 0316 0216 0116 0016 2004000C Byte 5516 5516 5516 5516 20040010 Byte 20040014 Byte 3316 3316 3316 3316 20040018 Byte 0016 0016 0016 0016 2004001 Byte Callable Routines Memory Test 20040020 Set Rest of ROM Set Data and Code 20040080 Set Last P MLO 004501 20040000 Set 20040004 Set These physical addresses in the rtVAX 300 base system ROM set are fixed as follows 20040000 processor restart address The rtVAX 300 hardware begins execution at address 20040000 on one of the following conditions At power on On execution of a HALT instruction assertion of the EXT HLT line for example when a break signal is received from the user supplied console device the HALT button is pressed 4 4 FIRMWARE On processor detection of severe corruption of its operating environ
59. 2 This command invokes extended diagnostics and utilities Tests 116 through 716 are onboard power up tests tests 816 through 16 are user supplied power up tests Refer to Table 4 5 for a list of test numbers and their meanings FIRMWARE 4 19 4 3 6 14 Unjam U NJ AM This command provides a system reset The status of all devices returns to a known initial state that is registers are reset to 0 and logic is reset to state 0 This operation is implemented on the rtVAX 300 by invoking the hardware IORESET and calling AM routines for the Ethernet interface and the console serial line unit if present The user is responsibile for decoding the processor register to produce a reset signal and for using this signal to reset the user s devices Any device that may interrupt the rtVAX 300 at IPL 1616 or IPL 171g must be reset in this fashion The user cannot reasonably expect to continue from an UNJ AM command 4 3 6 15 Transfer X FER ADDRESS COUNT CR lt CHECKSUM gt DATA STREAM lt CHECKSUM gt This command transfers binary data to and from physical memory It is intended for use only by host software through an attached console terminal serial port Channel A Do not expect to be able to type this command from a keyboard Note that XON XOFF line is disabled during the binary transfer these characters are treated as binary data when they occur in the binary data stream
60. Instruction Stream Read References The CVAX processor has an instruction prefetcher with a 12 byte 3 longword instruction prefetch queue for prefetching program instructions from either cache or main memory Whenever there is an empty longword in the and the prefetcher is not halted due to an error the instruction prefetcher generates an aligned longword request instruction stream I stream read reference Hardware Architecture 3 29 3 1 14 2 Data Stream Read References Whenever data is immediately needed by the CVAX processor to continue processing a demand data stream D stream read reference is generated More specifically demand D stream references are generated on operand page table entry PTE system control block SCB and process control block PCB references When interlocked instructions such as branch on bit set and set interlock BBSSI are executed a demand D stream read lock reference is generated Since the CVAX processor does not impose any restrictions on data alignment other than the aligned operands of the ADAWI and interlocked queue instructions and since memory can be accessed only one aligned longword at a time all data read references are translated into an appropriate combination of masked and nonmasked aligned longword read references If the required data is a byte word within a longword or an aligned longword then a single aligned longword demand D stream read reference
61. J oz 929 Vos 8 rz 1 09805 zi 081 Coz 12 iu 52 22 564 1 Hir _ ele Sela Wd uso 1 22 8 5214178 sii og Te gi 9 30 jexoog eioN 23 va di 8423 5 Wd s 89154508 03 26 8ulsdsd 54 99 GI ags a u 36 vd 199195 Q BOOVAAIHON 39 Yso pue Jeisibou sse jppy eseg SY m 9213 2 LI ai QNO H 2991 Wd Ji TAS 288 pesn 120 40 19 9 26vv00 O lIN 2 ASZ 199 T 2 001 095 5015 96H 01 2001 2 71095 SE 4008 i S M T z 2 1 inova 268 T 169 864 T lt CT um Hu FER 1 5 ETT 880 HE 6 0S bE 628 vk 9 8 m T 1 2 889 al 995 e Jexeedg WHO 8 dno L L v OOADOIWNY E 4j 189 T 24
62. Note If an external DMA device remains DAL bus master longer than 6 pseconds the Ethernet coprocessor FIFO may overflow when receiving packets See Figure 2 16 2 42 Technical Specification Figure 2 16 05 05 CSDP DAL DMA Cycle MLO 004403 2 6 11 Cache Invalidate Cycle External logic initiates a conditional cache invalidate cyde to allow the CVAX to detect and invalidate stale data stored in cache A cache invalidate cyde requires at least four microcydes The sequence of events is as follows 1 4 After DMG L is asserted external logic drives the address on the DAL lt 31 00 gt lines and asserts AS L to latch the address into the rtVAX 300 External logic should also assert CCTL L to start the cache invalidate cycle The rtVAX 300 invalidates the quadword entry selected by the DMA address if the location is stored in cache External logic deasserts CCTL L and optionally reasserts CCTL L to conditionally invalidate the alternate quadword formed by inverting DAL lt 03 gt H This allows external logic to detect and invalidate stale data stored in any naturally aligned octaword ends when external logic deasserts CCTL L and AS L If a cache parity error is detected during a conditional cache invalidate no machine check is generated no invalidate occurs and the error is logged in the MSER
63. Overflow X M X X X V Collision after 512 bits V V V X X V Runt frame V V V X X V Runt frame 14 bytes V X X X V Watchdog timeout V V X X X V V Valid X M eaningless 3 72 Hardware Architecture 3 6 2 2 Transmit Descriptors Figure 3 29 shows the format of Transmit Descriptors Table 3 35 through Table 3 38 describe the TDESx bit structures The TDESO word contains transmitted frame status and descriptor ownership information Figure 3 29 Transmit Descriptor Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 18 12 11 10 09 08 07 06 05 04 03 02 01 00 1 0 SGEC writes as 0 u Ignored by the SGEC on read never written Table 3 35 TDESO Fields Bit Name Description 00 DE Deferred When set indicates that the Ethernet coprocessor had to defer while trying to transmit a frame This condition occurs if the channel is busy when the Ethernet coprocessor is ready to transmit 01 UF Underflow E rror When set indicates that the transmitter has truncated a message due to data late from memory This bit indicates that the Ethernet coprocessor encountered an empty transmit FIFO while in the midst of transmitting a frame The Transmission process enters the suspended state and sets 58 5401 02 TN Translation Not Valid When set indicates that a translation error occurred when the Ethernet coprocessor was translating a VAX virtual buffer address It may only set if TDES1 lt 3
64. Q0 rsv dov muldlen rw muldaddr ab prodlen rw prodaddr ab 22 SUBPA sublen rw subaddr ab Subtract packed 0 5 diflen rw difaddr ab 4 operand rsv reserved operand fault iov integer overflow trap decimal overflow trap ddvz decimal divide by zero trap continued on next page 3 4 Hardware Architecture Table 3 1 Cont Microcode Assisted Emulated Instructions OP Mnemonic and Arguments Description nzvc Exceptions 23 SUBPS6 sublen rw subaddr ab Subtract packed rsv minlen rw minaddr ab diflen rw 6 difaddr ab rsv reserved operand fault iov integer overflow trap decimal overflow trap ddvz decimal divide by zero trap 3 1 4 Processor State The processor state is stored in processor registers rather than in memory The processor state is composed of 16 general purpose registers GPRs the processor status longword PSL and the internal processor registers IPRs Nonprivileged software can access the GPRs and the processor status word bits 15 002 of the PSL Only privileged software can access the IPRs and bits 31 16 of the PSL The IPRs are explicitly accessible only by the move to processor register MTPR and move from processor register MFPR instructions which can be executed only while running in kernel mode 3 141 General Purpose Registers The rtVAX 300 implements 16 general purpose registers as specifi
65. lt 0 gt Carry condition code C 3 1 4 3 Internal Processor Registers The rtVAX 300 IPRs can be accessed by using the MFPR and MTPR privileged instructions Each IPR falls into one of the following categories 1 Implemented by rtVAX 300 in the CVAX chip as specified in the Architecture Reference M anual 2 Implemented by rtVAX 300 and all designs that use the CVAX chip uniquely 3 Not implemented timed out by the DAL bus timer after 32 us Read as 0 NOP on write 4 Access not allowed accesses result in a reserved operand fault 5 Accessible but not fully implemented Accesses yield unpredictable results 6 Externally implemented on application module Table 3 3 lists each rtVAX 300 IPR its mnemonic its access type read or write and its category number Hardware Architecture 3 7 Table 3 3 Internal Processor Registers Decimal Hex Register Mnemonic Type Category 0 0 Kernel stack pointer KSP r w 1 1 1 Executive stack pointer ESP r w 1 2 2 Supervisor stack pointer SSP 1 3 3 User stack pointer USP r w 1 4 4 Interrupt stack pointer ISP r w 1 7 5 7 5 Reserved 3 8 8 PO base register POBR r w 1 9 9 PO length register POLR r w 1 10 A P1 base register 1 r w 1 11 B P1 length register r w 1 12 System base register SBR 1 13 System length register SLR r w 1 15 14 Reserved 3 16 10 Process control block base PCBB r w 1 17 1 System control block base SCBB r w 1 18 1
66. mlo 004486 ps turnpage Device Interfacing 8 45 8 46 Device Interfacing Figure 8 24 I O Device Interfacing DSP DMA Transceiver and Parity Generator mlo 004487 ps foldout Device Interfacing 8 47 8 48 Device Interfacing Figure 8 25 Device Interfacing DMA Address Drivers mlo 004488 ps foldout Device Interfacing 8 49 8 50 Device Interfacing Figure 8 26 Device Interfacing VAX to DSP 1 Way Mirror Register mlo 004489 ps fol dout Device Interfacing 8 51 8 52 Device Interfacing Figure 8 27 Device Interfacing 300 DSP CSR mlo 004490 ps fol dout Device Interfacing 8 53 8 54 Device Interfacing Figure 8 28 Device Interfacing DSP Controller mlo 004491 ps fol dout Device Interfacing 8 55 8 56 Device Interfacing Figure 8 29 Device Interfacing D A and A D Interface mlo 004492 ps fol dout Device Interfacing 8 57 8 58 Device Interfacing Figure 8 30 Device Interfacing rtVAX 300 ThinWire Thickwire Network Connections ml o 004455 ps 36 5 Device Interfacing 8 59 8 60 Device Interfacing Figure 8 31 Device Interfacing rtVAX 300 I O Pin Connectors mlo 006377 ps foldout Device Interfacing 8 61 8 62 Device Interfacing Figure 8 32 l O Device Interfacing Decoupling Caps mlo 004494 ps fol dout Device Interfacing 8 63
67. 2 2 Minimum Hardware Configuration The rtVAX 300 processor is a platform that requires hardware to be usable Section 2 2 1 and Section 2 2 2 lists the minimum hardware requirements needed for the rtVAX 300 processor 2 2 1 System RAM The rtVAX 300 processor contains no RAM However in order for the rtVAX 300 processor to run its power on self test diagnostics successfully and issue the console program prompt the processor needs at least 64K bytes of RAM Under DECnet Phase at least 512K bytes are needed to boot a VAXELN system image with the Ethernet driver local and remote debuggers and a 200K byte user application The RAM resides in VAX memory space beginning at physical address 00000000 2 2 2 Console The rtVAX 300 processor needs no console However a console port is required in order for the processor to use the console emulation program report errors and warnings and display system crashes The rtVAX 300 processor supports the Signetics 2681 dual universal asynchronous receiver transmitter SCN 2681 DUART or a compatible device as a console interface The data lines of the SCN 2681 DUART should be connected to the DAL 07 00 lines When the DUART is read from written to the BM 0 L line should be asserted The rtVAX 300 processor uses channel A of the DUART for the console Channel B is available and can be used by the application for example to load an application image over serial lines A VAXELN de
68. 3 35 3 36 3 38 3 39 3 40 3 40 3 41 3 41 3 41 3 41 3 42 3 43 3 45 3 46 3 6 1 Control Status Registers 3 6 1 1 Vector Address IPL Sync Asynch CSRO 3 6 1 2 Transmit Receive Polling Demands CSR1 CSR2 3 6 1 3 Descriptor List Addresses CSR3 CSR4 3 6 1 4 Status Register CSR5 3 6 1 5 Command and Mode Register CSR6 3 6 1 6 System Base Register CSR7 3 6 1 7 Watchdog Timer Register 5 9 3 6 1 8 Revision Number and Missed Frame Count CSR10 3 6 1 9 Boot Message Registers CSR11 CSR12 CSR13 3 6 1 10 Breakpoint Address Register CSR14 3 6 1 11 Monitor Command Register 5815 3 6 2 Descriptor and Buffer Formats 3 6 2 1 Receive Descriptors 3 6 2 2 Transmit Descriptors 3 6 2 3 vus dee eb Sees aha e ts 3 6 2 3 1 First Setup Frame 3 6 2 3 2 Subsequent Setup 3 6 2 3 3 Setup Frame Descriptor 3 6 2 3 4 Perfect Filtering Setup Frame Buffer 3 6 2 3 5 Imperfect Filtering Setup Frame Buffer 3 6 3 Operation uuu Pee eae MORAN Rep NE 3 6 3 1 Hardware and Software Reset 3 6 3 2 ESTUDIS iux hee a
69. 3 6 1 3 Descriptor List Addresses CSR3 CSR4 The two descriptor list heads address registers are identical in function one is used for the transmit buffer descriptors and one for the receive buffer descriptors both cases the registers point the Ethernet coprocessor to the start of the appropriate buffer descriptor list The descriptor lists reside rtVAX 300 physical memory space and must be longword aligned Note For best performance Digital recommends that the descriptor lists be octaword aligned Caution Initially these registers must be written before the respective Start command is given see Section 3 6 1 5 otherwise the respective process remains in the stopped state New list head addresses are acceptable only while the respective process is in the stopped or suspended states Addresses written while the respective process is in the running state are ignored and discarded If the rtVAX 300 attempts to read any of these registers before writing to them the Ethernet coprocessor responds with unpredictable values Figure 3 20 shows the format of the descriptor list Table 3 21 describes its bit structure Hardware Architecture 3 51 Figure 3 20 CSR3 CSR4 Format 313029 02 0100 ofo Start of Receive List RBA olo CSR3 ofo Start of Transmit List TBA olo CSR4 0 ignored by the SGEC MLO 004418 Table 3 21 CSR3 CSR4 Bits Register Bit Name Access Description CSR3 29 00
70. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 FRAME LE RDESO RDES1 RDES2 BUFFER SVAPTE PHYSICAL ADDRESS RDES3 0 SGEC writes as 0 u Ignored by the SGEC on never written Table 3 30 RDESO Fields Bit Name Description 00 Overflow When set indicates received data in this descriptor s buffer was corrupted due to internal FIFO overflow This will generally occur if Ethernet coprocessor requests are not granted before the internal receive FIFO fills up 01 CE CRC Error When set indicates that a CRC error has occurred on the received frame continued on next page 3 68 Hardware Architecture Table 3 30 Cont RDESO Fields Bit Name Description 02 03 05 06 07 08 09 DB TN FT CS TL LS FS Dribbling Bits When set indicates the frame contained a non integer multiple of eight bits This error will be reported only if the number of dribbling bits in the last byte is greater than two Meaningless if RDESO 06 or RDESO lt 11 gt are set The CRC check is performed independent of this error however only whole bytes are run through the CRC logic Consequently received frames with up to six dribbling bits will have this bit set but if 50 lt 01 gt or another error indicator is not set these frames should be considered valid 0 lt 01 gt 0 lt 02 gt
71. 5 2 5 3 5 4 5 5 5 6 hi l C C Memory Bitmap Descriptor ROM Boot Memory Organization Sample Design Memory Subsystem Functional Diagram Sample Design DRAM Address Path Sample Design Memory Controller Sequence Sample Design Memory Controller Longword Timing Sample Design Memory Controller Octaword Read Cycle EPI Sample Design Memory Controller Octaword Write Cycle TIMING EAR ed Abn aeree aqoa dur Sample Design Memory Controller Refresh Timing Sample Design Address Decoder and Power On Rese RAM Memory Sample Design Address Latches Sample Design Memory Controller Sample Design DRAM Memory Array 1 Sample Design DRAM Memory Array 2 Sample Design RAM Data 5 Sample Design Console Terminal Interface Block Diagram cce ge xe xe xc Ee Sample Design Console Cycle Sequence Sample Design Interrupt Acknowledge Cycle Timing Sample Design Console Read and Write Cycle Timing Sample Design Boot ROM Functional Block Diagram Sample Design Address Sample Design Address Latches
72. 6 T 1 avaunod 22 1 lt 0 gt 1 22 lt 0 gt 5 2 BEEN uw 5 2 gt wa lt gt H sid z uaavi ig m H HQdY1 Iv m H amp Haqvi LA v 01 lt gt LA v OL lt gt H lt 3r 6 H lt H 6 H lt 8 H 92H V 8 H 92H V a Cs 4 H lt gt a Cs 2 ea 9 H gt H lt 8 gt 1 vi 9 H gt V V a H A 8 92 H lt 01 gt A 8 92 H lt 01 gt EN lt gt 22H iad m H lt 2H V xj 2H V H 1290 82 lt gt 12120 82 lt 61 gt H 9 gt H H 9 gt V 387 H lt 1 gt 00 1 39 91 H lt 1 gt 00 1 lt 9 gt 2 lt 9 gt SEI lt gt oM lt gt 4 WOUdAn jd 4 wWOddAn Uy H O VIVdWOH 07 lt 91 gt 1 iom com e CP H DER ADU NEM AS H Nd 8 SPPVIVIWOH vi H lt 6 LPVIVONOH vi mu _ TER PVIVONOH St EY ey H SIPVIVONOH 51 H lt 5
73. Hardware Architecture 3 89 Table 3 42 Ethernet Coprocessor Summary of Reported Errors Classification Error System Errors Memory Error Serial Interface Collision Fail Errors Transmit Watchdog Timeout Receive Watchdog Timeout Loss of Carrier Frame Errors CRC Error Framing Error Overflow U nderflow Error Translation Error Late Collision Error Frame less than 64 bytes long 3 6 5 2 On Chip Diagnostics The Ethernet coprocessor contains extensive on chip diagnostics These diagnostics include an internal self test loopback modes and a time domain reflectometer 3 6 5 2 1 Internal Self Test The Ethernet coprocessor s self test is run after a reset of the chip The internal self test checks the operation of the following sections of the Ethernet coprocessor Internal ROM e Internal RAM e Transmit FIFO Receive FIFO e Address Recognition RAM 3 6 5 2 2 Loopback Modes The self test performs local loopback test The Ethernet coprocessor supports these loopback modes internal loopback and external loopback Internal loopback mode permits the testing of Ethernet coprocessor logic that includes frame length checking CRC generation and checking and descriptor management for example chaining and virtual address translation External loopback mode provides a loopback capability on an active Ethernet or IEEE 802 3 network This mode places the Ethernet coprocessor in full duplex operation in which it receives
74. INPUT PARAMETERS cpmbx address of console mailbox bitmap address of memory bitmap descriptor Scratch address of scratch memory area IMPLICIT INPUTS None OUTPUT PARAMETERS None IMPLICIT OUTPUTS None ROUTINE VALUE None SIDE EFFECTS None board level initialization argument block offsets offset cpmbx address of console mailbox bitmap address of memory bitmap descriptor scratch address of scratch memory area gt usrom share byte 300 usrom board init lt gt ret return to caller User Boot Diagnostic ROM Sample D 5 Sbttl rtVAX 300 Board level Test 8 FUNCTIONAL DESCRIPTION This routine user supplied is called by the rtVAX 300 s resident firmware at system power on to do board level test 8 It is called at IPL 31 in kernel mode with memory management disabled CALLING SEQUENCE calls 5 300 usrom test 8 INPUT PARAMETERS scratch address of scratch memory area failing pc address of longword to store failing pc expected data address of quadword to store expected data actual data address of quadword to store actual data flags board level test flags IMPLICIT INPUTS None OUTPUT PARAMETERS r0 test results IMPLICIT OUTPUTS None ROUTINE VALUE 1 device not present or untestable 0 test failed 1 test passed SIDE EFFECTS None Me
75. IPL 1416 to IPL 1716 Console DUART IPL 1446 Ethernet coprocessor IPL 1516 Interval Timer IPL 1616 Software interrupt invoked by MTPR src zSIRR IPL 0116 to OF 16 AST delivery when REI restores a PSL with a mode gt ASTLVL IPL 0216 Each device has a separate interrupt vector location in the system control block SCB Thus interrupt service routines do not need to poll devices in order to determine which device interrupted The vector address for each device is determined by hardware To reduce interrupt overhead no memory mapping information is changed when an interrupt occurs Thus the instructions data and contents of the interrupt vector for an interrupt service routine must be in the system address Space or present in every process at the same address Hardware Architecture 3 13 3 1 10 3 1 11 3 1 12 3 1 12 1 Interrupt Control The IRQ lt 3 0 gt L HLT L and PWRFL L inputs to the processor and three registers control the hardware interrupt system Asserting any of the input pins generates an interrupt at the hardware level given in Table 3 4 The three registers are used to control the software interrupt system Internal Hardware Interrupts The rtVAX 300 10 ms interval timer interrupts at IPL 1616 and the Ethernet coprocessor can interrupt the rtVAX 300 at IPL 1516 These interrupts have higher priority than IRQ lt 2 gt L and IRQ lt 1 gt L which also interrupt at IPL 1616 and IPL 1516
76. LADDR lt 19 gt H LADDR lt 18 gt H MLO 004476 Device Interfacing 8 29 Figure 8 14 Device Interfacing DRAM Address Path mlo 006397 ps turnpage 8 30 Device Interfacing Figure 8 15 Device Interfacing Memory Controller mlo 004478 ps fol dout Device Interfacing 8 31 8 32 Device Interfacing Figure 8 16 Device Interfacing DRAM Memory Array 1 mlo 004479 ps turnpage Device Interfacing 8 33 Figure 8 17 Device Interfacing DRAM Memory Array 2 mlo 004480 ps turnpage 8 34 Device Interfacing Figure 8 18 Device Interfacing RAM Data Latches RAM 15 H RAM 14 H RAM 13 H RAM 12 H RAM 11 H RAM 10 H lt 9 gt RAM 8 H MRDYL lt 7 gt RAM 6 RAM 5 lt 4 gt RAM 3 H lt 2 gt lt 1 gt RAM 0 MRDYL DAL lt 15 gt DAL lt 14 gt DAL lt 13 gt DAL lt 12 gt DAL lt 11 gt DAL lt 10 gt DAL lt 9 gt DAL lt 8 gt DAL lt 7 gt DAL lt 6 gt DAL lt 5 gt DAL lt 4 gt DAL lt 3 gt DAL lt 2 gt DAL lt 1 gt DAL lt 0 gt RAM lt 31 gt RAM lt 30 gt RAM lt 29 gt lt 28 gt RAM lt 27 gt RAM lt 26 gt RAM lt 25 gt RAM lt 24 gt MRDY L RAM lt 23 gt RAM lt 22 gt lt 21 gt
77. MAUs either internal or external need three isolation pulse transformers to isolate the differential signals COL RX and XMIT of the transceiver chip from the SIA ThinWire products with integrated transceivers use 75 uH pulse transformers Power supply The DP8932 transceiver chip operates over a supply voltage range of 8 46V to 9 54V The chip draws from 50 to 200 mA The transceiver chip has a power supply noise immunity of 100 mV peak to peak 7 6 3 2 2 Layout Considerations To minimize the capacitance introduced to the ThinWire coaxial cable by the transceiver chip follow these guidelines Mount the transceiver chip as close to the center pin of the BNC connector as possible no more than 4 cm away Align the RXI pin 14 and the anode of the isolation diode with the center pin of the BNC connector Keep the length of traces from the and pins 14 and 15 to the BNC connector to a minimum not greater than 4 cm Keep all metal traces especially GND and VEE traces and planes as far as possible from the RXI and TXO traces Network Interconnect Interface 7 15 na multilayered PC board void the area of GND and VEE planes beneath the RXI and TXO lines Solder the DP8392 chip directly onto PC board Do not use a socket the DP8392 has a special lead frame designed to conduct heat out of the chip e Connect VEE pins 4 5 and 13 to large metal traces or planes Good heat conduction is
78. None ROUTINE VALUE 1 device not present or untestable 0 test failed 1 test passed SIDE EFFECTS None board level test 10 argument block offsets User Boot Diagnostic ROM Sample 0 9 offset lt Scratch address of scratch memory area failing address of longword to store failing pc if test fails expected data address of quadword that test can Store expected data if test fails actual data address of quadword that test can Store actual data if test fails flags board level test flags gt usrom share byte 300 usrom test 10 m lt gt ret return to caller Sbttl rtVAX 300 Board level Test 11 FUNCTIONAL DESCRIPTION This routine user supplied is called by the rtVAX 300 s resident firmware at system power on to do board level test 11 It is called at IPL 31 in kernel mode with memory management disabled CALLING SEQUENCE calls 5 300 usrom test 11 INPUT PARAMETERS scratch address of scratch memory area failing pc address of longword to store failing pc expected data address of quadword to store expected data actual data address of quadword to store actual data flags board level test flags IMPLICIT INPUTS wx None OUTPUT PARAMETERS r0 test results IMPLICIT OUTPUTS None ROUTINE VALUE Ne Ne Ne Se Se Se Se Ne Ne Ne Ne scc Se Se 5e e 1 device not present or untestab
79. RR 2 4 2 1 7 Strud re RO 2 4 2 1 8 Interval Timer 2 4 2 1 9 Internal Cache dnd 2 5 2 2 Minimum Hardware Configuration 2 5 2 2 1 System RAM lt eeu 2 5 2 2 2 Console uci Dese 2 5 2 3 Bus 5 2 6 2 3 1 Power 5 2 6 2 3 2 Reset and Power Up Requirements 2 6 2 3 3 Power Down Sequencing 2 7 2 4 Pin and Signal Description 2 8 2 4 1 Data and Address 5 2 11 2 4 2 Ethernet 5 2 12 2 4 3 Bus Control 5 2 14 2 4 4 2 4 5 2 4 6 2 4 7 2 4 8 2 4 9 2 4 10 2 5 2 5 1 2 5 2 2 5 3 2 5 4 2 5 5 2 6 2 6 1 2 6 2 2 6 3 2 6 4 2 6 5 2 6 6 2 6 7 2 6 8 2 6 8 1 2 6 8 2 2 6 9 2 6 10 2 6 11 Bus Retry Cydes 2 17 Status and Parity Control Signals 2 17 Interrupt Control d Sate eink Saige be 2 19 DMA Control 5 5 2 19 System Control Signals 2 20 Clock Signals 4 2 isole 2 20 Power Supply 5 2
80. Receive Descriptor Status Validity 5 5 EDESI Fields uem ERRORES IDES2Fields ix xr sanos ERE Transmit Descriptor Status Validity Setup Frame Descriptor Bits Ethernet Coprocessor CSR Nonzero Fields After Reset Ethernet Coprocessor Summary of Reported Errors System Type Register Fields Firmware Error Messages Countdown Status 5 Boot Countdown Indications LED Test Number Code List Scratch RAM Offset Definitions Console Mailbox Register Fields DUART and Display Status Register Fields 3 44 3 45 3 46 3 48 3 49 3 50 3 51 3 52 3 53 3 57 3 62 3 63 3 64 3 64 3 65 3 66 3 68 3 71 3 72 3 72 3 72 3 73 3 75 3 77 3 78 3 78 3 80 3 87 3 90 4 5 4 22 4 26 4 27 4 30 4 36 4 37 4 39 xvii xviii bids ads d Co d d NOOO cto O9 08 QUO Tq 1 Default Boot Device Register Fields rtVAX 300 Data Transfer and Bus Cyde Types rtVAX 300 DAL Parity and Byte Masks rtVAX 300 CSDP lt 4 0 gt IPR and IACK Codes Memory Read Cycle Selection Quadword and Octaword Read Cycle Transfers Memory Controller Setup Times DRAM Timing Parameters for 80 ns Page Mode 1M Bit x DRAM CAS Before RA
81. The machine then increments INVADDR 3 2 driving the address of the next longword onto the DRAM address bus The state of INVADDR 3 2 is compared to LADDR 31 30 and the cycle repeats if another longword is needed If another longword is required and it is a read LWRITE is deasserted the state machine jumps to READCY C2 deasserts DRAMREADY and asserts ENBCAS driving the next longword into the inputs of the RAM latches When DS deasserts and the rtVAX 300 processor has latched the previous longword the state machine jumps into the READCYCI state and the process repeats itself until the last longword is read Table 5 5 lists all transfer cydes along with the order of the longwords that are transferred Table 5 5 Quadword and Octaword Read Cycle Transfers rtVAX 300 Memory Address Latched Address DRAMADDR Longword LADDR 03 02 03 02 Transferred Quadword X 0 X 0 First X 0 X 1 Second X 1 X 1 First X 1 X 0 Second Octaword 0 0 0 0 First 0 0 0 1 Second 0 0 1 0 Third 0 0 1 1 Fourth After AS and DS have been asserted the rtVAX 300 processor waits for the assertion of RDY L indicating that the memory or device has transferred the data Wait states of one microcycle are added to the 1 0 or memory access cycle until the memory controller asserts RDY L If RDY L is not asserted 16 to 32 us after the assertion of AS the rtVAX 300 completes the access cyde indicates an error condition and transfers op
82. and lines BM lt 3 0 gt are asserted as required WR L is negated 2 30 Technical Specification 3 300 asserts AS L validating lines CSDP lt 4 0 gt L BM lt 3 0 gt L WR L and the address information on DAL 29 02 4 Line DS L is asserted for each data transfer to indicate that the DAL lines are available to receive the incoming data BM 3 0 L are changed with each assertion of DS 5 ThertVAX 300 checks for a complete cycle after slipping one This is done once every starting at the second possible P1 rising edge External logic indicates that the cycle is complete by one of the following three responses a If no error occurs external logic places the requested data on the DAL 31 007 lines and parity information on CSDP lt 3 0 gt L asserts DPE L if parity is to be checked and asserts RDY L while ERR L is deasserted for each data transfer The rtVAX 300 reads the data and parity information and deasserts DS L for every transfer If the rtVAX 300 detects a parity error the processor is interrupted and the rtVAX 300 ignores the data on the DAL lt 31 00 gt lines and terminates the b If an error occurs on any longword external logic asserts ERR L with RDY L deasserted The rtVAX 300 ignores the data on the DAL 31 00 H lines and terminates the without reading any additional data c External logic cannot request a retry of the
83. e address Specifies the physical address that the binary data transferred to or from It is specified as a hexadecimal number e count Specifies the number of bytes to be transferred The count is expressed as an 8 bit hexadecimal number If the high order bit of the count longword is 1 the data are transferred read from physical memory to the console terminal if it is 0 the data are transferred written from the console terminal to physical memory CR Carriage Return e checksum Specifies the two s complement checksum of the command string or data stream The checksum is one byte of data expressed as a 2 digit hexadecimal number e data stream Count bytes of binary data 4 20 FIRMWARE 4 3 6 16 Comment COMMENT COMMAND comment The exdamation pointprefixes a comment wherever it appears on the line the remainder of the line is ignored 4 3 7 Supported Boot Devices The boot device names that you can use to boot the rtVAX 300 processor are as follows 1 EZAO Ethernet 2 PRAO System ROM in memory space starting at physical address 10000000 PRBO System ROM in I O Space starting at physical address 20200000 PRB1 System ROM in 1 0 Space copied to system memory 5 0 on SCN 2681 DUART at 1200 bps CSB1 Channel B on SCN 2681 DUART at 2400 bps 7 CSB2 Channel B on SCN 2681 DUART at 9600 bps If no device name and or qualifiers are given on the BOOT
84. logic Figure 8 12 shows the address decoder and power on reset Figure 8 13 shows the address latches Figure 8 14 shows the DRAM address path Figure 8 15 shows the memory controller Figure 8 16 shows DRAM memory array 1 Figure 8 17 shows DRAM memory array 2 Figure 8 18 shows the RAM data latches Figure 8 19 shows the console interface Figure 8 20 shows the user boot ROM bank 1 with drivers Figure 8 21 shows the user boot ROM bank number 2 Figure 8 22 shows the DSP and private RAM Figure 8 23 shows the DSP PGM loader ROM Figure 8 24 shows the DSP DMA transceiver and parity generator Figure 8 25 shows the DMA address drivers Figure 8 26 shows the VAX to DSP 1 way mirror register Figure 8 27 shows the rtVAX 300 and DSP CSR Figure 8 28 shows the DSP DMA controller Figure 8 29 shows the D A and A D interface Figure 8 30 shows rtVAX 300 ThinWire Thickwire network connections Figure 8 31 shows 300 I O pin connectors Figure 8 32 shows the decoupling caps Device Interfacing 8 27 Figure 8 12 Device Interfacing Address Decoder and Power On Reset Power On and Power Glitch Reset 45V 4 2 2 2 R3 R5 100K 470 2 R8 1 1 4 1K 1 RESETVAXL 2 75109 47 25 225 1 45V 1 1 1 R6 2 R4 eisque R11 5 34 2 1 1B 2K 2K 12 74 1B 801 13 2 2 HLTREQL 1 7 Run 2 11 E25 3 HLTL 52 F32 p E
85. lt gt er 961171 96 lt 81 gt 1 96 SE lt gt lt 1 gt 7 rigge HAWA E e lt gt Jojoeuuo ey OdQ 1 Jojeuuo 62 040 9051090 lt 08 62 08 6c lt gt 8c ZZ 7 8c 22 7 lt 92 H lt 01 gt 1 0 1 92 11199 lt 6 gt TVA telag 82 H iseoui 1 lt gt 1 1 lt 9 gt lt 1 gt 22 12 Q oul H lt 6 gt 02 lt gt 1 0 lt gt 0c 1 1 lt gt LL lt 2 AS 8L LL 1 SH i lt gt 91 SL lt 0 gt 7370 91 1x ft gt 5 gt 1 1 1 1 0076 2 gt 2059 HH ie lt gt dS lt OL 6 1 lt 1 gt 4 89 8 7 lt 0 gt 4955 8 p 103414 9 1 lt gt 1 9 1 lt 2 gt 1008 021195 521009 lt 0 gt 1008 1 1 2 er e 08 006 5 i 5 T 082 gt os fer AS _ 09 HH fer lt 27 lt gt lt gt 8 Jv lt OL gt NNOOON
86. the instruction can be restarted A fault is an exception that occurs during an instruction and leaves the registers and memory in a consistent state such that the elimination of the fault condition and restarting the instruction gives correct results After an instruction faults the PC saved on the stack points to the instruction that faulted An abort is an exception that occurs during an instruction and leaves the value of the registers and memory unpredictable such that the instruction cannot necessarily be correctly restarted completed simulated or undone After an instruction aborts the PC saved on the stack points to the instruction that was aborted which may or may not be the instruction that caused the abort the instruction may or may not be restarted depending on the dass of the exception and the contents of the parameters that were saved Exceptions are grouped into six classes e Arithmetic Memory management e Operand reference e Instruction execution Tracing e System failure Hardware Architecture 3 17 Table 3 5 lists exceptions by dass Exceptions save the PC and PSL and in some cases one or more parameters on the stack Most exceptions do not change the IPL of the processor except the exceptions in serious system failures class which set the processor IPL to 1 6 and cause the excepti on to be dispatched to the appropriate service routine through the SCB except for the interrupt stack not va
87. these routines are executed and the system attempts to boot or to enter console mode depending on the setting of the BOOT 2 0 lines The longword at ROM address 2008001C contains the address of the user s initialization procedure The 7 longwords starting at ROM address 20080020 contain the physical addresses of the seven test routines The physical address of these routines must be in the range of 20080040 to 200FFFFC 0 value of 0 for the physical address indicates that this routine does not exist Figure 4 6 shows the layout of this ROM Refer to Appendix D for a template of these routines 4 8 1 Optional User Initialization Routine Routines in the initialization ROM can initialize any of the user supplied devices to a known state and use the interrupt stack for variable storage The only requirement is that the processor context be restored according as described in the VAX calling standard after these ROMs exit 1 Registers R2 to R15 the interrupt stack and all IPRs must be preserved The VAX Architecture Reference Manual describes this standard 4 34 FIRMWARE Figure 4 6 User Boot Diagnostic ROM Board Level LED Display Initialization ROM Range 31 16 15 0 200F FFFC Board Level Initialization Code Along With Diagnostics Testing Code All code segments restore processor 2008 0040 context and end with RET 2008 0024 Physical Address of Test 9 6Fh 60h 2008 001C Physical Address of Init Code F8h FOh 2008
88. 00 1 z lt gt Ds WOYdAN ox 9I 1 ij XLIPVIVGWOH LA et lt 5 6I VIVOWOH 2 Ss 0z v1vdWOH A ae IZ VIVaWOH 61 lt gt 02 T 1200 0 dur 8 5 1 sain NM v 0 ee H sr Hdavi 6 H lt za 008 HEP HOO 2 9 H s8 Hdavi A ev n C oz H gt 23 PV gt gt S H lt gt L SRO gt lt dap CTE 9 8XA8Z L H lt gt N3pg WOHdADn lt lt gt vi lt i Up lt 22 gt 1 zi m lt 82 gt 1 A 2 lt gt lt gt 02 Du ewo eevivanog 0 SEA 557700 2 3 0 H sd S50 8 701 1 063 9 lt 0 gt 0 138 H WOWBN3 8 93 9 6 lt gt 146 0 63000 7 010 2 WOHd AN
89. 00 1 AZE 92 lt 0 gt 00 1 9c lt 0 gt 4 H i2 H gt 42 H gt 42 lt zi HOQVi ez ez e lt 21 gt 00 1 Sc lt 1 gt Sc L HOQOVT1 Sc lt 1 gt 0 1 Sc lt 1 gt 0 1 rL Haava lt gt lt p uaa lt gt 8c lt gt 82 lt 91 gt 00 1 8 lt 91 gt 00 1 82 lt 91 gt 00 1 lt 91 gt 00 1 62 lt 91 gt 00 1 62 lt 9 gt 6c H 912Hdadv1 H L Haqv3 5 H lt 1 gt g H lt 1 gt 5 H lt 1 gt 2 soea E H lt eos 1 E lt DOE E H lt L WOHdAR L WOudAN WOHdAR WNOHdAR J lt 0 gt e VIVdWoH 8I VIVdWOH sre vivdWNOH lt 7i H e vIVaWou lt 7 lt 52 gt 71 7 lt H 0l VIVdWOH lt 81 gt 1 9e vivdWNoH EPVIVdWOH lt 6I VIVdWOH z vivdWNoH lt gt 8i lt 8r 8r H lt 82 gt 71 8r e VIVdWoH lt gt lt
90. 0014 Reserved Must be 0 2008 000C Any Value 2008 0004 Rom Byte Number 0302010046 2008 0000 Any Value Must be 3101 6 31 16 15 lt gt gt MLO 006375 The CALLG CALLS instruction is used to call the ROM routines and the RET instruction to return from them You must follow the VAX calling standard and therefore save registers R2 to R11 If you use R2 to R11 in the routine specify them in the procedure entry mask Registers R12 to R15 are specially handled CALLX RET and need not concern users writing code according to the standard The procedures are called at IPL 1216 with memory mapping disabled FIRMWARE 4 35 4 8 1 1 Optional Initialization Routine e user s devices are optionally placed a known state before self test is run console mailbox is optionally modified 4 8 1 2 System Scratch RAM The rtVAX 300 system firmware acquires a number of pages of RAM memory at power on initialization These pages are marked bad in the memory bitmap to prevent higher level software from modifying their data indiscriminately Table 4 6 lists the offsets in the scratch RAM to parameters and variables of interest to operating system or option ROM developers Table 4 6 Scratch RAM Offset Definitions Offsetig Name 00 Console Program Mailbox 01 Display console existence 02 Boot register 03 Reserved 04 SCR A RESTORE CONSOLE 08 SCR A SAVE CONSOLE Figure 4 7 shows
91. 1 1 Address Latch uoi a AWA a pate e ee eM n 8 1 8 1 2 Address 8 2 8 1 3 Access Cache Control Data Parity and 1 0 Cycle Types veu RE e 8 3 8 2 rtVAX 300 Interrupt 5 8 4 8 2 1 Interrupt 8 5 8 2 2 Interr pt Vector 2a uber xe Red 8 6 8 3 General Bus Interfacing Techniques 8 6 8 31 BUSETO S e aan s aur d Aeris 8 7 8 3 2 Using the rtVAX 300 as a Bus Master 8 7 8 3 3 Using the rtVAX 300 Bus Slave 8 8 8 3 4 Building Engine thertVAX 300 8 8 8 4 DMA Device Mapping 5 8 9 8 4 1 Q22 bus to Main Memory Address Translation 8 13 8 4 2 Q22 bus Map Registers 8 13 8 4 3 Dual Ported Memory 8 14 8 5 rtVAX 300 to Digital Signal Processor DSP Application Example len gum 8 15 8 5 1 DSP Private Memory 8 17 8 5 2 Words of DSP Private 8 18 8 5 3 DSP 4K Word Private Initialization ROM 8 18 8 5 4 DSP DMA 0 004 a PERIERE 8 18 8 5 5 Control and Status Register 8 19 8 5 5 1 1 Way Mirro
92. 1 9915450 62 ov N p 8v Z J 5 6Y 6V 22 6V 22 6V 22 8 01 61 OW OW OW 17 1 HS4 cmm XI EE mi m LES ubp L L L L H lt 0 gt vv i 52 Ed i 5 Pd 279 EESTI ERE Sp LV s 27 90 SL 52 89 SL 9230 Si 15250 z Haavdsa E 9 9 91 91 lt 5 gt 9224 H lt gt 6e ZY 013 383 883 0790 9LL9H 9LLOWH 9LLOWH 9LLINH lt 21 H lt gt se OI 9YOIc Ol ol H g uaavdsa 95 89 H lt 6 gt 57 H lt 01 gt ve 017 REM 621 H lt oe ZHY lt gt Ze lt 2 9206 H Pvivadsd 220 H e vivadsd 13 fk td H lt ag 15270 Heyswivaded 5248 H lt gt i9 Sk 89 H e vivadsa 9 264 H lt 01 gt 71 0460 9 ora H lt 99 H EIPVIVOdEG 28 H lt pl gt vivadsa za H lt gt 2 sid 920026 SL AS 98 700 lt 0 gt VLVddSd gt 1 lt 2 gt 1 45 lt gt lt gt 1 45
93. 1 if test should return immediately upon failure if 0 test may continue to completion and return an error if thereis a failure Bit 3 console DUART exists otherwise 0 Bit 4 1if LED test display exists otherwise 0 4 8 2 2 Self Test Routine Output The return status of each test is placed in register RO Return status meanings are as follows 1 Test passed successfully During self test the hexadecimal digit corresponding to the test number followed by 3 periods is displayed to indicate that the test passed 0 Device under test failed the test During self test the hexadecimal digit corresponding to the test number followed by a and 2 periods is displayed to indicate that the test failed 1 Device being tested is not present During self test the hexadecimal digit corresponding to the test number followed by and 2 periods is displayed to indicate that the tested option is not present however this is not considered a failure FIRMWARE 4 43 4 8 3 Linking the User Initialization User Test ROM To link the ROM containing the user initialization User Test routines you may use the following LINK command to generate a ROM image in file ROM _ IMAGE SYS LINK SYSTEM X20080000 NOHEADER EXE ROM IMAGE SYS roml obj rom2 0bj 4 9 Creation and Down Line Loading of Test Programs 4 9 1 User Supplied Test Procedures The LED status display values between 1016 and 7F 16 are res
94. 15 Display 14 12 DAL lt 19 gt 13 pg 13 188 10 24 cb DAL lt 18 gt 12 5 16 Riks g HOLD DAL lt 17 gt 5 p4 gt 1 BEANK Ros DAL lt 16 gt 4 po gt 1e 74 7 12 F32 74 11 Lco 2 C 40 Flo 7415175 Rabie DAL 25 13 pa DAL 24 12 7 R156 RST L 521 2 1B 4100 L7 pst 03 GER MLO 004450 6 20 Console and Boot ROM Interface Table 6 3 Application Module Address Decoder Pin Setting Input 1 AS 2 DAL 13 3 DAL14 4 DAL 15 5 DAL 16 6 DAL 17 7 DAL 18 8 DAL 19 9 DAL 20 10 DAL21 11 DAL 22 13 DAL23 14 DAL24 15 DAL25 16 DAL26 17 DAL27 18 DAL28 19 DAL29 Output 23 IUPCONE 22 IUPCPUST 21 SELROM 20 CYCRES Console and Boot ROM Interface 6 21 Figure 6 10 Sample Design Console Interface MLO 004449 P S foldout 6 22 Console and Boot ROM Interface Console and Boot ROM Interface 6 23 Figure 6 11 Sample Design User Boot ROM Bank 1 with Drivers MLO 004451 P S foldout 6 24 Console and Boot ROM Interface Console and Boot ROM Interface 6 25 Figure 6 12 Sample Design User Boot ROM Bank 2 ML O 004452 P S foldout 6 26 Console and Boot ROM Interface Figure 6 13 Application Module Address Decoder Memory Device Memory Locations DAL lt 29 2 gt Selected 29 2423 16 15 0807 02 20100000 2010003F 100000 00010000
95. 1FC Adapter vectors Interrupt 0 Not implemented by the rtVAX 300 200 7F FC Device vectors Interrupt 0 Correspond to DAL bus vectors placed on DAL lt 15 02 gt H 3 26 Hardware Architecture 3 1 12 6 3 1 12 7 Hardware Detected Errors The rtVAX 300 can detect three types of error conditions during program executi on e DAL bus parity errors indicated by M SER on a read being set This error cannot be distinguished if detected during a read reference e nternal cache tag parity errors indicated by M SER lt gt being set Internal cache data parity errors indicated by MSER 1 being set Hardware Halt Procedure The hardware halt procedure is the mechanism by which the hardware assists the firmware in emulating a processor halt The hardware halt procedure saves the current value of the PC in IPR 42 SAVPC and the current value of the PSL MAPEN 0 and halt code IPR 43 SAVPSL The current stack pointer is saved in the appropriate internal register The PSL is set to 041F 0000 I PL 1 16 kernel mode using the interrupt stack and the current stack pointer is loaded from the interrupt stack pointer Control then passes to the resident firmware at physical address 20040000 with the state of the processor as follows Register New Contents SAVPC Saved PC SAVPSL 31 16 07 00 Saved PSL 31 16 07 00 gt SAVPSL lt 15 gt Saved MAPEN 07 SAVPSL lt 14 gt Valid PSL flag unkn
96. 8 20 User Boot ROM Bank 1 with ML O 004483 Foldout Drivers Schem 8 21 User Boot ROM Bank 2 MLO 004484 F oldout Schematic 8 22 DSP and Private RAM MLO 004485 F oldout Schematic 8 23 DSP PGM Loader ROM MLO 004486 Turnpage Schematic 8 24 DSP DMA Xceiver and Parity MLO 004487 Foldout Generator Schm 8 25 DMA Address Drivers MLO 004488 F oldout F 2 Foldouts Schematic continued on next page Foldouts Table 1 Cont Turnpage and Foldout Illustrations Number Title MLO Number Format 8 26 VAX to DSP 1 Way Mirror ML O 004489 Foldout Register Schem 8 27 rtVAX 300 and DSP CSR MLO 004490 F oldout Schematic 8 28 DSP DMA Controller Schematic MLO 004491 F oldout 8 29 D A and A D Interface MLO 004492 F oldout Schematic 8 31 rtVAX 300 1 0 Pin Connectors MLO 006377 Foldout Schematic 8 32 Decoupling Caps ML O 004494 Foldout Foldouts F 3 986 v00 O IN W pig Wed YSE puz 1514 uua uM sv 4982 1129 ddd va vyo 00 00 W 214g X ysel
97. 8 64 Device Interfacing Physical Electrical and Environmental Characteristics This appendix discusses the following topics Physical characteristics Section A 1 e Electrical characteristics Section A 2 e Environmental characteristics Section A 1 Physical Characteristics The rtVAX 300 processor is a 117 mm x 79 mm 4 61 in x 3 11 in module encapsulated in a black painted metallic body The body acts as a heat sink to dissipate the heat generated by the rtVAX 300 The rtVAX 300 weighs 142 g 5 0 oz 31096 The rtVAX 300 has four mounting holes one on each corner Each hole is threaded for a 4 40 U S A screw You can use these holes either to bolt the rtVAX 300 to the mother board by using up to four screws or to provide extra grounding for the rtVAX 300 and its cover which can help reduce electromagnetic interference EMI The recommended torque on the screws is 0 50 4 5 in Ib 22096 You can connect the rtVAX 300 connectors to other modules by means of its 100 square 0 635 mm x 0 635 mm 0 025 in x 0 025 in pins Figure 1 5 detailed mechanical drawing of the pin layout You can mount the rtVAX 300 on another module either by using standard Sockets for example Digital part number 12 11004 05 by soldering Refer to Figure A 3 for footprint dimensions Figure A 2 Figure A 3 and Figure A 4 show a top bottom and side view of the rtVAX 300 respectively Physical Ele
98. 9 gt 1 lt gt 1 4 SLIM lt 8 gt 1 4 001 ar OA 1 HOLO3A8N3 or LA eA zi A 083 bres WA w 1800 6 1104 51 St 4 083 bres WA epo gi 204 1 NOHNOOT3S Sho ee door T WINI Oa ase 294 yg gH 4 001 WAOE 3 34 ted AS lt Seld zr EL Ed 9 1 3 00 908 vL onas SGE 1458 ar zaoa 1N3 04 or 4 15H 1 18149 gt 00 cis 38 a Be 1 i EE m aivis 8 28H Wd 0 09 peeu 8 avis ei 999 gt 3191 1948 31715 iz 989 6 54 3 ALVIS zz 0 H 52 umog dn 01 22 9r3 _ Wd 7 FH sc 505 5 pesn 199205 40 uonoejeg SW 09 eieis YOYI pue 5 00 req s 3 9 Tsa 2 1 05 2l Og T S lt SMT BAL 9 L 684 al 5 5 2 ZHI 798976 18XL ae E 9696 AIX Wd H
99. Dispatching Interrupts Vectors The system control block is a page aligned table containing the vectors used to dispatch exceptions and interrupts to the appropriate service routines Only device vectors in the range of 10016 to 7 16 should be used except by devices emulating console storage and terminal hardware The console reserves vectors 02 0 to 02CC and interrupts at IPL 1416 by means of IRQ 0 L The rtVAX 300 internal Ethernet coprocessor can interrupt at IPL 1516 This interrupt is daisy chained to the external interrupt request lt 1 gt L and is serviced before IRQ 1 L The vector is set by writing to the Ethernet coprocessor CSRO register at location 20180000 Interrupt Action Interrupts can be divided into two classes nonmaskable and maskable Nonmaskable interrupts cause a halt through the hardware halt procedure which saves the PC PSL lt 0 gt and a halt code in IPRs raises the processor IPL to 16 and then passes control to the resident firmware The firmware dispatches the interrupt to the appropriate service routine based on the halt code and hardware event indicators Nonmaskable interrupts cannot be blocked by raising the processor but be blocked by running out of the halt protected address space except those nonmaskable interrupts that generate a halt code of 3 Nonmaskable interrupts with a halt code of 3 cannot be blocked since this halt code is generated after a
100. ENBCONDATA PRESENT READCYC2 NEXT READCYC3 OUT ENBCONDATA PRESENT READCYC3 NEXT READCYC4 OUT ENBCONDATA PRESENT READCYC4 IF P4 NEXT FINISHREAD OUT ENBCONDATA OUT IOREADY DEFAULT NEXT READCYC4 OUT ENBCONDATA PRESENT FINISHREAD NEXT FINISHUP1 6 32 Console and Boot ROM Interface PRESENT FINISHUP1 NEXT FINISHUP2 PRESENT FINISHUP2 NEXT FINISHUP3 PRESENT FINISHUP3 NEXT IDLE PRESENT IOCYC1 NEXT IOCYC2 PRESENT IOCYC2 IF P4 NEXT FINISHIO OUT IOREADY DEFAULT NEXT IOCYC2 PRESENT FINISHIO EXT IDLE PRESENT ROMCYCI EXT ROMCYC2 PRESENT ROMCYC2 EXT ROMCYC3 PRESENT ROMCYC3 EXT ROMCYC4 PRESENT ROMCYC4 EXT ROMCYC5 PRESENT ROMCYC5 EXT ROMCYC PRESENT ROMCYC IF P4 NEXT FINISEROM OUT IOREADY DEFAULT NEXT ROMCYC6 PRESENT FINISHROM EXT IDLE PRESENT ILLEGAL1 EXT IDLE PRESENT ILLEGAL2 EXT IDLE PRESENT ILLEGAL3 EXT IDLE PRESENT ILLEGAL4 EXT IDLE PRESENT ILLEGALS EXT IDLE PRESENT ILLEGAL6 EXT IDLE PRESENT ILLEGAL EXT IDLE Console and Boot ROM Interface 6 33 6 4 3 Interrupt Decoder PAL 6 34 The interrupt decoder PAL decodes the CSDP 2 0 L CSDP lt 44 gt L and DAL lt 06 02 gt lines to determine when the rtVAX 300 is running an interrupt acknowledge cyde The CONIACK signal is asserted when the rtVAX 300 is running a console interrupt acknowledge cyde for a console
101. H oi Hdavi 44 H lt 24 H lt gt L 24 H lt 427 H lt lt lt lt lt gt 1 gz H lt gt H EL HdQY1 H EL HQQY eL Hdavi H gt H lt gt y y H lt gt sz gt 827 H lt lt gt gt 6 lt H lt H lt 60 lt 4 4 Si d L WOHdAn v WOHdAn 0 4 WOHdARn WOHdAQn lt 0 gt 1 H evivawou 9r vivaWou Em lt gt i P vivaWog8 vi lt 6 gt 1 vi H Zi vIVdaWog vi lt 52 gt 1 vi e vivaWog Si 0 vIVdaWoH Si H 8i vIvdWou Sr lt gt Si evilvawou m LPVIVOWOH m H 6r vivaWou m lt 42 gt 1 SP vivaWog lt gt 8i lt gt 8i lt 82 gt 1 lt lt gt 1 EP vIVdaWNoH lt 12 gt 1 H lt 62 gt 1 6i lt 9 gt 1 lt 02 ze vivaWwou 02 H lt 06 gt 1 02 lt gt 1
102. Ne Se Ne Se Ne Ne Ne Ne Ne Se Ne Ne Ne Ne Ne Ne Me Se Se Ne Me Se Ne Se Se Se Se e board level test 8 argument block offsets D 6 User Boot Diagnostic ROM Sample Ne Ne Ne Se Se Se Se Ne Ne Se Ne Ne Ne Ne s Ne Se s s Ne Ne Se Ne Se Se 5e e offset lt scratch address of scratch memory area failing pc address of longword to store failing pc if test fails expected data address of quadword that test can Store expected data if test fails actual data address of quadword that test can Store actual data if test fails flags board level test flags gt usrom share byte 300 usrom test 8 m lt gt ret return to caller Sbttl rtVAX 300 Board level Test 9 FUNCTIONAL DESCRIPTION This routine user supplied is called by the rtVAX 300 s resident firmware at system power on to do board level test 9 It is called at IPL 31 in kernel mode with memory management disabled CALLING SEQUENCE calls 5 300 usrom test 9 INPUT PARAMETERS scratch address of scratch memory area failing pc address of longword to store failing pc expected data address of quadword to store expected data actual data address of quadword to store actual data flags board level test flags IMPLICIT INPUTS kk OUTPUT PARAMETERS r0 test results IMPLICIT OUTPUTS kk ROUTINE VALUE 1 device not present or untestable Us
103. No internal states are retained no descriptors are owned and all rtVAX 300 visible registers are set to 0 except where otherwise noted Note The Ethernet coprocessor does not explicitly disown any owned descriptors so a descriptor s Own bits might be left in a state indicating Ethernet coprocessor ownership Table 3 41 lists the CSR fields that are not set to O after reset Table 3 41 Ethernet Coprocessor CSR Nonzero Fields After Reset Field Value CSR3 Unpredictable CSR4 Unpredictable 5 5 lt 16 gt 1 CSR6 lt 28 25 gt 1 CSR6 lt 31 gt Unpredictable after hardware reset 1 after software reset CSR7 Unpredictable CSR9 RT 1250 After the reset sequence completes the Ethernet coprocessor executes the self test procedure to do basic sanity checking After the self test completes the Ethernet coprocessor sets the initialization done flag 58 5431 The self test completion status bits CSR5 30 and CSR5 29 26 indicate whether the self test failed and the reason for the failure Note Self test takes 25 ms to complete Hardware Architecture 3 87 If the self test completes successfully the Ethernet coprocessor is ready to accept further rtVAX 300 commands Both the reception and transmission processes are placed in the stopped state Successive reset commands either hardware or software may be issued The only restriction is that Ethernet coprocessor CSRs should not be accesse
104. SBI quadword dear SBIQC w 3 55 37 O bus reset w 6 56 38 M emory management enable MAPEN r w 1 57 39 TB invalidate all TBIA w 1 58 3A TB invalidate single TBIS w 1 59 3B TB data TBDATA r w 3 60 Microprogram break MBRK r w 3 61 3D Performance monitor enable PMR 3 62 3E System identification SID r 1 register initialized on power up and by negation of RST when the processor is halted continued on next page Hardware Architecture 3 9 Table 3 3 Cont Internal Processor Registers Decimal Hex Register Mnemonic Type Category 63 3F Translation buffer check TBCHK w 1 127 64 7F 40 Reserved 4 register initialized on power up by negation of RST when the processor is halted 3 1 5 Interval Timer The rtVAX 300 interval timer IPR 24 is implemented according to the VAX Architecture Reference Manual for subset processors The interval clock control status register ICCS is implemented as the standard subset of the standard VAX ICCS in the CVAX chip NICR and ICR are not implemented Figure 3 2 Figure 3 2 Interval Timer 81 070605 00 MLO 004570 Bit Definition 31 07 Unused Read as zeros must be written as zeros lt 06 gt Interrupt enable IE Read write This bit enables and disables the interval timer interrupts When the bit is set an interval timer interrupt is requested every 10 ms with an error of less than 0 01 percent When the bit is clear interv
105. Sample Design DRAM Address MLO 004428 Turnpage Path Schematic 5 6 Memory Controller Octaword MLO 004433 Turnpage Read Cycle Timing 5 7 Memory Controller Octaword MLO 004432 Turnpage Write Cycle Timing 5 12 Memory Controller Schematic MLO 006376 Foldout Memory System Interface 5 13 DRAM Memory Array 1 ML O 006390 Turnpage Schematic Memory System Interface 5 14 DRAM Memory Array 2 ML O 006391 Turnpage Schematic Memory System Interface 5 15 RAM Data Latches Schematic MLO 004440 Turnpage Memory System Interface continued on next page Foldouts 1 Foldouts Table 1 Cont Turnpage and Foldout Illustrations Number Title MLO Number Format 6 4 Console Read and Write MLO 004444 Turnpage Timing 6 10 Console Interface Schematic MLO 004449 Foldout Console and Boot ROM 6 11 User Boot ROM Bank 1 with MLO 004451 Foldout Drivers Console and Boot ROM 6 12 User Boot ROM Bank 2 MLO 004452 Foldout Schematic 7 6 DC DC Converter MLO 004459 Turnpage 8 4 DMA Read Cyde Timing MLO 004467 Turnpage 8 7 DSP and rtVAX 300 Processor MLO 006394 Turnpage Interface 8 9 DMA Write Cyde Timing MLO 004472 Foldout 8 14 DRAM Address Path Schematic MLO 006397 Turnpage 8 15 Memory Controller Schematic MLO 004478 Foldout 8 16 DRAM Memory Array 1 MLO 004479 Turnpage Schematic 8 17 DRAM Memory Array 2 ML O 004480 Turnpage Schematic 8 19 Console Interface Schematic MLO 004482 Foldout
106. Status Codes The CSDP lt 4 0 gt L lines indicate the type of transfer cycle that is taking place Note that the address decoder for memory must include the CSDP lt 4 0 gt L cyde status information to prevent accidental memory access during an interrupt acknowledge cyde an IPR access cyde or an rtVAX 300 internal access cycle Interrupt acknowledge cycles are performed in the same way as a memory read cycle however CSDP 4 0 reads 1 addition IPR access cydes are performed in the same way as a memory read cyde however CSDP lt 4 0 gt reads 1 010 Lastly during rtVAX 300 internal access cycles CSDP lt 4 0 gt reads gt Thus if CSDP 4 0 indicates an interrupt acknowledge cycle access cycle rtVAX 300 internal access cycle do not allow the memory controller to perform a memory access cycle although the longword address on DAL 29 027 is within the system RAM space The remaining codes are useful for implementing a multiple processor system to lock and unlock dual ported memory however most simple applications need to decode these lines only to determine when the rtVAX 300 is running an interrupt acknowledge cycle an access cycle If an accessed with MTPR and instructions is implemented externally such as IPR 3716 the I O reset registers the read and write codes must be decoded to select the IPR The read lock code could b
107. The ROMs must be plugged into their correct sockets otherwise the rtVAX 300 will not boot 6 2 3 Boot ROM Interface Design Figure 6 5 shows the design of a 1M byte boot ROM connected to the rtVAX 300 s DAL lines This ROM is constructed from eight 128K x 8 bit 27010 1M bit ROMs Eight ROMs are needed to construct a memory size of 1M bytes and each ROM is connected to one of the four bytes of the rtVAX 300 DAL lines by means of 244 drivers During a read cycle it is not necessary to qualify each byte with the BM lt 3 0 gt L lines The rtVAX 300 reads only the byte s in the longword that correlate to an asserted BM 3 0 and ignores the other bytes However during write cycles you must write only to the byte s selected by an asserted BM lt 3 0 gt L line Since ROMs are read only and cannot be written to the select logic need not include the BM 3 02 L signals Figure 6 5 Sample Design Boot ROM Functional Block Diagram DAL lt 18 2 gt Drivers SELROM lt 0 gt Address Decoder ROM READ LWRITE SELROM lt 0 gt DS SELROM lt 1 gt SELROM lt 1 gt __ MLO 004445 Console and Boot ROM Interface 6 13 6 2 4 Boot ROM Address Decoder The address decoder shown in Figure 6 6 decodes the address placed on the DALs by the rtVAX 300 When valid address for ROM bank 0 between 20200000 and 2027FFFF is placed on the DAL bus the address decoder asserts the SELROMO signal In
108. The VAX architecture defines three kinds of hardware initialization e Power up 1 0 bus e Processor 341 Power Up Initialization Power up initialization occurs when power is restored and includes a hardware reset an I O bus initialization a processor initialization and initialization of several registers as defined in the VAX Architecture Reference Manual In addition to initializing these registers the rtVAX 300 firmware also configures main memory the local I O space registers An rtVAX 300 hardware reset occurs on power up and the assertion of RST L A hardware reset initiates the hardware halt procedure Section 3 1 12 7 with a halt code of 03 The reset also initializes some IPRs and most 1 space registers to a known state Those IPRs that are affected by a hardware reset 3 40 Hardware Architecture are noted in Section 3 1 4 3 The effect hardware reset has 1 space registers is documented in the description of the registers 3 4 2 I O Bus Initialization An bus initialization occurs on power up the assertion of RST L when the processor is halted or as the result of an MTPR to IPR 55 IORESET or console UNJ AM command The 1 bus reset register IORESET IPR 55 is implemented externally on the rtVAX 300 application hardware An of any value to IORESET causes an 1 bus initialization 3 4 3 Processor Initialization A processor initialization occurs on power up on the assert
109. a command line No action is taken a command until after it is terminated by a carriage return A null line terminated by a carraige FIRMWARE 4 9 return is treated as a valid null command No action is taken and the console reprompts for input Carriage return is echoed as lt CR gt lt LF gt e Delete deletes the last character that the operator previously typed The previous character is erased from the screen and the cursor is restored to its previous position Ctr C aborts processing of the current command if control has not been passed to another program such as the system level diagnostics The console program echoes this key as C causes the console to ignore transmissions to its terminal until the next is entered This key is echoed as o when it disables output but is not echoed when it reenables output Output is reenabled if the console prints an error message or prompts for a command from the terminal Displaying a REPEAT command does not reenable output When output is reenabled for reading a command the console prompt is displayed Output is also enabled by entering program I O mode and then pressing Ctr Q resumes output to the console terminal that has been stopped by cti S Additional are ignored Ctr G and are not echoed
110. addition when a valid address for ROM bank 1 between 20280000 and 202FFFFF is placed on the DAL bus the address decoder asserts the SELROM 1 signal These two signals are latched by the assertion of AS H and select the appropriate ROM bank when the DS L output signal of the rtVAX 300 is asserted the ROM outputs and drivers are enabled 6 2 5 ROM Address Latch Since the address is valid on the DAL 29 02 bus only at the beginning of any rtVAX 300 access latches are needed to preserve this address for the duration of the access cycle The 74F 373 latches shown in Figure 6 7 serve to latch the ROM longword address upon the assertion of AS L This latched address LADDR 18 02 is fed directly into the address inputs of the ROMs 6 2 6 ROM Read Cycle Timing 6 14 Figure 6 8 shows the read cycle timing for the ROM system The 5 must have valid data placed on them 28 ns before the rising edge of P1 DS L asserts 27 ns after the rising edge of P3 To operate without any wait states data must be available at the same time as the assertion of DS L 1 The access time of the ROMs used is 250 ns therefore you must insert three wait states ROMREAD asserts 5 ns after DS thus ROM read cycle access time is calculated as follows number of wait states x 100 to time DS assertion delay Data in setup time 74F 244 propagation delay 74F 20 propagation delay ROM read cycle access time In t
111. address lines to transfer memory and device addresses and data Since the address is valid only on this bus at the beginning of a device read or write cycle address latches are needed to latch the address These latches can be connected as shown in Figure 8 1 by using the AS signal to latch the address In addition the byte mask signals BM 3 05 write line WR L and status signals CSDP lt 4 0 gt must all be latched along with the address The outputs of these latches are used as inputs to address decoders and other application specific logic The outputs of these latches maintain valid address and cyde status information throughout the access cyde Device Interfacing 8 1 Figure 8 1 I O Device Interfacing Address Latches BM lt 3 0 gt LBM lt 3 0 gt DAL lt 21 18 gt LADDR lt 31 30 gt LADDR lt 21 2 gt Hold 74F373 From rtVAX 300 Hold To Application Logic DAL lt 31 30 gt 74F373 DAL 21 2 CSDP lt 4 0 gt LCS lt 4 0 gt LWRITE MLO 004464 8 1 2 Address Decoding 8 2 Address decoding to generate chip select signals must be performed for each memory mapped I O peripheral Programmable logic such as the PAL 22710 can be used to decode the rtVAX 300 addresses and generate the chip select signals for the memory subsystem and 1 0 peripherals To implement full address decoding for a byte word or longword wide peripheral 28 address bits must be decoded However mos
112. and cost and size are less important fast static RAMs are the better choice If cost size and power consumption are big concerns dynamic RAMs are the better choice For most applications the slower less expensive DRAMs are a good choice because the rtVAX 300 performance is greatly enhanced by its internal cache 5 3 Basic Memory Interface The rtVAX 300 can access up to 256M bytes of physical memory and up to 510M bytes of memory mapped 1 0 The physical memory addresses are in the range of 00000000 to OFFFFFFF Appendix C lists rtVAX 300 address assignments 5 2 Memory System Interface The device address is first multiplexed onto the DAL 31 00 bus and the data is then transferred through that same bus This reduces the number of external pins on the rtVAX 300 processor module however it requires the addition of external latches to store the device address for the duration of the bus Other bus information must also be latched such as the WR CSDP 4 0 L and sometimes the BM lt 3 0 gt L lines The latches must hold the bus cyde and address information while AS L is asserted When the rtVAX 300 attempts reading from or writing to memory it first places the memory s physical address DAL 29 027 DAL 01 00 are unused at this time and DAL lt 31 30 gt indicate the number of longwords that are to be transferred Table 5 4 shows the codes for DAL lt 31 30 gt and the number of longwor
113. are physically present in the Ethernet coprocessor and are directly accessed by the rtVAX 300 processor The rtVAX 300 processor can access these registers by a single longword instruction The rtVAX 300 perceives no delay and the Hardware Architecture 3 47 instruction completes immediately The physical CSRs contain most of the commonly used features of the Ethernet coprocessor The virtual CSRs are CSR8 through CSR14 These registers not directly accessible to the rtVAX 300 processor When the rtVAX 300 processor accesses one of these registers the Ethernet coprocessor controls access to these registers by fetching the requested information from on chip memory and passing it to the rtVAX 300 processor Table 3 17 lists and describes Ethernet coprocessor registers Table 3 17 Ethernet Coprocessor Registers Address Register Name 20008000 CSRO Vector Address IPL Sync Async see Section 3 6 1 1 20008004 CSR1 Transmit Polling Demand see Section 3 6 1 2 20008008 CSR2 Receive Polling Demand see Section 3 6 1 2 2000800C CSR3 Receive List Address see Section 3 6 1 3 20008010 5 4 Transmit List Address see Section 3 6 1 3 20008014 CSR5 Status Register see Section 3 6 1 4 20008018 CSR6 Command and M ode Register see Section 3 6 1 5 2000801C CSR7 System Base Register see Section 3 6 1 6 20008020 CSR8 Reserved 20008024 CSR9 Watchdog Timer Register see Section 3 6 1 7 20008028 CSR10 Revision Number and Mis
114. bus Whenever the CVAX processor generates a cacheable reference not stored in the internal cache a quadword transfer is generated on the DAL bus If the CVAX processor reference is a request 1 read then the quadword transfer consists of two indivisible longword transfers the first being a request stream read prefetch and the second being a request I stream read fill If the CVAX processor reference is a demand D stream read then the quadword transfer consists of two indivisible longword transfers the first being a demand D stream read and the second being a request D stream read fill Hardware Architecture 3 31 3 3 2 Internal Cache The rtVAX 300 includes a 1K byte 2 way associative write through internal cache with a 100 ns time CVAX processor read references access one longword at a time CVAX processor writes access one byte at a time A single parity bit is generated stored and checked for each byte of data and each tag The internal cache can be enabled disabled by setting dearing the appropriate bits in the CADR The internal cache is flushed by any write to the CADR as long as cache is not in diagnostic mode 3 3 2 1 Internal Cache Organization The internal cache is divided into two independent storage arrays called set 1 set 2 Each set contains a 64 row by 22 bit tag array a 64 row 72 bit data array Figure 3 7 shows the organization of the two sets Figure 3 7 I
115. by the following notation Signal Name HIGHEST BUS LOWEST IN BUS assertion For example the signal DAL 31 00 represents a 32 bit wide bus named DAL whose bits are numbers 0 to 31 each signal in this bus is active high Therefore if bit number 5 of this bus is connected to a gate the signal name for that bit is DAL 05 Associated Documents e Leonard Timothy E ed VAX Architecture Reference Manual Bedford MA The Digital Press 1987 Levy Henry M and Eckhouse Richard H J Computer Programming and Architecture The VAX 2d ed Bedford MA The Digital Press 1989 e rtVAX 300 Programmer s Guide e VAXELN rtVAX 300 Supplement xxi rtVAX 300 Test Box xxii You can order an rtVAX 300 test box and User s Guide from Design Analysis Associates The Design Analysis Associates part number for the text box is DAA 20RTVX 01 The address for Design Analysis Associates is Design Analysis Associates 75 West 100 South Logan UT 84321 U S A Phone 801 753 2212 FAX 801 753 7669 1 Overview of the 300 Processor The rtVAX 300 is a realtime target processor that is adaptable to running applications that benefit from a fully supported network connection Designed to be embedded in a robust computing network the rtVAX 300 processor is a 117 mm x 79 mm 4 61 x 3 11 module encapsulated in a black painted metallic cover The rtVAX 300 processor is intended to
116. command the console uses the value determined by BOOT 2 0 4 3 8 Console Program Messages Error messages consist of a 2 digit number prefaced by a question mark and an abbreviated text message Error message numbers are in the range 0016 through 7F 16 Section 4 5 discusses and illustrates startup messages that can be displayed during power on initialization Table 4 2 lists and describes firmware error messages FIRMWARE 4 21 Table 4 2 Firmware Error Messages Description 02 04 05 06 07 08 0A 0 10 11 12 13 19 1B 1D 1E 21 4 22 FIRMWARE 702 EXT HLT 04 ISP ERR 205 DBL 06 HLT INST 207 SCB ERR3 208 SCB ERR2 0A CHM FR ISTK 0B CHM TO ISTK 0C SCB RD ERR 10 MCHK AV 711 KSP AV 12 DBL ERR2 13 DBL ERR3 19 PSL EXC5 PSL EXC6 PSL EXC7 710 PSL EXC7 PSL EXC7 PSL EXC7 221 CORRPTN The external HLT line was asserted The interrupt stack was inaccessible or invalid during the processing of an interrupt or exception A machine check occurred while the processor was trying to report a machine check A kernel mode HALT instruction was executed SCB interrupt vector bits lt 1 0 gt equaled 3 SCB interrupt vector bits lt 1 0 gt equaled 2 A change mode instruction was executed when PSL 4S was set The exception vector for the
117. corresponds to a page of memory bit O corresponds to physical page 0 bit 1 corresponds to physical page 1 etc If a bit is 1 the corresponding page is considered a general purpose memory page that the operating system can use A page whose bit is 0 is considered bad or reserved by the console program and is not to be used as general purpose memory The initialization routine may change any bit from a 1 to a O to indicate that a page is reserved for any reason or is not to be passed to the loaded operating system as a normal memory page Bits set to 0 when the user initialization routine is called should not be set to 1 by user firmware The memory self test that executes later will change the bit that corresponds to any defective page of memory to a 0 Pages whose bit is 0 when the memory self test starts will not be tested 4 8 2 Optional User Supplied Diagnostic Routines User supplied ROM test routines can test any of the user supplied devices The seven longwords at 20080020 through 20080038 are checked for addresses of user supplied tests If these longwords contain a number in the range 20080040 through 200FFFFC it is considered the address of a user test and the test at this location is called with a CALLG CALLS instruction Any tests not used should have a 0 as the test address The processor context must be restored according to the calling standard after these ROMs exit 1 The LED status display values between 1016 a
118. cycle for octaword transfer reads 6 ThertVAX 300 completes the cycle by deasserting DS L and AS L Figure 2 11 illustrates octaword transfer read cycle timing and Table 2 8 shows responses to this Technical Specification 2 31 Figure 2 11 Octaword Transfer Read Cycle Timing ML O 004398 ps turnpage 2 32 Technical Specification Table 2 8 rtVAX 300 Responses to Octaword Transfer Read Cycle Parity Action for CCTLL RDYL ERRL Error Action for First Reference Other References H H X Wait for data Wait for data X H L X is aborted after end of is aborted after reading current longword end of reading current longword H L H H Proceed to second reference Proceed to next longword reference X L H L Interrupt processor Abort Interrupt processor Abort cyde cyde X L L X Finish reading longword Finish reading longword Abort cycle retry Abort cycle No retry 2 6 5 Single Transfer Write Cycle Figure 2 12 illustrates single transfer write cycle timing During an rtVAX 300 single transfer write cycle the rtVAX 300 writes one longword to the main memory or to an I O device An rtVAX 300 write cycle requires at least two microcycles Each transfer can be increased in increments of one microcyde The sequence of events of rtVAX 300 write cycle is as follows 1 The rtVAX 300 transfers the physical address onto the lt 29 02 gt lines The DAL 31 305 lines set
119. detected at the first P1 sample point but RDY L is asserted at the second P1 sample point the cyde will terminate according to the retry protocol c To request retry external logic asserts both L and ERR L DAL arbitration occurs after the initial read is terminated 6 ThertVAX 300 completes the cycle by deasserting AS and DS 2 6 8 2 External IPR Write Cycle An external processor register write cycle is initiated when an MTPR move to processor register instruction writes a category 3 processor register Section 3 1 4 3 defines processor register categories The only IPR register that should be implemented externally is IPR 3716 This is the reset register and any write to this register should reset all external devices Implementing any other IPR externally may cause future software incompatibilities An external processor register write cycle protocol is the same as an rtVAX 300 write cycle as shown in Figure 2 12 However CSDP 2 0 reads 0105 indicating an external IPR cycle cycle requires at least two microcycles may be extended in increments of one microcycle The sequence of events for an external processor register write cyde is as follows ThertVAX 300 transfers the processor register number onto DAL 07 02 and DAL lt 31 30 gt are set to 01 to indicate a longword transfer DAL 28 08 DAL 1 0 are zero BM 3 02 are all asserted CSDP
120. device select latches by using the D flip flops built into the 22V10 PAL 5 32 Memory System Interface Figure 5 9 Sample Design Address Decoder and Reset Power On and Power Glitch Reset Address Decoder PAL Includes latch 5V Note Socket used here 1 12 2 2 1N4154 Z 100K 470 Decode PAL 2 11 2 K SELRAM L IACKIPR L 1 RESETVAXL ENBCCTLDPE PEU CYCRES 2 1 2 1 L 10UF LL 10UF 47K 2 a 2 CSDP lt 2 gt L CSDP lt 1 gt L CSDP 0 L zd 1 1 1 lt 29 gt DAL 28 eis a lt 27 gt DAL 26 2 1 T DAL 25 74 13 2 2 HLTL ES Run 2 11 501 lt 225 1 ASH 3 5218 Halt 10 CSDP 4 L 8 DSL WRL 45V Note The rtVAX 300 uses CMOS 245 drivers for 2 2 1 1 the DAL lines and 244 drivers for the control lines 2K 2K These drivers have very fast rise and fall times which can fis 4 2K generate a fair amount of undershoot and overshoot Some 2 B PAL devices RAM chips may malfunction when exposed E 2 2 10 excessive overshoot and undershoot It may be necessary Run 2 1501 to isolate these devices from the rtVAX 300 signal lines with EC d TTL buffers or provide series termination resistors for these lines 3 g 18 ls Reset 4 MLO 006389 Memo
121. due to the buffer overflow When dear frames too long for the current receive buffer are transferred to the next buffer s in the receive list continued on next page Table 3 23 Cont CSR6 Bits Bit Name Access Description 9 8 OM R W Operating Mode Determine the Ethernet coprocessor main operating mode Value Meaning 00 Normal operating mode 01 Internal loopback The Ethernet coprocessor will loop back buffers from the transmit list The data will be passed from the transmit logic back to the receive logic The receive logic will treat the looped frame as it would any other frame and subject it to the address filtering and validity check process 10 External loopback The Ethernet coprocessor transmits normally and will enable its receive logic to its own transmissions The receive logic will treat the looped frame as it would any other frame and subject it to the address filtering and validity check process 11 Reserved for diagnostics continued on next page Hardware Architecture 3 59 Table 3 23 CSR6 Bits Bit Name Access Description 10 SR R W 11 ST R W 3 60 Hardware Architecture Start Stop Reception command When set the Reception process is placed in the running state the Ethernet Coprocessor attempts to acquire a descriptor from the receive list and process incoming frames Descriptor acquisition is attempted from the current position in the list the
122. during cache invalidate cycles Write cycles that do not involve cache invalidation CCTL L not asserted and read cycles can occur without wait states e Error ERR L 1 0 2 External logic asserts this signal to indicate an error associated with the current bus cycle and to end the bus cycle The rtVAX 300 processor asserts this signal when a bus timeout condition occurs Either the ERR L or the RDY L signal must be asserted to end the current bus cyde RDY L and ERR L are synchronous inputs and must be asserted within the timing values specified in Section 2 6 Note The rtVAX 300 processor has an internal timer that aborts any read or write cyde if an RDY L or an ERR L signal is not received from 16 to 32 us after AS L is asserted This provides for the bus timeout feature and prevents the rtVAX 300 processor from hanging when communicating with a nonexistent or faulty memory I O device 2 16 Technical Specification Cache Control Signal CCTL L During a DMA cycle the assertion of this signal by external logic initiates a conditional cache invalidate cyde The internal Ethernet controller also asserts this signal during DMA write cydes During an rtVAX 300 read cyde this signal is asserted to prevent the accessed data from being stored in the internal cache memory of the rtVAX 300 CCTL L is level sensitive and must be asserted synchronously with the timing sampling point for the rtVAX 300 processor read cy
123. edge of CLKA Figure 2 3 shows the timing cyde of the reset function 2 6 Technical Specification Figure 2 3 Timing Cycle Reset Function RST ER GONE _ DPE CSDP MLO 004389 Note Timing diagrams within this manual often contain circled numbers Table A 3 explains their meanings 2 3 3 Power Down Sequencing Power Fail The system power supply conditions external power and transforms it for use by the processor When external power fails the power supply requests a power fail interrupt of the processor by asserting the PWRFL L signal The PWRFL L signal is a maskable interrupt at IPL 1E 16 The power supply must continue to provide power to the processor for at least 2 ms after the interrupt is requested in order to allow the operating system to save state When the power supply can no longer provide power to the processor the processor halts through the assertion of the HLT L signal Refer to Appendix A for a summary of electrical characteristics Section 2 4 8 and Table 2 1 define the PWRFL L control signal and its functions Technical Specification 2 7 2 4 Pin and Signal Description This section briefly describes the input output signals and power and ground connections of the rtVAX 300 processor Table 2 1 lists bus and interface signals and their functions Table 2 2 lists pin assignments Figure 2 4 shows the pin layout Table 2 1 Bus Interface Signals
124. for board level testing and initialization The processor status LEDs are used to indicate the progress of rtVAX 300 self test and processor operating mode This chapter discusses the following topics e Console system interface Section 6 1 Booting from external ROM Section 6 2 e rtVAX 300 processor status LED register Section 6 3 e Console and boot ROM illustrations and programmable array logic Section 6 4 6 1 Console System Interface The rtVAX 300 processor module does not contain an internal console serial line unit SLU however 16 console registers are reserved in the rtVAX 300 processor reserved space to select and program an external Signetics 2681 console Dual Universal Asynchronous Receiver Transmitter SCN 2681 DUART These registers occupy physical locations 20100000 to 2010003F The built in firmware of the rtVAX 300 programs and communicates with the external SCN 2681 DUART which implements these console registers The firmware detects the absence of an external console DUART and will stop communication with the console and continue to boot if the console is inoperable or nonexistent Table 3 13 lists console register addresses and their read and write functions Reprinting of SCN 2681 documentation is by courtesy of the copyright owner North American Philips Corporation Console and Boot ROM Interface 6 1 Note Digital recommends that the console DUART be implemented in every application
125. functional and that the Ethernet network ID ROM contains a valid network address and correct checksum The Ethernet tests consist of the Ethernet selftest an Ethernet sanity test internal and external loop back testing of the Ethernet address filter testing and several others This test will determine if the Ethernet can be used for booting This is the final selftest 8F Ethernet sanity test failed 8b ROM network ID address test failed 8D Ethernet internal loop back failed 8C Ethernet collision test failed 8B Multicast Addressing Test failed 8A CRC Test failed 4 32 FIRMWARE continued on next page Table 4 5 Cont LED Test Number Code List Test LED Description No 89 Frame Type Test failed 88 Virtual Mode Test failed 80 Ethernet tests passed The remaining tests are reserved for the user application specific test ROMs and are not part of the rtVAX 300 7F 70 User supplied Test 8 6F 60 User supplied Test 9 5F 50 J User supplied Test 4F 40 User supplied Test 3F 30 J User supplied Test C 2F 20 User supplied Test D E 1 10 User supplied Test E of the routines below are in the rtVAX 300 gt System boot This is not a test If other tests pass the system either boots or enters console mode as determined by the Boot Register setting 05 System is awaiting or executing a console command 03 Console Restore Procedure called before control i
126. gt bus During read cycles the CSDP lt 3 0 gt L lines must be driven with valid parity while the DAL lt 31 00 gt bus is driven with the data The odd bytes DAL 31 24 15 08 are driven with odd parity and the even bytes DAL 23 167 07 007 are driven with even parity If the CSDP lt 3 0 gt L lines are not driven with valid parity during a read cyde when DPE L is asserted the rtVAX 300 performs a DAL parity error machine check as described in Table 3 11 If the Ethernet controller was bus master at the time of the error the CPU will be interrupted and will not perform a machine check To accommodate peripherals that do not generate or check parity the DPE L line is provided to cause the rtVAX 300 to ignore DAL parity DPE L must be driven along with the data during a read if it is driven low the rtVAX 300 checks the parity on all 4 bytes regardless of the assertion of BM 3 02 L if it is driven high the rtVAX 300 ignores the data parity information Table 5 2 lists the parity bits and byte mask lines associated with the 4 bytes of the DAL lt 31 00 gt bus Proper parity is required only when the DPE line is being asserted Read cycles from devices residing in the 1 0 space do not require parity generation Table 5 2 rtVAX 300 DAL Parity and Byte Masks Byte Parity DAL Mask CSDP Type 07 00 0 0 Even 15 08 1 1 Odd 23 16 2 2 Even 31 24 3 3 Odd Memory System Interface 5 7 Note
127. hardware reset Maskable interrupts save the PC and PSL raise the processor IPL to the priority level of the interrupt except for vectors with DAL lt O gt H set to 1 where the processor IPL is set to 1716 independent of the level at which the interrupt was received and dispatch the interrupt to the appropriate service routine through the SCB 3 14 Hardware Architecture Table 3 4 lists the various interrupt conditions for the rtVAX 300 plus their associated priority levels and SCB offsets Table 3 4 Interrupts Priority Interrupt Condition SCB Offset Nonmaskable Reset asserted HLT L asserted 2 1 Unused PWRFL L asserted 0 10 18 17 IRQ lt 3 gt L asserted Device vector on DAL lt 15 02 gt 16 Interval timer interrupt CO IRQ lt 2 gt L asserted Device vector on DAL lt 15 02 gt 15 Ethernet coprocessor Vector placed in Ethernet coprocessor interrupt CSRO IRQ lt 1 gt L asserted Device vector on DAL lt 15 02 gt 14 Console terminal 02CO IRQ lt O gt L asserted Device vector on DAL 15 022 13 10 Unused OF 01 Software interrupt 84 BC requests 1This condition forces execution to the resident firmware s dispatcher with a halt code of 3 hardware reset This condition forces execution to the resident firmware s dispatcher with a halt code of 2 external halt Note If the external device sets DAL 002 of the vector that it places on the bus the rtVAX 300 p
128. iB 5 DSL 13 WRL 11 lt 6 gt DAL 5 DAL 4 H DAL 3 H DAL 2 H CSDP 4 L 5 50 lt 2 gt 4 5 lt 1 gt 3 CSDP lt 0 gt L 2 Jon IN ko ASH PAL 22 10 131 23 NC Cycle Reset Ro 22 21 520 18 85 18 DPEDRIVE L t7 ENBVECTOR L IOIACK L R2 t5 CONIACK L IACK L D10 D9 D8 D7 06 05 04 D3 D2 D1 DO CLK MLO 006396 Figure 8 13 Device Interfacing Address Latches Address Latches 8BF LADDR 17 DAL lt 17 gt DAL lt 16 gt LADDR lt 16 gt DAL lt 15 gt LADDR 15 DAL 14 LADDR 14 DAL 13 LADDR 13 LADDR 12 DAL lt 12 gt DAL lt 11 gt LADDR lt 11 gt H DAL lt 10 gt LADDR 10 LADDR 31 LADDR 30 ASL DAL 9 H LADDR 9 LADDR lt 8 gt DAL 8 H DAL 7 H LADDR 7 DAL 6 H LADDR 6 DAL 5 H LADDR lt 5 gt DAL 4 LADDR 4 LADDR 3 DAL 3 H DAL 2 H LADDR 2 H ASL lt 3 gt L lt 2 gt BM lt 1 gt L lt 0 gt WRL DAL lt 31 gt H DAL lt 30 gt H DAL lt 21 gt H DAL lt 20 gt H DAL lt 19 gt H DAL lt 18 gt H Address Latches LBM lt 3 gt L LBM lt 2 gt L LBM lt 1 gt L LBM lt 0 gt L LWRITE L LADDR lt 31 gt H LADDR lt 30 gt H LADDR lt 21 gt H LADDR lt 20 gt H
129. in Figure 5 9 are both stable 10 ns after the rising edge of AS H The 4 ns delay of the AS inverter in Figure 5 12 must be added therefore and SELMEM are delayed 14 ns after the falling edge of AS Since AS falls 23 ns after the CLKA rising edge IACKIPR and SELMEM assert 37 ns 23 ns 14 ns after the CLKA edge Thus the setup time for these two signals is 13 ns 50 ns 37 ns which is greater than the 12 ns requirement Similar analysis was done to the rest of the memory controller sequencer setup times and Table 5 6 lists the setup times of all the signals Table 5 6 Memory Controller Setup Times Minimum Actual Signal Name Setup ns Setup ns IACKIPR 12 13 SELRAM 12 13 LWRITE 12 62 12 42 05 12 22 SYNCHAS 12 21 REFREQ 12 30 RST 12 35 LADDR30 12 62 LADDR31 12 62 INVADDR2 12 38 INVADDR3 12 38 5 22 Memory System Interface 5 10 3 Memory Subsystem Longword and Quadword Read Cycle Timing Section 2 6 specifies the memory system longword quadword and octaword read and write cyde timing The rtVAX 300 bus timing is synchronous with CLKA and CLKB This timing is used to derive the states required by the memory controller state machine The state machine shown in Figure 5 4 illustrates sample operation of the memory controller Figure 5 5 shows the sample longword and quadword read timing The critical timing parameters for the rtVAX 300 memory system must be satisfied along with the t
130. indicating that the register number BM lt 3 0 gt CSDP lt 3 0 gt L and WR L are valid and can be latched 2 38 Technical Specification Figure 2 14 Interrupt Acknowledge Cycle CLKA P1 P3 P1 P3 P1 P3 CLKB P2 P4 P2 P4 P2 DAL DPE MITTIT Internal Cyc CSDP 3 0 5 49 2 D WR M JE RDY ERR MLO 004401 4 ThertVAX 300 asserts DS L to indicate that DAL are available to receive incoming data 5 The rtVAX 300 checks for a complete cycle once every two clock cycles starting at the next possible P1 The response of external logic is as follows Ifthe processor register is implemented external logic transfers the required data on DAL 31 00 H asserts DPE L if parity is to be Technical Specification 2 39 checked and asserts with ERR deasserted The rtVAX 300 reads the data from DAL 31 00 H b If the processor register is not implemented external logic asserts ERR L with RDY L deasserted The rtVAX 300 ignores the data on DAL 31 00 and internally forces the result to zero A detected parity error will force the result to zero and is not reported Therefore it is recommended that DPE L remain asserted during a processor register read The unimplemented response will be recognized only if RDY L is deasserted for two consecutive P1 sample points If this response ERR L asserted and RDY L deasserted is
131. its own transmissions In either loopback mode the rtVAX 300 software must e Build the data frame that is to be transmitted 3 90 Hardware Architecture e Provide a receive buffer for the looped data that is to be returned to the rtVAX 300 processor Loopback operation is selected by the operating mode bits 5 6 lt 09 08 gt 3 6 5 2 3 Time Domain Reflectometer Ethernet coprocessor has a time domain reflectometer to help find faults on the Ethernet cable The detects shorts and opens on the cable that result in reflections on the cable Hardware Architecture 3 91 4 FIRMWARE The rtVAX 300 processor firmware contains the following components A subset of the VAX console program Power on and Ethernet self tests e Bootstrap for booting from Ethernet serial lines or PROM The rtVAX 300 processor uses the clock interrupt for various timers Portions of the code run at IPL 1516 to allow clock interrupts No other interrupts are used The rtVAX 300 system firmware is the software in the system ROM The corresponding firmware sections provide these functions e Power on self test Tests the base system and the optional console at power on e System configuration Handles integration of the optional console and memory with the base system by accessing external devices sizing memory and checking for console hardware registers e Dispatcher Handles entry to the system ROM by booting or enteri
132. j P11P2 P3 PA PTIP2TPSTPATPTIP2 IPA TPT IP2 P3 PTIPZTPSTPATPTIP2 IPS PN PN YN FN FN YN FN FN FN DAL lt 31 0 gt pc vecrdR AoonEss WAITE BYTE ASL DSL LWRITE L 7 CONIACK L IOREADY L ENBVECTOR L IDLE IDLE IlACKCYC2 IDLE IDLE IDLE IACKCYC1 FINISHIACK IDLE IDLE IDLE MLO 004443 6 1 4 Console Timing Parameters To ensure reliable console operation all timing parameters of the SCN 2681 DUART and the rtVAX 300 must be satisfied Table 6 1 lists important timing parameters of the SCN 2681 DUART 6 6 Console and Boot ROM Interface Table 6 1 2681 DUART Timing Parameters Minimum Time Parameter Name ns Maximum Time ns Address setup time to WR assertion 10 Address hold time to RD WR assertion 0 WR RD pulse width 225 Data valid after RD low 175 Data float after RD high 100 Data in setup before WR deasserts 100 Data in hold after WR deasserts 20 High time between WR and RD 200 Figure 6 4 shows a timing diagram of the console read and write This state machine is docked on CLKA therefore all state transitions occur on the positive edge of CLKA The setup times for each of these inputs were calculated like those of the memory controller and meet the requirements of the 15 ns 22V10 PAL that was used 6 141 Console Address Setup and Hold Times When the rtVAX 300 is acce
133. ment corruption The processor is forced into kernel mode at IPL 1 16 and mapping is disabled so that all addresses are physical 1 e 20040004 5 5 TYPE This is the system type register The value representing the rtVAX 300 is 09nn0002 where nn is a 2 bit quantity representing the major and minor revisions The high byte is always 09 representing the rtVAX 300 The next byte contains two 4 bit quantities identifying the major and minor version of the resident firmware The lowest byte 2 identifies the rtVAX 300 as a single user system Figure 4 4 shows the system type register Table 4 1 lists its fields 20040008 reserved for ROM part data 24 bytes 6 bytes in each of the 4 system ROM s are reserved for information contained in each ROM byte Section 4 1 1 lists the information contained in each ROM byte Figure 4 4 System Type Register 31 2423 2019 1615 08 07 00 MLO 004423 Table 4 1 System Type Register Fields Data Bit Definition lt 31 24 gt System processor type of the 300 This field is 0916 lt 23 20 gt Firmware Revision Major ID This field is 0115 for the 300 Firmware Version V1 0 lt 19 16 gt Firmware Revision Version Minor ID This field is 0016 for the rtVAX 300 Firmware Version V1 0 15 082 Reserved This field is 0016 for the rtVAX 300 Firmware Version V 1 0 07 00 Licensing bitmask Unused The of this field is 0216 indicating a single user system
134. mm 0 410 in 16 764 mm 0 660 in 10 922 mm 0 430 in 8 636 mm 0 340 in MLO 006398 Physical Electrical and Environmental Characteristics 3 Figure A 2 rtVAX 300 Top View 490000000000000000000000000 50000000000000000 00000000042 rtVAX 300 78 994 mm 0 254 mm 3 110 in 0 01 in 9 0 000000000000000000000000 1 B50 2 117 094 0 254 4 610 0 01 MLO 004496 A 4 Physical Electrical and Environmental Characteristics Figure A 3 rtVAX 300 Bottom View 72 517 mm 0 254 mm 2 540 mm 0 254 ____ gt Le 2 855 in 0 010 in 0 100 in 0 010 in a 68 580 mm 0 254 mm gt 6 422 0 254 4 2 700 0 010 0 255 in 0 010 in la 66 040 mm 0 254 ______ gt 2 600 in 0 010 in 6 422 mm 0 254 mm _ 0 255 in 0 010 in _ D t No 4950 00 SG oo oo eM oo oo 81 280 mm oa 0 254 mm 8 200 in 0 010 in 2 117 094 104 140 un 0 254 mm 0 254 mm 4 610 4 100 0 010 in 0 010 in oo 110 617 mm 0 254 mm 4 355 in 0 010 in d
135. ns 615 199 ns The FINISHUP1 to FINISHUP3 and IDLE states deassert the ENBCONDATA signal for at least 200 ns after each console read or write cycle This satisfies the 200 ns RD and WR deassertion time after each console read or write cycle 6 1 4 4 Console Write Cycle and Data In Setup and Hold Timing Analysis During console write cycles the WR line of the DUART must be asserted for at least 225 ns The data is latched in the DUART internal register upon the deassertion of this line Figure 6 4 shows the console write cycle timing The ENBCONWR line is deasserted when the console state machine deasserts the ENBCONDATA line The console state machine asserts the ENBCONDATA line on the P3 edge after AS asserts ENBCONDATA remains asserted for five CLKA cycles and deasserts on the P3 edge of CLKA before the cycle ends At this time the console state machine asserts asserting the 300 RDY L line and ending the console write cycle Memory system write cycle data in setup time is calculated as follows 5 50 DAL write data setup 74F 00 minimum propagation delay 741 245 propagation delay Memory system write cycle data in setup time In this case data in setup time 250 ns 23 ns 2 ns 6 ns 269 ns 6 10 Console and Boot ROM Interface The input data is valid on the DALs until after the P1 edge of The ENBCONDATA line deasserts on the P3 edge of CLKA Thus the data in hold time is c
136. of the following occurs is reading or writing information to or from memory internal or external ROM internal or external registers the Ethernet coprocessor or any other external memory or peripheral device Ethernet coprocessor is reading from or writing to external RAM e is acknowledging an interrupt internal or external to the rtVAX 300 2 6 1 Microcycle Definition A microcyde is the basic timing unit for a CVAX bus cyde A microcyde is defined as four clock phases as shown in Figure 2 8 A microcyde equals two CLKIN cycles Figure 2 8 Microcycle Timing 1 microcycle 50 ns CLKA CLKB MLO 004395 2 6 2 Single Transfer Read Cycle Both the CVAX and the Ethernet coprocessor inside the rtVAX 300 can initiate a single transfer read cyde This cyde requires at least two microcydes microcycles can be added in increments of one microcycle Figure 2 9 shows the timing of a single transfer read cycle Note space read references always occur as single transfer read cycles Technical Specification 2 25 Figure 2 9 Single Transfer Read Cycle Timing CLKA P1 P3 P1 P3 P1 P3 CLKB P2 P4 P2 P4 P2 69 A lt gt AS 6 B T 2 7 MLO 004396 The sequence of events is as follows The CVAX transfers the physical address onto the DAL lt 29 02 gt lines The DAL lt
137. operating environment The system firmware treats this like a processor restart caused by a kernel mode HALT e The system powers on the Boot Register bits 2 0 are specified to be Halt or the boot switch is set for a boot option and the boot operation fails Boot fails for any reason External HALT the external HLT line to the rtVAX 300 is asserted at any time This lineis typically connected to a user supplied HALT button 4 3 2 Compatible Console Interface The rtVAX 300 ROM code includes console support similar to that supported by the rest of Digital s VAX product line 4 3 3 Entering and Exiting from Console Mode Normal operation of the rtVAX 300 is in program 1 mode The mode is set to console 1 0 mode by one of the methods described in Section 4 2 You issue the BOOT START or CONTINUE console command to exit from console mode Caution The operator can put the system in an inconsistent state by issuing console commands Processor operation in such a state is undefined If power fails the rtVAX 300 processor enters the power off state and loses all context that is memory and register contents 4 3 4 Console Keys The rtVAX 300 console 1 0 program responds to the following keys and signals Note During execution of the XFER console command data directed to and from the console are interpreted as binary data and thus may not be interpreted as described below Return ends
138. progress do boot endif halt do halt See Section 4 2 1 See Section 4 2 2 See Section 4 2 3 4 2 1 Restart The restart operation searches system memory for a restart parameter block RPB This data structure is constructed by the VAXELN operating system or by the console program If a valid RPB is found the operating system is restarted at an address specified in the RPB An internal flag indicating restart in progress is set to prevent repeated attempts to restart a failing operating system A system restart can occur as the result of a processor halt 4 2 2 Boot The system firmware can load and start bootstrap an operating system The firmware searches for a section of correctly functioning system memory large enough to hold a primary bootstrap program If the firmware finds such a section of memory it loads and starts the primary bootstrap The primary bootstrap then loads and starts the operating system An internal flag indicating that a bootstrap is in progress is set to prevent repeated attempts to boot the operating system when one attempt has already failed FIRMWARE 4 7 System bootstrap occurs when the operator enters a BOOT command when the processor halts 4 2 3 Halt The console Halt program interprets commands entered on the console terminal and controls the processor operation The following people may use console terminal operator to boot the operating system custo
139. provide series termination resistors for these lines MLO 004447 Table 6 2 shows a list of ROM access times and the number of required wait states The delay of the drivers if placed between the ROM outputs and the DAL lines must be added to the ROM access time Table 6 2 Typical ROM Access Time continued on next page Console and Boot ROM Interface 6 15 Figure 6 7 Sample Design Address Latches Address Latches CTL and DPE Drivers 1B 74 CONE L 12 gt CCTLL DR 17 H DAL 17 EUM 13 DR 16 DAL 16 H mE 74 DR H DAL 15 H 515 45V 9115125 gt DEBE lt 14 gt H DR 14 zs 10 LWRITE H 94 DAL lt 13 gt DR 13 DR 12 H DAL 12 T iB CONE L 124 DR 11 1 SELCONROML ENBROM L 1 DR lt 10 gt H DAL 10 H Note Parity checking not enabled because caching not allowed on console reads P State Flip Flop RSTL Address Latches 14 1B 2 D PR 1 5 74 CLKA 3 F74 E18 LADDR 9 CLR DAL 9 1B DAL lt 8 gt ASL 574 ASH F04 E4 DAL lt 7 gt H LADDR lt 7 gt H WRL LWRITE L LADDR lt 6 gt H 12 LADDR lt 18 gt H Ht 04 Address Strobe Synchronizer LADDR H LBM L DAL 5 2 BM lt 3 gt L 592 1B D3 ASL 49 PT LADDR lt 4 gt H
140. re 20 SEE Pod gt 6O as aang 9 6 24 H ol QP ENA s SB 993 3IVIS 6l 6 9497 31VIS og 949 Jojuno 31VIS 12 umoq dn oa 31v18 18 8 pa 104 5 9613 1 gO 58 5 td 01 22 Vd vl lt SS Va 9 s gt ye ig sw 091 pesn a lt 9 gt 1 0 ob euupey eris MOYI WOH 05100 9 083 EJ v lt 1820 2 ME wz ae o B 1 SLM Jav 3 aw 1 lt gt 903 ye 684 R 1 9 ZHN 79898 18Xl n zs 992 gt 8i 9296 X19 1X 101 923 9696 tn Wd s gt z AS eui YL lt 6 gt 19 HA 894 at ek 9 00 H lt ord vi Dar H sead 4 y H zp Haavi A D 7 euaavi 2 T lt gt 7 oy Be TINOJ S H 09 1 lt 8i S T 022 550 rig sce ar ma z 1 H ia 6i 08H lt 7 7 L ev
141. recommended a dedicated path be used for voltage return between the AUI connector and the power supply Avoid coupling this noise into the logic ground of the board 9 DC to DC converter is used to create 9V supply that is necessary to run the DP8392 chip when used The ground reference for the 9V supply is the ThinWire coaxial cable ground This supply and its ground must be DC isolated from the other grounds in the design Network Interconnect Interface 7 19 7 6 34 Grounding 7 20 Four different ground references must be considered in the Ethernet interface Logic ground This is the reference for the system 45V supply Chassis ground This is the lowest available impedance path to earth usually provided by the AC power line Voltage return This is the reference for the 12V supply Keep the voltage drop over the path to the power supply small to ensure that a minimum requirement of 11 28V is delivered to the AUI connector when 0 5 A are being drawn from the 12V supply Ultimately the logic chassis and voltage return grounds may all be common However it is recommended that these three grounds be tied together only at one location at the power supply Connector grounding ThinWire BNC connector grounding requirements if used The shell of the BNC connector must be common with the ground of the DP8392 chip and the return of the 9V supply This ground must be DC isolated from the remaining thr
142. references the reference is never stored in the cache so an internal cache miss occurs and a single longword reference is generated on the DAL bus Hardware Architecture 3 33 On cacheable references the physical address must translated to determine if the contents of the referenced location resides in the cache The cache index field bits 8 3 of the physical address is used to select one of the 64 rows of the cache with each row containing a single entry from each set The cache tag field bits 28 92 of the physical address is then compared to the tag block of the entry from both sets in the selected row If a match occurs with the tag block of one of the set entries and the valid bit within the entry is set the cache contains the contents of the referenced location and a cache hit occurs On a cache hit the set match signals generated by the compare operation select the data block from the appropriate set The cache displacement field bits 2 02 of the physical address is used to select the byte s within the block No DAL bus transfers are initiated on CVAX processor references that hit the internal cache If no match occurs the cache does not contain the contents of the referenced location and a cache miss occurs In this case the data must be obtained from either second level cache or the main memory controller so a quadword transfer is initiated on the DAL bus Figure 3 11 3 3 2 3 Internal Cache Data Bloc
143. settle after each access The RAS precharge time for the DRAMs is maintained because the memory controller enters the FINISHUP state followed by the IDLE state after every memory access or refresh cycle During these two states all the memory controller s outputs are unasserted and the controller stays in each state for 50 ns This deasserts the RAS and CAS lines for at least 100 ns after each memory access satisfying the RAS and CAS precharge requirements 5 30 Memory System Interface Figure 5 8 Sample Design Memory Controller Refresh Timing Pi P2 P2 P4 P2 P2 P4 CLKA H CLKB H REFREQL REFCYCL ENBCASL RASL IDLE IDLE IDLE REFRESHCYC i FINISHUP IDLE STARTREFRESH ENDREFRESH MLO 004430 5 10 7 DAL Bus Turnoff Time The DAL bus turnoff time must also be preserved to prevent bus contention This time is 35 ns P 10 after the P1 edge when DS has deasserted After that time the rtVAX 300 begins to drive the DAL bus with the next address The DRIVERAM signal which turns off the DRAM latches deasserts one 74 20 gate delay after DS Thus the turnoff time is as follows DS deassertion delay 742 20 propagation delay 74F 373 turnoff time Turnoff time In this case turnoff time 25 ns 5 ns 7 ns 37 ns after P1 edge Memory System Interface 5 31 Because the memory system is deactivated in 37 ns transceivers not required between the rtVAX
144. stack pointer internal processor register Interrupt status register interrupt service routine Kernel stack pointer internal processor register Memory management enable internal processor register Memory error register DUART channel A mode registers DUART channel B mode registers Memory system error internal processor register Definition NI Network Interface OPCR DUART output port configuration register POBR PO base internal processor register POLR PO length internal processor register P1 base internal processor register PILR P1 length internal processor register PCBB Process control block base internal processor register PPTE Processor page table entry processor PTE PTE page table entry entry in page table of memory map PWRFL Power failure interrupt bus interface signal QMR Q22 bus map register RAM Random access memory RAS Row address strobe RCV Ethernet receive data bus interface signal RDY Bus ready input interface signal RHRA DUART channel A Rx holding register RHRB DUART channel B Rx holding register ROM Read only memory RST Reset bus interface signal SAVPC Console saved PC internal processor register SAVPSL Console saved PSL internal processor register SBR System base internal processor register SCBB System control block base internal processor register SGEC Second generation Ethernet coprocessor SIA Serial interface adapter SID System identification internal processor registe
145. state of the POBR POLR P1BR P1LR SBR and SLR should be logged Error Description 5 The calculated virtual address for a process PTE was in the PO space instead of in the system space when the CVAX processor attempted to access a process PTE after a translation buffer miss 6 The calculated virtual address space for a process PTE was in the P1 space instead of in the system space when the CVAX processor attempted to access a process PTE after a translation buffer miss 7 The calculated virtual address for a process PTE was in the PO space instead of in the system space when the CVAX processor attempted to access a process PTE to change the PTE M bit before writing toa previously unmodified page 8 The calculated virtual address for a process PTE was in the space instead of in the system space when the CVAX processor attempted to access a process PTE to change the PTE M bit before writing toa previously unmodified page Interrupt errors indicate that the interrupt controller in the CVAX processor requested a hardware interrupt at an unused hardware IPL The most likely cause of this type of a machine check is a problem internal to the CVAX chip Machine checks due to unused IPL errors are nonrecoverable A nonvectored interrupt generated by a serious error condition memory error power fail or processor halt has probably been lost Execution of the operating system should be terminated Hardware Arc
146. supports virtual DMA and buffer management It contains one 120 byte FIFO queue for data reception and another for data transmission with loopback capability It complies with IEEE Standard 802 3 It provides collision handling transmission deferral and retransmission and automatic jam and backoff It has a continuous packet rate of up to 14 000 frames per second The Ethernet interface can perform DMA transfers directly to the 256M bytes of system RAM The coprocessor is programmed by reading from and writing to a set of registers on the rtVAX 300 Figure 7 1 shows a block diagram of an interface which supports AUI connection to Thickwire and ThinWire or direct connection to ThinWire Proper operation of Ethernet IEEE 802 3 interface requires precise and specific physical design of the power and ground arrangements Briefly components connected to the trunk network cable must be DC and low frequency isolated from system ground This isolation is provided by the isolation transformer and dc dc converter Figure 7 3 illustrates this isolation 7 2 Network Interconnect Interface Figure 7 1 Network Interconnect Controller Block Diagram Application 300 Transceiver Chip ThinWire Isolation Transformer Switching Unit AUI Cable Media MLO 004456 7 3 Thickwire Network Interconnect Thickwire Ethernet interconnect requires addition of an external is
147. the cost of the memory elements to determine the type of memory devices which are used To improve its performance the rtVAX 300 processor contains a 1K byte cache This cache has a very high hit rate greater than 7096 for some applications and allows the rtVAX 300 to read a longword one microcycle This cache helps to provide very high performance with relatively slow external memory by satisfying many of the required processor read operations in one The best processor performance is still realized with the fastest memory system so the memory system should be designed to be as fast as practical 5 2 Static and Dynamic RAMs The memory system can be constructed from either static or dynamic RAMs Dynamic RAMs provide more storage at a lower cost per bit than static RAMs and they also require less PC board space for the same density Static RAMs store data more reliably than dynamic RAMs because the data is stored in a latch and not as a charge on a capacitor Static RAMs have faster access time than dynamic RAMs Dynamic RAMs require refresh cydes to retain the stored data and also require address multiplexing and precise strobe ti ming These requirements complicate the design of a memory controller for DRAMs Once the size of the external memory system has been determined the type and speed of the memory elements must be defined after weighing all of the factors mentioned above If performance is the only issue
148. the frame size This bit may set only if data chaining is disabled 5 6 lt 07 gt 1 Runt Frame When set indicates that this frame was damaged by a collision or premature termination before the collision window had passed Runt frames will only be passed on to the rtVAX 300 if CSR6 lt 03 gt is set Meaningless if RDESO 00 is set Data Type Indicates the type of frame the buffer contains according tothe following table Value Meaning 00 Serial received frame 01 nternally looped back frame 10 Externally looped back frame Serial received frame The Ethernet coprocessor does not differentiate between looped back and serial received frames Therefore this information is global and reflects only CSR6 lt 09 08 gt Length Error When set indicates a frame truncation caused by one of the following e The frame segment does not fit within the current buffer and the Ethernet coprocessor does not own the next descriptor The frame is truncated e The Receive Watchdog timer expired CSR5 lt 05 gt is also set Error Summary The logical OR of RDESO bits 00 01 03 06 07 11 14 Frame Length The length in bytes of the received frame Meaningless if RDESO lt 14 gt is set Own bit When set indicates the descriptor is owned by the Ethernet coprocessor When cleared indicates the descriptor is owned by the rtVAX 300 The Ethernet coprocessor clears this bit upon completing processing of the d
149. the frame transmission aborted due to an error In the latter cases the transmission process is placed in the suspended state 02 RI R W1 Receive Interrupt When set indicates that frame has been placed on the receive list Frame specific status information was posted in the descriptor The reception process remains in the running state 03 RU R W1 Receive Buffer Unavailable When set indicates that the rtVAX 300 owns next descriptor on the receive list and could not be acquired by the Ethernet coprocessor The reception process is placed in the suspended state Once set by the Ethernet coprocessor this bit will not be set again until a poll demand is issued and the Ethernet coprocessor encounters a descriptor that it cannot acquire To resume processing receive descriptors the rtVAX 300 must issue the poll demand command continued on next page Hardware Architecture 3 53 Table 3 22 CSR5 Bits Bit Name Access Description 04 05 06 07 16 ME RW TW BO DN R W1 3 54 Hardware Architecture Memory Error Is set when any of the following occurs Ethernet coprocessor 15 the DAL bus master and the ERR L pin is asserted by external logic generally indicative of a memory problem Parity error detected on rtVAX 300 to Ethernet coprocessor CSR write or Ethernet coprocessor read from memory When Memory Error is set reception a
150. this mode with both sets enabled or both sets disabled yields unpredictable results 3 3 2 6 Memory System Error Register The memory system error register MSER IPR 39 records the occurrence of internal cache hits as well as parity errors on the DAL bus in the cache This register is unique to CVAX processor designs M SE R 6 4 1 07 are peculiar in the sense that they remain set until explicitly cleared Each bit is set on the first occurrence of the error it logs and remains set for subsequent occurrences of that error The MSER is explicitly cleared through the MTPR instruction irrespective of the write data Figure 3 13 shows the memory system error register Table 3 11 lists its fields Figure 3 13 Memory System Error Register 31 0807060504 030201 00 DIT MSER MLO 004569 3 38 Hardware Architecture 3 3 2 7 Table 3 11 Memory System Error Register Fields Data Bit Definition 31 08 lt 07 gt lt 06 gt lt 105 gt lt 04 gt lt 03 02 gt lt 01 gt lt 00 gt Unused Always read as zero Writes have no effect Hit miss HM Read only Writes have no effect Cleared on all cacheable references that hit the internal cache Set on all cacheable references that miss the internal cache Cleared on power up by the negation of RST L DAL parity error DAL Read write to dear Set whenever a DAL bus parity error is detected Cleared on power
151. to 015 to indicate a single longword transfer BM 3 0 L and CSDP 4 0 are asserted as required WR L is asserted The rtVAX 300 asserts AS validating CSDP lt 4 0 gt 1 BM 3 02 L WR L and the address information on DAL 29 02 The rtVAX 300 transfers the output data on the DAL lt 31 00 gt lines and byte parity information onto CSDP 3 02 L and CSDP 4 is deasserted The rtVAX 300 then asserts L indicate that valid parity information is available and asserts DS L to indicate that the DAL lines contain valid data Technical Specification 2 33 5 ThertVAX 300 checks for complete cycle once every two phases starting at the second possible P1 rising edge External logic indicates that the cyde is complete by one of the following three responses a If noerror occurs external logic reads the DAL line s data and asserts RDY L while ERR L is deasserted b If error occurs external logic asserts ERR L with RDY L deasserted The rtVAX 300 generates a machine check An error is recognized only if RDY L is deasserted for two consecutive P1 sample points c External logic can request a retry of the by asserting RDY L and ERR L DAL arbitration occurs after the write operation is terminated 6 ThertVAX 300 completes the cycle by deasserting DS L and AS L Notes 1 space writes always occur as single transfer write cycles 2 The Ethernet controller can issu
152. transfers are required the DMA device can reassert DMR L and go back to step 1 The deassertion of DMR L allows the rtVAX 300 to access memory between DMA requests 10 The DMA device deasserts the DMR L signal the rtVAX 300 deasserts the DMG L signal and the DMA transfer is complete The DMA timing diagram Figure 8 4 shows more details of the read and write cycles In that figure all data and strobe signals are controlled on rising edges of both CLKA and CLKB For example the AS L signal asserts on the rising edge of CLKA P1 state and deasserts on the rising edge of CLKB P2 state To emulate the proper timing of these strobe signals a state machine must be clocked on CLKA and some output latches must be clocked on CLKB See Figure 8 28 for an example of this 8 4 DMA Device Mapping Registers When I O devices or bus interface must support DMA to the rtVAX 300 system memory a scatter gather S G map is useful This map translates the DMA addresses generated by the I O device into the physical addresses of the rtVAX 300 system memor y The VAX architecture defines a page to contain 512 bytes To access any byte within any page 9 bits of addressing are required for the byte offset within a page and 21 bits are needed the page frame number to locate the page within the 30 bits of addressing accommodated by the To map the 1 0 device DMA address to the rtVAX 300 system memory correctly the S G map provides the pa
153. untestable 0 test failed 1 test passed SIDE EFFECTS None board level test 14 argument block offsets User Boot Diagnostic ROM Sample It is called D 15 offset lt scratch failing pc pc if test fails expected data address o Store expected data if actual data address of scra tch memory area address of longword to store failing f quadword that test can test fails address of quadword that test can store actual data if test fails board level test flags gt usrom share byte 300 usrom test 14 lt gt ret return to caller end D 16 User Boot Diagnostic ROM Sample flags Sample C Program to Build Setup Frame Buffer Example E 1 shows a C program to create the setup frame buffer for the hashing filtering mode Example E 1 Hash Filtering Setup Frame Buffer Creation C Program This program builds the setup frame buffer for the SGEC imperfect filtering H he addresses are read in the IEEE 802 address display format xx XX XX XX XX XX from the file specified in the in filename argument The setup frame is writen the file specified by the out filename argument If missing the setup frame is sent to the standart output Each multicast address generates hit in the hash filter The first read physical addresses is kept as the physical address f
154. up by the negation of RST L Machine check MCD DAL parity error Read write to dear Set whenever a DAL bus data parity error causes a machine check These errors generate machine checks only on demand D stream read references Cleared on power up by the negation of RST L Machine check MCC Internal cache parity error Read write to dear Set whenever an internal cache parity error in the tag or data store causes a machine check These errors generate machine checks only on demand D stream read references Cleared on power up by the negation of RST L Unused Always read as zero Writes have no effect Data parity error DAT Read write to dear Set when a parity error is detected in the data store of the internal cache Cleared on power up by the negation of RST L Tag parity error TAG Read write to dear Set when a parity error is detected in the tag store of the internal cache Cleared on power up by the negation of RST L Internal Cache Error Detection Both the tag and data arrays in the internal cache are protected by parity Each 8 bit byte of data and the 20 bit tag are stored with an associated parity bit The valid bit in the tag is not covered by parity Odd data bytes are stored with odd parity even data bytes are stored with even parity The tag is stored with odd parity The stored parity is valid only when the valid bit associated with the internal cache entry is set Tag and data parity on the entire lon
155. work in the following situations e Distributed applications that are part of a Digital computing network e Customized embedded standalone hardware e Remote data acquisition and computing platform that can be linked to use Digital data communication message protocol DDCMP serial lines e Applications that use proprietary I O buses and industry standard buses such as the VME bus the IBM e Applications that interface with industry standard LSI VLSI peripheral chips The rtVAX 300 processor is the basic hardware element that you extend to handle your application adding only the memory 1 0 devices that you need Many facets of the final system from memory and 1 0 to power and packaging are under your control When a Signetics 2681 dual universal asynchronous receiver transmitter SCN 2681 DUART serial line chip is added to its configuration the rtVAX 300 processor can support a console terminal amp BM PC AT is a registered trademark of the International Business Machines Corporation SCN is a trademark of the Signetics Corporation Overview of the rtVAX 300 Processor 1 1 1 1 Central Processor The central processor is implemented by using Digital s CVAX chip This chip contains about 180 000 transistors and supports full VAX memory management and a 4G byte virtual address space The CVAX chip contains all VAX visible general purpose registers GPRs a 1K byte instruction data cache
156. 0 gt was set Transmission process enters the suspended state and sets 58 5401 continued on next page Hardware Architecture 3 73 3 74 Table 3 35 TDESO Fields Bit Name Description 06 03 Collision Count A 4 bit counter indicating the number of collisions that occurred before the transmission attempt succeeded or failed Meaningless when TDESO lt 08 gt is also set 07 HF Heartbeat Fail When set indicates Heartbeat Collision Check failure the transceiver failed to return a collision pulse as a check after the transmission Some transceivers do not generate heartbeat and so will always have this bit set If the transceiver does support it it indicates transceiver failure Meaningless if 50 lt 01 gt is set 08 EC Excessive Collisions When set indicates that the transmission was aborted because 16 successive collisions occurred while attempting to transmit the current frame 09 LC Late Collision When set indicates frame transmission was aborted due to a late collision Meaningless if TDESO lt 01 gt is set 10 NC No Carrier When set indicates the carrier signal from the transceiver was not present during transmission possible problem in the transceiver or transceiver cable Meaningless in internal loopback mode CSR5 lt 18 17 gt 1 11 LO Loss of Carrier When set indicates loss of carrier during transmission possible short circuit in the Ethernet cable Meaningless in
157. 0 gt 1 BM lt 3 0 gt L WR L and address information on DAL 31 02 4 DSL is asserted for each data transfer to indicate that the DAL lines are available to receive the incoming data 5 The CVAX checks for a complete once every after each longword cyde starting at the next possible P1 rising edge External logic indicates that the is complete by one of the following three responses a If no error occurs external logic places the requested data on the DAL lt 31 00 gt lines and parity information on CSDP lt 3 0 gt L asserts DPE L if parity is to be checked asserts CCTL L if data caching is to be disabled and asserts RDY L while ERR L is deasserted for each data transfer The CVAX reads the data and parity information and deasserts DS for every transfer If the caching is prevented CCTL asserted the cycle immediately terminates without reading the second longword If the CVAX detects a parity error the appropriate error information is logged in the MSER the CVAX ignores the data on the DAL 31 00 lines and generates a machine check if the cycle was a demand read If a parity error is detected on the first longword the CVAX performs the second data transfer and ignores all the data b If an error occurs on either longword external logic asserts ERR L with RDY L deasserted The CVAX ignores the data on the DAL 31 00 lines terminates the cycle without reading any addi
158. 0000000000000 lt 123 120 gt PHYSICAL ADDRESS 15 L 127324 The low order bit of the low order byte is the address s multicast bit Example 3 1 illustrates a Perfect Filtering Setup buffer fragment 3 82 Hardware Architecture Example 3 1 Perfect Filtering Buffer Ethernet addresses to be filtered 8 09 65 12 34 76 09 BC 87 DE 03 15 Setup frame buffer fragment 126509A8 00007634 DE87BC09 00001503 Q Ethernet multicast addresses written according to the IEEE 802 spedification for address display Thosetwo addresses as they would appear in the buffer 3 6 2 3 5 Imperfect Filtering Setup Frame Buffer This section describes how the Ethernet coprocessor interprets a setup frame buffer when SDES1 lt 25 gt is set The Ethernet coprocessor can store 512 bits serving as hash bucket heads and one physical 48 bit Ethernet address Incoming frames with multicast destination addresses are subjected to the imperfect filtering Frames with physical destination addresses are checked against the single physical address For any incoming frame with a multicast destination address the Ethernet coprocessor applies the standard Ethernet CRC function to the first six bytes containing the destination address and then uses the least significant nine bits of the result as a bit index into the table If the indexed bit is set the frame is accepted if it is deared the f
159. 1 LI 171 lt gt 1 lt 91 gt 7 4 lt 0 gt WYH i VH lt lt gt lt gt lt gt VH lt 9 gt WYH Z NvH T AQUIN lt 8 gt WYH lt 6 gt lt 01 gt lt gt lt gt lt H lt t gt lt gt 31IHMHSINId QV3HHSINId LOADGWAY SOADALIYM LOADALINM 7AQv3uol VIVINOO8N3 H lt 0 16 gt 1 E AA o 28 zd AA T 28 18 2 14 64 id bd Zd bd bd Ed 14 Ed 14 bd d Zd id Ed 14 bd Ed id bd 14 Ed id vd id 6 00 lt 0 gt lt gt lt gt lt 6 gt 1 4 lt p gt vd lt 9 gt 7 lt
160. 10 The internal cycles start off as regular read write cycles However by the end of the address portion of the cyde all data lines are undefined The beginning of an internal cycle is indicated by an address within the reserved space or the assertion of CSDP 4 The end of the is indicated by the deassertion of AS L See Figure 2 15 DMA Cycle The rtVAX 300 can relinquish the DAL lines and related control signals upon request from an external DMA device or other processor The sequence is as follows 1 The external device requests control of the bus by asserting DMR L 2 Once the rtVAX 300 finishes the current bus cycle and no pending DMA requests are present from the Ethernet coprocessor the rtVAX 300 causes the DAL lt 31 00 gt H lines AS L DS L WR L BM lt 3 0 gt L and CSDP lt 4 0 gt L to become high impedance and asserts DMG L DAL bus arbitration occurs at the end of each bus so that devices can intervene between bus retry cycles Technical Specification 2 41 Figure 2 15 Internal Read or Write Cycle CLKA CLKB DAL P1 P3 P1 P3 P1 P3 P1 P3 MLO 004402 3 Toreturn bus control to the rtVAX 300 the external device deasserts DMR L and the rtVAX 300 responds by deasserting DMG L and returning to regular bus cydes The rtVAX 300 does not invalidate cache entries unless the CCTL L line is asserted appropriately Figure 2 16 illustrates timing
161. 10 SDEFINE ILLEGAL4_ B 110 You now define equations to ease the state transition conditions Memory access can start only if SYNCHAS and SELRAM are asserted and if and REFREQ are not asserted to give refresh priority over memory access and to prevent memory access during an rtVAX 300 interrupt acknowledge EQU 1 through 4 determine when multiple longword transfer cydes complete by looking at the cycle type LADDR 31 30 and the address of the last longword INVADDR 3 2 that was transferred MEMACCESS SYNCHAS amp SELRAM amp IACKIPR EQUI LADDR31 LADDR30 amp FINVADDR2_ amp FINVADDR3 END LONGWORD XFR EQU2 LADDR31 LADDR30 amp FINVADDR2 amp FINVADDR3 END QUADWORD XFR EQU3 LADDR31 LADDR30 amp FINVADDR2_ amp FINVADDR3 END HEXWORD XFR EQU4 LADDR31 LADDR30 amp FINVADDR2 amp FINVADDR3 END OCTAWORD XFR Memory System Interface 5 45 The state machine listing is as follows SEQUENCE MEMORY PRESENT IDLE IF REFREQ RST NEXT STARTREFRESH OUT REFCYC OUT ENBCAS IF MEMACCESS amp REFREQ RST NEXT STARTACCESS OUT RAS DEFAULT NEXT IDLE OUT REFCYC OUT RAS OUT ENBCAS OUT INVADDR2_ OUT INVADDR3_ OUT DRAMREADY OUT FLAG PRESENT STARTACCESS IF MEMACCESS amp DS NEXT ACCESSCYC OUT ENBCAS IF MEMACCESS NEXT ENDREFRESH DEFAULT NEXT STARTACCESS PRESENT ACCE
162. 11 delay DRAM column address hold time In this case DRAM column address hold time 250 ns 12 ns 2 5 ns 5 ns 0 ns 2 ns 5 ns 30 ns Memory Subsystem Octaword Write Cycle Timing Like the access time for read cydes DRAMs also have setup and hold times that must be met for write cycles The data on the DALs is strobed into the DRAMs on the falling edge of CAS The rtVAX 300 can write up to four longwords one access cycle Refer to Figure 5 7 for the octaword write sample timing All multiple word write cycles slip one microcycle for each longword transferred This was necessary to satisfy the data in setup and hold times Calculating Data In Setup Time The Data In setup and hold timing must be calculated to ensure that valid data is strobed into the DRAMs The DALs are driven with valid data 23 ns 2P 27 before the rising edge of P1 The DRAMs CAS line is driven 17 ns after the rising edge of P1 thus the worst case DRAM data in setup time is calculated as follows 2 74F 00 minimum propagation delay 23 5 0 ns state machine minimum propagation delay Data in setup time this case data in setup time 23 ns 4 ns 0 ns 27 ns Calculating Data In Hold Time The rtVAX 300 continues to drive the DAL bus with valid data until P 6 31 ns after the rising edge of the following P1 Thus the minimum data in hold timing can be calculated as follows 2 74F 00 maximum propagation de
163. 11010 SDEFINE ILLEGAL2 B 11011 SDEFINE ILLEGAL3 B 11100 SDEFINE ILLEGALA B 11101 SDEFINE ILLEGAL5 B 11110 SDEFINE ILLEGAL6 B 11111 SDEFINE ILLEGAL7 B 10000 You set access and cyde information as follows WRITEACCESS LWRITE amp 0 amp amp SYNCHAS READACCESS LWRITE amp LBMO amp CONE SYNCHAS ROMACCESS LWRITE amp ENBROM amp SYNCHAS IACKCYCLE CONIACK CPUST amp SYNCHAS You force the idle state during power up and reset assertion as follows Console and Boot ROM Interface 6 31 ENBCONDATA AR RST ENBCONDATA SP B 0 IOREADY AR RST IOREADY SP B 0 STATEA AR RST STATEA SP B 0 STATEB AR RST STATEB SP B 0 STATEC AR RST STATEC SP B 0 STATED AR RST STATED SP B 0 STATEE AR RST STATEE SP B 0 The state machine listing is as follows SEQUENCE CONSOLE PRESENT IDLE IF WRITEACCESS NEXT WRITECYC1 OUT ENBCONDATA IF READACCESS NEXT READCYC1 OUT ENBCONDATA IF IACKCYCLE NEXT IF ROMACCESS NEXT ROMCYCI DEFAULT NEXT IDLE PRESENT WRITECYC1 NEXT WRITECYC2 OUT ENBCONDATA PRESENT WRITECYC2 NEXT WRITECYC3 OUT ENBCONDATA PRESENT WRITECYC3 NEXT WRITECYC4 OUT ENBCONDATA PRESENT WRITECYC4 NEXT WRITECYC5 OUT ENBCONDATA PRESENT WRITECYC5 IF P4 NEXT FINISHWRITE OUT ENBCONDATA OUT IOREADY DEFAULT NEXT WRITECYC5 OUT ENBCONDATA PRESENT FINISHWRITE NEXT FINISHUP1 PRESENT READCYC1 NEXT READCYC2 OUT
164. 2 3 state output off state current 0 5 pA Active supply current 2000 mA Physical Electrical and Environmental Characteristics 7 Table A 3 AC Characteristics Number gt Description Minimum Maximum Units 1 tasp Address strobe assertion delay 0 23 5 2 DALD DAL address setup 2p 27 2p ns WR assertion delay 3 DAL address hold p 6 ns 4 DALZ DAL address to high impedance 25 5 state 5 tam Byte mask setup 9 p ns 6 tpsp DS strobe assertion delay 2p 2p427 ns 7 tps DAL data setup 28 ns 8 DAL data hold 5 ns 9 DAL data to high impedance state 40 ns 10 Parity setup 26 ns 1 isws RDY and ERR sample window setup 23 ns 12 tswH RDY and ERR sample window hold 5 45 ns 13 tpsip DS strobe deassertion delay 0 25 ns 14 tasip AS strobe deassertion delay p 28 5 15 DAL undefined delay 28 51 5 16 2 5 17 WR hold p ns 18 DPE setup 10 p ns 19 DPEH DPE hold time p ns 20 DMG assertion delay 0 43 ns 21 sHLZ Strobe high impedance delay 0 27 ns 22 DS delay after DMG 6p ns 23 DAL high impedance delay 42 ns 24 tsyns Asynchronous input setup 23 5 25 isyNH Asynchronous input hold 23 ns 26 tasapru DAL hold during cache invalidate 20 ns 27 time during octaword 5 invalidate continued on next page A 8 Physical E
165. 2 Interrupt priority level IPL r w 11 19 13 AST level ASTLVL 11 20 14 Software interrupt request SIRR w 1 21 15 Software interrupt summary SISR r w 11 23 22 17 16 Reserved 3 24 18 Interval dock control status 5 r w 21 25 19 Next interval count NICR w 3 26 1A Interval count ICR 3 27 1B Time of year clock register TODR r w 3 28 1C Console storage receiver status CSRS r w 51 29 1D Console storage receiver data CSRD r 51 30 1E Console storage transmit CSTS status register initialized on power up and by negation of RST when the processor is halted 3 8 Hardware Architecture continued on next page Table 3 3 Cont Internal Processor Registers Decimal Hex Register Mnemonic Type Category 31 Console storage transmit data CSTD w 51 32 20 Console receiver control status RXCS r w 3 33 21 Console receiver data buffer RXDB r 3 34 22 Console transmit control status 5 r w 3 35 23 Console transmit data buffer TXDB w 3 36 24 Translation buffer disable TBDR r w 3 37 25 Cache disable CADR r w 21 38 26 Machine check error summary MCESR r w 3 39 27 M emory system error MSER 21 41 40 29 28 Reserved 3 42 2A Console saved PC SAVPC r 2 43 2B Console saved PSL SAVPSL r 2 47 44 2F 2C Reserved 3 48 30 SBI Fault status SBIFS r w 3 49 31 SBI silo SBIS r 3 50 32 SBI silo comparator SBISC r w 3 51 33 SBI maintenance SBIMT 3 52 34 SBI error SBIER r w 3 53 35 SBI timeout address SBITA r 3 54 36
166. 21 Memory 1 0 5 2 21 Address Decode and Boot ROM 2 23 Boot ROM ug Pec LR 2 23 Programming the User ROMs 2 24 Network Interface Registers 2 24 Board L evel Initialization and Diagnostic 5 2 24 Bus Cycles and 5 2 25 Microcyde Definition 2 25 Single Transfer Read Cyde 2 25 Quadword Transfer Read Cycle 2 27 Octaword Transfer Read 2 30 Single Transfer Write 2 33 Octaword Transfer Write Cycle 2 35 Interrupt 2 36 External IPR 5 2 38 External IPR Read Cyde 2 38 External IPR Write 2 40 internal Gee Rue Ree E eR adil ES 2 41 DMA GVCOG corte May me ae 2 41 Cache Invalidate 2 43 3 Hardware Architecture 31 3 1 1 3 1 2 3 1 3 3 1 4 3 1 4 1 3 1 4 2 3 1 4 3 3 1 5 3 1 6 3 1 7 Central PErOCessOr dog cage 3 2 Data iR Re Eur tem Re ncn 3 2 In
167. 27 7013 O Digital Equipment Corporation 1990 1991 rights reserved Printed in U S A The following are trademarks of Digital Equipment Corporation DDCMP DEC DECnet DECnet VAX DECwindows DELUA DEQNA DEUNA DSSI IVAX MicroVAX PDP Q22 bus RQDX RQDX rtVAX 300 ThinWire VAX VAXcluster VAX DOCUMENT VAXELN VMS and the DIGITAL Logo IBM PC AT is a registered trademark of the International Business Machines Corporation PROMLINK is a registered trademark of the DATA 1 Corporation 51537 This document was prepared with DOCUMENT Version 1 2 Contents Preface o xix 1 Overview of the rtVAX 300 Processor 1 1 Central 550 1 2 1 2 Floating Point Accelerator 1 2 1 3 Ethernet 550 1 3 1 4 System Support 5 1 3 1 5 Resident Firmware 1 3 2 Technical Specification 2 1 Functional 2 1 2 1 1 Architecture 2 2 2 1 2 CPU and 2 5 ses ees nds 2 2 2 1 3 ROM and Reserved Memory Locations 2 2 2 1 4 Network Interface 2 2 2 1 5 Decode and Control 2 4 2 1 6 Interrupt Structure ee
168. 300 processor Figure 3 17 shows a block diagram of this function This section provides an overview of the following Control status registers Section 3 6 1 Descriptors and buffers format Section 3 6 2 Operation Section 3 6 3 Serial interface Section 3 6 4 Diagnostics and testing Section 3 6 5 3 46 Hardware Architecture Figure 3 17 Ethernet Coprocessor Block Diagram DAL lt 31 00 gt RX AS Receive 05 Machine RCLK BM TEST lt 3 0 gt WR CCTL RDY ERR CSDP 30 Bus Interface Unit Receive FIFO Transmit RXEN DMR FIFO Transmit TCLK Machine IRQ TXEN 16 D CSL Internal IOP Bus THEG To All Blocks BIREQ ROM RAM TSM CLKA Clocks CLKB RESET MLO 004415 3 6 1 Control Status Registers The Ethernet coprocessor contains 16 CSRs found at locations 20008000 through 200080 that are used to control its operation The CSRs are located the I O address space The register addresses must be longword aligned and can be accessed only by using longword instructions The CSRs are divided into two groups physical CSRs and virtual CSRs The assigned locations for the registers are defined in Table 3 17 You program the Ethernet interface by reading and writing to these registers The network ID ROM provides the physical network address for the rtVAX 300 at 20008040 to 200080BF The physical CSRs are CSRO through CSR7 and 5 15 These registers
169. 300 Processor Interface Block Diagram Device Interfacing Device Interfacing Device Interfacing I O Device Interfacing Device Interfacing HALT Logic DMA State Machine Sequence DMA Write Cycle Timing Reset Timer Address Decoder and Power On M peter avid 1 Device Interfacing I O Device Interfacing 1 Device Interfacing I O Device Interfacing I O Device Interfacing Device Interfacing 1 Device Interfacing Device Interfacing Address Latches DRAM Address Path Memory Controller DRAM Memory Array 1 DRAM Memory Array 2 RAM Data Latches Console Interface User Boot ROM Bank 1 with Drivers 1 Device Interfacing 1 Device Interfacing I O Device Interfacing Device Interfacing Generator I O Device Interfacing User Boot ROM Bank 2 DSP and Private RAM DSP PGM Loader ROM DSP DMA Transceiver and Parity 7 10 7 13 7 17 7 18 8 2 8 3 8 6 8 10 8 12 8 14 8 16 8 20 8 22 8 25 8 26 8 28 8 29 8 30 8 31 8 33 8 34 8 35 8 37 8 39 8 41 8 43 8 45 8 47 8 49 8 26 Device Interfacing VAX to DSP 1 Way Mirror Registon AD Wan ste Ae 8 51 8 27 Device Interfacing rtVAX 300 DSP CSR 8 53 8 28 Device Inte
170. 300 and the memory system This time is less than the 53 ns maximum time required by the rtVAX 300 If the turnoff time for any peripheral is greater than 53 ns transceivers are needed to isolate that peripheral from the DAL bus after the peripheral has been accessed 5 11 Memory System Illustrations and Programmable Array Logic The following sections show memory system illustrations and programmable array logic Figure 5 9 shows the design sample for the address decoder and power on reset Figure 5 10 shows the RAM memory map Figure 5 11 shows the design sample for the address latches Figure 5 12 shows the design sample for the memory controller Figure 5 13 shows the design sample for DRAM memory array 1 Figure 5 14 shows the design sample for DRAM memory array 2 Figure 5 15 shows the design sample for the RAM data latches 5 11 1 Application Module Address Decoder PAL Table 5 9 lists the programmable array logic PAL that decodes the rtVAX 300 address and cycle status lines This PAL does the following e Selects the memory and decodes rtVAX 300 interrupt acknowledge cycles e Asserts the SELRAM IACKIPR and ENBCCTLDPE lines which control the data parity enable and cache control drivers select system RAM and signal when the rtVAX 300 is running an interrupt acknowledge IPR cyde The SELRAM and IACKIPR select lines are internally latched the rising edge of AS H This PAL eliminates the need for external
171. 31 30 gt lines set to 01 to indicate a single longword transfer 2 The BM 3 05 L and CSDP 4 0 L lines are asserted as required and the WR L line is negated 3 The CVAX asserts AS L validating CSDP L BM L WR L and address information 2 26 Technical Specification 4 The CVAX asserts DS L to indicate that the DAL lines are available to receive the incoming data 5 The CVAX checks for a complete cycle once every two phases starting at the next possible P1 rising edge External logic indicates that the cycle is complete by one of the following three responses a If no error occurs external logic places the requested data on the DAL 31 007 lines and parity information on CSDP 43 02 L asserts DPE L if parity is to be checked and asserts RDY L while ERR L is deasserted If the CVAX detects a parity error appropriate error information is logged in the memory system error register MSER the CVAX ignores the data on the DAL lt 31 00 gt lines and generates a machine check if the cycle was a demand read b If a bus error occurs external logic asserts ERR L with RDY L deasserted The CVAX ignores the data on the DAL lt 31 00 gt lines and generates a machine check if the cyde was a demand read cyde An error is recognized only if RDY L is deasserted for two consecutive P1 sample points External logic can request a retry of the cycle by asserting RDY L and ERR L Certain request read cy
172. 4 0r2Haav1i H lt 8 gt 02 uaavi lt 6 gt lt gt H lt gt 14374 2 9 LL XNW 127HQQV1 tY00 OTN _ 5 OAOQV3H OA9HS3H43H OAOSS3ODV 040553007 04085400 OAO0SS3OOV OAOSS3OOV lt 0 8 gt HQQVANI HQQVANI lt 0 6 gt 5 0 1 11092135 1SvH i Y 18 lt 0 1 gt 71 H d Id itd Edi d 1 vd H Zd 14 d 14 d 14 Zd 14 d Zd 14 vd Ed 14 td Ed Zd 14 Ed Zd 14 vd Ed Zd bd vd Ed Zd 14 vd Ed Zd Id 11 lt 0 1 gt GALYASSV LON SI 3 1IHM C1 10 9AO3IIHM IOAO3IIHM EOADALINM__ LOADALINM EOADALINM _ LOAOSLIHM SSHOOVIHVIS 088300 55 OA9S
173. 4 245 turn off time Turn off time In this case turn off time 25 ns 5 ns 5 ns 35 ns after edge Note The time required to deactivate memory and peripheral devices must be considered in the application design to prevent bus contention conflicts 6 1 4 3 Console Read Cycle Timing Analysis Since the read access time of the DUART is 175 ns two wait states are needed to satisfy the rtVAX 300 read timing These wait states are added by delaying the assertion of the rtVAX 300 RDY L signal During a console read cycle the console state machine asserts the ENBCONDATA signal which enables the ENBCONRD to the DUART and the ENBCONDAL signal is asserted when DS asserts The assertion of ENBCONDAL and ENBCONRD turns on the bus transceivers and asserts the RD input of the DUART The console controller state machine waits 200 ns and then asserts the IOREADY signal within the rtVAX 300 RDY L window adding two wait states The console controller completes the console read by deasserting ENBCONDATA and I OREADY for 150 ns and then waits for another console access to begin Console and Boot ROM Interface 6 9 Console read access time is calculated as follows 5 x CLKA period rtVAX 300 data setup time CLKA edge to ENBCONDATA assertion 74F 00 propagation delay 74F 245 propagation delay Access time from RD In this case access time from 5 x 50 ns 28 ns 12 ns 5
174. 4 2 DAL bus parity errors 04 Internal cache parity errors 04 2 ERR L asserted without RDY L 04 DAL bus timeout errors 1Dispatched by resident firmware rather than through the SCB Handled through machine check 3 1 12 4 Information Saved on a Machine Check Exception response to a machine check exception the PSL PC four parameters and a byte count are pushed onto the stack as shown in Figure 3 4 Hardware Architecture 3 19 Figure 3 4 Information Saved on a Machine Check Exception Internal State Information 2 MLO 004408 Byte Count Byte count 31 00 indicates the number of bytes of information that follow on the stack excluding the PC and PSL Machine Check Code Parameter Machine check code 31 00 indicates the type of machine check that occurred Possible machine check codes and their associated causes follow e Floating point errors indicate that the floating point accelerator CF PA chip detected an error while communicating with the CVAX processor chip during the execution of a floating point instruction The most likely causes of these types of machine checks a problem internal to the CVAX processor chip a problem internal to the CFPA or a problem with the interconnect between the two chips Machine checks due to floating point errors may be recoverable depending on the state of the VAX cant restart flag captured in internal state information 2 lt 15 gt and the first
175. 5 3 80 Hardware Architecture SE ES OW HP Setup Error When set indicates the setup frame buffer size in not 128 bytes Error Summary Set when bit 13 is set Own bit When set indicates that the descriptor is owned by the Ethernet coprocessor When cleared indicates that the descriptor is owned by the rtVAX 300 The Ethernet coprocessor clears this bit upon completing processing of the descriptor and its associated buffer Interrupt on Completion When set the Ethernet coprocessor sets 5 5 lt 01 gt after this setup frame has been processed Hash Perfect filtering mode When set the Ethernet coprocessor interprets the setup frame as a hash table and does imperfect address filtering The imperfect mode is useful when there are more than 16 multicast addresses to listen to When clear the Ethernet coprocessor does a perfect address filter of incoming frames according to the addresses specified in the setup frame continued on next page Table 3 40 Cont Setup Frame Descriptor Bits Word Bit Name Description 26 IF Inverse filtering When set the Ethernet coprocessor does inverse filtering the Ethernet coprocessor receives incoming frames with destination address not matching the perfect addresses and rejects frames with destination address matching one of the perfect addresses Meaningful only for Perfect filtering 50 51 lt 25 gt 0 while Promiscuous and Multicast modes are not s
176. 5 D3 C7 6B 46 0A 55 2D 7E as 12 34 35 76 08 Setup frame buffer 00000000 35341248 00000876 Ethernet multicast addresses written according to the IEEE 802 spedification for address display An Ethernet physical address The first part of an Imperfect Filter Setup frame buffer with set bits for the multicast addresses The second part of the buffer with the physical address 3 6 3 Operation A program in rtVAX 300 memory called the port driver controls the operati on of the Ethernet coprocessor The Ethernet coprocessor and the port driver communicate through two data structures Command and Status Registers CSRs These registers are located in the Ethernet coprocessor and mapped in the rtVAX 300 5 address Hardware Architecture 3 85 space The CSRs are used for initialization global pointers command transfer and global error reporting Descriptor Lists and Data Buffers These are collectively called the host communication area and are located in rtVAX 300 memory These lists and buffers handle the actions and status reporting related to buffer management The Ethernet coprocessor can be viewed as two independent concurrently executing processes reception and transmission These processes are started after the Ethernet coprocessor completes its initialization sequence Once started these processes alternate between three sta
177. 8 19 20 21 22 23 STATEA STATEB STATEC STATED STATEE ENBCONDATA This output asserts the rtVAX 300 READY line to signal that valid data is on the DAL lines and the cyde should end This output correlates to a state bit for this machine This output correlates to a state bit for this machine This output correlates to a state bit for this machine This output correlates to a state bit for this machine This output correlates to a state bit for this machine The assertion of this signal enables a DUART read or write cycle You define a state name for each bit pattern as follows FIELD CONSOLE STATEE STATED STATEC STATEB STATEA 6 30 Console and Boot ROM Interface SDEFINE IDLE 00000 E SDEFINE WRITECYCI B 00001 SDEFINE WRITECYC2 B 00010 SDEFINE WRITECYC3 B 00011 SDEFINE WRITECYC4 B 00100 SDEFINE WRITECYC5 B 00101 SDEFINE FINISHWRITE B 00110 SDEFINE READCYC1 B 10001 SDEFINE READCYC2 B 10010 SDEFINE READCYC3 B 10011 SDEFINE READCYCA B 10100 SDEFINE FINISHREAD B 10101 SDEFINE FINISHUP1 B 10110 SDEFINE FINISHUP2 B 10111 SDEFINE FINISHUP3 B 11000 SDEFINE IOCYCl 00111 SDEFINE IOCYC2 01000 SDEFINE FINISHIO B 01001 SDEFINE ROMCYC1 01010 SDEFINE ROMCYC2 01011 SDEFINE ROMCYC3 01100 SDEFINE ROMCYC4 01101 SDEFINE ROMCYC5 01110 SDEFINE 6 01111 SDEFINE FINISHROM B 11001 SDEFINE ILLEGAL1 B
178. 802 3 grounding specification All cables shipped by Digital Equipment Corporation comply with the IEEE 802 3 ground design requirements 7 6 3 5 Isolation Boundary An isolation boundary must exist between the coaxial cable medium and the circuitry within the station This boundary has two characteristics e t presents a high impedance to low frequency signals This is required in order to limit currents in ground loops These ground loops are set up by multiple stations connecting to their local earth grounds and to the coaxial cable ground that is the network media The impedance between either coaxial cable conductor center conductor or shield and any of the conductors in the AUI must be at least 250 at 60 Hz e t presents a low impedance to high frequency signals This creates a low impedance path for noise to be shunted to earth ground The magnitude of the impedance between the shield of the coaxial cable and the protective ground of the AUI must be at most 15 2 in the frequency range of 3 MHz to 30 MHz This isolation boundary is implemented within the MAU When a station has only an AUI connector the design need not implement these isolation requirements because they are implemented in the external MAU The isolation boundary must be implemented in internal MAUs and is provided by the isolation transformer between the SIA and the MAU The requirement for a high impedance at 60 Hz is met by the use of two blocks a DC to
179. 81 DUART device is initialized and the console port Channel A is initialized to 9600 bps no parity 8 bits character and 1 stop bit The secondary serial line Channel B is not initialized at this time e No check is made to determine whether a device is on the other end of the cable Capabilities of Console Terminals Console terminals for the 300 must support at least USASCII graphic character encoding The terminal may optionally support the DEC Multinational Character Set which is a superset of USASCII National replacement character sets are not supported Characters normally transmitted by the Console program are the USASCII graphic characters 2116 through 7E 16 the space character 2016 and control characters 0016 CR LF and 0816 BS a backspace character 4 3 11 Console Entry and Exit The system firmware must do several things when it enters and exits from console mode to ensure that the console window is displayed correctly Attached Terminals When present the attached terminal on serial port Channel A is expected to be operable at all times The console support firmware does not attempt to alter the state of these terminals or the serial port through which they are connected At entry to the console mode firmware calls the operating system s SAVE routine SCR A SAVE CONSOLE if supplied and the console prompt is displayed at exit firmware calls the operating system s RESTORE routine SC
180. 8392 transceiver chip must be connected directly to the coaxial BNC connector by an etch run of less than 4 cm The 15 pin D sub connector is the AUI interface to an external MAU if one is employed Note that either the direct ThinWire connect or the external MAU can be employed never both W8 is the Heartbeat enable jumper for the DP8392 chip and W9 is the Ethernet IEEE 802 3 isolation jumper W9 should be installed for standard product shipment Note The isolation transformer is not shown in Figure 7 5 Network Interconnect Interface 7 9 Figure 7 5 Network Interconnect Transceiver Connector and Connector J1 ay COAX Wa R11 1624 222 R16 TRANZORB 499 1 499 1 499 1 499 b6 A RX gy R20 1M Gor 0664 4700 1000V XMIT XMIT 777 R13 2 R12 40 2 7 40 2 F1 12V OND c15 R19 2A RCV 1UF XMIT COLL Notes The shell of the D Sub connector J2 to be attached to chassis ground AUI RCV e The etch for ground B and 12V to J2 must be capable of handling a current of 5A e Ground B to be connected to logic ground at the power supply only COLL e Pins 4 5 and 13 of E4 to be connected to the VEE plane with a surface area gt 1 sq in for heat dissipat
181. 9 51 EZT E o 0 1 dNO50 IVNV dd 1 5 D5 34 eM 001 098 499 T 20ADQTVNV ASZ 968 231 3001 2 13533 02 189 100 1 1 Kez H ARE rev AOL H ZNIOIIN 694 92 6013 2 d 806 1 AS 09S 54 ixsi vi XS Ast 1 LHS 1 HOHOLIHS OL E 969 W oL H LINO 92 19 HISVIN 9 0S n lt sdozz sug 4 SE v e bo a a M voe 8 316 S T 1 2 2 8 9 3995 M 075 T 0260 1 v 29 DIET 9 5 JequinN euoudojolN 8013 508 1 228900 01 1
182. 919 lt gt 2 S0S i 6 zu 0 lt 7 INIXVASN3 z9 ou Aa H T 93 H 9018 e vivddsda 5 H 5 Suo ims H 8 5 022 H 58 74 164 4 Le L LE 001H 0L a a no Lu ozz ET lt gt L L lt p gt SI 9 H SS vi H lt 905 Ti g EH do dr 2 693 snieis OML 26297 487 dold 8 H HSOXVAHOLVI Jeziuoyjou AS Sda 1258 XVAI3S3H 8 d H lt e gt H 13534938 E al 5 a9 09 1 6j 45013599 NE C H 1745019599 19 ou 023 erg 1 8 905 H pen 1 48013638 058 7 3 6r 9 v vOd lt 693 693 17019450 72 ar 014 ag doi 5 293 al al de H lt gt Jeziuougou S dsa 1ejsibeu YSI 5 167700 1
183. A base address register The rtVAX 300 can now reset these 2 bits and the DSP copies the program to its own private memory and begins to execute it The base address register see Figure 8 27 drives through the bus drivers see Figure 8 26 to the rtVAX 300 DAL bus The DSP cannot read any of these bits however it can write to the interrupt VAX bit as described above When set the interrupt bit for the rtVAX 300 requests an interrupt by asserting lt 2 gt When the rtVAX 300 runs an interrupt acknowledge this request is deared however the bit in the CSR remains set When this register is read this bit is cleared at the end of the read cyde The interrupt bit for the DSP operates in the same manner however it asserts the DSPIR lt gt bit This bit is cleared when the DSP runs an interrupt acknowledge cycle 8 5 6 DMA Base Address Register The rtVAX 300 can perform DMA to up to 64K bytes of memory The DMA base address register selects the 64K byte block of memory which can be seen by the DSP The DSP CSR whose implementation is shown in Figure 8 25 is readable and writeable only from the rtVAX 300 and cannot be accessed by the DSP 8 6 Reset Power Up The rtVAX 300 processor must have its RST L line asserted for at least 750 ns when it is first powered up to ensure the stability of all on chip voltages before beginning operation Assertion of this line resets all rtVAX 300 internal registers and sets the progra
184. AL2 DAL line 2 from the rtVAX 300 contains information about the IPL of the rtVAX 300 By decoding the DAL and CSDP lines this PAL can determine when the rtVAX 300 is running a console interrupt acknowledge cycle continued on next page Console and Boot ROM Interface Table 6 6 Interrupt Decoder Pin Setting Comment Input Signals 9 DAL3 DAL line 3 from the rtVAX 300 contains information about the IPL of the rtVAX 300 By decoding the DAL and CSDP lines this PAL can determine when the rtVAX 300 is running a console interrupt acknowledge cycle 10 DAL4 DAL line 4 contains information about the IPL of the rtVAX 300 By decoding the DAL and CSDP lines this PAL determines when the rtVAX 300 is running a console interrupt acknowledge cycle 11 DAL5 DAL line 5 contains information about the IPL of the rtVAX 300 By decoding the DAL and CSDP lines this PAL can determine when the rtVAX 300 is running a console interrupt acknowledge cycle 13 DAL6 DAL line 6 contains information about the IPL of the rtVAX 300 By decoding the DAL and CSDP lines this PAL determines when the rtVAX 300 is running a console interrupt acknowledge cycle 14 DAL7 DAL line 7 is used as one of the console address decoder inputs 15 DAL8 DAL line 8 is used as one of the console address decoder inputs 16 DAL9 DAL line 9 is used as one of the console address decoder inputs 17 DAL 10 DAL line 10 is used as one of the console address decoder inpu
185. AX 300 supplies 78 2 termination on these lines Chapter 7 discusses this connection in greater detail e Receive RCV RCV non TTL This differential pair of wires connects through a user supplied isolation transformer to a user supplied 15 pin D sub connector when the rtVAX 300 processor is connected to a media attachement unit MAU with a transceiver cable The rtVAX 300 supplies 78 2 termination on these lines See Figure 2 5 2 12 Technical Specification Transmit XMT non TTL This differential pair of wires connects through a user supplied isolation transformer to a user supplied 15 pin D sub connector when the rtVAX 300 processor is connected to a media attachement unti MAU with a transceiver cable See Figure 2 5 Figure 2 5 Thickwire Connections 8 Chassis GND 15 Not Connected 0 14 Chassis GND O 13 12V Source 12 RCV 7 Not Connected 6 Reference GND 5 RCV 4 Chassis GND 11 Chassis GND 3 XMT d 10 2 COL 9 COL 1 Chassis GND 15 Pin D Sub Female View MLO 004391 Technical Specification 2 13 2 4 3 Bus Control Signals Bus control signals are as follows Address Strobe AS L O Z This signal indicates that valid address information is available on the DAL lt 29 02 gt bus and valid status information is on the BM 3 02 CSDP lt 4 0 gt L and WR L lines The leading edge of this signal be used to lat
186. BROM and AS signals are asserted The state machine then counts seven CLKA ticks and asserts the IOREADY signal which in turn asserts the RDY L line of the rtVAX 300 Additional wait states can easily be added for slower ROMs by Console and Boot ROM Interface 6 17 increasing the number of counts states needed before the assertion of the RDY L line 6 2 7 ROM Turn Off Time The rtVAX 300 uses ROMs that have a data turn off time of 60 ns This time exceeds the 35 ns specified by the rtVAX 300 processor Data drivers are added between the ROM data outputs and the DAL bus to stop driving the DAL bus after DS L deasserts to prevent bus contention The calculation of ROM turn off time is as follows DS deassertion delay 74F 20 propagation delay 74F 244 turn off time ROM turn off time from CLKA to P1 edge In this case ROM turn off time from CLKA to P1 edge 227 ns 5 ns 6 ns 38 ns To determine if drivers are needed add the DS assertion delay to the ROM CS select delay and subtract the total from 35 ns The resulting value is the maximum turn off delay that can be tolerated without the addition of drivers In this example the maximum turn off delay of the ROMs was as follows Sample maximum turn off delay 35 ns 28 ns 5 ns 12 ns If the ROMs take longer than 12 ns from CS deassertion to HI Z a set of drivers must be added between the ROMs data bus and the DAL bus to prevent bus contentio
187. Base Address of External ROM The external user ROM s base address first and lowest physical location may be at 20200000 or 10000000 To boot from this ROM you must connect the BOOT 3 0 pins as shown in Table 3 12 When the rtVAX 300 finishes initializing after a reset operation it begins to copy the VAXELN system image from the ROMs to its external system RAM or runs out of the ROMs The rtVAX 300 does not send the MOP requests over the network instead the rtVAX 300 boots from the ROMs Table 3 12 lists boot options 6 2 2 Programming the Boot ROMs The system file generated by EBUILD must first be down line loaded to the rtVAX 300 target by means of the network as the booting device You can then use the remote and local debuggers to debug the application software Once the application software is running correctly EBUILD should be used to generate a new system file selecting the ROM as the boot method The resulting SYS file should then be run through the DATA 1 0 PROMLINK program for example which creates a loadable file for the EPROM programmer The programmed ROMs are then inserted into the EPROM programmer programmed and then inserted into their correct sockets on the user s application module 1 PROMLINK is a registered trademark of the DATA 1 Corporation 6 12 Console and Boot ROM Interface You can now connect the BOOT lt 3 0 gt L pins as shown in Figure 2 7 the rtVAX 300 boots from these ROMs Note
188. DAL are asserted the DMA controller waits for the assertion of RDY L in the RDY ERR window The assertion 8 18 Device Interfacing of ENBDMADAL turns on the 74F 543 transceivers shown in Figure 8 24 Once RDY L is received the DMAREADY signal is asserted asserting the DSPREADY signal through the DSP MEMORY PAL If this is a DMA read cycle the DSPDM ARDY signal causes the 74F 543 transceivers to latch the data on the DAL bus and continue to drive the DSP data bus with that data until the DSP finishes the read cycle The DSP global memory access cyde now completes and the DMA controller deasserts AS L DS L DMR L and ENBDMADAL See the state machine diagram described by Figure 8 8 and the timing diagram in Figure 8 4 for details 8 5 5 Control and Status Register A control and status register CSR is implemented between the rtVAX 300 and the DSP This register has an 8 bit 1 way mirror for interprocessor communication It also contains interrupt reset and hold bits for each processor 8 5 5 1 1 Way Mirror Register The bottom 8 bits of the CSR register see Figure 8 26 form a 1 way mirror register When the DSP reads from I O space the DSPIS signal is asserted indicating that the DSP is accessing the CSR The DSR BADDR PAL then asserts the ENBDSPCSR line once DSPSTRB asserts driving the contents of the mailbox onto the DSPDATA bus These contents are the value that was last written to by the rtVAX 300 and not the contents las
189. ESO of the chain descriptor after processing To protect against infinite loop a chain descriptor pointing back to itself considered owned by the rtVAX 300 regardless of the ownership bit state Hardware Architecture 3 71 Table 3 32 RDES2 Fields Bit Name Descriptor 08 00 PO Page Offset The byte offset of the buffer within the page Meaningful only if 51 lt 30 gt is set Note Receive buffers must be word aligned 30 16 BS Buffer Size The size in bytes of the data buffer Note Receive buffers size must be an even number of bytes not shorter than 16 bytes Table 3 33 RDES3 Fields Bit Name Descriptor 31 00 SV PV PA SVAPTE PAPTE Physical Address When 51 lt 30 gt is set RDES3 is interpreted as the address of the Page Table Entry and used in the virtual address translation process The type of the address System Virtual address SVAPTE or Physical Address PAPTE is determined by RDES1 lt 29 gt When RDES1 lt 30 gt is dear RDES3 is interpreted as the physical address of the buffer When 51 lt 31 gt is set RDES3 is interpreted as the VAX physical address of another descriptor Note Receive buffers must be word aligned Table 3 34 summarizes the validity of the Receive Descriptor status bits regarding the reception completion status Table 3 34 Receive Descriptor Status Validity Reception Rx Status Report Status RF TL CS FT DB CE ES LE BO DT FS LS FL TN OF
190. Gp lt TE Jey JeAuq 1220 187 ajqejoipaidun X 0 SI saaug sng SNIS pue oDesso N dSQ 0 XVA 19598 5 1eseu ola 1dnueju V V V V V V V V V V V V V od X X X X X X X X 0 L L 0 0 0 0 X 0 0 0 0 4 59 JON ejqeu3 ed 82104 qai snmeis 031 sneis 7 lt 9 gt ALIWA lt gt lt gt lt 0 gt 1 22 lt 2 lt gt 0c lt gt 61 lt gt 81 lt 4 gt 1 Zt lt 9 gt 1 91 lt gt 3nul NI YNO ov LA ev ZA v A 963 vVodvZ dav 2 48 eeg yGdvZ HAOSNHu L 1220 398 0 91 lt 0 gt 031
191. L compatible oscillator at a maximum frequency of 20 MHz A lower frequency can be used to lower power consumption or to match the processor to slower memory devices The duty must be 5090 e Basic Clock Output This TTL buffered dock must be used to synchronize the rtVAX 300 external logic and the CPU bus cydes This dock provides the P1 and P3 timing reference Note the following two items all timing is referenced to CLKA and Basic Clock Output CLKB This TTL buffered clock must be used to synchronize the rtVAX 300 system This dock provides the P2 and P4 timing reference 10 ms Interval Timer INTIM This signal produces a 10 ms TTL square wave 50 duty cycle 2 4 10 Power Supply Connections Power supply connections are as follows 45V DC power 45V e Reference ground 45V return GND 2 5 Memory and I O Space The rtVAX 300 processor can access 510M bytes 256 R W and 254 R O of memory space 1 0 space of 512M bytes The Ethernet coprocessor has direct DMA access to all of memory space 2M bytes of the rtVAX 300 processor s ROM space and 2M bytes of 1 0 space are reserved for the diagnostic ROM registers and special reserved areas 2M bytes of I O space are used for local registers Refer to Appendix C Figure 2 6 shows the partitioning and layout of memory addition to the registers shown in Figure 2 6 the rtVAX 300 p
192. M 1 When reset the internal Data bus is monitored on the external test pins BM L TEST 03 00 Quad Select bits Meaningful only in test mode TSM 1 These bits define the specific 4 bits of the internal Data bus or Address bus which are monitored on the external test pins BM L TEST 03 00 QAD Bits 00 03 007 01 07 047 10 lt 11 08 gt 1 lt 15 12 gt Start Read When set starts the Examine the data addressed by 5 15 lt 31 16 gt 15 fetched and stored into the same register field Reset by hardware at the end of the operation Address Data Before the Examine cycle starts it points to the location to be read 3 cydes after the assertion of CSR15 lt 15 gt it contains the read data 3 6 2 Descriptor and Buffer Formats The Ethernet coprocessor transfers frame data to and from receive and transmit buffers in rtVAX 300 memory These buffers are pointed to by descriptors also resident rtVAX 300 memory There are two descriptor lists one for receive and one for transmit The starting address of each list is written into CSRs 3 and 4 respectively A descriptor list is a forward linked either implicitly or explicitly list of descriptors the last of which may point back to the first entry thus creating a ring structure Explicit chaining of descriptors through setting xDES1 31 is called descriptor chaining The descriptor lists reside in VAX physical memory address space
193. MEMACCESS amp EQUI EQU2 EQU3 EQU4 z EXT WRITECYC2_ OUT DRAMREADY DEFAULT NEXT FINISHUP OUT RAS PRESE PRESE PRESE EXT PRESE EXT PRESE EXT PRESE EXT TW TW TS REF TR END TE FIN 0 DL 1 1 UT ENBCAS UT INVADDR2 UT INVADDR3 UT DRAMREADY RITECYC2 _ 0 0 0 0 106 NEXT WRITECYC3 IF DS NEXT WRITECYC2 RITECYC3 IF DS NEXT ACCESSCYC OUT ENBCAS OUT FLAG IF DS NEXT WRITECYC3 TARTREFRESH RESHCYC OUT RAS EFRESHCYC REFRESH OUT 5 DREFRESH ISHUP OUT REFCYC UT RAS ISHUP OUT RAS BCAS VADDR2_ VADDR3_ RAMREADY LAG CJ HA Hi EH EH Memory System Interface 5 47 PRESENT POWERU EXT FINISHUP PRESENT ILLEGA EXT FINISHUP PRESENT ILLEGAL2 EXT FINISHUP PRESENT ILLEGA EXT FINISHUP PRESENT ILLEGA EXT FINISHUP 5 48 Memory System Interface 6 Console and Boot ROM Interface This chapter provides information and examples for interfacing a processor status LED register and an external boot ROM to the rtVAX 300 processor The console is used for hardware and software debugging and the optional boot ROM is used to store the VAXELN image and user application permanently so that the rtVAX 300 processor can boot without an operational network or host system This ROM could also be used
194. NBVAXHLT L 2 1 ENBVAATE E g B Hal m 10 BTREQL 74 74 8 25 505 505 45V ABS 2 2 1 1 R1 82 R15 R13 1 1 1B 2K 2 1B 74 ENS Reset 1801 4 mm 6 E25 Note The rtVAX 300 uses CMOS 245 drivers for the DAL lines and ACTQ244 drivers for the CONTROL lines These drivers have very fast rise and fall times which can generate a fair amount of undershoot Some PAL devices and RAM chips may malfunction when exposed to excessive overshoot and under shoot It may be necessary to isolate these devices from the rtVAX 300 signal lines with TTL buffers or provide series termination resistors for these lines 8 28 Device Interfacing Address Decoder PAL Includes latch Note Socket used here PAL Decode PAL 22V10 E132 Bro p23 SELRAMH 522 SELROM H 321 CONEL 7 520 L Re 519 SELCSR L 5 518 Cycle Reset R3 16 2 15 DAL 26 13 50 DAL 25 11 pg 24 10 pg lt 23 gt 957 lt 22 gt 8 06 DAL 21 H 7 p5 lt 20 gt 6 p4 lt 19 gt 5 pa lt 18 gt 4 p2 lt 17 gt 3 p4 DAL 16 H 2 po ASH CLK DAL 27 DAL 28 DAL 29 DAL 2 Interrupt Decoder PAL Includes latch Note Socket used here PAL 2 74 1 2 2 RSTREQL 1 Run 2 L501 74 BUTTRST L s1 3 25 F32 E icon ENBRSTL 24 5
195. None Ne Ne Ne Se Ne Se Se Ne sl s s Se 5e e board level test 12 argument block offsets D 12 User Boot Diagnostic ROM Sample Ne Ne Ne Se Se Se Se Ne Ne Se Ne Ne Ne Ne s Ne Se s s Ne Ne Se Ne Se Se 5e e offset lt scratch address of scratch memory area failing pc address of longword to store failing pc if test fails expected data address of quadword that test can Store expected data if test fails actual data address of quadword that test can Store actual data if test fails flags board level test flags gt usrom share byte 300 usrom test 12 m lt gt ret return to caller Sbttl rtVAX 300 Board level Test 13 FUNCTIONAL DESCRIPTION This routine user supplied is called by the rtVAX 300 s resident firmware at system power on to do board level test 13 is called at IPL 31 in kernel mode with memory management disabled CALLING SEQUENCE calls 5 3005 usrom test 13 INPUT PARAMETERS scratch address of scratch memory area failing pc address of longword to store failing pc expected data address of quadword to store expected data actual data address of quadword to store actual data flags board level test flags IMPLICIT INPUTS OUTPUT PARAMETERS r0 test results IMPLICIT OUTPUTS kk ROUTINE VALUE 1 device not present or untestable User Boot Di
196. R A RESTORE CONSOLE if supplied Firmware sends an XON character 1116 to the attached terminal at entry to console mode to try to eliminate a hung line condition these indude for the 200 series keyboard locked executing Device Control String for example ReGIS SI XEL Tektronix mode local mode and Set Up 4 24 FIRMWARE 4 4 Entity Based Module and Ethernet Listener The Ethernet maintenance operation protocol MOP module supports MOP Version 3 and Version 4 functions The hardware device type of the rtVAX 300 the SYSID hardware code field is 10516 The Ethernet listener polls the Ethernet subsystem for receipt of packets Once a packet has been received the listener code inspects the packet protocol in order to determine the actions to take Important protocols are as follows e loopback packet protocol 90 00 for Ethernet connectivity testing The listener forwards or loops back a MOP loopback packet DECnet SYSID request packet protocol 60 02 type 5 for sizing the network The listener generates a DECnet SYSID e Ethernet counters request packet protocol 60 02 type 9 for checking the performance of the system on the Ethernet The listener generates an Ethernet counters packet DECnet bootstrap trigger packet protocol 60 01 type 6 for forcing the rtVAX 300 system to enter its bootstrap sequence This packet must include an 8 byte password and remote trigger must be enabled in ord
197. RAM 4 8 1 2 1 SCR A SAVE CONSOLE 4 8 1 2 2 SCR A RESTORE CONSOLE 4 8 1 3 Input 5 4 8 1 4 Memory Bitmap Descriptor Format 4 8 2 Optional User Supplied Diagnostic Routines 4 8 2 1 Self Test Routine Input 5 4 8 2 2 Self Test Routine Output 4 8 3 Linking the User Initialization User Test ROM 4 9 Creation and Down Line Loading of Test Programs 4 9 1 User Supplied Test 5 4 9 2 Writing Test 5 4 9 3 Using MOP to Test 5 410 Serial Line Boot Directions 4 11 ROM Bootstrap Operations 4 11 1 Booting from Cached ROM Address 4 11 2 Booting from ROM I O Address Space 5 Memory System Interface viii 5 1 Memory Speed and Performance 5 2 Static and Dynamic 5 5 3 Basic Memory 1 5 4 Cycle Status 5 5 5 Byte EINES ss gua Qr Pg 5 6 Data Parity 0 5 7 Internal Cache Control
198. RBA R W A 30 bit rtVAX 300 physical address of the start of the receive list CSR4 29 00 TBA R W A 30 bit rtVAX 300 physical address of the start of the transmit list Note The descriptor lists must be longword aligned 3 6 1 4 Status Register CSR5 This register contains all the status bits that the Ethernet coprocessor reports to the rtVAX 300 Figure 3 21 shows the format of CSR5 Table 3 22 describes its bit structure Figure 3 21 CSR5 Format 313029 2625242322212019181716151413121110090807060504 03 02 0100 S D MLO 004419 3 52 Hardware Architecture Table 3 22 5 5 Bits Bit Name Access Description 00 IS R W1 Interrupt Summary The logical OR of CSR5 lt 06 01 gt 01 TI R W1 Transmit Interrupt When set indicates one of the following e Either all the frames in the transmit list have been transmitted next descriptor owned by the rtVAX 300 or a frame transmission was aborted due to a locally induced error The port driver must scan the list of descriptors to determine the exact cause The transmission process is placed in the suspended state Chapter 5 explains the transmission process state transitions To resume processing transmit descriptors the port driver must issue the Poll Demand command A frame transmission completed and TDES1 lt 24 gt was set The transmission process remains in the running state unless the next descriptor is owned by the rtVAX 300 or
199. Read References Data Stream Read References Write References Floating Point Accelerator Floating Point Accelerator Instructions Floating Point Accelerator Data 5 Cache Memory Cacheable 5 Internal Cache Internal Cache Organization Internal Cache Address Internal Cache Data Block Allocation Internal Cache Behavior on Writes Cache Disable Register Memory System Error Register Internal Cache Error Detection Hardware Initialization Power Up Initialization Bus Initialization Processor Initialization Console Interface Registers Boot Register Console DUART Memory System Control Status Register Status LED Register Ethernet Coprocessor Co Id dog 2 2 Qo ga qu do o 3 27 3 29 3 29 3 29 3 30 3 30 3 30 3 31 3 31 3 31 3 31 3 32 3 32 3 33 3 34
200. Register Number Byte Offset E 52 Extract Register Number to Select Map Register Q22 bus Map Register 32 Bit Map Register 3130 20 19 0 Page Frame Number Valid 2 Selected Register Main Memory Address 28 9 8 0 Page Frame Number Byte Offset 29 Bit Physical Memory Address MLO 004468 Implementing these mapping registers allows Q22 bus DMA devices to perform DMA to and from contiguous Q22 bus addresses the S G map maps each page of Q22 bus memory to a page in system RAM if the Valid bit is set These mapping registers must be readable and writeable only from the rtVAX 300 and directly mapped to 1 0 space locations When the rtVAX 300 is writing to or reading from the Q22 bus the mapping registers are not used to address the Q22 bus The Q22 bus address space is directly mapped to locations in the rtVAX 300 1 0 space The S G map is used only when Q22 bus devices are performing DMA to the rtVAX 300 system memory The rtVAX 300 can access its memory space through the Q22 bus interface by accessing a Q22 bus address that is validly mapped to its own system RAM These mapping registers are not a requirement and some low cost rtVAX 300 bus interfaces may not implement them addition larger buffer areas that span many K bytes can be used to reduce the number of mapping registers In these applications sections of the rtVAX 300 system RAM are directly mapped to an addre
201. Reserved C9 Initialization of Ethernet coprocessor after selftests C8 UNJ AM function after selftests C7 Performing automatic restart boot halt action according to Boot Register Not implemented at this time 5 Floating Point Accelerator Test The different groups of floating point instructions induding F D G float adds subtracts multiplies comparisons and divides are tested and verified with known results This verifies the operation of the CFPA AF instructions AE instructions AD ACBF instructions AC ADDF 2 ADDF 3 instructions AB CMPF instructions continued on next page FIRMWARE 4 31 Table 4 5 Cont LED Test Number Code List Test LED Description No CVTFD CVTFG instructions A9 CVTFB CVTFW CVTFL CVTRFL instructions A8 CVTBF CVTWF CVTLF instructions A7 DIVF2 DIVF3 instructions A6 instructions A5 MULF2 MULF3 instructions A4 POLYF instructions A3 SUBF 2 SUBF3 instructions A2 TSTF instructions tests Passed 6 Interval Timer Test Verify the on board interval timer interrupt signal exists does generate interrupts when enabled and is accurate 9F Interval timer interrupts when disabled via IPL 9E Interval timer doesn t interrupt 9D Time between interrupts is too short or isn t consistent 9C Interval timer interrupts when disabled via ICCS IPR 90 Interval timer tests passed 7 Ethernet Test Tests that the Ethernet interface is
202. S Refresh Timing Parameters Application Module Address Decoder PAL Application Module Address Decoder Equations Memory Subsystem Sequencer State Machine PAL SCN 2681 DUART Timing Parameters Typical ROM Access Time Application Module Address Decoder Equations Console Sequencer State MachinePAL Interrupt Decoder Interrupt Decoder PAL Equations MAU Signals Description Ethernet Board Parts List Response to Bus Errors and DAL Parity Errors Q22 bus Map Register Bits TM S320C25 Digital Signal Processor Memory Map Recommended Operating Conditions DC CharacteristicS AC CharacteristicS Space Address Assignment Input Output Space Local Register Input Output Space 4 40 5 4 5 7 5 11 5 15 5 20 5 22 5 26 5 30 5 34 5 35 5 42 6 7 6 15 6 21 6 28 6 29 6 34 6 36 7 7 7 11 8 7 8 14 8 17 7 7 8 C 1 C 1 C 2 Preface The rtVAX 300 is a target processor designed to be embedded in a Digital Equipment Corporation computing network The rtVAX 300 processor permits the coupling of realtime instruments peripheral devices sensors and similar devices to DECnet VAX computers servers workstations and terminals The rtVAX 300 processor is also compatibl
203. S3O99V 55399 Narioo sauadv lt 0 gt 1 1 lt 0 gt SVO 1 1 1001348 7 94 wnioo 15 H 0 1e 1 va diZd Id vd d Zd 14 4 4 24 1 14 74 Edi d 14 54 14 54 d Zd 14 14 54 24 d 1 Ed Ed vd Ed 14 Ed 14 Hd Ed 1 Ed bd Ed 1 Ed 1 vd Ed Ed Id lt gt Q3 LH3SSV LON SI 31LIHAWT 20 922900 do WNVH3T8VN3 Sr an 1 XVAI3S3H 1 5956 ___ 14364 ez EP 001 101 5 57 80 1 7 vi 03 ee 800 2 L 6 ai 97 1 E oo KE gr ad 1 pora yore m 6 T1122 jsenbeu 1 3dq11998N3 5 i
204. SP AK Word Private Initialization ROM The DSP can read from only the initialization ROM The DSP MEMORY PAL asserts the CSROM output when a valid ROM program space address is placed on the DSPADDR bus The OEROM signal is later asserted and the DSP asserts the DSPSTRB line with DSPWRITE unasserted Since the ROMs are very slow the DMA CONTROL PAL adds three wait states to the access After those wait states have occurred the DMA CONTROL PAL asserts the DMAREADY line which in turn asserts the DSPREADY line ending the cyde 8 5 4 DSP DMA Cycles Certain portions of the DSP s memory can be mapped globally This global memory is mapped between locations 8000 and FFFF Access to these locations causes the DSP DMA controller to assert the 3005 DMR L line Then the rtVAX 300 tri states the DAL bus and all of the control signals and asserts the DMG L line now the DMA controller must start a DMA access cyde Once the DMA controller state machine receives the DMG L signal from the rtVAX 300 the DRIVEADDR signal is asserted to drive the DSP s DMA address onto the rtVAX 300 s DAL bus through the 74F 244 drivers shown in Figure 8 25 The assertion of DRIVEADDR asserts the ENBADDR signal through the REG PAL driving DAL 31 02 CSDP lt 4 2 0 gt L and BM 3 0 L with the appropriate address and control information Next the AS L signal is asserted and later the DRIVEADDR signal deasserts Now the DS signal and the ENBDMA
205. SSCYC IF 1 4 amp LWRITE 6 FINVADDR2 amp FINVADDR3 6 FLAG 105 NEXT READCYC 00 DRAMREADY OUT ENBCAS OUT INVADDR2 IF 4 amp LWRITE 6 FINVADDR2 amp FINVADDR3 amp FLAG DS NEXT READCYC 00 DRAMREADY OUT ENBCAS OUT INVADDR2_ OUT INVADDR3_ IF 1 4 amp LWRITE 6 FINVADDR2 amp FINVADDR3 amp FLAG 105 NEXT READCYC OUT DRAMREADY OUT ENBCAS OUT INVADDR2 IF 1 4 amp LWRITE amp FINVADDR2 amp FINVADDR3 6 FLAG 105 NEXT READCYC 00 DRAMREADY OUT ENBCAS OUT INVADDR2_ OUT INVADDR3_ IF 1 4 amp LWRITE amp FINVADDR2 amp FINVADDR3_ NEXT WRITECYC1_ OUT DRAMREADY OUT ENBCAS OUT INVADDR2 IF 1 4 amp LWRITE amp FINVADDR2 amp FINVADDR3_ NEXT WRITECYC1_ OUT DRAMREADY OUT ENBCAS OUT INVADDR2 OUT INVADDR3 IF 4 amp LWRITE 6 FINVADDR2 amp FINVADDR3_ NEXT WRITECYC1_ OUT DRAMREADY OUT ENBCAS OUT INVADDR2 IF 1 4 amp LWRITE 6 FINVADDR2 amp FINVADDR3_ 5 46 Memory System Interface NEXT WRITECYC1_ OUT DRAMREADY OUT ENBCAS OUT INVADDR2 OUT INVADDR3 DEFAULT NEXT ACCESSCYC PRESENT READCYC IF MEMACCESS amp EQUI EQU2 EQU3 EQU4 N EXT ACCESSCYC OUT ENBCAS OUT DRAMREADY OUT FLAG EQU4 NEXT REFRESHCYC OUT RAS OUT ENBCAS OUT INVADDR2 OUT INVADDR3_ OUT DRAMREADY OUT FLAG DEFAULT NEXT FINISHUP OUT RAS UT ENBCAS UT INVADDR2 UT INVADDR3 UT DRAMREADY UT FLAG PRESENT WRITECYCIl IF
206. T I This signal causes nonmaskable interrupt at IPL 16 that causes the rtVAX 300 processor to enter the console emulation program in the firmware This signal is negative edge triggered and internally synchronized e Power Failure PWRFL L I This signal allows external logic to notify the rtVAX 300 of a power failure The rtVAX 300 processor samples the signal every The PWRFL L signal generates an interrupt at IPL 1E4g This interrupt is internally acknowledged by the 300 and does not use an interrupt acknowledge bus cycle This signal is edge sensitive and internally synchronized Boot BOOT 3 0 I These pins determine the default boot actions of the rtVAX 300 These signals are pulled up internally and default to 1 When a pin is low it registers 0 See Table 3 12 for different allowable boot devices e Boot Requests BTREQ L OD This signal is asserted low once a valid trigger request is received over the Ethernet from a host system This lead is gated with a board level remote trigger enable signal and fed into the HLT L signal 2 4 9 Clock Signals Clock signals are as follows e 20 MHz Clock Output CLK 20 This taps into the internal oscillator and can be fed back into CLKIN to drive the rtVAX 300 Note Use this signal only to drive CLKIN 2 20 Technical Specification e System Clock Input CLKIN 1 This system clock input must be TT
207. The rtVAX 300 CVAX chip provides special microcode assistance to aid the macrocode emulation of the following instruction groups Character string except MOVC3 5 CMPC3 5 LOCC SCANC SKPC and SPANC Decimal string CRC EDITPC e H_floating Octaword instruction groups are not implemented but may be emulated by macrocode The rtVAX 300 processor provides microcode assistance for the emulation of these instructions by system software The processor processes the operand specifiers creates a standard argument list and takes an emulated instruction fault Table 3 1 describes microcode assisted emulated instructions Table 3 1 Microcode Assisted Emulated Instructions OP Mnemonic and Arguments Description nzvc Exceptions 20 ADDPA addlen rw addaddr ab Add packed 4 operand 0 rsv sumlen rw sumaddr ab 21 ADDP6 adadllen rw addladdr ab Add packed 6 operand TERO rsv dov add2len rw add2addr ab sumlen rw sumaddr ab F8 ASHP cnt rb srclen rw Arithmetic shift and EEO rsv srcaddr ab round rb dstlen rw round packed dstaddr ab 35 len rw srcladdr ab Compare packed 3 00 src2addr ab operand 37 CMPP4srcllen rw srcladdr ab Compare packed 4 00 src2len rw src2addr ab operand OB CRC inicrcrl strlen rw Calculate cydic 00 stream ab redundancy check reserved operand fault iov integer overflow trap decimal overflow tra
208. V is used to supply power to the MAU The MAU may be the DP 8392 chip and associated circuitry or may be an external MAU connected to the station by an AUI cable It is not permissible to supply power to both 5 simultaneously in order to prevent transmission on two networks When the MAU is the onboard DP8392 chip the current drawn from the 12V supply is approximately 220 mA When power is supplied to an external MAU through the AUI connector the current draw can be as much as 0 5A steady state The voltage that appears at the AUI connector must be at least 11 28V 12V 6 when the external MAU is drawing the maximum current of 0 5A It is therefore important to minimize the DC resistance of the path between the power supply of the station and the AUI connector In addition to the steady state current requirements there are consid erations for surge current The 12V supply must be able to handle the surge current drawn by an external MAU when it is hot swapped The connection of an external MAU should not crash the station or otherwise affect normal operation of the station The 12V supply as seen at the AUI connector is allowed to go out of tolerance during MAU hot swap Transceivers draw currents of up to 25 A lasting 500 us A significant amount of noise can be coupled into the voltage return line for the 12V supply Most of this is switching noise from the DC to DC converter either onboard or in the external MAU It is
209. a following the hash filter Subsequent non multicast addresses if any are ignored The address crc is generated by the crc polynomial specified by the IEEE 802 3 standard 274 32 26 23 22 16 12 11 10 8 7 5 4 2 FCS X X X X X X X X X 1 include lt stdio gt main argv int char argv continued on next page Sample C Program to Build Setup Frame Buffer 1 Example E 1 Cont Hash Filtering Setup Frame Buffer Creation C Program FILE fopen fin fout unsigned char address 6 setup frame 128 line 80 physical_cnt 0 int i hash_index if 2 printf n Usage program in_filename out_filename n exit 1 if fin fopen argv 1 r printf Error s cannot be open for read n argv 1 exit 1 if argc gt 3 if fout fopen argv 2 w printf Error s cannot be open for write n argv 2 fclose fin exit Iy initialize the setup buffer for i 0 i lt 128 i setup_frame i 0 while 1 get a Ethernet address if fgets line 80 fin break sscanf line 2X 2X 2X 2X 2X 2X amp address 0 amp address 1 amp address 2 amp address 3 amp address 4 amp address 5 check the address type if address 0 amp 1 multicast address calculate the hash index has
210. a DDCMP MOP load function is executed See the DDCMP specification for more details The SCN 2681 console DUART must be supplied by the user for this to work 101 CSB1 DECnet DDCMP boot Same as CSBO except the secondary DUART is initialized to 2400 bps 110 CSB2 DECnet DDCMP boot Same as CSBO except the secondary DUART is initialized to 9600 bps 111 EZAO Boot from Ethernet The standard MOP protocol for Ethernet loads is used This field is initialized from the Boot Register at power on or reset and may be modified by the user s initialization code continued on next page Table 4 9 Cont Default Boot Device Register Fields Field Description lt 3 gt Reserved lt gt Set if memory test is to be performed power up cleared when test is not to be performed This register is a pseudo register located in scratch RAM lt 75 gt Reserved 4 8 1 21 SCR A SAVE CONSOLE Scratch RAM contains the longword physical address of a save routine supplied by the operating system This routine is called as the console program enters console mode The routine gives the operating system the opportunity to save the current state of hardware that may be obliterated by the console device and to ensure that the console device hardware is in an operable state as discussed in Section 4 3 11 and shown in lt scratch ram defs tab This routine is called with a J SB instruction at IPL 1F1g in kernel mode with mem
211. a watchdog timer If the transmitter is active for an illegal length of time the transmitter is disabled Thus jabbering broken nodes are not allowed to interfere with the operation of the network Figure 7 4 shows an DP8392 chip block diagram Figure 7 4 Network Interconnect DP8392 Chip Block Diagram Data RXI Receivers Receive Squelch Collision Detection 10 MHz Oscillator Transmit Squelch Heartbeat Generator Jabber Monitor TX Data Transmitter Transceiver Medium Interface Interface MLO 004461 7 6 1 2 2 Interface the coaxial cable side the DP8392 chip connects to the 50 2 Ethernet coaxial cable by BNC connector On the rtVAX 300 side the DP8392 chip differential signals connect to the rtVAX 300 differential signals through isolation transformers 7 8 Network Interconnect Interface 7 6 2 Implementation of Design The following sections discuss implementation considerations e Section 7 6 2 1 discusses the transceiver e Section 7 6 2 2 discusses layout requirements e Section 7 6 2 3 lists Ethernet board parts e Section 7 6 2 4 discusses the DC DC converter 7 6 2 1 ThinWire Transceiver Figure 7 5 shows the ThinWire interface BNC connector and the AUI connector 15 pin D sub Included in this figure is the BNC connector for direct ThinWire connection and the required capacitive bypassing between reference planes The DP
212. a Block Data MLO 004567 Internal Cache Behavior on Writes On CVAX processor generated write references the internal cache is write through All CVAX processor write references that hit the internal cache cause the contents of the referenced location in main memory to be updated as well as the copy in the cache On DMA write references that hit the internal cache the cache entry containing the copy of the referenced location is invalidated If the internal cache is configured to store only I stream references then the entire internal cache is also flushed whenever an REI instruction is executed The VAX architecture requires that an REI instruction be executed before executing instructions out of a page of memory that has been updated Hardware Architecture 3 35 3 3 2 5 Cache Disable Register The cache disable register CADR IPR 37 controls the internal cache and is unique to processor designs that use the CVAX chip Figure 3 12 shows the cache disable register and Table 3 10 lists its fields Figure 3 12 Cache Disable Register 31 08070605040302 0100 I D D 2111 111 1 MLO 004568 Table 3 10 Cache Disable Register Fields Data Bit Definition 31 08 07 06 lt 07 gt lt 06 gt lt 05 04 gt lt 05 gt lt 04 gt lt 03 02 gt lt 01 gt Unused Always read as zeros Writes have no effect These bits are used selectively to enable or disa
213. a oF eH 6696 40 xS ev 5 i Eod al eva s 2 125 Eu a 5254 zy zia 6 ogg 9 6 Y H lt vi si cok T i 0L 5289 2 T lt e gt va Z 2 vL 6014 2 lt gt L 984 BE 5 1892 ozz S 32 99 1uv a 407 297 Iv Lg 2 6296 lt gt TA 48 0 9 al 09 093 2 080 7 3998 0320 1dnueiu w 1800 yor L ozz 0220 1dnueju ES 66H s maxa JOojejeuet 10128A 1dnueiu 388 00 44444202 9 00000202 sseippy 10 63000 62 01072 m eL N3 5
214. address set by CSR3 or the position retained when the Rx process was previously stopped If no descriptor can be acquired the Reception process enters the suspend state The Start Reception command is honored only when the Reception process is in the stopped state The first time this command is issued an additional requirement is that CSR3 has already been written to else the Reception process will remain in the stopped state When cleared the Reception process is placed in the stopped state after completing reception of the current frame The next descriptor position in the receive list is saved and becomes the current position after reception is restarted The Stop Reception command is honored only when the Reception process is in the running or suspended state Start Stop Transmission command When set the transmission process is placed in the running state and the Ethernet coprocessor checks for a frame to transmit at the transmit list at the current position the address set by CSR4 or the position retained when the Tx process was previously stopped If it does not find a frame to transmit the transmission process enters the suspend state The Start Transmission command is honored only when the transmission process is in the stopped state The first time this command is issued an additional requirement is that CSR4 has already been written to else the transmission process will remain in the stopped state When cleared the
215. addresses are virtually mapped through single level page tables and process space addresses virtually mapped through 2 level page tables Refer to the VAX Architecture Reference M anual for descriptions of the virtual to physical address translation process and the format for VAX page table entries PTEs 3 1 8 1 Translation Buffer To reduce the overhead associated with translating virtual addresses to physical addresses the rtVAX 300 processor employs a 28 entry fully assodative translation buffer for caching VAX PTEs in modified form Each entry can store a modified PTE for translating virtual addresses in either the VAX process space or VAX system space The translation buffer is flushed whenever memory management is enabled or disabled for example by writes to IPR 56 when any page table base or length registers are modified for example by writes to IPRs 8 to 13 and by writing to IPR 57 TBIA or IPR 58 TBIS Hardware Architecture 3 11 Each entry is divided into two parts 23 bit tag register and 31 bit PTE register The tag register stores the virtual page number VPN of the virtual page that the corresponding PTE register maps the PTE register stores the 21 bit PFN field the PTE V bit the PTE M bit and an 8 bit partially decoded representation of the 4 bit VAX PTE PROT field from the corresponding VAX PTE and a translation buffer valid TB V bit During virtual to physical address translation the conten
216. after 160 ms it asserts the HLT L line of the rtVAX 300 processor and stops counting The assertion of the HLT L line on the rtVAX 300 processor breaks the program execution and drops the program into console emulation This break detection circuit can be eliminated if a separate halt switch is implemented or if the console break key is not needed Console and Boot ROM Interface 6 11 6 2 Booting from External ROM The default booting device for the rtVAX 300 is the network In this configuration the BOOT 3 0 L pins are tied to Vcc or left unconnected The BOOT 3 07 L pins are tied high through pull up resistors When the rtVAX 300 initializes after a power on reset it sends the maintenance operation protocol M OP message over the network The host system responsible for booting the rtVAX 300 receives these MOP requests and begins to down line load the ELN system file to the rtVAX 300 Oncethis file is loaded into the rtVAX 300 s memory the rtVAX 300 begins executing the application software from its RAM Many applications require the rtVAX 300 to boot internally independently of the state of the network or host This is accomplished by connecting a ROM the rtVAX 3005 1 0 space or memory space and fixing the VAXELN system image in this ROM The rtVAX 300 can now boot the intended application if the host node is not available or the network segment fails This feature is important if controller downtime is unacceptable 6 2 1
217. agnostic ROM Sample 0 13 0 test failed 1 test passed SIDE EFFECTS None M board level test 13 argument block offsets offset Scratch address of scratch memory area failing address of longword to store failing pc if test fails expected data address of quadword that test can Store expected data if test fails actual data address of quadword that test can Store actual data if test fails flags board level test flags gt usrom share byte 300 usrom test 13 m lt gt ret return to caller Sbttl rtVAX 300 Board level Test 14 D 14 User Boot Diagnostic ROM Sample Ne Se Ne Se Ne Se Se Ne s Ne Ne Ne Ne Se Ne Ne Ne Ne Se Se Se Ne Se Se Se 5e 5s 5e e FUNCTIONAL DESCRIPTION This routine user supplied is called by the rtVAX 300 s firmware at system power on to do board level test 14 at IPL 31 in kernel mode with memory management disabled CALLING SEQUENCE calls 5 300 usrom test 14 INPUT PARAMETERS scratch address of scratch memory area failing pc address of longword to store failing pc expected data address of quadword to store expected data actual data address of quadword to store actual data flags board level test flags IMPLICIT INPUTS None OUTPUT PARAMETERS r0 test results IMPLICIT OUTPUTS None ROUTINE VALUE 1 device not present or
218. ails of the connection to Thickwire and ThinWire Ethernet are in Chapter 7 The Ethernet coprocessor can perform direct memory access DMA to any location in memory space This controller is programmed by reading from and writing to a set of registers in the Ethernet coprocessor SGEC Refer to Section 2 5 2 2 Technical Specification Figure 2 1 rtVAX 300 Block Diagram CLKA CLKIN CLK20 ENS IRQ lt 3 0 gt IRQ lt 1 gt Arb Logic CSDP lt 3 0 gt BM and CVAX BM lt 3 0 gt __ Buffers IRQ Ethernet Coprocessor DMG NI DMR DMR MG DMA USER DMG D Arb Logic USER DMR Boot Ferren Decode Logic AS DS Buff CFPA CCTL RDY ERR rtVAX 300 Connector Pins DAL lt 31 00 gt DAL Buffers MLO 006367 Technical Specification 2 3 2 1 5 Decode and Control Logic The control logic consists of state machines responsible for the following RDY signal generation for the ROMs DMA and interrupt arbitration between DMA devices and the Ethernet coprocessor and decoding internal addresses to control the output buffer direction and to assert CSDP lt 4 gt The control logic also provides the counters for generating the timeout error signal and the 10 ms interval timer interrupt 2 1 6 Interrupt Structure The rtVAX 300 processor has access to the four interrupt request lines that the CVAX chip uses Int
219. ain 1 048 576 bits divided into 512 rows each containing 2048 data bits Thus it takes only 512 refresh cycles for each row to refresh every bit within the DRAM The specifications for the 80 ns page mode DRAMs require that every row of the entire DRAM array be refreshed every 8 0 ms The rows can all be refreshed in sequence every 8 0 ms or one row can be refreshed every 15 6 us 8 0 ms 512 rows The 8 bit counter shown in Figure 5 12 sets the refresh request SR latch every 12 8 us and the memory controller then refreshes a row of the DRAMs and resets the SR latch In this scheme a new row is refreshed every 12 8 us so the entire DRAM is refreshed every 6 6 ms 512 x 12 8 us and the refresh requirements are met Before a refresh cycle can occur a refresh row address must be generated This address is latched into the DRAMs and each bit cell in that row is refreshed during the refresh cyde The DRAMs that were used generate their own refresh address internally simplifying the external logic by eliminating the need for a refresh row address counter DRAMs that support column address strobe CAS before row address strobe RAS refresh internally generate their own refresh row address When the DRAM CAS line is asserted before the RAS line the internal refresh row address counter is incremented and the next row is selected When the RAS line is then asserted the selected row of bit cells are refreshed RAS and CAS are then deass
220. al timer interrupts are disabled This bit is cleared on power up 5 007 Unused Read as zeros must be written as zeros Interval timer requests are posted at IPL 1616 with a vector of C016 The interval timer is the highest priority device at this IPL 3 10 Hardware Architecture 3 1 6 ROM Address Space The entire 128K byte boot and diagnostic ROM may be read from ROM space addresses 20040000 through 2007FFFF Writes to this space result in a machine check Any I stream read from the halt mode ROM space places the rtVAX 300 in halt mode The CVAX processor is protected from further halts 3 1 7 Resident Firmware Operation The rtVAX 300 resident firmware can be entered by transferring program control to location 20040000 Section 3 1 9 lists the various halt conditions that cause the CVAX processor to transfer program control to location 20040000 When running the rtVAX 300 resident firmware provides the services expected of a VAX console system In particular the following services are available Bootstrap following processor halts or initial power up An interactive command language allowing the user to examine and alter the state of the processor Diagnostic tests executed on power up that check out the CVAX processor the memory system and the Ethernet coprocessor 3 1 8 Memory Management The rtVAX 300 implements full VAX memory management as defined in the VAX Architecture Reference Manual System space
221. alculated as follows 1 CLKA period State machine output delay 74F 00 propagation delay Data in hold time In this case data in hold time 50 ns 12 ns 5 ns 233 ns 6 1 5 Console Oscillator A 3 6864 MHz crystal oscillator provides the clock signals and internal timing to the DUART The baud rate and other serial line configuration information is software programmable by writing to the appropriate console register The built in firmware of the rtVAX 300 sets the baud rate to 9600 with 8 data bits and 1 stop bit 6 1 6 Line Drivers and Receivers The voltages of RS 232 and DE C 423 are not directly TTL compatible Line drivers and receivers must convert the TTL voltages of the DUART to the standard voltage levels that are used for RS 232 and DEC 423 applications The 9636 and 9639 line drivers and receivers see Figure 6 10 serve as the DEC 423 interface drivers 6 1 7 Console Break Key Support You can set up the console terminal break key to halt the rtVAX 300 program execution This is accomplished by adding a break detection circuit connected to the HLT L line of the rtVAX 300 When the break key of the console terminal is depressed the RXD line receiver output is asserted low for more than 160 ms The counter see Figure 6 10 begins counting as soon as the RXD line is low it will reset as soon as the RXD line returns to the high state This counter is clocked by the 10 ms interval timer and once it counts to 16
222. all memory management hardware including a 28 entry translation buffer and several system registers such as the cache disable register CADR memory system error register MSER and system control block base register SCBB The CVAX chip provides the following functions e Fetches all VAX instructions e Executes 181 VAX instructions e Assists in the execution of 21 additional instructions e Passes 70 floating point instructions to the chip The remaining 32 VAX instructions induding H floating and octaword must be emulated in macrocode The CVAX chip provides the following subset of the VAX data types Byte e Word Longword e Quadword e Character string e Variable length bit field acrocode emulation can provide support for the remaining data types The cache is a 1K byte 2 way associative write through cache memory that is implemented within the CVAX chip 1 2 Floating Point Accelerator The floating point accelerator is implemented by the CVAX floating point accelerator CF PA chip The chip contains about 60 000 transistors and executes 70 floating point instructions The CFPA chip receives operations code information from the CVAX chip and receives operands directly from memory or from the CVAX chip The floating point result is always returned to the CVAX chip 1 2 Overview of the rtVAX 300 Processor 1 3 Ethernet Coprocessor The rtVAX 300 processor contains the second generation E
223. an error message is issued and the contents of the SP are unpredictable If no qualifier is specified MEMORY is assumed Valid qualifiers are e Search memory for a page aligned 128K byte segment of good memory e RPB Search memory for a restart parameter block The search leaves memory unchanged SP contains the address of the 20016 4 3 6 6 Halt H ALT A halt message is displayed followed by the console prompt FIRMWARE 4 15 4 3 6 7 Help HE LP Supported console commands are listed along with supported parameters and available options Figure 4 5 illustrates the Help screen Figure 4 5 Help Display gt gt gt help DEPOSIT B W L 0 P V I 3 U N lt n gt lt addr gt sym lt datum gt EXAMINE B W L 0 P 1 0 N lt n gt lt addr gt sym Jj SET BOOT lt ddcu gt SET BFLG lt bflg gt SET HALT lt 0 3 gt SET TRIG lt 0 1 gt SHOW BOOT BFLG ETHER HALT MEM TRIG INITIALIZE UNJAM BOOT R5 lt bflg gt PRBx CSBx CONTINUE START lt addr gt REPEAT lt cmd gt TEST lt n gt FIND MEM RPB XFER lt addr gt lt cnt gt HALT HELP gt gt gt lt endmark gt The Help display is intended to aid the user and does not provide a complete description of the commands 4 3 6 8 Initialize INITIALIZE A
224. an rtVAX 300 named RTVAX1 connected to TXB4 to which you need to down line load the file MOM LOAD RTVAX300 SYS you would enter the following NCP SET command SET NODE 1 ADDRESS 1 1 SERVICE CIRCUIT TX 1 4 LOAD FILE MOMSLOAD RTVAX300 SYS FIRMWARE 4 47 7 Start the DECnet line using the terminal name derived in step 4 as follows NCP gt SET LINE tt m n STATE ON LINE SPEED xxxx tt m n The terminal name derived in step 3 XXXX The line speed to be used one of 1200 2400 or 9600 bps for the rtVAX 300 For example you use the following NCP SET LINE command to set the line for device TXB4 at 9600 baud NCP SET LINE TX 1 4 STATE ON LINE SPEED 9600 8 Start the DECnet virtual circuit and instruct DECnet to service load requests as follows gt SET CIRC tt m n STATE ON SERVICE ENABLED For example you use the following NCP SET CIRCUIT command to start the virtual circuit for device TXB4 specified in the previous step SET CIRC TX 1 4 STATE ON SERVICE ENABLED Note Use NCP DEFINE rather than NCP SET commands to save the information in the nonvolatile database where it can be automatically used whenever DECnet is started or restarted 4 11 ROM Bootstrap Operations The ROM boctstrap allows an rtVAX 300 system to execute either out of ROM or out of RAM after the system image has been copied from ROM to RAM You can specify which RAM bootstrap to use in any of the following
225. and continue on error It has two levels of subtests functional unit of the device under test particular function of the subunit being tested FIRMWARE 4 29 Table 4 5 LED Test Number Code List Test LED Description No 0 Initialization test This test is not user selectable FF Power up value this is the value set on power up It indicates that there is power on the module If the display remains at this value the rtVAX 300 is unable to execute the first few instructions correctly FE The first few instructions have completed The rtVAX 300 can write to the display register FD Special value used for the rtVAX 300 HALT test in the tester box This value is used only when the using the rtVAX 300 tester box FC Special value used for the rtVAX 300 HALT test in the tester box This value is used only when the using the rtVAX 300 tester box FB The actual presence of the LED display is verified F8 Value set when User Initialization ROM entry point is called F7 F1 Reserved for use by the User s Initialization ROM The preliminary initialization is completed Basic rtVAX 300 instructions work and it is possible to communicate off the chip 1 rtVAX 300 ROM verification LED tests and checksum Verify the ROM checksum the high and low bytes of ROM are the same version and ROM test patterns are correct If the Tester is present the LED registers are verified This may be the only means t
226. and interpreter is case insensitive The lowercase ASCII characters a through z are treated as uppercase characters The parser rejects characters with codes greater than 7816 These characters are acceptable in comments Type ahead is not supported Characters received before the console prompt is displayed are checked for control characters such as 2115 and but otherwise discarded 4 3 6 Console Commands The rtVAX 300 console program supports the commands described in the following sections 4 3 6 1 Boot B OOT R5 ATUM gt lt device name gt The console program loads an operating system If the load is successful the operating system is started Qualifier The qualifier is of the form DATUM where DATUM is a hexadecimal value passed as a longword in register five R5 to the bootstrap program This valueis used as boot flags by the loaded code An equivalent qualifier takes the form R5 lt DATUM gt for backward compatibility Refer to the spedification of the loaded operating system for a detailed list of other used flags The rtVAX 300 system firmware interprets only bit 9 of this longword If bit 9 is set the firmware immediately halts before transferring control to the booted code The rtVAX 300 system firmware uses none of the other bits Device Name 1 The character sequence is 0016 OA16 0016 16 16 16 2016 which
227. another descriptor Note Transmit buffers may start on arbitrary byte boundaries Table 3 39 summarizes the validity of the Transmit Descriptor status bits regarding the transmission completion status Table 3 39 Transmit Descriptor Status Validity Transmission Tx Status Report Status LO NC LC EC HF ES TO LE TN UF DE Underflow X X V X WM V Excessive collisions V V X V Watchdog timeout X M X X X WM V Internal Loopback X X X V V Valid X Meaningless 3 6 2 3 Setup Frame A setup frame defines the Ethernet coprocessor Ethernet destination addresses These addresses filter all incoming frames The setup frame is never transmitted over the Ethernet nor looped back to the receive list While the setup frame is being processed the receiver logic temporarily disengages from the Ethernet wire The setup frame size is always 128 bytes and must be wholly contained in a single transmit buffer There are two types of setup frames e Perfect Filtering addresses 16 list 3 78 Hardware Architecture Imperfect Filtering hash bucket 512 heads one physical address 3 6 2 3 1 First Setup Frame A setup frame must be queued that is placed in the transmit list with Ethernet coprocessor ownership to the Ethernet coprocessor before the reception process is started except when the Ethernet coprocessor is in promiscuous reception mode Note The self test completes with the E
228. another HLT L to be recognized HLT L must be deasserted for at least two microcycles A break detection circuit may be added to the console receive line to assert the HLT line when the console break key is depressed Chapter 6 gives details of and illustrates this circuit When in the HALT position the RUN HALT switch S1 sets a flip flop which asserts the HLT L output to the rtVAX 300 processor as shown in Figure 8 11 This causes the rtVAX 300 to enter a halt routine and to store the content of certain rtVAX 300 registers This is a momentary contact switch that is normally in the RUN position 3 16 Hardware Architecture 3 1 12 3 Execution of the HALT instruction or assertion of HLT L causes the execution of macroinstructions to be suspended and the restart process to be entered The initiation of the restart process is under control of the processor microcode which saves the processor state and passes control to the internal boot and diagnostic ROMs beginning at physical address 20040000 These ROMs implement the console emulation program and give control to the console displaying the 2 prompt when a halt condition is detected Exceptions There are three types of exceptions Trap Fault Abort A trap is an exception that occurs at the end of the instruction that caused the exception After an instruction traps the PC saved on the stack is the address of the next instruction that would normally have been executed and
229. are equal to 111 binary and the four least significant bits contain ALU condition codes e 07 00 captures the offset between the virtual address of the start of the instruction being executed at the time of the machine check saved PC and the virtual address of the location being accessed PC at the time of the machine check PC lt 31 00 gt captures the virtual address of the start of the instruction being executed at the time of the machine check PSL PSL 31 002 captures the contents of the PSL at the time of the machine check System Control Block The system control block SCB consists of at least two pages in memory that contain the vectors by which interrupts and exceptions are dispatched to the appropriate service routines IPR 17 the system control block base register SCBB points to the SCB Figure 3 5 represents the SCB Table 3 6 describes its format 3 24 Hardware Architecture Figure 3 5 System Control Block Base Register 313029 0908 00 H Physical Longword Address of PCB DNA SCBB MLO 004409 Table 3 6 System Control Block Format SCB Interrupt Exception Param Offsetig eter Notes 00 Unused IRQ passive release on other VAX systems 04 Machine check Abort 4 Parameters depend on error type 08 Kernel stack not valid Abort 0 Must be serviced on interrupt stack 0 Power Interrupt 0 is raised 16 10 Reserved privileged Fault 0 instruction 14 Cust
230. as main memory address bits 08 00 These bits are undefined on power up and the negation of DCOK when the processor is halted 8 4 3 Dual Ported Memory 8 14 Another communication method that can used is the design of dual ported memory Either the system RAM can be dual ported or some dual ported RAM be placed the I O space addition dual ported RAM in the 1 0 space does not require the implementation of cache invalidation cydes because 1 0 references are not stored in the cache Dual ported RAM in the 1 0 space has the advantage that the processor can still read from and write to system RAM while the 1 0 device is reading from and writing to the dual ported 1 0 RAM This method does not require the design of a DMA engine therefore the logic may be simpler Device Interfacing 8 5 rtVAX 300 to Digital Signal Processor DSP Application Example A 2 processor system was designed and constructed as an application example for the rtVAX 300 This application module has the following features 4M bytes of parity DRAM system memory that operates with one wait state A 1M byte user boot ROM for permanent storage of application software Two DEC 423 serial lines for the console and down line loading DECnet Ethernet network interface for both ThinWire and Thickwire A Texas Instrument TM S320C25 DSP with 4K words of private memory 4K words of initialization and loader ROM for the DSP A D A and A D converter
231. asserted by the PAL based on AS L from the rtVAX 300 to indicate that the address cyde status information is valid and that the rtVAX 300 is starting a console or ROM access The data strobe signal of the rtVAX 300 processor is asserted when the processor is ready to transfer data on the DAL bus This signal is asserted when the rtVAX 300 is in the P3 or P4 state and deasserted when the rtVAX 300 is in the P1 or P2 state It is used by this state machine to determine when to assert the IOREADY line This latched version of the rtVAX 300 WR L signal is asserted when the rtVAX 300 is carrying out a bus write This signal asserts when the rtVAX 300 trys to access the console registers This pin is the latched byte mask for the lowest byte in the rtVAX 300 s 32 data lines This signal asserts when the rtVAX 300 runs an interrupt acknowledge cyde for an interrupt caused by the console This signal asserts when the rtVAX 300 tries to access the user boot ROM It causes the state machine to assert to complete the cycle This signal asserts during power up and system reset It resets this state machine to the idle state continued on next page Console and Boot ROM Interface 6 29 Table 6 5 Cont Console Sequencer State Machine PAL Pin Setting Comment 11 ICPUST This signal asserts when the rtVAX 300 is accessing the processor status LED register Signal Outputs 16 1
232. ate cache entry cache No second reference H L H L Machine check if demand No machine check read Invalidate cache Invalidate cache entry entry Log error in MSER Log error in MSER No second reference L L H L Machine check if demand No machine check read Invalidate cache Invalidate cache entry entry Log error in MSER Log error in MSER No second reference X L L X No machine check No No machine check cache change No second reference retry Invalidate cache entry No retry 2 6 4 Octaword Transfer Read Cycle During an octaword transfer read cycle the rtVAX 300 reads four consecutive longwords supplying the address of the first longword only An octaword transfer read cycle requires at least nine microcycles Only the Ethernet coprocessor initiates octaword transfer reads The sequence of events of octaword transfer read is as follows 1 ThertVAX 300 transfers the physical address of the preferred longword onto the DAL lt 29 02 gt lines This address is always octaword aligned and lines DAL lt 03 02 gt are always zero The DAL lt 31 30 gt lines are set to 11 to indicate an octaword transfer The rtVAX 300 sends an address of only the initial longword preferred other associated addresses implied and therefore are not transferred These implied addresses are generated by incrementing the count on address bits 2 and 3 2 Lines CSDP lt 4 0 gt L 1 111 gt demand read
233. be latched during the address transfer portion of the memory access cycle The BM 3 0 L lines of the rtVAX 300 must be connected to a separate 74F 373 latch The HOLD L line of this latch cannot be connected directly to the AS L signal of the rtVAX 300 Decoding logic which decodes LADDR 31 30 is used to gate the HOLD L input of the address latches with the AS L line of the rtVAX 300 1 Figure 5 11 schematically represents this logic Figure 5 1 Memory Organization ET 00 eee i 08 gt 16 gt 0 DAL lt 31 24 gt Note Modules that have been designed to latch the byte mask lines under all conditions work correctly with current Digital supplied VAXELN Ethernet device drivers Digital recommends that all future designs implement the selective byte mask latch as described above Selective byte mask latching is required by users who write Ethernet device drivers that place buffers on nonoctaword aligned boundaries or DAL lt 29 02 gt DAL lt 31 00 gt MLO 004426 1 LADDR 31 30 are asserted during octaword transfer cycles 5 6 Memory System Interface support continuous address buffer chaining without a 16 byte buffer at the end of each buffer 5 6 Data Parity Checking To monitor the data integrity of the DAL 31 00 bus parity bits are provided with each byte The parity bits are driven onto CSDP 3 0 during write cycles while the data is driven onto the DAL lt 31 00
234. ber that corresponds to the letter s position in the alphabet then subtract one from that number 4 46 FIRMWARE For example if the port you are using is 4 convert the third character B to 2 since B is the second letter of the alphabet subtract 1 which leaves 1 Take the following steps to build the new device name a Append a dash to the first two characters of the VMS device name the dd in the ddcu format b Append the digit obtained in step 3 to the resulting string Append another dash to the resulting string d Append the unit number which is the fourth and following digits of the VMS device name the in the format For example the device name TXB4 becomes TX 1 4 The device name 1 becomes TT 0 1 Do not append the colon character to the new device name Run the Network Control Program NCP as follows RUN 5 555 5 gt Use the NCP SET command to identify the 300 node name and address and to specify the new device name derived in step 4 and the file that DECnet must down line load to the rtVAX 300 when it makes a load request SET NODE name ADDRESS a n SERVICE CIRCUIT tt m n LOAD FILE file ext name The DECn amp name assigned to the 300 a n The DECnet address of the 300 tt m n The terminal name derived in step 3 file ext The name of the system image to be loaded to the rtVAX 300 For
235. bits wide therefore DAL 31 08 are ignored when accessing the console Console and Boot ROM Interface 6 3 6 1 2 Console State Machine When the address decoder has asserted CONE L the DUART is selected and the console state machine jumps to the WRITECYCI state if it is a console write cycle to the READCYCI state if it is a read ENBCONDATA and either the DUART RD or the WR input are asserted The state machine waits the appropriate number of wait states for the console read or write cycle synchronizes with the P3P4 signal and asserts IOREADY This sets the ready hold latch see Figure 6 10 and the RDY L input to the rtVAX 300 is asserted until the end of the access cyde The state machine then jumps to the FINISHUP1 to FINISHUP3 states These states are necessary to satisfy the 200 ns of deselect time required by the SCN 2681 DUART Refer to Figure 6 2 to see the console state machine sequences CAUTION The RDY L ERR L and CCTL L lines are tri stateable bidirectional lines These lines are pulled up by resistors inside the rtVAX 300 processor and must be driven by a tri stateable driver such as the 74 125 If these lines are driven by a standard TTL totem pole output the rtVAX 300 processor will not function 6 1 3 Console Interrupt Acknowledge Cycles Interrupt requests to the rtVAX 300 processor from the DUART are generated the IRQ lt 0 gt L line when the receive buffer is full or the transm
236. ble each set within the cache S2E Read write When set set 2 of the cache is enabled When cleared set 2 of the cache is disabled Cleared on power up by the negation of RST L SIE Read write When set set 1 of the cache is enabled When cleared set 1 of the cache is disabled Cleared on power up by the negation of RST L These bits are used selectively to enable or disable storing stream and D stream references in the cache ISE Read write When set stream memory space references are stored in cache if it is enabled when cleared they not stored in cache Cleared on power up by the negation of RST L DSE Read write When set D stream memory space references are stored in cache if it is enabled when cleared they are not stored in cache Cleared on power up by the negation of RST L Unused Always read as 1s Write wrong parity WWP Read write When set incorrect parity is stored in the internal cache whenever it is written When cleared correct parity is stored in the cache whenever the cache is written Cleared on power up by the negation of RST L continued on next page 3 36 Hardware Architecture Table 3 10 Cont Cache Disable Register Fields Data Bit Definition lt 00 gt Diagnostic mode DIA Read write When set the internal cache is in diagnostic mode and writes to the CADR will not cause the internal cache to be flushed When cleared the cache is in normal operating mode wri
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238. bus map contains 8192 registers that control the mapping of Q22 bus addresses into main memory Each register maps a page of the Q22 bus memory space into a page of main memory These registers are implemented a 32K byte block of I O space The local I O space address of each register was chosen so that register address bits 14 02 are identical to Q22 bus address bits 21 09 of the Q22 bus page that the register maps Figure 8 6 shows the format of the Q22 bus map registers QMRs Table 8 2 lists the register bits and their meanings Device Interfacing 8 13 Figure 8 6 Q22 bus Register 3130 2019 00 MLO 004469 Table 8 2 Q22 bus Map Register Bits Data Bit Meaning 31 Valid bit V Read write When a Q22 bus map register is selected by bits 21 09 of the Q22 bus address the Valid bit determines whether mapping is valid for that Q22 bus page If the Valid bit is set Q22 bus addresses within the page controlled by the register are mapped into the main memory page determined by bits 28 09 If the Valid bit is clear the Q22 bus interface does not respond to addresses within that page 30 20 Unused These bits must always read and be written as zero 19 00 A Address bits 28 09 Read write When a Q22 bus map register is selected by a Q22 bus address and if that register s Valid bit is set then these 20 bits are used as main memory address bits 28 09 Q22 bus address bits 08 00 are used
239. cal Specification Figure 2 4 rtVAX 300 Pin Layout GND lt 0 gt lt 2 gt lt 0 gt lt 2 gt reserved reserved reserved reserved reserved reserved reserved reserved reserved 2 4 1 Data and Address Bus 45V lt 1 gt lt 3 gt INTIM lt 1 gt BM lt 3 gt DMR 5V HLT blank keypin IRQ lt 1 gt IRQ lt 3 gt RDY 5V reserved XMT XMT RCV RCV COL COL reserved reserved OOOOOOOOOOOOOOO 1 49 View of Application Board Socket CLKIN CLK20 5V CSDP lt 0 gt CSDP lt 2 gt CSDP lt 4 gt 5V DAL lt 00 gt DAL lt 02 gt DAL lt 04 gt DAL lt 06 gt DAL lt 08 gt DAL lt 10 gt DAL lt 12 gt DAL lt 14 gt 5V DAL lt 16 gt DAL lt 18 gt DAL lt 20 gt DAL lt 22 gt DAL lt 24 gt DAL lt 26 gt DAL lt 28 gt DAL lt 30 gt 5V 0 CLKB GND CSDP lt 1 gt CSDP lt 3 gt DPE GND DAL lt 01 gt DAL lt 03 gt DAL lt 05 gt DAL lt 07 gt DAL lt 09 gt DAL lt 11 gt DAL lt 13 gt DAL lt 15 gt GND DAL lt 17 gt DAL lt 19 gt DAL lt 21 gt DAL lt 23 gt DAL lt 25 gt DAL lt 27 gt DAL lt 29 gt DAL lt 31 gt GND MLO 006378 The data and address lines DAL 31 00
240. captures the opcode of the instruction that was being read executed at the time of the machine check e 23 16 captures the internal state of the CVAX processor chip at the time of the machine check The four most significant bits are equal to 1111 and the four least significant bits contain highest priority software interrupt 3 07 Hardware Architecture 3 23 3 1 12 5 e lt 15 08 gt captures the state of CADR 07 00 at the time of the machine check See Section 3 3 2 5 for an interpretation of the contents of this register e 07 00 captures the state of the M SER 07 00 at the time of the machine check See Section 3 3 2 6 for an interpretation of the contents of this register Internal State Information 2 Internal state information 2 is divided into five fields The contents of these fields are described as follows e 31 24 captures the internal state of the CVAX processor chip at the time of the machine check This field contains SC register lt 7 0 gt e 23 16 captures the internal state of the CVAX processor chip at the time of the machine check The two most significant bits are equal to 11 binary and the six least significant bits contain state flags 5 02 e lt 15 gt captures the state of the VAX can t restart flag at the time of the machine check e 14 08 captures the internal state of the CVAX processor chip at the time of the machine check The three most significant bits
241. ch the address and status information Note BM 3 0 L must be latched during quadword and longword cycles must flow through during octaword access cydes During a DMA transfer the rtVAX 300 processor uses the assertion of AS L tolatch the DMA address which is used in a cache invalidate cyde when CCTL L is asserted Data Strobe DS L O Z This signal indicates that the DAL 31 00 and CSDP 3 0 L lines are free to receive data and parity information during a read cycle or that valid data is on the DAL lt 31 00 gt lines and valid parity on CSDP lt 3 0 gt L during a write cycle Byte Masks BM 3 02 L 0 2 These signals indicate which bytes of the DAL lines contain valid data as listed in Table 2 4 Table 2 4 Byte Masks Byte Mask Description Data Byte lt 0 gt Low byte of low word DAL 07 007 lt 1 gt 1 High byte of low word DAL 15 08 lt 2 gt Low byte of high word DAL 23 16 gt L High byte of high word DAL lt 31 24 gt For a read cyde byte masks indicate which bytes of the DAL lines must have data driven onto them for a write cycle they indicate which bytes of the DAL lines contain valid data Lines BM 3 0 L are valid when the AS L signal is asserted during quadword and longword access cycles Octaword transfer cycles require that these lines not be latched 2 14 Technical Specification Write Read WR L O Z This signa
242. change mode had bit 0 set A hard memory error occurred while the processor was trying to read an exception or interrupt vector An access violation or invalid translation occurred during the processing of a machine check An access violation or invalid translation occurred during the processing of an invalid kernel stack pointer exception A machine check occurred while the processor was trying to report a machine check A machine check occurred while the processor was trying to report a machine check PSL 26 24 5 on an interrupt or exception PSL 26 24 6 an interrupt or exception PSL 26 24 7 on an interrupt or exception PSL 26 247 5 REI PSL 26 24 6 on an REI PSL lt 26 24 gt 7 an REI Console memory corrupted continued on next page Table 4 2 Cont Firmware Error Messages 6 Description 22 22 ILL REF The requested reference would violate virtual memory protection the address is not mapped the reference is invalid in the specified address space or the value is invalid in the specified destination 23 23 ILL CMD The command string cannot be parsed 24 724 INV DGT The number has an invalid digit 25 25 LTL The command was too large for the console to buffer The message is issued only after the receipt of the terminating carriage return 26 26 ILL ADR The specified address falls outside the limits of the addressing spac
243. check DAL bus parity although proper parity is not required for 1 space reads if the DPE lineis deasserted If DAL parity generation and detection are not needed for the I O device drive the L line high during that device s read cycle 74F 657 parity transceiver can be used to generate and detect parity for 1 0 device Note that the odd bytes DAL lt 15 08 gt and DAL lt 31 24 gt have odd parity and that the even bytes DAL 07 00 and DAL lt 23 16 gt have even parity If the I O device is capable of DMA operations to the rtVAX 300 processor s external RAM memory the 1 0 device must generate the correct parity when writing to memory otherwise the rtVAX 300 detects DAL parity error when reading those modified memory locations Device Interfacing 8 3 8 2 rtVAX 300 Interrupt Structure 8 4 Most simple peripherals such as A D D A parallel and serial 1 devices can be directly mapped to a valid location of the rtVAX 300 processor s 1 0 space When the device requests service it asserts of the four lt 0 gt lines and waits for the rtVAX 300 to run an interrupt acknowledge cycle This interrupt acknowledge looks like a normal memory read cyde however the CSDP 4 07 L reads 1X011 indicating an external interrupt acknowledge The IPL of the device interrupt being serviced is placed on DAL 06 02 and AS L is asserted This IPL must then be decode
244. chnical Specification 2 35 to indicate octaword transfer The rtVAX 300 sends an address only of the initial longword preferred The address of all other associated addresses are implied and therefore are not transferred These addresses are generated by incrementing the count on address bits 2 and 3 2 The CSDP lt 4 0 gt L lines 1 111 write no unlock the BM lt 3 0 gt L lines are asserted as required and WR L is asserted 3 ThertVAX 300 asserts AS validating CSDP lt 4 0 gt L BM lt 3 0 gt L WR L and the address information on DAL 29 02 4 ThertVAX 300 drives the DAL lt 31 00 gt H lines with valid data places parity information on CSDP 3 0 L and CSDP 4 remains deasserted The rtVAX 300 then asserts DS L to indicate that the DAL lines contain valid data and L to indicate that CSDP lt 3 0 gt L contain valid parity information BM lt 3 0 gt L are changed as required with each assertion of DS L 5 ThertVAX 300 checks for a complete cyde once every microcyde starting at the second possible P1 rising edge External logic indicates that the cyde is complete by one of the following three responses a If no error occurs external logic asserts RDY L while ERR L is deasserted for each data transfer b If an error occurs on any longword external logic asserts ERR L with RDY L deasserted The rtVAX 300 continues the octaword write with BM 3 0 set to 1 and only then complet
245. clearing CSR5 01 and 5 5 lt 02 gt After the rtVAX 300 IPL is lowered below the Ethernet coprocessor level another interrupt will be delivered with the CSR5 lt 03 gt bit set Should the port driver clear all CSR5 set interrupt bits before the interrupt has been acknowledged the interrupt will be suppressed 3 6 4 Serial Interface The Ethernet coprocessor supports the full IEEE 802 3 frame encapsulation and media access control MAC The Ethernet coprocessor functions in a send and receive half duplex mode and is in either the transmit or receive mode The exception to this is when the Ethernet coprocessor is in one of its loopback modes which operate in full duplex 3 88 Hardware Architecture 3 6 4 4 Transmit Mode In transmit mode the Ethernet coprocessor initiates a DMA cyde to access data from the transmit buffer in rtVAX 300 memory to assemble a packet to be transmitted on the network It then adds a preamble and start frame delimiter SF D pattern to the beginning of the data calculates and appends a cydic redundancy check CRC value if enabled to the data to make the packet After the packet is assembled the Ethernet coprocessor waits for MAC to allow transmission on the network When transmission is enabled the Ethernet coprocessor serializes the data and sends it to the serial interface adapter SIA 3 6 4 2 Receive Mode In receive mode the decoded serial data and clock are fed to the Ethernet coprocessor f
246. cles do not reissue a bus cycle if they are retried Specifically if the retry occurs on a prefetch reference the operation may not be reissued because the processor may execute a branch operation before the prefetch can be retried In addition Ethernet controller cycles cannot be retried 6 The CVAX completes the cycle by deasserting DS L and AS 2 6 3 Quadword Transfer Read Cycle During a quadword transfer read cycle the CVAX reads two longwords from main memory A quadword transfer read requires at least three microcycles Each longword transfer may be increased in increments of one microcyde The sequence of events of a quadword transfer read is as follows 1 The CVAX transfers the physical address of the preferred longword onto the DAL 29 02 lines This address be aligned with either of the two longwords of the quadword DAL 02 indicates whether the upper or lower longword is transferred first DAL lt 31 30 gt H lines are set to 105 to indicate a quadword transfer The CVAX sends an address of only the initial longword preferred The address of the second associated longword cache fill is implied and therefore is not transferred External logic can generate the implied address simply by inverting bit 02 of the preferred address Technical Specification 2 27 2 BM lt 3 0 gt L and CSDP 4 0 L are asserted as required and WR L is negated 3 The CVAX asserts AS validating CSDP lt 4
247. coprocessor drives this value on the rtVAX 300 bus DAL lt 31 00 gt H pins DAL 31 16 lt 01 00 gt are set to 0 DAL lt 01 00 gt are ignored when CSRO is written and set to 1 when read 29 SA R W Sync Asynch This bit determines the Ethernet coprocessor operating mode when it is the bus master When this bit is set the Ethernet coprocessor operates as a synchronous device when clear as an asynchronous device continued on next page Hardware Architecture 3 49 Table 3 18 CSRO Bits Bit Name Access Description 31 30 IP R W Interrupt Priority ls the rtVAX 300 interrupt priority level at which the Ethernet coprocessor interrupts IP 00 14 01 15 10 16 11 17 3 6 1 2 Transmit Receive Polling Demands CSR1 CSR2 Figure 3 19 shows the format of both CSR1 and CSR2 Table 3 19 describes the CSR1 bit structure Table 3 20 describes the bit structure of CSR2 Figure 3 19 CSR1 CSR2 Format 31302928272625242322212019181716151413121110090807060504 03 02 0100 MLO 004417 Table 3 19 CSR1 Bits Bit Name Access Description 00 PD R W Transmit Polling Demand Checks the transmit list for frames to be transmitted The PD value is meaningless 3 50 Hardware Architecture Table 3 20 CSR2 Bits Bit Name Access Description 00 PD R W Receive Polling Demand Checks the receive list for receive descriptors to be acquired The PD value is meaningless
248. ctrical and Environmental Characteristics 1 Caution The pin face of the rtVAX 300 module has conductive components Design the mounting to provide positive control of at least 0 010 in clearance between these components of the 300 module and the application module A 2 Physical Electrical and Environmental Characteristics Figure A 1 rtVAX 300 Mechanical Drawing 2 540 mm lt 72 517 2 855 0 100 in la 68 580 mm yl 6 422 mm 2 700 0 255 lt 66 040 mm gt 2 600 6 422 0 255 Note All four holes are drilled S 5 and tapped for 4 40 screws Vcc CLKIN lt 1 gt CLK20 lt 3 gt NTIM CSDP lt 0 gt BM lt 1 gt CSDP lt 2 gt BM lt 3 gt CSDP lt 4 gt DMR Vec Vec DAL lt 00 gt 81 280 mm HLT DAL lt 02 gt i Cut for Keyin DAL lt 04 gt 3 200 in Boe DAL lt 06 gt RQ lt 3 gt DAL lt 08 gt RDY DAL lt 10 gt DS DAL lt 12 gt 104 140 mm as 5145 4 100 Reserved DAL 16 XMT DAL lt 18 gt XMT L lt 20 gt RCV L lt 22 gt 110 617 mm x lt gt 4 355 COL L lt 28 gt L lt 30 gt Vcc Top Component Side View Looking Through Heat Sink Y Y 78 994 mm 3 110 in 117 094 mm 4 61 7 874 mm 0 310 in 10 41
249. d 7 1 1 WSHOLVI 18 159 8 154505 d8dSdS h H td d Zd ld td d Zd ld d d Zd ld d d Zd ld d d Zd ld td d Zd ld td d Zd ld td d Zd ld td d Zd ld d d Zd ld H VXT1O Zd bd Ed Zd id bd Ed Zd id bd Ed Zd id bd Ed Zd id Ed Zd id bd Ed Zd id bd Ed Zd id bd Ed Zd id bd Ed Zd id bd Ed Zd id bd Ed Zd id Ed 26 900 O1W 001 avy Ley t cw ast L 1105136 2 984 6 lt gt 1 lt 0 gt v aor lt 1 lt gt a lt gt lt gt 5 1 158V5 i 02 lt gt K B Em d gt Hepudavxnw s 840 lt gt lt 2 gt 579 EST r uaav1 4 1 lt gt 2 atu H zudavwvud H eudavxnw 93 lt gt EEES ean Em 4 T esvowvud 2 ou lt gt 293 44 si udavi zz er lt 9 gt lt gt
250. d and the interrupting device must place a vector on DAL 15 02 and assert RDY L DAL 31 16 and DAL 01 are ignored however DAL 02L can be used to force the processor IPL to 1716 when asserted Thus if a device interrupts the rtVAX 300 by asserting lt 0 gt L the processor raises its IPL to 1416 If the vector that is driven onto DAL 15 00 is odd DAL 00 is set to 1 the rtVAX 300 raises its priority level to IPL 171g when executing the interrupt service routine It is now up to the interrupt service routine to lower the IPL of the rtVAX 300 so that other interrupt requests are not blocked Lines IRQ lt 3 0 gt L are level sensitive and the interrupting device can continue to assert the IRQ O L line until the interrupt service routine lowers the rtVAX 300 IPL level below the interrupt request IPL The rtVAX 300 does nct service interrupt requests of the same or lower IPL than the IPL at which the processor is now operating Therefore if a device requests an interrupt by asserting lt 1 gt L and the processor runs an interrupt acknowledge for that device the processor s IPL is raised to 1516 If the device continues to assert the lt 1 gt L line the processor does not acknowledge the second interrupt until the interrupt service routine lowers the processor s IPL below 1516 this prevents interrupt stacking and allows multiple devices to interrupt the processor by using the same interrupt request li
251. d during a 1 period following the reset Access during this period will result in a CP BUS timeout error Access to Ethernet coprocessor CSRs during the self test are permitted only CSR5 reads should be performed 3 6 3 2 Interrupts Various events generate interrupts CSR5 contains all the status bits that may cause an interrupt provided CSR6 lt 30 gt is set The port driver must clear the interrupt bits by writing a 1 to the bit position to enable further interrupts from the same source Interrupts are not queued and if the interrupting event recurs before the port driver has responded to it no additional interrupts are generated For example CSR5 lt 02 gt indicates that one or more frames were delivered to rtVAX 300 memory The port driver should scan all descriptors from its last recorded position up to the first description owned by the Ethernet coprocessor An interrupt is generated only once for simultaneous multiple interrupting events The port driver must scan CSR5 for the interrupt cause s The interrupt will not be regenerated unless a new interrupting event occurs after the rtVAX 300 acknowledged the previous one and provided the port driver cleared the appropriate CSR5 bit s For example 585 lt 01 gt and CSR5 lt 02 gt may both be set the rtVAX 300 acknowledges the interrupt and the port driver begins executing by reading CSR5 Now CSR5 lt 03 gt sets The port driver writes back its copy of CSR5
252. d of the cyde This results in a passive release of the interrupt Figure 2 14 illustrates interrupt acknowledge cyde timing 2 6 8 External IPR Cycles Section 2 6 8 1 and Section 2 6 8 2 discuss external IPR cydes 2 6 81 External IPR Read Cycle An external processor register read cyde is initiated when an MFPR move from processor register instruction reads a category 3 processor register Section 3 1 4 3 defines processor register categories The only IPR register that should be implemented externally is IPR 374g This is the reset register and any write to this register should reset all external devices Implementing any other IPR externally may cause future software incompatibilities The external processor register read cycle protocol is the same as that of a single transfer CPU read as shown in Figure 2 9 However CSDP lt 2 0 gt L reads 010 indicating an external IPR This requires at least two microcycles and can be extended in increments of one microcycle The sequence of events for an external processor register read cyde is as follows 1 The 300 transfers the processor register onto DAL 07 027 and DAL 31 30 are set to 015 to indicate longword transfer DAL lt 29 08 gt and DAL 1 07 are zero 2 BM lt 3 0 gt L are all asserted CSDP 2 0 read 0102 DAL lt 29 08 gt and DAL 10 01 are zero and WR L is unasserted 3 ThertVAX 300 asserts AS L
253. d by the address strobe synchronizer latch as shown in Figure 5 12 This is necessary because AS deasserts just before the rising edge of CLKA possibly causing the state machine to missequence By synchronizing AS with CLKB SYNCHAS deasserts after the rising edge of CLKA Note The setup time of the state machine must be met on all unmasked inputs to prevent missequencing During a memory access cyde SYNCHAS and SELRAM are asserted while IACKIPR is deasserted When these conditions are true and REFREQ is unasserted the memory controller state machine jumps to the STARTACCESS state and asserts RAS The row address has been latched by the DRAMs and the SELCOL line is asserted by the address MUX select latch when CLKA deasserts The column address of the first longword is placed on the DRAM address bus Next the controller ensures that the DS line is asserted and then asserts the ENBCAS signal If this is a write cyde ENBCAS is then deasserted and DRAMREADY is asserted The state of INVADDR 3 2 is incremented creating the DRAM column address for the next longword Next the state of INVADDR 3 2 is compared to LADDR 31 30 to determine if the last longword has been transferred If that was the last longword the state machine jumps to the FINISHUP state deasserts all outputs and waits the RAS precharge time before it allows another memory access 5 18 Memory System Interface Figure 5 4 Sample Design Memory Controll
254. d drives it on the ROM address bus to the boot and diagnostic ROMs the Network Interface address decode logic and the Network Interface address ROMs The ROM address decode logic decodes the address on the DAL bus to provide control signals for the ROMs and the boot register 2 5 2 Boot ROM The boot ROM contains the boot drivers self test diagnostics and console emulation program 1 also accesses the registers used by the Ethernet coprocessor and the registers used by the user provided console ports The boot register is a read only register that resides at address 2003FFEC The firmware reads this register on power up to determine the default boot device and whether or not to enable remote console and remote trigger For additional information on the boot ROM refer to Figure 3 14 Technical Specification 2 23 2 5 3 Programming User ROMs The system file generated by the VAXELN System Builder EBUIL D command is first down line loaded by using the network as the booting device on the rtVAX 300 target You can use the remote and local debuggers to debug the application software Once the application software is running correctly you should generate a new system file by selecting the ROM as the boot method and then run the resulting SYS file through the PROMLINK program to create a loadable file for the EPROM burner The ROMs are then inserted into the EPROM programmer programmed and then inserted into their correct sockets Th
255. de 2 4 4 Bus Retry Cycles External hardware can force the rtVAX 300 processor to retry the current bus cycle by asserting both RDY L and ERR L at the same time This has no effect on the current bus cycle and the data are transferred later when the is successfully retried Only longword and quadword processor access cydes can be retried octaword and Ethernet controller cycles cannot be retried 2 4 5 Status and Parity Control Signals Status and parity control signals are as follows Data Parity Enable DPE L 1 0 2 This signal controls the checking and generation of data parity During an rtVAX 300 read cycle or an interrupt acknowledge cycle is asserted by external logic to enable data parity checking by the rtVAX 300 During an rtVAX 300 write cycle the rtVAX 300 asserts DPE L to indicate to external logic that valid parity information is on CSDP lt 3 0 gt L Control Status and Data Parity CSDP lt 4 0 gt L 1 O Z These lines transfer cycle status and data parity information between the rtVAX 300 processor and external devices During the first part of the bus cycle CSDP 4 07 and WR L provide status information about the current bus cycle as listed in Table 2 5 CSDP 3 indicates the set in internal cache memory that is being allocated during a cacheable read operation and is undefined during all other bus cycles CSDP lt 3 gt L is asserted to specify set 1 and negated to specify set 2 Techn
256. digit depends on the status of the first digit This register is mapped to the word location 201FFFFE Figure 3 16 shows the layout of this register Table 3 15 describes its bit structure Table 3 16 is a LED Display chart Figure 3 16 LED Display Status Register 262524232221201918171615 BLANK LED B BLANK LED A 201FFFFC LED lt 0 gt MLO 004509 Table 3 15 LED Display Status Register Fields Bit Description BLANK LED B Blank or turn off the most significant LED display digit 1 means blank or disable this display digit O means to enable this display digit BLANK LED A Blank or turn off the least significant LED display digit 1 means blank or disable this display digit O means enable this display digit LED lt 3 0 gt The 4 bit binary hexadecimal code to be displayed on the most significant LED display Note that these signals are inverted LED lt 3 0 gt The 4 bit binary hexadecimal code to be displayed on the least significant LED display Note that these signals are inverted Hardware Architecture 3 45 Table 3 16 LED Display Chart LED lt 3 0 gt BLANK HEX code displayed 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 XX XX HO gt 00 UM m Blanked 3 6 Ethernet Coprocessor The Ethernet coprocessor supports the Ethernet interface to the rtVAX
257. ds that are to be transferred The 28 bit address provided by the rtVAX 300 on DAL lt 29 02 gt is a longword address that uniquely identifies one of 268 435 456 32 bit wide memory locations The rtVAX 300 provides four byte masks BM lt 3 0 gt L to facilitate byte accesses within 32 bit memory locations The rtVAX 300 imposes no restrictions on data alignment Any data item regardless of size may start at any memory address except the aligned operands of ADAWI and interlocked queue instructions Any rtVAX 300 read or write falls into one of the following categories byte access word access within a longword word access across longwords aligned longword access unaligned longword access Quadword and octaword accesses always occur on longword boundaries Byte accesses word accesses within a longword and aligned longword accesses require one bus cyde Word accesses that cross a longword boundary and unaligned longword accesses require two bus cydes Table 5 1 lists each transfer and the type and number of bus cycles required for the transfer Memory System Interface 5 3 Table 5 1 300 Data Transfer and Bus Cycle Types Number Data Transfer of Bytes Number of Bus Cycle Type Transferred Bus Cycles Type Byte 1 1 Longword Aligned word 2 1 Longword Unaligned word 2 2 Longword Aligned longword 4 1 Longword Unaligned longword 4 2 Longword Aligned quadword 8 1 Quadword Aligned octaword 16 1 Octaword 5 4 Cycle
258. e 27 27 VAL TOO LRG The specified value does not fit in the destination 28 28 SW CONF Switches conflict 29 29 UNK SW The switch is unrecognized 2A 72 UNK SYM The symbolic address in the Examine or Deposit command is unrecognized 2B 2B CHKSM The command or data checksum on the Xfer command is invalid 2C 2C HLTED The operator entered a Halt command 2D 2D FND ERR The FIND command failed to find the RPB or 64K bytes of good memory 2E 2E TMOUT During an Xfer command data failed to arrive in the expected time 2F 2F MEM ERR A parity or other memory error occurred 30 730 UNXINT Unexpected interrupt or exception For some interrupts this message is followed by the PC PSL and interrupt vector 83 BOOT SYS This is the bootstrapping message 84 FAIL This is the general failure message 85 RESTART SYS This is the restarting system software message 86 RMT TRGGR This is the remote trigger request message FIRMWARE 4 23 4 3 9 Console Device 4 3 10 The console program operates an optional attached terminal connected through a serial port The attached terminal may be an ASCII video terminal for example a VT 100 or 220 a host computer running special software The existence of a console is determined by the following test performed at power on e Check the physical address 20100000 for a nonexistent memory error timeout If a timeout occurs no console is available for use e SCN 26
259. e The action taken is indicated below 0 Restart if that fails boot if that fails halt 1 Restart if that fails boot if that fails halt 2 Boot if that fails halt 3 Halt This field is initialized upon power up reset to the value 2 BOOT before the user s initialization routine if any is called This field may be inspected and modified by using the SET SHOW HALT console commands At entry to the console this value is moved to the HLT ACT field except for externally generated halts continued on next page FIRMWARE 4 37 Table 4 7 Cont Console Mailbox Register Fields Field Description RIP BIP HLT ACT A 1 bit field that serves as the restart in progress flag The bit is set when the console attempts a restart If it is already set the restart attempt is abandoned an error message is displayed and a boot is attempted This field is deared at power on It is also cleared at entry to the Console halt program after any attempts at restart and or boot A 1 bit field that serves as the bootstrap in progress flag The bit is set when the console attempts a cold restart If the bit is already set the bootstrap attempt is abandoned an error message is displayed and the Console halt program is executed This field is deared at power on It is also cleared at entry to the Console halt program after any attempt to boot A 2 bit field that temporarily encodes the action
260. e Data Internal Cache Address Translation Cache Disable Register Memory System Error Register Boot Register Memory System Control Status Register LED Display Status Register Ethernet Coprocessor Block Diagram CSRO Format sus ER eS Eus CSRI CSR2 Format CSR3 CSRA Format CSRI Format iR ge Lads CSRO Format isse be vk CSR7 CSRO Format 5 10 Format c i ke CSR14Format gris Receive Descriptor Format Transmit Descriptor Format Setup Frame Descriptor Format Perfect Filtering Setup Frame Buffer Format Imperfect Filtering Setup Frame Buffer Format System ROM Format System ROM Part System ROM Set System Type Help Display User Boot Diagnostic ROM Console Mailbox Register CPMBX Offset 0016 DUART and Display Status Default Boot Device Register BOOTDEV 3 25 3 29 3 32 3 33 3 33 3 33 3 35 3 36 3 38 3 42 3 44 3 45 3 47 3 49 3 50 3 52 3 52 3 57 3 62 3 62 3 63 3 65 3 65 3 68 3 73 3 80 3 82 3 84 4 5 4 16 4 35 4 36 4 38 4 39 xiii xiv 4 10 4 11 5 1
261. e if the console DUART and secondary DUART are present and usable This field is initialized at every entry to the console program Figure 4 9 Default Boot Device Register BOOTDEV 07 06 05 04 03 02 01 00 MLO 004505 FIRMWARE 4 39 Table 4 9 Default Boot Device Register Fields Field Description lt 2 0 gt 4 40 FIRMWARE 3 bit field used to determine the default boot action of the rtVAX 300 when it executes a boot sequence This field is temporarily overridden by a BOOT command with an explicit device specified Possible field meanings are as follows BOOTDEV Device Boot Action 000 No boot performed system enters or remains in HALT mode 001 PRAO Boot from ROM in system memory space The firmware searches for a boot block starting at physical address 10000000 every 16K bytes until it finds the boot block or has reached the address 00 010 Boot from ROM in 1 space The firmware searches for a boot block starting at physical address 20200000 at each 512 byte boundary until it finds the boot block or has made 256 attempts 011 Boot from ROM in 1 0 space after copy The same action as the PRBO boot is taken except the contents of ROM are copied into RAM memory address before control is transferred and then control is transferred to the RAM copy 100 CSBO DECnet DDCMP boot The secondary DUART on the SCN 2681 is initialized to 1200 bps and
262. e location immediately preceding the last location referenced in an examine or deposit operation For references to physical or virtual memory spaces the location referenced is the last address minus the size of the last reference 1 for byte 2 for word 4 longword The following limited set of mnemonic addresses is supported ASTLVL AST level register CADR Cache disable register ESP Executive mode stack pointer ICCS Interval clock control register IPL Interrupt priority level register ISP Interrupt stack pointer KSP Kernel mode stack pointer FIRMWARE 4 13 MSER POBR POLR P1BR P1LR PCBB PC PSL R lt n gt SAVPC SAVPSL SBR SCBB SID SIRR SISR SLR SP SSP TBCHK TBIA TBIS USP Memory management enable register Memory system error register PO base register PO length register P1 base register P1 length register Process control block base address register Program counter Program status longword General register n a decimal number 0 through 15 Saved PC register read only ignored on write Saved PSL register read only ignored on write System base register System control block base register System identification register Software interrupt request register Software interrupt summary register System length register Stack pointer Supervisor mode stack pointer Translation buffer check register Translation invalidate all register Translation invalidate single register User
263. e longword write cydes To maintain CPU cache consistency it asserts CCTL L at the beginning of the write cyde to start a quadword cache invalidation cycle Cache invalidation cycles require a minimum of four microcycles therefore if CCTL L is asserted at the beginning of the cycle the memory system must add two wait states a total cycle time of 400 ns to the cycle by holding off the assertion of RDY L If CCTL L is not asserted at the beginning of the cycle this is a CPU longword write cycle and zero or 1 wait state 200 or 300 ns memory access can be applied 2 34 Technical Specification Figure 2 12 Single Transfer Write Cycle Timing CLKA P1 P3 P1 P3 P1 P3 CLKB P2 P4 P2 P4 P2 DS 8 WR ig PE RDY ERR MLO 004399 2 6 6 Octaword Transfer Write Cycle Figure 2 13 illustrates octaword transfer write cycle timing During an octaword transfer write the rtVAX 300 writes four consecutive longwords supplying the address of the first longword only An octaword transfer write cycle requires at least nine microcydes Only the Ethernet coprocessor initiates octaword transfer The sequence of events of an octaword transfer write is as follows 1 ThertVAX 300 transfers the physical address of the preferred longword onto the DAL lt 29 02 gt lines This address is always octaword aligned DAL 03 02 are always zero The DAL 31 30 lines are set to 115 Te
264. e operation of this state machine This signal is asserted by decode logic when the rtVAX 300 is trying to access the DRAM continued on next page Table 5 11 Memory Subsystem Sequencer State Machine PAL Pins Setting Comment Input 8 19 21 22 23 24 25 26 27 FINVADDR2 FINVADDR3 LADDR30 LADDR31 IRST IRESETVAX IREFREQ This pin is controlled by external decode logic connected to the CSDP lines of the rtVAX 300 The signal asserts when the rtVAX 300 is running an interrupt acknowledge cycle but is not asserted for a memory read cycle and must be checked to prevent this state machine from starting a memory access cycle when the rtVAX 300 is running an cycle This is the output enable of the sequencer This is tied to the INVADDR2 output of this state machine and used as an input for determining the address of the last longword transferred during multiple longword transfer cycles This is connected to the INVADDR3 output of this state machine and used as an input for determining the address of the last longword transferred during multiple longword transfer cycles This signal is the second most significant bit of the latched address of the rtVAX 300 When it is deasserted and LADDR 31 is asserted a quadword read cycle is taking place This signal is the most significant bit of the latched address of the rtVAX 300 When i
265. e used to set a flop that locks the memory subsystem to prevent auxiliary processors from accessing it with interlocked instructions The write unlock code could then be used to unlock memory by resetting that flop If the rtVAX 300 is the only device that can access system memory the lock and unlock 5 can be ignored Table 2 5 lists the cyde status symbols 5 4 Memory System Interface 5 5 Byte Mask Lines The data path of the rtVAX 300 is 32 bits wide Byte mask lines indicate which byte s the processor is accessing M emory is viewed as four parallel 8 bit banks each of which receives the longword address in parallel DAL 29 027 The address placed on DAL 29 02 is a longword address the byte masks are used to select the bytes within that longword that are being accessed Each bank reads or writes one byte of the data bus DAL 31 00 when that byte s byte mask signal is asserted as shown in Figure 5 1 Byte mask lines BM 3 0 L must be latched on longword and quadword cycles and flow through on octaword cycles they need be used only during write cycles During write cycles the byte masks must be used to select only the byte s in memory indicated by asserted byte masks If a byte with an unasserted byte mask is written to the data in that location will be corrupted Note Valid parity must be placed on each CSDP lt 3 0 gt L line during a read cycle regardless of the assertion of BM
266. e with DECwindows applications The rtVAX 300 is the minimal hardware that you apply by adding required memory O devices interrupt logic and peripheral chips in order to customize it to the specific application that you have designed You can also interface your own proprietary LSI VLSI custom integrated circuits to your design because the rtVAX 300 permits direct access to its microprocessor bus Intended Audience This book is intended for hardware and software technical personnel who design and program subsystems and hardware configurations based on the rtVAX 300 processor Readers should be familiar with the information presented in the VAX Architecture Reference M anual Document Structure This document consists of eight chapters and five appendixes Chapter 1 Overview of the 300 Processor provides brief descriptions of the central processor floating point accelerator Ethernet coprocessor system support functions and resident firmware e Chapter 2 Technical Specification provides a functional description of the rtVAX 300 and describes the minimum hardware configuration bus connections pin and signal descriptions memory 1 0 space map registers and bus cycles and protocols e Chapter Hardware Architecture contains more detailed information the central processor floating point accelerator cache memory hardware initialization console interface registers and Ethernet coprocessor X
267. ed in the VAX Architecture Reference Manual These registers are used for temporary storage as accumulators and as base and index registers for addressing These registers are denoted RO through R15 The bits of a register are numbered from the right 0 through 31 gt Certain of these registers have been assigned special meaning by the VAX architecture R15 is the program counter PC The PC contains the address of the next instruction byte of the program e R14 is the stack pointer SP The SP contains the address of the top of the processor defined stack e R13 the frame pointer FP The procedure call convention builds a data structure on the stack called a stack frame The FP contains the address of the base of this data structure e R12 is the argument pointer AP The procedure call convention uses a data structure called an argument list The AP contains the address of the base of this data structure Consult the VAX Architecture Reference Manual for more information on the operation and use of these registers Hardware Architecture 3 5 3 1 4 2 Processor Status Longword The processor status longword PSL is implemented as specified in the VAX Architecture Reference Manual which should be consulted for a detailed description of the operation of this register The PSL is saved on the stack when an exception or interrupt occurs and is saved in the process control block PCB on a process context sw
268. ee grounds AUI connector grounding requirements Two variants of the AUI cable exist old Ethernet compliant cables and 802 3 compliant cables The old Ethernet cable has a protective outer shield which is connected to the connector shell and pin 1 of the cable It may have shields on the individual twisted pairs which are also connected to pin 1 IEEE 802 3 cable has a protective outer shield which is connected to the connector shell only It also has inner shields on the twisted pairs If the shields have a common drain wire the cable is connected to pin 4 If the shields have individual drain wires they are connected to pins 1 4 8 11 and 14 It is the goal of the sample design to meet the funcional requirements of both cable types This is accomplished by connecting the connector shell to chassis ground with DC resistance not to exceed 20 and connecting pins 4 8 11 and 14 to logic ground at the station s AUI connector A jumper is used to configure the connection of pin 1 in Network Interconnect Interface the station When the jumper is installed pin 1 is connected to logic ground When the jumper is removed pin 1 is left floating The jumper must be installed when 802 3 AUI cables are used with the station The jumper must be removed if the station has an old Ethernet cable Stations should ship with the jumper installed This ensures that the implementation of the interface complies the IEEE
269. elected CSR6 lt 02 01 gt 0 29 28 Data Type M ust be 2 to indicate setup frame SDES2 30 16 BS Buffer Size Must be 128 SDES3 29 1 PA Physical Address Physical address of setup buffer Note Setup buffers must be word aligned 3 6 2 3 4 Perfect Filtering Setup Frame Buffer This section describes how the Ethernet coprocessor interprets a setup frame buffer when SDES1 lt 25 gt is clear The Ethernet coprocessor can store sixteen 48 bit Ethernet destination addresses It compares the addresses of any incoming frame to these and based on the status of Inverse Filtering flag SDES1 lt 26 gt rejects those that match if SDES1 lt 26 gt 0 e Match if SDES126 gt 1 The setup frame must always supply all 16 addresses Any mix of physical and multicast addresses can be used Unused addresses should be duplicates of one of the valid addresses The addresses are formatted as shown in Figure 3 31 Hardware Architecture 3 81 Figure 3 31 Perfect Filtering Setup Frame Buffer Format 31 16 15 0 bytes 3 0 PHYSICAL ADDRESS 00 lt INDIVIDUAL GROUP bit lt 7 4 gt PHYSICAL ADDRESS 01 Address lt 31 00 gt Address 47 32 PHYSICAL ADDRESS 02 XXXXXXXXXXXXXXX PHYSICAL ADDRESS 03 XXXXXXXXXXXXXXX PHYSICAL ADDRESS 04 XXXXXXXXXXXXXXX PHYSICAL ADDRESS 05 PHYSICAL ADDRESS 13 E XXXXXXXXXXXXXXX PHYSICAL_ADDRESS 14 L X
270. en the BOOT pins 2 0 L be connected as shown in Table 3 12 and the rtVAX 300 will boot from these ROMs 2 5 4 Network Interface Registers The Network Interface on the rtVAX 300 is programmed by reading from and writing to a set of 16 Ethernet coprocessor registers located from 20008000 to 2000803F In addition to the 16 registers the Ethernet ID ROM providing the physical network address for the rtVAX 300 is located from 20010000 to 2001007F For detailed information on programming the Ethernet coprocessor chip see Chapter 3 2 5 5 Board Level Initialization and Diagnostic ROMs I O space locations 20080000 through 200F FFFF are reserved for use by the board level initialization and diagnostic ROMs After the firmware finishes executing the processor CF PA and ROM self tests it checks for an external ROM mapped to 20080000 If the ROMs exist control is transferred to them They can then perform board level initialization and diagnostics define a new boot device and execute the RET instruction to return to the internal firmware for memory testing and bootstrapping If user boot diagnostic ROMs do not exist the rtVAX 300 resident firmware continues with memory tests and bootstrapping Chapter 4 provides further programming information 1 PROMLINK is a registered trademark of the DATA 1 Corporation 2 24 Technical Specification 2 6 Bus Cycles and Protocols The rtVAX 300 processor performs bus cycles when one
271. enever software changes a valid PTE for the system or current process region or a system PTE that maps any part of the current process page table all process pages mapped by the PTE must be invalidated in the translation buffer The entire translation buffer can be invalidated by using the MTPR instruction to write a 0 to IPR 57 TBIA 3 12 Hardware Architecture The translation buffer can checked to see if it contains a valid translation for a particular virtual page by using the MTPR instruction to write a virtual address within that page to 63 If the translation buffer contains a valid translation for the page the condition code V bit bit lt gt of the PSL is set Note The TBIS TBIA and TBCHK IPRs are write only The operation of a MFPR instruction from any of these registers is undefined 3 1 9 Exceptions and Interrupts Both exceptions and interrupts divert execution from the normal flow of control An exception is caused by the execution of the current instruction and is typically handled by the current process for example an arithmetic overflow an interrupt is caused by some activity outside the current process and typically transfers control outside the process for example an interrupt from an external hardware device The following events cause interrupts e HLT L nonmaskable PWRFL L IPL 1 16 e Interrupt from a peripheral device received IRQ lt 3 0 gt L
272. ent to drive the address bus of the DRAMs directly the 74F 258 multiplexer is chosen high current drivers such as the 74F 244 are needed to drive the high capacitance of the DRAM address bus The rtVAX 300 supports multiple longword memory access cycles During quadword and octaword transfer cycles the rtVAX 300 places only one longword address on the DAL bus at the beginning of the transfer The memory system must generate the correct number of longwords in the correct order The subsequent longword addresses are generated by adding the F86 XOR gates between the two lowest order column address inputs of the 74F 711 multiplexer The assertion of the other input of the two F86 gates will cause the associated column address bit to invert DAL lt 31 30 gt indicate the number of longwords to be transferred Table 5 4 lists the codes for DAL lt 31 30 gt and the number of longwords that to be transferred 1 Half the address equals 10 bits because the 1M bit DRAMs require 20 bits of addressing Memory System Interface 5 13 Figure 5 3 Sample Design DRAM Address Path mlo 004428 ps turnpage 5 14 Memory System Interface Table 5 4 Memory Read Cycle Selection DAL Longwords 31 30 Cycle Type Transferred 0 1 Longword read or write 1 1 0 Quadword read cyde CPU 2 1 1 Octaword read or write 4 cycle Ethernet The memory controller looks at LADDR 31 30 to see the transfer cyde type and subs
273. equently asserts IN VADDR 3 2 to generate the necessary longword addresses during multiple longword transfer cycles 5 9 5 4 DRAM Array The memory system for the rtVAX 300 must be 32 bits wide If parity memory is desired 4 bits must be added so that each byte has 1 parity bit Most are a single bit wide so 36 5 are needed to implement parity memory DRAM packs which are 8 or 9 bits wide could also be used Note During Ethernet controller read cydes proper parity must be generated CSDP 3 0 for each longword read if L is asserted The scheme that is used to satisfy multiple word transfers requires that the DRAMs support page mode access For example when quadword read cycle is performed the address of the preferred longword is first placed on the DAL 29 02 bus DAL lt 31 30 gt read 102 The rtVAX 300 then asserts AS and the address is latched by the address latches The row address ripples through the F711 MUX and appears on the DRAM address bus The decoder is asserting the SELRAM and deasserting the IACKIPR signal The memory controller now asserts RAS and the row address is latched into the DRAMs The address MUX select latch then asserts the SELCOL signal driving the column address onto the DRAM address bus Now the memory controller asserts ENBCAS waits for the access time of the DRAMs and asserts DRAM READY The first longword is now latched into
274. er to initiate the bootstrap process The listener processes a down line loaded system image DECnet assistance volunteer packet protocol 60 01 type 3 for the case where the console program has failed an attempt at booting over the Ethernet The listener is established when an initialization routine sets up a pointer in the scratch RAM area to the listener s starting address The initialization routine is established when the Ethernet subsystem self test passes and sets up the pointer in scratch RAM to the initialization routine s starting address The initialization routine is called by the UNJ AM routine or at power up time prior to the console program startup unless the MOP flag is set to 0 This routine establishes the Ethernet controller data structures transmit and receive descriptor rings data buffers and some scratch area for the listener to maintain pointers and counters If the protocol is one of those described above the listener code takes the appropriate action If the protocol is unsupported for example DECnet routing updates the packet is disregarded FIRMWARE 4 25 4 5 Startup Messages The console displays messages and menus some during power up and others when the operator issues commands at the console terminal The latter depend on entries in the console memory 4 5 1 Power On Display This display is intended to give a complete but abbreviated account of the results of the power on initializatio
275. er Boot Diagnostic ROM Sample D 7 D 8 User 0 test failed 1 test passed SIDE EFFECTS None board level test 9 argument block offsets offset Scratch address of scratch memory area failing address of longword to store failing pc if test fails expected data address of quadword that test can Store expected data if test fails actual data address of quadword that test can Store actual data if test fails flags board level test flags gt usrom share byte 300 usrom test 9 m lt gt ret return to caller Sbttl rtVAX 300 Board level Test 10 Boot Diagnostic ROM Sample Ne Ne Ne Se Se Ne Se Se Ne Ne Se Me Ne Ne Ne Ne Ne Me Ne Ne Se Ne Se Me Se Se Se Se Se 5e e FUNCTIONAL DESCRIPTION This routine user supplied is called by the rtVAX 300 s resident firmware at system power on to do board level test 10 is called at IPL 31 in kernel mode with memory management disabled CALLING SEQUENCE calls 3005 usrom test 10 INPUT PARAMETERS scratch address of scratch memory area failing pc address of longword to store failing pc expected data address of quadword to store expected data actual data address of quadword to store actual data flags test flags IMPLICIT INPUTS None OUTPUT PARAMETERS r0 test results IMPLICIT OUTPUTS
276. er Sequence DRAMREADY ENBCAS IDLE REFCYC INVADDR1 INVADDR2 REFREQ RST Yes STARTREFRESHL_ STARTACCESS READ ACCESS 1 ENBCAS DRAMREADY REFRESHCYC RAS No ENDREFRESH ENBCAS 9 es READCYC2 DRAMREADY ENBCAS WRITECYCIL ENBCAS DRAMREADY FLAG FINISHUP INVADDR2 INVADDR3 ENBCAS RAS DRAMREADY REFCYC WRITECYC2 DRAMREADY m MEMORY ACCESS SYNCHAS amp IACK amp SELRAM WRITE ACCESS P4 amp LWRITE READ ACCESS 1 4 8 ILWRITE amp IFLAG DS EQUI INVADDR2 INVADDR3 LADDR lt 30 gt amp ILADDR 31 2002 INVADDR2 amp INVADDRS ILADDR 30 amp LADDR lt 31 gt EQU3 INVADDR2 8 INVADDRS amp ILADDR 30 amp ILADDR 31 EQU4 INVADDR2 amp INVADDR3 amp LADDR lt 30 gt amp LADDR lt 31 gt INVADDR2 IINVADDR2 WRITECYC4 DRAMREADY ENBCAS INVADDRS IINVADDR2 amp INVADDR3 INVADDR2 8 INVADDR3 MLO 006387 If another longword is required and it is a write cycle LWRITE is asserted the state machine jumps to WRITECYC2 and deasserts DRAMREADY The state machine then waits for DS to deassert and jumps to WRITECYC3 Once Memory System Interface 5 19 5 20 DS asserts the state machine jumps to WRITECY and asserts ENBCAS and DRAMREADY
277. eration to an error handler routine This action prevents the rtVAX 300 processor from stalling when a read or write request is directed to a nonexistent 1 0 device or memory location Memory System Interface 5 10 Memory Timing Considerations 5 10 1 The memory subsystem of the rtVAX 300 must satisfy some special timing requirements Table A 3 lists these requirements Note The rtVAX 300 read and write timing specifications must be followed explicitly Any timing parameter that is not within specification can cause intermittent or complete memory system failure The PLU S405 45 logic sequencer controls the timing of all the memory control signals This sequencer is clocked on the rising edge of CLKA therefore all outputs of the state machine will change 12 ns after the rising edge of CLKA Calculating Memory Access Time The rtVAX 300 accommodates slower memory and peripherals by providing the RDY L input The accessed peripheral can add any number of wait states into the access cyde by holding off the assertion of RDY L Each wait state is one microcycle long the processor will wait up to 32 us until it times out When calculating the speed of the memory elements first determine the number of wait states If you are operating with one wait state data must be valid 28 ns before the second rising P1 edge The access time of the DRAMs is specified from the time that the RAS lineis asserted The sample memory controller w
278. errupt request line 1 IPL 1516 is daisy chained to the user through the Ethernet coprocessor giving the Ethernet controller a higher priority than devices connected to this line Interrupt acknowledge cycles responding to the Ethernet coprocessor are marked as internal cycles and are indicated by the assertion of CSDP 4 Hardware external to the rtVAX 300 processor should ignore such cycles 2 1 7 DMA Structure The rtVAX 300 processor issues a DMA grant signal that is daisy chained to the user through the Ethernet coprocessor giving the Ethernet controller the highest DMA priority The rtVAX 300 processor relinquishes the bus once it grants DMA control to the user hardware However the rtVAX 300 processor monitors the AS line the CCTL line and the DAL lines to invalidate the appropriate cache entries during DMA write cycles if the CCTL line is asserted Note A device should not hold the rtVAX 300 bus for more than 6 us If such a device requires the bus for a longer time it should relinquish the rtVAX 300 DAL lines by deasserting DMR L and request it again 2 1 8 Interval Timer The interval timer generates a 5096 duty cycle 100 Hz TTL square wave This signal interrupts the CVAX once every 10 ms for VAXELN system dock updates 2 4 Technical Specification 2 1 9 Internal Cache The CVAX has a 1K byte write through cache as part of the CVAX chip Chapter 3 describes the organization of this cache
279. erted and the refresh is complete An external refresh address counter whose outputs are multiplexed to the DRAMs address lines must be added if the chosen DRAMs do not support CAS before RAS refresh 5 12 Memory System Interface 5 9 4 DRAM Row and Column Address Multiplexer DRAMs have multiplexed row and column address bus This means that half of the address of any bit is driven onto the DRAM address bus at one time For example to read one cell within the DRAM half of the address of that bit is driven onto the DRAM address bus Next the RAS is asserted and the second half of the address 10 bits is driven onto the DRAM address bus Next the CAS is asserted and the output driver is turned on After the DRAM access time delay data that is stored in the addressed cell is driven at the DRAM 5 data output Once the data has been transferred to the processor the RAS and CAS lines are deasserted and the 5 output is tri stated RAS must remain deasserted briefly to allow for internal DRAM precharging A multiplexer such as the 74F 711 shown in Figure 5 3 is needed to multiplex the row and column address onto the DRAM address bus Because the address bus of each DRAM is connected to the output of this multiplexer high current output drivers are needed to drive the high capacitive inputs of the DRAMs This will prevent excessive propagation delay The 74F 711 multiplexers provide sufficient drive curr
280. erved 1 blkb 28 reserved area 30051 usrom board init blkl 1 address of board level init 300 1 usrom test 8 blkl 1 address of board level test 8 300 1 usrom test 9 blkl 1 address of board level test 9 30051 usrom test 10 blkl 1 address of board level test 10 30051 usrom test 11 blkl 1 address of board level test 11 30051 usrom test 12 blkl 1 address of board level test 12 30051 usrom test 13 blkl 1 address of board level test 13 300 1 usrom test 14 blkl 1 address of board level test 14 300 1 usrom reserved 2 blkb 4 reserved area 300 1 usrom shared blkb 0 start of board level init and diagnostic testing code data fend _300Susrom User Boot Diagnostic ROM Sample D 3 LOCAL STORAGE rtVAX 300 user boot diagnostic rom entry points psect usromSycode rd nowrt quad 300 al usrom vector long x0003101 reserved byte 00 01 02 03 rom index numbers byte 02 02 02 02 reserved quad 0 reserved quad 0 reserved mbz assume lt 300 al usrom vec address _ 300 u assume lt 300 address 3005 assume lt 3 address 3005 assume lt 300 address _ 3005 usrom vec u 5 u 5 u assume lt _3005 0050 5 u 5 u 5 u l usrom vec 3 lt 0 S a S a S a rom vec srom test 10 vt al usrom vec address 300 us assume lt 3 a address 300 us assume 3005 address 300 usrom test 13 assume lt 3
281. erved for use these external self test routines When control is passed to the test in ROM the high digit of the LED status register is set to a value in the range of 1 through 7 to indicate the test number and the low digit is set to Fis The user s test code must change the value from the starting value to indicate progress through the user s subtests Normally the subtests count the lowest digit down from 16 to 016 The high order digit should always indicate the same value to make failure codes unique The return status of each test is placed in register RO Return status meanings are as follows 1 Test passed successfully 0 Device under test failed the test e 1 Device being tested is not present You can write simple test routines down line load their executable files EXE to the rtVAX 300 and run them 4 9 2 Writing Test Programs You write test routines in VAX MACRO or in any other programming language that does not call the runtime library RTL You compile them and link them to create an executable EXE file by using the SY STEM and HEADER qualifiers as in the following VAX MACRO code sample 5 MACRO LIST TEST MAR LINK SYSTEM HEADER TEST OBJ 4 44 FIRMWARE The HEADER information which contains the starting address of the executable code is automatically attached to the beginning of the EXE file The rtVAX 3005 built in maintenance operation protocol M OP loads the executable fi
282. es the cycle c External logic cannot request a retry of the cycle octaword transfer reads 6 ThertVAX 300 completes the cycle by deasserting DS and AS 2 6 7 Interrupt Acknowledge Cycle An interrupt acknowledge cyde sequence is similar to a single transfer read cycle The sequence of events follows During the address portion of the DAL 06 02 transfers the IPL of the interrupt being acknowledged The DAL lt 31 30 gt lines are set to 015 and the DAL lt 29 07 gt and DAL 01 00 lines are set to 0 2 36 Technical Specification Figure 2 13 Octaword Transfer Write Cycle Timing ML O 004400 ps turnpage Technical Specification 2 37 2 During the data portion of the external logic should transfer vector information on the DAL lines Lines DAL 15 02 contain the vector offset within the system control block The new processor status longword priority level is determined either by the external interrupt request level that caused the interrupt by DAL lt 00 gt If DAL lt 00 gt is 0 the new IPL is determined by the interrupt being serviced otherwise the new IPL is changed to 1716 Lines DAL lt 31 16 gt and DAL lt 01 gt are ignored 3 Assertion of ERR L and RDY L in the proper sequence causes the rtVAX 300 to abort or retry the abort or a data parity error causes the rtVAX 300 to ignore the data being read and to release the bus at the en
283. es the technical information necessary to design a RAM memory system for the rtVAX 300 processor A 4M byte DRAM memory array and controller design is presented as an example Design illustrations are induded at the end of this chapter This chapter discusses the following topics Memory speed and performance Section 5 1 e Static and dynamic RAMs Section 5 2 Basic memory interface Section 5 3 Cycle status codes Section 5 4 Byte mask lines Section 5 5 Data parity checking Section 5 6 e nternal cache control Section 5 7 Memory management unit Section 5 8 Memory system design example Section 5 9 Memory timing considerations Section 5 10 e Memory system illustrations and programmable array logic Section 5 11 5 1 Memory Speed and Performance The system performance of the rtVAX 300 system is linked to the performance of the memory system Most bus cycles are used to access memory because memory contains both the application instructions and data that the rtVAX 300 is processing Memory System Interface 5 1 turn the rtVAX 300 memory system performance depends the speed access time of the RAM memory devices used general the cost of memory devices is directly proportional to their speed and size Static RAMs generally provide the fastest access time however they are more costly and less dense than dynamic RAMs DRAMs The memory system speed must be weighed against
284. escriptor and its associated buffer 3 70 Hardware Architecture Table 3 31 RDES 1 Fields Bit Name Descriptor 29 30 31 VT VA CA Virtual case of virtual addressing RDES1 lt 30 gt 1 indicates the type of virtual address translation When clear the buffer address RDES3 is interpreted as a SVAPTE System Virtual Address of the Page Table Entry When set the buffer address is interpreted as a PAPTE Physical Address of the Page Table Entry Meaningful only if 51 lt 30 gt is set Virtual Addressing When set RDES3 is interpreted as a virtual address The type of virtual address translation is determined by the 51 lt 29 gt bit The Ethernet coprocessor uses RDES3 and RDES2 lt 08 00 gt to perform virtual address translation process to obtain the physical address of the buffer When dear RDES3 is interpreted as the actual physical address of the buffer 30 29 Addressing Mode 0 Physical 1 0 Virtual SVAPTE 1 1 Virtual PAPTE Chain Address When set RDES3 is interpreted as another descriptor s VAX physical address This allows the Ethernet coprocessor to process multiple noncontiguous descriptor lists and explicitly chain the lists Note that contiguous descriptors are implicitly chained contrast to what is done for a Rx buffer descriptor the Ethernet coprocessor clears neither the ownership bit RDESO lt 31 gt nor any other bit of RD
285. eset hold flop stores a 1 and the RST L line is deasserted by the rese latch The reset assertion time and deassertion timing in the specifications must be followed exactly RST L can deassert only 10 ns after or 20 ns before any CLKA edge If this timing is violated the rtVAX 300 does not initialize properly The RST L line can be asserted at any time wb R8 1K 1 RESETVAX 1 2 2 R3 R5 100K 470 1 1 1 AS 2 1 2 1 R7 25 MLO 004473 Device Interfacing 8 25 8 7 Halting Processor The rtVAX 300 is a dynamic device and cannot be halted by disabling its clock input CLKIN The CPU is halted either by executing the HALT instruction in kernel mode or by asserting the HLT L signal When in the HALT position the RUN HALT switch S1 sets a flip flop which asserts the HLT L output to the rtVAX 300 processor as shown in Figure 8 11 This causes the rtVAX 300 to enter a halt routine and to store the content of certain rtVAX 300 registers This is a momentary contact switch that is normally in the RUN position Figure 8 11 Device Interfacing HALT Logic 5V s2 Run 2 1 R6 2K 2 1 R11 2K 1 R34 2K 2 HLTREQ L 3 Halt 8 26 Device Interfacing MLO 006395 8 8 I O System Illustrations The following pages show 1 0 system illustrations and programmable array
286. ess lines of the DRAM This line is asserted only during the quadword hexword and octaword read The assertion of this signal inverts the LADDR 2 gt bit of the column address which is then driven onto the address lines of the DRAM This line is asserted only during the quadword hexword and octaword read cycles This output controls assertion of the RDY L line to signal that valid data is on the DAL lines and that the cycle should end You define the internal state bits and assign a state name for each bit pattern as follows In addition all illegal states are defined so as to prevent the machine from accidentally hanging All illegal states next state to the idle state 5 44 Memory System Interface NODE STATEO STATE1 STATE2 STATE3 FLAG STATEO CKMUX E STATEl CKMUX STATE2 CKMUX STATE3 CKMUX FLAG CKMUX REFCYC CKMUX DRAMREADY CKMUX INVADDR2 CKMUX INVADDR3 CKMUX RAS CKMUX CLKA ENBCAS CKMUX CLKA OO OO E we FIELD MEMORY STATE3 STATE2 STATE1 STATEO SDEFINE IDLE 0000 SDEFINE STARTACCESS 8 0100 SDEFINE ACCESSCYC 0110 SDEFINE READCYC B 0010 SDEFINE WRITECYCI B 1110 SDEFINE WRITECYC2 B 1100 SDEFINE WRITECYC3 B 0111 SDEFINE STARTREFRESH B 1000 SDEFINE REFRESHCYC B 1001 SDEFINE ENDREFRESH B 1011 SDEFINE FINISHUP B 000 SDEFINE POWERUP B 1 SDEFINE ILLEGAL1_ B 00 SDEFINE ILLEGAL2 B 010 SDEFINE ILLEGAL3_ B 10
287. execution of MULL DIVL and EMUL integer instructions 3 2 2 Floating Point Accelerator Data Types The rtVAX 300 floating point accelerator supports byte word longword quadword F floating D floating and G floating data types TheH floating data type is not supported but may be implemented by macrocode emulation 3 3 Cache Memory To maximize CVAX processor performance the rtVAX 300 incorporates a 1K byte cache implemented within the CVAX chip 3 3 1 Cacheable References Any reference that can be stored by the internal cache is called a cacheable reference The internal cache stores CVAX processor read references to the memory space bit lt 29 gt of the physical address equals 0 only It does not cache I O space references DMA references external devices including the Ethernet coprocessor The type s of CVAX processor references that can be cached either request instruction stream I stream read references or demand data stream D stream read references other than read lock references is determined by the state of cache disable register lt 5 4 gt The normal operating mode is for both I stream and D stream references to be stored Whenever the CVAX processor generates a noncacheable reference a single longword reference of the same type is generated on the DAL bus Whenever the CVAX processor generates a cacheable reference stored in the internal cache no reference is generated on the DAL
288. f the first device This device drives a vector onto the DAL bus and drives RDY L if it was the device that was asserting lt 0 gt L However if the first device did not assert the IRQ 0 L signal it passes the interrupt acknowledge to the second device by asserting an interrupt acknowledge output signal This IACKOUT signal is then fed into the interrupt acknowledge input of the second device The second device can now drive the vector onto the DAL bus and assert RDY L If the second device did not assert the lt 0 gt signal and it receives the interrupt acknowledge input it should not drive the vector onto DAL lt 15 00 gt or assert RDY L ThertVAX 300 times out after 32 us and aborts the interrupt acknowledge cycle Aborted interrupt acknowledge cycles result in a passive release without a machine check Device Interfacing 8 5 Figure 8 3 Device Interfacing Interrupt Daisy Chain Block Diagram Device 1 CSDP lt 4 2 0 gt Device 2 DAL lt 6 2 gt IACK Decoder Device Interrupt Request Device Interrupt Request Open Collector IRQ lt 0 gt Driver MLO 004466 8 2 2 Interrupt Vector The interrupt vector generated by the interrupting device is used as an offset to locate an entry in the System Control Block SCB This entry is then read from the SCB to determine the virtual starting address of the interrupt service routine for that in
289. firmware 4 6 1 Power On Configuration Register Figure 3 14 shows this register which the firmware reads once 4 6 2 External I O Bus Reset Register When you connect the rtVAX 300 to a bus such as the VME bus it is useful for the rtVAX 300 to be able to reset that bus and its peripherals under program control The console Unjam command provides this facility because it writes to 3716 the I O bus reset register It is not implemented within the rtVAX 300 processor module H owever if you need an external bus reset signal external board level logic should decode the external internal processor register write cycle to 371g and assert the I O bus reset line when any write is performed to that register location Any user devices that may interrupt at IPL 1616 or 1716 must implement I ORESET and the device must disable all interrupts upon receiving ORESET There are no bit assignments for the external bus reset I O register The 1 0 bus reset should be performed after any write to IPR 3716 4 7 Diagnostic Test List Tests are listed in the order they are executed upon restart Tests are executed implicitly by a power up restart condition or explicitly by a console TEST nn command where nn is the hexadecimal test number Table 4 5 lists LED displayed test numbers and their meanings Each test has the following features e When called from the console it supports loop on test loop on error halt on error
290. g of a memory access cyde This address must be decoded by an address decoder to provide a select signal for the memory controller physical memory must be mapped at the lowest possible memory addresses Physical memory must also be contiguous and 32 bits wide Therefore if a 1M byte memory array was constructed it must be mapped to locations 00000000 through OOOF FF FF Full memory address decoding must be implemented to prevent multiple mapping of memory This is necessary because the firmware begins at location 00000000 and uses a binary search algorithm to ascertain the configuration of memory for sizing and initialization Nonexistent memory is detected when the memory controller does not assert the RDY L line The rtVAX 300 internal timer times out and the memory sizing finishes with the highest responsive location marked as the top of memory The stacks are set up and the rtVAX 300 is able to boot If full memory address decoding was not implemented the initialization firmware would find an invalid top of memory This would cause the stack to write over free process pages and the rtVAX 300 to fail when it tries to boot The decoder can be implemented in a registered PAL as shown in Figure 5 9 In this configuration DAL lt 29 22 gt H are fed into the inputs of the PAL For memory access all of these bits must be zero The PAL s internal flip flop latches the output of this decoder SELRAM at the rising edge of AS H The SELRAM
291. gaged from the Ethernet wire Frames from the transmit list are looped back to the receive list subject to address filtering 10 External ndicates that the Ethernet coprocessor is working in full duplex mode Frames from the transmit list are transmitted on the Ethernet wire and are looped back to the receive list subject to address filtering 11 Diagnostic Mode E xplained in Section 3 6 5 2 23 22 RS R Reception Process State I ndicates the current state of the reception process as follows Value Meaning 00 Stopped 01 Running 10 Suspended Section 3 6 4 2 explains the reception process operation and state transitions continued on next page Hardware Architecture 3 55 Table 3 22 CSR5 Bits Bit Name Access Description 2524 TS R 29 26 55 R 30 SF R 31 ID R Transmission Process State I ndicates the current state of the transmission process as follows Value Meaning 00 Stopped 01 Running 10 Suspended Section 3 6 4 1 explains the transmission process operation and state transitions Self Test Status T he self test completion code valid only if 5 5 lt 30 gt is set is as follows Value Meaning 0001 ROM error 0010 RAM error 0011 Address filter RAM error 0100 Transmit FIFO error 0101 Receive FIFO error 0110 Special Loopback error Note Self test takes 25 ms to complete Self Test Failed When set indicates that t
292. ge frame number for the address that the 1 device generates Device Interfacing 8 9 Figure 8 4 Device Interfacing Read Cycle Timing ML O 004467 ps turnpage 8 10 Device Interfacing For example the Q22 bus supports 22 bits of addressing and multiple bus masters The bottom 9 bits of the Q22 bus are directly multiplexed onto the rtVAX 300 system memory address Bus address bits 08 02 are multiplexed onto DAL 08 02 and bus address bits 01 00 control BM 3 0 to access the correct byte of VAX memory The upper 13 bits of the Q22 bus address are used to select one entry in the S G map That entry in the S G map then contains the 20 bits of possible pages in memory space to define the PFN In addition a Valid bit bit 31 for each entry ensures that the operating system has correctly updated each map entry Thus the S G map consists of 8192 Q22 bus mapping registers OM Rs each being 21 bits wide The operating system dynamically updates each entry in the S G map as pages of the I O bus are mapped into physical pages of the rtVAX 300 system RAM The rtVAX 300 views the S G map as 8192 longword registers each register maps one page of Q22 bus memory to a page in the rtVAX 300 system RAM Figure 8 5 shows the translation from Q22 bus addresses to physical memory addresses Device Interfacing 8 11 Figure 8 5 Q22 bus to Main Memory Address Translation Q22 bus Address 21 9 8 0 Map
293. gt 1 0 3r 1 lt Zt N 6i VIVdWOH Zi sw 3 3 SPVIVOWOH 81 H ee Wa 9 lt gt 8i a lt 5 1 6i Pra lt 61 Na lt gt 02 663 lt 22 71 02 lt Z gt VLVGWOU 12 v c v1VQWOH 12 ow 290 973 1290 673 a5 2 2 q 2 d L lt 0 gt 6d 6I 22 lt 0 gt tos 5 2 ov LNdLNOINS 0 32 1 QV3HNOH lt gt 0 zi lt 5 zi H z udaavi IV L 1 H e dudavi LV LL H lt gt LA 01 gt D Er H lt gt 00 1 lt 6 gt 1 0 3r 6 H lt H se 2 6 lt 8 H 92H V 8 H lt 9 gt a Cs 2 H lt gt C o Hea H lt 9 H lt gt 3 tv S lt 6 gt 1 tv S H lt 6 gt HAAYI A 8 92 012 92 lt OL gt H UN lt gt H lt 22 lt gt mx 1 62 1560051
294. gt 4060 T lt gt 1 02a 1 LIHXVASN3 m 9 7 1 lt 124 55 7 4459 Ag 1 098 al 2113 lt 6 gt 1008 1 lt 2 gt 1009 OL 4 gi NH 113H6 8912 Yun 0215 Ag 19 gt 1 08 1 0 gt 100 AG VO 2 NIMTO 6 ims 8 le e Hur YOUMS vr 8 lt AZS E 5 09 00 2 2 388 JOJOBUUOD S o 45V 45V 45V 45V 45V MLO 004494
295. gword are checked on read references that hit the internal cache but only tag parity is checked on CPU and DMA write references that hit the internal cache Hardware Architecture 3 39 The action taken following the detection of an internal cache parity error depends on the reference type e During a demand D stream read reference the entire internal cache is flushed the CADR is deared which disables the first level cache and causes the second level cache to ignore all read operations The cause of the error is logged in MSER 4 0 and a machine check abort is initiated e During a request I stream read reference the entire internal cache is flushed unless 0 is set the cause of the error is logged MSER 1 05 the prefetch is halted but no machine check abort occurs and both caches remain enabled During a masked or nonmasked write reference the entire internal cache is flushed unless CADR 0 is set the cause of the error is logged MSER 0 only tag parity is checked CVAX processor writes that hit the internal cache there is no effect on CVAX processor execution and both caches remain enabled During a DMA write reference the cause of the error is logged in MSER 0 only tag parity is checked on DMA writes that hit the internal cache there is no effect on CVAX processor execution both caches remain enabled and invalidate operation occurs 3 4 Hardware Initialization
296. h index crc address amp address 0 update the hash filter setup frame hash 1 gt gt 3 1 lt lt hash index 8 continued on next page E 2 Sample C Program to Build Setup Frame Buffer Example 1 Hash Filtering Setup Frame Buffer Creation C Program else physical address if physical cnt for 150 i 6 i setup 6411 address i physical continue send a warning message if no or more than one physical addresses have been found Ey if physical cnt printf nWarning 55 does not contain a physical address n n argv 1 else if physical cnt 1 printf nWarning 5 contains more than one 39 physical address n n argv 1 physical cnt store the setup buffer in the specified out file if argc gt 3 for 150 i 18 itt fprintf fout 02X 02X 02X 02X n setup frame i 443 setup frame i 4 42 setup frame i 441 setup frame i 4 else for 150 i 18 1 printf 02X 02X 02X 02X n setup_frame i 4 3 setup_frame 1i 4 2 setup_frame i 4 1 setup_frame i 4 fclose fin fclose fout int crc address addr char addr continued on next page Sample C Program to Build Setup Frame Buffer 3 Example E 1 Hash Filtering Setup Frame Buffer Creation C Program int 0 unsigned char mean crc 33 Init CRC to all 175 for 150 1 l
297. he Ethernet coprocessor self test has failed The self test completion code bits indicate the failure type Initialization Done When set indicates that the Ethernet coprocessor has completed the initialization reset and self test sequences and is ready for further commands When dear indicates that the Ethernet coprocessor is performing the initialization sequence and ignoring all commands After the initialization sequence completes the transmission and reception processes are in the stopped state 3 56 Hardware Architecture 3 61 5 Command and Mode Register CSR6 This register is used to establish operating modes and for port driver commands Figure 3 22 shows the format of CSR6 Table 3 23 describes its bit structure Figure 3 22 CSR6 Format 31302928 2524 21201918 1615 121110090807060504 03 02 0100 B S 8 MLO 004420 Table 3 23 CSR6 Bits Bit Name Access Description 2 1 AF R W Address Filtering mode Defines the way incoming frames will be address filtered Value Meaning 00 Normal Incoming frames will be filtered according to the values of the SDES1 lt 25 gt and SDES1 lt 26 gt bits of the setup frame descriptor 01 Promiscuous incoming frames will be passed to the rtVAX 300 regardless of the SDES1 lt 25 gt bit value 10 All Multicast All incoming frames with Multicast destination addresses will be passed to the rtVAX 300 Incoming frames with individual destinatio
298. he rtVAX 300 memory by using DMA cycles Once the program has been loaded into the DSP s RAM the DSP executes the loaded program from this program RAM at location 400046 Since full address decoding was not implemented the ROM maps four times in the program space and the RAM maps eight times in the data space and four times in the program space Device Interfacing 8 17 8 5 2 4 Words of DSP Private RAM When the DSP reads data from external memory it first places the address on the DSPADDR address bus Either the program strobe PS signal for access to program memory or the data strobe DS signal for access to data memory is asserted The DSPWRITE signal is not asserted read cyde The DSP MEMORY PAL see Figure 8 28 looks at the SRAMADDR lt 0 gt line to determine if bank 0 or bank 1 is selected If bank 0 is selected the CSRAMO line is asserted and the two SRAMs in bank 0 are selected Both WRITERAM 1 0 signals remain unasserted Next the DSP asserts the DSPSTRB signal enabling all SRAM outputs The DSPREADY signal is asserted by the DSP MEMORY PAL and the DSP reads the data and ends the Write cycles operate in the same manner however the WRITESRAM 1 0 signals assert with DSPSTRB for the selected bank The DSP requires the use of 40 ns static RAMs to operate without any wait states The propagation delay of the 5 MEMORY PAL must be added to the access time therefore 25 ns SRAMs were used 8 5 3 D
299. his case ROM access time 2300 ns 50 ns 27 ns 28 ns 6ns 5ns 284 ns 1 100 72 28 0 ns according to the rtVAX 300 specifications Console and Boot ROM Interface Figure 6 6 Sample Design Address Decoder Address Decoder PAL Includes latch 1B Note Socket used here G74 CPUST L 432 Decode PAL UPCONE L p CONEL UPCPUSTL F32 SELROMH NC Cycle Reset PAL LOWCONE L LOWCPUST L CONIACK L 20 NC Cycle Reset DAL 23 22 DAL 21 20 DAL lt 19 gt DAL lt 18 gt DAL lt 6 gt DAL lt 17 gt DAL 5 H DAL lt 16 gt DAL lt 4 gt H 10 DAL lt 15 gt DAL 3 DAL lt 14 gt DAL 2 DAL lt 13 gt CSDP lt 4 gt L 50 lt 2 gt L ASH 5 lt 1 gt 5 lt 0 gt L DAL lt 24 gt WRL DAL 25 DSL DAL 26 lt 27 gt DAL 28 DAL 29 lt 7 gt DAL 8 H DAL 9 DAL 10 DAL lt 11 gt H DAL lt 12 gt Note The rtVAX 300 uses CMOS ACTQ245 drivers for the DAL lines and ACTQ244 drivers for the control lines These drivers have very fast rise and fall times which can generate a fair amount of undershoot and overshoot Some PAL devices and RAM chips may malfunction when exposed to excessive overshoot and undershoot It may be necessary to isolate these devices from the rtVAX 300 signal lines with TTL buffers or
300. hitecture 3 21 Error Description 9 A hardware interrupt was requested at an unused IPL e Microcode errors indicate that the microcode detected an impossible situation during instruction execution Note that most erroneous branches in the CVAX processor microcode cause random microinstructions to be executed The most likely cause of this type of machine check is a problem internal to the CVAX chip Machine checks due to microcode errors are nonrecoverable Depending on the current mode either the current process or the operating system should be terminated Error Description A An impossible state was detected during an MOVC3 or MOVC5 instruction not move forward move backward or fill Readerrors indicate that an error was detected when the CVAX processor tried to read from the internal cache main memory or an external 1 0 device The most likely cause of this type of machine check must be determined from the state of the MSER Machine checks due to read errors may be recoverable depending on the state of the VAX can t restart flag captured in internal state information 2 lt 15 gt and the first part done flag captured in PSL lt 27 gt If the first part done flag 15 set the error is recoverable If the first part done flag is cleared then the VAX can t restart flag must also be cleared for the error to be recoverable otherwise the error is unrecoverable and depending on the curren
301. ical Specification 2 17 Table 2 5 rtVAX 300 Bus Status Signals CSDP WRL 4L 2L lt gt 01 Bus Cycle H H L L L Request D stream read H H L L H Reserved H H L H L External IPR read H H L H H External interrupt acknowledge H H H L L Request stream read H H H L H Demand D stream read lock H H H H L Demand D stream read modify intent H H H H H Demand D stream read no lock or modify intent L H L L L Reserved L H L L H Reserved L H L H L External IPR write L H L H H Reserved for use by DMA devices L H H L L Reserved E H H L H Write unlock L H H H L Reserved L H H H H Write no unlock X L X X X Reserved rtVAX 300 internal interrupt acknowledge cycle only During the second part of the bus cycle the CSDP lt 3 0 gt L lines are used to transfer byte parity information for the DAL line data during a read or write cycle During the read the rtVAX 300 processor checks parity on all four bytes regardless of the assertion of the BM 3 02 signals On a write cycle the rtVAX 300 generates data parity on the CSDP lt 3 0 gt L lines 2 18 Technical Specification 2 4 6 Interrupt Control IRQ lt 3 0 gt L lines are asynchronous interrupt request lines External logic uses them to indicate interrupt requests to the CVAX The rtVAX 300 samples the lines every microcyde and they must stay asserted until the end of the interrupt acknowledge cycle Although the rtVAX 300 proces
302. igure 7 2 shows the rtVAX 300 isolation transformer and jumpers 7 6 1 2 1 Transceiver Chip The five major transceiver functions are as follows Transmit The DP8392 chip takes a differential input output of the rtVAX 300 and drives a single ended AC signal onto the ThinWire Ethernet coaxial cable Receive A signal is received from the coaxial cable corrected for frequency distortion and driven to the rtVAX 300 on the receive differential pair The receiver has high input impedance and low input capacitance to minimize reflections and loading of the ThinWire coaxial cable The receiver squelch prevents noise on the coaxial cable from triggering the receiver At the end of reception the squelch also serves to prevent dribble bits Collision Detect A low pass filter extracts the average DC level on the coaxial cable and compares it to the collision threshold The collision threshold is met if more than one transmitter is simultaneously active on the coaxial cable The DP8392 chip signals the collision to the 300 by a 10 MHz signal on the collision differential pair Heartbeat Generator After each transmission the DP8392 chip sends a 10 MHz signal to the rtVAX 300 on the collision differential pair This tests the collision detection circuitry The heartbeat also called the SQE test may be disabled with the HE pin Network Interconnect Interface 7 7 Jabber Monitor The DP8392 monitors each transmission with
303. ill assert the RAS line 12 ns after the rising edge of P3 The RAS driver delay must also be added along with the 74F 374 latch delay thus the access time from RAS is as follows 3 0 x CLKA period Data setup time Memory controller delay RAS driver delay Latch delay Access time In this case access time 23 x 50 ns 28 ns 12 ns 5 ns 7 ns 98 ns Therefore during a read cyde with one wait state data must become valid 98 ns after the assertion of RAS Thus 98 ns or faster DRAMs used with this scheme allow the memory subsystem to operate with one wait state Memory System Interface 5 21 5 10 2 State Machine Input Setup Time In Figure 5 12 the PLUS405 45 state machine used as the memory controller requires 12 ns of setup time at each of its inputs The actual setup time on any of these inputs is calculated by adding the maximum propagation delay of each gate located between the source and the state machine input This sum is added to the delay of the source from the rising edge of CLKA For example the AS signal is asserted by the rtVAX 300 23 ns after the rising edge of CLKA when the processor is in the state The delay of the F00 gate in the address strobe synchronizer 5 ns is added to 23 ns to yield 28 ns total delay from the rising edge of CLKA Because the cycle time of CLKA is 50 ns the setup time of SYNCHAS is 22 ns meeting the 12 ns requirement ThelACKIPR and SELRAM outputs of the 22V10 PAL
304. iming parameters for the DRAMs Section 2 6 discusses the values of these parameters addition the DRAMs have some critical timing parameters that must be met Table 5 7 lists these parameters Memory System Interface 5 23 01 FOR THE LONGWORD CYCLE AND 10 FOR QUADWORDS P1 P2 P2 P2 P2 P2 P2 P2 P2 Note LWRITE L IS DEASSERTED AND LADDR lt 31 30 gt Figure 5 5 Sample Design Memory Controller Longword Timing FINISHU ACCESSCYC 55 ACCESSCYC IDLE IDLE a E d ra s ae T N z a e a S ca pc cuc ui SNP Ede TRUE URGERE RE Toe lt Lab os N 8 amp a isr lt e an 6 Mi ds 6 Y p IIT Lad 9 dub msc ee mtt ceu oec Bl lt 5 N 5 d 1 axi oe ord sens er e Y al Eg a e N a o a Q Parse 5 n x Uc usu EST cerro a t e z a n lt T
305. ings single precision double and extended double precision floating point numbers The remaining data types are supported through software emulation This chapter discusses the following topics e Central processor Section 3 1 e Floating point accelerator Section 3 2 e Cache memory Section 3 3 e Hardware Initialization Section 3 4 e Console interface registers Section 3 5 Ethernet coprocessor Section 3 6 Hardware Architecture 3 1 3 1 Central Processor The central processor of the rtVAX 300 supports the CVAX chip subset plus six additional string instructions of the VAX instruction set and data types and full VAX memory management It is implemented by a single VLSI chip called the CVAX 3 1 1 Data Types The rtVAX 300 processor supports the following subset of VAX data types Byte Word Longword Quadword Character string Variable length bit field M acrocode emulation can provide support for the remaining VAX data types 3 1 2 Instruction Set The rtVAX 300 processor implements the following subset of VAX instruction set types in microcode Integer arithmetic and logical Address Variable length bit field Control Procedure call Miscellaneous Queue Character string moves MOVC3 MOVC5 CMPC3 CMPC5 LOCC SCANC SKPC and SPANC Operating system support F floating G floating D floating 3 2 Hardware Architecture 3 1 3 Microcode Assisted Emulated Instructions
306. internal loopback mode CSR5 lt 18 17 gt 1 12 LE Length Error When set indicates one of the following Hardware Architecture Descriptor unavailable owned by the rtVAX 300 in the middle of data chained descriptors e Zero length buffer in the middle of data chained descriptors e Setup or Diagnostic descriptors Data type TDES1 lt 29 28 gt lt gt 0 in the middle of data chained descriptors e Incorrect order of first segment TDES1 lt 26 gt and last segment TDES1 lt 25 gt descriptors in the descriptor list The Transmission process enters the suspended state and sets CSR5 lt 01 gt continued on next page Table 3 35 TDESO Fields Bit Name Description 14 15 29 16 31 TO ES TDR OW Transmit Watchdog Timeout When set indicates that the transmit watchdog timer has timed out indicating that the Ethernet coprocessor transmitter was babbling The interrupt CSR5 lt 06 gt is set and the Transmission process is aborted and placed in the stopped state Error Summary The logical OR of 01 02 08 09 10 11 12 14 Time Domain Reflectometer This is a count of bit time and is useful for locating a fault on the cable using the velocity of propagation on the cable Valid only if 50 lt 08 gt is also set Two excessive collisions in a row with the same 20 TDR values indicate a possible cable open Own bit When set indicates the descriptor is owned by the Ethe
307. interrupt IPL 1416 The console is connected to the rtVAX 300 IRQ 0 L line DAL 12 06 H lines are decoded to produce the LOWCONE signal to enable the console The CONIACK and LOWCONE outputs are internally latched by the rising edge of AS This is accomplished by using the internal D flops to store the output information The ENBVECTOR output asserts to drive the interrupt vector onto the DAL bus during an interrupt acknowledge cycle Table 6 6 lists the pins settings and comments Table 6 7 lists the corresponding equations Table 6 6 Interrupt Decoder Pin Setting Comment Input Signals 1 AS This is the active high inverted rtVAX 300 address strobe signal AS L It is used to dock the internal latches on the rising edge while WR L DAL and CSDP L information is valid 2 IDS This data strobe line DS L of the rtVAX 300 is asserted when the processor is expecting to receive the interrupt acknowledge vector from the DAL s 3 IWR WR L signal from the rtVAX 300 is high during an interrupt acknowledge 4 CSDPO The cyde status bit 0 is asserted during an rtVAX 300 external interrupt acknowledge cycle 5 CSDP1 The cycle status bit 1 is asserted during an rtVAX 300 external interrupt acknowledge cycle 6 CSDP2 The cyde status bit 0 is deasserted during an rtVAX 300 external interrupt acknowledge cycle 7 CSDP4 The cycle status bit 4 is deasserted during an rtVAX 300 external interrupt acknowledge cycle 8 D
308. ion of RST L when the processor is halted as the result of a console INITIALIZE command and after a halt caused by an error condition 3 5 Console Interface Registers The following tables and figures list and show hardware registers that the rtVAX 300 processor references Boot register Section 3 5 1 e Console registers for SCN 2681 DUART Section 3 5 2 e Memory system control status register Section 3 5 3 LED display status register Section 3 5 4 Appendix C contains tables of rtVAX 300 address assignments 3 5 1 Boot Register The Boot register is read once by the firmware when the system is powered on or reset Bits 3 0 define the initial value of bits 3 0 of the boot action cell This register is decoded by the rtVAX 300 and BOOT 3 0 L are used for the contents of this register If the user does not connect these pins their default value is 1 Figure 3 14 shows the boot register Table 3 12 lists boot options as they relate to register contents Hardware Architecture 3 41 Figure 3 14 Boot Register 31 04 03 02 01 00 Table 3 12 Boot Options Remote Trigger Console Power On Boot Action MLO 006371 Register Bit Setting L lt 2 gt lt 1 gt L lt 0 gt L Action X L L L X L L H PRAO X L H L PRBO X L H H PRB1 X H L L CSBO X H L H CSB1 X H H L CSB2 X H H H EZAO L X X X No boot performed rtVAX 300 enters console mode executing the c
309. ion purposes Place E4 within 2 cm of J1 Void all planes as near to J1 as possible A indicates the 9V return e B indicates the 12V return 7 10 Network Interconnect Interface MLO 006393 7 6 2 2 Layout Requirements The shell of the AUI connector must be attached to the chassis ground e Etch running from pin 6 of the AUI connector to the 12V return and from pin 13 of the AUI connector to the 12V source must be capable of maintaining a steady state current of 5 amperes e is recommended that the 12V return line pin 6 be taken from the AUI connector and returned to the power supply directly The return for the 12V supply should not be connected through logic ground due to possible noise problems caused by ground loops Pins 4 5 and 13 of the DP8392 chip require thermal relief This can be accomplished by connecting these pins to the 9V plane by an etch pad with a surface area greater than 6 45 1 inch2 e Placement of the BNC connector is critical In order to reduce stray capacitance place the BNC connector as close as possible to the DP8392 chip no further than 4 cm etch length away and void all planes beneath the connecting etch 7 6 2 3 Typical Ethernet Board Parts List Table 7 2 shows a list of parts used in this design example Table 7 2 Ethernet Board Parts List Generic Name Discrete Value Total in Design RES 40 2 2 CAP uF 1 RES 100 1 JUMPER 8 ENETXFMR 75
310. ions Appendix A describes the physical electrical and environmental characteristics of the rtVAX 300 processor Appendix B lists and defines acronyms used frequently in this guide Appendix C lists address assignments for memory space input output space and local register input output space Appendix D supplies user boot diagnostic firmware routines Appendix E contains a C program that builds a setup frame buffer for the hashing filtering mode Conventions This manual adheres to the following numbering and signal naming conventions Numbering Conventions computer addresses are hexadecimal numbers for example address 10000000 denotes 1000000016 All other numbers are decimal based unless otherwise specified Digital Signal Naming Conventions A signal name begins with a letter may end with either an H or L means that the signal is active high that is the signal voltage is between 2 4V and 5 0V means that the signal is active low that is the signal voltage is between 0 0V and 0 8V The term Asserted means that a signal voltage is within the active voltage range for that signal For example the signal AS is an low signal if this signal is asserted a voltage between 0 0V and 0 8 is present voltages are specified with respect to the 45V power supply ground that is used to power the rtVAX 300 1 is equivalent to high 0 is equivalent to low Signal buses are specified
311. iptor pointing back to itself is considered owned by rtVAX 300 regardless of the ownership bit state Table 3 37 TDES2 Fields Bit Name Descriptor 08 00 PO Page Offset The byte offset of the buffer within the page Meaningful only if TDES1 lt 30 gt is set Note Transmit buffers may start on arbitrary byte boundaries 30 16 BS Buffer Size The size in bytes of the data buffer If this field is 0 the Ethernet coprocessor ignores this buffer The frame size is the sum of all buffer size fields of the frame segments between and including the descriptors having TDES1 lt 26 gt and TDES1 lt 25 gt set Note If the port driver wishes to suppress transmission of a frame this field must be set to 0 in all descriptors comprising the frame and prior to the Ethernet coprocessor acquiring them If this rule is not adhered to corrupted frames might be transmitted Hardware Architecture 3 77 Table 3 38 TDES3 Fields Bit Name Descriptor 31 00 5 SVAPTE PAPTE Physical Address When TDES1 lt 30 gt is set TDES3 is interpreted as the address of the Page Table Entry and used in the virtual address translation process The type of the address System Virtual address SVAPTE or Physical Address PAPTE is determined by TDES1 lt 23 gt When TDES1 lt 30 gt is clear TDES3 is interpreted as the physical address of the buffer When TDES1 lt 31 gt is set TDES3 is interpreted as the VAX physical address of
312. is CR gt gt gt lt P gt this character string can be used by host software executing a binary load on the special attached terminal port to determine when it may respond FIRMWARE 4 11 The of the boot device is passed to the bootstrap routine in register zero RO The name is of the form ddcu where dd is a 2 letter device mnemonic c is an optional 1 letter adapter designator and is a 1 digit decimal unit number The console program accepts lowercase letters but converts the name to uppercase A terminating colon on the device name is acceptable but not required this character is not passed to the loaded code Section 4 3 7 lists boot devices and their corresponding mnemonics 4 3 6 2 Continue C ONTINUE The console 1 mode is exited Operation returns to or begins in program mode at the PC value either saved when console 1 0 mode was entered entered by the operator using the DEPOSIT command Note The interrupt stack pointer ISP must contain a valid virtual or physical address of RAM memory for this command to work Two longwords are pushed on the interrupt stack If the interrupt stack contains an invalid address the following message is displayed 04 ISP ERR 4 3 6 3 Deposit D EPOSIT lt QUALIFIER gt lt ADDRESS gt lt DATUM gt The specified datum is written to the specified address e Qualifiers Access size qualifiers B byte
313. is generated If the required data is a word that crosses a longword boundary or an unaligned longword then two successive aligned longword demand D stream read references are generated Data larger than a longword is divided into a number of successive aligned longword demand D stream reads with no optimization 3 1 14 3 Write References Whenever data is stored or moved a write reference is generated Since the CVAX processor does not impose any restrictions on data alignment other than the aligned operands of the ADAWI and interlocked queue instructions and Since memory can be accessed only one aligned longword at a time all data write references are translated into an appropriate combination of masked and nonmasked aligned longword write references If the required data is byte a word within a longword or an aligned longword then a single aligned longword write reference is generated If the required data is a word that crosses a longword boundary or an unaligned longword then two successive aligned longword write references are generated Data larger than a longword is divided into a number of successive aligned longword writes 3 2 Floating Point Accelerator The floating point accelerator is implemented in a single VLSI chip 3 30 Hardware Architecture 3 2 1 Floating Point Accelerator Instructions The floating point accelerator processes F floating D floating and G floating format instructions and accelerates the
314. is reserved for use by the console program This field will be repeated as many times as needed to display all address ranges that are not available to the operating system 4 18 FIRMWARE 4 3 6 12 4 3 6 13 TRIG Shows the state of remote trigger enable If the returned value is 0 remote triggers are not allowed if 1 remote triggers are allowed provided the remote trigger password is set correctl y Note The symbols used in the SET and SHOW commands must be entered as shown however they can be entered in lowercase and uppercase The spelling of each symbol is critical Start S TART ADDRESS The console starts executing instructions at the specified address The address is treated within the context of the user s memory management mode physical or virtual If no address is given the current saved PC is used The START command is equivalent to a DEPOSIT PC followed by a CONTINUE No initialization is performed Note The interrupt stack pointer ISP must contain a valid virtual or physical address of RAM memory for this command to work Two longwords are pushed on the interrupt stack If the interrupt stack contains an invalid address the following message is displayed 04 ISP ERR Also note that the ISP is undefined after a power up or reset TheINITIALIZE command can be used to initialize the ISP and the rest of the processor Test T EST
315. itch Nonprivileged software can access bits 15 002 only privileged software can access bits 31 16 Processor initialization sets the PSL to 0417000015 Figure 3 1 shows the format of the processor status longword Table 3 2 describes the fields within the PSL Figure 3 1 Processor Status Longword 313029282726252423222120 1615 08070605040302 0100 PRV MOD CUR MOD FPD MLO 004406 Table 3 2 Processor Status Longword Bit Map Data Bit Definition lt 31 gt Compatibility mode Reads as zero The 300 does not support compatibility mode lt 30 gt Trace pending 29 28 Unused Must be written as zero lt 27 gt First part done lt 26 gt Interrupt stack IS lt 25 24 gt Current mode CUR 23 22 Previous mode lt 21 gt Unused Must be written as zero 20 16 Interrupt priority level IPL 15 82 Unused Must be written as zero continued on next page 3 6 Hardware Architecture Table 3 2 Cont Processor Status Longword Bit Data Bit Definition lt gt Decimal overflow trap enable DV Has effect rtVAX 300 hardware Can be used by macrocode which emulates VAX decimal instructions lt 6 gt Floating underflow fault enable FU lt 5 gt I nteger overflow trap enable lt 4 gt Trace trap enable T lt 3 gt Negative condition code lt 2 gt Zero condition code 2 lt 1 gt Overflow condition code V
316. itter buffer is empty The rtVAX 300 processor responds to interrupt requests by initiating an interrupt acknowledge cycle shown in Figure 6 3 the sequence is shown in Figure 6 2 The INT output of the DUART asserts the RQ lt O gt L input of the rtVAX 300 processor The rtVAX 300 processor executes an interrupt acknowledge cyde during which it expects to read a vector from the interrupting device The interrupt vector generator see Figure 6 10 drives a vector of 02 016 onto the DAL bus when the ENBVECTOR signal is asserted The cycle status decoder see Figure 6 6 monitors the CSDP lt 4 0 gt and DAL 06 02 lines to determine if the rtVAX 300 processor is performing an interrupt acknowledge cycle The interrupt priority level IPL is detected when DAL 06 02 is read If the IPL correlates to an interrupt generated by the console the status decoder asserts the CONIACK signal 6 4 Console and Boot ROM Interface Figure 6 2 Sample Design Console Cycle Sequence oo WRITECYC1 1 O IDLE WRITECYC2 READCYC1 IOREADY IACKCYC2 CERE UE Y ROMCYC2 Y REN READCYC2 Yes Y Yes Y ROMCYC3 WRITECYC4 fo
317. ix XX Chapter 4 Firmware describes the system firmware ROM format system firmware entry console program entity based module and Ethernet listener startup messages hardware CSRs referenced by the rtVAX 300 firmware a diagnostic test list user defined board level boot and diagnostic ROMS creation and down line loading of test programs and ROM bootstrap operations Chapter 5 Memory System Interface describes memory speed and performance static and dynamic RAMs basic memory interface cyde status codes byte mask lines data parity checking internal cache control memory management unit a memory system design example memory timing considerations memory system illustrations and programmable array logic Chapter 6 Console and Boot ROM Interface discusses console system interface booting from external ROM the processor status LED register console interface and boot ROM illustrations and programmable array logic Chapter 7 Network Interconnect Interface describes the rtVAX 300 DECnet communications Ethernet interface thickwire network interconnect ThinWire support Ethernet coprocessor registers and a hardware implementation example Chapter 8 Device Interfacing discusses 1 0 device mapping the interrupt structure general bus interfacing techniques DMA device mapping registers an rtVAX 300 to digital signal processor application example reset power up halting the processor and 1 0 system illustrat
318. k Allocation 3 34 Cacheable references that miss the internal cache initiate quadword read the DAL bus When the requested quadword is supplied by either the second level cache or the main memory controller the requested longword is passed on to the CVAX processor and a data block is allocated in the cache to store the entire quadword Because the cache is 2 way associative only two data blocks one in each set can be allocated to a given quadword These two data blocks are determined by the cache index field of the address of the quadword which selects a unique row within the cache Selection of a data block within the row for example set selection for storing the new entry is random Since the rtVAX 300 supports 256M bytes 32M quadwords of physical memory up to 512K quadwords share each row two data blocks of the cache Contiguous programs larger than 512 bytes or any noncontiguous programs separated by 512 bytes have a 50 percent chance of overwriting themselves when cache data blocks are allocated for the first time for data separated by 512 bytes one page After six allocations there is a 97 percent probability that both sets in a row will be filled Hardware Architecture Figure 3 11 Internal Cache Address Translation 2928 Space Valid Bit Set 1 20 Bit 64 Tag Data Block Cache Tag 0908 0302 00 Cache Index Cache Displacement Valid Bit 20 Bit 64 Tag Dat
319. l specifies the direction of a data transfer on the DAL bus for the current bus cyde When the signal is asserted the rtVAX 300 processor is performing a write operation when the signal is deasserted it is performing a read operation or interrupt acknowledge cyde The WR L signal is valid when AS L is asserted Technical Specification 2 15 Ready RDY 1 1 0 2 External logic asserts this signal to indicate the completion of the current bus cycle When this signal is not asserted the rtVAX 300 processor extends the current bus cyde for a slower memory or peripheral device The RDY L or ERR L signal must be asserted to end the current bus cyde These signals must be driven by tri state drivers Both signals can be asserted simultaneously to force the rtVAX 300 processor to retry the current bus cyde During internal cycles CSDP lt 4 gt asserted the rtVAX 300 processor drives RDY L high The rtVAX 300 processor asserts RDY L before the end of an internal cycle The rtVAX 300 processor does not drive the RDY L signal on non internal cydes Note During quadword cache invalidate cydes AS L must remain asserted for at least 250 ns which equates to 4 microcycle write Two wait states must be added Memory systems faster than 400 ns must delay cache invalidate write cycles at least two microcydes by holding off the assertion of RDY L Slower memory systems already adhere to the minimum AS L assertion requirement
320. lay Memory controller delay 31 5 100 5 Data in hold time 5 28 Memory System Interface Figure 5 7 Sample Design Memory Controller Octaword Write Cycle Timing mlo 004432 ps turnpage Memory System Interface 5 29 5 10 5 5 10 6 In this case data in hold time 131 ns 12 ns 12 ns 107 ns Memory Subsystem Refresh Timing Figure 5 8 shows the memory controller refresh timing The DRAMs that are used support CAS before RAS refresh page mode and they have an access time of 80 ns These DRAMs require that CAS be asserted at least 20 ns before RAS and RAS must be asserted for at least 80 ns If CLKA is operating at 20 MHz the cyde time is 50 ns The timing diagram also shows that ENBCAS and REFCYC assert 50 ns after REFREQ asserts REFCYC clears REFREQ and all of the DRAMs CAS lines are asserted RAS asserts 50 ns after ENBCAS asserts and all three signals remain asserted for 100 ns Table 5 8 lists all of the timing parameters needed for CAS before RAS refresh Table 5 8 DRAM CAS Before RAS Refresh Timing Parameters Minimum Maximum Actual Parameter Description Time ns Time ns Time ns CAS low while RAS high 20 40 RAS low time 80 10000 100 RAS precharge time 70 100 RAS Precharge Time RAS precharge time is defined as the amount of time that the DRAM needs to be unselected RAS and CAS are deasserted after any access cyde This is needed because internal voltages of the DRAM s must
321. le D 10 User Boot Diagnostic ROM Sample 0 test failed 1 test passed SIDE EFFECTS None board level test 11 argument block offsets offset scratch address of scratch memory area failing_pc address of longword to store failing pc if test fails expected_data address of quadword that test can Store expected data if test fails actual data address of quadword that test can Store actual data if test fails flags board level test flags gt usrom share byte 300 usrom test 11 m lt gt ret return to caller Sbttl rtVAX 300 Board level Test 12 User Boot Diagnostic ROM Sample D 11 FUNCTIONAL DESCRIPTION This routine user supplied is called by the rtVAX 300 s resident firmware at system power on to do board level test 12 It is called at IPL 31 in kernel mode with memory management disabled CALLING SEQUENCE calls 5 300 usrom test 12 INPUT PARAMETERS scratch address of scratch memory area failing pc address of longword to store failing pc expected data address of quadword to store expected data actual data address of quadword to store actual data flags board level test flags IMPLICIT INPUTS None OUTPUT PARAMETERS r0 test results IMPLICIT OUTPUTS None ROUTINE VALUE 1 device not present or untestable 0 test failed 1 test passed SIDE EFFECTS
322. le Commands Xe Ee NE E s n E x EGER x Helps Borie eine t DR ent dd eua Unjam E Ri Transfer lk Ev Re ak eee ee Supported Boot Devices Console Program Messages Console Capabilities of Console Terminals Console Entry and Exit Entity Based Module and Ethernet Listener Startup 5 Power On Display Boot Countdown Description Halt AGHONY ji aioe ue Re Boot Device x iie xd Boot e EXER e Hardware CSRs Referenced by the Firmware Power On Configuration Register External I O Bus Reset Register Diagnostic Test 5 User Defined Board Level Boot and Diagnostic ROM 4 8 4 8 4 9 4 9 4 9 4 11 4 11 4 11 4 12 4 12 4 15 4 15 4 15 4 16 4 16 4 47 4 17 4 18 4 19 4 19 4 20 4 20 4 21 4 21 4 21 4 24 4 24 4 24 4 25 4 26 4 26 4 27 4 28 4 28 4 28 4 29 4 29 4 29 4 29 4 34 vii 4 8 1 Optional User Initialization Routine 4 8 1 1 Optional Initialization Routine 4 8 1 2 System Scratch
323. le interface and boot ROM illustrations and describes the programmable array logic PALS used Figure 6 10 illustrates a sample design of a console interface Figure 6 11 and Figure 6 12 illustrate sample designs of user boot ROM banks 1 2 respectively Figure 6 13 shows the the memory map for all the RAM and ROM registers Table 6 4 lists the corresponding equations 6 4 4 Application Module Address Decoder PAL The application module address decoder PAL selects the memory and 1 0 devices It asserts the UPCPUST SELROM and CONE signals for the system console and the external boot ROM The ROM and console select lines are internally latched on the rising edge of AS H This eliminates the need for external device select latches by using the D flip flops that are built into the 22V 10 PAL Table 6 3 lists pin settings Console and Boot ROM Interface 6 19 Figure 6 9 Sample Design Processor Status Display lt 2 gt 9 LBM lt 2 gt 925 CPUST 10 LBM lt 3 gt L 2 2 CPUST IE 5 4 5 40 Flo 7418175 15 R DAL lt 23 gt 13 103 R2 DAL lt 22 gt 12 R1 DAL lt 21 gt 5 DAL lt 20 gt 4 100 o 1 seem 45V 4BF 4D Flop 7415175 HEX
324. le into memory and jumps to the starting address You define the program as the load file when you set up the network data base Do not begin the program s code with the VAX MACRO ENTRY statement or its equivalent in other languages Example 4 4 shows a VAX MACRO self looping test program that allows you to verify correct down line loading Example 4 4 Self Looping Test Program START brb START end START When you power up the rtVAX 300 issue the gt gt gt BOOT ETHERNET command to boot it The processor loads the test program into memory and runs it You halt the processor it displays the current program counter address which you can verify The address should be 00001800 but can vary according to the firmware revision You can also end a test program with the HALT instruction The processor halts and displays the program counter address 4 9 3 Using MOP to Run Test Programs You use the network control program NCP to set up your network data base for an rtVAX 300 target node You define the target node name address hardware address and load file as in Example 4 5 The network data base consists of the following permanent data base which is stored on the system disk You need BYPASS privileges to modify the permanent data base you use the DEFINE command to make modifications volatile working data base which is loaded at network startup time from the permanent data base You need OPER privileges t
325. le writing a system page table entry to change the PTE lt gt bit before writing a previously unmodified page or while writing a process control block PCB entry during a context switch or during the execution of instructions that modify any stack pointers stored in the PCB Most Recent Virtual Address Parameter Most recent virtual address 31 00 captures the contents of the virtual address pointer register at the time of the machine check If a machine check other than machine check 81 occurs on a read operation this field represents the virtual address of the location that is being read when the error occurs plus four If machine check 81 occurs this field represents the physical address of the location that is being read when the error occurs plus four If a machine check other than machine check 83 occurs on a write operation this field represents the virtual address of a location that is being referenced either when the error occurs or sometime after plus four If a machine check 83 occurs this field represents the physical address of the location that was being referenced either when the error occurs or sometime after plus four In other words if the machine check occurs on a write operation the contents of this field cannot be used for error recovery Internal State Information 1 Parameter Internal state information 1 is divided into four fields The contents of these fields are described as follows e 31 24
326. lectrical and Environmental Characteristics Table A 3 Cont AC Characteristics Number Description Minimum Maximum Units 28 taspty delay from asserting CCTL 0 4p ns during cache invalidate 29 tasaprs DAL setup during cache invalidate 25 ns 30 tpMRG DMR maximum assertion after 6000 ns DMG 31 insTw Reset assertion width 30p ns 32 insTD Strobe delay after reset 0 25 ns 33 insTs Reset input setup prior to P1 20 2p 10 ns 34 Initial AS delay 40p ns 35 tznDY Z state RDY to RDY H 11 ns 36 inpvz RDY deasserted to RDY Z 2p ns 37 tasas CSDP lt 4 gt setup time 2p 42 2p ns 38 taswo Minimum AS assertion time for 21p ns octaword cache invalidation 39 Minimum AS assertion time for 10p ns quadword cache invalidation Note p 0 25 microcyde 0 50 CLKA cyde 25 ns for 20 MHz Physical Electrical and Environmental Characteristics 9 A 3 Environmental Characteristics Environmental characteristics include e Temperature Operating temperature 0 C to 70 C with the following restrictions 0 to 50 C No fan required natural convection cooling 50 to 60 C Fan required with at least 508 mm s 100 LFM across the rtVAX 300 processor 60 to 70 C Fan required with at least 1000 mm s 200 LFM across the rtVAX 300 processor The rtVAX 300 has no preferred orientation for cooling e Relative humidity Operating 10 to 90 noncondensing
327. lid exception and exceptions that occur while an interrupt or another exception are being serviced which cause the exception to be dispatched to the appropriate service routine by the resident firmware The VAX Architecture Reference Manual describes the exceptions listed in Table 3 5 except machine check in greater detail Section 3 1 12 4 describes the machine check exception in greater detail Table 3 8 in Section 3 1 12 7 describes exceptions that can occur while an interrupt or another exception are being serviced Table 3 5 Exceptions SCB Offsets Type Meaning Arithmetic Trap and Fault 34 Trap Integer overflow 34 Trap Integer divide by zero 34 Trap Subscript range 34 Fault Floating overflow 34 Fault Floating divide by zero 34 Fault Floating underflow Memory Management Exceptions 20 Fault Access control violation 24 Fault Translation not valid Operand Reference Exceptions 1C Fault Reserved addressing mode 18 Abort Reserved operand fault Instruction Execution Exceptions 10 Fault Reserved privileged instruction C8 Trap Instruction emulation CC Fault Suspended emulator continued on next page 3 18 Hardware Architecture Table 3 5 Cont Exceptions SCB Offset Type Meaning 40 4C Trap Change mode CHMK CHME CHMS CHMU 2C Fault Breakpoint Tracing Exception 28 Fault Trace System Failure Exceptions 1 Abort Interrupt stack not valid 08 Abort Kernel stack not valid 04 Abort Machine check 0
328. lopment the rtVAX 300 supports virtual memory The internal memory management unit MMU of the rtVAX 300 processor translates virtual addresses to physical addresses Since the MMU resides within the rtVAX 300 only physical addresses appear on the DAL lt 29 02 gt H bus Thus the memory system design is simplified the memory subsystem is directly addressed by the rtVAX 300 processor The VAX Architecture Reference Manual provides more information on virtual to physical address translation of the MMU 5 9 Memory System Design Example The remainder of this chapter discusses the design of a 4M byte DRAM memory system for the rtVAX 300 This memory system consists of the following elements e Address status decoders Address latches e Refresh request timer e Thirty six 1M bit DRAMs 32 for data and 4 for parity bits e DRAM row and column address multiplexer DRAM data latches Memory controller state machine Figure 5 2 shows a simplified diagram of the memory controller logic Read write and refresh memory operations are sequenced by the memory controller 1 Memory system design is similar to that of a nonvirtual addressed processor Memory System Interface 5 9 Figure 5 2 Sample Design Memory Subsystem Functional Diagram mlo 006386 ps turnpage 5 10 Memory System Interface 5 9 1 Address Decoder The rtVAX 300 places a 28 bit longword address on the DAL 29 027 bus at the beginnin
329. lt 2 Gp lt gt 1 109 St __ _ lt 6 gt lt 2 gt 1 0 br H lt 92 gt 1 100 vv v lt 8 gt H lt 42 gt 1 0 lt gt AOH Ly lt gt NNOOON Ale lt e2 gt 1v0 orl 68 lt gt AOH 07 5 5 62 lt 9 gt NNOSON a lt 12 gt 1 0 lt 02 gt 1 0 INX 12 __ lt gt lt 6 gt 1 0 96 p 66 lt gt 9 S lt b gt NNOOON T ER a ve lt 91 gt 7 0 Age SE NNOOON E lt gt 26 LE 5 5 lt gt 0 5p 62 lt 15 THM T lt 0 gt 1008 or OMS z 2 2 L 1va 82 2 lt 21 gt 1 0 15 1 lt 92 Sc lt 01 gt 1 0 1 13192 4 gt 1008 Si 2 021 pp lt 8 gt 1 0 1 lt gt 1 lt 2 gt 0 lt gt 1 22 12 lt 9 gt 1 1 lt 1 gt 0 1 lt 0 gt 1 1 lt gt 1008 2NS n lt gt 02 5 p 61 lt gt lt gt 1 8v lt gt Zk lt 2 gt 1 0 1H 1 154 4 gt 1008 Y H iva HH ist EMS NES ed L 1 1 5 021 9 1 ap H 1 lt gt 4280 1 lt gt 1 1 lt gt 4282 0L 6 1 lt 2
330. lt 2 0 gt read 0105 and WR L is asserted The rtVAX 300 asserts AS L to indicate that the register number BM 43 05 CSDP lt 3 0 gt and WR L are valid and be latched 4 ThertVAX 300 transfers the data onto DAL 31 00 and asserts DS L to indicate that the DAL contains valid data 2 40 Technical Specification 5 ThertVAX 300 checks for completed cycle once every two dock phases starting at the next possible P1 The response of the external logic is as follows processor register is implemented external logic reads the data from DAL and asserts RDY L while ERR L is deasserted b Ifthe processor register is not implemented external logic responds either as if the register is unimplemented by asserting ERR L when RDY L is deasserted or as if the register is implemented by asserting RDY L with ERR L deasserted Both responses have the same effect and no special action is taken The unimplemented response indicates no special action only if RDY L is deasserted for two consecutive P1 sample points If this response is detected at the first P1 sample point but RDY L is asserted at the second P1 sample point the cyde will terminate according to the retry protocol c Torequest retry external logic asserts both L and ERR L DAL arbitration occurs after the initial write cycle is terminated 6 ThertVAX 300 completes the by asserting AS L and DS L 2 6 9 Internal Cycles 2 6
331. lt 3 0 gt L if DPE L is asserted Therefore use the byte masks only for write cycles and select all 4 bytes during read cydes This parity information is required for proper functioning of the Ethernet controller The rtVAX 300 s Ethernet controller can use octaword transfer cycles when transferring to nonoctaword aligned buffers in memory This forces the byte mask lines to change state during octaword transfers The Digital supplied VAXELN device driver always sets up transmit and receive buffers on page boundaries so that all octaword transfers occur on octaword boundaries Thus the byte mask lines will not change during octaword transfers when using the Digital supplied Ethernet device driver Although Digital does not recommend this users can write their own Ethernet device driver and use nonoctaword aligned buffers Digital has tested device drivers that use nonaligned buffers and has found they have poorer performance than those that use aligned buffers Nonaligned buffers require that memory controllers connected to the rtVAX 300 write only to bytes whose byte mask lines are asserted for each longword that is transferred Memory System Interface 5 5 To handle octaword transfers to nonaligned buffers correctly you must not latch the byte mask lines They must be able to enable CAS line assertion of the DRAMs during each longword that is transferred directly Longword and quadword transfer cycles require that the byte mask lines
332. lt 4 0 gt L DPE L and WR L lines are tri stated by the DMA device This is the P2 phase During write the DAL bus is driven with the data and CSDP 3 0 L is driven with the byte parity by the bus master During a read cyde the DMA peripheral listens to the DAL and CSDP lines to read the data During either cyde the DS L lineis asserted This is the P3 phase DMA write cydes must maintain rtVAX 300 internal cache coherency therefore a DMA write to an address whose data has been previously cached invalidates that cache entry The DMA bus master accomplishes this by first asserting the CCTL L line and then driving the DMA addresses onto the DAL bus and asserting AS L This cache Device Interfacing invalidation cycle prevents stale data from existing in the rtVAX 300 internal cache 7 The DMA device waits for the assertion of RDY L during the P1 phase Until RDY L is asserted all signals stay in the same state 8 During a read cyde the memory subsystem asserts RDY L and the DMA device must latch the data during a write cyde the DMA device must tri state the DAL 31 00 and CSDP lt 4 0 gt L lines during the P2 phase 9 If another DMA transfer is required the DMA device goes to step 3 Only eight successive DMA transfers are allowed the DMA device must relinquish the bus to the 300 by deasserting DMR In addition DMA devices cannot remain bus master for longer than 6 us If more DMA
333. m counter to 20040000 Once the RST L line is deasserted the rtVAX 300 begins booting by fetching instructions that start at physical location 20040000 the starting location of the rtVAX 300 internal boot and diagnostics ROMs The power on reset circuit shown in Figure 8 10 asserts the RESETVAX line when power is first applied to the board The 4 7 kf and 470 12 resistors the input of the LM211 comparator set that input voltage to 4 5V The 10 capacitor this input charges more quickly than the 10 uF capacitor which is charged to 5V through a 100K resistor to Vcc Thus when power is first applied the input of the LM 211 comparator quickly reaches 4 5V The input of the comparator is at a lower voltage than the input until the 10 pF capacitor charges over 4 5V This takes slightly longer than the RC time constant of 100 000 x 0 00001 1 second While the input is at a lower 8 24 Device Interfacing Figure 8 10 Device Interfacing Reset Timer Logic 45V potential than the input the open collector output of the LM 211 comparator is turned on and the RESETVAX signal is asserted When the reset switch is pressed the BUTTRST signal also asserts through the 74 32 gate of the ENBRST switch shown in Figure 8 31 When either BUTTRST or RESETVAX is asserted the 74F 579 counter is reset and the reset hold latch is cleared After 12 8 us the counter overflows and the TC output toggles The r
334. me 0 Column address hold time 20 RAS precharge time 70 RAS width 80 10 000 Access time from RAS 80 Access time from CAS 20 Output disable time after CAS 20 RAS to CAS lead time 25 60 Data in setup time before CAS 0 Data in hold time after CAS 15 5 10 3 1 Calculating DRAM Row Address Setup Time When the rtVAX 300 is accessing memory the memory controller asserts RAS on the rising edge of The address is placed on the DAL 29 02 bus 20 ns before the rising edge of P1 This address has to propagate through the 74F 373 latches the 74F 86 XOR gate and the 74F 711 MUX The total propagation delay is as follows 1 CLKA period Address to P1 edge Propagation of 74F 373 Propagation of 74F 86 Propagation of 74F 711 Minimum memory controller delay Minimum RAS driver delay DRAM row address setup time this case DRAM row address setup time 50 ns 23 5 7 5 5 6 ns 0 ns 2 ns 57 ns 5 26 Memory System Interface 5 10 3 2 5 10 3 3 5 10 3 4 Calculating DRAM Row Address Hold Time Once RAS has been asserted the SELCOL input to the 74F 711 is asserted on the following CLKA falling edge When the worst case row address hold time is calculated the minimum propagation delay of the two 74F 00 gates of the address MUX select flop must be added to the RAS to SELCOL time The row address hold time is calculated as follows RAS to CLKA rising edge Memory c
335. mer service engineer to maintain the system system user to communicate with running programs The processor can halt on one of the following conditions operator command A serious system error AHALT instruction e Assertion of the HLT line e Boot failure Although users may employ the console program to develop software this is not a goal of its implementation The operator may put the system in an inconsistent state by using console commands The operation of the processor in such a state is undefined 4 3 Console Program This section discusses the operator interface to the firmware console program The console program operates an optional user supplied terminal through the Signetics 2681 Serial Line Unit SCN 2681 DUART chip or its equivalent 4 3 1 Entering the Console Program The rtVAX 300 operates normally in program I O mode The mode is set to console 1 0 mode by of the following methods Kernel HALT occurs the rtVAX 300 is running in kernel program mode a program executes the HALT instruction and the default recovery action is specified to halt Boot operation fails and the default action is set for Boot Halt boot operation fails and the default recovery action is set for Restart B oot H alt 4 8 FIRMWARE The operating environment is severely corrupted the processor forces a processor restart when it detects one of several events indicating severe corruption of its
336. mode stack pointer The rtVAX 300 system firmware maintains shadow copies of many processor registers because reference to the actual registers would interfere with the operation of the rtVAX 300 firmware Data accessible only through their shadow copies are general registers RO through R15 the PSL and internal registers MAPEN 5 SCBB IPL MSER CADR Access of any stack pointer may involve the current stack pointer R14 the shadow copy of the stack pointer and the internal registers 4 14 FIRMWARE Notes The shadow copy replaces the actual copy at console exit 2 Upon entry of the ROM code the IPR CADR is not correctly saved however if the IPR CADR is changed by a DEPOSIT command the value added by the DEPOSIT command is restored e Datum The datum is specified as hexadecimal number A missing datum is treated as a zero entry 4 3 6 4 Examine E XAMINE lt QUALIFIER gt lt ADDRESS gt The contents of the specified address are displayed in hexadecimal e Qualifiers Supported qualifiers are the same as the DEPOSIT command e Address The address specification is the same as the DEPOSIT command 4 3 6 5 Find F IND QUALIFIER LIST gt The console searches the system memory starting at physical address zero for a page aligned 256K byte section of main memory or a restart parameter block RPB If the segment or block is found its address plus 512 is left in the SP otherwise
337. module that uses the rtVAX 300 processor The console provides a tool for debugging the application hardware and software Without the console terminal you cannot use the console emulation program and the local debugger I O registers implemented in the application hardware be debugged by using the EXAMINE and DEPOSIT commands of the console emulation program through the console terminal The built in console emulation routines provide other commands for performing self test and external memory testing The VAXELN kernel also provides a local debugger that is used through the console User written VAX assembly language programs for debugging hardware and VAXELN system images can easily be loaded through the second DUART A console terminal interface for the rtVAX 300 processor must contain the following elements Full address decoder to select the console DUART Cycle status decoder to detect console interrupt acknowledge cycles Address latches to hold the console register address SCN 2681 DUART to implement the console registers and interface Line receivers and drivers DAL transceiver to prevent bus contention Interrupt vector generator Optional 160 ms break detector Console state machine Figure 6 1 shows the console terminal interface block diagram The interface contains the address and cycle status decoder the DUART DAL bus transceivers address latches an interrupt vector generator and a console state machine The co
338. n These drivers are enabled by the ROMREAD L signal 6 2 8 ROM Speed vs rtVAX 300 Performance If the ROMs are copied to RAM the speed of these ROMs affects only the time required to boot the VAXELN system on the rtVAX 300 Once the rtVAX 300 has finished booting it runs out of system RAM and no longer accesses the ROMs The entire system image has been copied from the ROMs to system RAM before the VAXELN kernel begins executing If a longer boot period can be tolerated slower ROMs can be used If the rtVAX 300 is designed to run out of the ROMs the access time of the ROMs directly affects the runtime performance 1 The ROMs used the example were specified at 60 ns from CS deassertion to HI Z 6 18 Console and Boot ROM Interface 6 3 300 Processor Status LED Register Many applications must have a visual indication of the rtVAX 300 processor status Two 7 segment LED displays and a status register can be implemented on the user s application module to use as a processor status display When the rtVAX 300 firmware is performing self test it writes to that register to show the progress of self test This register is at physical address 201FFFFE and is implemented as shown in Figure 6 9 The implementation of this register is optional if it is deleted the rtVAX 300 continues to perform its self tests correctly 6 4 Console Interface and Boot ROM Illustrations and Programmable Array Logic This section shows conso
339. n The display includes the board name and firmware version a hexadecimal countdown list of test modules through 1 with a quick summary of the status of each and an expanded status report of those test modules for which error or status information is available Example 4 2 shows a sample power on display Example 4 2 Sample Power On Display rtVAX 300 Vn m gt gt gt where n is the major version number m is the minor version number the countdown line each test number is followed by a status character and two periods Table 4 3 lists the status codes and their meanings Table 4 3 Countdown Status Codes Code Meaning Test completed without fatal error Fatal error detected in test Test determined option is missing The return status of a user supplied test was not 1 test passes 0 test failed or 1 option not present 4 26 FIRMWARE 4 5 2 Boot Countdown Description When the rtVAX 300 is loading an operating system the LED display and the console display if they exist indicate the progress of the boot Table 4 4 explains the meanings the LED displays and console messages Table 4 4 Boot Countdown Indications LED Console Message Meaning 02 2 The bootstrap code has started no valid load host or ROM boot block has been located yet 01 Ti For ROM boots the ROM boot block has been located and if the ROM is to be copied to memo
340. n addresses will be filtered according to the SDES1 lt 25 gt bit value 11 Unused Reserved continued on next page Hardware Architecture 3 57 Table 3 23 Cont CSR6 Bits Bit Name Access Description 3 PB R W 3 58 Hardware Architecture Pass Bad Frames mode When set the Ethernet coprocessor passes frames that have been damaged by collisions or are too short due to premature reception termination Both events should have occurred within the collision window 64 bytes or else other errors are reported When clear these frames are discarded and never show up in the rtVAX 300 receive buffers Note Pass Bad Frames is subject to the address filtering mode that is to monitor the network this mode must set together with the promiscuous address filtering mode Force Collision mode Allows the collision logic to be tested This chip must be in internal loopback mode for FC to be valid If this bit is set a collision is forced during the next transmission attempt This results in 16 transmission attempts with excessive collision reported in the transmit descriptor Disable Data Chaining mode When set no data chaining occurs in reception frames no longer than the current receive buffer are truncated RDESO lt 09 08 gt are always set The frame length returned 0 lt 30 16 gt is the true length of the nontruncated frame while 50 lt 10 gt indicates that the frame has been truncated
341. nd 7F 16 are reserved for use these external self test routines When control is passed to the test in ROM the high order byte of the LED status register is set to a value in the range of 1 through 7 to indicate the test number and the low order byte is set to F1e The user s test routine must change the value from the starting value to indicate progress through the user s subtests Normally the subtests count the 1 Registers R2 to R15 the interrupt stack and all IPRs must be preserved 4 42 FIRMWARE lowest digit down from to 016 The high order byte should always indicate the same value to make failure codes unique 4 8 2 1 Self Test Routine Input Parameters The user defined initialization routine is called with five parameters Parameter 1 AP 44 is the address of a scratch memory area The first 4K bytes may be used as a scratch memory area Parameter 2 AP 48 is the address of a longword that the test may use to store the PC if the test fails Parameter AP 12 is the address of a quadword that the test may use to store expected data if the test fails Parameter 4 AP 16 is the address of a quadword that the test may use to store actual data if the test fails Parameter 5 AP 20 is a longword containing flags Bit 0 Lif explicitly called with a TEST x command Informational messages should be suppressed if this bit is 0 Bit 1 1 if test is called by the powerup sequence Bit 2
342. nd transmission processes are aborted and placed in the stopped state Note At this point port driver must issue a Reset command and rewrite all CSRs Receive Watchdog Timer nterrupt When set indicates that the receive watchdog timer has timed out indicating that some other node is transmitting overlength packets on the network Current frame reception is aborted and 50 lt 14 gt and 50 lt 08 gt are set Bit CSR5 02 is also set The reception process remains in the running state Transmit Watchdog Timer Interrupt When set indicates that the transmit watchdog timer has timed out indicating that the Ethernet coprocessor transmitter was transmitting overlength packets The transmission process is aborted and placed in the stopped state Also reported into the Tx descriptor status 50 lt 14 gt flag Boot Message When set indicates that the Ethernet coprocessor has detected a boot message on the serial line and has set the external pin BOOT L Done When set indicates that the Ethernet coprocessor has completed a requested virtual CSR access After a reset this bit is set continued on next page Table 3 22 CSR5 Bits Bit Name Access Description 18 17 OM R Operating Mode These bits indicate the current Ethernet coprocessor operating mode as follows Value Meaning 00 Normal operating mode 01 Internal Loopback I ndicates that the Ethernet coprocessor is disen
343. ne It is good practice to have the 1 0 device dear the interrupt request after the rtVAX 300 runs an interrupt acknowledge cycle for that device Typically a CSR register associated with the I O device contains the interrupt control bit s When a device has requested an interrupt a bit is set in that register This bit can automatically reset after the CSR is read or the ISR can clear this bit by writing back to the CSR The ISR branches to the correct servicing code which depends on the nature of the interrupt after reading this CSR The ISR executes the service code which cannot be preempted After executing the code the ISR lowers the processor s IPL and other interrupts can be serviced See the rtVAX 300 Programmer s Guide for a diScussion of 1585 Device Interfacing 8 2 1 Interrupt Daisy Chaining In many applications more than four devices need to request interrupts from the rtVAX 300 To accommodate multiple devices the interrupt requests are logically ORed and the interrupt acknowledge is daisy chained between the devices as shown in Figure 8 3 For example if two devices need to interrupt at IPL 1416 the interrupt request line of both devices can connect to lt 0 gt through open collector drivers decoder that decodes interrupt acknowledgments at IPL 144g asserts the device interrupt acknowledge signal After being latched this signal is then ANDed with DS and fed into the interrupt acknowledge input o
344. network The DP8392 transceiver chip introduces about 4 5 pF when it is not transmitting To decrease this capacitance the off state capacitance of a diode placed in series with the transmitter output TXO pin of the chip is used 7 14 Network Interconnect Interface general purpose diode like the 0664 of 25V and 135 mA provides maximum 2 pF of capacitance when it reverse biased and has a reverse recovery time of a maximum 10 ns This means that the capacitance introduced by the DP8392 is reduced from 4 5 pF to 1 4 pF maximum and that 10 ns are added to the transmitter start up delay the time required for transmitted data to validly appear on the coaxial medium Precision Resistor The transceiver chip uses a 1K 196 resistor between pins 11 RR and 12 RR to set ThinWire coaxial drive levels output rise and fall times 10 MHz collision oscillator frequency jabber timing and receiver squelch timing 1K 0 25 W 1 resistor is recommended Decoupling capacitor A 0 1 to 0 47 capacitor is needed between the GND and VEE pins 10 and 4 5 13 This decoupling capacitor helps reduce impulse and ripple noise on the transceiver chip power supply below limits of 75 mV and 100 mV peak to peak respectively A ceramic capacitor should be used for its good high frequency characteristics A 0 47 pF 25V capacitor is recommended If impulse noise and ripple limits are exceeded packet loss results Pulse Transformer
345. ng the console emulation program e Bootstrap Loads the next level of software that is the VAXELN realtime executive e Console emulation program E mulates a subset of the VAX standard console program This chapter discusses the following topics e System firmware ROM format Section 4 1 e System firmware entry Section 4 2 e Console program Section 4 3 e Entity based module and Ethernet listener Section 4 4 FIRMWARE 4 1 e Startup messages Section 4 5 e Hardware CSRs referenced by rtVAX 300 firmware Section 4 6 Diagnostic test list Section 4 7 Board level initialization ROM Section 4 8 e System scratch RAM Section 4 8 1 2 e Creation and down line loading of test programs Section 4 9 e Serial line boot directions Section 4 10 ROM Boctstrap Operations Section 4 11 4 1 System Firmware ROM Format The base rtVAX 300 firmware is contained in four 8 bit wide ROMs this provides a full 32 bit memory data path Figure 4 1 shows the system ROM format Figure 4 1 System ROM Format 31 24 23 16 15 08 07 00 MLO 004499 System firmware ROMs require two types of information some information is required on a per byte basis for ease of manufacture and development the bulk of the information software and tables is supplied by the set of ROM parts 4 1 1 System ROM Part Format The following features are provided for each ROM part that is for each of the four ROM chips These features simplif
346. ns must be invalidated This is accomplished by running a conditional cache invalidation DMA cyde This cyde begins by asserting the CCTL L line before the DMA address during the DMA write cycle See Figure 8 9 Each conditional invalidate cycle causes the rtVAX 300 to detect collision on a quadword cache entry Two consecutive conditional invalidate cydes can be used to detect a collision on a naturally aligned octaword To maintain cache coherency a detected collision invalidates that entire quadword within the rtVAX 300 internal cache The Ethernet controller can issue longword write cydes To maintain CPU cache consistency the Ethernet controller asserts CCTL L at the beginning of the write cycle to start a quadword cache invalidation cycle Cache invalidation cycles require at least 4 microcycles therefore if CCTL L is asserted at the beginning of the write cycle the memory system must add two wait states a total cycle time of 400 ns to the cycle by holding off the assertion of RDY 5 8 Memory System Interface L If CCTL L is not asserted at the beginning of the write cycle this is a CPU longword write and zero or one wait state 200 or 300 ns memory access can be applied All DMA devices that use cache invalidation cycles to maintain internal cache consistency must adhere to the cache control timing specifications shown in Figure 2 17 5 8 Memory Management Unit To facilitate multitasking and to ease program deve
347. nsole terminal connects to channel A of the DUART a serial line output of a VMS host can be connected to channel B to down line load hardware debugging assembly language programs and VAXELN system images Other general purpose RS 232 peripheral devices can also connect to channel B 6 2 Console and Boot ROM Interface Figure 6 1 Sample Design Console Terminal Interface Block Diagram TXA RXA and IACK gt eceiver Decoder Line me TXB RXB Console B Receiver ENBVECTOR LADDR lt 5 2 gt ENBCONRD ENBCONWR Console Interface Controller ENBCONDATA 4 IOREADY ENBCONWR Interrupt ENBCONRD Vector Generator LWRITE Drivers 45V Bits 9 7 6 Bits 15 10 8 5 0 DAL 15 05 ENBVECTOR MLO 004441 6 1 1 Console Access When the rtVAX 300 processor accesses any of the 16 console registers the rtVAX 300 first places the register address the DAL lt 29 02 gt bus This address is in the range of 20100000 through 2010003F The address decoder see Figure 6 6 asserts the console enable 1 signal when valid console address is latched CONE L asserts on the rising edge of AS H and remains asserted throughout the entire console access cycle The 4 low order address bits DAL 05 02 are latched see Figure 6 7 fed into lt 3 0 gt of the DUART to select one of the 16 internal registers The DUART is only 8
348. nt Timing Cyde for Reset Function rtVAX 300 Pin Layout Thickwire 5 rtVAX 300 Memory and 1 0 5 rtVAX 300 Memory Bank Organization Timing Single Transfer Read Cycle Timing Quadword Transfer Read CycleTiming Octaword Transfer Read Cycle Timing Single Transfer Write Timing Octaword Transfer Write Cyde Timing Interrupt Acknowledge Internal Read or Write Cyde DMA creaga XR Octaword Cache Invalidate Quadword Cache Invalidate Cyde Processor Status Longword Interval TIME csse ue exer Interrupt Registers Information Saved on a Machine Check Exception 3 83 3 85 4 6 4 26 4 28 4 45 4 46 E 1 2 3 2 6 2 7 2 11 2 13 2 22 2 23 2 25 2 26 2 29 2 32 2 35 2 37 2 39 2 42 2 43 2 44 2 45 3 10 3 16 3 20 WN deda 3 oo System Control Block Base Register System Identification Register Internal Cache Organization Internal Cache Entry Internal Cache Tag Block Internal Cach
349. nternal Cache Organization Set 1 Set2 64 64 by 22 Bit 64 by 72 Bit 64 by 22 Bit 64 by 72 Bit Rows Tag Array Data Array Tag Array Data Array Cache Entry 93 7271 00 93 7271 00 MLO 004411 A row within a set corresponds to a cache entry so there are 64 entries in each set and a total of 128 entries in the entire cache Each entry contains a 22 bit tag block and a 72 bit 8 byte data block Figure 3 8 shows the organization of a cache entry 3 32 Hardware Architecture 3 3 2 2 Figure 3 8 Internal Cache Entry 93 7271 00 Tag Block Data Block MLO 004412 A tag block consists of a parity bit a valid bit and a 20 bit tag Figure 3 9 shows the organization of a tag block Figure 3 9 Internal Cache Tag Block 212019 00 Bit MLO 004413 A data block consists of 8 bytes of data each with an associated parity bit The total data capacity of the cache is 128 8 byte blocks or 1024 bytes Figure 3 10 shows the organization of a data block Figure 3 10 Internal Cache Data Block Data js 56 55 48 47 40 39 32 31 24 23 16 15 08 07 Eh EE MLO 004414 Internal Cache Address Translation Whenever the CVAX processor requires an instruction or data the contents of the internal cache are checked to determine if the referenced location is stored there The cache contents are checked by translating the physical address as follows e noncacheable
350. o display errors EF The ROM high and low byte identification words are incorrect EE ROM version numbers don t match ED ROM test patterns are incorrect EC ROM checksum is incorrect EO ROM tests exited successfully 2 Memory Test Codes DF DE DD D1 are displayed by the Scratch Memory tests that find and verify RAM used by ROM code and locate verify and initialize RAM for use by the console data structures The RAM is tested with a bit pattern test an address test and deared to 0 DF No memory present DE Memory could not be cleared 4 30 FIRMWARE continued on next page Table 4 5 Cont LED Test Number Code List Test LED Description No Sizing Memory D8 Full Memory Test Clearing Memory D7 Full Memory Test Memory Addressing Test D6 Full Memory Test Test Each Page of Memory D5 Full Memory Test Test Page Boundaries D1 Sizing Memory completed DO Scratch memory initialized and is usable 3 Console channel routine channel existence and verification Check to see if a console device responds to the console address If found the unit is tested to verify its operation Operation of the device s CSR addresses is verified characters are looped back the interrupt feature is exercised The console will be used after this point if it exists and is functional CF Console not found output directed to console discarded Not necessarily a failure CE Console detected CD
351. o modify the volatile data base you use the SET command to make modifications as in Example 4 5 FIRMWARE 4 45 Example 4 5 Setting Up Network to Run Test Programs set node rtv300 hard address 08 00 2B 12 BC 36 gt set node rtv300 service circuit qna 0 gt set node rtv300 load file user day test exe network service is disabled you must enable it for example set circuit qna 0 service enable When you boot from Ethernet MOP loads and starts the test program 4 10 Serial Line Boot Directions The following directions show how to set up a VMS system for serial down line loading of VAXELN system images to an rtVAX 300 target through the second console on the DUART 1 Toload the asynchronous DDCMP driver execute the following statements each time the system is booted RUN SYSSSYSTEM SYSGEN SYSGEN CONNECT NOA0 NOADAPTOR SYSGEN 77 2 Configure the asynchronous terminal port as a DDCMP port as follows SET TERM ddcu PROTOCOL DDCMP where 9915 device code e cis the controller designation e uis the unit number Note To ensure that these procedures are performed on each system startup you can enter the commands in steps 1 and 2 in the system startup file 3 Determine the DECnet name for the terminal port used to boot the rtVAX 300 do so change the third character of the VMS device name the in the ddcu format from a letter to the num
352. ocations 20008000 through 2000803F Refer to Section 3 6 1 and Table 3 17 for a full description The Network ID ROM provides a unique physical network address for the rtVAX 300 readable at locations 20008040 through 200080BF This address 15 predetermined by Digital and cannot be changed This network address 15 marked on the rtVAX 300 body 7 4 Network Interconnect Interface 7 6 Hardware Implementation Example A dual purpose ThinWire Attachment Unit Interface AUI design was chosen as the sample design because many designs now incorporate IEEE 802 3 network interfaces via either ThinWire or AUI The terms ThinWire and AUI should be understood Many aspects of these two interfaces are similar however detailed implementation of the two differs significantly The main difference lies in the connection of the network controller to the media ThinWire adapters are designed specifically to attach directly to the ThinWire RG58 like cable that is they employ an internal MAU contrast AUI interconnect never attaches directly to the media Instead they employ an IEEE 802 3 standard interface to a Media Attachment Unit MAU which will attach to the media Figure 7 1 shows a block diagram of the sample design The broken lines indicate the design s functional boundaries 7 6 1 Ethernet Interface An Overview Figure 7 3 shows a Ethernet interface block diagram This interface supports both direct ThinWire and AUI interfaces
353. offset into the ROM where execution is to begin 20 This longword contains the sum of the previous three longwords The rtVAX 300 supports two ROM address spaces e Cached ROM address space ROM address space Booting from Cached ROM Address Space Cached ROM address space is located in memory space to permit the caching of any data and instruction references to it Cached ROM address space provides 254M bytes of addressing It begins at address 1000 0000 and ends at address 1F DFFFFF Booting from cached ROM address space is selected by the device PRAO To speed the search for the ROM boot block only pages on 16K byte boundaries are checked for a ROM boot block Booting from ROM I O Address Space ROM 1 0 address space is located in user I O space Any data and instruction references to ROM located here are not cached ROM 1 0 address space starts at the base of user 1 0 space starting at address 20200000 Booting from ROM 1 0 address space is selected by the devices or PRB1 There is restriction on the upper bound of ROM 1 0 address space However the search for a ROM boot block is limited to 255 pages and is done on a page by page basis Bootstrap operation for the two devices PRBO and PRB1 is identical except that for PRB1 the ROM is copied to the first contiguous piece of good RAM in memory space large enough to hold the ROM image 4 50 FIRMWARE 5 Memory System Interface This chapter provid
354. ogged in MSER bits Machine check abort read invalidated 06 05 Write Machine check abort Request D stream Entry Logged in MSER bit read invalidated 06 Request I stream Halted Entry Logged in MSER bit read invalidated 06 The entire row in cache memory selected by the faulting address is invalidated whether or not the reference is cacheable The entries from both sets are invalidated Only DAL parity errors log status 8 3 2 Using the rtVAX 300 as a Bus Master In most bus interfacing applications the rtVAX 300 functions as a bus master The address space of the bus should be mapped to the 3005 1 0 space An interrupt controller is needed to handle and control interrupts that are generated on the bus this controller must interrupt the rtVAX 300 and provide an interrupt vector when the rtVAX 300 acknowledges the interrupt A bus cycle controller is also needed to control the bus protocol of the 1 0 bus correctly service bus access cycles from the rtVAX 300 This controller becomes fairly complex if multiple bus masters are allowed on the 1 0 bus Device Interfacing 8 7 8 3 3 Using 300 as Bus Slave certain applications rtVAX 300 functions as a slave processor on a system bus To do this a bus interface must be designed to interface the bus to dual ported memory on the rtVAX 300 This memory must map to the rtVAX 300 s O space and to some address space of the system bu
355. olation transformer and a 15 pin D sub connector to the rtVAX 300 Figure 7 2 shows the wiring requirements for the collision detect receive and transmit signals for this connector Figure 7 2 shows a jumper array to allow alternate support of a ThinWire interconnect Figure 7 5 shows the AUI connector and pinning 7 4 ThinWire Support The rtVAX 300 connects to a ThinWire Ethernet network through the DP8392 transceiver and a few other components An isolated 9V power source is needed to support the ThinWire connection The user s application can incorporate the design shown in Figure 7 5 which allows selection of either the Thickwire or the ThinWire configurations Network Interconnect Interface 7 3 Figure 7 2 Network Interconnect Isolation Transformer and Jumpers xn Tw a 300 2 XMT AUI w5 XMT XMIT 2 AUI XMIT 3 RCV 1 W4 COL RX 2 3 AUI_RCV COL 7 W3 RX 2 3 AUI RCV All etch to and from T1 to be of minimum length with each differential w2 pair having identical lengths and COLL paired runs 2 W1 COLL 2 COLL 3 MLO 006392 7 5 Ethernet Coprocessor Registers The rtVAX 300 Ethernet coprocessor is programmed by reading from and writing to a set of 16 registers at l
356. omer reserved Fault 0 XFC instruction instruction 18 Reserved operand 0 Not always recoverable abort 1C Reserved addressing Fault 0 mode 20 Access control violation Fault 2 Parameters are virtual address status code 24 Translation not valid Fault 2 Parameters are virtual address status code 28 Trace pending TP Fault 0 2C Breakpoint instruction Fault 0 30 Unused Compatibility mode in other VAX processors 34 Arithmetic Trap 1 Parameter is type code Fault continued on next page Hardware Architecture 3 25 Table 3 6 System Control Block Format SCB Interrupt Exception Param Offset eter Notes 38 3C Unused 40 CHMK Trap 1 Parameter is sign extended operand word 44 CHME Trap 1 Parameter is sign extended operand word 48 CHMS Trap 1 Parameter is sign extended operand word 4C CHMU Trap 1 Parameter is sign extended operand word 50 80 Unused 84 Software level 1 Interrupt 0 88 Software level 2 Interrupt O Ordinarily used for AST delivery 8c Software level 3 Interrupt O Ordinarily used for process scheduling 90 BC Software levels 4 15 Interrupt O CO nterval timer Interrupt O IPL is 1616 INTIM C4 Unused C8 Emulation start Fault 10 Same mode exception FPD 0 parameters opcode PC specifiers CC Emulation continue Fault 0 Same mode exception 1 no parameters DO DC Unused EO EC Reserved for customer or CSS use FO FC Unused Reserved to Digital 100
357. on No title to and ownership of the software is hereby ransferred The information in this software is subject to change without notice and should not be construed as commitment by Digital Equipment Corporation DIGITAL assumes no responsibility for the use or reliability of its software on equipment which is not supplied by DIGITAL Me Me Me Me Me Me Me Me User Boot Diagnostic ROM Sample 0 1 FACILITY rtVAX 300 User Boot Diagnostic Firmware ABSTRACT This module contains routines to provide user defined rtVAX 300 ROM based board level initialization and diagnostics It is a template intended to serve as the starting point for implementing rtVAX 300 User Boot and Diagnostic routines When used as a template the code and definitions for the sample routines should be modified and expanded as needed Assemble ROM based firmware modules as follows MACRO LIST OBJECT 300USERROM MAR KERMAC MLB LIBRARY Note that the above assumes that KERMAC MLB macro library can be found in your default directory Build an executable image by specifying the ROM s address as follows LINK SYSTEM X20080000 MAP FULL 300USERROM OBJ AUTHOR Realtime Software Engineering CREATION DATE 15 Feb 1991 MODIFIED BY modifier s name dd mmm yyyy VERSION svv u ep 01 modification description Ne Ne Ne Se Se Ne Se Ne Ne Ne Ne Ne Se Ne scs Ne Ne Ne Ne Ne
358. onsole emulation program Boot from ROM at location 10000000 in memory space Boot from ROM 1 0 space Copy ROM from I O space to memory space and then boot DECnet DDCMP boot using Channel B of DUART at 1200 bps DECnet DDCMP boot using Channel B of DUART at 2400 bps DECnet DDCMP boot using Channel B of DUART at 9600 bps Boot from Ethernet using standard MOP protocol Enable remote console and remote triggering 3 5 2 Console DUART Register Table 3 13 lists the addresses for the console registers and their functions 3 42 Hardware Architecture Table 3 13 Console Registers SCN 2681 DUART Address Read Function Write Function 20100000 20100004 20100008 2010000C 20100010 20100014 20100018 2010001C 20100020 20100024 20100028 2010002C 20100030 20100034 20100038 2010003C Channel A mode registers MRA2 Channel A status register SRA Reserved register Channel A receive holding register RHRA Input port change register IPCR Channel A B interrupt status register ISR Counter timer interval register upper CTU Counter timer interval register lower CTL Channel B mode register MRB1 MRB2 Channel B status register SRB Reserved register Channel B receive holding register RHRB Reserved register Input port register Start counter command register Stop counter command register Channel A mode registers
359. ontroller output delay 2x minimum propagation of 74F 00 Minimum 74F 711 delay Minimum 74F 04 delay DRAM row address hold time In this case DRAM row address hold time 50 ns 12 ns 2x2 ns 8 ns 4 5 38 ns Calculating DRAM Column Address Setup Time The memory controller asserts ENBCAS on the P1 edge following the assertion of RAS The CAS lines of the DRAMs assert after two minimum 74F 00 delays The SELCOL line which drives the column address onto the DRAM address bus does this two maximum 74F 00 gate delays after the falling edge of CLKB The column address setup time is calculated as follows SELCOL to CLKA rising edge 2 x maximum propagation of 74F 00 address MUX latch Maximum propagation of 74F 711 2 x minimum propagation of 74F 00 CAS decode latch Minimum CAS driver delay DRAM column address setup time this case DRAM column address setup time 25 ns 2x 5 ns 15 ns 2 2 ns 2 ns 6 ns Calculating DRAM Column Address Hold Time The INVADDR 3 2 lines assert on the P3 edge that follows the assertion of ENBCAS The column address hold time is calculated as follows CAS assertion to INVADDR 3 2 assertion ENBCAS memory controller output propagation delay 2 x maximum propagation of 74F 00 CAS driver delay Minimum INVADDR 3 27 memory controller delay Minimum 74F 86 delay Memory System Interface 5 27 5 10 4 5 10 4 1 5 10 4 2 Minimum 746 7
360. oot These memory elements have a specification for the amount of undershoot that can safely be tolerated If this value is exceeded the DRAM can corrupt its stored data or can be damaged permanently Many techniques can be used to reduce the amount of overshoot and undershoot that the DRAM experiences The RAS CAS WE and address lines connecting to the DRAMs must be made as short as possible to reduce the lines inductance and capacitance These lines should be daisy chained to all of the connection points Series dampening resistors should be added to all of these lines as close to the MU X outputs as possible as shown in Figure 5 3 The data and strobe signal lines of the rtVAX 300 are driven by an ACTQ 244 or ACTQ 245 These CMOS drivers can also generate a fair amount of overshoot and undershoot Therefore it is good practice to add series termination resistors for these lines on the application module to improve signal integrity These resistors slow the rise and fall times of the DRAMs reducing the reflections The value of these resistors is determined measuring the overshoot and rise time of these signal lines on the actual PC board prototype The resistor value should be the lowest that gives an undershoot voltage below that tolerated by the DRAMs that are used Shunt resistors can also be used at the end of these lines as terminators 5 16 Memory System Interface 5 9 7 DRAM Data Latches The latches shown in Figure 5 15
361. or aborts all processes and starts the reset sequence After completing the reset and self test sequence the Ethernet coprocessor sets bit CRS5 lt 31 gt Clearing this bit has no effect Note The CSR5 lt 05 gt value is unpredictable on read after hardware reset 3 6 1 6 System Base Register CSR7 This CSR contains the physical starting address of the rtVAX 300 system page table This register must be loaded by rtVAX 300 software before any address translation occurs so that memory will not be corrupted Figure 3 23 shows the format of CSR7 Table 3 24 describes its bit structure Hardware Architecture 3 61 Figure 3 23 5 7 Format 313029 00 ofo System Base Address CSR7 MLO 004421 Table 3 24 CSR7 Bits Bit Name Access Description 29 00 SB R W System base address The physical starting address of the rtVAX 300 System Page Table Not used if VA Virtual Addressing is cleared in all descriptors Caution This register should be loaded only once after a reset Subsequent modifications of this register may cause unpredictable results 3 6 1 7 Watchdog Timer Register CSR9 The Ethernet coprocessor has two timers that restrict the length of time during which the chip can receive or transmit These watchdog timers are enabled by default and assume the default values after hardware or software resets Figure 3 24 shows the format of the watchdog timer register Table 3 25 describes its bit structure Figu
362. ory management disabled A value of 0 in this field implies that no routine has been provided and no call is made in this case The console program does not wait for the hardware that is used by the console device to complete its current operation become stable before calling this routine This field is zeroed at power on 4 8 1 2 2 SCR A RESTORE CONSOLE This is the longword physical address of a restore routine supplied by the operating system This routine is called as the console program exits from console mode The routine gives the operating system the opportunity to restore the original hardware state when the console program no longer needs to use the console device This routine is called with J SB instruction at IPL 1F4g in kernel mode with memory management disabled A value of 0 in this field implies that no routine has been provided no call is made in this case This field is zeroed at power on 4 8 1 3 Input Parameters The user defined initialization routine is called with three parameters e Parameter 1 AP 44 is the address of the console mailbox Parameter 2 is the address of the memory bitmap descriptor Section 4 8 1 4 defines this descriptor e Parameter AP 412 is the address of a scratch memory area FIRMWARE 4 41 4 81 4 Memory Bitmap Descriptor Format Figure 4 10 Memory Bitmap Descriptor 31 16 15 0 Bitmap Length in Bytes Bitmap Starting Address MLO 006374 Each bit
363. own for halt code of 3 SAVPSL 13 87 Saved restart code SP Current interrupt stack PSL 0412 0000 PC 20040000 MAPEN 0 ICCS 0 for a halt code of 3 MSER 0 for a halt code of 3 CADR O for a halt code of 3 internal cache is also flushed SISR 0 for a halt code of 3 ASTLVL 0 for a halt code of 3 else Undefined Hardware Architecture 3 27 The firmware uses the halt code in combination with any hardware event indicators to dispatch the execution or interrupt that caused the halt to the appropriate firmware routine either console emulation power up reboot or restart Table 3 7 and Table 3 8 list the interrupts and exceptions that can cause halts along with their corresponding halt codes and event indicators Table 3 7 Nonmaskable Interrupts That Can Cause a Halt Halt Code Interrupt Condition 2 External Halt CVAX HALT pin asserted 3 Hardware Reset CVAX RESET pin negated Table 3 8 Exceptions That Can Cause a Halt Halt Code Exception Condition 6 Halt instruction executed in kernel mode Exceptions While Servicing an Interrupt or Exception 4 Interrupt stack not valid during exception 5 Machine check during normal exception 7 SCB vector 0 5 lt 1 0 gt 11 8 SCB vector 5 lt 1 0 gt 10 A executed while on interrupt stack B executed to the interrupt stack 10 ACV or TNV during machine check exception 11 ACV or TNV during kernel stack not valid exception
364. p ddvz decimal divide by zero trap continued on next page Hardware Architecture 3 3 Table 3 1 Cont Microcode Assisted Emulated Instructions OP Mnemonic and Arguments Description nzvc Exceptions F9 CVTLP srcrl dstlen rw Convert long to packed 5 dstaddr ab 36 CVTPL srden rw srcaddr ab Convert packed to long 5 dst wl 08 CVTPS srden rw srcaddr ab Convert packed to leading 0 rsv dstlen rw dstaddr ab separate 09 CVTSP srden rw srcaddr Convert leading separate 0 5 dstlen rw dstaddr ab to packed 24 CVTPT srden rw srcaddr ab Convert packed to trailing 0 5 tbladdr ab dstlen rw dstaddr ab 26 CVTTP srden rw srcaddr ab Convert packed to trailing 0 rsv tbladdr ab dstlen rw dstaddr ab 27 divrlen rw divraddr ab Divide packed FEKO rsv dov ddvz divdlen rw quolen rw quoaddr ab 38 EDITPC srden rw srcaddr ab Edit packed to character rsv pattern ab dstaddr ab string 39 MATCHC objlen rw objaddr ab Match characters 0 00 srden rw srcaddr ab 34 MOVP len rw srcaddr ab Move packed 00 dstaddr ab 2bE srden rw srcaddr ab Move translated 0x fill rb tbladdr ab dstlen rw characters dstaddr ab 2F MOVTUC srclen rw srcaddr ab Move translated until esc rb tbladdr ab dstlen rw character dstaddr ab 25 MULP mulrlen rw mulraddr ab Multiply packed
365. part done flag captured in PSL lt 27 gt If the first part done flag is set the error is recoverable If the first part done flag is cleared then the VAX can t restart flag must also be deared for the error to be recoverable otherwise the error is unrecoverable and depending on the current mode either the current process or the operating system should be terminated The information pushed onto the stack by this type of machine check is from the instruction that caused the machine check 3 20 Hardware Architecture Error Description 1 The CFPA chip detected a protocol error while attempting to execute a floating point instruction 2 The CFPA chip detected a reserved instruction while attempting to execute a floating point instruction 3 The chip returned an illegal status code while attempting to execute a floating point instruction CPSTA lt 1 0 gt 102 4 The CFPA chip returned an illegal status code while attempting to execute a floating point instruction CPSTA lt 1 0 gt 102 Memory management errors indicate that the microcode in the CVAX processor chip detected an impossible situation while performing memory management functions The most likely cause of this type of a machine check is a problem internal to the CVAX chip Machine checks due to memory management errors are nonrecoverable Depending on the current mode either the current process or the operating system should be terminated The
366. performs the following functions Sequences the RAS CAS and address enable control lines for memory access and refresh on the rtVAX 300 application example Arbitrates between refresh requests and memory accesses Controls the the RDY L signal to the rtVAX 300 to mark the end of a memory access cyde Table 5 11 lists pins settings and comments Table 5 11 Memory Subsystem Sequencer State Machine PAL Comment Pins Setting Input 1 CLKA 2 SYNCHAS 3 IDS 4 CLKB 5 4 6 IL WRITE 7 SELRAM 5 42 Memory System Interface The rtVAX 300 A phase of the CVAX clock used to trigger all state transitions The rtVAX 300 asserts this signal to indicate that the address cyde status information is valid and that the rtVAX 300 is starting a memory access The signal remains asserted until the end of the memory access cyde and is synchronized to deassert on the CLKA positive edge This rtVAX 300 data strobe signal output is asserted when the DAL bus is ready to transfer data This rtVAX 300 B phase of the processor dock is added here in case extra states need to be clocked off its edge This signal is asserted when the rtVAX 300 is in the P3 or P4 state and deasserted when the rtVAX 300 is in the P1 or P2 state This state machine uses the signal to determine when to assert the DRAM READY line This latched write signal output from the rtVAX 300 is asserted during a write cycle and unasserted for reads It affects th
367. processor initialization is performed The following registers are set all values in hexadecimal 4 16 FIRMWARE PSL 041 0000 ASTLVL SISR 5 CADR PC 200 ISP 200 O O Ff other registers are unpredictable 4 3 6 9 Repeat 4 3 6 10 R EPEAT COMMAND The console program repeatedly executes the specified command Repeated execution of a command stops when the operator types or when abnormal circumstance occurs Any console command may be specified for the command Set SE T gt VALUE Note saved values are lost on power failure or reset Set the console parameter to the indicated value The following console parameters and their acceptable values are defined e BOOT Sets the default boot device The value must be a valid boot device name as specified in Table 4 9 in the device field e BFLG Set the default boot flags The value must a hexadecimal number of up to eight characters The value that is entered is not checked for validity e HALT Set the default halt action and halt switch codes This code specifies the default action the console should take for all error halts and halt instructions FIRMWARE 4 17 TRI G Set remote trigger to be enabled or disabled This allows a remote system to request a local boot of the system If the Ethernet self test has failed then this command is illegal The powe
368. r SIRR Software interrupt request internal processor register SISR Software interrupt summary internal processor register SLR System length internal processor register SLU Serial line unit SRA DUART channel A status register Acronyms 3 Definition SRAM SRB SSP TBCHK TBIA TBIS THRA THRB USP WR XMT Static random access memory DUART channel B status register Supervisor stack pointer internal processor register Translation buffer check internal processor register Translation buffer invalidate all internal processor register Translation buffer invalidate single internal processor register DUART channel A Tx holding register DUART channel B Tx holding register User stack pointer internal processor register Write line bus interface signal Ethernet transmit data bus interface signal B 4 Acronyms Address Assignments This appendix covers the following topics e Memory space address assignment Table C 1 e nput output space Table C 2 Local register input output space Table C 3 Table C 1 Memory Space Address Assignment Address Range Contents 00000000 0FFFFFFF Cached read write memory space 256M bytes 10000000 1F DFFFFF Cached read only memory space 254M bytes 1FE00000 1FFFFFFF Reserved memory space 2M bytes Table C 2 Input Output Space Address Range Contents 20000000 201FFFFF Local register 1 space 2M bytes 20200000 3FFFFFFF Use
369. r 1 space 510M bytes Address Assignments 1 Table C 3 Local Register Input Output Space Address Range Contents 20000000 20007F F F 20008000 2000803F 20008040 2000F F F F 20010000 2001007F 20010080 2003F F EB 2003FFEC 20040000 2007FF FF 20080000 200F FFFF 20100000 2010003F 20100040 2010F FFF 20110000 20110004 201FFFFB 201F FFFC Reserved local register I O space Ethernet coprocessor register 1 space Reserved local register I O space Network interface address ROM 1 space Reserved local register I O space Boot register rtVAX 300 boot diagnostic ROM space User boot diagnostic ROM space Console DUART register 1 space Reserved local register space Memory system control status register Reserved local register I O space LED display status register C 2 Address Assignments D User Boot Diagnostic ROM Sample This appendix contains a template of the functions that might be incorporated in a user supplied boot and diagnostic ROM title 300USERROM rtVAX 300 User Boot Diagnostic Firmware ident rtVAX 300 V1 0 00 COPYRIGHT c 1991 by Digital Equipment Corporation Maynard Massachusetts his software is furnished under a license and may be used and copied nly in accordance with the terms of such license and with the nclusion of the above copyright notice This software or any other opies thereof may not be provided or otherwise made available to any ther pers
370. r Register 8 19 8 5 5 2 Interrupt Reset and Hold Bits 8 24 8 5 6 Base Address Register 8 24 8 6 Reset Power U 8 24 8 7 Halting the 550 8 26 8 8 System 5 5 8 27 A Physical Electrical and Environmental Characteristics A 1 Physical 5 5 A 1 A 2 Electrical 5 7 Environmental 5 5 10 B Acronyms C Address Assignments D User Boot Diagnostic ROM Sample Xi E Sample C Program to Build Setup Frame Buffer Examples 8 1 3 2 4 1 4 2 4 3 4 4 4 5 E 1 Figures Xii 2 1 2 2 2 3 2 4 2 5 d Mdb 4 dedu dori T AP d C nm Perfect Filtering Buffer Imperfect Filtering Buffer Firmware Dispatch Code Sample Power On Display Sample Halt Action Display Self Looping Test Program Setting Up the Network to Run Test Programs Hash Filtering Setup Frame Buffer Creation C Program rtVAX 300 Block Diagram Typical rtVAX 300 Environme
371. r on condition for this is determined by BOOT 3 gt 4 3 6 11 Show SH OW gt The indicated console parameter is displayed BOOT Displays the default boot device as defined above If no boot device has been specified the field appears as four dots BFLG Displays the default boot flags If no default flags have been specified then 00000000 is displayed HALT Shows the default halt action code ETHER or ETHERNET Displays the hardware Ethernet address The Ethernet address ROM is validated and is displayed as ID YY YY YY YY YY YY where is a valid 2 digit hexadecimal number If the Ethernet address ROM is invalid then ID XX XX XX XX XX XX is displayed to indicate that the Ethernet address ROM is invalid MOP Shows the state of the enable network listener bit If the returned value is 0 the network listener is disabled if 1 the listener is enabled Displays information concerning the rtVAX 300 system memory The format of the display is gt gt gt SHOW MEM 00400000 00000000 D400 003FFFFF The first 8 character field displays the total amount of memory in the system including the console data structures The second 8 character field shows the first address of 256K bytes of contiguous memory The final line of the display shows the address range of the area of memory that is not available to the operating system This includes the area of memory that
372. rame is rejected This filtering mode is called imperfect because multicast frames not addressed to this station may slip through but it still reduces the number of frames that the rtVAX 300 must process Figure 3 32 shows the format for the hash table and the physical address Hardware Architecture 3 83 3 84 Figure 3 32 Imperfect Filtering Setup Frame Buffer Format 31 16 15 0 lt 3 0 gt HASH FILTER 00 lt 7 4 gt HASH FILTER 01 HASH FILTER 02 bytes HASH FILTER 03 HASH FILTER 14 63 60 HASH FILTER 15 67 64 PHYSICAL ADDRESS L s INDIVIDUAL GROUP Rt lt 71 68 gt XXXXXXXXX lt 75 72 gt lt 127 120 gt XXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXX XXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX don t care Bits are sequent ially numbered from right to left and down the table For example if the destination address 8 0 is 33 the Ethernet coprocessor examines bit 1 the second longword Example 3 2 illustrates an Imperfect Filtering Setup frame buffer Appendix E shows a C program to compute the setup frame buffer for the hashing filtering mode Hardware Architecture Example 3 2 Imperfect Filtering Buffer Ethernet addresses to be filtered 25 00 25 00 27 00 A3 C5 62 3F 25 87 D9 C2 C0 99 0B 82 7D 48 4D FD CC 0A E7 C1 96 36 89 DD 61 CC 28 5
373. re 3 24 CSR9 Format 31 1615 00 Receive Watchdog Time Out RT Transmit Watchdog Time Out TT CSR9 MLO 004422 3 62 Hardware Architecture Table 3 25 5 9 Bits Bit Name Access Description 15 00 31 16 TT RT R W R W Transmit Watchdog Time Out The transmit watchdog timer protects the network against Ethernet coprocessor transmissions of overlength packets If the transmitter stays for 16 cycles of the serial dock the Ethernet coprocessor cuts off the transmitter and sets the CSR5 lt 06 gt bit If the timer is set to zero it never times out The value of TT is an unsigned integer With a 10 MHz serial clock this provides a range of 1 6 us to 100 ms The default value is 1250 corresponding to 2 ms Receive Watchdog Time Out The receive watchdog timer protects the rtVAX 300 microprocessor against other transmitters sending overlength packets on the network If the receiver stays on for RT 16 cycles of the serial clock the Ethernet coprocessor cuts off reception and sets the CSR5 lt 05 gt bit If the timer is set to zero it will never time out The value of RT is an unsigned integer With a 10 MHz serial clock this provides a range of 1 6 us to 100 ms The default value is 1250 corresponding to 2 ms Note An Rx or Tx watchdog value between 1 and 44 is forced to the minimum time out value of 45 72 us 3 6 1 8 Revision Number and Missed Frame Count CSR10 This
374. register contains a missed frame counter and Ethernet coprocessor identification information Figure 3 25 shows the format of CSR10 Table 3 26 describes its bit structure Figure 3 25 CSR10 Format 31 DIN 28 27 24 23 HRN 2019 1615 00 FRN MFC CSR10 MLO 006383 Hardware Architecture 3 63 Table 3 26 CSR10 Bits Bit Name Access Description 15 00 19 16 FRN R 23 20 HRN R 27 24 31 28 DIN R Missed Frame Count Counter for the number of frames that were discarded and lost because rtVAX 300 receive buffers were unavailable The counter is cleared when read by the rtVAX 300 Firmware Revision Number Stores the internal firmware revision number for this particular Ethernet coprocessor Hardware Revision Number Stores the revision number for this particular Ethernet coprocessor Reserved Read as zeros Chip Identification Number Determines whether this is an SGEC or an SGEC compatible device 3 6 1 9 Boot Message Registers CSR11 CSR12 CSR13 These registers contain the boot message verification and processor fields Table 3 27 describes their bit structure Table 3 27 CSR11 CSR12 CSR13 Bits Register Bit Name Access Description CSR11 31 00 VRF lt 31 00 gt CSR12 31 00 VRF 63 327 CSR13 07 00 PRC R W Boot Message Verification field lt 31 00 gt R W Boot Message Verification field lt 63 32 gt R W Boot Message Processor field 3 6 1 10 Breakpoin
375. required for long term reliability A minimum total trace or plane area of 6 45 cm 1 inch is recommended to take advantage of the 3 5 W power dissipation rating of the chip package at 25 C Do not use heat relieved mounting holes for these pins e Connect the CDS pin independently to the coaxial shield The CDS collision detect sense pin is provided for accurate detection of collision levels on the coaxial cable To avoid altering the collision threshold due to intermediate ground drops from pin 16 to the coaxial shield attach pin 16 independently to the coaxial shield by a short heavy conductor During ESD testing any potential differences between power ground pin 10 and the CDS pin pin 16 can cause some internal functions to latch up e Place the decoupling capacitor connected across GND and VEE as close to the transceiver chip as possible to minimize the trace inductance e Etch runs from the pins of the differential pairs COL pins 1 and 2 RX pins 3 and 6 and XMIT pins 7 and 8 must be parallel pairs of minimum equal lengths The possibility of one side of the differential pair picking up more noise than the other is minimized when the lines are balanced e For ThinWire designs maintain a voltage isolation barrier of 500V RMS between input and output circuits Figure 7 7 shows the typical layout of a ThinWire interface 7 16 Network Interconnect Interface Figure 7 7 Network Interconnect Layout of ThinWire Medi
376. rfacing DSP DMA Controller 8 55 8 29 Device Interfacing D A A D Interface 8 57 8 30 I O Device Interfacing rtVAX 300 ThinWire Thickwire Network Connecdions 8 59 8 31 1 Device Interfacing 300 I O Pin Connectors 8 61 8 32 Device Interfacing Decoupling 5 8 63 1 rtVAX 300 Mechanical A 3 A 2 rtVAX 300 Top 4 A 3 rtVAX 300 Bottom View A 5 4 rtVAX 300 Side View 6 Tables 2 1 Bus Interface 5 5 2 8 2 2 rtVAX 300 Processor Pin Description 2 9 2 3 Lud ware PE ERR Exe 2 12 2 4 Byte 3 ole RV owe eee ed Po 2 14 2 5 rtVAX 300 Bus Status 5 5 2 18 2 6 Interrupt Priority Assignments 2 19 2 7 rtVAX 300 Responses to a Quadword Transfer Read Cyde 2 30 2 8 rtVAX 300 Responses to Octaword Transfer Read Cycle 2 33 3 1 Microcode Assisted Emulated Instructions 3 3 3 2 Processor Status Longword Bit Map 3 6 3 3 Internal Processor Registers 3 8 3 4 erneut c ER epe ERE RES 3 15 3 5 Exceptions RR xx LER ead ER LESER ER 3 18 3 6 System Control Block Fo
377. rmat 3 25 3 7 Nonmaskable Interrupts That Can Cause Halt 3 28 3 8 Exceptions That Can Cause a Halt 3 28 3 9 System Identification Register 3 29 3 10 Cache Disable Register Fields 3 36 3 11 Memory System Error Register 05 3 39 3 12 Boot Options ers du ent ete Re 3 42 3 13 Console Registers SCN 2681 3 43 xvi 3 14 3 15 3 16 3 17 3 18 3 19 3 20 3 21 3 22 3 23 3 24 3 25 3 26 3 27 3 28 3 29 3 30 3 31 3 32 3 33 3 34 3 35 3 36 3 37 3 38 3 39 3 40 3 41 3 42 4 1 Memory System Control Status Register Fields LED Display Status Register Fields LED Display Chart Ethernet Coprocessor Registers CSROBits m Rec CSRI hue uem CSR2 BitS CSR3 CSR4 5 CSR5 Bits bets CSROBItS umi REI ERES Bits je CSRO BIES tee 65810 i wast fe settee CSR11 5 12 CSR13 5 5 14 5 ai 25815 RDESO 5 RDESIFields sk RDES2 5 RDES3 5
378. rnet coprocessor When cleared indicates the descriptor is owned by the rtVAX 300 The Ethernet coprocessor clears this bit upon completing processing of the descriptor and its associated buffer Table 3 36 TDES1 Fields Bit Name Descriptor 23 24 25 26 VT LS FS Virtual Type In case of virtual addressing TDES1 lt 30 gt 1 indicates the type of virtual address translation When clear the buffer address TDES3 is interpreted as a SVAPTE System Virtual Address of the Page Table Entry When set the buffer address is interpreted as a PAPTE Physical Address of the Page Table Entry Meaningful only if TDES1 lt 30 gt is set Interrupt on Completion When set the Ethernet coprocessor sets CSR5 lt 01 gt after this frame has been transmitted To take effect this bit must be set in the descriptor where bit 25 is set Last Segment When set indicates that the buffer contains the last segment of a frame First Segment When set indicates that the buffer contains the first segment of a frame continued on next page Hardware Architecture 3 75 Table 3 36 Cont TDES1 Fields Bit Name Descriptor 27 AC 29 28 DT 30 VA 3 76 Hardware Architecture Add CRC disable When set the Ethernet coprocessor will not append the CRC to the end of the transmitted frame To take effect this bit must be set in the descriptor where bit 26 is set Note If the transmitted frame is
379. rocessor contains internal processor registers as described in Chapter 3 Table 3 3 lists and describes internal processor registers Technical Specification 2 21 Figure 2 6 rtVAX 300 Memory and I O Space 3FFFFFFF User I O Space 20200000 201FFEFF Local Register 20000000 1FFFFFFF Reserved 1FE00000 1FDFFFFF Cache ROM 10000000 System RAM 00000000 The rtVAX 300 accesses memory in bytes words 2 bytes longwords 4 bytes quadwords 8 bytes or octawords 16 bytes However quadword and octaword accesses are restricted to the system RAM portion of the memory space The rtVAX 300 read write memory is organized into four banks as shown in Figure 2 7 The rtVAX 300 issues longword addresses on the DAL bus You can read from or write to any byte of any memory location by using the different byte mask signals 2 22 Technical Specification LED Status Register Memory System CSR Console Registers User Boot or Diagnostic ROM Boot ROMs NI ID ROM Ethernet Registers 201FFFFF 201FFFFC 20110004 20110000 2010003F 20100000 200FFFFF 20080000 2007FFFF 20040000 2003FFFF 2003FFEC 2001007F 20010000 2000803F 20008000 20000000 MLO 006366 Figure 2 7 rtVAX 300 Memory Bank Organization BM lt 3 gt lt 2 gt lt 1 gt lt 0 gt MLO 006369 2 5 1 Address Decode and Boot ROM The internal ROM address latch logic latches the address on the DAL bus an
380. rocessor raises the IPL to 171g after responding to interrupts generated by the assertion of IRQ lt 3 gt L IRQ lt 2 gt L IRQ lt 1 gt L or IRQ lt O gt L The rtVAX 300 maintains the at the priority of the interrupt if DAL 002 is zero Hardware Architecture 3 15 3 1 12 2 Three IPRs control the interrupt system IPR 18 the interrupt priority level register IPL IPR 20 the software interrupt request register SIRR and IPR 21 the software interrupt summary register 5158 IPL is used for loading the processor priority The SIRR is used for generating software interrupt requests The SISR records pending software interrupt requests at levels 1 through 15 Figure 3 3 shows the format of these registers Refer to the VAX Architecture Reference Manual for more information on these registers Figure 3 3 Interrupt Registers 21 0504 00 Ignored Returns 0 PSL lt 20 16 gt 31 0403 00 31 1615 00 o pas DiC By A 91 81 7161514131211 MLO 004407 Halting the Processor The rtVAX 300 is a dynamic device and cannot be halted by disabling its clock input CLKIN The CPU is halted either by executing the HALT instruction in kernel mode or by asserting the HLT L signal Assertion of the HLT L signal results in the execution of a nonmaskable interrupt by the CPU HLT L is edgesensitive and must be asserted for at least two microcycles to guarantee its being sensed by the CPU In order for
381. rom the external SIA The Ethernet coprocessor uses the decoded clock to read the data into its internal FIFO receive buffer The data is deserialized and the destination address is checked If the message is for the Ethernet coprocessor a CRC value for the received data is calculated and compared to the CRC checksum at the end of the frame If there is a CRC error an error bit is set in the receive descriptor The Ethernet coprocessor notifies the rtVAX 300 processor of all received frames including those with CRC errors and framing errors Frames less than 64 bytes long are not delivered to the rtVAX 300 processor unless the Ethernet coprocessor is programmed to do so 3 6 5 Diagnostics and Testing The Ethernet coprocessor supports three levels of testing and diagnostics First Level Error reporting during normal operation e Second Level system software controlled diagnostic features Third Level Hardware diagnostic mode which allows access to the internal data paths of the Ethernet coprocessor 3 6 5 1 Error Reporting The Ethernet coprocessor reports error conditions that relate to the network as a whole or to individual data frames Network related errors are recorded as flags in one or more of the Ethernet coprocessor s CSRs and result in an interrupt being posted to the rtVAX 300 CVAX processor Frame related errors are written to the descriptor entries of the corresponding frame Table 3 42 lists reported errors by dass
382. rs Run etch to these pins as parallel pairs maintaining equal etch length 7 6 3 2 DP8392 Transceiver This section discusses e External components Section 7 6 3 2 1 Layout considerations Section 7 6 3 2 2 Additional application hints Section 7 6 3 2 3 7 6 3 2 1 External Components The following paragraphs list and discuss external components Pulldown Resistors The ThinWire receive and collision balanced differential line drivers from the transceiver chip need four pulldown resistors to VEE Being external to the chip they allow setting of the voltage swings required to drive the differential lines dissipate power outside of the chip which adds to long term reliability In addition they are used with the transformer to control the differential undershoot which occurs when the drivers reset In ThinWire designs with integrated transceivers the transceiver is directly connected to isolation transformers In this case higher value pulldown resistances up to 1 5K 02 may be used to save power still provide the necessary AC voltage swing The use of resistances greater than 1 5K 2 is not justified by the amount of power saved and results in too low a signal for proper operation of the SIA receiver squelch e Diode The requirements for the capacitance added by the transceiver chip to the ThinWire coaxial cable are strict The transceiver along with the media dependent interface is allotted 10 pF in a ThinWire
383. rtVAX 300 Hardware User s Guide Order Number EK 382AB UG 002 This manual contains technical and physical specifications of the rtVAX 300 processor and information necessary for configuring it into host and target configurations that is information on the following interfaces memory system console and boot ROM network interconnect and 1 device Revision Update Information This manual supersedes the rtVAX 300 Hardware User s Guide EK 382AA UG 001 Software Revision VAXELN Version 4 2 Hardware Revision rtVAX 300 Version C1 Firmware Revision Version 1 1 Digital Equipment Corporation Maynard Massachusetts First Printing 1990 Revised April 1991 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document Any software described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license No responsibility is assumed for the use or reliability of software or equipment that is not supplied by Digital Equipment Corporation or its affiliated companies Restricted Rights Use duplication or disdosure by the U S Government is subject to restrictions as set forth subparagraph c 1 ii of the Rights in Technical Data and Computer Software dause at DFARS 252 2
384. ry this procedure has started For Ethernet and serial line boots a host system has offered to down line load an operating system to the rtVAX 300 and load of the operating system has started 00 0 The load of the operating system from the host or copying verification of ROM is complete and control is being transferred to the loaded operating system When the system is booted a positive indication of boot status is returned in the processor LED display and on the console terminal The loaded firmware may be an operating system or a secondary loader The name of the boot device appears on the console terminal The value 2 appears on the console terminal and the processor LEDs to indicate that the bootstrap device is about to be accessed The value 1 appears on the console terminal and the processor LEDs to indicate that the rtVAX 300 firmware has found the secondary bootstrap image on the boot device and is now reading the image into physical memory For ROM boots the ROM boot block has been located and copied to memory if the boot device was For Ethernet and Serial Line boots a host system has volunteered is downline loading the rtVAX 300 system The value 0 appears on the console terminal and the processor LEDs to indicate that the rtVAX 300 resident firmware is now transferring control to the operating system or secondary bootstrap FIRMWARE 4 27 A typical console display during the boo
385. ry System Interface 5 33 Table 5 9 Application Module Address Decoder PAL Pin Description Input 1 AS 2 DAL 22 3 DAL23 4 DAL 24 5 DAL25 6 DAL 26 7 DAL27 8 DAL 28 9 DAL 29 10 CSDPO 11 CSDP1 13 CSDP2 14 CSDP4 15 IDS 16 IWR Output 23 ISELRAM 22 NACKIPR 21 IENBCCTLDPE 20 CYCRES 5 34 Memory System Interface Figure 5 10 shows the RAM memory map Table 5 10 lists the corresponding equations Figure 5 10 RAM Memory Memory Locations DAL lt 29 2 gt Device Selected 29 2423 16 15 0807 02 9 00000000 003FFFFF 000000 XXXXXXXX XXXXXX MLO 004435 Table 5 10 Application Module Address Decoder Equations Line Equals SELRAM D IDAL29 amp DAL28 amp DAL27 amp DAL26 amp IDAL25 amp DAL24 amp DAL23 amp DAL22 SELRAM AR CYCRES IACKIPR D IWR amp ICSDP2 amp CSDP1 amp CSDPO CSDP2 amp CSDP1 amp CSDPO IACKIPR AR CYCRES CYCRES IAS amp IACKIPR SELRAM ENBCCTLDPE DS amp SELRAM Memory System Interface 5 35 Figure 5 11 DAL 17 DAL 16 DAL 15 DAL 14 DAL 13 DAL 12 DAL lt 11 gt H DAL 10 DAL 9 H Sample Design Address Latches Address Latches 8BF 8 Bit Latch 74 373 8BF 8 Bit Latch 74 373 DAL 8 DAL 7 DAL 6 DAL 5 DAL 4 DAL 3 DAL 2 ASL LADDR 17
386. s It is useful to construct a few CSRs that allow the master processor on the system bus to interrupt the rtVAX 300 and give status information In addition the rtVAX 300 should be able to interrupt the master processor 8 3 4 Building a DMA Engine for the rtVAX 300 8 8 The rtVAX 300 allows the peripherals to request the DAL bus and become DAL bus master When the rtVAX 300 has given bus mastership to the external device the rtVAX 300 tri states its DAL 31 00 AS L DS L WR L BM 3 0 and CSDP lt 4 0 gt L lines DMA peripheral must now drive each of these lines with the same protocol as the rtVAX 300 AII control signals must be pulled up to prevent accidental assertion when their lines are first tri stated It is also good practice to pull up the DAL 31 002 BM 3 05 CSDP 4 07 L lines to prevent oscillation when these lines are not driven The DMA peripheral transfers information in the following sequence 1 The DMA device asserts the DMR L signal requesting to become DAL bus master and waits for the assertion of DMG L 2 ThertVAX 300 finishes the present transfer cycle tri states all signal lines and asserts DMG L 3 The DMA device drives the DMA address on the DAL bus the cyde status onto CSDP 4 0 and the BM 3 0 lines which are the byte access information along with the WR L and DPE L lines The DMA device asserts AS L This is the P1 dock phase The DAL 31 00 CSDP
387. s interface signal CLKIN System clock input signal CLK20 20 MHz clock output bus interface signal COL Ethernet collision detect bus interface signal CONE Console enable signal CRA DUART channel A command register CRB DUART channel B command register CSDP Cyde status data parity bus interface signal CSRA DUART channel A dock select register Acronyms 1 Definition CSRB CTL CTU CVAX DAL DMA DMG DMR DPE DRAM DS DSP DUART ERR ESP GND HLT 5 IMR IPCR IPL IPR IRQ ISP ISR KSP MAPEN MEMERR MRA MRB MSER B 2 Acronyms DUART channel B dock select register DUART counter timer register lower DUART counter timer register upper CMOS VAX microprocessor the rtVAX 300 processor s CPU Data and address lines Direct memory access DMA grant bus interface signal Direct memory request bus interface signal Data parity enable bus interface signal Dynamic random access memory Data strobe bus interface signal Digital signal processor Dual universal asynchronous receiver transmitter Bus error input interface signal Executive stack pointer internal processor register 5V ground return signal Halt processor bus interface signal Interval clock control and status internal processor register DUART channel A and B interrupt mask status register DUART input port change register Interrupt priority level Internal processor register Interrupt request bus interface signal Interrupt
388. s transferred to user s code by CONTINUE command 02 Attempting boot 01 Boot host found or ROM bootblock located 00 Control passed to downline loaded code or external ROM code Once control is passed to the loaded code the state LEDs will only have meaning as defined by that code Caution User code may modify the display without affecting the ROM code However such modifications may cause confusion if the user believes the status was caused by the ROM code FIRMWARE 4 33 4 8 User Defined Board Level Boot and Diagnostic ROM An optional user defined initialization routine and up to seven user defined self test routines can be located in user ROM This 32 bit wide user ROM is located at a starting address of 20080000 of physical 1 space This ROM is optional and is not necessary for the normal operation of the firmware initialization and self test routines On power up the firmware runs preliminary self tests and then checks to see if a ROM exists at location 20080000 If a ROM responds to that address the console program checks for a user supplied ROM initialization routine in user ROM before executing the full self tests If the routine is found the ROM initialization routine is called Once the rtVAX 300 firmware regains control from the user ROM initialization routine the rtVAX 300 completes its self test If the ROM exists at location 20080000 it is checked again for user supplied self test routines
389. sed Frame Count see Section 3 6 1 8 2000802C CSR11 Boot Message Register see Section 3 6 1 9 20008030 CSR12 Boot Message Register see Section 3 6 1 9 20008034 CSR13 Boot Message Register see Section 3 6 1 9 20008038 CSR14 Breakpoint Address Register see Section 3 6 1 10 2000803C 5 15 Monitor Command Register see Section 3 6 1 11 3 6 1 1 Vector Address IPL Sync Asynch CSRO This register must be the first one written by the rtVAX 300 because the Ethernet coprocessor may generate an interrupt on parity errors during rtVAX 300 writes to CSRs Caution A parity error that occurs while the rtVAX 300 is writing to CSRO may cause an rtVAX 300 failure due to an erroneous interrupt vector To 3 48 Hardware Architecture protect against failure CSRO is written as follows while IPL 1616 is disabled 1 Write CSRO 2 Read CSRO 3 Compare value read to value written If values mismatch repeat step 2 4 Read CSR5 and examine CSR5 lt 04 gt for pending parity interrupt Should an interrupt be pending write CSR5 to dear it Figure 3 18 shows the format of CSRO Table 3 18 describes its bit structure Figure 3 18 CSRO Format 3130292827262524232221201918171615 02 0100 gt MLO 004416 Table 3 18 CSRO Bits Bit Name Access Description 15 00 IV R W Interrupt Vector During an interrupt acknowledge cyde for an Ethernet coprocessor interrupt the Ethernet
390. shorter than 64 bytes the Ethernet coprocessor adds the padding field and the CRC regardless of the lt AC gt flag Data Type Indicates the type of data that the buffer contains according to the following table Value Meaning 00 Normal transmit frame data 10 Setup frame Refer to Section 3 6 2 3 11 Diagnostic frame Refer to Section 3 6 5 Virtual Addressing When set TDES3 is interpreted as a virtual address The type of virtual address translation is determined by the TDES1 lt 23 gt bit The Ethernet coprocessor uses TDES3 and TDES2 lt 08 00 gt to perform a VAX virtual address translation process to obtain the physical address of the buffer When clear TDES3 is interpreted as the actual physical address of the buffer VA VT Addressing Mode x Physical 1 0 Virtual SVAPTE 1 1 Virtual PAPTE continued on next page Table 3 36 Cont TDES1 Fields Bit Name Descriptor 31 CA Chain Address When set TDES3 is interpreted as another descriptor s VAX physical address This allows the Ethernet coprocessor to process multiple noncontiguous descriptor lists and explicitly chain the lists Note that contiguous descriptors are implicitly chained contrast to what is done for a Rx buffer descriptor the Ethernet coprocessor clears neither the ownership bit RDESO lt 31 gt nor any other bit of RDESO of the chain descriptor after processing To protect against infinite loop a chain descr
391. signal will remain valid throughout the entire bus cycle until AS H deasserts The CSDP lt 4 0 gt L bits must be decoded to prevent them from enabling memory when the rtVAX 300 is executing an interrupt acknowledge cycle or an externally implemented internal processor register access cycle Disable memory during these two cycles Table 5 3 lists their bit assertions Table 5 3 rtVAX 300 CSDP lt 4 0 gt IPR and IACK Codes CSDP lt 4 gt CSDP lt 2 gt CSDP lt 1 gt CSDP lt 0 gt Bus Cycle Type H L H L External IPR read or write H L H H External interrupt acknowledge L X X X rtVAX 300 internal cycle Memory System Interface 5 11 5 9 2 Address Latches The rtVAX 300 uses a time multiplexed data and address DAL bus Address latches such as the 74F 373 must be connected to the DAL lines and the HOLD line of these latches must be connected to the AS line This latched address can then be fed into the address inputs of the memory elements Also the WR L and BM lt 3 0 gt L lines must be latched Figure 5 11 shows the connections of these latches 5 9 3 DRAM Memory Refresh Each bit of data stored in a DRAM memory element is stored as a charge a very small capacitor Through time this charge is bled from these capacitors 50 each bit must constantly be refreshed to retain the stored data Special access 5 are defined for the DRAMs that refresh an entire row of data bits The 1M bit DRAMs used in this example cont
392. sor s Ethernet coprocessor shares lt 1 gt L on the CVAX the coprocessor is serviced before the user interrupt Table 2 6 lists the interrupt priority level IPL assignments as they relate to IRQ 0 and IRQ lt 1 gt L Table 2 6 Interrupt Priority Assignments IRQL 6 Device lt 0 gt 14 User defined shared with external console lt 1 gt 15 User defined shared with the Ethernet coprocessor lt 2 gt 16 User defined shared with the interval timer IRQ3 17 User defined 2 4 7 DMA Control Signals DMA control signals are as follows DMA Request DMR L External logic uses this signal to request control of the DAL bus and its related control signals DMA Grant DMG L O This signal indicates that the rtVAX 300 processor has granted the use of the DAL bus and its related control signals Note Both DMA request and DMA grant signals are daisy chained from the CVAX processor through the Ethernet coprocessor chip inside the rtVAX 300 to the user defined hardware Therefore the Ethernet coprocessor has the first priority for a DMA In addition to prevent Ethernet FIFO overflows a user device cannot remain bus master longer than 6 us Technical Specification 2 19 2 4 8 System Control Signals System control signals are as follows Reset RST 1 This signal initializes the rtVAX 300 processor to a known state This line must be asserted on power up e Halt HL
393. ss space within the bus This method requires contiguous allocation of DMA data buffers and reduces the flexibility of the VAXELN device drivers 8 12 Device Interfacing Refer to the rtVAX 300 5 Guide for information 300 device drivers Digital recommends implementing error registers for bus interfaces These registers log events such as DMA timeout and bus protocol and parity errors Error conditions should interrupt the processor or assert the ERR L line The ERR L line is asserted only if the present processor bus cycle caused the error condition The system software can access these error registers to acknowledge the error condition and take the appropriate action 8 4 1 Q22 bus to Main Memory Address Translation On DMA references to main memory the 22 bit Q22 bus address must be translated into a 29 bit physical memory address This translation process is performed by the Q22 bus interface by using the Q22 bus map This map contains 8192 mapping registers one for each page in the Q22 bus memory space each of which can map a page 512 bytes of the Q22 bus memory address space into any of the 1M pages in main memory Figure 8 5 shows how Q22 bus addresses are translated to main memory addresses At system power up the Q22 bus map registers including the Valid bits are undefined The system software must initialize these registers and enable the S G map 8 4 2 Q22 bus Map Registers The Q22
394. ssing the console the address is placed on the DAL lt 29 02 gt bus 23 ns before the rising edge of Pl ENBCONDATA is asserted on the rising edge of P3 The address information has to propagate through the 74F 373 latches see Figure 6 7 The calculation for the address setup time is as follows 742 244 turn off time 5 ns 50 ns 23 ns Propagation of F373 DUART address setup time In this case the DUART address setup time 5 ns 50 ns 23 ns 7 ns 71 ns The address on A 3 07 of the DUART will be valid during the entire console access cyde so the DUART address hold time is easily satisfied Console and Boot ROM Interface 6 7 Figure 6 4 Sample Design Console Read and Write Cycle Timing mlo 004444 ps turnpage 6 8 Console and Boot ROM Interface 6 1 4 2 Console Data Time The turn off time of any device connected to the rtVAX 300 DAL bus must be less than 35 ns after the rising edge of during the last Since the turn off time of the DUART is 100 ns a transceiver is needed between the DUART data bus and the DAL lt 07 00 gt H bus This 74F 245 transceiver see Figure 6 10 turns off with the deassertion of DS satisfying the required bus turn off time The transceiver also adds delay to the read access time and the write setup time The calculation for the timing analysis for the console turn off time is as follows DS deassertion delay 741 32 propagation delay 7
395. stops output to the console terminal until is pressed Ctri S and are not echoed causes the console to echo U lt CR gt and deletes the entire line Ctr U is pressed on an empty line it is echoed and the console displays gt gt gt to prompt for another command Ctr R causes the console to echo followed by the current command line This function can be used to improve the readability of a command line that has been heavily edited When is pressed as part of a command line the console deletes the line as it does with e Break allows the system to enter console 1 0 mode upon receipt of the BREAK signal you must supply circuitry to assert the EXT HLT lineif the received signal goes into the spacing state for more than 100 ms The SCN 2681 DUART does not support BREAK processing directly Chapter 6 gives a circuit example BREAK is echoed as C 4 10 FIRMWARE 4 3 5 Console Command Syntax The console program prompt is three right angles gt gt gt on a new line 1 The following restrictions apply to console commands They are limited to 80 characters Characters entered after the 80th character replace the last character in the buffer Though characters so lost may be displayed on the Console display they will not be induded in the actual command line The comm
396. store data for processor reading while the next longword is accessed in the DRAMs This overlapping improves the performance of the memory system for multiple longword transfer cycles When the data for the first longword is valid the memory controller asserts DRAMREADY This sets the ready hold latch see Figure 5 12 and asserts the RDY L line of the rtVAX 300 This latch is cleared when the rtVAX 300 deasserts the data strobe DS line When the RDY L line is asserted the data that was present at the DRAM outputs is latched and driven onto the DAL bus Once the data has been latched the CAS hold latch can deassert the CAS 3 0 lines of the DRAMs and the memory controller can assert the INVADDR2 line to generate the next longword address The memory controller reasserts the ENBCAS line asserting the CAS 3 0 lines and driving the next longword data into the inputs of the RAM data latches When the processor finishes transferring the first longword the second longword is latched into the data latches Caution The RDY L ERR L and CCTL L lines tri stateable lines These lines are pulled up by resistors in the rtVAX 300 and must be driven by a tri stateable driver such as the 74F 125 If these lines are driven by a standard TTL totem pole output the rtVAX 300 will not function These latches can be eliminated however the memory controller state machine must be redesigned and quadword read cycles take one more
397. str ctlon Set cs A REEL Reese TREE 3 2 Microcode Assisted Emulated Instructions 3 3 Processor State rios dua cer ean RR re Rae 3 5 General Purpose 5 5 3 5 Processor Status Longword 3 6 Internal Processor Registers 3 7 Interval Timer 3 10 ROM Address 3 11 Resident Firmware Operation 3 11 31141 31142 31 143 3 2 1 3 2 2 3 3 3 3 1 3 3 2 3 3 2 1 3 3 2 2 3 3 2 3 3 3 2 4 3 3 2 5 3 3 2 6 3 3 2 7 3 4 3 4 1 3 4 2 3 4 3 3 5 3 5 1 3 5 2 3 5 3 3 5 4 3 6 Memory Management Translation Buffer Memory Management Control Registers Exceptions and Interrupts Interrupt Control Internal Hardware Interrupts Dispatching Interrupts 5 Interrupt Actlon ib EX ative dan ERE ES Halting the 550 Exceptions Information Saved on a Machine Check Exception System Control Hardware Detected 5 Hardware Halt Procedure System Identification CPU References Instruction Stream
398. t 33 itt crc i 1 Compute the address CRC by running the CRC 48 steps for 150 1 lt 6 itt for k 0 k 8 k mean crc 32 addrti gt gt k amp 1 for m 32 m gt 2 m crc m crc m 1 crc 27 27 mean crc 24 crc 24 mean crc 23 crc 23 mean crc 17 crc 17 mean crc 13 crc 13 mean crc 12 12 mean crc 11 crc 11 mean crc 09 crc 09 mean crc 08 crc 08 mean crc 06 crc 06 mean crc 05 crc 05 mean crc 03 crc 03 mean crc 02 crc 02 mean crc 01 mean Extract the hash index from the CRC residue warning the bits are mirrored into the CRC the bit of CRC residue is the lsb bit of the hash index for k 24 k lt 33 k hash hash 1 crc k return hash amp 1 E 4 Sample C Program to Build Setup Frame Buffer Foldouts This appendix contains a list of illustrations that will appear as foldout pages or turn pages in the final printed copy of the book Table F 1 lists each illustration its number title and format Table F 1 Turnpage and Foldout Illustrations Number Title MLO Number Format 2 11 Octaword Transfer Read Cyde ML O 004398 Turnpage Timing 2 13 Octaword Transfer Write MLO 004400 Turnpage Timing 5 2 Sample Design Memory ML O 006386 Turnpage Subsystem Functional Diagram 5 3
399. t Address Register CSR14 This register contains the breakpoint address that causes the internal microprocessor to jump to patch address This register in conjunction with the diagnostic descriptors allows software patches Figure 3 26 shows the format of CSR14 Table 3 28 describes its bit structure 3 64 Hardware Architecture 3 6 1 11 Figure 3 26 CSR14 Format 3130 1615 00 Code Restart Address CRA Breakpoint Address BPA CSR14 MLO 004424 Table 3 28 CSR14 Bits Bit Name Access Description 15 00 R W Breakpoint Address The internal processor address at which the program will halt and jump to the RAM loaded code 30 16 CRA RW Code Restart Address The first address in the internal ROM to which the internal processor jumps after a breakpoint occurs 31 BE R W When set breakpoint is enabled Monitor Command Register CSR15 This register is a physical CSR It contains the bits that select the internal test block operation mode Figure 3 27 shows the format of CSR15 Table 3 29 describes its bit structure Figure 3 27 CSR15 Format 161514131211 10090807060504 03 02 0100 cenis MLO 004425 Hardware Architecture 3 65 Table 3 29 CSR15 Bits Bit Name Access Description 12 BS 14 13 QAD 15 ST 31 16 ADDR DATA RAV Bus Select When set the monitoring is applied on the internal Address bus Meaningful only in test mode TS
400. t PAL programmable devices do not offer enough input pins and you can cascade two PAL devices to decode the memory address as shown in Figure 8 2 The first PAL decodes the upper address bits DAL 29 13 and the outputs of this PAL are all latched by the device select latch ROM and RAM selected by the first PAL Two other outputs of this PAL are latched and fed into a second PAL with the low order latched address bits LADDR lt 12 02 gt The output of this PAL asserts the CONE console register select SELBADDR base address register and SELCSR I O CSR register The data strobe DS line enables these three select signals Device Interfacing Figure 8 2 Device Interfacing Address Decoding Block Diagram Device First Select Decoder Latch SELRAM SELROM SELDSPRAM DAL lt 29 13 gt 17 LSELCONIO Address LSELREGIO Latches SELBADDR SELCSR LADDR lt 12 2 gt DAL lt 12 2 gt Second Decoder MLO 004465 8 1 3 Access Cache Control Data Parity and I O Cycle Types The rtVAX 300 does not cache any data read from the 1 0 space Thus the CCTL L line of the rtVAX 300 must be driven low when 1 0 read access is performed The rtVAX 300 performs only longword transfer cycles to the 1 0 space This allows for a simple design of I O peripherals because they need not respond to quadword or octaword access cycles O devices can be constructed to generate and
401. t interface Section 7 2 e Thickwire network interconnect Section 7 3 e ThinWire support Section 7 4 e Ethernet coprocessor registers Section 7 5 e Hardware implementation example Section 7 6 71 DECnet Communications The rtVAX 300 allows the transfer of information and programs among Digital s systems and among Digital s and other manufacturer s systems Network communications between Digital s systems is facilitated by DECnet hardware and software VAXELN programs developed on a host VAX processor can be loaded into the target rtVAX 300 based application through the network The rtVAX 300 communicates with other VAX processors through the Ethernet local area network Systems and devices can easily be connected to the network network expansion is possible without interrupting network operations Programs and data can be transferred between realtime applications and VAX processors in the network Network Interconnect Interface 7 1 Ethernet provides the following features Simplified network design allows installation of new devices without interrupting communication Cable segments can be added to expand networks Remote locations have fast access to data High speed communication can take place between nodes 7 2 Ethernet Interface The Ethernet coprocessor and serial interface adapter SIA built into the rtVAX 300 provide the basis of an interface to an Ethernet network The coprocessor has these features It
402. t is asserted and LADDR 30 is deasserted a quadword read cycle is taking place This signal asserts during power up and system reset t causes the state machine to run refresh cycles continually to warm up the DRAM upon power up This signal is asserted to start a system reset its assertion forces the IDLE state and deasserts all outputs This signal is asserted by an external refresh request counter every 3 28 ms This request is reset when this state machine asserts the EN BREFRESH signal continued on next page Memory System Interface 5 43 Table 5 11 Cont Memory Subsystem Sequencer State Machine PAL Pins Setting Comment Output 12 13 15 16 17 18 IRAS IENBCAS IREFCYC INVADDR3 INVADDR2 IDRAMREADY The assertion of this signal strobes the row address into the selected DRAMs for refresh or memory access The assertion of this signal strobes the column address into the selected 5 writes data into them during a write cyde and turns on the output drivers during a read cyde to drive output data The assertion of this signal turns on the refresh address counter output drivers driving the next refresh address onto the address lines of the DRAMs This line dears the refresh request latch and its deassertion increments the refresh address counter The assertion of this signal inverts the LADDR 3 bit of the column address which is then driven onto the addr
403. t mode either the current process or the operating system should be terminated The information pushed onto the stack by this type of machine check is from the instruction that caused the machine check Error Description 80 An error occurred while reading an operand a process page table entry during address translation or on any read generated as part of an interlocked instruction 81 An error occurred while reading a system page table entry during address translation a process control block entry during a context switch or a system control block entry while processing an interrupt Write errors indicate that an error was detected when the CVAX processor tried to write to either the internal cache the main memory or an external device The most likely cause of this type of machine check must be determined from the state of the MSER Machine checks due to write 3 22 Hardware Architecture errors are nonrecoverable because the processor can perform many read operations out of the internal cache before a write operation completes For this reason the information that is pushed onto the stack by this type of machine check cannot be guaranteed to be from the instruction that caused the machine check Error Description 82 An error occurred while writing an operand or a process page table entry to change the PTE M bit before writing a previously unmodified page 83 An error occurred whi
404. t process is 2 0 255 c0 This illustrates a boot from the Ethernet Other boot devices would be displayed depending on the seeting of the user boot register 4 5 3 Halt Action The operator may inspect and possibly modify the console fields used during processor restarts by using the console SET SHOW HALT command for example Example 4 3 Sample Halt Action Display gt gt gt SET HALT 2 gt gt gt 3 gt gt gt See Section 4 2 1 for more information 4 5 4 Boot Device The operator may inspect the console field used for the default boot device and modify it by using the console SET SHOW BOOT command for example gt gt gt SET BOOT EZA0 2 gt gt gt gt gt gt See Section 4 2 2 more information This field is initialized from the boot register upon reset or power up When there is no default for the boot device it is displayed as four periods To clear the field enter a period at the prompt 4 5 5 Boot Flags The operator may inspect and possibly modify the console field used as default boot flags for system image boot by using the console SET SHOW BFLG command for example gt gt gt SET BFLG 00000000 2 gt gt gt 10 gt gt gt See Section 4 3 6 1 for information Boot command This field is zeroed upon power up or reset 4 28 FIRMWARE 4 6 Hardware CSRs Referenced by the Firmware The following sections illustrate and discuss the hardware CSRs referenced by the
405. t written to by the DSP When the DSP writes to 1 space the DSPIS signal is also asserted The DSR BADDR PAL then asserts the LATCHDSPCSR line when DSPSTRB asserts When LATCHDSPCSR deasserts the data on the DSP data bus is latched into the DSP mirror register The data on DSP data bit 08 is used to set the VAX interrupt request flop as shown in Figure 8 27 When this bit is set an interrupt at IPL 1616 is posted by asserting the IRQ lt 2 gt L line of the rtVAX 300 When the rtVAX 300 reads this mirror register it reads the most recent value written to it by the DSP When the rtVAX 300 writes to this register the DSP reads that value the next time it reads from that register Device Interfacing 8 19 8 20 Figure 8 8 Device Interfacing DMA State Machine Sequence REQDALBUSL DRIVEADDRLJ MDRIVEADDR Device Interfacing ASSERTAS AS MDRIVEADDR DMACYC1 DS FINISHUP1 DSPREADY FINISHUP2 DSPREADY MLO 004471 Device Interfacing 8 21 Figure 8 9 I O Device Interfacing DMA Write Cycle Timing mlo 004472 ps foldout 8 22 Device Interfacing Device Interfacing 8 23 8 5 5 2 Interrupt Reset and Hold Bits When the system is first reset the CSR register clears all of its bits except the HOLD DSP and RESET DSP bits Once the rtVAX 300 boots it writes the DSP program into a reserved block of rtVAX 300 system memory and sets the DM
406. terrupting device Each interrupting device must generate a unique vector so that a different ISR is invoked for each device Table 3 4 lists the relationship between interrupts and the SCB 8 3 General Bus Interfacing Techniques In some applications the rtVAX 300 interfaces with a general purpose 1 0 bus such as the VME bus the PC AT bus 1 The design of this interface can vary The rtVAX 300 application module can function either as a bus master or a slave processor Communication between the rtVAX 300 application module and other modules on the bus is carried out through either shared memory or dual ported data registers 1 IBM PC AT is a registered trademark of the International Business Machines Corporation 8 6 Device Interfacing 8 3 1 Bus Errors When a bus error occurs external logic notifies the CPU by asserting ERR L during a bus The CPU responds as shown in Table 8 1 External logic can assert both ERR L and RDY L to request a retry of bus cycles CAUTION The RDY L ERR L and CCTL L lines tristateable bidirectional lines These lines are also internally pulled up by a resistor and they must be driven by tristateable drivers If these lines are driven by a standard TTL totem pole output the rtVAX 300 does not function Table 8 1 Response to Bus Errors and DAL Parity Errors Cycle Type Prefetch _ Cache Error Status Machine Flows Demand D stream Entry L
407. tes stopped running or suspended State transitions take place as a result of port driver commands or the occurrence of selected external events A simple programming sequence of the chip can be summarized as follows 1 2 After power up or reset verify that self test completed successfully Load CSRs with major parameters such as the system base register interrupt vector address filtering mode Create transmit and receive lists and load CSRs to identify them to the Ethernet coprocessor Place a setup frame in the transmit list to load the internal reception address filtering table Start receive and transmit processes by placing them in the Running state Wait for Ethernet coprocessor interrupts Issue a Polling Demand command if either the receive or transmit process enters the suspended state This is done after correcting the cause of the process suspension The following sections describe Ethernet coprocessor operation Hardware and software reset Section 3 6 3 1 Interrupts Section 3 6 3 2 3 86 Hardware Architecture 3 6 3 4 Hardware and Software Reset The Ethernet coprocessor responds to two types of reset commands a hardware reset through the RESET L pin and a software reset command triggered by setting CSR6 lt 31 gt In both cases the Ethernet coprocessor aborts all ongoing processing and starts the reset sequence The Ethernet coprocessor restarts and reinitializes all internal states and registers
408. tes to the CADR cause the internal cache to be flushed all valid bits set to the invalid state and the internal cache is configured for write through operation Note The internal cache can be disabled either by disabling both set 1 and set 2 clearing CADR lt 07 06 gt or by not storing either stream or D stream references clearing CADR lt 05 04 gt For maximum performance the cache should be configured to store both and D stream references stream only mode suffers from a degradation in performance from what would normally be expected relative to and D stream mode and D stream only mode because invalidation of cache entries due to writes to memory by a DMA device are handled less efficiently In I stream only mode the entire internal cache is flushed whenever REI instruction is executed The VAX Architecture Reference Manual states that an REI instruction must be executed before executing instructions out of a page of memory that has been updated whereas in the other two modes of operation cache entries are invalidated on an individual basis only if a DMA write operation results in a cache hit CVAX processor write references with a longword destination for example MOVL write the data into main memory if it exists as well as invalidate the corresponding cache entry irrespective of whether or not a cache hit occurred CVAX processor write references with a quadword destination for example
409. that is privately coupled to the DSP A DMA engine that allows the DSP to write to and read from rtVAX 300 system memory An interprocessor communication CSR Figure 8 7 shows the rtVAX 300 and DSP processor interface Device Interfacing 8 15 Figure 8 7 Device Interfacing DSP and 300 Processor Interface Block Diagram ML O 006394 ps turnpage 8 16 Device Interfacing 8 5 1 DSP Private Memory The DSP executes programs in 4K words of private RAM memory 4 words of ROM for initialization and program loading are privately coupled to the DSP Table 8 3 shows the memory map of the DSP Table 8 3 TMS320C25 Digital Signal Processor Memory Map Program Data Physical Space Space Global Memory Location Device Device Space Device 0000 0FFF ROM RAM None 1000 1FFF ROM RAM None 2000 2FFF ROM RAM None 3000 3FFF ROM RAM None 4000 4FFF RAM RAM None 5000 5FFF RAM RAM None 6000 6FFF RAM RAM None 7000 7FFF RAM RAM None 8000 FFFF None None 300 memory accessed cycles The DSP is a word oriented device expecting to transfer 16 bits of data at a time The rtVAX 300 can transfer either bytes words or longwords during each bus cycle When the DSP is reset it begins to execute code from program space location 0000 The loader ROM is at that location The code in that ROM first initializes some registers and vectors of the DSP then the code causes the DSP to load a program from t
410. that the console is to take when the next processor halt occurs except for externally generated halts such as BREAK and assertion of the HLT signal The action taken is as described for HLT SWX above This field is copied from the HLT SWX field at power on upon execution of the SET SHOW HALT console commands and at entry to the console Figure 4 8 DUART and Display Status 07 4 38 FIRMWARE 06 05 04 03 02 01 00 Reserved to Console Code DISP MLO 004504 Table 4 8 DUART and Display Status Register Fields Field Description DISP DUART A 1 bit field used by the console code to determine if the hexadecimal display at address 201FFFFE is present If the bit is set that address responded and the display is assumed to exist If the bit is dear there was no hardware response to that address User supplied tests and booted images may test this bit to determine if the display register exists This field is initialized at every entry to the console program A 1 bit field used by the console code to determine if the SCN 2681 console DUART and secondary DUART at address 20100000 are present If the bit is set the address responded and preliminary tests determined that the console DUART was usable If the bit is clear either there was no hardware response to that address or the DUART tests determined that there was not a usable DUART present User supplied tests and booted images may test this bit to determin
411. the data latches shown in Figure 5 15 and the ENBCAS line is deasserted The INVADDR2 line is now asserted driving the next longword address onto the DRAM address bus Now the ENBCAS line of the DRAM is reasserted and the next longword appears at the data latches DRAMREADY is reasserted the second longword is transferred and the access cycle is complete Memory System Interface 5 15 If page mode access is not supported by the DRAMs the row address would have to be restrobed into the DRAMs for the second longword and the memory performance would suffer 5 9 6 DRAM Terminating Resistors The very fast rise and fall times of the DRAM s address RAS CAS and WE lines have some very high frequency components associated with them When one of these signals changes state the voltage change has to travel down the PC board trace The trace acts like a transmission line to very high frequencies and the impedance of this line may not be uniform A reflection occurs when a signal encounters a change in impedance These reflections cause signal overshoot and undershoot where the line voltage bounces above 5 0V or below 0 0 Signal reflections deteriorate the signal transition edges in a clock signal this could affect which time data is strobed in the case of data this could affect when the signal can be sampled Most TTL gates can handle a small amount of overshoot and undershoct DRAMs are easily damaged by excessive overshoot and undersh
412. the layout of the console mailbox register and Table 4 7 describes its fields Figure 4 8 shows the layout of the console DUART and display status and Table 4 8 describes its fields Figure 4 9 shows the layout of the default boot device register and Table 4 9 describes its fields Figure 4 7 Console Mailbox Register CPMBX Offset 0046 07 06 05 04 03 02 01 00 TRIG HLT SWX HLT ACT MLO 004503 4 36 FIRMWARE Table 4 7 Console Mailbox Register Fields Field Description TRIG RMT HLT SWX A 1 bit field that indicates that remote triggers are allowed and that the trigger password can be changed If this bit is set remote trigger is allowed and the network trigger password can be set This field is initialized upon power up reset to the value of the MOP bit of the Flags byte after the user s initialization routine if any is called A 1 bit field that enables or disables the action of the MOP remote console If that bit is set to 1 all functions support by the MOP remote console are enabled Refer to Section 4 4 for details of the supported functions This field is initialized upon power up reset to the value of the MOP bit of the Boot Flags byte after the user s initialization routine if any is called A 2 bit halt switch field used to encode permanently the desired console action when a processor halt occurs except externally generated halts brought about by the assertion of the EXT HALT lin
413. thernet coprocessor SGEC chip and can pass data and instructions to and from other stations on a network without processor intervention The Ethernet coprocessor has the following attributes Supports ThinWire and thickwire Ethernet interfaces to the rtVAX 300 processor Contains 16 control and status registers CSRs that control its operation Resets hardware and software and handles interrupts Supports the full IEEE 802 3 frame encapsulation and media access control Supports three levels of testing and diagnostics 1 4 System Support Functions System support functions provided by the rtVAX 300 processor indude Halt boot request arbitration logic Interval timer with 10 ms interrupts Flexible interface to the rtVAX 300 processor 5 DAL bus Ethernet Thickwire connections Control logic to attach a console terminal 1 5 Resident Firmware The resident firmware consists of 256K bytes of ROM The firmware gains control when the processor halts it contains programs that provide the following services Board initialization Power up self testing of the rtVAX 300 processor and its attached memory system Emulation of a subset of the standard console automati c manual bootstrap and a simple command language for examining altering the state of the processor Booting from ROM network or DECnet DDCMP Overview of the rtVAX 300 Processor 1 3 The rtVAX 3005 firmware interface is extensible you can use it to add your own po
414. thernet coprocessor Address filtering table fully set to 0 A reception process started without loading a setup frame rejects all incoming frames except those with a destination physical address 00000016 3 6 2 3 2 Subsequent Setup Frame Subsequent setup frames may be queued to the Ethernet coprocessor regardless of the reception process state The only requirement for the setup frame to be processed is that the transmission process be in the running state The setup frame is processed after all preceding frames have been transmitted and after the current frame reception if any is completed The setup frame does not affect the reception process state but during the setup frame processing the Ethernet coprocessor is disengaged from the Ethernet wire 3 6 2 3 3 Setup Frame Descriptor Setup frame descriptors 4 longword format as shown in Figure 3 30 Table 3 40 describes the SDECx bit structure Hardware Architecture 3 79 Figure 3 30 Setup Frame Descriptor Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 18 12 11 10 09 08 07 06 05 04 03 02 01 00 0 SGEC writes as 0 SDESO only u Ignored by the SGEC on read never written S oo o o fo of of olo lo o o S o o o o o o o SDESO SDES1 SDES2 SDES3 Table 3 40 Setup Frame Descriptor Bits Word Bit Name Description SDESO 13 15 31 SDES1 24 2
415. ting from External ROM Base Address of External ROM Programming the Boot ROMs Boot ROM Interface Design Boot ROM Address ROM Address ROM Read Timing ROM Turn Off ROM Speed vs rtVAX 300 Performance rtVAX 300 Processor Status LED Register Console Interface and Boot ROM Illustrations and Programmable Array LOgiC 5 23 5 26 5 27 5 27 5 27 5 28 5 28 5 28 5 30 5 30 5 31 5 32 5 32 5 42 P LLLLLLLLLLLLLL HH HO IL 7 d od MD 6 4 1 Application Module Address Decoder PAL 6 19 6 4 2 Console Sequencer State Machine PAL 6 29 6 4 3 Interrupt Decoder 6 34 7 Network Interconnect Interface 7 1 DECnet 5 7 1 72 Ethernet Interface 7 2 7 3 Thickwire Network Interconnect 7 3 7 4 ThinWireSupport 7 8 7 5 Ethernet Coprocessor Registers
416. tional data and generates a machine check if the cycle was a demand read Only the first transfer can be a demand cycle An error is recognized only if RDY L is deasserted for two consecutive P1 sample points c External logic can request a retry of the by asserting RDY L and ERR L If the retry occurs during the second longword transfer the read cyde is not reissued 6 The CVAX completes the cycle by deasserting DS L and AS L Figure 2 10 illustrates quadword transfer read cyde timing and Table 2 7 shows responses to this 2 28 Technical Specification Figure 2 10 Quadword Transfer Read Cycle Timing CLKA P1 P3 P1 P3 P1 P3 P1 P3 CLKB P2 P4 P2 P4 P2 P4 P2 3 o 014490 9 49 10 Du lt CCTL UE lt Parity gt 1 AS CSDP 6 43 i 6 49 8 i 678 RDY ERR MLO 004397 Technical Specification 2 29 Table 2 7 rtVAX 300 Responses to a Quadword Transfer Read Cycle Parity Action for Second CCTLL RDYL ERRL Error Action for First Reference Reference X H H X Wait for data Wait for data X H L X Machine check if demand No machine check read Invalidate cache Invalidate cache entry entry No second reference H L H H No machine check Update machine check Update cache Proceed to second cache reference L L H H No machine check No machine check Update Invalid
417. transmission process is placed in the stopped state after completing transmission of the current frame The next descriptor position in the transmit list is saved and becomes the current position after transmission is restarted The Stop Transmission command is honored only when the transmission process is in the running or suspended states continued on next page Table 3 23 CSR6 Bits Bit Name Access Description 19 20 28 25 30 31 SE BE BL RE R W R W R W R W R W Single_Cycle Enable mode When set the Ethernet coprocessor transfers only a single longword or an octaword in a single DMA burst on the rtVAX 300 bus Boot Message Enable mode When set enables the boot message recognition When the Ethernet coprocessor recognizes an incoming boot message on the serial line CSR5 lt 07 gt is set and the external pin BOOT L is asserted for a duration of 6 T cycles of the rtVAX 300 clock Burst Limit mode Specifies the maximum number of longwords to be transferred in a single DMA burst on the rtVAX 300 bus When CSR6 lt 19 gt is cleared permissible values are 1 2 4 and 8 when set the only permissible values are 1 and 4 and a value of 2 or 8 is respectively forced to 1 or 4 After initialization the burst limit is set to 1 Interrupt Enable mode When set setting of CSR5 lt 06 01 gt generates an interrupt Reset command When set the Ethernet coprocess
418. ts 18 DAL11 DAL line 11 is used as one of the console address decoder inputs 19 DAL 12 DAL line 12 is used as one of the console address decoder inputs Output Signals 23 ILOWCONE This signal and the UPCONE of the address decoder select the console 22 ILOWCPUST This signal selects the processor status LED register and the UPCPUST of the address decoder 21 ICONIACK This signal is asserted when the rtVAX 300 is running an interrupt for the console 20 ICYCRES This signal resets all the select outputs asynchronously once AS deasserts Console and Boot ROM Interface 6 35 Table 6 7 Interrupt Decoder PAL Equations Line Equals CONIACK D IWR amp CSDP4 amp ICSDP2 amp CSDP1 amp CSDPO amp DAL6 amp IDAL5 amp DAL4 amp DAL3 amp DAL2 CONIACK AR CYCRES LOWCONE D IDAL12 amp DAL11 amp DAL10 amp IDAL9 amp IDAL8 amp IDAL7 amp 6 LOWCONE AR CYCRES LOWCPUST D DAL12 amp DAL11 amp DAL10 amp DAL9 amp DAL8 amp DAL7 amp DAL6 amp DAL5 amp DAL4 amp DAL3 amp DAL2 LOWCPUST AR CYCRES CYCRES IAS amp CONIACK LOWCONE LOWCPUST 6 36 Console and Boot ROM Interface 7 Network Interconnect Interface The rtVAX 300 processor connects easily to Digital s Ethernet network The VAXELN kernel can include DECnet communication through the built in Ethernet interface This chapter discusses the following topics e DECnet communications Section 7 1 e Etherne
419. ts of the 28 tag registers are compared with the virtual page number field bits lt 31 9 gt of the virtual address of the reference If there is a match with one of the tag registers a translation buffer hit has occurred and the contents of the corresponding PTE register are used for the translation If there is no match the translation buffer does not contain the necessary VAX PTE information to translate the address of the reference and the PTE must be fetched from memory Upon fetching the PTE the translation buffer is updated by replacing the entry that is selected by the replacement pointer Since this pointer is moved to the next sequential translation buffer entry whenever it is pointing to an entry that is accessed the replacement algorithm is not last used NLU 3 1 8 2 Memory Management Control Registers Four IPRs control the memory management unit MMU IPR 56 MAPEN IPR 57 TBIA IPR 58 TBIS and IPR 63 TBCHK M emory management can be enabled disabled through IPR 56 MAPEN Writing O to this register with an MTPR instruction disables memory management writing a 1 enables memory management Writes to this register flush the translation buffer To determine whether or not memory management is enabled 56 is read by the instruction Translation buffer entries that map a particular virtual address can be invalidated by using the MTPR instruction to write the virtual address to IPR 58 TBIS Note Wh
420. tus M SCR register located at physical address 20110000 can optionally be implemented to disable memory tests The optional memory system control status register MSCR is mapped to location 20110000 it contains 1 bit If this register is not implemented the rtVAX 300 uses the default bit value of 1 enabling memory tests and disabling processor restart Figure 3 15 shows the layout of this register Table 3 14 describes its bit structure Figure 3 15 Memory System Control Status Register 31 02 0100 20110000 Undefined and Not Used Enable Memory Tests MLO 006348 Table 3 14 Memory System Control Status Register Fields Bit Description 31 02 Not used lt 01 gt Set if memory test is to be performed power up cleared when test is not to be performed If the register is not implemented the default is 1 lt 00 gt Not used Note Digital does not recommend that the memory tests be disabled If they are disabled parity errors can occur when an uninitialized memory location is being read and an untested page frame number bit map will be generated 3 44 Hardware Architecture 3 5 4 Status LED Register The rtVAX 300 allows you to connect a processor status LED display to display the status of self test and diagnostic routines The rtVAX 300 will continue its self test routines if this optional register does not exist The first digit indicates the current state of the system the second
421. uH 1 DP8392 COAXXCVR 1 BIZENER 400V 1 FUSE 2A 1 CONN 15 15 P D SUB 1 JUMPER 1 continued on next page Network Interconnect Interface 7 11 Table 7 2 Cont Ethernet Board Parts List Generic Name Discrete Value Total in Design CAP 4700 pF 1 RES 1K 196 1 RES 1M 1 RES 499 4 DIODE D664 2 CAP 01 pF 1 CAP 820 pF 1 CAP 47 pF 1 CAP 150 pF 1 CAP 68 uF 1 ZENER 8 2V 196 1 TRANSISTOR NPN SWITCHING 1 DIODE UES1302 1 DIODE 1N 4004 1 TRANS POWER XFORM 1 INDUCTOR 2 2 uH 1 4N 38 OPTO ISOLATOR 1 555 TIMER 1 NMOS NMOS POWER FET 1 RES 1K 1 RES 75 1 RES 39 2 2 RES 14 7K 196 1 RES 16 5K 196 1 7 6 2 4 DC DC Converter Figure 7 6 shows a discrete DC DC converter that produces the voltage required by the DP8392 chip while maintaining the isolation requirements of Ethernet Note that some modular DC DC converters perform the same functions as the discrete converter 7 12 Network Interconnect Interface Figure 7 6 Network Interconnect DC DC Converter MLO 004459 ps Network Interconnect Interface 7 13 7 6 3 Ethernet Interface Detailed Design Considerations This section presents detailed information regarding use of the standard Ethernet devices The data presented here are more detailed than those found in the device specifications and form the basis for the layout requirements presented in Section 7 6 7 6 3 1 Differential Signals The transmit XMIT E receive RX and collision COL signals are differential pai
422. um Interface Pulldown Resistors ThinWire Grounding 1 E D d ThinWire Connector 0 Precision Q Q Q Q Resistor E apac tor ee ee ed Transformer DP8392 Heartbeat Enable Switch MLO 004462 7 6 3 2 3 Additional ThinWire Application Hints You may find the following application hints useful PCB layout considerations Figure 7 8 shows a heat spreader implemented in Side One Component Side PCB etch connected to pins 4 5 and 13 of the transceiver chip This heat spreader works in conjunction with the special copper leadframe used in the DP8392 chip to conduct heat out of the VEE pins Since this large area of Side One etch is under the chip it does not require extra PCB space to implement You need not route signals under the chip on side one if the layout is done as indicated above EMC compliance ThinWire Ethernet interfaces can be difficult to certify for FCC Class B Class A requirements are less difficult The best approach is to use very low ESR capacitors between the isolated ThinWire cable shield and the system chassis earth ground The best type of device is a multilayered ceramic surface mount capacitor These devices have very low ESR insignificant lead length and are available in a 1000 VDC rating that Network Interconnect Interface 7 17 Figure 7 8 Network Interconnect Heat Spreader O G
423. usrom vec address 300 usrom test 14 long 0 reserved mbz assume 300 al usrom vec rom test 11 l usrom vec rom test 12 l usrom vec i EXTERNAL REFERENCES rom test 8 address rom test 9 address of no external data routines directly referenced in this Sbttl rtVAX 300 Board level Initialization D 4 User Boot Diagnostic ROM Sample rom board init address of board level initialization 8 9 t 10 E 2 13 t 14 tor eq 30051 usrom board init tor eq 30051 usrom test 8 f board level test tor eq 30051 usrom test 9 f board level test tor eq 300 1 usrom test 10 address of board level tes tor eq 30051 usrom test 11 address of board level tes tor eq 30051 usrom test 12 address of board level tes tor eq 30051 usrom test 13 address of board level tes tor eq 30051 usrom test 14 address of board level tes tor eq 30051 usrom shared module Ne Se Ne Se Ne Se Se Ne Ne Ne Ne Ne Ne Ne Se Se Ne Ne Ne Se Se Se Se Se Se e e FUNCTIONAL DESCRIPTION This routine user supplied is called by the rtVAX 300 s resident firmware at system power on to do any board level initialization It is called at IPL 31 in kernel mode with memory management disabled CALLING SEQUENCE calls 3 300 usrom board init
424. vice driver supports both channels The console IPL 1416 is associated with interrupt request line lt 0 gt and the vector 02 016 The control logic has assigned locations for the registers that the SCN 2681 DUART uses These registers are decoded assigned addresses in the reserved portion of I O space Table 3 13 lists the physical address of each register Chapter 6 contains details on how to connect the SCN 2681 DUART tothe rtVAX 300 Technical Specification 2 5 2 3 Bus Connections Figure 2 2 shows a typical interface configuration of the rtVAX 300 processor and includes control signals and bus connections All signals are TTL levels except for the Ethernet differential pairs Figure 2 2 Typical rtVAX 300 Environment rtVAX 300 Thickwire Network Backbone DAL lt 31 00 gt M User Isolation 4 Transformer Defined Console Hardware MLO 006368 2 3 1 Power Connections The rtVAX 300 processor requires a 2 DC power supply Seven pins provided to connect to 45V and seven pins for 5V return The four mounting holes can also serve as a ground connection The power decoupling and proper ground connections are very important Refer to Section A 2 for detailed information 2 3 2 Reset and Power Up Requirements Asserting the RST L signal for a minimum of 30 clock periods resets the rtVAX 300 processor This line must be deasserted within the specified time before the rising
425. ways By selecting a boot action in the BOOT register at power on Byusing the BOOT command and explicitly specifying any of the ROM boot devices 4 48 FIRMWARE overriding the default boot action in the register through software The ROM bootstrap uses a boot block mechanism that allows flexible placement of the ROM in either of the two ROM address spaces To locate a ROM bootstrap the rtVAX 3005 resident firmware searches a ROM address space looking for a valid page aligned ROM boot block When the first six longwords of any such page contain a valid ROM boot block the rtVAX 3005 firmware copies the ROM contents if selected and starts execution Otherwise the search continues until the resident firmware has either searched all of the ROM address space or has found a ROM boot block Figure 4 11 shows the format of the ROM boot block Figure 4 11 ROM Boot Block 31 23 23 16 15 0 Check Value 0018 16 Must Be Zero Size of ROM in Pages Must Be Zero Offset into ROM to Start Execution Sum of Previous Three Longwords where This word must 001816 BB 2 This byte may be any value BB 3 This byte must be the one s complement of the sum of the previous three bytes BBM This longword must be 0 FIRMWARE 4 49 4 11 1 4 11 2 BB 8 This longword contains the size in pages of the ROM BB 12 This longword must be 0 BB 16 This longword contains the byte
426. wer up initialization and self test diagnostics 1 4 Overview of the rtVAX 300 Processor 2 Technical Specification This chapter discusses the technical specifications of the rtVAX 300 processor covering the following subjects Functional description Section 2 1 Minimum hardware configuration Section 2 2 Bus connections Section 2 3 Pin and signal description Section 2 4 Memory and 1 0 space Section 2 5 Bus cycles and protocols Section 2 6 2 1 Functional Description The functional description of the 300 processor consists of the following Architecture summary Section 2 1 1 Processor and floating point accelerator Section 2 1 2 ROM and reserved memory locations Section 2 1 3 Network Interface Section 2 1 4 Decode and control logic Section 2 1 5 Interrupt structure Section 2 1 6 DMA structure Section 2 1 7 Interval timer Section 2 1 8 Internal cache Section 2 1 9 Technical Specification 2 1 2 1 1 Architecture Summary Based on Digital s CVAX microprocessor chip the rtVAX 300 processor contains an Ethernet coprocessor a floating point accelerator an interval timer control logic and a diagnostic and boot ROM Figure 2 1 shows a block diagram of the rtVAX 300 processor The rtVAX 300 processor provides a common interface to the user logic as dose to the CVAX microprocessor bus interface as possible The rtVAX 300 processor can access up to 510M bytes of physical memory 256M b
427. y development and manufacture of ROM parts The first two bytes 00 and 01 of each chip are reserved for data used within the context of the full set of chips The ROM set data start on a longword boundary Byte addressing is the address within the isolated chip not the address in the system firmware ROM address space nor the address within the ROM set The information presented in Figure 4 2 represents the data within each byte of the system ROM space The data are replicated for each byte of the devices associated with the system ROM 4 2 FIRMWARE Figure 4 2 System ROM Reserved for ROM Set Data Manufacturing Check Data 3315 07 00 Byte 0 Byte 1 Byte 2 Byte 3 Byte4 Byte 5 Byte 6 Manufacturing Check Data 0016 Byte 7 Reserved for ROM Set Data Byte 8 Last MLO 004500 Contents are as follows e Version byte 02 Contains the version number of the console code for the rtVAX 300 system firmware The same value appears in each of the four ROM parts so that a set of chips may be verified to be compatible with a high level of confidence ROM byte number byte 03 Indicates the position of the byte among the set of ROMs used to implement the firmware This is equal to the low two bits of the physical address of the first byte in this ROM part This value ranges from 0 to 3 Manufacturing check data bytes 04 through 07 M ay be used for a quick verification of the ROM The data are 5516
428. ytes are read write memory and 254M bytes are read only memory memory 15 directly accessible by its Ethernet coprocessor and is cacheable by the CVAX The rtVAX 300 also provides access to 512M bytes for 1 space and 254M bytes for a boot ROM accesses in I O space not cached 2 1 2 CPU and CFPA The processor on the rtVAX 300 is Digital s CVAX chip with its associated CVAX floating point accelerator CFPA The rtVAX 300 runs VAXELN software based on the VAX instruction set The VMS and ULTRI X operating systems are not supported on the rtVAX 300 2 1 3 ROM and Reserved Memory Locations The upper 2M bytes of memory space are reserved for Digital The lowest 2M bytes of I O space are the rtVAX 300 local register 1 space intended for the user The rtVAX 300 processor stores in 1 space its self diagnostic routines console emulation program other routines that it needs to boot bootstrap supported devices registers and the Network ID ROM The rtVAX 300 tester console serial line unit SLU and board level initialization and diagnostic ROMs can also use a portion of this 1 space 2 1 4 Network Interface The Ethernet controller or Network Interface NI shown in Figure 2 1 connects the rtVAX 300 processor to the Ethernet It consists of the Ethernet coprocessor which interfaces to the CVAX chip data and address line DAL bus and the serial interface adapter SI A to allow users to connect to Ethernet Det

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