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Xilinx UG492 User's Manual

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1. dpo eallx View IP Symbol Sx E logic Ethernet AVB Endpoint T RESET TX CLK PLB Configuration TETE eee Number of PLB Masters b Range 1 16 nee beue PLB Base Address 00000000 Range 00000000 FFFF8000 E PORET AV RX DATA 0 Me ARE AV RX FRAME BAD RX_DATA 0 LEGACY_TX_DATA 0 ACER SS LEGACY TX DATA VALID RX FRAME BAD uj cr d Datasheet lt Back Page 2 of 2 Next gt Cancel Help Figure 4 2 GUI Page 2 Number of PLB Masters The Ethernet AVB Endpoint core is a PLB slave On the connected PLB there may be several PLB Masters Each slave must uniquely acknowledge individual masters using unique PLB signals during transactions For this reason set this integer value to match the number of PLB masters that will be present on the PLB PLB Base Address The Ethernet AVB Endpoint core is a PLB slave The base address of the core must be selected Valid range is 0x00000000 to OxFFFF8000 The least significant 15 bits of the base address must be set to 0 bits 17 to 31 of the PLB Base Address Ethernet AVB Endpoint User Guide www xilinx com 37 UG492 July 23 2010 Chapter 4 Generating the Core XILINX Parameter Values in the XCO File XCO file parameter names and their values are identical to the names and values shown in the GUI Table 4 1 shows the XCO file parameters and values and summarizes the GUI defaults The following is an example of the CSET parameters in an XCO file CSET co
2. ssseeeeseeeeeee ee 145 Table 15 5 Implement Directory 0 e 146 Table 15 6 Results Directory lsssssssessssssee e 147 Table 15 7 Simulation Directory 000 000s 147 Table 15 8 Functional Directory 0 ee 147 Table 15 9 Timing Directory 00 0 e 148 Table 15 10 Driver Data Directory 0 149 Table 15 11 Driver Example Directory 0 cee eee 149 Table 15 12 Driver Source Directory 0 0 eee 150 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 16 Table 16 1 Table 16 2 Table 16 3 Table 16 4 Table 16 5 Table 16 6 Table 16 7 Table 16 8 Table 16 9 Detailed Example Design EDK format Project Directory is iouis age REO eed ot ede EX ERR Pa 160 Component Name Directory 0 eee ees 160 Doc Directoty ocn dodo tear regem Rer heen heat eee e Aene 161 Driver Data Directory 0 0 0 0 6 eee eee 161 Driver Data Directory 0 0 0 0 6 6c teen eee 162 pcore netlist Directory 0 e eee eee ee 162 Driver Data Directory 0 00 00 roket eien tenes 163 Driver Example Directory 0 0 163 Driver Source Directory 0 0 0 6 eee 164 Appendix A RTC Time Stamp Accuracy Ethernet AVB Endpoint User Guide www xilinx com UG492 July 23 2010 15 16 www xilinx com XILINX Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Pre
3. The demonstration test bench for the example design Instantiates the example design the Device Under Test DUT generates clocks resets and gathers statistics as the simulation is run Back to Top simulation functional The functional directory contains functional simulation scripts provided with the core Table 15 8 Functional Directory Name Description lt project_dir gt lt component_name gt simulation functional simulate_mti do ModelSim macro file that compiles Verilog or VHDL sources and runs the functional simulation to completion wave_mti do ModelSim macro file that opens a wave window and adds signals of interest to it It is called by the simulate_mti do macro file simulate_ncsim sh IES script file that compiles the Verilog or VHDL sources and runs the functional simulation to completion Ethernet AVB Endpoint User Guide UG492 July 23 2010 www xilinx com 147 Chapter 15 Detailed Example Design Standard Format g XILINX Table 15 8 Functional Directory Cont d Name Description wave ncsim sv IES macro file that opens a wave window and adds signals of interest to it It is called by the simulate ncsim sh script file simulate vcs sh VCS script file that compiles the Verilog sources and runs the functional simulation to completion vcs commands key This file is sourced by VCS at the start of simulation it configures th
4. XILINX Chapter 5 Core Architecture As described in Chapter 4 Generating the Core the core can be generated in one of two formats the functionality of which is described in this chapter Standard CORE Generator Format provided for the standard ISE software environment This option will deliver the core in the standard CORE Generator output format as used by many other cores including previous versions of this core and all other Ethernet LogiCORE IP solutions When generated in this format the core is designed to interface to the LogiCORE IP Tri Mode Ethernet MAC or the LogiCORE IP Embedded Tri Mode Ethernet MAC wrappers available in selected Virtex families See Figure 5 1 EDK pcore Format provided for the Embedded Development Kit This option will deliver the core in the standard pcore format suitable for directly importing into the Xilinx Embedded Development Kit EDK environment When generated in this format the core is designed to interface to the XPS LocalLink Tri Mode Ethernet MAC xps ll temac See Figure 5 2 Ethernet AVB Endpoint User Guide www xilinx com 39 UG492 July 23 2010 Chapter 5 Core Architecture g XILINX Standard CORE Generator Format Figure 5 1 illustrates the functional blocks of the Ethernet AVB Endpoint core when it is generated in standard CORE Generator format As illustrated this is intended to be connected to the LogiCORE IP Tri Mode Ethernet M
5. component name implement implement sh LINUX shell script that processes the example design through the Xilinx tool flow See Implementation Scripts page 151 for more information implement bat Windows batch file that processes the example design through the Xilinx tool flow See Implementation Scripts page 151 for more information xst prj XST project file for the example design VHDL only it enumerates all of the VHDL files that need to be synthesized xst scr XST script file for the example design Back to Top 146 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 implement results Directory and File Contents The results directory is created by the implement script after which the implement script results are placed in the results directory Table 15 6 Results Directory Name Description lt project_dir gt lt component_name gt implement results routed v hd Back annotated SimPrim based model used for timing simulation routed sdf Timing information for simulation Back to Top lt component name gt simulation The simulation directory and subdirectories that provide the files necessary to test a Verilog or VHDL implementation of the example design For more information see Example Design page 152 Table 15 7 Simulation Directory Name Description lt project_dir gt lt component_name gt simulation demo_tb v hd
6. Simulation License No action is required to obtain the Simulation Only Evaluation license key it is provided by default with the Xilinx CORE Generator software Full System Hardware Evaluation License To obtain a Full System Hardware Evaluation license do the following 1 Navigate to the product page for this core 2 Click Evaluate 3 Follow the instructions to install the required Xilinx ISE software and IP Service Packs Obtaining a Full License Key To obtain a Full license key please follow these instructions 1 Purchase the license through your local sales office Once the order has been entered an email will be sent to your Account Administrator with instructions on how to access the account 2 Navigate to the product page for this core www xilinx com products ipcenter DO DI EAVB EPT htm Click Order Follow the instructions to generate the required license key on the Xilinx Product Licensing Site www xilinx com getproduct Further details can be found at www xilinx com products ipcenter ipaccess fee htm Installing the License File 28 The Simulation Only Evaluation license key is provided with the ISE software CORE Generator system and does not require installation of an additional license file For the Full System Hardware Evaluation license and the Full license an email will be sent to you containing instructions for installing your license file Additional details about IP license key installa
7. component name simulation Simulation scripts Cj simulation functional Functional simulation files O simulation timing Timing simulation files Ethernet AVB Endpoint User Guide www xilinx com 143 UG492 July 23 2010 Chapter 15 Detailed Example Design Standard Format XILINX lt component_name gt drivers v2_04_a Files for compiling the low level drivers provided with the core Cj drivers avb_v2_04_a data Data files for automatic integration into Xilinx Platform Studio L3 drivers avb v2 04 a examples An application example using the low level driver files Lj drivers avb v2 04 a src Low level driver source C files Directory and File Contents The core directories and their associated files are defined in the following tables project directory The project directory contains all the CORE Generator software project files Table 15 1 Project Directory Name project di r gt Description lt component_name gt gc Top level netlist This is instantiated by the Verilog or VHDL example design component name v hd Verilog or VHDL simulation model UniSim based component name v ho eo Verilog or VHDL instantiation template for the core component name XCO Log file that records the settings used to generate a core An XCO file is generated by the CORE Generator software for each core that it creates in the current project directory An
8. 00 00000008 116 Connection of the PLB to the EDK for LogiCORE IP Ethernet MACs 119 Using the Xilinx XPS LocalLink Tri Mode Ethernet MAC 124 Inttod ctiOn seseris 2 shee a ee dee et eed 124 xps ll temac configuration i e ene nee te eee ee Salen eee 124 System Overview AVB capable xps ll temac 0 60 c eee eee eee 125 Ethernet AVB Endpoint Connections 00 e eee eee ee 126 MES File Syntax beet e ptt e He PH Ee Se EE ee ecdesiae 127 Chapter 13 Software Drivers Clock Mast r eter bee bte te eee e NB d BEE eds 131 Clock Slave oer ites atin bbb d M Aete dines iu e io e cA 132 Software System Integration 0 00 00 132 Driver Instantiation 22 23 bee ioe eek ea ON ee eR 9d pex He PEG Mew ds Beans 132 Interrupt Service Routine Connections 6 ccc eee ees 133 Core ImitialiZatiOn serseri vere DRE ated Neb e bale good 134 Ethernet AVB Endpoint Setup 00 0 0 e 134 Starting and Stopping the AVB Drivers 000 0 e eee eee eee 136 Ethernet AVB Endpoint User Guide www xilinx com UG492 July 23 2010 XILINX Chapter 14 Quick Start Example Design OVervIeW assis Se ee ee ee ee le PME ee eis Was 137 Generating the Cones nooeo dieat ELA HEU ox a E Inr Lua d ierat aa 139 Implementing the Example Design ssssssseseese esee 141 Simulating the Example Design esos ed ehe men nd 141 Setting up for Simulation 6 6 66 ce
9. SI rdwrAddr p SI rdCom PLB rdBurst Single Read Transaction Figure 10 1 Ethernet AVB Endpoint User Guide www xilinx com 88 UG492 July 23 2010 Processor Local Bus Interface XILINX Single Write Transaction Figure 10 2 illustrates a single write data transfer on the PLB Note the following Wait states can be added to the Address cycle by asserting S1 wait and delaying Sl addrAck Wait states can be inserted in the Write sample by delaying the assertion of Sl wrDAck PLB clk PLB RNW 11111111 0 7 PLB BE 0000 0 3 PLB size PLB type 0 2 PLB_abort 0 31 PLB ABus SI addrAck PLB AValid D AO 0 31 PLB wrDBus p SI wrDAck SI wrCom PLB wrBurst 0 31 0000 S rdDBus 0 3 0000 SI rdWrAddr p SI rdDAck SI rdCom PLB rdBurst Figure 10 2 Single Write Transaction 89 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 Chapter 10 Configuration and Status g XILINX PLB Address Map and Register Definitions Figure 10 3 displays an overview of the Address Space occupied by the Ethernet AVB Endpoint core on the PLB Common across all addressable space each unique PLB address value references a single byte of data The variable PLB_base_address shown in Figure 10 3 and in the tables that follow represent the starting base address of the AVB core within the entire PLB address space this is
10. component name example design v hd Top level file that allows the example P P gn P P design to be implemented in a device as a standalone design tx frame stimulus v hd An HDL file which is capable of producing Ethernet frames at maximum line rate and containing a predictable pattern in the data field temac loopback shim v hd An HDL file which sits in the place of an Ethernet MAC an Ethernet MAC is required in a real system This file loops back the data from the transmitter client to the receiver client Ethernet AVB Endpoint User Guide www xilinx com 145 UG492 July 23 2010 Chapter 15 Detailed Example Design Standard Format g XILINX Table 15 4 Example Design Directory Cont d Name Description rx_frame_checker v hd An HDL file which is capable of receiving Ethernet frames at maximum line rate This will check the data contained in each Ethernet frame received against a predictable pattern This file partners the tx_frame_stimulus file plb_client_logic v hd An HDL file that sits in the place of an embedded microprocessor an embedded microprocessor is required in a real system which provides stimulus to the PLB performing write and reads that initiate PTP frame transmission Back to Top lt component name gt implement The implement directory contains the core implementation script files Table 15 5 Implement Directory Name Description project dir
11. rtc_sec_field 47 0 Output This is the synchronized seconds field from the RTC clk8k Output This is an 8KHz clock which is derived from and synchronized in frequency to the RTC rtc_nanosec_field_1722 31 0 Output The IEEE1722 specification contains a different format for the RTC provided here as an extra port This is derived and is in sync with the IEEE802 1 AS RTC If desired this port can be used as the RTC reference for 1722 Packet Manager blocks as illustrated in Figure 3 2 See also TEEE1722 Real Time Clock Format page 81 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 6 Ethernet AVB Endpoint Transmission As illustrated in Figure 5 1 data for transmission over an AVB network can be obtained from three types of sources 1 AV Traffic For transmission from the Tx AV Traffic I F of the core 2 Precise Timing Protocol PTP Packets Initiated by the software drivers using the dedicated hardware Tx PTP Packet Buffer 3 Legacy Traffic For transmission from the Tx Legacy Traffic I F of the core Tx Legacy Traffic I F The signals forming the Tx Legacy Traffic I F are defined in Table 5 2 All signals are synchronous to the Tri Mode Ethernet MAC transmitter clock tx c1k which must always be qualified by the corresponding clock enable tx c1k en see Table 5 1 This interface is intentionally identical to the clie
12. 3 Legacy Traffic For transmission from the Legacy Traffic I F of the core The transmitter Tx arbiter must prioritize these packets To aid with this the arbiter contains configuration registers that can be used to set the percentage of available Ethernet bandwidth reserved for AV traffic To comply with the specifications this should not be configured to exceed 75 The arbiter then polices this bandwidth restriction for the AV traffic and ensures that on average it is never exceeded Consequently despite the AV traffic having a higher priority than the legacy traffic there is always remaining bandwidth available to schedule legacy traffic The output of the arbiter should be connected directly to the client Tx interface of the connected Ethernet MAC as illustrated See Chapter 6 Ethernet AVB Endpoint Transmission for further information Rx Splitter The input to the splitter is connected directly to the client Receive Rx interface of the connected Ethernet MAC Received data from an AVB network can be of three types e Precise Timing Protocol PTP Packets Routed to the dedicated hardware Rx PTP Packet Buffers which can be accessed by the Software Drivers PTP packets are identified by searching for a specific value in the MAC Length Type field e AV Traffic Routed to the AV Traffic I F of the core These packets are identified by searching for MAC packets containing a MAC VLAN field with one of two possible configur
13. conjunction with recent historical data to calculate the error between its local RTC counter and that of the RTC clock master The software will then periodically calculate an RTC correction value and an updated increment rate and these values are written to appropriate RTC configuration registers See Chapter 13 Software Drivers for further information Tri Mode Ethernet MACs Although not part of the Ethernet AVB Endpoint core a Xilinx Tri Mode Ethernet MAC core is a requirement of the system see Figure 5 1 and Figure 5 2 The IEEE Audio Video Bridging technology stipulates the following configuration requirements on this MAC e The MAC must only operate in full duplex mode e The MAC must only operate at 100 Mbps and or 1 Gbps e VLAN mode must be enabled the AV traffic will always contain VLAN fields e Flow Control is not supported on the network and must be disabled e Jumbo Frames are not supported and must be disabled e The built in Address Filter Module of the MAC must be disabled 46 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Core Interfaces Core Interfaces All ports of the core are internal connections in FPGA fabric All clock signals are inputs and no clock resources are used by the core This enables clock circuitry to be implemented externally to the core netlist providing full flexibility for clock sharing with other custom logic Clocks and Reset Table 5 1 defines t
14. offset will occur on every clock cycle of the RTC reference clock The result from this addition forms the new value of the Synchronized RTC nanoseconds field It is this version of the RTC nanoseconds field which is made available as an output of the core the rtc_nanosec_field 31 0 port Increment of the Seconds Field The RTC seconds field is conceptually implemented in a similar way to the nanoseconds field The seconds field should be incremented by a value of one whenever the synchronized RTC nanoseconds field saturates at one second The RTC Offset Control Registers allow the software to make large step corrections to the seconds field in a similar manner Again the step correction capability can be used to either initialize the RTC counter following reset or to synchronize the local RTC to that of the Grand Master Clock when the local device is acting as a clock slave 78 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Time Stamping Logic Clock Outputs Based on the Synchronized RTC Nanoseconds Field The c1k8k 8 kHz clock output derived from the Synchronized RTC is provided as an output from the core The synchronized RTC counter unlike the controlled frequency version has no long term drift assuming the provided software drivers are used correctly Therefore the c1k8k signal will be synchronized exactly to the network RTC frequency The 8 KHz clock is the period of the short
15. rx frame bad Figure 7 8 Errored Frame Reception across the AV Traffic Interface 4 As illustrated in Figure 7 8 reception of any frame in which the av rx frame bad is asserted in place of av xx frame good indicates that this frame must be discarded by the AV client it was either received with errors or was not intended for the AV traffic interface 74 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 6 Real Time Clock and Time Stamping This chapter considers two of the logical components that are partially responsible for the AVB timing synchronization protocol e Real Time Clock e Time Stamping Logic These are both described in this chapter as they are closely related Real Time Clock A significant component of the PTP network wide timing synchronization mechanism is the Real Time Counter RTC which provides the common time of the network Every device on the network will maintain its own local version The RTC is effectively a large counter which consists of a 32 bit nanoseconds field the unit of this field is 1 nanosecond and this field will count the duration of exactly one second then reset back to zero and a 48 bit seconds field the unit of this field is one second this field will increment when the nanosecond field saturates at 1 second The seconds field only wraps around when its count fully saturates The entire RTC is therefore designed neve
16. 0 RO tx_frame_waiting indication The Tx PTP Packet Buffer is split into 8 regions of 256 bytes each of which can contain a separate PTP frame There is 1 tx_frame_waiting bit for each of the 8 regions Each bit when logic 1 indicates that a request has been made for frame transmission to the Tx Arbiter but that a grant has not yet occurred When the frame has been successfully transmitted the bit will be set to logic 0 This bit allows the microprocessor to run off a polling implementation as opposed to the Interrupts 18 16 0 RO tx_packet indicates the number block RAM bin position of the most recently transmitted PTP packet 31 19 0 RO Unused Note A read or a write to this register clears the interrupt_ptp_tx interrupt asserted after each successful PTP packet transmission 92 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Rx PTP Packet Control Register PLB Address Map and Register Definitions Table 10 2 defines the associated control register of the Rx PTP Packet Buffer used by the Software Drivers to monitor the position of the most recently received PTP frame Table 10 2 Rx PTP Packet Buffer Control Register PLB_base_address 0x2004 Bit no Default Access Description 0 0 WO rx_clear When written with a 1 forces the buffer to empty in practice moving the write address to the same value as the read addre
17. 0x5000 Receiver Configuration Word 0 PLB base address 0x5200 Receiver Configuration Word 1 PLB base address 0x5400 Transmitter Configuration PLB base address 0x5600 Flow Control Configuration PLB base address 0x5800 MAC Speed Configuration PLB base address 0x5A00 Management Configuration MAC Address Filter Registers The Address Filter optionally present in the Tri Mode Ethernet MAC LogiCORE IP solution must not used Instead new Legacy MAC Header Filters have been added to the Receiver Legacy Traffic path which is capable of providing address recognition for eight unique MAC addresses See MAC Header Filter Configuration Ethernet AVB Endpoint User Guide UG492 July 23 2010 www xilinx com XILINX MAC MDIO Registers The Tri Mode Ethernet MAC has MDIO master capability To access an MDIO register via the Ethernet MAC construct the address as follows PLB Address Map and Register Definitions MDIO register address PLB_base_address 0x6000 MDIO_ADDRESS 8 where MD IO A DDRESS is a 10 bit b inary address constructed from the 5 bit MDIO Physical Address PHYAD and the 5 bit MDIO Register Address REGAD as follows MDIO ADDRESS PHYAD RI See the Tri Mode Ethernet MAC User Guide and IEEE802 3 for further MDIO information Ethernet AVB Endpoint User Guide UG492 July 23 2010 EGADJ www xili
18. 1048576 1 229 fraction of one nanosecond For this reason the RTC increment rate can be adjusted to a very fine degree of accuracy This provides the following features e The RTC can be incremented from any available clock frequency that is greater than the AVB standards defined minimum of 25 MHz However the faster the frequency of the clock the smaller will be the step increment and the smoother will be the overall RTC increment rate Xilinx recommends clocking the RTC logic at 125 MHz because this is a readily available clock source obtained from the transmit clock source of the Ethernet MAC at 1 Gbps speed This frequency significantly exceeds the minimum performance of the P802 1AS specification e When acting as a clock slave the rate adjustment of the RTC can be matched to that of the network clock master to an exceptional level of accuracy The software drivers provided with this core will periodically calculate the increment rate error between itself and the master and update the RTC increment value accordingly The core also contains a configuration register which allows a large step change to be made to the RTC This can be used to initialize the RTC after power up It is also used to make periodic corrections as required by the software drivers when operating as a clock slave if the increment rates are closely matched these periodic step corrections will be small See Chapter 9 Precise Timing Protocol Packet Buffers fo
19. Compiles the structural UniSim simulation model Compiles HDL example design source code Compiles the demonstration test bench Starts a simulation of the test bench Opens a Wave window and adds signals of interest Runs the simulation to completion Ethernet AVB Endpoint User Guide www xilinx com 151 UG492 July 23 2010 Chapter 15 Detailed Example Design Standard Format g XILINX Timing Simulation The test script is a ModelSim IES or VCS macro that automates the simulation of the test bench and is in the following location lt project_dir gt lt component_name gt simulation timing The test script performs the following tasks e Compiles the SimPrim based gate level netlist simulation model e Compiles the demonstration test bench e Starts a simulation of the test bench using back annotated timing information SDF e Opens a Wave window and adds signals of interest e Runs the simulation to completion Example Design 152 Figure 15 1 illustrates the complete example design for the Ethernet AVB Endpoint Individual sub blocks are described in the following sections Example Design Top Level Tx Frame AV Traffic Stimulus Loopback Module Tx Frame Ethernet Stimulus Legacy AVB Traffic Endpoint Core l l l Legacy i ENRETE Traffic _ Checker Rx Frame Checker AV Traffic Interrupts Figure 15 1 Example Design HDL for the Ethernet AVB Endpoint Note The example design is designed to allow the
20. Ethernet AVB Endpoint User Guide www xilinx com 161 UG492 July 23 2010 Chapter 16 Detailed Example Design EDK format XILINX pcores eth_avb_endpoint_v2_04_a hdl vhdl Contains a VHDL wrapper file for the core netlist to enable integration into Platform Studio Table 16 5 Driver Data Directory Name Description lt project_dir gt lt component_name gt MyProcessorIPLib pcores eth avb endpoint v2 04 hdl vhdl eth avb endpoint vhd This is a wrapper file around the Ethernet AVB Endpoint netlist to enable dynamic PLB address assignment from within Platform Studio Back to Top pcores eth avb endpoint v2 04 a netlist The pcore netlist directory contains the netlist for the core that was synthesized during core generation Table 16 6 pcore netlist Directory Name Description lt project_dir gt lt component_name gt MyProcessorIPLib pcores eth_avb_endpoint_v2_04 netlist lt component_name gt ngc Netlist for the core that was synthesized during core generation Back to Top MyProcessorlPLib drivers avb v2 04 a A directory containing the software device drivers for the Ethernet AVB Endpoint core and associated supporting files 162 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Directory and File Contents drivers avb v2 04 a data The driver data directory contains the data files for automatic generation of parameter specific files when int
21. Example Design and Test Bench 138 Figure 14 2 Ethernet AVB Endpoint Core Customization Screen 140 Chapter 15 Detailed Example Design Standard Format Figure 15 1 Example Design HDL for the Ethernet AVB Endpoint 152 Figure 15 2 Ethernet AVB Endpoint Demonstration Test Bench 156 Figure 15 3 Simulator Wave Window Contents sess 158 10 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 16 Detailed Example Design EDK format Appendix A RTC Time Stamp Accuracy Figure A 1 RTC Periodic Error 0 0666s Figure A 2 RTC Sampling Logic 0 00 0 c cece eee eee eee Figure A 3 Sampling Position Uncertainty 0 000 Figure A 4 Overall Time Stamp Accuracy 060000 eh Ethernet AVB Endpoint User Guide www xilinx com UG492 July 23 2010 11 12 www xilinx com XILINX Ethernet AVB Endpoint User Guide UG492 July 23 2010 Schedule of Tables Chapter 1 Chapter 2 Chapter 3 Chapter 4 Table 4 1 Chapter 5 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Table 5 6 Table 5 7 Table 5 8 Table 5 9 Table 5 10 Table 5 11 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Table 10 1 Table 10 2 Table 10 3 Table 10 4 Table 10 5 Table 10 6 Introduction Licensing the Core Overview of Ethernet Audio
22. Figure 10 2 Single Write Transaction 000 000 ccc e 89 Figure 10 3 PLB Address Space of the Ethernet AVB Endpoint Core and Connected Tri Mode Ethernet MAC 0 0 0 en 91 Chapter 11 Constraining the Core Chapter 12 System Integration Figure 12 1 Connection to the Tri Mode Ethernet MAC Core without Ethernet Statistics 0 0 eect e 113 Figure 12 2 Connection to the Tri Mode Ethernet MAC and Ethernet Statistic Cores 115 Figure 12 3 Connection to the Virtex 5 FPGA Embedded Tri Mode Ethernet MAC without Ethernet Statistics 0 0 0 0 eee 117 Figure 12 4 Connection to the Virtex 5 FPGA Embedded Tri Mode Ethernet MAC and Ethernet Statistic Core 0 00 cee eee 118 Figure 12 5 Connection of the Ethernet AVB Endpoint Core into an Embedded Processor Sub system 00 cese Re rem e e rr EIER CLIP EP eres 120 Figure 12 6 Connection into an Embedded Processor Sub system with an EDK Top level Project 5 e tte ei emere veges ieee ree eran 121 Figure 12 7 Connection into an Embedded Processor Sub system with an ISE Software Top Level Project 0 eee 122 Figure 12 8 Connection of the Ethernet AVB Endpoint Core into an Embedded Processor Sub systeim is syed serre enig Ka ERE E bere bas 125 Figure 12 9 Connection to the XPS LocalLink Tri Mode Ethernet MAC 127 Chapter 13 Software Drivers Chapter 14 Quick Start Example Design Figure 14 1 Ethernet AVB Endpoint
23. Filters 40 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX EDK pcore Format EDK pcore Format Figure 5 2 illustrates the functional blocks of the Ethernet AVB Endpoint core when it is generated in EDK pcore format As illustrated this is intended to be connected to the XPS LocalLink Tri Mode Ethernet MAC Each of the functional blocks illustrated will be introduced in the following sections of this chapter However observe from the figure that e The xps_ll_temac contains its own PLB interface Consequently the logic connecting the PLB Interface of the Ethernet AVB Endpoint core to the Host I F as seen in Figure 5 1 is not present in this case e The Legacy Traffic Interface of the Ethernet AVB Endpoint core is connected directly to the xps ll temac this allows the xps_ll_temac core to source and sink legacy frame data such as TCP IP protocol traffic The full duplex AV Traffic Interface remains for connection to custom logic e The MAC Header Filters as seen in Figure 5 1 are not present in this case The xps ll temac instead contains its own Address Filter logic Ethernet AVB Endpoint Tiefe AV Traffic I F Te Arbiter XPS LocalLink Tri Mode bim e Ethernet MAC Avb2TemacTxData Chen software drivers Temac2AvbRxData Precise Timing Protocol PTP Tx Time Stam ERES EB Tx PTP Packet Buffer p x Micro PLB
24. Generate as an EDK pcore AV TX DONE TX UNDERRUN AV TX ACK TX_ACK The generated core will include the standard Core Generator deliverables HDL TX RESET example design scripts demonstration testbench AV RX DATA 7 0 AV RX VALID RX CLK AV RX FRAME GOOD RX CLK EN AV RX FRAME BAD RX DATA 0 RX DATA VALID LEGACY TX DATA 7 0 RX FRAME GOOD LEGACY TX DATA VALID RX FRAME BAD LEGACY TX UNDERRUN RX RESET LEGACY TX ACK Datasheet lt Back Page 1 of 2 Next gt Figure 4 1 GUI Page 1 Ethernet AVB Endpoint User Guide www xilinx com 35 UG492 July 23 2010 36 Chapter 4 Generating the Core XILINX Component Name The component name is used as the base name of the output files generated for the core Names must begin with a letter and must be composed from the following characters a through z 0 through 9 and Core Delivery Format The Ethernet AVB Endpoint core can be delivered in two different formats selectable from this section of the CORE Generator software Customization GUI Standard CORE Generator software format provided for the standard ISE software environment This option will deliver the core in the standard CORE Generator software output format as used by many other cores including previous versions of this core and all other Ethernet LogiCORE IP solutions When generated in this format the core is designed to interface to the Log
25. Itcan be used by an Ethernet AVB Endpoint System that is configured as a talker to time a class measurement interval for an SR stream The class measurement interval for a stream depends upon the SR class associated with the stream SR class A corresponds to a class measurement interval of 125 microseconds SR class B corresponds to a class measurement interval of 250 microseconds The class measurement interval for a stream is used to limit the number of data frames that are placed into the stream s queue per class measurement interval e Itcan be used by higher layer applications for example IEEE1722 to provide presentation time stamps for audio and video data This is used for example to synchronize the lip sync on a TV set so a viewer hears the words at the same time as they see the lips move The P802 1AS specification is implemented in the Ethernet AVB Endpoint using a combination of hardware and software The hardware components are incorporated into the core and the software component is provided with the core in the form of drivers These drivers should be run on an embedded processor MicroBlaze or PowerPC 30 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX P802 1Qav AVB Specifications This specification defines the mechanism for queuing and forwarding AV traffic from a talker to a listener across the network This can involve several network hops network bridge devices that the d
26. July 23 2010 13 XILINX Table 10 7 Seconds Field Offset bits 31 0 PLB_base_address 0x2808 95 Table 10 8 Seconds Field Offset bits 47 32 PLB_base_address 0x280C 95 Table 10 9 RTC Increment Value Control Register PLB_base_address 0x2810 95 Table 10 10 Current RTC Nanoseconds Value PLB_base_address 0x2814 96 Table 10 11 Current RTC Seconds Field Value bits 31 0 PLB_base_address 0x2818 96 Table 10 12 Current RTC Seconds Field Value bits 47 32 PLB_base_address 0x281C 0 0c cee cece eee en 96 Table 10 13 RTC Interrupt Clear Register PLB_base_address 0x2820 96 Table 10 14 RTC Phase Adjustment Register PLB_base_address 0x2824 97 Table 10 15 Software Reset Register Address at PLB_base_address 0x2828 97 Table 10 16 MAC Header Filter Configuration Registers 00005 98 Table 10 17 Tri Mode Ethernet MAC and Ethernet Statistics Configuration Registers lisse 100 Chapter 11 Constraining the Core Chapter 12 System Integration Chapter 13 Software Drivers Chapter 14 Quick Start Example Design Chapter 15 Detailed Example Design Standard Format Table 15 1 Project Directory oce ese Eo bn het aeter le ete e etg 144 Table 15 2 Component Name Directory 000s 145 Table15 3 Doc Directory ils occ eset haere Utere eir mtra ee eds 145 Table 15 4 Example Design Directory
27. MAC Received data from an AVB network can be of three types e Precise Timing Protocol PTP Packets Routed to the dedicated hardware Rx PTP Packet Buffer which can be accessed by the Software Drivers PTP packets are identified by searching for a specific MAC Destination Address e AV Traffic Routed to the Rx AV Traffic I F of the core These packets are identified by searching for MAC packets containing a MAC VLAN field with one of two possible configurable VLAN priority values see Rx Filtering Control Register e Legacy Traffic Routed to the Rx Legacy Traffic I F of the core All packet types which are not identified as PTP or AV Traffic will be considered legacy traffic Rx Legacy Traffic I F The signals forming the Rx Legacy Traffic I F are defined in Table 5 3 All signals are synchronous to the Tri Mode Ethernet MAC receiver clock xx c1k which must always be qualified by the corresponding clock enable xx c1k en see Table 5 1 This interface is intentionally identical to the client receiver interface of the supported Xilinx Tri Mode Ethernet MAC core there is a one to one correspondence between signal names of the block level wrapper from the Tri Mode Ethernet MAC example design after the legacy prefix is removed This provides backward compatibility all existing MAC client side designs which use the clock enable should be able to connect to the legacy Ethernet port unmodified Operation of the
28. Rx Legacy Traffic Interface is closely connected with the frame header match results of the Legacy MAC Header Filters If the filters are enabled and do not obtain a match the frame data does not appear on this interface Legacy rx data validand legacy rx frame good legacy rx frame bad are not asserted When a match is obtained these signals are asserted as described in the following sections Ethernet AVB Endpoint User Guide www xilinx com 65 UG492 July 23 2010 Chapter 7 Ethernet AVB Endpoint Reception g XILINX Error Free Legacy Frame Reception rx clk enable legacy rx data 7 0 a sa ur hk DATA legacy_rx_data_valid legacy_rx_frame_good J legacy_rx_frame_bad Figure 7 1 Normal Frame Reception across the Legacy Traffic Interface Figure 7 1 illustrates the timing of a normal inbound error free frame transfer that has been accepted by the Legacy MAC Header Filters The legacy client must be prepared to accept data at any time there is no buffering within the core to allow for latency in the receive client After frame reception begins data is transferred on consecutive clock enabled cycles to the receive client until the frame is complete The core asserts the legacy_rx_frame_good signal to indicate that the frame was intended for the legacy traffic client and was successfully received without error 66 www xilinx com Ethernet AVB Endpoint User Guide UG
29. Video Bridging Generating the Core XCO File Values and Default Values 0 000 000 0 ccc eee eee Core Architecture Clocks and Resets ii icc sce dg e d e deca RR E be Ra Legacy Traffic Signals Transmitter Path 0 0 00 cece eee eee Legacy Traffic Signals Receiver Path 0 0 cece eee AV Traffic Signals Transmitter Path 0 eee AV Traffic Signals Receiver Path Tri Mode Ethernet MAC Transmitter Interface 0000045 Tri Mode Ethernet MAC Receiver Interface 000 cece eee Tri Mode Ethernet MAC Host Interface Configuration Status PLBSignals i e RR e b exe REPE CH ER y EU E bd Interrupt Signals cessere seeded serge nage creed IA ere PUP Signals uper one She dat nies emus hot de pute ico etus Ethernet AVB Endpoint Transmission Ethernet AVB Endpoint Reception Real Time Clock and Time Stamping Precise Timing Protocol Packet Buffers Configuration and Status Tx PTP Packet Buffer Control Register PLB base address 0x2000 Rx PTP Packet Buffer Control Register PLB base address 0x2004 Rx Filtering Control Register PLB base address 0x2008 Tx Arbiter Send Slope Control Register PLB base address 0x200C Tx Arbiter Idle Slope Control Register PLB base address 0x2010 RTC Nanoseconds Field Offset PLB base address 0x2800 Ethernet AVB Endpoint User Guide www xilinx com UG492
30. W Match Pattern Ethernet frame bits 64 to 95 0x3000 32 bit pattern to match against the Ethernet filters 0x20 frame bits 64 to 95 Specifically match pattern 0x8 bits 31 0 MAC Source Address bits 47 16 98 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX PLB Address Map and Register Definitions Table 10 16 MAC Header Filter Configuration Registers Cont d Address PLB_base_address 0x3000 filter 0x20 0xC Default Access 0x00000000 R W Description Match Pattern Ethernet frame bits 96 to 127 32 bit pattern to match against the Ethernet frame bits 96 to 127 For frames with a VLAN tag match pattern bits 31 0 can be matched against the full VLAN field For frames without a VLAN match pattern bits 15 0 can be matched against the Length Type field PLB base address 0x3000 filter 0x20 0x10 OxFFFFFFFF R W Match Enable Ethernet frame bits 0 to 31 There is a 1 to 1 correspondence between all bits in this register and all bits in the Match Pattern Ethernet frame bits 0 to 31 register For each bit logic 1 enables the match the corresponding bit in the Match Pattern will be compared logic 0 disables the match the corresponding bit in the Match Pattern will be a don t care PLB base address 0x3000 filter 0x20 0x14 0x0000FFFF R W Match Enable Ethernet frame bits 32
31. XCO file can also be used as an input to the CORE Generator software lt component_name gt _flist txt List of files delivered with the core Back to Top 144 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Directory and File Contents lt project directory gt lt component name gt The lt component name gt directory contains the release notes file provided with the core which may include last minute changes and updates Table 15 2 Component Name Directory Name Description lt project_dir gt lt component_name gt eth_avb_endpoint_readme txt Core release notes file Back to Top lt component name gt doc The doc directory contains the PDF documentation provided with the core Table 15 3 Doc Directory Name Description lt project_dir gt lt component_name gt doc eth_avb_endpoint_ds677 pdf Ethernet AVB Endpoint Data Sheet eth_avb_endpoint_ug492 pdf Ethernet AVB Endpoint User Guide Back to Top lt component name gt example design The example design directory contains the example design files provided with the core For more information see Example Design page 152 Table 15 4 Example Design Directory Name Description project dir component name example design component name example design ucf Example User Constraints File UCF P P amp P provided for the example design
32. any time to halt the IEEE802 1 AS PTP protocol by calling the following function XAvb Stop InstancePtr The software example included will halt the drivers whenever the Ethernet PHY Auto Negotiation indicates that it has lost the link or has negotiation to an unsupported ethernet mode for example half duplex 136 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 14 Quick Start Example Design The quick start steps provided in this chapter let you quickly generate an Ethernet AVB Endpoint core run the design through implementation with the Xilinx tools and simulate the design using the provided demonstration test bench For detailed information about the Standard CORE Generator example design see Chapter 15 Detailed Example Design Standard Format For detailed information about the EDK pcore example design seeChapter 16 Detailed Example Design EDK format Overview The Ethernet AVB Endpoint example design consists of the following e Ethernet AVB Endpoint core netlist e Example design HDL top level and associated HDL files e Demonstration test bench to exercise the example design Ethernet AVB Endpoint User Guide www xilinx com 137 UG492 July 23 2010 Chapter 14 Quick Start Example Design g XILINX The Ethernet AVB Endpoint example design has been tested using Xilinx ISE software v12 2 Cadence Incisive Enterprise Simulator IES v9 2 Mentor Graphi
33. bus PLB PAvaild Input PLB primary address valid indicator PLB SAValid Input Unused PLB secondary address valid indicator PLB rdPrim Input Unused PLB secondary to primary read request indicator PLB wrPrim Input Unused PLB secondary to primary write request indicator PLB masterID Input PLB current master identifier 0 log2 NUM_MASTERS PLB_abort Input PLB abort request indicator PLB_busLock Input Unused PLB bus lock PLB_RNW Input PLB read not write PLB_BE 0 3 Input PLB byte enables PLB_MSize 0 1 Input PLB master data bus size PLB_size 0 3 Input PLB transfer size Only support size 0 PLB_type 0 2 Input PLB transfer type Only support type 0 PLB_TAttribute 0 15 Input Unused PLB transfer attribute bus PLB_lockErr Input Unused PLB lock error indicator PLB_wrDBus 0 31 Input PLB write data bus PLB_wrBurst Input PLB write burst transfer indicator PLB_rdBurst Input PLB read burst transfer indicator PLB_rdPendReq Input Unused PLB pending read request priority PLB_wrPendReq Input Unused PLB pending write request priority PLB_rdPendPri 0 1 Input Unused PLB pending read bus request indicator Ethernet AVB Endpoint User Guide www xilinx com 53 UG492 July 23 2010 Chapter 5 Core Architecture 54 Table 5 9 PLB Signals Cont d XILINX PIN Name Direction Description PLB wrP
34. clk TNM NET ree clk TIMEGRP rtc_clock rtc cik TIMESPEC TS rtc clock PERIOD rtc clock 8000 ps HIGH 50 Timespecs for Critical Logic within the Core Signals must cross clock domains at certain points within the core To guarantee that these signals are sampled correctly on the new clock domain many constraints are required and must not be removed These constraints are also present in the example design UCF delivered with the core JEEAEEATERETEHERE HERE AERE THERE HERE HEHETEHERE HERE TEHETEHERE HERE TEHETEHERE HE ETHER HERE HERE TEHERE HERE HE ETHER IE E E E Clock Domain Crossing Constraints JEEAEEAERETEHETE HERE AERE TEHERE HERE IEEE ERE HERE TEHETEHERE HERE TEHETEHERE HE ETHER HERE HERE TEE HERE HE ETHER IE E E E clock domain crossing constraints for Tx timestamp logic INST top tx rtc sample inst sample toggle req TNM FFS tx sample req INST top tx rtc sample inst resync sample toggle req data sync TNM FFS tx sample req resync TIMESPEC ts tx sample req FROM tx sample req TO tx sample req resync 6 5 ns DATAPATHONLY INST top tx rtc sample inst sample taken toggle TNM FFS tx sample taken INST top tx rtc sample inst resync sample taken toggle data sync TNM FFS tx sample taken resync TIMESPEC ts tx sample taken FROM tx sample taken TO tx sample taken resync TIG INST top tx rtc sampl
35. data valid EMACOCLIENTRXDVLD EMACOCLIENTRXSTATSVLD NC EMACOCLIENTRXGOODFRAME EMACOCLIENTRXSTATSBYTEVLD Nc EMACOCLIENTRXBADFRAME rx frame good rx frame bad host opcode 1 0 HOSTOPCODE 1 0 host addr 9 0 HOSTADDR 9 0 host wr data 31 0 gt HOSTWRDATA 31 0 host req HOSTREQ host miim sel bm HOSTMIIMSEL host miim rdy HOSTMIIMRDY host rd data mac 31 0 host rd data stats 31 0 HOSTRDDATA 31 0 host stats Isw rdy HOSTCLK host stats msw rdy HOSTEMAC1SEL host_clk ost c I 9 GND GND host clk Figure 12 3 Connection to the Virtex 5 FPGA Embedded Tri Mode Ethernet MAC without Ethernet Statistics Figure 12 3 illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri Mode Ethernet MAC EMAC core when not using the Ethernet Statistics core Figure 12 3 provides detail for the connections between the two cores which were shown in Figure 5 1 All connections as shown are logic less connections Because the AVB standard does not include support for half duplex or flow control operation the relevant half duplex flow control signals of the EMAC can be left unused inputs can be tied to logic 0 outputs can be left unconnected Ethernet AVB Endpoint User Guide www xilinx com 117 UG492 July 23 2010 Chapter 12 System Integration XILINX Because the EMAC core can often be used in different clocking mo
36. e selected from the CORE Generator software Customization GUI see PLB Base Address in Chapter 4 when the core is generated in Standard CORE Generator Format e automatically assigned and configured when the core is generated in EDK pcore Format 90 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX PLB Address Map and Register Definitions The entire address space is now described in two sections e Ethernet AVB Endpoint Address Space e ri Mode Ethernet MAC Address Space which can be addressed through the Ethernet AVB Endpoint core Address Space This address is only present when the core is generated in Standard CORE Generator Format Address Ox7FFF Tri Mode Ethernet MAC MDIO PHY Management 0x6000 TEMAC Address Space Tri Mode Ethernet MAC Configuration and Statistics 0x4000 Reserved 0x3100 Address Filter Configuration 0x3000 0x2900 AVB RTC Configuration 0x2800 0x201C Address Space Ethernet AVB Endpoint AVB Tx Rx Configuration 0x2000 Reserved 0x1800 Tx PTP Packet Buffer 0x1000 RxPTP Packet Buffer PLB base address 0x0000 Figure 10 3 PLB Address Space of the Ethernet AVB Endpoint Core and Connected Tri Mode Ethernet MAC Ethernet AVB Endpoint User Guide www xilinx com 91 UG492 July 23 2010 Chapter 10 Configuration and Status XILINX Ethernet AVB Endpoint Address Space Rx PTP Pa
37. import and connect pcore peripherals rather than by manually editing the mhs file for a given project Please refer to Xilinx Platform Studio documentation Certain lines are highlighted and commented to draw attention Ethernet AVB Endpoint User Guide UG492 July 23 2010 www xilinx com 127 Chapter 12 System Integration XILINX B E B EGIN xps 11 temac PARAMETER INSTANCE Hard Ethernet MAC PARAMETER C NUM IDELAYCTRL 2 PARAMETER C IDELAYCTRL LOC IDELAYCTRL XOYA4 IDELAYCTRL X1Y5 PARAMETER C FAMILY virtex5 PARAMETER C PHY TYPE 1 PARAMETER C TEMAC1 ENABLED 0 PARAMETER C BUS2CORE CLK RATIO 1 PARAMETER C TEMAC TYPE 0 PARAMETER C TEMACO PHYADDR 0b00001 PARAMETER HW VER 2 02 a PARAMETER C TEMACO AVB 1 Enable AVB connections PARAMETER C BASEADDR 0x81c00000 PARAMETER C HIGHADDR 0x81cOffff BUS INTERFACE SPLB mb plb BUS INTERFACE LLINKO PORT TemacIntcO0 Irpt PORT TemacPhy RST n PORT GTX CLK 0 clk 125 0000MHzPLLO PORT REFCLK clk 200 0000MHz PORT LlinkTemacO0 CLK clk 125 0000MHzPLLO PORT MII TX CLK O0 fpga 0 Hard Ethernet MAC MII TX CLK 0 Hard Ethernet MAC LLINKO Hard Ethernet MAC TemacIntcO0 Irpt fpga 0 Hard Ethernet MAC TemacPhy RST n pin pin PORT GMII TXD O0 fpga 0 Hard Ethernet MAC GMII TXD 0 pin PORT GMII TX EN 0 fpga 0 Hard Eth
38. rtc configuration inst rtc cpu reclock wr toggle TNM FFS rtc wr toggle INST top rtc inst rtc configuration inst rtc cpu reclock resync write tog gle data sync TNM FFS resync rtc write toggle TIMESPEC ts rtc wr toggle FROM rtc wr toggle TO resync rtc write toggle TIG INST top rtc inst rtc configuration inst rtc cpu reclock rd toggle TNM FFS rtc rd toggle INST top rtc inst rtc configuration inst rtc cpu reclock resync read togg le data sync TNM FFS resync rto read toggle TIMESPEC ts rtc rd toggle FROM rtc rd toggle TO resync rtc read toggle TIG INST top rtc inst rtc configuration inst rtc cpu reclock new rd toggle TNM FFS cpu rtc rd toggle INST top rtc inst rtc configuration inst rtc cpu reclock resync new rd to ggle data sync TNM FFS resync cpu rto rd toggle TIMESPEC ts cpu rtc rd toggle FROM cpu rtc rd toggle TO resync cpu rtc rd toggle TIG INST top rtc inst rtc configuration inst rtc cpu reclock new wr toggle TNM FFS cpu rtc wr toggle INST top rtc inst rtc configuration inst rtc cpu reclock resync new wr to ggle data sync TNM FFS resync cpu rtc wr toggle TIMESPEC ts cpu rtc wr toggle FROM cpu rtc wr toggle TO resync cpu rtc wr toggle TIG INST top rtc inst rtc configuration inst rtc cpu reclock new be TNM FFS rtc cpu sample INST top rtc inst rtc configuration inst rtc cpu reclock new addr TNM F
39. should be set to logic 1 immediately following the end of frame transmission This than allows the Tx Arbiter to schedule legacy traffic transmission if any legacy frames are queued If following the end of frame reception the bandwidth allocation for AV traffic has been exceeded the Tx Arbiter switches to service the legacy traffic regardless of the state of the av_tx_done signal For this reason the av_tx_done signal should be considered an aid to the Tx Arbiter to help make best use of the available network bandwidth Asserting this signal after all AV traffic has been serviced immediately allows the Tx Arbiter to service the legacy traffic This helps achieve in excess of the 25 minimum allocation for the legacy traffic However holding off the assertion of av_tx_done will not act as cheat mode to exceed the maximum bandwidth allocation for the AV traffic www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Tx Arbiter Tx Arbiter Overview As illustrated in Figure 5 1 data for transmission over an AVB network can be obtained from three types of sources 1 AV Traffic For transmission from the AV Traffic I F of the core 2 Precise Timing Protocol PTP Packets Initiated by the software drivers using the dedicated hardware Tx PTP Packet Buffer 3 Legacy Traffic For transmission from the Legacy Traffic I F of the core The transmitter Tx arbiter selects from these
40. stats Isw rdy rx statistics valid host stats msw rdy TX Statistics vector 27 0 J amp host clk Figure 12 2 Connection to the Tri Mode Ethernet MAC and Ethernet Statistic Cores Figure 12 2 illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri Mode Ethernet MAC TEMAC core when using the Ethernet Statistics core This shares much in common with Figure 12 1 but take note of the following additional points e Allthe MAC Management Interface output signals of the Ethernet AVB Endpoint core connect directly to the signals of the same name at both the TEMAC and Ethernet Statistics cores e The Ethernet AVB Endpoint core provides two separate MAC Management Interface inputs for management reads This allows for logic less connections between all three cores as illustrated To achieve this connect host_rd_data_mac 31 0 of the Ethernet AVB Endpoint core to the host_rd_data 31 0 port of the TEMAC connect host_rd_data_stats 31 0 of the Ethernet AVB Endpoint core to the host_rd_data 31 0 port of the Ethernet Statistics core Ethernet AVB Endpoint User Guide UG492 July 23 2010 www xilinx com 115 Chapter 12 System Integration g XILINX LogiCORE IP Embedded Tri Mode Ethernet MACs Virtex 5 FPGA Embedded Tri Mode Ethernet MAC Wrapper Generation When generati
41. the core to be reset This also asserts the tx reset signal of Table 5 1 This reset does not affect transmitter configuration settings If read always returns 0 1 0 WO Receiver path reset When written with a 1 forces the entire receiver path of the core to be reset This also asserts the xx reset signal of Table 5 1 This reset does not affect receiver configuration settings If read always returns 0 2 0 WO PTP Transmitter logic reset When written with a 1 forces the PTP transmitter logic of the core to be reset This is a subset of the full transmitter path reset of bit 0 This reset does not affect PTP transmitter configuration settings If read always returns 0 Ethernet AVB Endpoint User Guide www xilinx com 97 UG492 July 23 2010 Chapter 10 Configuration and Status g XILINX Table 10 15 Software Reset Register Address at PLB_base_address 0x2828 Bit Number Default Access Description 3 0 WO PTP Receiver logic reset When written with a 1 forces the PTP receiver logic of the core to be reset This is a subset of the full receiver path reset of bit 1 This reset does not affect PTP receiver configuration settings If read always returns 0 31 4 0 RO Unused MAC Header Filter Configuration When the core is generated in EDK pcore Format the Legacy MAC Header Filters are not included since the xps ll temac can optionally co
42. three sources in the following manner e If there is AV packet available and the programmed AV bandwidth limitation is not exceeded then the AV packet is transmitted e otherwise the Tx arbiter checks to see if there are any PTP packets to be transmitted otherwise if there is an available legacy packet then this will be transmitted The Ethernet AVB Endpoint core contains configuration registers to set up the percentage of available Ethernet bandwidth reserved for AV traffic To comply with the IEEE P802 1 Qav specification these should not be configured to exceed 75 The arbiter then polices this bandwidth restriction for the AV traffic and ensures that on average it is never exceeded Consequently despite the AV traffic having a higher priority than the legacy traffic there is always remaining bandwidth available to schedule legacy traffic The relevant configuration registers for programming the bandwidth percentage dedicated to AV traffic are defined in Chapter 10 Configuration and Status and are e Tx Arbiter Send Slope Control Register e Tx Arbiter Idle Slope Control Register These registers are defaulted to values which dedicate up to 75 of the overall bandwidth to the AV traffic This is the maximum legal percentage that will be defined in the IEEE802 1 AVB standards In many implementations it may be unnecessary to change these register values Correct use of the av_tx_done signal as defined in Tx AV Traffic
43. time 40000 ns The test bench allows the DUT to run until the simulation time is exceeded after this Ethernet frames already in the system are allowed to complete cleanly then the test bench reports the final statistics and end Changing Frame Data The Ethernet Frame Stimulus and Ethernet Frame Checker modules can be set to produce and check different Ethernet frames by changing the parameters sent to them These parameters are set in the Top Level Example Design HDL Editing this file allows a Functional Simulation to immediately use the new settings However because these modifications require logical changes the Implementation Scripts must be re run on the design before running a Timing Simulation Please see the Top Level Example Design HDL file for information about these frame type parameters As an example the following syntax is taken from the Verilog version of the file and contains the syntax required to configure both the Legacy Ethernet Frame Stimulus and Ethernet Frame Checker modules Configure the Legacy frames used in this example design the following parameters can be edited Use minimum sized Ethernet frames 64 bytes total length parameter 10 0 EGACY FRAME LENGTH 11 d64 Set the Destination Address to be AA BB CC DD EE FF parameter 47 0 j EGACY DEST ADDR 48 hFFEEDDCCBBAA Set the Destination Address to be 00 11 22 33 44 55 parameter 47 0 EGACY SRC ADDR 48
44. to 0 then only matching MAC headers are passed to the Rx Legacy Traffic I F Ethernet AVB Endpoint User Guide UG492 July 23 2010 www xilinx com 93 Chapter 10 Configuration and Status g XILINX 94 Tx Arbiter Send Slope Control Register The sendSlope variable is defined in IEEE P802 1 Qav to be the rate of change of credit in bits per second when the value of credit is decreasing during AV packet transmission Together with the Tx Arbiter Idle Slope Control Register registers define the maximum limit of the bandwidth that is reserved for AV traffic this will be enforced by the Tx Arbiter The default values allow the maximum bandwidth proportion of 75 for the AV traffic See the IEEE P802 1 Qav specification and Tx Arbiter for more information Table 10 4 Tx Arbiter Send Slope Control Register PLB base address 0x200C Bit no Default Access Description 19 0 2048 R W The value of sendSlope 31 20 0 RO Unused Tx Arbiter Idle Slope Control Register The idleSlope variable is defined in IEEE802 1Qav to be the rate of change of credit in bits per second when the value of credit is increasing whenever there is no AV packet transmission Together with the Tx Arbiter Send Slope Control Register two registers define the maximum limit of the bandwidth that is reserved for AV traffic this is enforced by the Tx Arbiter The default values allow the maximum bandwi
45. to 63 There is a 1 to 1 correspondence between all bits in this register and all bits in the Match Pattern Ethernet frame bits 32 to 63 register For each bit logic 1 enables the match the corresponding bit in the Match Pattern will be compared logic 0 disables the match the corresponding bit in the Match Pattern will be a don t care PLB base address 0x3000 filter 0x20 0x18 0x00000000 R W Match Enable Ethernet frame bits 64 to 95 There is a 1 to 1 correspondence between all bits in this register and all bits in the Match Pattern Ethernet frame bits 64 to 95 register For each bit logic 1 enables the match the corresponding bit in the Match Pattern will be compared logic 0 disables the match the corresponding bit in the Match Pattern will be a don t care PLB base address 0x3000 filter 0x20 0x1C 0x00000000 R W Match Enable Ethernet frame bits 96 to 127 There is a 1 to 1 correspondence between all bits in this register and all bits in the Match Pattern Ethernet frame bits 96 to 127 register For each bit logic 1 enables the match the corresponding bit in the Match Pattern will be compared logic 0 disables the match the corresponding bit in the Match Pattern will be a don t care Ethernet AVB Endpoint User Guide UG492 July 23 2010 www xilinx com 99 100 Chapter 10 Configuration and Status g XILINX Tri Mode Ethernet
46. to the supported embedded processors MicroBlaze or PowerPC As a result the PLB interface does not require in depth understanding and the following information is provided for reference only See the EDK documentation for further information The PLB interface defined by IBM can be complex and support many usage modes such as multiple bus masters It can support single or burst read writes and can support different bus widths and different peripheral bus widths The general philosophy of the Ethernet AVB Endpoint core has been to implement a PLB interface which is as simple as possible The following features are provided e 32 bit data width e Implements a simple PLB slave e Supports single read writes only no burst or page modes Single Read Transaction Figure 10 1 illustrates a single read data transfer on the PLB Note the following e Wait states can be added to the Address cycle by asserting S1 wait and delaying Sl addrAck e Wait states can be inserted in the Read fetch by delaying the assertion of S1 rdDAck Ethernet AVB Endpoint User Guide www xilinx com 87 UG492 July 23 2010 XILINX Chapter 10 Configuration and Status PLB_clk PLB_RNW 11111111 0 7 PLB BE 0 3 PLB size PLB type 0 2 PLB abort 0 31 PLB ABus PLB PAValid SI addrAck 0 31 PLB_wrDBus SI wrDAck p SI wrCom PLB wrBurst D A0 0 31 0000 SI rdDBus 0000 0 3 0000
47. top avb configuration inst tx cpu reclock new wr toggle TNM FFS cpu tx wr toggle INST top avb configuration inst tx cpu reclock resync new wr toggle data sync TNM FFS resync cpu tx wr toggle TIMESPEC ts cpu tx wr toggle FROM cpu tx wr toggle TO resync cpu tx wr toggle TIG INST top avb configuration inst tx cpu reclock new be TNM FFS tx cpu sample INST top avb configuration inst tx cpu reclock new addr TNM FFS tx cpu sample TIMESPEC ts tx cpu sample FROM cpu bus TO tx cpu sample 16 ns DATAPATHONLY INST top avb configuration inst clear tx int TNM FFS tx regs sample Ethernet AVB Endpoint User Guide www xilinx com 107 UG492 July 23 2010 Chapter 11 Constraining the Core XILINX INST top avb_configuration_inst tx_send_frame TNM FFS tx regs sample INST top avb configuration inst tx sendslope int TNM FFS tx regs sample INST top avb configuration inst tx idleslope int TNM FFS tx regs sample TIMESPEC ts tx regs sample FROM cpu bus TO tx regs sample 24 ns DATAPATHONLY INST top avb configuration inst rd data tx TNM FFS tx rd data INST top avb configuration inst cpu rd data TNM FFS tx cpu rd data TIMESPEC ts tx rd data FROM tx rd data TO tx cpu rd data 16 ns DATAPATHONLY clock domain crossing constraints for RTC Configuration Logic INST top rtc inst
48. trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 9 18 08 v1 1 Initial Xilinx release ISE 10 1 Update 3 4 24 09 v1 2 Updated to version 1 2 of the core Xilinx tools 11 1 6 24 09 v2 1 Updated to version 2 1 of the core Xilinx tools 11 2 9 16 09 v2 2 Updated to version 2 2 of the core Xilinx tools 11 3 4 19 10 v2 3 Updated to version 2 3 of the core Xilinx tools 12 1 7 23 10 v2 4 Updated to version 2 4 of the core Xilinx tools 12 2 Added four chapters from the Getting Started Guide to this User Guide e Licensing the Core Quick Start Example Design Detailed Example Design Standard Format Detailed Example Design EDK format The Getting Started Guide is being discontinued in this release Ethernet AVB Endpoint User Guide www xilinx com UG492 July 23 2010 Table of Contents Reviston HIStory io oda goede ye heed atte Gal we ee iU eq Oe ee hw d Rd aes Schedule of Figures aaan c cece cece cece eect teenies Schedule of Tables RR Preface About This Guide Guide Contents 0 0 cee eee een ehh hh een CONVENTIONS epe E Rb EUR NOEL EUR EEVRNEE E RUE AN RE Typographical io ee e o e E e 9 m E RE REEF cy Sede eae OnlineDocument lesse re List of Abbreviations 0 00 0 ccc ce en een e Chapter 1 Introducti
49. txt Core release notes file Back to Top 160 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Directory and File Contents lt component name gt doc The doc directory contains the PDF documentation provided with the core Table 16 3 Doc Directory Name Description project dir component name doc eth avb endpoint ds677 pdf Ethernet AVB Endpoint Data Sheet eth avb endpoint ug492 pdf Ethernet AVB Endpoint User Guide Back to Top component name MyProcessorlPLib This is the route directory which should be imported into the Xilinx Embedded Development Kit MyProcessorlPLib pcores eth avb endpoint v2 04 a A directory containing the pcore HDL and netlist hardware components for the Ethernet AVB Endpoint core and associated supporting files pcores eth avb endpoint v2 04 a data The driver data directory contains the data files for automatic integration into Platform Studio Table 16 4 Driver Data Directory Name Description project dir2 component name MyProcessorIPLib pcores eth avb endpoint v2 04 data eth avb endpoint v2 1 0 bbd Black Box description file for the core netlist eth avb endpoint v2 1 0 mpd Microprocessor Description file for the pcore contains a list and definition of ports eth avb endpoint v2 1 0 pao Peripheral Analyze Order file containing a list of HDL sources requiring synthesis Back to Top
50. 2 6 Connection into an Embedded Processor Sub system with an EDK Top level Project Figure 12 6 shows the implementation using an EDK project In this hierarchy the Ethernet AVB Endpoint Tri Mode Ethernet MAC and all custom logic blocks must be manually translated into pcores using the standard pcore approach described in Xilinx Platform Studio documentation The standard EDK flow can then be implemented to build the project Ethernet AVB Endpoint User Guide www xilinx com 121 UG492 July 23 2010 Chapter 12 System Integration g XILINX In this example the instance of the Ethernet AVB Endpoint core should be assigned a base address in the Microprocessor Hardware Specification mhs file to match that of the Ethernet AVB Endpoint PLB Base Address in the generated netlist produced by the CORE Generator software Then the AVB software drivers can be assigned to this instance in the Microprocessor Software Specification mss file Using an ISE Software Top Level Project ISE tool domain EDK tool domain BRAM Imb bram if cntlr Microblaze xps uartlite xps intc pcore plb port Ethernet AVB Endpoint Host I F MDIO PLB LL AV Custom AV logic a traffic VF Ethernet PHY I F Lg Legacy Custom Legacy logic Lg traffic VF l Figure 12 7 Connection into an Embedded Processor Sub system with an ISE Software Top Level Project 122 www xil
51. 2 Pdelay Req Frame 0x1200 0x08 reserved 1 Follow Up Frame frame length field 0x00 0x1100 0 Sync Frame Y byte wide data 0x1000 Figure 9 1 Tx PTP Packet Buffer Structure www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Rx PTP Packet Buffer Rx PTP Packet Buffer The Rx PTP packet buffer is illustrated in Figure 9 2 This provides working memory to hold each received PTP frame The software drivers via the PLB configuration bus can then read and decode the contents of the received PTP frames The PTP packet buffer is implemented in dual port block RAM Port A of the block RAM is connected to the PLB configuration bus all addresses in the buffer can be read writes are not allowed Port B of the block RAM is connected to the Rx Splitter module which routes all received PTP frames into the Rx PTP Packet Buffer The Rx PTP Packet Buffer is divided into sixteen identical buffer sections as illustrated Each section contains 256 bytes which are formatted as follows e The PTP frame data itself is stored from address 0 onwards the entire MAC frame from the Destination Address onwards will be written with the exception of the FCS field which will have been removed by the TEMAC The amount of addresses used will be dependent on the particular PTP frame size which is different for each PTP frame type Each PTP buffer provides a maximum of 252 bytes more than that required for the largest PTP f
52. 2010 XILINX Conventions Acronym Spelled Out PHY physical side interface PHYAD Physical Address PLB Processor Local Bus PTP Precise Timing Protocol REGAD Register Address RTC Real Time Clock RO Read Only R W Read Write Rx Receive SFD Start of Frame Delimiter SRP Stream Reservation Protocol TEMAC Tri Mode Ethernet MAC TCP IP Transmission Control Protocol Internet Protocol TOE TCP IP Offload Engine Tx Transmitter UCF User Constraints File us microseconds VHDL VHSIC Hardware Description Language VHSIC an acronym for Very High Speed Integrated Circuits VLAN Virtual LAN Local Area Network WO Write Only XCO Xilinx CORE Generator core source file XPS Xilinx Platform Studio part of the EDK software XPS LL TEMAC XPS LocalLink Tri Mode Ethernet MAC Ethernet AVB Endpoint User Guide UG492 July 23 2010 www xilinx com 21 Preface About This Guide 22 www xilinx com XILINX Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 1 Introduction This chapter introduces the core and provides related information including recommended design experience additional resources technical support and how to submit feedback to Xilinx The Ethernet AVB Endpoint core is a fully verified solution that supports Verilog HDL and VHDL In addition the example design in this guide is prov
53. 492 July 23 2010 XILINX Rx Legacy Traffic I F Errored Legacy Frame Reception l rx_clk_enable a DA Jl SA VLAN legacy rx data valid A legacy rx frame good legacy rx frame bad M Figure 7 2 Errored Frame Reception across the Legacy Traffic Interface 4 As illustrated in Figure 7 2 reception of any frame in which the legacy_rx_frame_bad is asserted in place of legacy_rx_frame_good indicates that this frame must be discarded by the Legacy client it was either received with errors or was not intended for the legacy traffic interface Legacy MAC Header Filters Overview of Operation MAC Header Filters are provided on the receiver legacy traffic path as illustrated in Figure 5 1 These have a greater flexibility than the standard address filter provided in the Tri Mode Ethernet MAC which must be disabled The MAC Header Filters include the ability to filter across any of the initial 16 bytes of an Ethernet frame including the ability to filter only on the Destination Address Length Type Field VLAN tag if present or any bit wise match combination of the preceding Fight individual MAC Header Filters are provided numbered from 0 through to 7 each of which is separately configured Ethernet AVB Endpoint User Guide www xilinx com 67 UG492 July 23 2010 Chapter 7 Ethernet AVB Endpoint Reception g XILINX 68 rx_clk_enable legacy_rx_data 7 0 a DA SA l L T DATA l legac
54. 5 5 all signals are synchronous to the Tri Mode Ethernet MAC receiver clock xx c1k which must always be qualified by the corresponding clock enable xx c1lk en see Table 5 1 This interface is intentionally identical to the legacy receiver interface there is a one to one correspondence between signal names when the legacy prefix is exchanged for the av prefix Error Free AV Traffic Reception dA i IX clk enable DA as SA l L T a DATA l av rx data valid av_rx_frame_good J av_rx_frame_bad Figure 7 7 Normal Frame Reception across the AV Traffic Interface Figure 7 7 illustrates the timing of a normal inbound frame transfer The AV client must be prepared to accept data at any time there is no buffering within the core to allow for latency in the receive client After frame reception begins data is transferred on consecutive clock enabled cycles to the AV receive client until the frame is complete The core asserts the av_rx_frame_good to indicate that the frame was intended for the AV traffic client and was successfully received without error Ethernet AVB Endpoint User Guide www xilinx com 73 UG492 July 23 2010 Chapter 7 Ethernet AVB Endpoint Reception g XILINX Errored AV Traffic Reception y y rx_clk_enable l DA Jl SA VLAN av_rx_valid av rx frame good av
55. AC or to the LogiCORE IP Embedded Ethernet Wrappers available in certain Virtex devices Each of the functional blocks illustrated will be introduced in the following sections of this chapter However observe from the figure that e The Host I F management interface of the Tri Mode Ethernet MAC is connected directly to the Ethernet AVB Endpoint LogiCORE IP This enables the MAC to be fully configured via the PLB Interface of the Ethernet AVB Endpoint core e The core provides two independent full duplex interfaces for customer logic the AV Traffic Interface and the Legacy Traffic Interface e The Legacy Traffic Interface contains MAC Header Filters these are provided to replace the Address Filter functionality of the LogiCORE IP Tri Mode Ethernet MACs which must be disabled Ethernet AVB Endpoint Rx Client Rx PHY 4 Precise Timing Protocol PTP AV Tx Arbiter Traffic AV Traffic I F Tri Mode Ethernet 1X a MAC Rx 4 4 Tx Client Tx PHY L Ich software drivers Tx Time Stamp Real Time Counter Rx Time Stamp Tx PTP Packet Buffer Embedded Micro PLB I F Processor Rx PTP Packet Buffer Host I F Legacy Traffic Legacy Traffic I F s Rx Splitter Figure 5 1 Ethernet AVB Endpoint Core Block Diagram for Connection to LogiCORE IP Tri Mode Ethernet MAC Tx Rx MAC Header
56. AVB Endpoint assumes that any per stream traffic management has been done prior to AV traffic being input on the AV traffic port To comply with the transmission selection rules for P802 1Qav it is assumed that if multiple streams are input to the Ethernet AVB Endpoint via the AV traffic port that the credit based shaper algorithm has been used per stream as the transmission selection mechanism prior to the AV traffic being input on the AV traffic port If multiple AV streams are input to the Ethernet AVB Endpoint via the AV traffic port it is assumed that the IdleSlope SendSlope control registers See Tx Arbiter Send Slope Control Register and Tx Arbiter Idle Slope Control Register are programmed correctly to be the sum of the IdleSlope SendSlope values for all the streams that are input on the AV traffic port The credit based shaper algorithm used on the AV traffic port will enforce a hiLimit loLimit on the credits to ensure that this interface is not misused Listener Assumptions The Ethernet AVB Endpoint provides a mechanism for identifying received AV traffic for either one or two SR classes see Rx Filtering Control Register however it does not provide any buffering for AV traffic Ethernet frames Buffering is expected to be done outside the Ethernet AVB Endpoint after it has separated out the AV traffic Ethernet frames as the buffering requirements are expected to be application specific Ethernet AVB Endpoint User Guide ww
57. COCLIENTRXD 7 0 EMACOCLIENTRXSTATSVLD rx data valid e EMACOCLIENTRXDVLD EMACOCLIENTRXSTATSBYTEVLD rx frame good EMACOCLIENTRXGOODFRAME rx frame bad EMACOCLIENTRXBADFRAME host opcode 1 0 e HOSTOPCODET 1 0 host addr 9 0 e HOSTADDR 9 0 host wr data 31 0 HOSTWRDATA 31 0 host req e HOSTREQ host miim sel e HOSTMIIMSEL host miim rdy e HOSTMIIMRDY host rd data mac 31 0 4 HOSTRDDATA 31 0 hos rd data stats 31 0 host stats Isw rdy HOSTCLK host stats msw rdy HOSTEMAC1SEL host clk e GND Ethernet Statistics Block level Wrapper from Ethernet Statistics Example Design host_clk e g i host opcode 1 0 txclientclkin host addr 9 0 clienttxstats clienttxstatsvld host req clienttxstatsbytevalid host miim sel host miim rdy rxclientclkin host rd data 31 0 clientrxstats 6 0 amp host stats Isw rdy clientrxstatsvid amp host stats msw rdy clientrxstatsbytevalid amp clientrxdvld we host clk Figure 12 4 Connection to the Virtex 5 FPGA Embedded Tri Mode Ethernet MAC and Ethernet Statistic 118 Core www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Using the Xilinx LogiCORE I
58. E E D um 3 i D 3 2 28 8 o A o EPOD m 8 og 8 I eo o Sampling i uncertainty l Timing Case 1 Timing Case 2 l Figure A 4 Overall Time Stamp Accuracy In Figure A 4 two time stamps of the RTC are sampled The figure shows that the accuracy is variable For example e The request for the 1st time stamp is made at 60 ns Because the time to the next RTC reference clock is 20 ns this will not violate the setup time for the 1st synchronization flip flop in Figure A 2 Therefore on the next RTC reference clock the sample will be taken as 40 ns resulting in an error of 20 ns which is entirely due to the RTC Real Time Instantaneous Error e The request for the 2nd time stamp is made at 239 ns This is very close to the rising edge of the 1st synchronization flip flop in Figure A 2 so the situation is unpredictable Ethernet AVB Endpoint User Guide www xilinx com 171 UG492 July 23 2010 Appendix A RTC Time Stamp Accuracy XILINX Ifthe flip flop samples the new value then Timing Case 1 results The RTC is sampled as 200 resulting in an error of 39 ns which is entirely due to the RTC Real Time Instantaneous Error Ifthe flip flop samples the old value then Timing Case 2 results The RTC is sampled 1 RTC reference clock period later as 240 resulting in an error of only 1 ns Hopefully these examples have illustr
59. Erb epo Ra e OE S ata lee Kee 165 Appendix A RTC Time Stamp Accuracy Time Stamp ACCUEIMCY osos Red rcov eau erepta dq add dedita 167 RTC Real Time Instantaneous Error 0 000 cece eee tenes 167 RTC Sampling Prror 2 ced sched ceed et IP IH RI Le y Re E bees ees 169 Accuracy Resulting from the Combined Errors sesesee 171 Ethernet AVB Endpoint User Guide www xilinx com UG492 July 23 2010 XILINX www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 Schedule of Figures Chapter 1 Introduction Chapter 2 Licensing the Core Chapter 3 Overview of Ethernet Audio Video Bridging Figure 3 1 Example AVB Home Network 0006 6 Figure 3 2 Example Ethernet AVB Endpoint System 0000008 Chapter 4 Generating the Core Fieure4 1 GUD Page 1 eedem cas e ER MER Whe Raa a ahead Figure 4 2 GUI Page 2 5 e cec eoe E eee Usb e e o eee e ea Chapter 5 Core Architecture Figure 5 1 Ethernet AVB Endpoint Core Block Diagram for Connection to LogiCORE IP Tri Mode Ethernet MAC ssssssssseee eee Figure 5 2 Ethernet AVB Endpoint Core Block Diagram for Connection to the XPS Tri Mode Ethernet MAC xps ll temac in the EDK 00 Chapter 6 Ethernet AVB Endpoint Transmission Figure 6 1 Normal Frame Transmission across the Legacy Traffic Interface Figure 6 2 Legacy Frame Transmission with Underrun sssses F
60. F rocessor Tx PHY eooo Rx PTP Packet Buffer Realtime Counter Rx Time Stamp a e Rx PHY La Legacy Traffic Legacy Traffic I F ix Spier Tx CCE P Rx a a Avb2TemacRxData Temac2AvbTxData PLB Figure 5 2 Ethernet AVB Endpoint Core Block Diagram for Connection to the XPS Tri Mode Ethernet MAC xps Il temac in the EDK Ethernet AVB Endpoint User Guide www xilinx com 41 UG492 July 23 2010 Chapter 5 Core Architecture g XILINX Functional Block Description 42 The following functional blocks described in the following sections are illustrated in Figure 5 1 and Figure 5 2 PLB Interface The core provides a PLB version 4 6 interface as its configuration port to provide easy integration with the Xilinx Embedded Development Kit and access to an embedded processor MicroBlaze or PowerPC which is required to run the Software Drivers All the configuration and status register address space of the Ethernet AVB Endpoint core can be accessed through the PLB Additionally when the core is generated in Standard CORE Generator Format the PLB logic provides a logic shim which is connected to the Host I F of the supported Xilinx Tri Mode MAC core this enables all configuration and status registers of the MAC to also be available via the PLB See Chapter 10 Configuration and Status for more information AV Traffic Interface The AV traffic interface provides a dedicate
61. FS rtc cpu sample TIMESPEC ts rtc cpu sample FROM cpu bus TO rtc cpu sample 16 ns DATAPATHONLY 108 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Required Constraints INST top rtc_inst rtc_configuration_inst reg_nanosec_offset TNM FFS rtc regs sample NST top rtc inst rtc configuration inst reg sec offset TNM FFS rtc regs sample NST top rtc inst rtc configuration inst reg epoch offset TNM FS rtc regs sample NST top rtc inst rtc configuration inst reg rtc increment TNM FS rtc regs sample INST top rtc inst rtc configuration inst reg offset 8k TNM FFS rtc regs sample TIMESPEC ts rtc regs sample FROM cpu bus TO rtc regs sample 24 ns DATAPATHONLY H I E alt F INST top rtc inst rtc configuration inst rd data result TNM FFS rtc rd data INST top rtc inst rtc configuration inst cpu rd data TNM FFS rtc cpu rd data TIMESPEC ts rtc rd data FROM rtc rd data TO rtc cpu rd data 16 ns DATAPATHONLY INST top rtc inst rtc configuration inst pulselidivi128sec toggle TNM FFS pulseldivi128sec toggle INST top rtc inst rtc configuration inst resync set toggle data sync TNM FFS resync set toggle TIMESPEC ts pulseidivi128sec toggle FROM pulsel1divi128sec toggle TO resync set toggle 8 ns DATAPATHONLY clock domain cro
62. I F will allow the Tx Arbiter to share the bandwidth allocation efficiently between the AV and Legacy sources even in the situations where the AV traffic requires less than 75 of the overall bandwidth However for the cases that require less than 75 of the overall bandwidth careful configuration can result in a smoother less bursty transmission of the AV traffic which should prevent frame bunching across the AVB network Credit Based Traffic Shaping Algorithm To enforce the bandwidth policing of the AV Traffic a credit based shaper algorithm has been implemented in the Ethernet AVB Endpoint core Figure 6 4 illustrates the basic operation of the algorithm and indicates how the Tx Arbiter decides which Ethernet frame to transmit Ethernet AVB Endpoint User Guide www xilinx com 61 UG492 July 23 2010 Chapter 6 Ethernet AVB Endpoint Transmission XILINX increasing credit idleSlope sendSlope hiLimit H credits withdrawn vhs pna when no frames when no trames are waiting are waiting increasing time loLimit CETT TT TT TT conflicting legacy traffic present so queued AV frame is not number of AV transmitted until conflicting legacy frame has been transmitted queued frames transmitting AN frame TRUE FALSE transmitting Legacy frame TRUE FALSE Figure 6 4 Credit based Shaper Operation Figure 6 4 illustrates the
63. LogiCORE p Ethernet AVB Endpoint v2 4 User Guide XILINX XILINX Xilinx is providing this product documentation hereinafter Information to you AS IS with no warranty of any kind express or implied Xilinx makes no representation that the Information or any particular implementation thereof is free from any claims of infringement You are responsible for obtaining any rights you may require for any implementation based on the Information All specifications are subject to change without notice XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE Except as stated herein none of the Information may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx 2008 2010 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries The PowerPC name and logo are registered trademarks of IBM Corp and used under license All other
64. MAC Address Space When the core is generated in EDK pcore Format for import into EDK and connection to the xps ll temac the address space defined in this section is not included and the address space will return 0s for a read and all writes will be ignored When the core is generated in Standard CORE Generator Format the address space of the Ethernet MAC is incorporated into the address space of the Ethernet AVB Endpoint core as illustrated in Figure 10 3 The Ethernet MAC Address space is then split into two sections e MAC Configuration and Statistics e MAC MDIO Registers MAC Configuration and Statistics Table 10 17 defines the statistic registers and configuration registers of the Tri Mode Ethernet MAC core These are listed with their assigned addresses See the Tri Mode Ethernet MAC User Guide UG138 and the Ethernet Statistics User Guide UG170 for additional descriptions of these registers Table 10 17 Tri Mode Ethernet MAC and Ethernet Statistics Configuration Registers Address PLB base address 0x4000 to PLB base address 0x41 FF Description A maximum of 64 configurable Ethernet MAC statistics registers can be accessed through the PLB interface let the statistics registers be numbered by STATISTIC_NUMBER from 0 to 63 Each statistic returns a 64 bit counter value Accordingly Address of STATISTIC_NUMBER PLB base address 0x4000 STATISTIC_NUMBER 8 PLB base address
65. ORT PORT E db db Hb db db db dto dt db PORT PORT END Ethernet AVB Endpoint User Guide UG492 July 23 2010 PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Connected Interrupts to a xps intc core av tx data net gnd av tx valid net gnd av tx done net gnd av tx ack av_rx_data av_rx_valid av rx frame good av rx frame bad rtc_nanosec_field rtc_sec_field Clk8k rtc nanosec field 1722 interrupt ptp tx interrupt ptp timer AvbPtpInt interrupt ptp rx AvbRxInt www xilinx com 129 Chapter 12 System Integration g XILINX 130 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 13 Software Drivers Clock Master Software drivers delivered with the Ethernet AVB Endpoint core provide the following functions which utilize the dedicated hardware within the core for the Precise Timing Protocol PTP IEEE P802 1AS specification e Best Clock Master Algorithm BMCA determines whether the core should operate in master clock or slave clock mode e PTP Clock Master functions e PTP Clock Slave functions that accurately synchronize the local Real Time Clock RTC to match that of the network clock master The following definitions provide only a simplistic concept of PTP protocol operation For detailed information about the PTP protocol see the IEEE P802 1AS specification This chapter only describes the basic operation
66. P Tri Mode Ethernet MACs Figure 12 4 illustrates the connection of the Ethernet AVB Endpoint core to the EMAC when using the Ethernet Statistics core This shares much in common with Figure 12 2 however note the following additional points e Allofthe MAC Management Interface output signals of the Ethernet AVB Endpoint core connect directly to the signals of both the EMAC and Ethernet Statistics cores e The Ethernet AVB Endpoint core provides two separate MAC Management Interface inputs for management reads This allows for logic less connections between all three cores as illustrated To achieve this connect host_rd_data_mac 31 0 of the Ethernet AVB Endpoint core to the HOSTRDDATA 31 0 port of the EMAC connect host rd data stats 31 0 of the Ethernet AVB Endpoint core to the host rd data 31 0 port of the Ethernet Statistics core Virtex 6 FPGA Embedded Tri Mode Ethernet MAC The Ethernet AVB Endpoint core will also connect directly to the Virtex 6 FPGA Embedded Tri Mode Ethernet MAC EMAC Use all of the preceding steps described for the Virtex 5 FPGA EMAC the only difference being that Virtex 6 FPGA EMAC does not come in pairs each EMAC is an individual element Connection of the PLB to the EDK for LogiCORE IP Ethernet MACs Figure 12 5 illustrates the connection of the core to an embedded processor subsystem MicroBlaze processor is illustrated As shown e The PLB can be shared across all periphera
67. Scripts Implementation Scripts The implementation script is either a shell script or batch file that processes the example design through the Xilinx tool flow and is one of the following locations Linux lt project_dir gt lt component_name gt implement implement sh Windows lt project_dir gt lt component_name gt implement implement bat The implement script performs the following steps 1 ND S ROS HDL example design files are synthesized using XST Ngdbuild is run to consolidate the core netlist and the example design netlist into the NGD file containing the entire design Design is mapped to the target technology Design is placed and routed on the target device Static timing analysis is performed on the routed design using trce A bitstream is generated Netgen runs on the routed design to generate a VHDL or Verilog netlist as appropriate for the Design Entry project setting and timing information in the form of SDF files The Xilinx tool flow generates several output and report files that are saved in the following directory which is created by the implement script project dir component name implement results Simulation Scripts Functional Simulation The test script is a ModelSim IES or VCS macro that automates the simulation of the test bench and is in the following location project dir component name simulation functional The test script performs the following tasks
68. Synchronized RTC Nanoseconds Field 79 Time Stamping Logic iis i cess hie buws be ECERRECCRERSCEREE I RE REL RR 79 Time Stamp Sampling Position of MAC Frames 00000 e eee 80 IEEE1722 Real Time Clock Format ssss sene 81 Chapter 9 Precise Timing Protocol Packet Buffers Tx PTP Packet Buffer s eese RR Ie 83 Rx PTP Packet Buffer usse RR e 85 Chapter 10 Configuration and Status Processor Local Bus Interface 0 ccc ccc cena 87 Single Read Transaction i e ebbe rrt reet pie pbi e wade ends 87 Single Write Transaction een 89 PLB Address Map and Register Definitions 000005 90 Ethernet AVB Endpoint Address Space ununun nenna nrnna rnrn rnnr 92 Tri Mode Ethernet MAC Address Space 2 66 00 cece nee 100 Chapter 11 Constraining the Core Required Constraints von s aee dae Rr pea de ud vo ud ie AUD Rea pep e qn 103 Device Package and Speedgrade Selection 000 00 0 c eee eee 103 I O Location Constraints sees rs 103 Placement Constraints ener EP ep CN Ve ded enc Aes 103 Timing Constraints oss casa ek e ase gales cule meee ERRARE e ene eda 103 Chapter 12 System Integration Using the Xilinx LogiCORE IP Tri Mode Ethernet MACs 111 LogiCORE IP Tri Mode Ethernet MAC Soft Core 0 000 00008 112 LogiCORE IP Embedded Tri Mode Ethernet MACs
69. This is achieved in part by receiving the PTP Sync and Follow Up frames transmitted across the network by the clock master and containing the sampled RTC value of the master The PTP mechanism also tracks the total routing delay across the network between the clock master and itself The software drivers use this data in conjunction with recent historical data to calculate the error between its local RTC counter and that of the RTC clock master The software then periodically calculates an RTC correction value and an updated increment rate and these values are written to appropriate RTC configuration registers Because the drivers are provided as C code text files they can be easily modified and designers can edit the files to provide their own secret source or even to update the software drivers for P802 1AS specification changes Software System Integration The software drivers for the Ethernet AVB Endpoint core need to be run on an embedded processor In addition they require instantiation into the overall software project and then initialization An example software project file that performs the required steps is included with the core in the following location component name MyProcessorIPLib drivers ethernet avb endpoint v2 04 a examples xavb example c This software example has been tested in a real system For this reason use this file for reference along with the following descriptions e Driver Instantiation
70. Traffic Endpoint s l Core I l J Statistic Legacy Gathering Traffic AV T raffic Interrupts Figure 15 3 Simulator Wave Window Contents www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 16 Detailed Example Design EDK format This chapter provides detailed information about the core when generated in the Standard Embedded Development Kit EDK format including a description of files and the directory structure generated This option is selected from page 1 of the customization GUI Please refer instead to Chapter 15 Detailed Example Design Standard Format when requiring the Standard CORE Generator software format C3 project directory Top level project directory name is user defined C9 project directory component name gt Core release notes file Lj component name doc Product documentation O MyProcessorIPLib pcores eth avb endpoint v2 04 a core netlist and HDL for the pcore C9 peores eth avb endpoint v2 04 a data Data files for automatic integration into Xilinx Platform Studio pcores eth avb endpoint v2 04 a hdl vhdl VHDL wrapper file for the core netlist to enable integration into Platform Studio pcores eth avb endpoint v2 04 a netlist The Ethernet AVB Endpoint core netlist O MyProcessorIPLib drivers avb v2 04 a Software Device Drivers for the pcore drivers avb v2 04 a data Data files fo
71. Uncertain a value of 1 indicates that there is a possible discontinuity in GrandMaster time A value of 0 indicates that Timestamps are no longer uncertain Qparam CallBackRef contains a callback reference from the driver in Kk kkk kk k e e e k ke k k kc se cse she he e e e k k k ERK ERE k k ke e ke k kc kc kc RR k k k k REE kc kc kkk kkk kk kk kk static void GMDiscontinuityHandler void CallBackRef unsigned int TimestampsUncertain xil_printf r nGMDiscontinuityHandler Timestamps are now s r n TimestampsUncertain uncertain certain Starting and Stopping the AVB Drivers The default state after driver initialization is for the AVB drivers to be inactive After the Ethernet link has been established the drivers can be started using the following function call This will begin operation of the IEEE802 1 AS PTP protocol XAvb_Start InstancePtr Before starting the drivers ensure that the Ethernet PHY has successfully auto negotiated a full duplex link at either 100 Mbps or 1 Gbps Ethernet speeds Early implementations may also require the completion of an LLDP Link Layer Discovery Protocol function LLDP has been used in early AVB implementations to negotiate support of AVB between peer devices for interoperability AVB standards are still considering the use of LLDP LLDP is not currently included in our software drivers or example file The AVB drivers can be stopped at
72. User Guide Blue underlined text Hyperlink to a website URL Go to www xilinx com for the latest speed files Ethernet AVB Endpoint User Guide UG492 July 23 2010 www xilinx com 19 Preface About This Guide 20 List of Abbreviations XILINX The following table describes acronyms used in this manual Acronym Spelled Out AV Audio Video AVB Audio Video Bridging BMCA Best Master Clock Algorithm CRC Cyclic Redundancy Check DA Destination Address DMA Direct Memory Access DSP Digital Signal Processor EDK Embedded Development Kit EMAC Ethernet MAC FCS Frame Check Sequence FIFO First In First Out FPGA Field Programmable Gate Array Gbps Gigabits per second GMII Gigabit Media Independent Interface GUI Graphical User Interface HDL Hardware Description Language TES Incisive Unified Simulator I F Interface IO Input Output IP Intellectual Property ISE Integrated Software Environment KHz Kilo Hertz LLDP Link Layer Discovery Protocol MAC Media Access Controller Mbps Megabits per second MDIO Management Data Input Output MHS Microprocessor Hardware Description a proprietary file format using the mhs file extension for a XPS project MHz Mega Hertz ms milliseconds MPMC Multi Port Memory Controller ns nanoseconds www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23
73. a INST top rx splitter inst vlan priority a sample TNM FFS vlan priority a sample TIMESPEC ts vlan priority a sample FROM vlan priority a TO vlan priority a sample TIG INST top avb configuration inst vlan priority b int TNM FFS vlan priority b INST top rx splitter inst vlan priority b sample TNM FFS vlan priority b sample TIMESPEC ts vlan priority b sample FROM vlan priority b TO vlan priority b sample TIG clock domain crossing constraints for Tx Configuration INST top avb configuration inst tx cpu reclock wr toggle TNM FFS tx wr toggle INST top avb configuration inst tx cpu reclock resync write toggle data s ync TNMM FFS resync tx write toggle TIMESPEC ts tx wr toggle FROM tx wr toggle TO resync tx write toggle TIG INST top avb configuration inst tx cpu reclock rd toggle TNM FFS tx rd toggle INST top avb configuration inst tx cpu reclock resync read toggle data sy nc TNM FFS resync tx read toggle TIMESPEC ts tx rd toggle FROM tx rd toggle TO resync tx read toggle TIG INST top avb configuration inst tx cpu reclock new rd toggle TNM FFS cpu tx rd toggle INST top avb configuration inst tx cpu reclock resync new rd toggle data sync TNM FFS resync cpu tx rd toggle TIMESPEC ts cpu tx rd toggle FROM cpu tx rd toggle TO resync cpu tx rd toggle TIG INST
74. a smooth counter whereas the synchronized RTC may suffer from occasional step changes whenever a new offset adjustment is periodically applied by the software drivers These step changes avoided by using the controlled frequency RTC could otherwise lead to errors in the various PTP calculations which are performed by the software drivers Note The Software Drivers can themselves obtain when required the local synchronized RTC value simply by summing the captured time stamp with the current nanoseconds offset value of the RTC Offset Control Registers effectively performing the step 2 calculation of Figure 8 2 in software Ethernet AVB Endpoint User Guide www xilinx com 79 UG492 July 23 2010 Chapter 8 Real Time Clock and Time Stamping g XILINX Time Stamp Sampling Position of MAC Frames A time stamp value should be sampled at the beginning of the first symbol following the Start of Frame Delimiter SFD of the Ethernet MAC frame as seen on the PHY This is illustrated in Figure 8 3 Xilinx Tx IEEE defined Tx sample position sample position known fixed PHY specific Tx latency Tx latency AV traffic Ethernet Tri Mode AVB Ethernet Endpoint MAC LogiCORE LogiCORE Ethernet PHY PHY Media legacy traffic ae known fixed PHY specific Rx latency Rx latency Xilinx Rx IEEE defined Rx sample position sample position Figure 8 3 Time Stamping Position Figure 8 3 also illustrate
75. able VLAN priority values the VLAN priorities are defaulted to values of 3 and 2 e Legacy Traffic Routed to the Legacy Traffic I F of the core All packet types which are not identified as PTP or AV Traffic will be considered legacy traffic See Chapter 7 for further information MAC Header Filters The MAC Header Filters provided on the receiver legacy traffic path when the core is generated in Standard CORE Generator Format These filters provide a greater flexibility than the standard address filter provided in the LogiCORE IP Tri Mode Ethernet MACs which must be disabled The MAC Header Filters include the ability to filter across any of the initial 16 bytes of an Ethernet frame including the ability to filter only on the Destination Address Length Type Field VLAN tag if present or any bit wise match combination of the preceding Eight individual MAC Header Filters are provided each of which is separately configured See Chapter 7 Ethernet AVB Endpoint Reception for further information When the core is generated in EDK pcore Format the Legacy MAC Header Filters are not included since the xps Il temac can optionally contain its own Address Filter logic Ethernet AVB Endpoint User Guide www xilinx com 43 UG492 July 23 2010 44 Chapter 5 Core Architecture g XILINX Precise Timing Protocol Blocks The various hardware Precise Timing Protocol PTP blocks within the core provide the dedicated hardware to
76. ad ND i BD EGIN PARAM PARAM PARAM eth_avb_endpoint ETER INSTANCE eth_avb_endpoint_0 ER HW_VER 2 02 a ER C MEMO BASEADDR pun pun 0xcc000000 128 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Using the Xilinx XPS LocalLink Tri Mode Ethernet MAC PARAMETER C MEMO HIGHADDR OxccOOffff BUS INTERFACE SPLB mb plb PORT reset sys periph reset Connect as per Figure 12 9 PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT tx clk TemacOAvbTxClk tx clk en Temac0OAvbTxClkEn rx clk TemacOAvbRxClk rx clk en TemacOAvbRxClkEn tx data Avb2MacOTxData tx data valid Avb2MacOTxDataValid tx underrun Avb2MacOTxUnderrun tx ack Mac0O2AvbTxAck rx data Mac0O02AvbRxData rx data valid Mac02AvbRxDataValid rx frame good Mac0O2AvbRxFrameGood rx frame bad Mac02AvbRxFrameBad legacy tx data Temac02AvbTxData legacy tx data valid Temac02AvbTxDataValid legacy tx underrun Temac02AvbTxUnderrun legacy tx ack Avb2TemacOTxAck legacy rx data Avb2TemacORxData legacy rx data valid Avb2TemacORxDataValid legacy rx frame good Avb2TemacORxFrameGood legacy rx frame bad Avb2TemacORxFrameBad rtc clk TemacOAvbTxClk Unused in this example connect to custom pcores PORT P
77. al 8 ns up or down by a very fine degree of accuracy The step 1 addition illustrated in Figure 8 2 of current counter value plus increment will occur on every clock cycle of the RTC reference clock The result from this addition forms the new value of the controlled frequency RTC nanoseconds field This controlled frequency RTC will initialize to zero following reset and will continue to increment smoothly on every RTC reference clock cycle by the current value contained in the RTC Increment Value Control Register Figure 8 2 illustrates that 26 bits have been reserved for the Increment Value the upper 6 bits of which overlap into the nanoseconds field For this reason the largest per cycle increment 1ns 2 6 64 ns The lowest clock period which is expected to increment this counter is 40 ns corresponding to the 25 MHz MAC clock used at 100 Mbps speeds So this should satisfy all allowable clock periods Step 2 Synchronized RTC The value contained in the RTC Offset Control Registers written by the microprocessor is then applied to the free running controlled frequency RTC counter This is used by the microprocessor to e Initialize the power up value of the Synchronized RTC e Apply step corrections to the Synchronized RTC when a slave based on the timing PTP packets received from the Grand Master Clock RTC The step 2 addition illustrated in Figure 8 2 of controlled frequency RTC value plus
78. alue register for the seconds field of the Real Time Clock When read this returns the latest value of the counter This register and the registers defined in Table 10 10 and in Table 10 11 are linked When the nanoseconds value register is read see Table 10 10 the entire RTC is sampled Table 10 12 Current RTC Seconds Field Value bits 47 32 PLB_base_address 0x281C Bit no Default Access Description 15 0 0 RO Sampled Value of the synchronized RTC Seconds field bits 47 32 32 16 0 RO Unused RTC Interrupt Clear Register Table 10 13 describes the control register defined for the interrupt_ptp_timer signal the periodic interrupt signal which is raised by the Real Time Clock Table 10 13 RTC Interrupt Clear Register PLB base address 0x2820 Bit no Default Access Description 0 0 WO Write ANY value to bit 0 of this register to clear the interrupt ptp timer Interrupt signal This bit always returns 0 on read 31 1 0 RO Unused www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX PLB Address Map and Register Definitions Phase Adjustment Register Table 10 14 describes the Phase Adjustment Register which has units of nanoseconds This value is used to correct the 8k clock generation circuit when a new nanosecond offset value is written to the RTC It additionally could be used to apply a phase offset to the clk8k signal The val
79. and some key components of the software drivers The software driver code is documented such that the comments can be viewed by Doxygen and detailed descriptions of all aspects of the software are available throughout the code This should allow customers to fully understand the operation of the provided software drivers and to edit the drivers for their own secret source applications Fundamentally the slave Real Time Clock synchronization functions complete a software controlled phase locked loop Therefore many implementations are possible The provided software drivers implement a very simple software PLL implementation However this has been shown in hardware to provide excellent Real Time Clock synchronization results The document section drivers avb v2 04 a src in Chapter 16 lists all of the C files delivered with the Ethernet AVB Endpoint core and provides a description of how the software is divided up between these files If the core is acting as clock master the software drivers delivered with the core periodically sample the current value of the RTC and transmit this value to every device on the network using the P802 1 defined Sync and Follow Up PTP packets Ethernet AVB Endpoint User Guide www xilinx com 131 UG492 July 23 2010 Chapter 13 Software Drivers XILINX Clock Slave If the core is acting as a clock slave the local RTC is closely matched to the value and frequency of the network clock master
80. and the Xilinx ISE Software Manuals and Help You can download these documents from www xilinx com support software manuals htm Functional Simulation This section provides instructions for running a functional simulation of the Ethernet AVB Endpoint core using either VHDL or Verilog The functional simulation model is provided when the core generated implementing the core before simulation is not required To run a VHDL or Verilog functional simulation of the example design 1 Openacommand prompt or shell then set the current directory to project dir component name simulation functional 2 Launch the simulation script ModelSim vsim do simulate mti do IES simulate ncsim sh VCS simulate vcs sh Verilog only The simulation script compiles the functional simulation model the example design files the demonstration test bench and adds relevant signals to a wave window It then runs the simulation to completion After completion you can inspect the simulation transcript and waveform to observe the operation of the core Ethernet AVB Endpoint User Guide www xilinx com 141 UG492 July 23 2010 Chapter 14 Quick Start Example Design g XILINX Timing Simulation What s Next 142 This section contains instructions for running a timing simulation of the Ethernet AVB Endpoint core using either VHDL or Verilog A timing simulation model is generated when run through the Xilinx tools using the imple
81. associated configuration register It is recommended that these interrupts are routed to the input of an EDK Interrupt Controller module as part of the embedded processor subsystem Table 5 10 Interrupt Signals Signal Direction Description interrupt_ptp_timer Output This interrupt is asserted every 1 128 second as measured by the RTC This acts as a timer for the PTP software algorithms interrupt_ptp_tx Output This is asserted following the transmission of any PTP packet from the Tx PTP Packet Buffers interrupt_ptp_rx Output This is asserted following the reception of any PTP packet into the Rx PTP Packet Buffers Ethernet AVB Endpoint User Guide www xilinx com 55 UG492 July 23 2010 Chapter 5 Core Architecture 56 PTP Signals XILINX Table 5 11 defines the signals which are output from the core by the Precise Timing Protocol Blocks These signals are provided for reference only and may be used by an application For example the 1722 Packet Managers as illustrated in Figure 3 2 require the following e clk8k this marks the class measurement interval to be used for traffic shaping for SR class A AV traffic e xrtc_nanosec_fieldand rtc sec field used in the 1722 presentation time stamp logic Table 5 11 PTP Signals Signal Direction Description rtc nanosec field 31 0 Output This is the synchronized nanoseconds field from the RTC
82. ata must pass through P802 1Qav is also responsible for enforcing the 75 maximum bandwidth restriction across each link of the network that can be reserved for the AV traffic Only a subset of the P802 1Qav requirements for an Endpoint is implemented in the Ethernet AVB Endpoint core with the following assumptions for talkers and listeners Talker Assumptions AV traffic Ethernet frames that are input to the Ethernet AVB Endpoint use the VLAN priority values that the Bridges in the network recognize as being associated with SR classes exclusively for transmitting stream data Legacy traffic Ethernet frames that are input to the Ethernet AVB Endpoint do not use the VLAN priority values that the Bridges in the network recognize as being associated with SR classes exclusively for transmitting stream data The credit shaping algorithm operates on the AV traffic port so in order to comply with the transmission selection rules for P802 1Qav all Ethernet frames input on the AV traffic port are assumed to be of the same SR Class However the Ethernet AVB Endpoint does not enforce this rule and it is acceptable to send a mix of SR Class A and SR Class B Ethernet frames on the AV traffic port In this case the Ethernet AVB Endpoint will not prioritize SR Class A Ethernet frames over SR Class B Ethernet frames instead it will apply the credit based shaper algorithm to all of the Ethernet frames that are input on the AV traffic port The Ethernet
83. ated that the timing uncertainty in the asynchronous sampling circuit has not resulted in any additional error The maximum inaccuracy per time stamp sample is still equal to the period of the RTC reference clock in this example 40 ns By using a high frequency RTC reference clock a high degree of accuracy can be obtained For example when using a 125 MHz clock source for the RTC the maximum time stamp error will be 8 ns or less 172 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010
84. ating the Core Ethernet AVE GUI Page diss iyi i0pie idee Re Eee be dece doe par e e dues 35 Component Name enisi pertsepti dade A eee e s es e oae dee P dn 36 Core Delivery Format esse eter Sos pane tile baee ed edd ode aate acm nds 36 Ethernet AVB GUI Page 2 cooisecse eoe e PORE OO o CR 37 Number of PLB Masters 0000 c ccc RR RR e es 37 PLB Base Address cete ARR eR REED EGRE REC wattle d E aen 37 Parameter Values in the XCO File uussessssee ee 38 Output Generation cuu eden ther ig beo oe ice Ra ede dee detail pd e ease 38 Chapter 5 Core Architecture Standard CORE Generator Format Luuuuseseeee ee 40 EDK pcore Format ssssesssssssssssssseee eee eee 41 Functional Block Description 00 00 42 PLB Interface iscsi eor LR PRERENDER DE aA Ek ea a 42 AV Traffic Interface vc ven ives vedas SEEN 3r RYXGu Ee he TERR ades 42 Legacy Traffic Interface 0 en 42 TX Arbiter cosctetur eb e EPI eR e rto abe tee er oup a 43 Rx Splitters cicscctess seve cote ee eis pere ace ka d p ag ee ad cendo ndis 43 MAC Header Filters 0 0 0 cc eee e 43 Precise Timing Protocol Blocks 06 c cece e 44 Software Drivers sasasi tieira iene inaa eG e ed RR a E E ES ah EARN e vache 46 Tri Mode Ethernet MACs lsseeeeeeee eee res 46 Core Interfaces oen Baia EERHEREY E Leb Banks TEE ERE PY eh TEES 47 Clocks and Reset iiie ei y eR Ry CE REEEY aah a esa EG X aoe RE edis 47 Legac
85. ble for the microprocessor to read This sampling of the RTC is performed in hardware for accuracy See Chapter 9 Precise Timing Protocol Packet Buffers for further information www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX RTC Functional Block Description A significant component of the PTP network wide timing synchronization mechanism is the Real Time Counter RTC which provides the common time of the network Every device on the network will maintain its own local version The RTC is effectively a large counter which consists of a 32 bit nanosecond field the unit of this field is 1 nanosecond and this field will count the duration of exactly one second then reset back to zero and a 48 bit second field the unit of this field is one second this field will increment when the nanosecond field saturates at 1 second The seconds field will only wrap around when its count fully saturates The entire RTC is therefore designed never to wrap around in our lifetime The RTC counter is implemented as part of the core in hardware Conceptually this counter is not related to the frequency of the clock used to increment it A configuration register within the core provides a configurable increment rate for this counter this increment register simply takes the value of the clock period which is being used to increment the RTC However the resolution of this increment register is very fine in units of 1
86. can be used to set the initial value following power up When in PTP clock slave mode the Software Drivers use this register to implement the periodic step corrections www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Ethernet AVB Endpoint User Guide UG492 July 23 2010 PLB Address Map and Register Definitions This register and the registers defined in Table 10 6 and in Table 10 8 are linked These three offset values will be loaded into the RTC counter logic simultaneously following a write to the nanosecond offset register defined in Table 10 6 Table 10 7 Seconds Field Offset bits 31 0 PLB base address 0x2808 Description Bit no Default Access 31 0 0 R W 32 bit offset value for the RTC seconds field bits 31 0 Used by the microprocessor to initialize the RTC then afterwards to perform the regular RTC corrections when in slave mode Table 10 8 describes the offset control register for the upper 16 bits of seconds field of the Real Time Clock used to force step changes into the counter When in PTP clock master mode this can be used to set the initial value following power up When in PTP clock slave mode the Software Drivers use this register to implement the periodic step corrections This register and the registers defined in Table 10 6 and in Table 10 7 are linked These three offset values will be loaded into the RTC counter logic simultaneously follow
87. ce eee eee eee 141 Functional Simulation 0 0 00 0000000 ccc ccc eee es 141 Timing Simulation 2k eR ieii nei Ree e er PR eR Re E e RA a bl 142 What s Next sius vv bs Lee ithe Ree EC hee ee RE eie e pta 142 Chapter 15 Detailed Example Design Standard Format Directory and File Contents cigs ke de treu pa oak Oe erra AP ak eb 144 project directory cs s erties he ce be E d UA bach EU dap re dae adele sand ord 144 project directory component name ssssseesseees 145 component name doc 6 eee 145 component name gt example design 06666 c cece eens 145 component name gt implement 0 cee ees 146 implemernt results 45 4144 die cer bten Re p e De EEUU Iber eisai tess 147 component name simulation 0 eee 147 simulation functional csse e 147 simulation timing srr cerarirers iii eidi e 148 lt component_name gt drivers v2_04_a 10 eens 149 drivers yb V2 04a data eed ee ace Ege Seca eee Pad ecd wes 149 drivers avb v2 04 a examples issssssessseeeee ee eee eens 149 drivers avb v2 04 a src ileeeeeeeee RR e re 150 Implementation Scripts 12s ses used bere e d aor UO OR o de e 151 Simulation SCENES cuu i3 aded vade RATE aede e d E siet ea d ieu 151 Functional Simulation 0 0 00 0000 ence nent n 151 Timing Simulation iced ke ker RR EE BRE eee ede Ee eRe oS ERA 152 Example Desigu iso eRHEHGE VERE VEHURESER REX VER A EN EROR ER OR d
88. ck source obtained from the transmit clock source of the Ethernet MAC at 1 Gbps speed this frequency will significantly exceed the minimum performance of the P802 1AS specification When acting as a clock slave the rate adjustment of the RTC can be matched to that of the network clock master to an exceptional level of accuracy by slightly increasing or decreasing the value within the RTC Increment Value Control Register The software drivers provided with this core will periodically calculate the increment rate error between itself and the master and update the RTC increment value accordingly The core also contains configuration registers RTC Offset Control Registers which allow a large step change to be made to the RTC This can be used to initialize the RTC after power up It is also used to make periodic corrections as required by the software drivers when operating as a clock slave however if the increment rates are closely matched these periodic step corrections will be small www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Real Time Clock RTC Implementation Increment of Nanoseconds Field Figure 8 2 illustrates the implementation used to create the RTC nanoseconds field This is performed by the use of an implementation specific 20 bit sub nanoseconds field as illustrated The nanoseconds and sub nanoseconds fields can be considered to be concatenated together All RTC log
89. cket Buffer Address Space The Address space of the Rx PTP Packet Buffer is 4k bytes from PLB_base_address to PLB base address OxOFFF This represents the size of a single Virtex 5 FPGA block RAM pair 4k bytes Every byte of this Block RAM can be read from the PLB See Rx PTP Packet Buffer for operation Tx PTP Packet Buffer Address Space The Address space of the Tx PTP Packet Buffer is continuous from PLB base address 0x1000 to PLB base address 0x17FF representing the size of a single Virtex 5 FPGA Block 18k RAM 2k bytes Every byte of this Block RAM is read write accessible via the PLB See Tx PTP Packet Buffer for operation Ethernet Audio Video End Point Configuration Registers Tx PTP Packet Control Register Table 10 1 defines the associated control register of the Tx PTP Packet Buffer used by the Software Drivers to request the transmission of the PTP frames Table 10 1 Tx PTP Packet Buffer Control Register PLB base address 0x2000 Bit no Default Access Description 7 0 0 WO tx_send_frame bits The Tx PTP Packet Buffer is split into 8 regions of 256 bytes Each of these can contain a separate PTP frame There is 1 tx_send_frame bit for each of the 8 regions Each bit when written to 1 will cause a request to be made to the Tx Arbiter When access is granted the frame contained within the respected region will be transmitted If read will always return 0 15 8
90. core in isolation to be tested and to demonstrate some of the functionality of the core and does not create a realistic implementation In a real system the loopback module should be replaced with an Ethernet MAC the PLB module should be replaced with an embedded processor and the frame stimulus and checker modules should be replaced with the desired AV and Legacy client functionality www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Example Design Top Level Example Design HDL The following files describe the top level example design for the Ethernet AVB Endpoint core VHDL project dir component name example design component name example design vhd Verilog project dir component name example design component name example design v The example design HDL top level contains the following e An instance of the Ethernet AVB Endpoint core e Two instances of an Ethernet Frame Stimulus block configured differently and connected as follows One instance is connected to the AV transmitter interface configured to produce VLAN Ethernet frames with a priority of 3 A second instance is connected to the Legacy transmitter interface configured to produce standard Ethernet frames without a VLAN field e An instance of a Loopback Module instantiated in place of where an Ethernet MAC should exist enables the example design to be standalone All AV and Legacy frames transmit
91. cs ModelSim v 6 5c and Synopsys VCS and VCS MX 2009 12 Demonstration Test Bench Example Design Top Level Clock and Tx frame AV traffic Reset stimulus eneration g loopback Tx frame module stimulus Ethernet legacy AVB traffic Endpoint LogiCORE Statistic Gathering legacy Rx frame traffic checker Rx frame checker AV traffic Interrupts PLB module Figure 14 1 Ethernet AVB Endpoint Example Design and Test Bench 138 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Generating the Core Generating the Core This section provides detailed instructions for generating the Ethernet AVB Endpoint example design core To generate the core 1 Start the CORE Generator tool For general help with starting and using CORE Generator software on your system see the documentation supplied with the ISE software including the CORE Generator Guide These documents can be downloaded from www xilinx com support software_manuals htm Create a new project For project options select the following A Virtex 6 Virtex 5 Spartan 3 Spartan 3E Spartan 3A 3A DSP or Spartan 6 device to generate the default Ethernet AVB Endpoint core Inthe Design Entry section select VHDL or Verilog then select Other for Vendor Locate the Ethernet AVB Endpoint core in the taxonomy tree listed under one of the following Automotive amp Industrial Automotive Commun
92. d full duplex port for the high priority AV data See Chapter 6 Ethernet AVB Endpoint Transmission and Chapter 7 Ethernet AVB Endpoint Reception for further information Legacy Traffic Interface The legacy traffic interface provides a dedicated full duplex port for the legacy data as described in Chapter 6 Ethernet AVB Endpoint Transmission and Chapter 7 Ethernet AVB Endpoint Reception When the core is generated in Standard CORE Generator Format then Legacy MAC Header Filters are provided on the receiver path These filters have a greater flexibility than the address filter provided in the LogiCORE Tri Mode Ethernet MACs which must be disabled When the core is generated in EDK pcore Format the legacy traffic interface is designed to connect directly to the ports of the xps ll temac core please see Figure 5 2 and Chapter 12 System Integration Additionally the Legacy MAC Header Filters are not included since the xps ll temac can optionally contain its own Address Filter logic www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Functional Block Description Tx Arbiter Data for transmission over an AVB network can be obtained from three types of sources 1 AV Traffic For transmission from the AV Traffic I F of the core 2 Precise Timing Protocol PTP Packets Initiated by the software drivers using the dedicated hardware Tx PTP Packet Buffers
93. d on this port rx data valid Input Control signal for the xx data 7 0 port rx frame good Input Asserted at the end of frame reception to indicate that the frame should be processed by the Ethernet AVB Endpoint core rx frame bad Input Asserted at the end of frame reception to indicate that the frame should be discarded by the MAC client MAC Management Interface This interface is only present when the core is generated in Standard CORE Generator Format designed for connection to LogiCORE IP Tri Mode Ethernet MAC devices When present these signals connect directly to the identically named LogiCORE IP Tri Mode Ethernet MAC signals except where stated in Table 5 8 and are synchronous to host clk When present all MAC configuration and MDIO register space is address mapped into the PLB of the Ethernet AVB Endpoint core A logic shim automatically drives this interface to access the MAC when the appropriate PLB address space is accessed Table 5 8 Tri Mode Ethernet MAC Host Interface Configuration Status Signal Direction Description host opcode 1 0 Output Defines the MAC operation configuration or MDIO read or write host addr 9 0 Output Address of the MAC register to access host wr data 31 0 Output Data to be written to the MAC register host rd data mac 31 0 Input Data read from the MAC register connect to the host rd data 31 0 signal of the MAC host rd data stats 31 0 Input Da
94. des note the following e The Ethernet transmitter client clock domain must always be connected to the tx_clk input of the Ethernet AVB Endpoint core Additionally the transmitter clock enable as used with the EMAC must always be connected to the tx_clk_en input of the Ethernet AVB Endpoint core e The Ethernet receiver client clock domain must always be connected to the rx_clk input of the Ethernet AVB Endpoint core Additionally the receiver clock enable as used with the EMAC must always be connected to the rx_clk_en input of the Ethernet AVB Endpoint core e The host_clk input of the Ethernet AVB Endpoint and the HOSTCLK input the EMAC must always share the same clock source Connections Including Ethernet Statistics Ethernet AVB Endpoint Core Netlist Block level Wrapper from Virtex 5 Embedded Tri mode Ethernet MAC Wrapper CLIENTEMACOPAUSEREQ CLIENTEMACOPAUSEVAL 15 0 GND tx_clk P DCCLK emt tx clk en TX CLIENT CLK ENABLE 0 EMACOCLIENTTXSTATS tx data 7 0 p gt CLIENTEMACOTXDJ 7 0 EMACOCLIENTTXSTATSVLD tx data valid we CLIENTEMACOTXDVLD EMACOCLIENTTXSTATSBYTEVLD tx_underrun CLIENTEMACOTXUNDERRUN tx_ack EMACOCLIENTTXACK NC 4 EMACOCLIENTTXCOLLISION NC 4 EMACOCLIENTTXRETRANSMIT CLIENTEMACOIFGDELAY GND rx_clk GMI RX CLO 4 4 7 7 TX Clk en RX CLIENT CLK ENABLE 0 EMACOCLIENTRXSTATS 6 0 rx data 7 0 EMA
95. dth proportion of 75 for the AV traffic See the IEEE P802 1 Qav specification and Tx Arbiter for more information Table 10 5 Tx Arbiter Idle Slope Control Register PLB base address 0x2010 Bit no Default Access Description 31 20 0 RO Unused 19 0 6144 R W The value of idleSlope RTC Offset Control Registers Table 10 6 describes the offset control register for the nanoseconds field of the Real Time Clock used to force step changes into the counter When in PTP clock master mode this can be used to set the initial value following power up When in PTP clock slave mode the Software Drivers will use this register to implement the periodic step corrections This register and the registers defined in Table 10 7 and in Table 10 8 are linked These three offset values will be loaded into the RTC counter logic simultaneously following a write to this nanosecond offset register Table 10 6 RTC Nanoseconds Field Offset PLB base address 0x2800 Bit no Default Access Description 29 0 0 R W 30 bit offset value for the RTC nanoseconds field Used by the microprocessor to initialize the RTC then afterwards to perform the regular RTC corrections when in slave mode 31 30 0 RO Unused Table 10 7 describes the offset control register for the lower 32 bits of seconds field of the Real Time Clock used to force step changes into the counter When in PTP clock master mode this
96. e FROM rx clear toggle TO rx Clear toggle resync TIG INST top ptp packet buffer inst rx ptp packet buffer inst rx mac logic in st address TNM FFS rx buf addr INST top ptp packet buffer inst rx ptp packet buffer inst rx mac logic in St rx packet TNM FFS rx buf addr sample TIMESPEC ts rx buf addr FROM rx buf addr TO rx buf addr sample 64 ns DATAPATHONLY clock domain crossing constraints for Tx PTP Packet Buffer logic INST top ptp packet buffer inst tx ptp packet buffer inst tx mac logic in st tx valid reg2 TNM FFS tx valid reg2 INST top ptp packet buffer inst tx ptp packet buffer inst tx mac logic in st resync frame tx toggle data sync TNM FFS tx valid reg2 resync TIMESPEC ts tx valid reg2 FROM tx valid reg2 TO tx valid reg2 resync TIG clock domain crossing constraints for Rx Configuration INST top avb configuration inst promiscuous mode int TNM FFS promiscuous mode INST top legacy inst address filter inst resync promiscuous mode data sy nc TNM FFS promiscuous mode resync TIMESPEC ts promiscuous mode FROM promiscuous mode TO promiscuous mode resync TIG 106 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Required Constraints INST top avb_configuration_inst vlan_priority_a_int TNM FFS vlan priority
97. e Interrupt Service Routine Connections e Core Initialization e Ethernet AVB Endpoint Setup e Starting and Stopping the AVB Drivers Note Unless you are already familiar with the Xilinx Embedded Development Kit EDK see the EDK documentation to follow the steps described Driver Instantiation Software driver instantiation for the Ethernet AVB Endpoint core follows the standard EDK model used for all EDK IP cores and as recommended for all user defined pcores see the EDK documentation Initialization of the driver requires that an instance of the driver is instantiated assigned a base address within the PLB address range and configured using the standardized cores CfgInitialize function 132 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Software System Integration For example in the user software the AVB drivers can be instanced as follows Allocate an instance of the XAvb device driver static XAvb Avb int Status XAvb_Config AvbConfigPtr Initialize AVB Driver AvbConfigPtr XAvb_LookupConfig AVB_DEVICE_ID Status XAvb_CfgInitialize amp Avb AvbConfigPtr AvbConfigPtr gt BaseAddress In the previous example the AVB_DEVICE_ID is defined in the xparameters h file automatically generated by the EDK tools as a result of the software driver instance and the hardware instance of the Ethernet AVB Endpoint core in the Microproce
98. e Microprocessor Hardware Specification mhs file this pcore was assigned a base address matching that of the Ethernet AVB Endpoint PLB Base Address in the generated netlist produced by the CORE Generator software Then the AVB software drivers were assigned to the plb port instance in the Microprocessor Software Specification mss file Ethernet AVB Endpoint User Guide www xilinx com 123 UG492 July 23 2010 Chapter 12 System Integration XILINX Using the Xilinx XPS LocalLink Tri Mode Ethernet MAC 124 The Ethernet AVB Endpoint core should be generated in the EDK pcore Format when connecting to the XPS LocalLink Tri Mode Ethernet MAC core xps Il temac Introduction The xps ll temac is delivered with data path FIFO s of configurable depth optional TCP IP Offload Engine TOE logic and various other optional features all of which can be connected to Scatter Gather Direct Memory Access DMA Engines Together with software drivers this provides an entire ethernet networking stack such as TCP IP All of this functionality is available in the EDK The xps ll temac uses a CORE Generator LogiCORE IP Ethernet MAs as a subcomponents It is able to use either the soft core TEMAC product or an Embedded Tri Mode Ethernet MAC available in certain Virtex devices The xps ll temac functionality remains identical for either MAC implementation The integration of the Ethernet AVB Endpoint core with the xps ll temac
99. e Ethernet MAC Ethernet AVB Endpoint MAC Transmitter I F MAC Receiver I F Legacy Transmitter I F Legacy Recevier I F pcore tx clk tx clk enable tx data 7 0 tx data valid tx underrun tx ack rx clk rx clk enable rx data 7 0 rx data valid rx frame good rx frame bad legacy tx data 7 0 legacy tx data valid legacy tx underrun legacy tx ack legacy rx data 7 0 legacy rx data valid legacy rx frame good legacy rx frame bad XPS LocalLink Tri Mode Ethernet MAC xps Il temac TemacOAvbTxClk TemacOAvbTxClkEn Avb2MacOTxData 7 0 Avb2MacOTxDataValid Avb2MacOTxUnderrun MacO2AVbTxAck TemacOAvbRxClk TemacOAvbRxCIkEn MacO2AvbRxData 7 0 MacO2AvbRxDataValid MacO2AvbRxFrameGood MacO2AvbRxFrameBad TemacO2AvbTxData 7 0 TemacO2AvbTxDataValid TemacO2AvbTxUnderrun Avb2TemacOTxAck Avb2TemacORxData 7 0 Avb2TemacORxDataValid Avb2TemacORxFrameGood Avb2TemacORxFrameBad Figure 12 9 Connection to the XPS LocalLink Tri Mode Ethernet MAC MHS File Syntax The following code extracts are taken from an XPS project which connected the Ethernet AVB Endpoint core to an instance of the xps_ll_temac This design targeted the Virtex 5 family and implemented the xps ll temac using an Embedded Tri Mode Ethernet MAC macro This MHS syntax is included for illustration guideline purposes It is recommended that the XPS GUI is used to
100. e corresponding clock enable tx_clk_en see Clocks and Resets Table 5 4 AV Traffic Signals Transmitter Path Signal Direction Description av_tx_data 7 0 Input Frame data to be transmitted is supplied on this port av_tx_valid Input A data valid control signal for data on the av tx data 7 0 port av tx done Input Asserted by the AV client to indicate that further frames following the current frame are are not held in a queue av tx ack Output Handshaking signal asserted when the current data on av tx data 7 0 has been accepted Ethernet AVB Endpoint User Guide www xilinx com 49 UG492 July 23 2010 Chapter 5 Core Architecture XILINX 50 AV Traffic Receiver Path Signals Table 5 5 defines the core client side AV traffic receiver signals used by the core to transfer data to the AV client All signals are synchronous to the MAC receiver clock rx_clk which must be qualified by the corresponding clock enable rx c1k en see Clocks and Resets Table 5 5 AV Traffic Signals Receiver Path Signal Direction Description av rx data 7 0 Output AV frame data received is supplied on this port av rx valid Output Control signal for the av rx data 7 0 port av rx frame good Output Asserted at the end of frame reception to indicate that the frame should be processed by the MAC client av rx frame bad Output Asserted at the end of frame reception to indicate that the f
101. e for the AVB timing synchronization protocol Chapter 9 Precise Timing Protocol Packet Buffers describes two components that are partially responsible for the transmission and reception of Ethernet Precise Timing Protocol frames these frames contain the AVB timing synchronization data Chapter 10 Configuration and Status defines general guidelines for configuring and monitoring the Ethernet AVB Endpoint core including an introduction to the PLB configuration bus and a description of the core management registers Chapter 11 Constraining the Core defines the Ethernet AVB core constraints Chapter 12 System Integration describes the integration of the Ethernet AVB Endpoint core into a system including connection of the core to the Xilinx Tri Mode Ethernet MAC and Ethernet Statistic cores Ethernet AVB Endpoint User Guide www xilinx com 17 UG492 July 23 2010 Preface About This Guide XILINX e Chapter 13 Software Drivers describes the function of the software drivers delivered with the core e Chapter 14 Quick Start Example Design Chapter 3 Quick Start Example Design provides instructions to quickly generate the core and run the example design through implementation and simulation using the default settings e Chapter 15 Detailed Example Design Standard Format provides detailed information about the core when generated in the standard CORE Generator format including a descript
102. e inst timestamp TNM FFS tx timestamp TIMESPEC ts tx timestamp route FROM tx timestamp TO FFS 8 ns DATAPATHONLY clock domain crossing constraints for Rx timestamp logic INST top rx rtc sample inst sample toggle req TNM FFS rx sample req INST top rx rtc sample inst resync sample toggle reqg data sync TNM FFS rx sample req resync TIMESPEC ts rx sample req FROM rx sample req TO rx Sample req resync 6 5 ns DATAPATHONLY Ethernet AVB Endpoint User Guide www xilinx com 105 UG492 July 23 2010 Chapter 11 Constraining the Core XILINX INST top rx_rtc_sample_inst sample_taken_toggle TNM FFS rx sample taken INST top rx rtc sample inst resync sample taken toggle data sync TNM FFS rx sample taken resync TIMESPEC ts rx sample taken FROM rx sample taken TO rx sample taken resync TIG INST top rx rtc sample inst timestamp TNM FFS rx timestamp TIMESPEC ts rx timestamp route FROM rx timestamp TO FFS 8 ns DATAPATHONLY clock domain crossing constraints for Rx PTP Packet Buffer logic INST top ptp packet buffer inst rx ptp packet buffer inst rx mac logic in St rx clear toggle TNM FFS rx clear toggle INST top ptp packet buffer inst rx ptp packet buffer inst rx mac logic in st resync clear toggle data sync TNM FFS rx clear toggle resync TIMESPEC ts rx clear toggl
103. e is requested the Tx PTP Buffer logic will give a priority order to the lowest PTP Buffer Number that has been requested The Tx PTP Packet Control Register also contains a frame waiting field This can be read by the software drivers to determine which of the previously requested PTP frames have been sent and which are still queued Following transmission completion of each requested PTP frame a dedicated interrupt signal interrupt ptp tx will be generated by the core On the assertion of the interrupt the captured timestamp will already be available in the upper four bytes of the buffer and the tx packet field of the Tx PTP Packet Control Register will indicate the most recently transmitted Buffer Number The Software Drivers provided with the core using the PLB and dedicated interrupts will use this interface to periodically as defined by the IEEE802 1AS protocol update specific fields within the PTP packets and request transmission of these packets Tx PTP Packet Buffers Buffer Number Buffer Base Address 7 Single Tx PTP Packet Buffer 0x1700 Signaling Frame 0X1600 timestamp 31 24 timestamp 23 16 Address Buffer Base Address OxFF OxFE timestamp 15 8 OxFD timestamp 7 0 OxFC 5 Announce Frame 0x1500 unused x 0x08 frame_length_field 4 Pdelay_Resp_Follow_Up N A Frame N Ox1400 Pdelay Resp Frame PTP Frame Data 0x1300
104. e simulator vcs session tcl VCS macro file that opens a wave window and adds signals of interest to it It is called by the simulate vcs sh script file Back to Top simulation timing The timing directory contains timing simulation scripts provided with the core Table 15 9 Timing Directory Name Description project dir2 component name simulation timing simulate mti do ModelSim macro file that compiles Verilog or VHDL sources and runs the timing simulation to completion wave mti do ModelSim macro file that opens a wave window and adds signals of interest to it It is called by the simulate mti do macro file simulate ncsim sh IES script file that compiles the Verilog or VHDL sources and runs the timing simulation to completion wave ncsim sv IES macro file that opens a wave window and adds signals of interest to it It is called by the simulate ncsim sh script file simulate vcs sh VCS script file that compiles the Verilog sources and runs the timing simulation to completion vcs commands key File sourced by VCS at the start of simulation it configures the simulator vcs session tcl VCS macro file that opens a wave window and adds signals of interest to it It is called by the simulate vcs sh script file Back to Top 148 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Directory and File Contents component name dri
105. e the AVB standard does not include support for half duplex or flow control operation the relevant half duplex flow control signals of the TEMAC can be left unused inputs can be tied to logic 0 outputs can be left unconnected Ethernet AVB Endpoint User Guide UG492 July 23 2010 www xilinx com 113 Chapter 12 System Integration XILINX Because the TEMAC core can often be used in different clocking modes note the following e The Ethernet transmitter client clock domain must always be connected to the tx_cl1k input of the Ethernet AVB Endpoint core Additionally the transmitter clock enable as used with the TEMAC must always be connected to the tx_clk_en input of the Ethernet AVB Endpoint core e The Ethernet receiver client clock domain must always be connected to the rx_clk input of the Ethernet AVB Endpoint core Additionally the receiver clock enable as used with the TEMAC must always be connected to the rx_clk_en input of the Ethernet AVB Endpoint core e The host_clk inputs of the Ethernet AVB Endpoint and of the TEMAC must always share the same clock source If desired this can also be the clock source used for the PLB interface 114 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Connections Including Ethernet Statistics Ethernet AVB Endpoint Core Netlist GND pause_req pause_val 15 0 TEMAC BLock level Wrapper from TEMAC Example Desi
106. e the MAC transmitter and receiver latencies are held in defines in a header file The software drivers also contain placeholder defines for users to input the PHY specific latency values for the PHYs used in the system IEEE1722 Real Time Clock Format The IEEE1722 specification defines the aobtp timestamp field This is derived by sampling the IEEE802 1 AS Real Time Clock and converting the low order time to nanoseconds From version 2 1 onwards this conversion is now performed in the Ethernet AVB Endpoint core and an alternative RTC in the 1722 format is output on the rtc nanosec field 1722 31 0 port This port contains a 32 bit word representing nanosecond values Unlike the IEEE802 1 AS nanosecond field which resets back to zero when it reaches 1 second the IEEE1722 nanosecond field counts fully to OxFFFFFFFF before wrapping around The field therefore wraps around approximately every 4 seconds If the system is using the IEEE1722 functionality this port can be sampled to create the aobtp timestamp field Otherwise this port can be ignored Ethernet AVB Endpoint User Guide www xilinx com 81 UG492 July 23 2010 Chapter 8 Real Time Clock and Time Stamping 82 www xilinx com XILINX Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 9 Precise Timing Protocol Packet Buffers This chapter considers two of the logical components which are partly responsible for the AVB timing synchron
107. e the various interfaces to the core in simulation Functional simulation is supported by a dynamically generated HDL structural model Full System Hardware Evaluation The Full System Hardware Evaluation license key is available at no cost and lets you fully integrate the core into an FPGA design place and route the design evaluate timing and perform back annotated gate level simulation of the core using the demonstration test bench provided with the core In addition the license key lets you generate a bitstream from the placed and routed design which can then be downloaded to a supported device and tested in hardware The core can be tested in the target device for a limited time before timing out ceasing to function at which time it can be reactivated by reconfiguring the device Ethernet AVB Endpoint User Guide www xilinx com 27 UG492 July 23 2010 Chapter 2 Licensing the Core XILINX Full The Full license key is available when you purchase a license for the core and provides full access to all core functionality both in simulation and in hardware including e Functional simulation support e Back annotated gate level simulation support e Full implementation support including place and route and bitstream generation e Full functionality in the programmed device with no time outs Obtaining Your License Key This section contains information about obtaining a simulation full system hardware and full license keys
108. ecific requirements Additional Core Resources For detailed information and updates about the Ethernet AVB Endpoint core see the following documents available from the product page e Ethernet AVB Endpoint Data Sheet e Ethernet AVB Endpoint User Guide From the document directory after generating the core e Ethernet AVB Endpoint Release Notes Technical Support Feedback For technical support see www support xilinx com Questions are routed to a team of engineers with expertise using the Ethernet AVB Endpoint core Xilinx provides technical support for use of this product as described in this guide Xilinx cannot guarantee timing functionality or support of this product for designs that do not follow these guidelines Xilinx welcomes comments and suggestions about the Ethernet AVB Endpoint core and the documentation supplied with the core Ethernet AVB Endpoint Core 24 For comments or suggestions about the Ethernet AVB Endpoint core submit a WebCase from www xilinx com support clearexpress websupport htm Be sure to include the following information e Product name e Core version number e Explanation of your comments www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Document Feedback For comments or suggestions about this document submit a WebCase from www xilinx com support clearexpress websupport htm Be sure to include the following information Doc
109. egrated into Platform Studio Table 16 7 Driver Data Directory Name Description project dir component name MyProcessorlPLib drivers avb v2 04 data avb v2 1 0 mdd Current MDD file used including the version of the tools interface avb v2 1 O tcl Used to provide design rule checks within Xilinx Platform Studio Back to Top drivers avb v2 04 a examples The driver examples directory contains an application example using the low level driver files Table 16 8 Driver Example Directory Name Description project dir component name MyProcessorlPLib drivers avb v2 04 examples xavb example c Contains a very basic example design of using the AVB driver Back to Top Ethernet AVB Endpoint User Guide www xilinx com 163 UG492 July 23 2010 Chapter 16 Detailed Example Design EDK format g XILINX drivers avb v2 04 a src The driver source src directory contains the low level driver source C files Table 16 9 Driver Source Directory Name Description project dir component name MyProcessorlPLib drivers avb v2 04 src Makefile Makefile to compile the drivers used by Platform Studio xavb h Main header file for the XAvb driver The file provides the constants type definitions and function templates which are required to initialize and run the IEEE802 1A5 Precise Timing Protocol PTP This defines the level 1 device driver for the Eth
110. endPri 0 1 Input Unused PLB pending read bus request indicator PLB reqPri 0 1 Input Unused PLB request priority Sl_addrAck Output Slave address acknowledge S SSize 0 1 Output Slave data bus size SI wait Output Slave wait indicator SI rearbitrate Output Slaverearbitrate bus indicator Not used tied to logic 0 SI wrDack Output Slave write data acknowledge SI wrComp Output Slave write transfer complete indicator SI WrBTerm Output Slave terminate write burst transfer SI rdBus 0 31 Output Slave read data bus SI rdWdAddr 0 3 Output Slave read word address SI rdDAck Output Slave read data acknowledge SI rdComp Output Slave read transfer complete indicator SI rdBTerm Output Slave terminate read burst transfer SI MBusy 0 NUM MASTERS 1 Output Slave busy indicator SI MWrErr 0 NUM MASTERS 1 Output Unused tied to logic 0 Slave write error indicator SI MRdErr 0 NUM MASTERS 1 Output Unused tied to logic 0 Slave read error indicator SI MIRO 0 NUM MASTERS 1 Output Unused tied to logic 0 Slave interrupt indicator www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Core Interfaces Interrupt Signals Table 5 10 defines the interrupt signals asserted by the core All interrupts are active high and are automatically asserted All interrupts required by the Software Drivers delivered with the core are cleared by software access to an
111. ernet AVB Endpoint core xavb_g c Contains a configuration structure that holds all the configuration values required per single instance of the device driver xavb c Provides the top level function calls for the Ethernet AVB Endpoint level 1 device driver xavb_ptp_packets c Provides the functions which are required for the creation of PTP frames for transmission and for the decode of received PTP frames xavb_ptp_bmca c Provides the functions which are required for the PTP Best Master Clock Algorithm BMCA xavb_rtc_sync c Provides the functions which are required to synchronize the local version of the Real Time Counter RTC when operating as a slave to that of the network clock master xavb_hw h Contains all the constant definitions and the bare minimum of functions function templates which are required for register read write access This defines the low level 0 device driver for the Ethernet AVB Endpoint core xavb_hw c This file partners the xavb_hw h header file and implements the functions for which avb_hw h contained a template Back to Top 164 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Importing the Ethernet AVB Endpoint Core into the Embedded Development Kit EDK Importing the Ethernet AVB Endpoint Core into the Embedded Development Kit EDK You can import a generated Ethernet AVB Endpoint netlist into an EDK
112. ernet MAC GMII TX EN O pin PORT GMII TX ER 0 fpga 0 Hard Ethernet MAC GMII TX ER O0 pin PORT GMII TX CLK 0 fpga 0 Hard Ethernet MAC GMII TX CLK 0 pin PORT GMII RX DV O fpga 0 Hard Ethernet MAC GMII RX DV O0 pin G G G PORT GMII RXD O0 fpga 0 Hard Ethernet MAC GMII RXD O0 pin G G PORT GMII RX ER O fpga 0 Hard Ethernet MAC GMII RX ER O0 pin PORT GMII RX CLK O fpga 0 Hard Ethernet MAC GMII RX CLK 0 pin PORT MDC O0 fpga 0 Hard Ethernet MAC MDC O0 pin PORT MDIO O0 fpga 0 Hard Ethernet MAC MDIO O0 pin Connect as per Figure 12 9 PORT TemacOAvbTxClk TemacOAvbTxClk PORT TemacOAvbTxClkEn TemacOAvbTxClk PORT TemacOAvbRxClk TemacOAvbRxClk PORT TemacOAvbRxClkEn TemacOAvbRxClkEn PORT Avb2MacOTxData Avb2MacOTxData PORT Avb2MacOTxDataValid Avb2MacOTxDataValid PORT Avb2MacOTxUnderrun Avb2Mac0TxUnderrun PORT Mac02AvbTxAck Mac02AvbTXxAck PORT Mac02AvbRxData Mac02AvbRxData PORT Mac0O2AvbRxDataValid Mac02AvbRxDataValid PORT Mac02AvbRxFrameGood Mac02AvbRxFrameGood PORT Mac02AvbRxFrameBad Mac02AvbRxFrameBad PORT Temac02AvbTxData Temac02AvbTxData PORT Temac0O2AvbTxDataValid Temac02AvbTxDataValid PORT Temac02AvbTxUnderrun Temac02AvbTxUnderrun PORT Avb2TemacOTxAck Avb2TemacOTxAck PORT Avb2TemacORxData Avb2TemacORxData PO Avb2TemacORxDataValid Avb2TemacORxDataValid PORT Avb2TemacORxFrameGood Avb2TemacORxFrameGood PO Avb2TemacORxFrameBad Avb2TemacORxFrameB
113. errupt In this simple demonstration nothing further is performed This functionality is related to the normal operation of a PTP clock master in that the logic results in a transmission of PTP Sync Follow Up pair of frames being sent periodically However the functionality is greatly simplified and none of the relevant variable PTP Sync Follow up fields are correctly set Note The real intent for the PLB interface is for connection into the EDK environment software drivers are provided to be run on an embedded processor which performs full 802 1AS Precise Timing Protocol PTP functionality See Chapter 13 Software Drivers for detailed information about the provided software drivers Ethernet AVB Endpoint User Guide www xilinx com 155 UG492 July 23 2010 Chapter 15 Detailed Example Design Standard Format g XILINX Demonstration Test Bench Figure 15 2 illustrates the Ethernet AVB Endpoint demonstration test bench a simple VHDL or Verilog program for exercising the example design and the core Demonstration Test Bench Example Design Top Level Clock Reset stimulus generation Tx frame stimulus Ethernet AVB Endpoint LogiCORE loopback Statistic Gathering Rx frame checker Rx frame checker AV traffic Interrupts PLB module Figure 15 2 Ethernet AVB Endpoint Demonstration Test Bench The following files describe the top level of the demonstration test bench VHDL lt project_dir gt
114. est class measurement interval for an SR class as specified in IEEE802 1Qav This clock could also be useful for external applications for example a 1722 implementation of the AV traffic Time Stamping Logic Whenever a PTP packet used with the Precise Timing Protocol PTP is transmitted or received see Precise Timing Protocol Packet Buffers in Chapter 9 a sample of the current value of the RTC is taken and made available for the software drivers to read The hardware makes no distinction between frames carrying event or general PTP messages as defined in IEEE P802 1AS it will always store a timestamp value for ethernet frames containing the Ethertype specified for PTP messages This time stamping of packets is a key element of the tight timing synchronization across the AVB network wide RTC and these samples must be performed in hardware for accuracy The hardware in this core will therefore sample and capture the local nanoseconds RTC field for every PTP frame transmitted or received These captured time stamps are stored in the Precise Timing Protocol Packet Buffers alongside the relevant PTP frame and are read and used by the PTP software drivers It is important to realize that is it actually the controlled frequency RTC nanoseconds field which is sampled by the time stamping logic rather than the synchronized RTC see Figure 8 2 This is important when operating as a clock slave the controlled frequency RTC always acts as
115. extends the functionality of the xps ll temac to additionally include all of the features of AVB Figure 5 2 provides an overview of this system observe that the AV Traffic Interface remains available for custom logic to source and sink the time sensitive streaming data e g audio video data Also refer to Figure 12 8 for a different perspective of this system xps ll temac configuration To configure the xps ll temac with the required ports to interface with the Ethernet AVB Endpoint ensure that the following option is set e C TEMAC AVB Ensure via xps ll temac software initialization that e Jumbo frames are disabled e VLAN is enabled the MAC is set to operate in promiscuous mode the TEMAC address filter is disabled For further information please refer directly to the xps I temac product specification www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Using the Xilinx XPS LocalLink Tri Mode Ethernet MAC System Overview AVB capable xps_ll_temac BRAM Imb bram if cntlr EDK Tool Domain Microblaze xps uartlite xps intc Ethernet AVB Endpoint LocalLink Re r2 MDIO PLB PLB AV traffic VF MAC Avb2TemacRx gt Ethernet client j Temac2AVBTx PHY I F VF Legacy I Avb2TemacTx traffic 4 Temac2AVBRx VF Figure 12 8 Connection of the Ethernet AVB Endpoint Core into an Embedded Processor S
116. face About This Guide Guide Contents The LogiCORE IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging AVB Endpoint core including how to customize generate and implement the core in supported Xilinx FPGA families This guide contains the following chapters Preface About this Guide introduces the organization and purpose of this guide and the conventions used in this document Chapter 1 Introduction introduces the core and provides related information including additional core resources technical support and how to submit feedback to Xilinx Chapter 2 Licensing the Core describes the available license options for the core and how to obtain them Chapter 3 Overview of Ethernet Audio Video Bridging provides an overview of Ethernet Audio Video Bridging including relevant specifications and a typical implementation Chapter 4 Generating the Core provides information about generating and customizing the core using the CORE Generator software Chapter 5 Core Architecture describes the major functional blocks of the Ethernet AVB Endpoint core Chapter 6 Ethernet AVB Endpoint Transmission describes data transmission over an AVB network Chapter 7 Ethernet AVB Endpoint Reception describes data reception over an AVB network Chapter 8 Real Time Clock and Time Stamping describes two components that are partially responsibl
117. figurable and flexible MAC Header matching logic as the Single MAC Header Filter Usage Examples demonstrates Ethernet AVB Endpoint User Guide www xilinx com 69 UG492 July 23 2010 Chapter 7 Ethernet AVB Endpoint Reception g XILINX Single MAC Header Filter Usage Examples Full Destination Address DA Match rx_clk rx_clk_enable legacy rx data 7 0 L T DATA legacy rx data valid Match Pattern Register Match Enable Register Don t cares Figure 7 4 Filtering of Frames with a Full DA Match The example illustrated in Figure 7 4 shows a single MAC Header Filter one of the eight provided configured to filter on a Destination Address In order for the frame to obtain a match the initial 48 bits of the received frame must exactly match the first 48 bits of the Match Pattern Register This example provides backwards compatibility with the Address Filters provided in the Tri Mode Ethernet MAC which must be disabled 70 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Rx Legacy Traffic I F Partial Destination Address DA Match y y rx_clk_enable i DA SA VLAN L T DATA legacy_rx_data_valid Match Pattern Register Match Enable Register Match Don t cares Figure 7 5 Filtering of Frames with a Partial DA Match The example illustrated in Figure 7 5 shows a single MAC Header Filter one of the eight provided conf
118. gn Using the Xilinx LogiCORE IP Tri Mode Ethernet MACs tx_clk Kik sc aa a og pees tx_clk_en j Clem an cs tx_data 7 0 tx_data 7 0 tx_statistics_valid tx_data_valid tx_underrun tx_data_valid tx_underrun tx_ack tx_ack NC tx_collision tx_retransmit tx_ifg_delay 7 0 rx_clk t X ck IX Clk en j e mx ck en TX Statistics valid rx data 7 0 e rx data 7 0 IX Statistics vector 27 0 rx data valid rx data valid rx frame good rx frame good rx frame bad rx frame bad host opcode 1 0 host addr 9 0 host wr data 31 0 host req host miim sel e host miim rdy host rd data mac 31 0 host opcode 1 0 host addr 9 0 host wr data 31 0 host req host miim sel host miim rdy host rd data 31 0 ix statistics vector 31 0 host rd data stats 31 0 host stats Isw rdy 3 host stats msw rdy lt host clk host clk 4 e6 Ethernet Statistics Block level Wrapper from Ethernet Statistics Example Design host clk host opcode 1 0 tx clk 4 host addr 9 0 tx clk en itx statistics valid 2 tx statistics vector 31 0 _______________w host req host miim sel host miim rdy TX Ck 4 host rd data 31 0 IX Clk en host
119. h guaranteed low latency e Other data referred to in this document as legacy traffic Does not have the strict requirement of AV traffic data can be started stopped and delayed without serious consequence for example a PC surfing the internet For these reasons an important aspect of the AVB technology is therefore to prioritize the audio video streaming data AV traffic over that of standard data transfer legacy traffic AVB Specifications The IEEE802 1 Audio Video Task Group is currently working on new specifications which combine to define this technology P802 1AS This specification defines how to synchronize a common time base across an entire AVB network utilizing functionality from IEEE1588 version 2 and known as Precise Timing Protocol PTP This common time base is in the form of a Real Time Clock RTC effectively a large counter which consists of a 32 bit nanoseconds field and a 48 bit seconds field A single device on the network is designated as the clock master by automatic resolution using a Best Master Clock Algorithm BMCA All other devices resolve to be slaves Using the P802 1AS PTP all slave devices will regularly update their own RTC to match that of the network clock master This common time base has various applications e It can be used to synchronize media clocks audio clocks or video pixel clocks across the entire network to match audio and video data rates between talkers and listeners e
120. h554433221100 Do not use VLAN fields parameter j EGACY HAS VLAN 1 b0 VLAN fields are not used so the following parameter is n a parameter 15 0 EGACY VLAN DATA 16 h0000 Use a Generic Type field parameter 15 0 EGACY TYPE FIELD 16 h8000 Ethernet AVB Endpoint User Guide www xilinx com 157 UG492 July 23 2010 Chapter 15 Detailed Example Design Standard Format g XILINX 158 Viewing the Simulation Wave Form The Simulation Scripts for the selected simulator automatically selects signals of interest from within the DUT and adds them to the simulator wave window These are organized into grouped interfaces which are identified using section headings in the wave window Figure 15 3 illustrates the grouped interfaces selected for the Functional Simulation The circled numbers represent the order in which they are displayed the wave window section headings are also numbered to match Figure 15 3 Further signals of interest may be added as desired The signals added to the Timing Simulation are a subset of the ones used in the Functional Simulation To summarize the PLB interface is not viewed due to synthesis implementation optimization that occurs on these signals the result of which merges signals and changes names O Demonstration Test Bench Example Design Top Level Clock and AV Traffic Reset Generation Loopback Module Ethernet Legacy AVB
121. he clock and reset signals which are required by the Ethernet AVB Endpoint core Table 5 1 Clocks and Resets Signal Direction Description reset Input Asynchronous reset for the entire core rtc_clk Input Reference clock used to increment the RTC The minimum frequency is 25 MHz Xilinx recommends a 125 MHz clock source tx_clk Input The MAC transmitter clock provided by the Tri Mode Ethernet MAC tx_clk_en Input A clock enable signal this must be used as a qualifier for tx_clk rx_clk Input The MAC receiver clock provided by the Tri Mode Ethernet MAC rx_clk_en Input A clock enable signal this must be used as a qualifier for rx_clk host_clk Input An input clock for the management interface of the connected Tri Mode Ethernet MAC This clock can be independent or could be shared with PLB_clk This signal is only present when the core is generated in Standard CORE Generator Format PLB_clk Input The input clock reference for the PLB bus tx_reset Output Output reset signal for logic on the Legacy Traffic and AV Traffic transmitter paths This reset signal is synchronous to tx c1k the reset is asserted when a transmitter path reset request is made to the Software Reset Register IX reset Output Output reset signal for logic on the Legacy Traffic and AV Traffic receiver paths This reset signal is synchronous to rx c1k the reset is asserted when a receiver path reset request i
122. how to write the Ethernet Source Address into all TX PTP packet buffers Setting up GrandMaster Discontinuity Callback Handler The Ethernet AVB Endpoint software defines a callback routine which is called when the endpoint switches between being a Master and a Slave or vice versa or when it loses PTP lock The application software must define a callback handler for this otherwise an error will be asserted The example software provides an example of this as follows Function Prototype static void GMDiscontinuityHandler void CallBackRef unsigned int TimestampsUncertain Main function in this example main FR XAvb Config AvbConfigPtr Setup the handler that will be called if the PTP drivers identify a possible discontinuity in GrandMaster time XAvb SetGMDiscontinuityHandler amp Avb GMDiscontinuityHandler amp Avb PR a dem f 5k kcsk kc kc kc ke se ke he e e he EREREE coke ke ec e he kc kc ke kc kc kc kckckckck kc kc kckckckckckckckck ckckck ck kc ko kc ko kk Ethernet AVB Endpoint User Guide www xilinx com 135 UG492 July 23 2010 Chapter 13 Software Drivers XILINX This function is the handler which will be called if the PTP drivers identify a possible discontinuity in GrandMaster time This handler provides an example of how to handle this situation but this function is application specific this case it is the instance pointer for the AVB driver param Timestamps
123. iCORE IP Tri Mode Ethernet MAC or the LogiCORE IP Embedded Tri Mode Ethernet MAC wrappers available in selected Virtex families See Chapter 12 System Integration When generated in this format Ethernet AVB GUI Page 2 is available for customization of the PLB Interface Generate as an EDK pcore provided for the Embedded Development Kit This option will deliver the core in the standard pcore format suitable for directly importing into the Xilinx Embedded Development Kit EDK environment When generated in this format the core is designed to interface to the XPS LocalLink Tri Mode Ethernet MAC xps Il temac See Chapter 12 System Integration When generated in this format page 2 of the GUI is not available the PLB Interface will be configured dynamically by the EDK Xilinx Platform Studio XPS software For directory and file definitions for the two available formats see Chapter 15 Detailed Example Design Standard Format and Chapter 16 Detailed Example Design EDK format www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Ethernet AVB GUI Page 2 Ethernet AVB GUI Page 2 Figure 4 2 shows page 2 of the Ethernet AVB Endpoint GUI customization screen This page provides options for configuring the PLB Interface of the core This option is only required when generating in the Standard CORE Generator software format
124. ic within the core is synchronous to the RTC Reference Clock rtc_clk Nano Seconds 32 bits unsigned Sub Nano Seconds 20 bits unsigned ome cd ERE as es ee es es ee J Step 1 fill with zero s rm RTC Increment Value 26 bits written by processor controlled frequency RTC a Step 2 RTC Nano Seconds Offset 30 bits written by processor Synchronised RTC omg Figure 8 2 Increment of Sub nanoseconds and Nanoseconds Field Ethernet AVB Endpoint User Guide www xilinx com 77 UG492 July 23 2010 Chapter 8 Real Time Clock and Time Stamping g XILINX There are two stages to the implementation Step 1 Controlled Frequency RTC The RTC Increment Value illustrated in Figure 8 2 is set directly from the RTC Increment Value Control Register The upper 6 bits of this register align with the lower 6 bits of the RTC nanoseconds field The lower 20 bits of the RTC Increment Value align with the 20 bit sub nanoseconds field It is assumed that the frequency of the RTC reference clock is known by the processor to enable the increment value to be programmed correctly For example if the RTC is being clocked from a 125 MHz clock source a nominal increment value of 8 ns should be programmed by writing the value 0x800000 into the RTC Increment Value Control Register However if the microprocessor determines that this clock is drifting with respect to the grand master clock it can revise this nomin
125. ications amp Networking Ethernet Communications amp Networking Networking Communications amp Networking Telecommunications Double click the core name A message may appear to indicate the limitations of the Simulation Only Evaluation license Click OK the core customization screen appears Ethernet AVB Endpoint User Guide www xilinx com 139 UG492 July 23 2010 Chapter 14 Quick Start Example Design Ethernet AVB Endpoint XILINX 140 AV_TX_DATAI 0 AV_TX_VALID AV_TX_DONE AV TX ACK AV RX DATA 7 0 AV RX VALID AV RX FRAME GOOD AV RX FRAME BAD LEGACY TX DATA 0 LEGACY TX DATA VALID LEGACY TX UNDERRUN LEGACY TX ACK IP Symbol TX CLK TX CLK EN TX DATA 0 TX DATA VALID TX UNDERRUN TX ACK TX RESET RX CLK RX_CLK_EN RX_DATAI 0 RX_DATA_VALID RX_FRAME_GOOD RX_FRAME_BAD RX_RESET gic PE Ethernet AVB Endpoint Component Name ethernet_avb_endpoint_v2_4 Core Delivery Format Standard CORE Generator format The generated core will include the standard Core Generator deliverables HDL example design scripts demonstration testbench Figure 14 2 Ethernet AVB Endpoint Core Customization Screen Generate as an EDK pcore 7 Entera core instance name in the Component Name field 8 Maintain the default options on GUI page 1 so that Standard CORE Generator format is selected 9 Click Generate to deliver the core usi
126. ice from the example network shown in Figure 3 1 as opposed to an intermediate bridge function which is not supported In the implementation the Ethernet AVB Endpoint core is shown connected to a Xilinx Tri Mode Ethernet MAC core which in turn is connected to an AVB capable network All devices attached to this network should be AVB capable to obtain the full Quality of Service advantages for the AV traffic This AVB network can be a professional or consumer network as illustrated in Figure 3 1 32 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Typical Implementation Figure 3 2 illustrates that the Ethernet AVB Endpoint core supports the two main types of data interfaces at the client side 1 The AV traffic interface is intended for the Quality of Service audio video data Illustrated are a number of audio video sources for example a DVD player and a number of audio video sinks for example a TV set The Ethernet AVB Endpoint gives priority to the AV traffic interface over the legacy traffic interface as dictated by IEEE P802 1Qav 75 bandwidth restrictions 2 The legacy traffic interface is maintained for best effort ethernet data Ethernet as we know it today for example the PC surfing the internet in Figure 3 1 Wherever possible priority is given to the AV traffic interface as dictated by IEEE P802 1Qav bandwidth restrictions but a minimum of 25 of the total Ethernet bandwidth is a
127. ics Ethernet AVB Endpoint Core Netlist tx_clk tx_clk_en tx_data 7 0 tx_data_valid tx_underrun tx_ack rx_clk rx_clk_en rx_data 7 0 rx_data_valid rx frame good rx frame bad host opcode 1 0 host addi 9 0 host wr data 31 0 host req host miim sel host miim rdy host rd data mac 31 0 host rd data stats 31 0 host stats Isw rdy host stats msw rdy host clk host clk GND NC NC GND lt a GND TEMAC Block level Wrapper from TEMAC Example Design pause_re pause val 15 0 tx clk tx clk en tx data 7 0 tx data valid tx underrun tx ack tx collision tx retransmit tx ifg delay 7 0 rx_clk rx_clk_en rx_data 7 0 rx_data_valid rx_frame_good rx_frame_bad host opcode 1 0 host addr 9 0 host wr data 31 0 host req host miim sel host miim rdy host rd data 31 0 host clk ix statistics valid tx statistics vector 31 0 rx statistics valid rx statistics vector 27 0 Figure 12 1 Connection to the Tri Mode Ethernet MAC Core without Ethernet Statistics NC NC NC NC Figure 12 1 illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri Mode Ethernet MAC TEMAC core when not using the Ethernet Statistics core Figure 12 1 provides detail for the connections between the two cores which were shown in Figure 5 1 All connections as shown are logic less connections Becaus
128. ided in both Verilog and VHDL formats System Requirements Windows e Windows XP Professional 32 bit 64 bit e Windows Vista Business 32 bit 64 bit Linux e Red Hat Enterprise Linux WS v4 0 32 bit 64 bit e Red Hat Enterprise Desktop v5 0 32 bit 64 bit with Workstation Option e SUSE Linux Enterprise SLE desktop and server v10 1 32 bit 64 bit Software e ISEG software v12 2 About the Core The Ethernet AVB Endpoint core is available through the Xilinx CORE Generator software included in the latest IP Update on the Xilinx IP Center For detailed information about the core see the Ethernet AVB Endpoint product page For information about licensing options see Chapter 2 Licensing the Core Ethernet AVB Endpoint User Guide www xilinx com 23 UG492 July 23 2010 Chapter 1 Introduction XILINX Recommended Design Experience Although the Ethernet AVB Endpoint core is a fully verified solution the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application For best results previous experience building high performance pipelined FPGA designs using Xilinx implementation software and user constraint files UCFs is recommended In addition previous experience using the Embedded Development Kit EDK and developing embedded software applications is recommended Contact your local Xilinx representative for a closer review and estimation for your sp
129. igure 6 3 Normal Frame Transmission across the AV Traffic Interface Figure 6 4 Credit based Shaper Operation esses Chapter 7 Ethernet AVB Endpoint Reception Figure 7 1 Normal Frame Reception across the Legacy Traffic Interface Figure 7 2 Errored Frame Reception across the Legacy Traffic Interface Figure 7 3 Normal Frame Reception Address Filter Match 00 Figure 7 4 Filtering of Frames with a Full DA Match 2 00005 Figure 7 5 Filtering of Frames with a Partial DA Match 045 Figure 7 6 Filtering of VLAN Frames with a Specific Priority Value Figure 7 7 Normal Frame Reception across the AV Traffic Interface Figure 7 8 Errored Frame Reception across the AV Traffic Interface Chapter 8 Real Time Clock and Time Stamping Figure 8 1 Real Time Counter RTC 0 0 6 cee Figure 8 2 Increment of Sub nanoseconds and Nanoseconds Field Figure 8 3 Time Stamping Position 0 60 cece cee teens Ethernet AVB Endpoint User Guide www xilinx com UG492 July 23 2010 XILINX Chapter 9 Precise Timing Protocol Packet Buffers Figure 9 1 Tx PTP Packet Buffer Structure esee 84 Figure 9 2 Rx PTP Packet Buffer 0 00000 ee 86 Chapter 10 Configuration and Status Figure 10 1 Single Read Transaction 0 0 00000 88
130. igured to filter on a partial Destination Address In order for the frame to obtain a match the initial 29 bits as used in this example of the received frame must exactly match the first 29 bits of the Match Pattern Register This functionality is useful for filtering across Multicast group Addresses Ethernet AVB Endpoint User Guide www xilinx com 71 UG492 July 23 2010 Chapter 7 Ethernet AVB Endpoint Reception g XILINX VLAN Priority Match es rx_clk_enable legacy_rx_data 7 0 L T l DATA legacy rx data valid Match Pattern Register Match Enable Register VLAN priority filter Don t cares Figure 7 6 Filtering of VLAN Frames with a Specific Priority Value The example illustrated in Figure 7 6 shows a single MAC Header Filter one of the eight provided configured to filter on frames containing a VLAN tag with a VLAN Priority value of 1 Any Other Combinations Because the Match Pattern Register and Match Enable Register provide the ability to filter across any bitwise match don t care pattern of the initial 128 bits of an Ethernet frame match combinations of Destination Address Length Type Field when no VLAN tag is present VLAN fields when present can be selected with complete flexibility 72 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Rx AV Traffic I F Rx AV Traffic I F The signals forming the Rx AV Traffic I F are defined in Table
131. iled Example Design EDK format www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 15 Detailed Example Design Standard Format This chapter provides detailed information about the core when generated for the Standard CORE Generator software format This option is selected from page 1 of the customization GUI and will deliver the core with the standard CORE Generator software directory structure used by many LogiCORE IP systems including all other CORE Generator software Ethernet cores This chapter provides detailed information on the core and example design including a description of files and the directory structure generated by the Xilinx CORE Generator software the purpose and contents of the provided scripts the contents of the example HDL wrappers and the operation of the demonstration test bench Please refer to Chapter 16 Detailed Example Design EDK format when targeting the Embedded Development Kit D project directory Top level project directory name is user defined C9 project directory component name gt Core release notes file Lj component name doc Product documentation Lj component name example design Verilog or VHDL design files Lj component name implement Implementation script files 9 implement results Results directory created after implementation scripts are run and contains implement script results C
132. implement the IEEE P802 1AS specification However the full functionality is only achieved using a combination of these hardware blocks coupled with functions provided by the Software Drivers run on an embedded processor Consequently the following hardware block descriptions also give some insight into the software driver functionality Note The following definitions provide only a simplistic concept of PTP protocol operation For detailed information about the PTP protocol see the EEE P802 1AS specification Tx PTP Packet Buffers The PTP packet buffer contains pre initialized templates for seven different PTP packets defined by the P802 1AS specification The buffer contents are read writable through the PLB and a separate configuration register within the core requests to the Tx Arbiter which of these seven packets is to be transmitted A dedicated interrupt signal will be generated by the core whenever a PTP packet has been transmitted The software drivers provided with the core using the PLB and dedicated interrupts will use this interface to periodically update specific fields within the PTP packets and request transmission of these packets See Chapter 9 Precise Timing Protocol Packet Buffers for further information Tx Time Stamp Whenever a PTP packet is transmitted a sample of the current nanosecond value of the local RTC is taken This timestamp value is written into a dedicated field within the Tx PTP Packet B
133. implementations www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Example Design PLB Module The following files describe the logic for the PLB module VHDL lt project_dir gt lt component_name gt example_design plb_client_logic vhd Verilog lt project_dir gt lt component_name gt example_design plb_client_logic v The PLB module connects to the PLB interface of the core and performs the following functions e Initialization A state machine writes to the RTC configuration space to set the RTC running at the correct frequency following reset power up e PTP Timer Interrupt Service Routine When the interrupt ptp timer is asserted a state machine requests transmission of a PTP sync frame then clears the interrupt e PTP Transmit Interrupt Service Routine When interrupt ptp txis asserted a PTP frame has been transmitted the state machine reads from the PTP Tx Control Status register to determine the type of PTP frame sent If it was a sync frame it then requests a follow up frame to be sent For any other PTP frame type no action is taken Reading from the PTP Tx Control Status register clears the interrupt e PTP Receive Interrupt Service Routine When interrupt_ptp_rx is asserted a PTP frame has been received the state machine reads from the PTP Rx Control Status register to determine which of the PTP frame buffers the received frame will be stored in this read also clears the int
134. ing a write to the nanosecond offset register defined in Table 10 6 Table 10 8 Seconds Field Offset bits 47 32 PLB base address 0x280C Bit no Default Access Description 15 0 0 R W 16 bit offset value for the RTC seconds field bits 47 32 Used by the microprocessor to initialize the RTC then afterwards to perform the regular RTC corrections when in slave mode 31 16 0 RO Unused RTC Increment Value Control Register Table 10 9 describes the RTC Increment Value Control Register This provides configurable increment rate for the Real Time Clock counter this increment register should simply take the value of the clock period which is being used to increment the RTC However the resolution of this increment register is very fine in units of 1 1048576 1 220 fraction of one nanosecond Therefore the RTC increment rate can be adjusted to a very fine degree of accuracy This provides the following features e The RTC can be incremented from any available clock frequency that is greater than the P802 1AS defined minimum of 25 MHz e When acting asa clock slave the rate adjustment of the RTC can be matched to that of the network clock master to an exceptional level of accuracy Table 10 9 RTC Increment Value Control Register PLB base address 0x2810 Bit no Default Access Description 25 0 0 R W Per rtc c1k clock period Increment Value for the RTC 31 26 0 RO Unused Cur
135. inx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Using the Xilinx LogiCORE IP Tri Mode Ethernet MACs Figure 12 7 shows the implementation using an ISE software top level project In this hierarchy the embedded processor subsystem is created using an EDK project containing only the blocks illustrated in the EDK tool domain block This EDK project is not the top level of the system and is instantiated as a black box subcomponent in a standard ISE software project as illustrated In this example e The EDK component is synthesized by the EDK tools this block can then be left alone unedited e All other components for example the Custom AV logic can be created using a standard ISE software project This flow should be familiar to a wider range of engineers than the EDK tool set The main advantages of this implementation hierarchy are in terms of possible faster development turn around for synthesis implementation run time This is as a result that the EDK components will pre exist in netlist format and do not have to be re synthesized for each design iteration A final word of explanation is required for the EDK project illustrated in Figure 12 7 To assign the AVB software drivers running on the MicroBlaze processor to the Ethernet AVB Endpoint core the plb port pcore was created This pcore is simply a bunch of wires to route through all of the PLB signals through to ports of the EDK block top level In th
136. ion of files and the directory structure generated e Chapter 16 Detailed Example Design EDK format provides detailed information about the core when generated in the Standard Embedded Development Kit EDK format including a description of files and the directory structure generated e Appendix A RTC Time Stamp Accuracy describe the necessity of accurate time stamps essential to the Precise Timing Protocol across the network link and provides some of the ways inaccuracies are introduced Conventions 18 This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Courier font Meaning or Use Messages prompts and program files that the system displays Signal names in text also Example Speed grade 100 Courier bold Literal commands that you enter in a syntactical statement ngdbuild design name Helvetica bold Commands that you select from a menu File Open Keyboard shortcuts Ctrl C Variables in a syntax statement for which you must supply values ngdbuild design_name reserved Italic font See the User Guide for more References to other manuals 3 information If a wire is drawn so that it Emphasis in text overlaps the pin of a symbol the two nets are not connected f I h t t 4 Dark Shading ISDOEISUBISIO TED DOO OE This feature is
137. iven in this specification However the current implementation uses truncated nanoseconds rather than the scaled Ns type The value is set to 0 by default define XAVB_PROP_DELAY_ASYMMETRY 0 Setting up SourcePortldentity and Default TX PTP Messages The TX Packet buffers are pre initialized with default values for all of the possible fields in each message However in order for the Ethernet AVB Endpoint software drivers to run correctly the following fields need to be written with sensible values e sourcePortIdentity in all TX PTP default messages e grandmasterldentity in TX PTP Announce message e pathSequence ClockIdentity 1 in TX PTP Announce message The example design xavb example c provides a simple mechanism to achieve this using the following defines define ETH SOURCE ADDRESS EUI48 HIGH OxFFEEDD define ETH SOURCE ADDRESS EUI48 LOW OxCCBBAA You can edit the defines above to be the Ethernet Source Address for the device and the example software then provides code that translates this address into an XAvb PortlIdentity struct The function XAvb SetupSourcePortlIdentity is called with the XAwb PortIdentity struct and writes it to the appropriate fields in the TX PTP Buffer Additionally it stores it in the XAvb struct as the following member Contains the local port Identity information XAvb PortIdentity portIdLocal The example software also provides an example of
138. ization protocol e Tx PTP Packet Buffer e Rx PTP Packet Buffer These are both described in this chapter as they are closely related Tx PTP Packet Buffer The Tx PTP packet buffer is illustrated in Figure 9 1 This packet buffer provides working memory to hold the PTP frames which are required for transmission The software drivers via the PLB configuration bus can read modify write the PTP frame contents and whenever required can request transmission of the appropriate PTP frames The PTP packet buffer is implemented in dual port block RAM Port A of the block RAM is connected to the PLB configuration bus all addresses in the buffer are read writable through the PLB Port B of the block RAM is connected to the Tx Arbiter module allowing PTP frames to be read out of the block RAM and transmitted through the connected TEMAC The Tx PTP Packet Buffer is divided into eight identical buffer sections as illustrated Each section contains 256 bytes which are formatted as follows e the first byte at address zero contains a frame length field This indicates how many bytes make up the PTP frame that is to be transmitted from this particular PTP buffer e The next seven bytes from address 1 to 7 are reserved for future use e The PTP frame data itself is stored from address 8 onwards The amount of addresses used is dependent on the indicated frame length field which will be different for each PTP frame type Each PTP b
139. key features of the credit based algorithm which are e The Tx Arbiter will schedule queued transmission from the Tx AV Traffic I F if the algorithm is in credit greater or equal to 0 e If there is less than 0 credit not shown in Figure 6 4 but the credit can sink below 0 then the Tx Arbiter will not allow AV traffic to be transmitted legacy traffic if queued will be scheduled instead e When no AV traffic is queued any positive credit will be lost and the credit is reset to 0 e When AV traffic is queued and until the time at which the Tx Arbiter is able to schedule it while waiting for an in progress legacy frame to complete transmission credit can be gained at a rate defined by the idleSlope 62 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Tx Arbiter e During AV traffic transmission credit is removed at a rate defined by the sendSlope e The hiLimit and loLimit settings impose a fixed range on the possible values of credit If the available credit hits one of these limits it will not exceed but saturate at the magnitude of that limit These limits are fixed in the netlist to ensure that the interface is not used incorrectly The overall intention of the two settings idleSlope and sendSlope is to spread out the AV traffic transmission as evenly as possible over time preventing periods of bursty AV transmission surrounded by idle AV transmission periods No further backgr
140. l Direction Description legacy rx data 7 0 Output Legacy frame data received is supplied on this port legacy rx data valid Output Control signal for the legacy rx data 7 0 port 48 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Core Interfaces Table 5 3 Legacy Traffic Signals Receiver Path Signal Direction Description legacy rx frame good Output Asserted at the end of frame reception to indicate that the frame should be processed by the MAC client legacy rx frame bad Output Asserted at the end of frame reception to indicate that the frame should be discarded by the MAC client either the frame contained an error or it was intended for the PTP or AV traffic channel legacy rx filter match 7 0 Output This output is only present when the MAC Header Filters are present when the core is generated in Standard CORE Generator Format When present each bit in the bus corresponds to one of the unique Legacy MAC Header Filters A bit is asserted in alignment with legacy rx data valid signal if the corresponding filter number obtained a match AV Traffic Interface AV Traffic Transmitter Path Signals Table 5 4 defines the core client side AV traffic transmitter signals used to transmit data from the AV client logic into the core All signals are synchronous to the MAC transmitter clock tx c1k which must be qualified by th
141. le INST top generic_host_if_inst resync_host_toggle data_sync TNM FFS resync_host_toggle TIMESPEC ts_host_toggle FROM host_toggle TO resync_host_toggle 8 ns DATAPATHONLY INST top generic_host_if_inst host_rd_data_result TNM FFS host_rd_data INST top generic_host_if_inst cpu_rd_data TNM FFS cpu_rd_data TIMESPEC ts cpu rd data FROM host rd data TO cpu rd data 8 ns DATAPATHONLY 110 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 12 System Integration As described in Chapter 4 Generating the Core and Chapter 5 Core Architecture the core can be generated in one of two formats Standard CORE Generator Format This option will deliver the core in the standard CORE Generator output format as used by many other cores including previous versions of this core and all other Ethernet LogiCORE IP solutions When generated in this format the core is designed to interface to the LogiCORE IP Tri Mode Ethernet MAC or the LogiCORE IP Embedded Tri Mode Ethernet MAC wrappers Refer to Using the Xilinx LogiCORE IP Tri Mode Ethernet MACs section of this chapter EDK pcore Format This option will deliver the core in the standard pcore format suitable for directly importing into the Xilinx Embedded Development Kit EDK environment When generated in this format the core is designed t
142. ls as illustrated e The Interrupt Signals should be connected to the inputs of an interrupt controller module for example the xps intc core provided with the EDK e The embedded processor should be configured to use the software drivers provided with the core see Chapter 13 Software Drivers not illustrated Ethernet AVB Endpoint User Guide www xilinx com 119 UG492 July 23 2010 Chapter 12 System Integration XILINX Imb bram if cntlr Microblaze xps intc xps uartlite Ethernet AVB Endpoint Host I F MDIO PLB Ethernet PHY I F Figure 12 5 Connection of the Ethernet AVB Endpoint Core into an Embedded Processor Sub system 120 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Using the Xilinx LogiCORE IP Tri Mode Ethernet MACs Figure 12 5 can be implemented using the Xilinx tool set using two methods e Using an EDK Project Top Level e Using an ISE Software Top Level Project Using an EDK Project Top Level BRAM Imb bram if cntlr Microblaze EDK Tool Domain PLB xps intc xps uartlite pcore plb port pcore pcore Ethernet TEMAC AVB Endpoint Host I F a MDIO PLB n pt ptp time n D pig X interrupt ptp rx pcore l l Custom AV logic l CESS MAC Ethernet client PHY I F pcore VE es l Legacy l Custom Legacy logic traffic l VE Pi Figure 1
143. lt component_name gt simulation demo_tb vhd Verilog lt project_dir gt lt component_name gt simulation demo_tb v The top level test bench entity instantiates the example design for the core which is the Device Under Test DUT The test bench provides clocks and resets and gathers statistics for the duration of the simulation A final statistic report is created at the end of the simulation run time that contains the following e The number of PTP frames transmitted and received e The number of AV frames transmitted and received e The number of legacy frames transmitted and received All transmitted frame statistics should exactly match the received frame statistics for each particular frame type if this is not the case an error message is issued e Finally the test bench estimates the percentage of overall Ethernet line rate consumed by each of the three types This should illustrate the bandwidth policing functionality of the core which should only allow the AV frames to consume a maximum of 75 of the overall bandwidth 156 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Example Design Customizing the Test Bench Simulation Run Time The default simulation run time is set to only 40 microseconds which can be easily extended by editing the simulation_run_time constant set near the top of the demonstration test bench file For example from the VHDL file constant simulation_run_time
144. lways available for legacy ethernet applications The AV traffic interface in Figure 3 2 is shown as interfacing to a 1722 Packet Manager block The IEEE1722 is also an evolving standard which will specify the embedding of audio video data streams into Ethernet Packets The 1722 headers within these packets can optionally include presentation time stamp information Contact Xilinx for further system level information Ethernet AVB Endpoint User Guide www xilinx com 33 UG492 July 23 2010 Chapter 3 Overview of Ethernet Audio Video Bridging 34 www xilinx com XILINX Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 4 Generating the Core The Ethernet AVB Endpoint core is fully configurable using the CORE Generator software which provides a Graphical User Interface GUI for defining parameters and options For help starting and using the CORE Generator software see the documentation supplied with the ISE software including the CORE Generator User Guide available from www xilinx com support software manuals htm Ethernet AVB GUI Page 1 Figure 4 1 shows page 1 of the Ethernet AVB Endpoint GUI customization screen Ethernet AVB Endpoint IP Symbol x VE E kgC Ethernet AVB Endpoint DERE GU Component Name ethernet avb endpoint v2 4 TX CLK EN AV TX DATA 7 0 TX DATA 7 0 Core Delivery Format AV TX VALID TX DATA VALID Standard CORE Generator format
145. mber Ethernet AVB Endpoint User Guide www xilinx com 85 UG492 July 23 2010 Chapter 9 Precise Timing Protocol Packet Buffers XILINX The Software Drivers provided with the core using the PLB and dedicated interrupt will use this interface to decode and then act on the received PTP packet information Buffer Number Rx PTP Packet Buffers Buffer Base Address 0x0F00 0x0E00 0x0D00 00CO0 0x0B00 x0A00 N 0x0990 b __ X 0x0800 N 0x0700 0x0600 0x0500 0x0400 0x0300 0x0200 0x0100 0x0000 Single Rx PTP Packet Buffer Address Buffer Base Address timestamp 31 24 OxFF timestamp 23 16 OxFE timestamp 15 8 OxFD timestamp 7 0 OxFC unused frame size PTP Frame Data 0x00 byte wide data Figure 9 2 Rx PTP Packet Buffer 86 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 10 Configuration and Status This chapter provides general guidelines for configuring and monitoring the Ethernet AVB Endpoint core including an introduction to the PLB configuration bus and a description of the core management registers Processor Local Bus Interface The Processor Local Bus PLB bus on the Ethernet AVB Endpoint core is designed to be integrated directly in the Xilinx Embedded Development Kit EDK where it can be easily integrated and connected
146. mediately after an update During the 40 ns update cycle the error accrues linearly to a maximum of 40 ns This behavior is periodic as illustrated In Figure A 1 two time stamps of the RTC are sampled The figure shows that the accuracy is variable For example e The 1st time stamp is requested at 119 ns However the RTC has yet to update and so the sample taken will be of 80 ns This has an inaccuracy of 39 ns e The 2nd time stamp is requested at 201 ns The RTC has recently updated and so the sample taken will be of 200 This has an inaccuracy of 1 ns Ethernet AVB Endpoint User Guide www xilinx com 167 UG492 July 23 2010 Appendix A RTC Time Stamp Accuracy XILINX The maximum RTC inaccuracy per time stamp sample is equal to the period of the RTC reference clock in this example 40 ns By using a high frequency RTC reference clock a high degree of accuracy can be obtained r 40 80 120 160 200 240 Time ns 40 RTC Error ns Timestamp A Timestamp B Error 39 ns Error 1 ns Figure A 1 RTC Periodic Error 168 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Time Stamp Accuracy RTC Sampling Error Take Timestamp SFD detected on MAC Client I F MAC Tx Rx clock It has to be assumed that the RTC reference clock is of a different frequency to the MAC transmitted and receiver clocks Therefore the RTC sampling logic has to be asynchronous There are a number of method
147. mentation script You must implement the core before attempting to run timing simulation To run a VHDL or Verilog timing simulation of the example design 1 Run the implementation script see Implementing the Example Design page 141 2 Open a command prompt or shell then set the current directory to lt project_dir gt lt component_name gt simulation timing 3 Launch the simulation script ModelSim vsim do simulate_mti do IES simulate_ncsim sh VCS simulate vcs sh Verilog only The simulator script compiles the gate level model and the demonstration test bench adds relevant signals to a wave window and then runs the simulation to completion You can then inspect the simulation transcript and waveform to observe the operation of the core The Ethernet AVB Endpoint core can be delivered in two different formats selectable from page 1 the CORE Generator Customization GUI e Standard CORE Generator software format provided for the standard ISE software environment For detailed information about the core delivery using the Standard CORE Generator software format including example design information guidelines for modifying the design and extending the test bench see Chapter 15 Detailed Example Design Standard Format e Generate as an EDK pcore provided for the Embedded Development Kit For detailed information about the core delivery for the Embedded Developments Kit EDK see Chapter 16 Deta
148. mponent_name eth_avb_endpoint_v2_4 CSET number_of_plb_masters 2 CSET plb_base_address 00000000 Table 4 1 XCO File Values and Default Values Parameter XCO File Values Default GUI Setting component_name ASCII text starting with a letter and eth_avb_endpoint_v2_4 based on the following character set a z 0 9 and _ generate_as_edk_pcore Select between true and false false number_of_plb_masters Select from the range 1 to 16 2 plb_base_address Select from the range 0x00000000 0x00000000 to OxFFFF8000 Output Generation The output files generated by the CORE Generator software are placed in the project directory The list of output files includes the following items The netlist file for the core Supporting CORE Generator software files Release notes and documentation Subdirectories containing an HDL example design Scripts to run the core through the back end tools and to simulate the core using Mentor Graphics ModelSim v6 5c Cadence Incisive Enterprise Simulator IES v9 2 and Synopsys VCS and VCS MX 2009 12 See the following chapters for a complete description of the CORE Generator software output files and for detailed information about the HDL example design 38 Chapter 14 Quick Start Example Design Chapter 15 Detailed Example Design Standard Format Chapter 16 Detailed Example Design EDK format www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010
149. must be constrained to the correct maximum frequency This is 125 MHz for 1 Gigabit Ethernet rates The following UCF syntax shows the necessary constraints being applied to tx c1k NET tx_clk TNM_NET tx_clk TIMEGRP tx_clock tx_clk TIMESPEC TS tx clock PERIOD tx clock 8000 ps HIGH 50 rx clk The interface clock of the Ethernet MACS receiver must be constrained to the correct maximum frequency This is 125 MHz for 1 Gigabit Ethernet rates The following UCF syntax shows the necessary constraints being applied to xx c1k NET rx clk TNM NET rx clk TIMEGRP rx clock rx clk TIMESPEC TS rx clock PERIOD rx clock 8000 ps HIGH 50 104 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Required Constraints rtc_clk The RTC can be incremented from any available clock frequency that is greater than the AVB standards defined minimum of 25 MHz However the faster the frequency of the clock the smaller will be the step increment and the smoother will be the overall RTC increment rate Xilinx recommends clocking the RTC logic at 125 MHz because this is a readily available clock source obtained from the transmit clock source of the Ethernet MAC at 1 Gbps speed This frequency significantly exceeds the minimum performance of the P802 1AS specification The following UCF syntax shows a 125 MHz period constraint being applied to rtc c1k NET rtc
150. n 152 Top Level Example Design HDL ssseeeee rne 153 Ethernet Frame Stimulus sese e 153 Ethernet Frame Checker 0 0 ccc cece eee een 154 Loopback Mod le 1 2 4b Rer bea ea dabei nade anes ice eit 154 PLB Module uree ee nee rates uta ee Ateste eee Pa 155 Demonstration Test Bench 00 ccc cc cect ence ete ne tenn ene 156 Customizing the Test Bench 0 6 6 ccc 157 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 16 Detailed Example Design EDK format Directory and File Contents 22 229 erbe a Fe led FER Pese 160 project directory usce eek eer Gad e aia dade a dede cds 160 project directory component name 6 cece eee 160 component name doc 2 0 en 161 component name MyProcessorIPLib 0 0 eee eee eee 161 MyProcessorIPLib pcores eth_avb_endpoint_v2_04_a 00000004 161 pcores eth avb endpoint v2 04 a data 00 00 161 pcores eth_avb_endpoint_v2_04_a hdl vhdl 0 0000 162 pcores eth avb endpoint v2 04 a netlist sess 162 MyProcessorIPLib drivers avb_v2_04_a 1 eee 162 drivers avb_v2_04 a data ccc cue ee eb ee E Rh ee ce hom sed 163 drivers avb v2 04 a examples isssssssssseeee eee eee eee ee 163 drivers avb_v2_04_a SrC ow eee e kai 164 Importing the Ethernet AVB Endpoint Core into the Embedded Development Kit EDK cresce TREE
151. nal an error in a frame which is currently undergoing transmission Ethernet AVB Endpoint User Guide www xilinx com 59 UG492 July 23 2010 60 Chapter 6 Ethernet AVB Endpoint Transmission XILINX tx_clk_enable av_tx_data 7 0 DA J SA L T DATA es DA av_tx_data_valid J J av_tx_done ee A A av_tx_ack Figure 6 3 Normal Frame Transmission across the AV Traffic Interface Figure 6 3 illustrates the timing of a normal frame transfer When the AV client initiates a frame transmission it places the first column of data onto the av tx data 7 0 port and asserts a logic 1 onto av tx valid After the Ethernet AVB Endpoint core reads the first byte of data it asserts the av tx ack signal On the next and subsequent rising clock edges the client must provide the remainder of the data for the frame The end of frame is signalled to the core by taking the av tx valid to logic 0 In Figure 6 3 following the end of frame transmission the av tx done signal is held low which indicates to the Tx Arbiter that another AV frame is queued Unless the configurable bandwidth restrictions have been exceeded this parks the Tx Arbiter onto the AV traffic queue Figure 6 3 then illustrates the client asserting the av tx valid signal to request a subsequent frame and the frame transmission cycle of Figure 6 3 repeats However if no further AV traffic frames are queued the av tx done signal
152. ndler e interrupt_ptp_rx needs to call the function XAvb_PtpRxInterruptHandler Again see the provided software example file that performs these steps Ethernet AVB Endpoint User Guide www xilinx com 133 UG492 July 23 2010 Chapter 13 Software Drivers g XILINX Core Initialization When Using a LogiCORE IP Tri Mode Ethernet MAC Note When connecting to the XPS LocalLink Tri Mode Ethernet MAC xps Il temac available in EDK the MAC is delivered with its own drivers and the functionality of this subsection is not required The Xilinx LogiCORE IP Tri Mode Ethernet MACs require initialization of the MDIO clock frequency the MDC signal and requires specific non default configuration VLAN enabled Flow Control disabled The following lines of code of perform these steps Configure MDIO Master in TEMAC MUST be done before any MDIO accesses XAvbMac WriteConfig InstancePtr Config BaseAddress XAVB MAC MGMT REG OFFSET 0x0000004F Disable TEMAC Flow Control XAvbMac WriteConfig InstancePtr Config BaseAddress XAVB MAC FC REG OFFSET 0x0 Initialize TEMAC by enabling Tx and Rx with VLAN capability XAvbMac WriteConfig InstancePtr Config BaseAddress XAVB MAC TX REG OFFSET XAVB MAC TX ENABLE MASK XAVB MAC TX VLAN ENABLE MASK Ethernet AVB Endpoint Setup This section describes the main elements that you may have to modify in order
153. ng the Virtex 5 FPGA Embedded Ethernet MAC Wrapper EMAC in the CORE Generator software be sure that the following options are selected e Enable EMACs Enable only a single EMAC from the pair at this time e Host Type Select Host e Speed Select Tri speed e Global Buffer Usage Clock Enable e Flow Control Configuration Disabled e EMACO Configuration Enable VLAN Enable in both the Transmitter Configuration and Receiver Configuration boxes See the Virtex 5 Embedded Tri Mode Ethernet MAC Wrapper Getting Started Guide UG340 for additional information 116 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Using the Xilinx LogiCORE IP Tri Mode Ethernet MACs Connections Without Ethernet Statistics Ethernet AVB Endpoint Core Netlist Block level Wrapper from Virtex 5 Embedded Tri mode Ethernet MAC Wrapper CLIENTEMACOPAUSEREQ CLIENTEMACOPAUSEVAL 15 0 GND tx clk TX ClK 0 tx clk en TX CLIENT CLK ENABLE 0 tx data 7 0 CLIENTEMACOTXD 7 0 EMACOCLIENTTXSTATS NC tx data valid CLIENTEMACOTXDVLD EMACOCLIENTTXSTATSVLD NC tx underrun CLIENTEMACOTXUNDERRUN EMACOCLIENTTXSTATSBYTEVLD NC tx ack EMACOCLIENTTXACK NC 4 EMACOCLIENTTXCOLLISION NC 74 EMACOCLIENTTXRETRANSMIT CLIENTEMACOIFGDELAY GND rx clk GMII RX CLKO IX Cclk en RX CLIENT CLK ENABLE 0 rx data 7 0 EMACOCLIENTRXD 7 0 EMACOCLIENTRXSTATS 6 0 NC rx
154. ng the default options The default core and its supporting files including the example design are generated in your project directly For a detailed description of the design example files and directories see Chapter 15 Detailed Example Design Standard Format www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Implementing the Example Design Implementing the Example Design After the core is generated the netlists and example design can be processed by the Xilinx implementation tools The generated output files include several scripts to assist you in running the Xilinx software To implement the Ethernet AVB Endpoint example design core From the CORE Generator software project directory window type the following Linux cd lt project_dir gt lt component_name gt implement implement sh Windows gt cd project dir N component name Vimplement implement bat These commands execute a script that synthesizes builds maps and place and routes the example design The script then creates gate level netlist HDL files in either VHDL or Verilog along with associated timing information SDF files Simulating the Example Design Setting up for Simulation To run functional and timing simulations you must have the Xilinx Simulation Libraries compiled for your system See the Compiling Xilinx Simulation Libraries COMPXLIB in the Xilinx ISE Synthesis and Verification Design Guide
155. not supported Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option name design name www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Conventions Convention Meaning or Use Example A list of it f hich Braces ag OF Lems Om Wue you lowpwr on off must choose one or more i in a list of Vertical bar Sey atest maaan lowpwr on off choices Angle brackets User defined variable or in code samples directory name Vertical ellipsis Repetitive material that has been omitted IOB 1 Name IOB 2 Name QOUT CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block block name loci loc2 locn Notations The prefix Ox or the suffix h indicate hexadecimal notation A read of address 0x00112975 returned 45524943h An n means the signal is active low usr teof nis active low Online Document The following conventions are used in this document location in another document Convention Meaning or Use Example C f link See the section Guide eS ee Contents for details Blue text location in the current Sec TilleR A document ee Tit le ormats in Chapter for details Cross reference link to a See Figure 2 5 in the Virtex 5 Red text FPGA
156. nt transmitter interface of the supported Xilinx Tri Mode Ethernet MAC core there is a one to one correspondence between signal names of the block level wrapper from the Tri Mode Ethernet MAC example design after the legacy prefix is removed This provides backwards compatibility all existing MAC client side designs can connect to the legacy Ethernet port unmodified Ethernet AVB Endpoint User Guide www xilinx com 57 UG492 July 23 2010 58 Chapter 6 Ethernet AVB Endpoint Transmission XILINX Error Free Legacy Frame Transmission St c _CMDm tx_clk_enable L DA ap SA L T DATA legacy_tx_data_valid legacy_tx_ack J legacy_tx_underrun x FC OH Figure 6 1 Normal Frame Transmission across the Legacy Traffic Interface Figure 6 1 illustrates the timing of a normal frame transfer When the legacy client initiates a frame transmission it places the first column of data onto the legacy_tx_data 7 0 port and asserts a logic 1 onto legacy_tx_data_valid After the Ethernet AVB Endpoint core reads the first byte of data it asserts the legacy tx ack signal On the next and subsequent rising clock edges the client must provide the remainder of the data for the frame The end of frame is signalled to the core by taking the legacy tx data valid to logic 0 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Tx AV Traffic I F Errored Legacy Frame Transmissi
157. ntain its own Address Filter logic When not provided the following address locations will return 0s for a read and all writes will be ignored When the core is generated in Standard CORE Generator Format the Legacy MAC Header Filters are provided These filters are present on the Rx Legacy traffic path are capable of providing match recognition logic against eight unique MAC frame headers Each of the eight individual filters require eight memory mapped registers to configure them as defined in Table 10 16 Each individual filter contains its own set of these eight registers When interpreting Table 10 16 the variable filter should be replaced with an integer number between 0 and 7 which represent the eight individual filters Table 10 16 MAC Header Filter Configuration Registers Address Default Access Description PLB base address OxFFFFFFFF R W Match Pattern Ethernet frame bits 0 to 31 0x3000 32 bit pattern to match against the Ethernet filters 0x20 frame bits 0 to 31 Specifically match pattern bits 0x0 31 0 MAC Destination Address Field bits 31 0 PLB base address Ox0000FFFF R W Match Pattern Ethernet frame bits 32 to 63 0x3000 32 bit pattern to match against the Ethernet filters 0x20 frame bits 32 to 63 Specifically match pattern bits 0x4 15 0 MAC Destination Address Field bits 47 32 31 16 MAC Source Address Field bits 15 0 PLB base address 0x00000000 R
158. nx com 101 Chapter 10 Configuration and Status g XILINX 102 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 11 Constraining the Core This chapter defines the Ethernet AVB Endpoint core constraints An example user constraints file UCF is provided for the core and the HDL example design Required Constraints Device Package and Speedgrade Selection The Ethernet AVB Endpoint core can be implemented in Spartan 3 Spartan 3E Spartan 3A 3A DSP Spartan 6 Virtex 5 and Virtex 6 devices that are large enough to accommodate the core and meet the following speed grades 1 for Virtex 5 and Virtex 6 devices 2 for Spartan 6 devices 4 for all Spartan 3 devices I O Location Constraints No specific I O location constraints are required Placement Constraints No specific placement constraints are required Timing Constraints The core can have up to five separate clock domains plb clk for the main EDK PLB and processor clock frequency host_clk for the management interface logic of the connected Tri Mode Ethernet MAC tx cl rx c Lk for the MAC transmitter clock domain 1k for the MAC receiver clock domain rtc clk for the Real Time Clock reference frequency These clock nets and the signals within the core that cross these clock domains must be constrained appropriately in a UCF Sections of UCF syntax are used in the following descriptions to pro
159. o interface to the XPS LocalLink Tri Mode Ethernet MAC xps ll temac Refer to Using the Xilinx XPS LocalLink Tri Mode Ethernet MAC section of this chapter Using the Xilinx LogiCORE IP Tri Mode Ethernet MACs The Ethernet AVB Endpoint core should be generated in the Standard CORE Generator Format The Ethernet AVB Endpoint core can be connected to the following Ethernet MACs from the CORE Generator LogiCORE IP library LogiCORE IP Tri Mode Ethernet MAC Soft Core available for all Spartan 3 Spartan 3E Spartan 3A Spartan 3A DSP Spartan 6 Virtex 5 and Virtex 6 devices LogiCORE IP Embedded Tri Mode Ethernet MACs available in selected Virtex 5 and Virtex 6 devices Please also refer to individual product documentation Ethernet AVB Endpoint User Guide www xilinx com 111 UG492 July 23 2010 Chapter 12 System Integration g XILINX LogiCORE IP Tri Mode Ethernet MAC Soft Core Tri Mode Ethernet MAC Core Generation When generating the Tri Mode Ethernet MAC TEMAC core in the CORE Generator software be sure that the following options are selected e Management Interface Enabled e Clock Enables Enabled e Address Filter Disabled See the Tri Mode Ethernet MAC User Guide UG138 for additional information 112 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Using the Xilinx LogiCORE IP Tri Mode Ethernet MACs Connections Without Ethernet Statist
160. oint Connections Figure 12 8 illustrates the overall connections of the Ethernet AVB Endpoint core only the AV Traffic Interface remains unconnected and is therefore available for custom logic All connections must be made in the EDK environment please refer to Xilinx Platform Studio documentation Extracts from a mhs file will be included at the end of this section to further illustrate these connections Figure 12 9 illustrates the connections of the Ethernet AVB Endpoint core to the XPS LocalLink Tri Mode Ethernet MAC xps ll temac core in detail All connections as shown are logic less connections Observe that e The Legacy Traffic Interface and Tri Mode Ethernet MAC Client Interface of the Ethernet AVB Endpoint core connect directly to the xps ll temac e The Ethernet transmitter client clock domain must always be connected to the tx clkinput of the Ethernet AVB Endpoint core Additionally the transmitter clock enable as used with the TEMAC must always be connected to the tx_clk_en input of the Ethernet AVB Endpoint core e The Ethernet receiver client clock domain must always be connected to the xx c1k input of the Ethernet AVB Endpoint core Additionally the receiver clock enable as used with the TEMAC must always be connected to the xx c1k en input of the Ethernet AVB Endpoint core 126 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Using the Xilinx XPS LocalLink Tri Mod
161. on _ tx_clk_enable DA Jl SA l L T DATA al legacy_tx_data_valid J legacy tx ack J legacy tx underrun Figure 6 2 Legacy Frame Transmission with Underrun The legacy tx underrunis provided to give full backwards compatibility between the Legacy Traffic I F and the client interface of the Tri Mode Ethernet MAC The legacy tx underrun provides a mechanism to inject an error into a frame before transmission is completed This can occur for example if a FIFO connected to the Legacy client empties during transmission To error the frame the legacy tx underrun signal may be asserted during the data transmission or up to 1 valid clock cycle after 1egacy tx data valid goes low Tx AV Traffic I F The signals forming the Tx AV Traffic I F are defined in Table 5 4 All signals are synchronous to the Tri Mode Ethernet MAC transmitter clock tx c1k which must always be qualified by the corresponding clock enable tx c1k en see Table 5 1 See Talker Assumptions page 31 for information about the expectations for the AV traffic input to the Ethernet AVB Endpoint on this interface This interface is intentionally very similar to the Tx Legacy Traffic I F Note however that the legacy traffic does not contain a signal that is equivalent to av tx done Additionally the AV does not contain a signal that is equivalent to legacy tx underrun no mechanism is currently provided on the AV interface to sig
162. on System Requirements ou less ipa ia eee ieee HE ie dee ieee yi eee ed About TNE CORE SEP Lr Recommended Design Experience 00 00 e cece eee eee eee Additional Core Resotrees iss eese det rare b ce tek be be dee hA dedos ds Technical Support o coss bet dete b EK HOD UNIO Ue OP Oe eC Feed Back iiss cere VE tes bt wee ER be toe E e NOE OR e be Ethernet AVB Endpoint Cres iser riets ccc e Doc ment 22e cones dpe eret err ot eo ee Dae andar inn d re EUR Chapter 2 Licensing the Core Before you Debits xv cs pilin P3 Geld ed e E iG eek yh eye e eed License OPDUONS or baleen RU deae MUR obe e Mea pone awake E dey Simulation Oly ict iue bebe d eC ERE Pd en P eic a i dies Full System Hardware Evaluation sse eh Full err Obtaining Your License Key caus pae eai te e b p ee gap doe i Ree Simulation License siue a eee re Full System Hardware Evaluation License 0 0000 e eee eee eee Obtaining a Full License Key 0 0 e Installing the License File css iicg pute eb Erg MEER Ve PEE Ya Chapter 3 Overview of Ethernet Audio Video Bridging AVB Specifications scedbees tek dae pudo d redo cdd oes dri Kad dae acea PIU TAS EEUU P8O2 a eor RE REDE ed ed Rea eee ed ee Peed Put i dee os isti E eae a D LAU sce EE Typical Implementation i i pio EEEEA Eo Ier oe taa EA eoe Pci dd Ethernet AVB Endpoint User Guide www xilinx com UG492 July 23 2010 XILINX Chapter 4 Gener
163. onnected to the supported embedded processors MicroBlaze or PowerPC As a result the PLB interface does not require in depth understanding and the following information is provided for reference only See the EDK documentation for further information The PLB interface defined by IBM can be complex and support many usage modes such as multiple bus masters It can support single or burst read writes and can support different bus widths and different peripheral bus widths The general philosophy of the Ethernet AVB Endpoint core has been to implement a PLB interface which is as simple as possible The following features are provided e 32 bit data width e Implements a simple PLB slave e Supports single read writes only no burst or page modes www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Core Interfaces PLB Interface Table 5 9 defines the signals on the PLB bus For detailed information see the IBM PLB specification Shaded rows represent signals not used by this core inputs are ignored and outputs are tied to a constant These signals are synchronous to PLB_c1lk see Clocks and Resets for additional information Table 5 9 PLB Signals PIN Name Direction Description PLB_clk Input Reference clock for the PLB PLB_reset Input Reset for the PLB synchronous to PLB_clk PLB ABus 0 31 input PLB address bus PLB UABus 0 31 Input PLB upper address
164. or the XAvb driver The file provides the constants type definitions and function templates which are required to initialize and run the IEEE802 1A5 Precise Timing Protocol PTP This defines the level 1 device driver for the Ethernet AVB Endpoint core xavb_g c Contains a configuration structure that holds all the configuration values required per single instance of the device driver xavb c Provides the top level function calls for the Ethernet AVB Endpoint level 1 device driver xavb_ptp_packets c Provides the functions which are required for the creation of PTP frames for transmission and for the decode of received PTP frames xavb_ptp_bmca c Provides the functions which are required for the PTP Best Master Clock Algorithm BMCA xavb_rtc_sync c Provides the functions which are required to synchronize the local version of the Real Time Counter RTC when operating as a slave to that of the network clock master xavb_hw h Contains all the constant definitions and the bare minimum of functions function templates which are required for register read write access This defines the low level 0 device driver for the Ethernet AVB Endpoint core xavb_hw c This file partners the xavb_hw h header file and implements the functions for which avb_hw h contained a template Back to Top www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Implementation
165. ound information is provided in this document with regard to the credit based algorithm The remainder of this section describes the idleSlope and sendSlope variables from the perspective of the Ethernet AVB Endpoint core Tx Arbiter Bandwidth Control The Ethernet AVB Endpoint core contains four configuration registers used for setting the cores local definitions of idleSlope and sendSlope The configuration register settings are described in general and then from the point of view of a single example which describes the calculations made to set the register default values This example dedicates up to 75 of the overall bandwidth to be reserved for the AV traffic leaving at least 25 for the Legacy Traffic The calculations described are independent of Ethernet operating speed no re calculation is required when changing between Ethernet speeds of 1 Gbps and 100 Mbps idleSlope The general equation is idleSlopeValue AV percentage 100 x 8192 In this example dedicating up to 75 of the total bandwidth to the AV traffic we obtain idleSlopeValue 75 100 x 8192 6144 The calculated value for the idleSlopeValue should be written directly to the Tx Arbiter Idle Slope Control Register This provides a per byte increment value when relating this to Legacy Ethernet frame transmission sendSlope The general equation is sendSlopeValue 100 AV percentage 100 x 8192 In this example dedicating up to 75 of the
166. project by following the usual steps to import a black box IP See the Xilinx Platform Studio documentation for information After importing the generated netlist the drivers can also be linked into the software application See Software System Integration in Chapter 13 for more information Ethernet AVB Endpoint User Guide www xilinx com 165 UG492 July 23 2010 Chapter 16 Detailed Example Design EDK format g XILINX 166 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Appendix A RIC Time Stamp Accuracy Time Stamp Accuracy The accuracy of the time stamps taken by sampling the Real Time Clock RTC whenever PTP frames are transmitted or received is essential to the Precise Timing Protocol across the network link For this reason the time stamps are performed in hardware Despite this time stamp inaccuracies can be introduced from two sources e RTC Real Time Instantaneous Error e RTC Sampling Error Following this discussion we then consider the Accuracy Resulting from the Combined Errors RTC Real Time Instantaneous Error Figure A 1 illustrates a RTC implementation which uses a 40 ns clock period as its clock source this is worst case Therefore the controlled frequency RTC will only be updated every 40ns Because the concept of a RTC is a continuous measurement of time the implementation of the RTC illustrated in Figure A 1 is only accurate im
167. r automatic integration into Xilinx Platform Studio drivers avb v2 04 a examples An application example using the low level driver files C3 drivers avb v2 04 a src Low level driver source C files Ethernet AVB Endpoint User Guide www xilinx com 159 UG492 July 23 2010 Chapter 16 Detailed Example Design EDK format XILINX Directory and File Contents The core directories and their associated files are defined in the following tables lt project directory gt The project directory contains all the CORE Generator software project files Table 16 1 Project Directory Name Description lt project_dir gt lt component_name gt ngc Top level netlist This is instantiated by the Verilog or VHDL example design lt component_name gt xco Log file that records the settings used to generate a core An XCO file is generated by the CORE Generator software for each core that it creates in the current project directory An XCO file can also be used as an input to the CORE Generator software lt component_name gt _flist txt List of files delivered with the core Back to Top lt project directory gt lt component name gt The lt component name gt directory contains the release notes file provided with the core which may include last minute changes and updates Table 16 2 Component Name Directory Name Description lt project_dir gt lt component_name gt eth_avb_endpoint_readme
168. r further information Ethernet AVB Endpoint User Guide www xilinx com 45 UG492 July 23 2010 Chapter 5 Core Architecture XILINX Software Drivers Software Drivers are delivered with the Ethernet AVB Endpoint core These drivers provide functions which utilize the dedicated hardware within the core for the PTP IEEE P802 1AS specification Functions include e The Best Master Clock Algorithm BMCA to determine whether the core should operate in master clock or slave clock mode e PTP Clock Master functions e PTP Clock Slave functions which accurately synchronize the local Real Time Clock RTC to match that of the network clock master If the core is acting as clock master then the software drivers delivered with the core will periodically sample the current value of the RTC and transmit this value to every device on the network using the P802 1 defined PTP packets The hardware Tx Time Stamp logic using the mechanism defined in P802 1AS ensures the accuracy of this RTC sample mechanism If the core is acting as a clock slave then the local RTC will be closely matched to the value and frequency of the network clock master This is achieved in part by receiving the PTP frames transmitted across the network by the clock master and containing the masters sampled RTC value The PTP mechanism will also track the total routing delay across the network between the clock master and itself The software drivers use this data in
169. r to wrap around in our lifetime The RTC is summarized in Figure 8 1 IEEE802 1AS Real Time Counter RTC Seconds field 48 bits unsigned Nano Seconds field 32 bits unsigned ee no quoq counts from 0 until fully saturated counts from 0 to 1 x 10 1 then wraps around to 0 then resets to 0 Figure 8 1 Real Time Counter RTC Ethernet AVB Endpoint User Guide www xilinx com 75 UG492 July 23 2010 76 Chapter 8 Real Time Clock and Time Stamping g XILINX Conceptually the RTC is not related to the frequency of the clock used to increment it A configuration register within the core provides a configurable increment rate for this counter this increment register RTC Increment Value Control Register is for this reason simply programmed with the value of the RTC Reference clock period which is being used to increment the RTC The resolution of this increment register is very fine in units of 1 1048576 1 220 fraction of one nanosecond Therefore the RTC increment rate can be adjusted to a very fine degree of accuracy This provides the following features The RTC can be incremented from any available clock frequency that is greater than the AVB standards defined minimum of 25 MHz However the faster the frequency of the clock the smaller will be the step increment and the smoother will be the overall RTC increment rate Xilinx recommends clocking the RTC logic at 125 MHz because this is a readily available clo
170. rame Should an illegally oversized PTP frame be received the first 252 bytes will be captured and stored other bytes will be lost e The top four addresses of each buffer from address OxFC to OxFF are reserved for a timestamp field At the beginning of PTP frame reception the Time Stamping Logic will sample the Real Time Clock Following the end of PTP frame reception this captured timestamp will automatically be written into this location to accompany the frame for which it was taken Following reset the first received PTP frame will be written into Buffer Number 0 The next subsequent received PTP frame will be written into the next available buffer in this case number 1 This process continues with buffer number 2 3 then 4 and so forth being used After receiving the 16th PTP frame which would have been stored into buffer number 15 the count will be reset and then buffer number 0 will be overwritten with the next received PTP frame For this reason at any one time the Rx PTP Packet Buffer is capable of storing the most recently received sixteen PTP frames Following the completion of PTP frame reception a dedicated interrupt signal interrupt_ptp_rx will be generated by the core On the assertion of the interrupt the captured timestamp will already be available in the upper four bytes of the buffer and the rx_packet field of the Rx PTP Packet Control Register will indicate the most recently filled Buffer Nu
171. rame should be discarded by the MAC client either the frame contained an error or it was intended for the PTP or legacy traffic channel Tri Mode Ethernet MAC Client Interface Table 5 6 Table 5 7 and Table 5 8 list the ports of the core which connect directly to the port signals of the Tri Mode Ethernet MAC core which are identically named For detailed information about the Tri Mode Ethernet MAC ports see the Tri Mode Ethernet MAC User Guide UG138 MAC Transmitter Interface These signals connect directly to the identically named Tri Mode Ethernet MAC signals and are synchronous to tx c1k Table 5 6 Tri Mode Ethernet MAC Transmitter Interface Signal Direction Description tx data 7 0 Output Frame data to be transmitted is supplied on this port tx data valid Output A data valid control signal for data on the tx data 7 0 port tx underrun Output Asserted to force the MAC to corrupt the current frame tx ack Input Handshaking signal asserted when the current data on tx data 7 0 has been accepted by the MAC www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Core Interfaces MAC Receiver Interface These signals connect directly to the identically named Tri Mode Ethernet MAC signals and are synchronous to rx c1lk Table 5 7 Tri Mode Ethernet MAC Receiver Interface Signal Direction Description rx data 7 0 Input Frame data received is supplie
172. rent RTC Value Registers Table 10 10 describes the nanoseconds field value register for the nanoseconds field of the Real Time Clock When read this will return the latest value of the counter www xilinx com 95 Chapter 10 Configuration and Status 96 XILINX This register and the registers defined in Table 10 11 and in Table 10 12 are linked When this nanoseconds value register is read the entire RTC including the seconds field is sampled Table 10 10 Current RTC Nanoseconds Value PLB_base_address 0x2814 Bit no Default Access Description 29 0 0 RO Current Value of the synchronized RTC nanoseconds field Note A read from this register samples the entire RTC counter synchronized so that the Epoch and Seconds field are held static for a subsequent read 31 30 0 RO Unused Table 10 11 describes the lower 32 bits of the seconds value register for the seconds field of the Real Time Clock When read this returns the latest value of the counter This register and the registers defined in Table 10 10 and in Table 10 12 are linked When the nanoseconds value register is read see Table 10 10 the entire RTC is sampled Table 10 11 Current RTC Seconds Field Value bits 31 0 PLB_base_address 0x2818 Bit no Default Access Description 31 0 0 RO Sampled Value of the synchronized RTC Seconds field bits 31 0 Table 10 12 describes the upper 16 bits of the seconds v
173. rol Register This contains a Promiscuous Mode bit which e when enabled allows all frames to be received on the Legacy Rx Traffic I F e when disabled only allows frames to be received on the Legacy Rx Traffic I F that contain a MAC Header that has matched at least one of the eight individual MAC Header Filters Each of the eight MAC Header Filters can be separately configured see MAC Header Filter Configuration As defined in this section each of the eight MAC Header Filters contains two 128 bit wide registers 16 bytes e Match Pattern Register This pattern is compared to the initial 128 bits received in the Legacy Ethernet frame bit 0 is the first bit within the frame to be received e Match Enable Register Each bit within this register refers to the same bit number within the Match Pattern Register When a bit in the Match Enable Register is set to logic 1 the same bit number within the Match Pattern Register is compared with the respective bit in the received frame and must match if the overall MAC Header Filter is to obtain a match logic 0 the same bit number within the Match Pattern Register is not compared This effectively turns the respective bit in the Match Pattern Register into a don t care bit the overall MAC Header Filter is capable of obtaining an overall match even if this bit did not compare The overall result of the Match Pattern Register and Match Enable Register is to provide a highly con
174. s made to the Software Reset Register Ethernet AVB Endpoint User Guide www xilinx com 47 UG492 July 23 2010 Chapter 5 Core Architecture XILINX Legacy Traffic Interface Legacy Traffic Transmitter Path Signals Table 5 2 defines the core client side legacy traffic transmitter signals These signals are used to transmit data from the legacy client logic into the core All signals are synchronous to the MAC transmitter clock tx c1k which must be qualified by the corresponding clock enable tx clk en see Clocks and Resets Table 5 2 Legacy Traffic Signals Transmitter Path Signal Direction Description legacy tx data 7 0 Input Frame data to be transmitted is supplied on this port legacy tx data valid Input A data valid control signal for data on the legacy tx data 7 0 port legacy tx underrun Input Asserted by the client to force the MAC to corrupt the current frame legacy tx ack Output Handshaking signal asserted when the current data on legacy tx data 7 0 has been accepted Legacy Traffic Receiver Path Signals Table 5 3 defines the core client side legacy traffic receiver signals These signals are used by the core to transfer data to the client All signals are synchronous to the MAC receiver clock xx c1k which must be qualified by the corresponding clock enable xx clk en see Clocks and Resets Table 5 3 Legacy Traffic Signals Receiver Path Signa
175. s the actual time stamp sampling position that is used by the core Time stamps are taken after the MAC frame SFD is seen not on the GMII but on the MAC Client I F The time stamping logic is deliberately designed this way for the following reasons 1 When the Ethernet AVB Endpoint core is to be connected to the Embedded Tri Mode Ethernet MAC the GMII is not always available to the FPGA fabric logic specifically when used with a 1000BASE X or SGMII physical interface the GMII exists only as an internal connection within the embedded block Therefore by sampling on the client interface we enable the Ethernet AVB Endpoint core to be connected to ANY Xilinx Tri Mode MAC used in ANY configuration 2 Sampling on the MAC Client I F provides the Ethernet AVB Endpoint core with the required time stamp exactly when it is needed Sampling on the GMII would require the use of sideband Time stamp Value FIFOs there may be more than a single MAC frame present in the pipeline stages of the MAC transmitter or receiver So by sampling on the MAC Client I F we are also able to reduce the need for extra FIFO logic 80 www Xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX IEEE1722 Real Time Clock Format Because the Xilinx Tri Mode Ethernet MACS have a known fixed latency the time stamps taken can easily be translated into the equivalent GMII position to comply with the standard This is performed in the software drivers wher
176. s to obtain a time stamp across an asynchronous clock boundary The simplest method is to simply pass a toggle signal from the Tx Rx domain into the RTC reference clock domain whenever a time stamp is required This method should only result in an uncertainty of one cycle the logic is illustrated in Figure A 2 synchronisation pair p 5 Take RTC Sample RTC Reference Clock rtc clk clock boundary Figure A 2 RTC Sampling Logic In Figure A 2 the Sample Timestamp signal is generated whenever the Tx Rx time stamp position is detected see Time Stamp Sampling Position of MAC Frames From this a toggle signal is generated as illustrated and this is passed across the clock domain from Tx Rx MAC clock to the RIC reference clock domain When in the RTC clock domain the toggle signal is re clocked using the two synchronization flip flops illustrated After this an edge detection circuit is used to determine that the RTC should be sampled The single clock period of uncertainty arises from the behavior of the first synchronization flip flop Figure A 3 illustrates that the rising edge of the toggle signal can occur very close to the clock edge of the RTC reference clock It is possible that the setup timing of this flip flop could be violated resulting in uncertainty as to whether a logic 0 or a logic 1 will be sampled If the flip flop samples logic 1 the result is Timing Case 1 if the flip flop
177. samples logic 0 Timing Case 2 results The overall result of this is to obtain a single Reference Clock Period of uncertainty in the captured time stamp value Ethernet AVB Endpoint User Guide www xilinx com 169 UG492 July 23 2010 Appendix A RTC Time Stamp Accuracy XILINX TIMING CASE 1 MAC Tx Rx clock ee toggle clock boundary RTC Reference Clock Qo Q1 Q2 Take RTC Sample A Sanhple TIMING CASE 2 MAC Tx Rx clock toggle RTC Reference Clock Qo Q1 Q2 Take RTC Sample Sampling uncertainty Figure A 3 Sampling Position Uncertainty 170 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Time Stamp Accuracy Accuracy Resulting from the Combined Errors The section RTC Real Time Instantaneous Error describes how a maximum error of one RTC reference clock period can result as a consequence of the RTC itself The section RTC Sampling Error describes how the position of the time stamp request as observed in the RTC reference clock domain can result in one RTC reference clock period of uncertainty Figure A 4 attempts to illustrate the result of the combination of these two types of error Again the worst case clock period of 40 ns is illustrated 40 80 120 160 200 240 Time ns RTC Error ns g 8 8g g c 3 c3 3 D a gz 9 E a ps o o 8 E 8g J l 8 e 0 9 o os 2 s l I8
178. sly across consecutive Ethernet frames The Ethernet Frame Stimulus block is designed to produce frames at full line rate to fully stress the core Ethernet Frame Checker The following files describe the Ethernet Frame Checker logic VHDL project dir component name example design rx frame checker vhd Verilog project dir component name example design rx frame checker v This module contains the logic to check a received Ethernet frame against expected parameters The MAC header fields of this expected frame are defined by generics Destination Address Source Address Length Type the VLAN field is optional Additionally the expected length of the Ethernet frame can also be set using a parameter The data field of the frame is expected to consist of a simple 8 bit binary counter which continues seamlessly across consecutive Ethernet frames This logic is designed to check against the frames generated by the tx frame stimulus module identical parameters must be passed into both modules to obtain a match Loopback Module The following files describe the Loopback module VHDL project dir component name example design temac loopback shim vhd Verilog project dir component name example design temac loopback shim v This logic implements a simple logic shim to provide a frame loopback function at the MAC client Interface This logic does NOT implement a MAC and should be replaced with a real MAC in any real
179. ss If read always return 0 7 1 0 RO Unused 11 8 0 RO rx_packet Indicates the number block RAM bin position of the most recently received PTP packet 31 12 0 RO Unused Note A read or a write to this register clears the interrupt_ptp_rx interrupt asserted after each successful PTP packet reception Rx Filtering Control Register Table 10 3 defines the associated control register of the Rx Splitter The Rx path is capable of identifying the AV packets using configurable VLAN priority Table 10 3 Rx Filtering Control Register PLB base address 0x2008 Bit no 2 0 Default 3 Access R W Description VLAN Priority A If a tagged packet is received with a VLAN priority field matching either of the Priority A or B values then the packet will be considered as an AV frame it will be passed to the AV I F Otherwise it will be passed to the Legacy I F 7 3 RO Unused 10 8 R W VLAN Priority B If a tagged packet is received with a VLAN priority field matching either of the Priority A or B values then the packet will be considered as an AV frame it will be passed to the AV I F Otherwise it will be passed to the Legacy I F 15 11 RO Unused 16 R W Promiscuous Mode for the Legacy MAC Header Filters If this bit is set to 1 the MAC Header Filter is set to operate in promiscuous mode All frames will be passed to the Rx Legacy Traffic I F If set
180. ssing constraints for MAC Host I F Logic INST top generic host if inst wr toggle TNM FFS wr toggle INST top generic host if inst resync write toggle data sync TNM FFS resync write toggle TIMESPEC ts wr toggle FROM wr toggle TO resync write toggle 8 ns DATAPATHONLY INST top generic host if inst rd toggle TNM FFS rd toggle INST top generic host if inst resync read toggle data sync TNM FFS resync read toggle TIMESPEC ts rd toggle FROM rd toggle TO resync read toggle 8 ns DATAPATHONLY INST top include plb plb intf inst Bus2IP Addr TNM FFS cpu bus INST top include plb plb intf inst Bus2IP Data TNM FFS cpu bus INST top include plb plb intf inst Bus2IP BE TNM FFS cpu bus INST top generic host if inst host address bitl10 TNM FFS host sample INST top generic host if inst host address TNM FFS host sample INST top generic host if inst stats upper word TNM FFS host sample INST top generic host if inst host wr data TNM FFS host sample INST top generic host if inst host be TNM FFS host sample TIMESPEC ts host sample FROM cpu bus TO host sample 8 ns DATAPATHONLY Ethernet AVB Endpoint User Guide www xilinx com 109 UG492 July 23 2010 Chapter 11 Constraining the Core g XILINX INST top generic_host_if_inst host_toggle_reg2 TNM FFS host_togg
181. ssor Software Specification mss file and the Microprocessor Hardware Specification mhs files When the core has been generated in the Standard CORE Generator format see Core Delivery Format the value of the base address used for the hardware instance in the mhs file must match the value of the PLB base address which was selected during the Ethernet AVB Endpoint core generation When the core has been generated in the EDK pcore format the value of the PLB base address will be automatically configured by XPS Interrupt Service Routine Connections The Ethernet AVB Endpoint core creates three interrupt output signals interrupt_ptp_timer interrupt_ptp_txand interrupt_ptp_rx Itis recommended that these be connected to the interrupt input ports of axps_intc core this is a standard interrupt controller core complete with associated software drivers which are available with the EDK In this version of the Ethernet AVB Endpoint core only the interrupt_ptp_timer and interrupt_ptp_rx interrupts are required by the software drivers The functionality provided by the interrupt_ptp_tx interrupt signal as used in previous software driver versions has been replaced with polling functionality to reduce the overall interrupt driver overhead The two hardware interrupt signals required need to be connected to the following interrupt routine service functions e interrupt ptp timer needs to call the function XAvb_PtpTimerInterruptHa
182. ta read from the Ethernet Statistics core connect to the host rd data 31 0 signal of the Ethernet Statistics core if present If the statistics core is not used then connect to logic 0 host miim sel Output When asserted the MAC will access the MDIO port when not asserted the MAC will access configuration registers host req Output Used to initiate a transaction onto the MDIO Ethernet AVB Endpoint User Guide www xilinx com 51 UG492 July 23 2010 Chapter 5 Core Architecture g XILINX 52 Table 5 8 Tri Mode Ethernet MAC Host Interface Configuration Status Signal Direction Description host_miim_rdy Input When high the MAC has completed its MDIO transaction host_stats_lsw_rdy Input Signal provided by the Ethernet Statistics core to indicate that the lower 32 bits of the statistic counter value is present on the host_rd_data_stats 31 0 port If the statistics core is not used then connect to logic 0 host_stats_msw_rdy Input Signal provided by the Ethernet Statistics core to indicate that the upper 32 bits of the statistic counter value is present on the host_rd_data_stats 31 0 port If the statistics core is not used then connect to logic 0 Processor Local Bus PLB Interface The Processor Local Bus PLB on the Ethernet Audio Video core is designed to be integrated directly in the Xilinx Embedded Development Kit EDK where it can be easily integrated and c
183. ted are then looped back and received at the corresponding AV and Legacy receive client interfaces e Two instances of an Ethernet Frame Checker block configured differently and connected as follows One instance is connected to the AV receiver interface configured to expect the VLAN frames produced by the AV Frame Stimulus block A second instance is connected to the Legacy receiver interface configured to expect the standard Ethernet frames produced by the Legacy Frame Stimulus block e APLB Module that connects to the PLB interface of the core and contains simple state machines to perform initialization of configuration and interrupt management state machines Ethernet Frame Stimulus The following files describe the Ethernet Frame Stimulus logic VHDL project dir component name example design tx frame stimulus vhd Verilog project dir component name example design tx frame stimulus v This module contains the logic to produce an Ethernet test frame The MAC header fields of this frame are defined by generics Destination Address Source Address Length Type the VLAN field is optional Additionally the length of the Ethernet frame can also be set using a generic Ethernet AVB Endpoint User Guide www xilinx com 153 UG492 July 23 2010 154 Chapter 15 Detailed Example Design Standard Format g XILINX The data field of the frame is designed to create a simple 8 bit binary counter that continues seamles
184. tion can be found in the ISE Design Suite Installation Licensing and Release Notes document www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 3 Overview of Ethernet Audio Video Bridging Figure 3 1 illustrates a potential home network consisting of wired ethernet and wireless components which utilize the technology being defined by the IEEE802 1 Audio Video Bridging Task Group This illustrates potential audio video talkers for example a Cable or Satellite Content Provider or home MP3 player and a number of potential listeners for example TV sets which may exist in several rooms In addition users of the various household PCs may be surfing the internet It is important to note that all of this data is being transferred across the single home network backbone Terrestrial Broadcast Satellite gt EI J e a il Jr dcos MN g Home Network wired DVD player Broadband Figure 3 1 Example AVB Home Network Ethernet AVB Endpoint User Guide www xilinx com UG492 July 23 2010 Chapter 3 Overview of Ethernet Audio Video Bridging g XILINX To understand the requirements of this network we must differentiate between certain types of data e Audio and Video streaming data referred to in this document as AV traffic Requires a good quality of service to avoid for example TV picture breakup and must be transferred reliably and wit
185. to operate the Ethernet AVB Endpoint software in their application System Specific Defines in xavb hw h This header file assumes that the rtc c1k input is connected to a 125 MHz clock source If a clock with a different frequency is connected to this input then the following fdefine should be edited so that the increment written to the RTC Increment Value Control Register matches the RTC clock define XAVB RTC INCREMENT NOMINAL RATE 0x00800000 System Specific Defines in xavb h The timestamp reference plane is defined by IEEE P802 1AS to be at the PHY and since the Ethernet AVB Endpoint captures the timestamp when the first symbol following the SFD is seen at the Ethernet MAC Client interface the software needs to know the fixed latency values through the MAC and PHY The following two defines should be edited to store the values in nanoseconds of the ingress and egress delays through the PHY that is being used in the system The values are set to 0 by default define XAVB TX MAC2PHY LATENCY IN NS 0 define XAVB RX PHY2MAC LATENCY IN NS 0 134 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Software System Integration You should also update the following define if there is a known asymmetry in the propagation delay on the link This define models the per port global variable delayAsymmetry as defined in IEEE P802 1AS and should be edited based on the description g
186. total bandwidth to the AV traffic we obtain sendSlopeValue 100 75 100 x 8192 2048 The calculated value for the sendSlopeValue should be written directly to the Tx Arbiter Send Slope Control Register This provides a per byte decrement value when relating this to AV Ethernet frame transmission Ethernet AVB Endpoint User Guide www xilinx com 63 UG492 July 23 2010 64 Chapter 6 Ethernet AVB Endpoint Transmission XILINX hiLimit The general equation is hiLimitValue 2000 x idleSlopeValue In this general equation the value of 2000 is obtained from the maximum number of bytes which may be present in legacy frames an Envelope frame as defined in IEEE802 3 can be of size 2000 bytes In this example dedicating up to 75 of the total bandwidth to the AV traffic we obtain hiLimitValue 2000 x 6144 12288000 loLimit The general equation is loLimitValue 1518 x sendSlopeValue In this general equation the value of 1518 is obtained from the maximum number of bytes which may be present in AV frames In this example dedicating up to 75 of the total bandwidth to the AV traffic we obtain loLimitValue 1518 x 2048 3108864 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 7 Ethernet AVB Endpoint Reception Rx Splitter The input to the Rx splitter see Figure 5 1 is connected directly to the client Receive Rx interface of the connected Ethernet
187. ub system Ethernet AVB Endpoint User Guide www xilinx com 125 UG492 July 23 2010 Chapter 12 System Integration XILINX Figure 12 8 illustrates the connection of the core to an embedded processor subsystem MicroBlaze processor is illustrated Observe that e The PLB can be shared across all peripherals as illustrated e The Interrupt Signals should be connected to the inputs of an interrupt controller module for example the xps_intc core provided with the EDK e The Legacy Traffic Interface and Tri Mode Ethernet MAC Client Interface of the Ethernet AVB Endpoint core connect directly to the xps_ll_temac This enables the xps ll temac to source and sink all legacy frame data This legacy data is transferred to and from the processor domain over a LocalLink interface to a Multi Port Memory Controller MPMC this contains scatter gather DMA functionality and access to all processor memory such as external SDRAM not illustrated This allows software applications running on the processor to easily assemble and disassemble legacy ethernet packets e The AV Traffic Interface remains available for custom logic This will be able to take priority over the processors legacy traffic as defined by the P802 1Qav component of the AVB specification Note that the embedded processor should be configured to use the software drivers provided with the core see Chapter 13 Software Drivers Ethernet AVB Endp
188. ue written into this register will be loaded into the 8k clock generation circuit at the same instant as the offset is applied to the RTC counter logic following a write to the nanosecond offset register defined in Table 10 6 As an example of applying a phase offset writing the value of the decimal 62500 half of an 8 KHz clock period to this register would invert the c1k8k signal with respect to a value of 0 This register can therefore provide fine grained phase alignment of these signals to a 1 ns resolution Table 10 14 RTC Phase Adjustment Register PLB base address 0x2824 Bit no Default Access Description 29 0 0 R W _ ns value relating to the phase offset for the clk8k RTC derived timing signal 31 30 0 RO Unused Software Reset Register Table 10 15 describes the Software Reset Register This register contains unique bits which can be written to in order to request the reset of a particular section of logic from within the Ethernet AVB Endpoint core A single bit can be written to in a single CPU transaction in order to reset just that particular function several to all bits can be written to in a single CDU transaction in order to reset several to all of the available reset functions Table 10 15 Software Reset Register Address at PLB base address 0x2828 Bit Number Default Access Description 0 0 WO Transmitter path reset When written with a 1 forces the entire transmitter path of
189. uffer where it is accessible along side the content of the PTP frame that was just transmitted By the time the Tx PTP buffer raises its dedicated interrupt this time stamp is available for the microprocessor to read This sampling of the RTC is performed in hardware for accuracy See Chapter 9 Precise Timing Protocol Packet Buffers for further information Rx PTP Packet Buffers Received PTP Packets will be written to the Rx PTP Packet Buffer by the Rx Splitter This buffer is capable of storing up to 16 separate PTP frames Whenever a PTP packet is received a dedicated interrupt will be generated The contents of the stored packets can be read via the PLB The oldest stored frame will always be overwritten by a new frame reception and so a configuration register within the core will contain a pointer to the most recently stored packet The software drivers provided with the core using the PLB and dedicated interrupt will use this interface to decode and then act on the received PTP packet information See Chapter 9 Precise Timing Protocol Packet Buffers for further information Rx Time Stamp When a PTP packet is received a sample of the current nanosecond value of the RTC is taken This timestamp value is written into a dedicated field within the Rx PTP Packet Buffer where it is accessible along side the PTP frame that was just received By the time the Rx PTP buffer raises its dedicated interrupt this time stamp is availa
190. uffer provides a maximum of 244 bytes more than that required for the largest PTP frame Each PTP frame holds the entire MAC frame with the exception of any required MAC padding or CRC these will automatically be inserted by the TEMAC from the Destination Address field onwards e The top four addresses of each buffer from address OxFC to OxFF are reserved for a time stamp field At the beginning of PTP frame transmission from any of the eight buffers the Time Stamping Logic will sample the Real Time Clock Following the end of PTP frame transmission this captured timestamp will automatically be written into this location to accompany the frame for which it was taken Ethernet AVB Endpoint User Guide www xilinx com 83 UG492 July 23 2010 XILINX Chapter 9 Precise Timing Protocol Packet Buffers Despite the logic and formatting of each individual PTP buffer being identical the block RAM is pre initialized at device configuration to hold template copies of each of the PTP frames as indicated in Figure 9 1 This shows that the first seven memory segments are in use PTP Buffer number 8 is currently unused and could therefore be used by proprietary applications The Tx PTP Packet Control Register is defined for the purpose of requesting which of the eight Tx PTP Buffers are to be transmitted It is possible to request more than a single frame at one time indeed it is possible to request all 8 When more than one fram
191. ument title Document number Page number s to which your comments refer Explanation of your comments Ethernet AVB Endpoint User Guide www xilinx com 25 UG492 July 23 2010 Chapter 1 Introduction 26 www xilinx com XILINX Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 2 Licensing the Core This chapter provides instructions for obtaining a license key for the Ethernet AVB Endpoint core which you must do before using the core in your designs The Ethernet AVB Endpoint core is provided under the terms of the Xilinx Core Site License Agreement Before you Begin This chapter assumes that you have installed the required Xilinx ISE Design Suite version following the instructions provided by the Xilinx ISE Installation Licensing and Release Notes Guide www xilinx com support documentation dt_ise htm Detailed software requirements can be found on the product web page for this core www xilinx com products ipcenter DO DI EAVB EPT htm License Options The Ethernet AVB Endpoint core provides three licensing options After installing the required ISE Design Suite version choose a license option Simulation Only The Simulation Only Evaluation license key is provided with the ISE CORE Generator tool This key lets you assess core functionality with either the example design provided with the Ethernet AVB Endpoint core or alongside your own design and allows you to demonstrat
192. vers v2 04 a A directory containing the software device drivers for the Ethernet AVB Endpoint core and associated supporting files drivers avb v2 04 a data The driver data directory contains the data files for automatic generation of parameter specific files when integrated into Platform Studio Table 15 10 Driver Data Directory Name Description project dir component name drivers avb v2 04 data avb v2 1 0 mdd Current MDD file used including the version of the tools interface avb v2 1 O tcl Used to provide design rule checks within Xilinx Platform Studio Back to Top drivers avb v2 04 a examples The driver examples directory contains an application example using the low level driver files Table 15 11 Driver Example Directory Name Description project dir2 component name drivers avb v2 04 examples xavb example c Contains a very basic example design of using the AVB driver Back to Top Ethernet AVB Endpoint User Guide www xilinx com 149 UG492 July 23 2010 Chapter 15 Detailed Example Design Standard Format drivers avb v2 04 a src XILINX The driver source src directory contains the low level driver source C files Table 15 12 Driver Source Directory Name Description project dir component name drivers avb v2 04 src Makefile Makefile to compile the drivers used by Platform studio xavb h Main header file f
193. vide examples Ethernet AVB Endpoint User Guide UG492 July 23 2010 www xilinx com 103 Chapter 11 Constraining the Core XILINX PERIOD Constraints for Clock Nets PLB_clk The clock provided to PLB c1k must be constrained to the appropriate frequency Note the frequency range of the embedded processor to which this bus is connected For example the maximum clock speed of the MicroBlaze processor is 100 MHz The following UCF syntax shows a 100 MHz period constraint being applied to the PLB clk signal NET plb clk TNM NET plb clk TIMEGRP plb clock plp elk TIMESPEC TS plb clock PERIOD plb clock 10000 ps HIGH 50 host clk The clock provided to host c1k must be constrained to the desired Management Interface operating frequency of the Tri Mode Ethernet MAC If host c1kis connected to the same clock source as any other Ethernet AVB Endpoint input clock for example PLB_clk or ref_c1k then this constraint is unnecessary and can be removed The maximum supported frequency of host c1k as specified by the Tri Mode Ethernet MAC core is 125 MHz The following UCF syntax shows a 125 MHz period constraint being applied to host clk NET host clk TNM NET host clk TIMEGRP host clock host clk TIMESPEC TS host clock PERIOD host clock 8000 ps HIGH 50 tx_clk The interface clock of the Ethernet MACs transmitter
194. w xilinx com 31 UG492 July 23 2010 Chapter 3 Overview of Ethernet Audio Video Bridging g XILINX P802 1Qat This specification defines a Stream Reservation Protocol SRP which must be used over the AVB network Every listener that intends to receive audio video AV traffic from a talker must make a request to reserve that bandwidth Both the talker and every bridge device that exists between the talker and the listener has the right to decline this request Only if each device is capable of routing the new AV traffic stream without violating the 75 total bandwidth restriction when taking into account previously granted bandwidth commitments will the bandwidth request be successful However after granted this audio video stream is reliably routed across the network until the reservation is removed Note No hardware components are required for the P802 1Qat specification because this is a pure software task This software is not provided by the Ethernet AVB Endpoint core Typical Implementation Xilinx Device Audio Video IEEE 1722 AV AVB network Sources Packet traffic Sinks Manager Tri Mode Ethernet Endpoint MAC LogiCORE LogiCORE Ethernet PHY traffic Embedded Processor System with TCP IP stack PLB management Figure 3 2 Example Ethernet AVB Endpoint System Figure 3 2 illustrates a typical implementation for the Ethernet AVB Endpoint core Endpoint refers to a talker or listener dev
195. y Traffic Interface oos rem eR yp v EE RE XR EY 48 AV Traffic Interface 2 0 0 ccc ene e e 49 Tri Mode Ethernet MAC Client Interface 0 0 0 0 ccc ete nee 50 Processor Local Bus PLB Interface 0 0 eee cece teens 52 Interrupt Signals sce v2 er Re yeas Ge eed ev Re e EE EEE E AES TREA oe Ce 55 PIP Signals 1202p sis seca er besser ee ba ker seed eee 56 Chapter 6 Ethernet AVB Endpoint Transmission IX Lebdcy Traffic UP esie adn 55155 i i tener ceste hie ee epa 57 Error Free Legacy Frame Transmission eeeeeeee 58 Errored Legacy Frame Transmission s ee 59 TAV Trate UE eene t esta Ee t ao SC on arose Alters 59 TEXAN BCH ERE TRECE TR ENE ENA REA PARVEDES AEEA ESAE ERE 61 Chapter 7 Ethernet AVB Endpoint Reception R Splitter oii Bape atts hc wen ER E e a a ae ees 65 Bx Legacy Traffic UP 4e bebo 4243 eras Celo EEEE c ba ei e ee p et aa 65 Error Free Legacy Frame Reception 0 cece eee cece 66 Errored Legacy Frame Reception ssse en 67 Legacy MAC Header Filters en 67 Rx AV Traffic UE sob RECUERDE ECRI4 CERE bns 73 Error Free AV Traffic Reception 0 n 73 Errored AV Traffic Reception 0 0 0 6 n 74 www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Chapter 8 Real Time Clock and Time Stamping Real Time Clock iR Pe Ub I IRNA pig EENEN EAN 75 RIC Implementation ee rece eene oe ode a we e reds 77 Clock Outputs Based on the
196. y rx data valid J legacy rx frame good L legacy_rx_frame_bad legacy_rx_filter_match 0 legacy_rx_filter_match 1 legacy_rx_filter_match 2 legacy_rx_filter_match 3 J legacy_rx_filter_match 4 legacy_rx_filter_match 5 legacy rx filter match 6 legacy rx filter match 7 Figure 7 3 Normal Frame Reception Address Filter Match Figure 7 3 illustrates Legacy frame reception for an error free frame in which at least one of the eight individual MAC Header Filters obtained a match filter number 3 is illustrated as having obtained the match in this example Note the following e Each of the eight individual MAC Header Filters has a corresponding bit within the legacy rx filter match 7 0 bus If the corresponding MAC Header Filter obtains a match the relevant bit will be asserted This will be fully aligned with the legacy rx data valid signal during frame reception e Every bit within the legacy rx filter match 7 0 bus will be asserted for frame reception in which the Frame Destination Address DA contained a Broadcast Address e Every bit within the legacy rx filter match 7 0 bus will be asserted when the MAC Header Filter is operating in Promiscuous Mode see Rx Filtering Control Register www xilinx com Ethernet AVB Endpoint User Guide UG492 July 23 2010 XILINX Rx Legacy Traffic I F MAC Header Filter Configuration The MAC Header Filters can be enabled or disabled by using the Rx Filtering Cont

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