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Xilinx DS610 User's Manual

1. Bank XC3SD3400A Pin 9916 Bank XC3SD3400A Pin 70616 1 IO L12N 1 U18 O 1 L47N 1 M18 10 1 IO L12P 1 U19 1 L47P 1 10 1 IO L10N 1 u20 1 IO L42N 1 A17 M20 DUAL 1 IO 1 021 vo 1 IO 145 1 M21 0 1 IO L21N 1 u22 0 1 IO L45N 1 M22 0 1 IO L23P 1 023 1 IO L38N 1 A13 M23 DUAL 1 IO L23N 1 VREF 1 024 VREF 1 IP_L36P_1 VREF_1 M24 VREF 1 IP_1 VREF_1 026 1 IO_L35N_1 A11 M25 DUAL 1 IO L17N 1 117 10 1 IO L35P 1 A10 M26 DUAL 1 IO L17P 1 1 IO L55N 1 L17 VO 1 IO L14N 1 T20 O 1 IO L55P 1 0 1 IO L26P 1 A4 123 DUAL 1 IO 153 1 L20 1 IO 126 1 A5 T24 DUAL 1 IO L50P 1 L22 VO 1 IO 127 R17 DUAL 1 IP_L40N_1 L23 INPUT 1 IO L27P 1 A6 R18 DUAL 1 IO L38P 1 A12 124 DUAL 1 IO L22P 1 R19 1 0 1 L57N 1 10 1 122 1 R20 1 0 1 157 1 Ki9 10 1 IO L25P 1 A2 R21 DUAL 1 L53N 1 K20 10 1 IO 125 1 A3 R22 DUAL 1 IO L50N 1 K21 1 IP L28P 1 VREF 1 R23 VREF 1 L46N 1 K22 0 1 IP_L28N_1 R24 INPUT 1 L46P 1 VO 1 IO L29P 1 A8 R25 DUAL 1 IP_L40P_1 24 INPUT 1 IO L29N 1 A9 R26 DUAL 1 IO L41P 1 K25 0 1 IO L34P 1 IRDY1 RH
2. DS610 3 v2 0 July 16 2007 Product Specification www xilinx com Package Type Package Type CS484 FG676 CS484 FG676 Signal Standard Top Bottom Left Right Signal Standard Top Bottom Left Right IOSTANDARD Banks 0 2 Banks 1 3 IOSTANDARD Banks 0 2 Banks 1 3 LVCMOS15 Slow 2 55 55 LVPECL_33 Inputs Only 4 31 31 RSDS_25 22 6 18 18 RSDS_33 27 8 15 TMDS_ 33 27 Em 12 m 10 PPDS 25 22 2 25 25 PPDS 33 27 4 10 10 DIFF HSTL 1 18 8 8 6 6 6 DIFF HSTL 18 2 8 4 DIFF HSTL 18 5 4 12 3 DIFF HSTL z 10 QuietlO 2 70 70 DIFF HSTL m 4 4 40 40 DIFF SSTL18 3 7 6 31 31 DIFF SSTL18 1 ES 1 8 31 DIFF 5512 9 9 12 20 DIFF 55112 1 4 LVCMOS12 Slow 2 40 40 DIFF SSTL3 I 4 5 4 m 25 DIFF 55113 3 3 6 18 Notes Fast 2 31 31 1 standards are supported on I O banks The left and right banks banks 1 and 3 support higher output drive 4 13 current than the top and bottom banks I O banks 0 2 6 9 Similarly true differential output standards such as LVDS _ 8505 PPDS miniLVDS and TMDS are only supported in top QuietlO 2 55 55 or bottom banks I O banks 0 and 2 Refer to UG331 Spartan 3 4 36 Generation FPGA User Guide for additional information 2 The numbers in this table are recommendations that assume 6
3. oe DSP 676 Pinout for Bank XC3SD1800A Pin Name 676 Bank XC3SD1800A Pin 70616 cd 0 IO 101 0 G20 O 0 IO L43N 0 K11 148 0 lo IO L39N O Kig vo 0 L52P O VREF 0 F8 VREF 0 IO L25P O GCLK4 K14 GCLK 7 IO L81N 0 lo O ua L27P 0 GCLK8 F13 GCLK 0 J10 INPUT 0 IO L24N 0 F14 O O 0143 0 4n Vo 110 L20P 0 F15 lO 0 IO 139 _0 J12 0 IO 0 17 O 0 J13 INPUT 0 IO LO2N 0 F19 O 0 IO 125 0 GCLK5 J14 GCLK 5 lo o J15 JIO L48N O E7 O 0 IO J16 Vo 0 IO L37P 0 E10 VO 0 0 J17 VREF EN 0 147 0 H9 Vo 0 12 O 0 0 H10 Vo 0 IO 124 0 E14 O 0 IO 135 0 H12 O 0 IO L20N O VREF 0 E15 VREF 0 H13 INPUT 0 IO L13N 0 E17 O 0 IO L16N 0 H15 PO ENG INPUT 0 IO 108 0 HT Vo 0 IO L10P 0 E21 O 9 HIS p INPUT 110 LAN O D6 lO 0 L52N B G8 DUAL 5 D7 IO LP 0 69 vO 110 L40N O D8 O 0 IO L46P 0 G10 L87N 58 lo 0 IP 0 G11 VREF 5 EH lo 0 IO L35P 0 612 VO 0 IO L32N O VREF 0 D11 VREF 0 L27N 0 GCLK9 GCLK D2 0 IPO SE INPUT 0 IO L30P 0 D13 O 0 IO L16P 0 615 vO 0 IP OIVREF 0 Di4 VREF 0 IO LOBN 0 G17 DS610 4 v2 0 July 16 2007 www
4. both the XC3SD1800A and XC3SD3400A FPGAs There ETT are no pinout differences between the two devices Bank Pin Name Ball Type Table 60 lists all the 5484 package pins They are sorted 0 IO 129 0 4 by bank number and then by name Pairs of pins that 0 IP_O C5 INPUT form a differential I O pair appear together in the table The 0 121 0 C6 UO table also shows the pin number for each pin and the pin type as defined earlier 0 IO L26P 0 Vo An electronic version of this package pinout table and er footprint diagram is available for download from the Xilinx 0 C9 Vo website at http www xilinx com bvdocs publications s3adsp_pin zip 0 IP_O C10 INPUT 0 0 C11 VREF Pinout Table 0 Table 60 Spartan 3A DSP 5484 Pinout 0 IO L14P 0 C13 5 2 0 IO L12N 0 15 0 IO L30N 0 A3 O 0 IO 108 0 C16 I O 0 IO L28N 0 A4 VO 0 IO LO3N O C17 I O 0 IO L25N 0 A5 0 IO 102 O VREF 0 C18 VREF 0 10 L25P 0 0 IO LOIN 0 C19 0 IO L24N O VREF 0 7 VREF 0 129 0 05 0 10_L20P_0 GCLK10 GCLK 0 lO 121 0 06 O 0 1O_L18P_0 GCLK6 AQ GCLK 0 lO L26N 0 D7 O 0 10 INPUT 0 IO L22N 0 D9 0 L15N 0 11 0 IO L16N 0 D10 0 0 12 INPUT 0 IO LO9N O D13 I O 0 L11P 0 A13 0 L12P 0 D14 0 IO L10P 0
5. Bank Pin Name S Type Bank Pin Name 587 3 IO L36P 3 V4 yo GND GND H19 GND 3 IO L35N 3 W1 y o GND GND J9 GND 3 lO 137 3 W2 411 3 IO L37P 3 W3 y o GND GND J13 GND 3 IO L35P 3 Y1 415 GND 3 L39P 3 Y2 INPUT GND GND K8 GND 3 VCCO 3 E2 VCCO GND GND K10 GND 3 VCCO 3 J2 VCCO GND GND K12 GND 3 VCCO 3 J5 VCCO GND GND K14 GND 3 VCCO 3 N2 VCCO GND GND L2 GND 3 VCCO 3 P5 VCCO GND GND L7 GND 3 VCCO 3 V2 VCCO GND GND L9 GND GND GND A1 GND GND GND L11 GND GND GND A22 GND GND GND L13 GND GND GND GND GND GND L15 GND GND GND 11 GND GND L19 GND GND GND AA16 GND GND GND M4 GND GND GND AB1 GND GND GND M8 GND GND GND AB22 GND GND GND M10 GND GND GND B7 GND GND GND M12 GND GND GND B12 GND GND GND M14 GND GND GND B16 GND GND GND M16 GND GND GND GND GND GND M21 GND GND GND C20 GND GND GND 08 GND GND GND N11 GND GND GND D11 GND GND GND N13 GND GND GND D16 GND GND GND N15 GND GND GND F6 GND GND GND P8 GND GND GND F17 GND GND GND P10 GND GND GND G2 GND GND GND P12 GND GND GND G4 GND GND GND P14 GND GND GND G9 GND GND GND R4 GND GND GND G11 GND GND GND R7 GND GND GND G13 GND GND GND R9 GND GND GND G15 GND GND GND R11 GND GND GND G21 GND GND GND R13 GND GND GND H7 GND GND GND R15 GND GND GND H8 GND GND GND R16 GND GND GND H10 GND GND GND T2 GND GND GND H12 GND GND GND T8 GND
6. Any Bank Any Bank Bank 0 Bank 0 2 5 of Bourns Vath of Bourns 2 5 2 art Number Number 5 __ 16 4 12 _ CAT16 PT4F4 2 5V 4650 20 500 No Vcco Requirement HH 14091 20 500 1 21000 1 1 6 HH 1 1650 1 1 1 1 08529 3 07 020107 Figure 6 External Termination Resistors for BLVDS 25 I O Standard TMDS_33 Standard Bank 0 and 2 3 3V Bank N 500 500 Leake 3 3V VCCAUX 3 3 2 4 DVI HDMI cable DS529 3 08 020107 Figure 7 External Input Resistors Required for TMDS 33 Standard Device DNA Data Retention Read Endurance Table 14 Device DNA Identifier Memory Characteristics Symbol Description Minimum Units DNA RETENTION Data retention continuous usage 10 Years Number of READ operations or JTAG ISC DNA read operations Unaffected by Read DNA HOLD or SHIFT operations cycles DS610 3 v2 0 July 16 2007 www xilinx com 19 Product Specification Switching Characteristics 5 XILINX Switching Characteristics All Spartan 3A DSP FPGAs ship in two speed grades 4 and the higher performance 5 Switching characteristics in this document are designated as Preview Advance Preliminary or Production as shown in Table 15 Each category is defined as follows Preview These specifications are based on es
7. Table 63 Spartan 3A DSP FG676 Pinout for Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued XC3SD1800A FPGA Continued Bank XC3SD1800A Pin 70616 Bank XC3SD1800A Pin Name FG676 3 IP_LO4P_3 C2 INPUT GND o M GND 3 IO LO2N 3 B1 O GND GND 6 GND 3 IO 102 3 B2 GND T12 GND 3 IP_L66P_3 AE1 INPUT GND GND T14 GND 3 IP_L66N_3 VREF_3 2 VREF GND GND GND 3 IO 165 3 AD1 9 GND T21 GND 3 IO_L65N_3 AD2 GND GND T26 GND 3 IO L60N 3 AC1 GND GND R11 GND 3 IO_L64P_3 AC2 GND GND R13 GND 3 IO L64N 3 AC3 GND GND R15 GND 3 IO 16 3 AB1 9 GND P12 GND 3 IO 155 3 AA2 GND GND P16 GND 3 IO L55N 3 AA3 GND GND P19 GND 3 IP_L58N_3 VREF_3 AAS VREF GND GND P24 GND 3 IP L16P 3 G2 INPUT GND GND N3 GND 3 IP L12P 3 G5 INPUT GND N8 GND 8 IP LO8P 3 D2 INPUT GND GND N11 GND 3 IP L62P 3 AB3 INPUT GND GND N15 GND 3 IP_L58P_3 INPUT GND GND M12 GND 3 108 3 D1 INPUT GND GND M14 GND 3 IP_L62N_3 INPUT GND GND M16 GND 3 IP_L54N_3 Y4 INPUT GND GND L1 GND 3 VCCO 3 5 GND GND 16 GND 3 VCCO_3 T2 GND GND L11 GND 3 GND GND 113 GND 3 VCCO_3 5 GND GND L15 GND 3 12 GND GND 121 GND 3 VCCO_3 L8 GND GND 126 GND 3 VCCO_3 5 GND GND K10 GND 3 VCCO_3
8. Inputs and Signal Standard Inputs Outputs Outputs Vner Vu 0 V SSTL3 I 1 5 Vper 0 75 Veer 0 75 50 1 5 VREF SSTL3_II 1 5 Vngr 0 75 0 75 25 1 5 VREF Differential LVDS_25 0 125 Vicm 0 125 50 1 2 VicM LVDS 33 Vic 0 125 0 125 50 1 2 VicM BLVDS 25 0 125 0 125 1M 0 VicM MINI LVDS 25 0 125 0 125 50 1 2 VicM MINI LVDS 33 0 125 0 125 50 1 2 Vicm LVPECL_25 0 3 0 3 VicM LVPECL 33 Vicm 0 3 0 3 N A N A VicM RSDS 25 Vicm 0 1 Vicm 0 1 50 1 2 VicM RSDS 33 Vicm 0 1 Vicm 0 1 50 1 2 VicM 5 33 Vicm 0 1 Vicm 0 1 50 3 3 VicM PPDS 25 Vicm 0 1 0 1 50 0 8 Vicm PPDS 33 Vicm 0 1 Vicm 0 1 50 0 8 VicM DIFF HSTL 18 0 9 Vaer 0 5 Vper 0 5 50 0 9 VREF DIFF_HSTL_II_18 0 9 Vner 0 5 0 5 50 0 9 VREF DIFF_HSTL_III_18 1 1 Vngr 0 5 0 5 50 1 8 VREF DIFF HSTL 1 0 9 0 5 0 5 50 0 9 VREF DIFF_HSTL_III 0 9 0 5 0 5 50 0 9 VREF DIFF 551118 0 9 Vner 0 5 Vper 0 5 50 0 9 VREF DIFF 551118 Il 0 9 0 5 0 5 50 0 9 VREF DIFF_SSTL2_l 1 25 0 5 0 5 50 1 25 VREF DIFF 55112 1 25 0 5 0 5 50 1 25 VREF DIFF 55113 1 1 5 0 5 0 5 50 1 5 VREF DIFF_SSTL3_II 1 5
9. Date Version Revision 04 02 07 1 0 Initial Xilinx release 05 25 07 1 0 1 Minor edits 06 18 07 1 2 Updated for v1 29 production speed files Noted banking rules in Table 11 and Table 12 Added DIFF_HSTL_I and DIFF_HSTL_III to Table 12 Table 13 and Table 25 Updated TMDS DC characteristics in Table 13 Updated I O Test Method values in Table 25 Added Simultaneously Switching Output limits in Table 27 Updated DSP48A timing symbols descriptions and values in Table 33 Added power on timing in Table 44 Added CCLK specifications for Commercial in Table 45 through Table 47 Updated Slave Parallel timing in Table 50 Updated JTAG specifications in Table 55 07 16 07 2 0 Added Low power options and updated typical values for quiescent current in Table 9 Updated DSP48A timing in Table 33 and Table 34 0 610 3 v2 0 July 16 2007 Product Specification www xilinx com 57 DC and Switching Characteristics 5 58 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification 2 XILINX Spartan 3A DSP FPGA Family Pinout Descriptions DS610 4 v2 0 July 16 2007 Introduction This section describes how the various pins ona Spartan 3A DSP FPGA connect within the supported component packages and provides device specific thermal characteristics For general information on the pin functions and the package characteristics see the Packaging section in UG331 Spartan 3 Generati
10. Test Logic Level Conditions Characteristics IOSTANDARD lo lon VoL Attribute mA mA Min V LVTTL 9 2 2 2 0 4 2 4 4 4 4 6 6 6 8 8 8 12 12 12 16 16 16 24 24 24 LVCMOS339 2 2 2 0 4 0 4 4 4 4 6 6 8 8 8 12 12 12 16 16 16 2400 24 24 LVCMOS259 2 2 2 0 4 Vcco 0 4 4 4 6 6 8 8 8 12 12 12 160 16 16 240 24 24 LVCMOS18 2 2 2 0 45 Vcco 0 45 4 4 4 6 8 8 8 1200 12 12 160 16 16 LVCMOS1599 2 2 2 0 25 0 75 Veco 4 4 4 6 6 6 80 8 8 124 12 12 LVCMOS12 0 2 2 2 0 4 0 4 4 4 4 4 64 6 6 16 www xilinx com Test Logic Level Conditions Characteristics IOSTANDARD VoL Attribute mA MA Min V PCI33_3 5 1 5 0 5 10 90 Veco 66 36 1 5 0 5 10 90 Veco 1 5 0 5 10 Vcco 90 Veco 8 8 0 4 0 4 HSTL_III 4 24 8 0 4 Veco 0 4 HSTL I 18 8 8 0 4 Vcco 0 4 HSTL 18 4 16 16 0 4 0 4 HSTL Ill 18 24 8 0 4 Vcco 0 4 SSTL18 I 6 7 6 7 0 475 Vp 0 475 SSTL18 11 13 4 13 4 0 475 Vrr 0 475 55112 8 1 8 1 0 61 0 61 SSTL2 11 16 2 16 2 0 80 0 80 SSTL3 I 8 8 06 0 6 SSTL3 14 16 16 0 8 0 8 Notes 1 2 The nu
11. VCCO 0 E13 0 IO L11N 0 C20 VCCO 0 E19 0 109 0 c21 VCCO O B5 VCCO 0 105 0 C22 10 VCCO O B11 VCCO 0 106 0 C23 VCCO 0 B16 0 IO L51N 0 VCCO 0 B22 VCCO 0 IO L45N 0 BA O VCCO 0 A7 vcco 0 IO 141 0 VO 1 IO LO1P 1 HDC Y20 DUAL 0 IO L42P 0 B7 O 1 IO LO1N 1 LDC2 21 DUAL 0 IO L38N 0 1 IO L13P 1 O 0 L36N 0 1 L13N 1 VO 0 L33N 0 1 IO L15P 1 y24 O 0 IO L29N 0 B12 1 IO L15N 1 25 O 0 IO L28P 0 GCLK10 GCLK 1 IP 1 Y26 INPUT 0 IO L26P B14 GCLK 1 IO 104 1 W20 0 IO 123 0 B15 1 104 1 21 0 IO L19N 0 B17 1 IO L18P 1 23 1 0 0 IO L18P 0 1 IO 108 1 O 0 IO L15P 0 10 1 LOBN 1 1 0 0 IO 0 B20 VREF 1 SUSPEND V20 PWRMGMT 0 109 0 B21 1 0 1 L10P 1 v21 O 0 IO LO7P 0 B23 1 1 v22 VO 0 IO L51P 0 WO 1 IO L21P 1 v23 O 0 IO L45P 0 A4 10 1 IO L19P 1 v24 O 0 IO L38P 0 A8 10 1 L19N 1 V25 0 IO L36P 0 A9 1 IP 1 VREF 1 26 VREF 84 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout Descriptions Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued
12. Time from the setup of data the or BY input to 1 58 1 88 ns the active transition at the CLK input of the CLB Hold Times Time from the active transition at the CLK input to the 0 00 0 00 ns point where data is last held at the F or G input Time from the active transition CLK input to the 0 00 0 00 ns point where data is last held at the BX or BY input Clock Timing The High pulse width of the CLB s CLK signal 0 63 0 75 ns The Low pulse width the CLK signal 0 63 0 75 ns Frog Toggle frequency for export control 0 770 0 667 MHz Propagation Times The time it takes for data to travel from the CLB s 0 62 0 71 ns G input to the X Y output Set Reset Pulse Width TRPW The minimum allowable pulse width High or Low to 1 33 1 61 ns 5 the CLB s SR input Notes 1 numbers this table are based the operating conditions set forth in Table 7 36 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification 5 XILINX DC and Switching Characteristics Table 29 CLB Distributed RAM Switching Characteristics Speed Grade 5 4 Symbol Description Min Max Min Max Units Clock to Output Times Time from the active edge the CLK input to
13. Notes 1 numbers in this table are based on the operating conditions set forth in Table 7 This means power must be applied to all Veco and lines 2 Power on reset and the clearing of configuration memory occurs during this period 3 This specification applies only to the Master Serial SPI and modes DS610 3 v2 0 July 16 2007 www xilinx com 47 Product Specification DC and Switching Characteristics 5 XILINX Configuration Clock CCLK Characteristics Table 45 Master Mode CCLK Output Period by ConfigRate Option Setting ConfigRate Temperature Symbol Description Setting Range Minimum Maximum Units oie 2 000 power on value Industrial 1 180 ns NE 5 413 5 Industrial 390 ns Tenue ed 207 and ns Industrial 195 ns Tung 7 178 T ns Industrial 168 ns Tine ae 156 usb ns Industrial 147 ns ues ja OMIM 123 ns Industrial 116 ns Tide d 103 167 ns Industrial 97 ns 18 93 ns Industrial 88 ns Tesi S 72 o ns Industrial 68 ns Tes 54 Bi ns Industrial 51 ns jou 55 47 5 Industrial 45 ns EE 44 75 ns Industrial 42 ns 33 anes 36 Bl ns
14. Spartan 3A Spartan 3A DSP Spartan 3A DSP FG676 XC3S1400A XC3S1400A XC3SD1800A XC3SD1800A XC3SD3400A XC3SD3400A FG676 Ball Type Bank Type Bank Type Bank Ball G16 0 0 GND GND G16 G18 N C N C 0 G18 F9 N C N C 0 9 10 0 0 VCCINT F10 F18 N C N C 0 VCCINT F18 E6 N C N C 0 9 0 GND E9 E20 0 0 VCCAUX VCCAUX E20 D5 N C N C 0 05 015 0 0 GND D15 D19 0 0 GND D19 C4 0 0 C4 B24 N C N C IP_O 0 GND GND B24 A5 0 0 GND A5 A7 0 0 VCCO 0 0 7 23 0 0 GND A23 A24 N C N C 0 VCCAUX VCCAUX A24 Y26 IP_L16N_1 1 IP_L16N_1 1 IP_1 1 Y26 W25 IP L16P 1 1 IP L16P 1 1 GND GND W25 W26 IP L20P 1 1 IP L20P 1 1 VCCAUX VCCAUX W26 V26 IP L20N 1 1 IP L20N 1 1 IP 1 VREF 1 1 V26 VREF 1 VREF 1 U25 IP L24P 1 1 IP L24P 1 1 GND GND U25 U26 IP L24N 1 1 IP L24N 1 1 IP 1 VREF 1 1 U26 VREF 1 VREF 1 H23 IP L48P 1 1 IP L48P 1 1 VCCAUX VCCAUX H23 H24 L48N 1 1 L48N 1 1 IP 1 1 H24 H25 L44N 1 1 144 1 1 VCCO 1 1 25 26 IP L44P 1 1 IP 44 1 1 IP 1 VREF 1 1 H26 VREF 1 VREF 1 G25 L52N 1 1 L52N 1 1 1 VREF 1 1 G25 VREF 1 VREF 1 G26 IP L52P 1 1 IP L52P 1 1 VCCAUX VCCAUX G26 B25 IP L65N 1
15. 1 IP L28P 1 VREF 1 R23 VREF 1 IO LO1P t HDC Y20 DUAL 1 IP L28N 1 R24 INPUT 1 IO LO1N 1 LDC2 Y21 DUAL 1 IO L29P 1 A8 R25 DUAL 1 IO L13P 1 Y22 O 1 IO 129 1 A9 R26 DUAL 1 IO L13N 1 Y23 1 IO_L34P_1 IRDY1 RHCLK6 P18 RHCLK 1 IO L15P 1 Y24 1 IO 1 1 RHCLK1 P20 RHCLK 1 IO L15N 1 25 O 1 IO L30P 1 RHCLKO P21 RHCLK 1 L16N 1 Y26 1 IO L37P 1 P22 O 1 104 1 W20 1 IO L33P 1 RHCLK4 P23 RHCLK 1 IO LOAN 1 W21 1 IO L31N 1 TRDYI RHCLK3 P25 RHCLK 1 IO L18P 1 W23 1 IO 1 RHCLK2 P26 RHCLK 1 IO 108 1 V18 1 IO L39N 1 15 N17 DUAL 1 IO LOBN 1 V19 1 IO L39P 1 14 N18 DUAL 1 SUSPEND V20 PWRMGMT 1 L34N 1 RHCLK7 N19 RHCLK 1 IO L10P 1 V21 O 1 IO_L42P_1 A16 N20 DUAL 1 IO L18N 1 22 O 1 L37N 1 N21 Te 1 IO L21P 1 V23 1 IP_L36N_1 N23 INPUT 1 IO 119 1 V24 1 IO 133 1 RHCLK5 N24 RHCLK 1 IO L19N 1 V25 1 IP_L32N_1 25 INPUT 1 IP_L20N_1 VREF_1 V26 VREF 1 IP_L32P_1 26 INPUT 1 IO L12N 1 U18 1 L47N 1 M18 O 1 IO L12P 1 U19 1 147 1 M19 O 1 IO L10N 1 U20 1 IO L42N 1 A17 M20 DUAL 1 IO L14P 1 021 1 IO L45P 1 M21 O 1 IO L21N 1 U22 1 IO L45N 1 M22 Te 1 IO L23P 1 023 1 IO L38N 1 A13 M23 DUAL 1 IO L23N 1 VREF 1 U24 VREF 1 IP L36P 1 VREF 1 M24 VREF 1 IP_L24N_1 VREF_1 026 VREF 1 IO 135 1 A11 M25 DUAL 1 117 1 117 1 IO L35P 1 A10 M26 DUAL 1 IO L17P 1 T18 1 IO L55N 1 L17 O
16. GND GND GND AD24 GND GND GND K17 GND GND GND 5 GND GND GND J24 GND GND GND GND GND GND GND GND GND AC18 GND GND GND H8 GND GND GND AB3 GND GND GND H14 GND GND GND GND GND GND H19 GND GND GND AB20 GND GND GND G2 GND GND GND 1 GND GND GND G5 GND GND GND AA4 GND GND GND G16 GND GND GND AA6 GND GND GND F1 GND GND GND GND GND GND F6 GND GND GND AA16 GND GND GND F11 GND GND GND AA19 GND GND GND F16 GND GND GND AA21 GND GND GND F21 GND GND GND AA26 GND GND GND F26 GND GND GND A1 GND GND GND E9 GND GND GND A5 GND GND GND D2 GND GND GND A6 GND GND GND D15 GND GND GND 11 GND GND GND D19 GND GND GND A16 GND GND GND GND GND GND 21 GND 90 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout Descriptions Table 65 Spartan 3A DSP FG676 Pinout for Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued XC3SD3400A FPGA Continued Bank XC3SD3400A Pin 70616 Bank XC3SD3400A Pin Name FG676 GND GND GND GND A26 GND VC
17. forth in Table 7 and Table 35 Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input For optimal jitter tolerance and faster lock time use the PERIOD attribute Some jitter and duty cycle specifications include 1 of input clock period or 0 01 UI For example the data sheet specifies a maximum jitter 1 of CLKIN period 150 Assume the CLKIN frequency is 100 MHz The equivalent CLKIN period is 10 ns and 196 of 10 ns is 0 1 ns or 100 ps According to the data sheet the maximum jitter is 100 ps 150 ps 250 ps averaged over all steps 5 The typical delay step size is 23 ps 42 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification 5 XILINX DC and Switching Characteristics Digital Frequency Synthesizer DFS Table 37 Recommended Operating Conditions for the DFS Speed Grade 5 4 Symbol Description Min Max Min Max Units Input Frequency Ranges 2 FREQ Frequency for the CLKIN input 0 2 333 0 2 333 MHz Input Clock Jitter Tolerance 3 CLKIN_CYC_JITT_FX_LF Cycle to cycle jitter at the CLKIN gx lt 150 MHz lt 300 300 5 JITT FX HF CLKFX output p gt 150 MHz 150 150 ps PER JITT FX Period jitter at the CLKIN input 1 1 ns Notes 1 DFS specifications apply when either of the
18. LO2N 3 LO2P 3 L29N 0 L21P 0 126 _0 L22P O L16P 0 VEO 0 INPUT Unrestricted INPUT INPUT INPUT vo Vo vo E 10 vo 41 general purpose input pin LO4P_3 Lo8P 3 129 o 121 0 L26N_0 L22N L16N_0 INPUT vo 3 me 3 3 INPUT 131 _0 0 INPUT 9N 0 DUAL Configuration B 0 _ 9 AWARE pins then possible p vo vo vo vo vo vo E 106 3 106 LO1P 3 103 3 103 3 L27P 0 123 0 VREF User I O or input 10 vo vo vo 5 28 voltage reference for bank L11P_3 101 107 3 LO7N_3 123 0 o Vo Vo Vo Vo Vo 5 CLK User I O input or L14P_3 105 106 LtoP 3 L10N clock buffer input _ 5 INPUT INPUT INPUT 5 3 L16P 3 L16N 3 L12P 3 VREF 3 CONFIG Dedicated K 9 vo vo vo vo vo 5 configuration pins L17P_3 L13P_3 L13N_3 L15P_3 SUSPEND pin 9 Vo L x L15N 3 4 5 JTAG Dedicated JTAG S o port pins f M D 8 2 3 L23P 3 10 INPUT INPUT 10 Vo Ground L22N_3 L31P_3 L23N_3 124 124 3 84 10 VO INPUT s 5 Vo L25P 3 L25N 3 3 3 L26P 3 VCCO Output voltage 10 vo vo vo vo supply for bank L28N 128 134 L32N 3 126 3 vo EE 10
19. 0 5 Vner 0 5 50 1 5 VREF Notes 1 Descriptions of the relevant symbols are as follows Vrer The reference voltage for setting the input switching threshold The common mode input voltage Vu Voltage of measurement point on signal transition V Low level test voltage at Input pin High level test voltage at Input pin Effective termination resistance which takes on a value of 1 MQ when no parallel termination is required V4 Termination voltage 2 load capacitance at the Output pin is 0 pF for all signal standards 3 According to the PCI specification The capacitive load C is connected between the output and GND Output timing for all standards as published in the speed files and the data sheet is always based on a C value of zero High impedance probes less than 1 pF are used for all measurements Any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the final timing numbers as published in the speed files and data sheet 32 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification XILINX Switching Characteristics Using IBIS Models to Simulate Load Conditions Application IBIS models permit the most accurate prediction of timing delays for a given application The parameters found in the IBIS model and correspond directly with the p
20. 2X Period jitter at the CLK2X and CLK2X180 outputs 0 5 0 5 ps of CLKIN of CLKIN period period 100 100 CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing integer 150 150 5 CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing non integer 0 5 0 5 ps division of CLKIN of CLKIN period period 100 100 Duty Cycle CLKOUT DUTY CYCLE DLL Duty cycle variation for the CLKO CLK90 CLK180 CLK270 All 1 of 1 of ps CLK2X CLK2X180 and CLKDV outputs including the CLKIN CLKIN BUFGMUX and clock tree duty cycle distortion period period 350 350 Phase Alignment CLKIN CLKFB PHASE Phase offset between the CLKIN and CLKFB inputs All 2150 2150 ps CLKOUT_PHASE_DLL Phase offset between DLL outputs CLKO to CLK2X 1 1 5 CLK2X180 CLKIN CLKIN period period 100 100 All others 5 1 1 of ps CLKIN CLKIN period period 150 150 Lock Time LOCK_DLL 3 When using the DLL alone The 5 2 lt lt 15 MHz All 5 5 ms time from deassertion at the DCM s Reset input to the rising transition gt 15 MHz 600 5 600 us at its LOCKED output When the DCM is locked the CLKIN and CLKFB signals are in phase Delay Lines DCM_DELAY_STEP Finest delay resolution averaged over all steps All 15 35 15 35 ps Notes The numbers in this table are based on the operating conditions
21. Dedicated JTAG pin 4 per device Not available as a pin Every package has four dedicated JTAG pins These pins are powered by VCCAUX TDI TMS TCK TDO 2007 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm other trademarks are the property of their respective owners All specifications are subject to change without notice DS610 4 v2 0 July 16 2007 Product Specification www xilinx com 59 Pinout Descriptions 5 XILINX Table 56 Types of Pins on Spartan 3A DSP FPGAs Continued T or Description Pin Name s in Type Dedicated ground pin The number of GND pins depends on the package used All must GND be connected Dedicated auxiliary power supply pin The number of VCCAUX pins depends on the VCCAUX package used All must be connected Dedicated internal core logic power supply pin The number of VCCINT pins depends on VCCINT the package used All must be connected to 1 2V Along with all the other pins in the same bank this pin supplies power to the output VCCO_ buffers within the I O bank and sets the input threshold voltage for some standards must be connected This package is not connected in this specific combination but may connected in l
22. Introduction The Spartan 3A DSP family of Field Programmable Gate Arrays FPGAs solves the design challenges in most high volume cost sensitive high performance DSP applications The two member family offers densities ranging from 1 8 to 3 4 million system gates as shown in Table 1 The Spartan 3A DSP family builds on the success of the Spartan 3A FPGA family by increasing the amount of memory per logic and adding XtremeDSP DSP48A slices New features improve system performance and reduce the cost of configuration These Spartan 3A DSP FPGA enhancements combined with proven 90 nm process technology deliver more functionality and bandwidth per dollar than ever before setting the new standard in the programmable logic and DSP processing industry Spartan 3A and Spartan 3A DSP FPGA Differences The Spartan 3A DSP FPGAs extend and enhance the Spartan 3A FPGA family The XC3SD1800A and the XC3SD3400A devices are tailored for DSP applications and have additional block RAM and XtremeDSP DSP48A slices The XtremeDSP DSP48A slices replace the 18x18 multipliers found in the Spartan 3A devices and are based on the DSP48 blocks found in the Virtex 4 devices The block RAMs are also enhanced to run faster by adding an output register Both the block RAM and 5 slices in the Spartan 3A DSP devices run at 250 MHz in the lowest cost standard 4 speed grade Because of their exceptional DSP price performance ratio Spartan 3A DS
23. 3 IO 144 3 IO L32N S LHCLK1 7 3 IO 144 3 02 VO 3 10 L35P S TRDY2 LHCLK6 LHCLK 3 IP 146 3 3 IO L29N 3 VREF 3 VREF 3 IO L42N 3 U4 O 3 IO_L29P_3 M2 VO 3 IO 149 3 U5 VO 3 L27N 3 3 IO L51N 3 Ue 3 L27P 3 3 156 3 07 10 3 IO L28P 3 M5 3 L56N 3 O 3 IO L28N 3 3 IO L61P 3 u9 3 L26N 3 M7 3 IO 138 3 3 126 3 3 IO L38N 3 3 IO L21N 3 M9 3 IO L42P 3 T5 3 IO 3 3 IO L51P 3 T7 10 3 IO L25N 3 L3 3 L48N 3 T9 3 IO L25P 3 L4 3 IO L48P 3 o 3 L18N 3 L7 3 IO L36P 3 VREF 3 R1 VREF 3 IO L15N 3 L9 3 L36N 3 R2 yo 3 IO L15P 3 L10 3 L37P 3 R3 3 IP 124 3 K1 88 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout Descriptions Table 65 Spartan 3A DSP FG676 Pinout for Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued XC3SD3400A FPGA Continued Bank XC3SD3400A Pin 70616 Bank XC3SD3400A Pin Name FG676 3 IO L23N 3 K2 3 lO L65P 3 AD1 3 IO 123
24. DS312 3_05_103105 All Speed Grades Slave Symbol Description Master Min Max Units Clock to Output Times ine from the falling transition on the CCLK pin to data appearing at the Both 1 5 10 ns DOUT pin Setup Times Tpcc The time from the setup of data at the DIN pin to the rising transition at the Both 7 ns CCLK pin Hold Times The time from the rising transition the CCLK pin to the point when data is Master 0 0 ns last held at the DIN pin Slave 1 0 Clock Timing High pulse width the CCLK input Master See Table 47 Slave See Table 48 Low pulse width the input Master See Table 47 Slave See Table 48 FccsER Frequency of the clock signal atthe No bitstream compression Slave 0 100 MHz CCLK input pin UNES With bitstream compression 0 100 MHz Notes 1 The numbers in this table are based on the operating conditions set forth in Table 7 2 For serial configuration with a daisy chain of multiple FPGAs the maximum limit is 25 MHz 50 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification XILINX DC Switching Characteristics Slave Parallel Mode Timing PROG_B Input INIT_B Open Drain CSI Input RDWR_B Input CCLK Input DO D7 Inputs Notes SMCCCS eee SMWCC C A eren Aere ne AAA
25. GND GND H14 GND GND GND T10 GND GND GND H16 GND GND GND T12 GND 66 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout Descriptions Table 60 Spartan 3A DSP 5484 Pinout Continued Table 60 Spartan 3A DSP 5484 Pinout Continued Bank Pin Name GND 114 VCCINT G7 VCCINT GND GND T15 GND VCCINT VCCINT G16 VCCINT GND GND T19 GND VCCINT VCCINT H9 VCCINT GND GND T21 GND VCCINT VCCINT H11 VCCINT GND GND U6 GND VCCINT VCCINT H13 VCCINT GND GND U11 GND VCCINT VCCINT H15 VCCINT GND GND U17 GND VCCINT VCCINT J8 VCCINT GND GND W7 GND VCCINT VCCINT J10 VCCINT GND GND W12 GND VCCINT VCCINT J12 VCCINT GND GND W16 GND VCCINT VCCINT J14 VCCINT GND GND GND VCCINT VCCINT GND Y20 GND VCCINT VCCINT K11 VCCINT VCCAUX PROG B A2 CONFIG VCCINT VCCINT K13 VCCINT VCCAUX DONE 21 VCCINT 15 VCCINT VCCAUX TCK A21 JTAG VCCINT VCCINT L8 VCCINT VCCAUX TMS B1 JTAG VCCINT VCCINT L10 VCCINT VCCAUX TDO B22 JTAG VCCINT VCCINT L12 VCCINT VCCAUX TDI D2 JTAG VCCINT VCCINT L14 VCCINT VCCAUX VCCAUX AA2 VCCA
26. L18P 2 Tus 2 INPUT GCLK2 2 21 22 L39N 1 GND vo L32P 1 Vo Vo L24N 1 L24P 1 GND L20N 1 RHCLK5 L21P 1 1 IRDY1 TRDY1 RHCI KA RHCI L18P 1 RHCLKO vo L10N 1 vo LOSP_1 vo 127 2 vo vo Vo L23P 2 L23N 2 L27P 2 L20P 1 L RHCLK4 GND M L19P 1 N RHCLK2 gt gt gt Right Half of CS484 Package top view 70 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout Descriptions FG676 676 Ball Fine Pitch Ball Grid Array The 676 ball fine pitch ball grid array FG676 supports both the XC3SD1800A and the XC3SD3400A FPGAs There multiple pinout differences between the two devices For a XC3SD1800A FPGA Table 63 lists all the FG676 package pins for the XC3SD1800A FPGA They are sorted by bank number and then by pin name Pairs of pins that form a differential I O Pinout Table Note The grayed boxes denote a difference between the XC3SD1800A and the XC3SD3400A devices list of differences and migration advice see the Footprint Migration Differences section pair appear together in the table The table also shows the pin number for each pin and the pin type as defined earlier Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued
27. 08529 3 02 051607 1 Itis possible to abort configuration by pulling CSI B Low in a given CCLK cycle then switching RDWR B Low High in any subsequent cycle for which CSI B remains Low The RDWR pin asynchronously controls the driver impedance of the DO D7 bus When RDWR B switches High be careful to avoid contention on the DO D7 bus Figure 12 Waveforms for Slave Parallel Configuration Table 50 Timing for the Slave Parallel Configuration Mode Speed Grades Symbol Description Min Max Units Setup Times 2 time from the setup data at the 00 07 pins to the rising transition pin ns Setup time the CSI_B pin before the rising transition the CCLK pin 5 Tsmccw Setup time on the RDWR B pin before the rising transition at the CCLK pin 17 ns Hold Times The time from the rising transition the CCLK pin to the point when data is last held at 1 5 the 00 07 pins Tsmcccs The time from the rising transition at the CCLK pin to the point when a logic level is last 0 5 held the B pin Tsmwcc The time from the rising transition at the CCLK pin to the point when a logic level is last 0 ns held at the pin Clock Timing The High pulse width at the CCLK input pin 5 ns The Low pulse width the CCLK input pin 5 ns Frequency o
28. 1 IO 114 1 T20 1 IO L55P 1 L18 O 1 IO L26P 1 A4 T23 DUAL 1 IO L53P 1 L20 O 1 IO 126 24 DUAL 1 IO L50P 1 122 9 1 IO 127 817 DUAL 1 140 1 123 INPUT 1 IO L27P 1 A6 R18 DUAL 1 IO L38P 1 A12 L24 DUAL 1 IO L22P 1 R19 1 L57N 1 K18 O 1 122 1 R20 1 157 1 K19 Te 1 IO L25P 1 A2 R21 DUAL 1 L53N 1 K20 O DS610 4 v2 0 July 16 2007 www xilinx com 73 Product Specification Pinout Descriptions 5 XILINX Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued Bank XC3SD1800A Pin 70616 Bank XC3SD1800A Pin Name 76676 1 IO L50N 1 21 UO 1 IO LO3N 1 A1 2 DUAL 1 IO L46N 1 K22 O 1 IO_LO5N_1 AC25 O 1 IO 146 1 K23 O 1 IO 106 1 AC26 O 1 IP 140 1 INPUT 1 IO LO7P 1 23 O 1 IO LA1P 1 K25 O 1 IO 107 1 VREF 1 AB24 VREF 1 IO LA1N 1 K26 1 IO LO6N 1 AB26 O 1 IO L59P 1 J19 1 IO LO9P 1 AA22 O 1 IO L59N 1 J20 1 IO LO9N 1 AA23 O 1 IO L62P 1 A20 J21 DUAL 1 _111 _1 24 O 1 IO 149 1 J22 1 IO LN 1 AA25 O 1 IO 149 1 J23 1 IP_L16P_1 25 INPUT 1 IO 143 1 A19 J25 DUAL 1
29. 14 y o 1 lO L24P 1 K19 0 105 0 15 1 lO L25P 1 A12 K20 DUAL 0 IO 104 0 F16 1 lO L22N 1 A11 K22 DUAL 0 IO L23P 0 G8 y o 1 L21N 1 RHCLK7 L17 RHCLK 0 VCCO 0 B5 VCCO 1 IP L23P 1 VREF 1 L18 VREF 0 VCCO 0 B10 VCCO 1 IO L20N 1 RHCLK5 L20 RHCLK 0 VCCO 0 B14 VCCO 1 L20P 1 RHCLK4 L21 RHCLK 0 VCCO 0 B18 VCCO 1 lO L22P 1 10 L22 DUAL 0 VCCO 0 E9 VCCO 1 L18N 1 RHCLK1 M17 RHCLK 0 VCCO 0 E14 VCCO 1 L21P 1 IRDY1 RHCLK6 18 RHCLK 1 IO 102 1 LDCO AA22 DUAL 1 L19N 1 TRDY1 RHCLKS3 M20 RHCLK 1 139 1 C21 INPUT 1 lO L17N 1 9 M22 DUAL 1 139 1 VREF 1 C22 VREF 1 lO L13P 1 A2 N17 DUAL 1 IO L36P 1 A20 D20 DUAL 1 IO L18P 1 RHCLKO N18 RHCLK 1 IO 137 1 A22 D21 DUAL 1 lO L15N 1 A7 N19 DUAL 1 IO L37N 1 A23 D22 DUAL 1 lO L15P 1 A6 N20 DUAL 1 IO L36N 1 A21 E19 DUAL 1 L19P 1 RHCLK2 N21 RHCLK 1 IO 135 1 E20 1 lO 17 1 8 22 DUAL 1 IO L33N 1 E22 y o 1 1 16 DUAL 1 138 1 25 18 DUAL 1 IP_L12N_1 VREF_1 P17 VREF 1 IO L38P 1 24 F19 DUAL 1 L10P 1 P19 1 IO L30N 1 A19 F20 DUAL 1 IP L16N 1 P20 INPUT 1 IO L35P 1 F21 1 _114 _1 5 22 DUAL 1 IO 1 F22 y o 1 IP L12P 1 R17 INPUT 1 IO L34P 1 G17 y o 1 L10N 1 R18 y o 1 IO L34N 1 G18 y o 1 107 1 R19 1 1 18 619 DUAL 1 lO 107 4 20 1 1 G20 INPUT 1 IP_L16P_1 VREF_1 R21 VREF 1 128 1 G22 1 lO L14P 1 4 R22 DUAL 1 IO L26P 1 A14 H17 DUAL 1 lO 105 1
30. 2 lO 2 20 2 2 2 IO L45N 2 AC 1 2 VCCO 2 11 2 2 22 2 VCCO 2 16 2 IP 2 VREF 2 AB6 VREF 2 VCCO 2 AE22 VCCO 2 IO L14N 2 7 2 2 2 IO 2 ABQ 2 VCCO 2 14 2 IO 121 2 AB12 2 VCCO 2 AB19 2 2 INPUT 3 lO 153 3 Y1 O 2 IO_L30N_2 MOSI CSI_B 15 DUAL 3 IO_L53N_3 Y2 O 2 IO_L38N_2 AB16 3 IP_L54P_3 Y3 INPUT 2 47 2 18 3 IO L57P 3 Y5 O 2 IO LO2N 2 CSO B DUAL 3 IO L57N 3 Y6 O 2 IP 2 VREF 2 AA9 3 IP L50P 3 wi INPUT 2 IO L12N 2 AA10 3 150 3 w2 VREF 2 IO_L17N_2 VS2 AA12 DUAL 3 IO_L52P_3 O 2 IO_L25P_2 GCLK12 AA13 GCLK 3 IO_L52N_3 WA O 2 IO_L27N_2 GCLK1 14 GCLK 3 163 3 we O 2 IO 2 INIT B 15 DUAL 3 L63P 3 W7 2 IO 2 17 3 147 Vi O 2 IO 147 2 18 3 IO L47N 3 v2 O 2 IP 2 VREF 2 AA20 VREF 3 IP 146 3 INPUT 2 IP_2 5 INPUT 3 149 3 V5 O 2 2 AD23 INPUT 3 159 3 V6 O 2 2 ACS INPUT 3 IO L59P 3 v7 O 2 2 3 161 3 O 2 2 18 INPUT 3 144 U1 O 2 IP 2 VREF 2 AB10 VREF 3 144 3 U2 2 2 AB20 INPUT 3 IP_L46P_3 U3 INPUT 2 IP_2 19 INPUT 3 142 3 U4 O 2 2 INPUT 3 L49P 3 U5 O 2 2 AB17 INPUT 3 IO L51N 3 U6 O 2 2 Y8 INPUT 3 156 3 U7
31. 3 O 3 L65N 3 AD2 O 3 IO L22N 3 KA 3 L60N 3 Act 110 3 IO L22P 3 K5 3 IO L64P 3 0 3 IO L18P 3 3 L64N 3 1 0 3 IO L13P 3 o 3 L60P 3 3 IO 105 3 3 IO L55P 3 VO 3 IO 105 3 3 IO L55N 3 AA3 1 0 3 IP L24P 3 J1 INPUT 3 IP_3 VREF_3 3 IP_L20N_3 VREF_3 J2 VREF 3 w5 3 IP_L20P_3 3 VCCO 3 T2 VCCO 3 L19N 3 J4 3 3 VCCO 3 IO_L19P_3 5 3 VCCO_3 3 IO L13N 3 Je o 3 L2 3 IO L10P 3 3 VCCO_3 L8 VCCO 3 IO LO1P 3 O 3 VCCO_3 5 VCCO 3 IO LO1N 3 J9 3 VCCO 3 E2 vcco 3 IO 117 3 3 VCCO 3 C2 3 IO L17P 3 H2 3 3 AB2 3 IP_3 VREF_3 H4 GND GND GND 3 IO L10N 3 GND GND 14 GND 3 IO LO3N 3 H7 Vo GND GND W19 GND 3 IP 3 G1 GND W24 GND 3 3 10 GND 25 GND 3 IO LO9N 3 G4 GND GND GND 3 IO 103 3 G6 1 0 GND GND U10 GND 3 L11N 3 F2 o GND GND 013 GND 3 IO_L14N_3 F3 o GND GND 017 GND 3 IO LO7N 3 F4 GND GND U25 GND 3 IO LO9P 3 F5 GND GND T1 GND 3 IO L11P 3 Et lo GND GND T6 GND 3 IO_L07P_3 ES 1 0 GND GND T12 GND 3 IO_LO6N_3 E4 GND GND 114 GND 3 IO 106 3 GND GND 3 IP_3 VREF_3 C1 VREF GND GND T21 GND 3 IO LO2N 3 o GND GND 126 GND 3
32. 5 Commercial 22 39 MHz Industrial 23 81 MHz 1850 27 48 MHz Industrial 29 23 MHz FooiKas j Commercial 37 60 2 Industrial 40 00 MHz Sa 44 80 MHz Industrial 47 66 MHz wo m 88 68 MHz Industrial 94 34 MHz Table 47 Master Mode CCLK Output Minimum Low and High Time ConfigRate Setting Symbol Description 1 3 6 7 8 10 12 13 17 22 25 27 33 44 50 100 Units Master Mode Commercial 595 196 98 3 84 5 74 1 58 4 48 9 44 1 34 2 25 6 22 3 20 9 17 1 12 3 10 4 5 3 ns TMCCL CCLK Minimum Low Industrial 560 185 92 6 79 8 69 8 55 0 46 0 41 8 32 3 24 2 21 4 20 0 16 2 11 9 10 0 5 0 ns and High Time Table 48 Slave Mode CCLK Input Low and High Time Symbol Description Min Max Units TsccL CCLK Low and High time 5 5 05610 3 2 0 16 2007 www xilinx com 49 Product Specification Switching Characteristics 5 XILINX Master Serial and Slave Serial Mode Timing PROG_B eee Input INIT_B Open Drain CCLK eee Input Output DIN pence 767 DOUT Output MCCH 4 TF cogent CCO DO Figure 11 Waveforms for Master Serial and Slave Serial Configuration Table 49 Timing for the Master Serial and Slave Serial Configuration Modes
33. 83 pA Equivalent pull up resistor value Vin GND 3 0V to 3 6V 5 1 11 4 23 9 at User I O Dual Purpose Input only and Dedicated pins 2 3V to 2 7V 62 14 8 33 1 based Note 2 1 7V to 1 9V 8 4 21 6 526 1 4V to 1 6V 10 8 284 740 1 14V to 1 26V 15 3 411 1194 Inpp Current through pull down Vin Vocaux 3 0V to 3 6V 167 346 659 pA resistor User I O Dual Purpose Input only and 2 25V to 2 75V 100 225 457 uA Dedicated pins Equivalent pull down resistor VccAUx 3 0V to 3 6V Vin 3 0V to 3 6V 5 5 10 4 208 value at User I O Dual Purpose Input only and Dedicated pins Vin 2 3V to 2 7V 4 1 78 15 7 based per Note 2 Vin 1 7V to 1 9V 30 57 111 1 4 to 1 6V 2 7 5 1 9 6 Vin 1 14 1 26V 2 4 4 5 8 1 2 25 to 2 75 Vin 3 0V to 3 6V 7 9 16 0 35 0 kQ Vin 2 3 to 2 7V 5 9 12 0 26 3 kQ Vin 1 7V to 1 9V 42 85 186 kQ Vin 1 4V to 1 6V 36 7 2 15 7 kQ Vin 1 14 to 1 26V 3 0 6 0 12 5 kQ Current per pin All levels 10 10 Input capacitance 3 10 pF Rpr Resistance of optional differential 3 3V 10 LVDS_33 MINI LVDS 33 90 100 115 Q termination circuit within a RSDS 33 differential I O pair Not available
34. GCLK 1 VCCO 1 125 VCCO 2 L28P 2 GCLK2 AF14 GCLK 1 VCCO 1 H22 VCCO 2 2 VREF 2 AF15 VREF 1 VCCO 1 H25 VCCO 2 IP 2 VREF 2 VREF 1 1 E25 2 L36P 2 02 AF18 DUAL 1 VCCO 1 AB25 VCCO 2 IO L37P 2 AF19 2 102 2 M2 Y7 DUAL 2 IO L39P 2 AF20 1 0 2 IO 105 2 Y9 2 IP_2 VREF_2 AF22 VREF 86 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout Descriptions Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued Bank XC3SD3400A Pin Name 9916 Bank XC3SD3400A Pin 76676 2 IO 148 2 AF23 2 IO 2 AC8 10 2 IO L52P 2 DO DIN IMISO AF24 DUAL 2 IO L15N 2 AC9 10 2 IO L51P 2 AF25 2 IP 2 VREF 2 AC10 VREF 2 IO LO6P 2 AE3 110 2 IO L23N 2 11 110 2 IO 107 2 AE4 2 IO L21N 2 12 2 IO L10N 2 AE6 I O 2 2 AC13 INPUT 2 IO L11N 2 AE7 2 IO L29N 2 14 1O 2 IO L18P 2 AE8 2 IO L30P 2 15 l O 2 IO L19P 20 51 AE9 DUAL 2 IO L38P 2 AC16 2 IO L22P 2 D7 AE10 DUAL 2 2 AC17 INPUT 2 IO 124 2 04 AE12 DUAL 2 IO
35. Industrial 34 ns T 26 P ns Industrial 25 ns 56 Commercial 22 m ns Industrial 21 ns 160 Commercial 11 2 on ns Industrial 10 6 ns Notes 1 Set the ConfigRate option value when generating a configuration bitstream 48 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification 5 XILINX Switching Characteristics Table 46 Master Mode CCLK Output Frequency by ConfigRate Option Setting ConfigRate Temperature Symbol Description Setting Range Minimum Maximum Units Feci frequency 1 Commercial SA00 0 797 MHz power on value Industrial 0 847 MHz Fcona ue ee 2 42 MHz Industrial 2 57 MHz Eus 4 83 2 Industrial 5 13 MHz 7 Commercial 5 61 MHz Industrial 5 96 MHz T 6 41 MHz Industrial 6 81 MHz EE m 8 12 MHz Industrial 8 63 MHz 12 m 9 70 MHz Industrial 10 31 MHz Fk ig BAS 10 69 MHz Industrial 11 37 MHz iz Commercial 13 74 MHz Industrial 14 61 MHz m Commercial aa 18 44 MHz Industrial 19 61 MHz Folios 25 1000 20 90 2 Industrial 22 23 MHz
36. Notes 1 The minimum READ pulse width is 5 ns and the maximum READ pulse width is 10 us DS610 3 v2 0 July 16 2007 www xilinx com Product Specification 45 and Switching haracteristics 5 XILINX Suspend Mode Timing gts SUSPEND Input AWAKE Output Flip Flops Blo Distributed RAM Entering Suspend Mode Exiting Suspend Mode sw gwe cycle f tsUSPENDHIGH_AWAKE 1 e tsUsPENDLOW_ 8 AWAKE sUsPEND_GWE lsUsPEND_GTS gt FPGA Outputs Defined by SUSPEND constraint FPGA Interconnect 1 1 1 1 1 tsUSPEND_DISABLE aa tg Inputs Figure 9 Suspend Mode Timing Table 43 Suspend Mode Timing Parameters 1 SUSPEND ENABLE Bocka X Blocked DS610 3 08 061207 lAWAKE Write Protected taWAKE_GTS Symbol Description Min Typ Max Units Entering Suspend Mode TSUSPENDHIGH AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter 7 5 suspend_filter No TSUSPENDFILTER Adjustment to SUSPEND pin rising edge parameters when glitch filter 160 300 600 ns enabled suspend_filter Yes TsuSPEND GWE Rising edge of SUSPEND pin until FPGA output pins drive their defined 10 ns i SUSPEND constraint behavior TsusPEND Rising edge of SUSPEND p
37. P 134 L34P UO LHCLKS 3 v vo vO L47P_3 L47N_3 INPUT L50P 3 vo L53P 3 GND vo 160 3 2 vo vO L64P_3 L64N_3 108 _2 vo vO lt gt gt gt vo vo vo GND 2 VCCINT GND L59P_3 L61N vo vo VCCINT VCCINT vo yo vo L25N 2 LOSN_2 L12P_2 GCLK13 VCCINT VO 125 2 2 L12N_2 GCLK12 vo vo GND Vo L14N 2 V ire E vo 2 123 2 INRUT GND GND 126 2 GCLK15 Vo L18P 2 INPUT vo Vo L66N VREI vo Vo yo Vo 126 2 GCLK14 Bank 2 Figure 18 FG676 Package Footprint for XC3SD3400A FPGA top view DS610 4 v2 0 July 16 2007 Product Specification www xilinx com 93 Pinout Descriptions vo vo vo E L16P 0 V 0 y vo vo L16N 0 108 _0 vO INPUT INPUT DES GI GND 9 Vo 25 0 VCCINT LION 0 GCLK4 vo L55N 1 VCCINT GND VCCINT GND VCCINT GND VCCINT GND L34N 1 VCCINT VCCINT GND L94P GND 1301 yo vo VCCINT GND VCCINT L22N 1 vo Vo vo VCCINT GND vo 1 0 vo vo vo vo vo 1 0 vo vo L31P_2 135 _2 L42P 2 L4eN 2 108 1 LosN_1 vo vo HD L31N_2 146 2 V vo M
38. Table 12 Recommended Operating Conditions for User I Os Using Differential Signal Standards for Drivers 1 Vip View IOSTANDARD Attribute Min V Nom Min mV Max mV Min Nom LVDS 2513 2 25 2 5 2 75 100 350 600 0 3 1 25 2 35 LVDS 338 3 0 3 3 3 6 100 350 600 0 3 1 25 2 35 BLVDS_25 4 2 25 2 5 2 75 100 300 0 3 1 3 2 35 MINI LVDS 2509 2 25 2 5 2 75 200 600 0 3 1 2 1 95 MINI LVDS 3309 3 0 3 8 3 6 200 600 0 3 12 1 95 LVPECL_25 5 Inputs Only 100 800 1000 0 3 1 2 1 95 LVPECL 3315 100 800 1000 0 3 1 2 2 86 RSDS 2509 2 25 2 5 2 75 100 200 0 3 1 2 1 5 RSDS 330 3 0 3 3 3 6 100 200 0 3 1 2 1 5 TMDS 33 3 4 7 3 14 3 3 3 47 150 1200 2 7 3 23 PPDS 250 2 25 2 5 2 75 100 400 0 2 2 3 5_33 3 0 3 3 3 6 100 400 0 2 2 3 DIFF HSTL I 18 1 7 1 8 1 9 100 0 8 1 1 DIFF HSTL 189 17 1 8 1 9 100 0 8 14 DIFF HSTL Ill 18 1 7 1 8 1 9 100 0 8 1 4 DIFF HSTL I 1 4 1 5 1 6 100 0 68 0 9 DIFF HSTL Ill 1 4 1 5 1 6 100 0 9 DIFF 551118 1 7 1 8 1 9 100 0 7 1 1 DIFF 551118 108 1 7 1 8 1 9 100 0 7 1 1 DIFF SSTL2 2 3 2 5 2 7 100 1 0 1 5 DIFF 55112 11 8 2 3 2 5 2 7 100 1 0 1 5 DIFF 55113 3 0 3 3 3 6 100 E 1 1 1 9 DIFF SSTLS Il 3 0 3 3 3 6 100 1 1 1 9 Notes 1 The Veco rail
39. 0 59 0 59 ns 16 mA 0 59 0 59 ns 24 mA 0 51 0 51 ns 24 mA 0 60 0 60 ns QuietlO 2 mA 27 67 27 67 ns QuietlO 2 mA 27 67 27 67 ns 4mA 27 67 27 67 ns 4mA 27 67 27 67 ns 6mA 27 67 27 67 ns 6mA 27 67 27 67 ns 8 16 71 16 71 8 16 71 16 71 12 16 29 16 29 ns 12 16 67 16 67 ns 16 mA 16 18 16 18 ns 16 mA 16 22 16 22 ns 24 mA 12 11 12 11 ns 24 mA 12 11 12 11 ns 28 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification XILINX DC Switching Characteristics Table 24 Output Timing Adjustments for Continued Table 24 Output Timing Adjustments for Continued Add the Add the Adjustment Adjustment Convert Output Time from Below Convert Output Time from Below aO with Deve and Speed Grade CHOSE wih Dove and Speed Grade Signal Standard IOSTANDARD 5 4 Units Signal Standard IOSTANDARD 5 4 Units LVCMOS25 Slow 2mA 5 33 5 33 ns LVCMOS15 Slow 2mA 5 82 5 82 ns 4mA 2 81 2 81 ns 4mA 3 97 3 97 ns 6mA 2 82 2 82 ns 6 mA 3 21 3 21 ns 8 1 14 1 14 ns 8 2 53 2 53 ns 12 mA 1 10 1 10 ns 12 mA 2 06 2 06 ns 16 mA 0 83 0 83 ns Fast 2 5 23 5 23 ns 24 m
40. 1 CLKFX period 200 Assume the CLKFX output frequency is 100 MHz The equivalent CLKFX period is 10 ns and 1 of 10 ns is 0 1 ns or 100 ps According to the data sheet the maximum jitter is 100 ps 200 ps 300 ps DS610 3 v2 0 July 16 2007 www xilinx com 43 Product Specification and Switching Characteristics x XILINX Phase Shifter PS Table 39 Recommended Operating Conditions for the PS in Variable Phase Mode Speed Grade 5 4 Symbol Description Min Max Min Max Units Operating Frequency Ranges PSCLK_FREQ Frequency for the PSCLK input 1 167 1 167 MHz Input Pulse Requirements PSCLK PULSE PSCLK pulse width as a percentage of the PSCLK period 40 60 40 60 Table 40 Switching Characteristics for the PS in Variable Phase Mode Symbol Description Phase Shift Amount Units Phase Shifting Range Maximum allowed number lt 60 MHz INTEGER 10 3 5 steps DCM DELAY STEP steps for a given CLKIN clock period where T CLKIN CLKIN 2 60 MHz 3 INTEGER 15 ns clock period in ns If using DIVIDE BY 2 TRUE double the clock effective clock period FINE SHIFT RANGE MIN Minimum guaranteed delay for variable phase shifting STEPS ns DCM_DELAY_STEP_MIN FINE SHIFT RANGE MAX Maximum guaranteed delay for variable phase shi
41. 1 IO L58P 1 VREF 1 22 VREF 2 IO L17P 2 RDWR B Y12 DUAL 1 IO L56N 1 F23 2 IO L25N 2 GCLK13 Y13 GCLK 1 IO L54N 1 F24 1 0 2 L27P 2 GCLKO Y14 GCLK 1 IO L54P 1 F25 2 IO 134 2 03 Y15 DUAL 1 IO 156 1 E24 VO 2 IP 2 VREF 2 Y16 VREF 1 IO L60P 1 E26 2 IO L43N 2 17 VO 1 IO L61N 1 024 2 IO LO5P 2 w9 o 1 IO L61P 1 025 2 109 2 W10 1 IO L60N 1 D26 1 0 2 IO L16N 2 W12 1 163 1 A23 C25 DUAL 2 IO 120 2 W13 1 IO L63P 1 22 C26 DUAL 2 IO L31N 2 w15 1 IP_1 VREF_1 26 VREF 2 146 2 wi7 1 IO 102 1 LDC1 AE26 DUAL 2 IO 109 2 10 1 IO 102 1 LDCO AD25 DUAL 2 IO 2 10 1 IO LO5P 1 AD26 I O 2 IO L16P 2 O 1 IO 103 1 0 AC23 DUAL 2 IO L20P 2 V13 O 1 IO LOSN AC24 DUAL 2 IO L31P 2 V14 1 IO LO5N 1 25 2 IO L35P 2 vis VO 1 IO 106 1 AC26 0 2 IO L42P 2 vie O 1 IO 107 1 AB23 I O 2 L46N 2 V17 O 1 IO 107 1 VREF 1 24 2 IO L13N 2 Utt 1 IO LO6N 1 AB26 O 2 IO L35N 2 u15 1 IO LO9P 1 AA22 2 142 2 016 1 IO LO9N 1 AA23 2 106 2 AF3 1 0 1 IO L11P 1 24 1 0 2 IO 107 2 AF4 1 0 1 IO L11N 1 AA25 2 IO L10P 2 1 VCCO 1 W22 VCCO 2 IO L18N 2 AF8 I O 1 VCCO 1 T19 VCCO 2 IO_L19N_2 VS0 AF9 DUAL 1 VCCO 1 125 vcco 2 L22N 2 06 AF10 DUAL 1 VCCO 1 N22 VCCO 2 IO 124 2 D5 AF12 DUAL 1 VCCO 1 L19 VCCO 2 IO L26P 2 GCLK14 AF13
42. 16 17 18 19 20 21 22 23 24 25 26 Right Half of FG676 Package top view INPUT L65N 1 E D E F G GND WH 2 INPUT 125 0 acne VREF_0 e L25P 0 VCCINT K GCLK4 VCCINT GND L vo vO VCCINT GND VCCINT taser M INPUT INPUT INPUT GND L37N_1 L36N_1 L32N_1 132 1 N 8 2 2 Ke 1 0 1 130 1 1 a RHCLK1 2 vo VCCINT GND R vo VCCINT GND T INPUT Vo Vo Vo 124 1 U L35N 2 L42N 2 L10N 1 vo L35P_2 V Vo Vo Y A A A B A yo INPUT L45P 2 V D vo A L48N 2 E INPUT 10 A iis j Bank 2 82 05610 4 2 0 16 2007 Product Specification XILINX Pinout Descriptions XC3SD3400A FPGA Table 65 lists all the FG676 package pins for the XC3SD3400A FPGA They are sorted by bank number and then by pin name Pairs of pins that form a differential I O pair appear together in the table Table 65 also shows the pin number for each pin and the pin type as defined earlier Pinout Table Note The grayed boxes denote a difference between the XC3SD1800A and the XC3SD3400A devices An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at http www xilinx com bvdocs
43. 18 ns Maximum Frequency FMAX All registers used Yes Yes Yes 287 250 MHz A1REG or B1REG to PREG Yes No 246 214 MHz Yes Yes 195 170 MHz DREG AOREG or BOREG to MREG Yes Yes 205 178 MHz 40 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification lt XILINX DC and Switching Characteristics Digital Clock Manager DCM Timing For specification purposes the DCM consists of three key components the Delay Locked Loop DLL the Digital Frequency Synthesizer DFS and the Phase Shifter PS Aspects of DLL operation play a role in all DCM applications All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLKO or the CLK2X feedback respectively Thus specifications in the DLL tables Table 35 and Table 36 apply to any application that only employs the DLL component When the DFS and or the PS components are used together with the DLL then the specifications listed in the DFS and PS tables Table 37 through Table 40 supersede any corresponding ones in the DLL tables DLL specifications that do not Delay Locked Loop DLL change with the addition of DFS or PS functions are presented in Table 35 and Table 36 Period jitter and cycle cycle jitter are two of many different ways of specifying clock jitter Both specifications describe statistical variation from a mean value Period jitter is the worst case deviation from the ideal clock period over a collection of mill
44. 2 2 AD16 INPUT 2 IO L28P 2 GCLK2 AF14 GCLK 2 IO L33N 2 AD17 O 2 IP_2 VREF_2 AF15 VREF 2 IO_L40P_2 AD19 O 2 IP 2 VREF 2 AF17 VREF 2 IO_L41P_2 AD20 O 2 IO L36P 2 D2 AF18 DUAL 2 IO 144 2 AD 1 O 2 IO 137 2 AF19 2 IO L45P 2 AD22 O 2 IO L39P 2 AF20 2 IO LO1P 2 1 DUAL 2 IP 2 VREF 2 AF22 VREF 2 IO 108 2 AC6 O 2 IO_L48P_2 AF23 2 2 O 2 IO_L52P_2 D0 DIN MISO AF24 DUAL 2 IO L15N 2 O 2 IO_L51P_2 AF25 2 _2 2 VREF 2 IO LO6P 2 AE3 2 IO L23N 2 11 O 2 IO_L07P_2 4 2 IO L21N 2 12 Te 2 IO L10N 2 AEG 2 _2 AC13 INPUT 2 IO L11N 2 AE7 2 IO L29N 2 14 O 2 IO_L18P_2 AE8 2 IO L30P 2 AC15 O 2 IO_L19P_2 VS1 9 DUAL 2 IO L38P 2 AC16 O 2 IO L22P 2 D7 AE10 DUAL 2 2 17 INPUT 2 IO L24N 2 04 AE12 DUAL 2 L40N 2 AC19 O DS610 4 v2 0 July 16 2007 www xilinx com 75 Product Specification Pinout Descriptions 5 XILINX Table 63 Spartan 3A DSP FG676 Pinout for Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued XC3SD1800A FPGA Continued Bank XC3SD1800A Pin Name 70616 Bank XC3SD1800A Pin Name 76676
45. GND Pair Vecayx 3 3V Switching Outputs per Vcco GND Pair VccAux 3 3V Package Type Package Type CS484 FG676 5484 FG676 Signal Standard Top Bottom Left Right Signal Standard Top Bottom Left Right IOSTANDARD Banks 0 2 Banks 1 3 IOSTANDARD Banks 0 2 Banks 1 3 fSingle Ended Standards LVCMOS25 Slow 2 76 76 LVTTL Slow 2 60 60 4 46 46 4 41 41 6 33 33 6 29 29 8 24 24 8 22 22 12 18 18 12 13 13 16 m 11 16 11 11 24 7 24 9 9 Fast 2 18 18 Fast 2 10 10 4 14 14 4 6 6 6 6 6 6 5 5 8 6 6 8 3 3 12 3 3 12 3 3 16 3 16 3 3 24 2 24 2 2 QuietlO 2 76 76 QuietlO 2 80 80 4 60 60 4 48 48 6 48 48 6 36 36 8 36 36 8 27 27 12 36 36 12 16 16 16 m 36 16 13 13 24 8 24 12 12 LVCMOS18 low 2 64 64 LVCMOS33 Slow 2 76 76 4 34 34 4 46 46 6 22 22 6 27 27 8 18 18 8 20 20 12 m 13 12 13 13 16 10 16 10 10 Fast 2 18 18 24 m 9 4 9 9 Fast 2 10 10 6 7 7 4 8 8 8 4 4 6 5 5 12 E 4 8 4 4 16 3 12 4 4 QuietlO 2 64 64 16 2 2 4 64 64 24 2 6 48 48 QuietlO 2 76 76 8 36 36 4 46 46 12 36 6 32 32 16 24 8 26 26 12 18 18 16 14 14 24 10 34 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification lt XILINX DC and Switching Characteristics Table 27 Recommended Number of Simultaneously Switching Outputs per Vcco GND Pair VccAux 3 3V Table 27 Recommended Number of Simultaneously Switching Outputs per Vcco GND Pair 3 3
46. IO LO2P 3 B2 Vo GND GND R11 GND 3 IP_L66P_3 INPUT GND GND GND 3 IP_L66N_3 VREF_3 2 VREF GND GND R15 GND DS610 4 v2 0 July 16 2007 www xilinx com 89 Product Specification Pinout Descriptions 5 XILINX Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued Bank XC3SD3400A Pin Name 9976 Bank XC3SD3400A Pin 70616 GND GND P12 GND GND GND GND GND GND P16 GND GND GND C14 GND GND GND P19 GND GND GND C19 GND GND GND P24 GND GND GND C24 GND GND GND GND GND GND B24 GND GND GND GND GND GND B25 GND GND GND N11 GND GND GND AF1 GND GND GND N15 GND GND GND AF6 GND GND GND M12 GND GND GND AF11 GND GND GND M14 GND GND GND AF16 GND GND GND GND GND GND AF21 GND GND GND 1 GND GND AF26 GND GND GND L6 GND GND AD3 GND GND GND L11 GND GND AD5 GND GND GND GND GND GND AD8 GND GND GND 15 GND GND GND AD13 GND GND GND L21 GND GND GND AD18 GND GND GND 126 GND GND GND AD23 GND GND GND
47. IP L24P 1 U25 INPUT 1 IO L43P 1 A18 J26 DUAL 1 IP L65N 1 B25 INPUT 1 IO L64P 1 A24 H20 DUAL 1 L20P 1 W26 INPUT 1 IO L62N 1 21 21 DUAL 1 IP_L48P_1 H23 INPUT 1 IP_L48N_1 H24 INPUT 1 IP_L52P_1 626 INPUT 1 IP_L44N_1 H25 INPUT 1 VCCO 1 22 1 IP_L44P_1 VREF_1 H26 VREF 1 VCCO 1 1 IO 164 1 A25 621 DUAL 1 VCCO 1 T25 vcco 1 IO L58N 1 G22 1 VCCO 1 N22 1 IO L51P 1 G23 1 1 L19 1 IO L51N 1 G24 1 1 125 1 IP_L52N_1 VREF_1 625 VREF 1 1 H22 1 IO L58P 1 VREF 1 F22 VREF 1 VCCO 1 E25 VCCO 1 IO L56N 1 F23 1 VCCO 1 AB25 VCCO 1 IO L54N 1 F24 2 IO LO2P 2 M2 Y7 DUAL 1 IO L54P 1 F25 2 IO 105 2 Y9 O 1 IO 156 1 24 2 IO 112 _2 Y10 Te 1 IO L60P 1 E26 O 2 IO_L17P_2 RDWR_B Y12 DUAL 1 IO L61N 1 024 2 IO L25N 2 GCLK13 Y13 GCLK 1 IO L61P 1 D25 2 IO L27P 2 GCLKO Y14 GCLK 1 IO L60N 1 D26 2 IO L34N 2 03 Y15 DUAL 1 IO 163 1 A23 C25 DUAL 2 IP 2 VREF 2 Y16 VREF 1 IO L63P 1 A22 C26 DUAL 2 IO L43N 2 Y17 O 1 IP L65P 1 VREF 1 B26 VREF 2 IO LO5P 2 w9 O 1 IO LO2P 1 LDC1 26 DUAL 2 IO LO9N 2 W10 O 1 IO LO2N 1 LDCO AD25 DUAL 2 IO L16N 2 wi2 O 1 IO 1 AD26 O 2 IO L20N 2 W13 O 1 IO LO3P 1 0 23 DUAL 2 IO L31N 2 w15 O 74 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout
48. L16N 3 3 L16N 3 3 IP 3 3 G1 G2 IP L16P 3 3 L16P 3 3 GND GND G2 G5 IP_L12P_3 3 IP_L12P_3 3 GND GND G5 D1 IP_LO8N_3 3 108 3 VCCAUX VCCAUX D1 D2 IP_LO8P_3 3 IP_LO8P_3 3 GND GND D2 C1 LOAN 3 3 IP_LO4N_3 3 IP_3 VREF_3 3 C1 VREF 3 VREF 3 C2 LO4P 3 3 104 3 3 VCCO 3 3 C2 IP_L62P_3 3 IP_L62P_3 3 GND GND AB3 AB4 IP_L62N_3 3 IP_L62N_3 3 VCCAUX VCCAUX AB4 AA4 IP_L58P_3 3 IP_L58P_3 3 GND GND AA4 5 L58N 3 3 IP_L58N_3 3 IP_3 VREF_3 3 5 3 3 Migration Recommendations There are multiple pinout differences between the XC3SD1800A and the XC3SD3400A FPGAs in the FG676 package Please note the differences between the two devices from Table 67 and take the necessary precautions 96 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification 5 XILINX Pinout Descriptions Revision History The following table shows the revision history for this document Date Version Revision 04 02 07 1 0 Initial Xilinx release 05 25 07 1 1 Updates to Table 58 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Corrected VREF pins in XC3S1800A FG676 Table 67 Updated FG676 package footprints for XC3SD1800A FPGA Figure 17 and XC3SD3400A FPGA Figure 18 Minor edits 06 18 07 1 2 Updated for Production release 07 16 07 2 0 Added Low power options Added advance thermal data to Table 59 SPARTAN 3 Soe
49. L40N 2 AC19 1O 2 IO L26N 2 GCLK15 AE13 GCLK 2 IO L41N 2 AC20 0 2 IO 128 2 GCLK3 AE14 GCLK 2 IO L45N 2 21 10 2 IO L32N 2 DOUT AE15 DUAL 2 2 22 0 2 IO L33P 2 AE17 2 IP 2 VREF 2 AB6 VREF 2 IO 136 2 01 AE18 DUAL 2 IO L14N 2 7 2 IO L37N 2 AE19 10 2 IO 2 9 110 2 IO L39N 2 AE20 2 IO 121 2 AB12 0 2 L4A4P 2 AE21 2 2 AB13 INPUT 2 IO L48N 2 AE23 2 IO L30N 2 MOSICSI AB15 DUAL 2 IO L52N 2 CCLK AE24 DUAL 2 L38N 2 AB16 10 2 IO L51N 2 25 2 IO 147 2 18 0 2 IO LO1N 2 MO AD4 DUAL 2 IO LO2N 2 CSO B 7 DUAL 2 IO LO8N 2 2 IP_2 VREF_2 AA9 VREF 2 IO 111 2 AD7 0 2 IO L12N 2 AA10 2 IP 2 AD9 INPUT 2 IO L17N 2 VS2 AA12 DUAL 2 IP 2 AD10 INPUT 2 IO L25P 2 GCLK12 AA13 GCLK 2 IO L23P 2 ADii l O 2 IO L27N 2 GCLK1 14 GCLK 2 IP 2 VREF 2 ADi2 VREF 2 L34P 2 INIT B AA15 DUAL 2 IO L29P 2 ADi4 l O 2 IO L43P 2 AA17 2 IO L32P 2 AWAKE 015 PWRMGMT 2 147 2 AA18 10 2 2 AD16 INPUT 2 IP_2 VREF_2 20 VREF 2 IO L33N 2 2 VCCO 2 W11 VCCO 2 IO 140 2 ADi9 10 2 VCCO 2 W16 VCCO 2 IO 141 2 AD20 0 2 VCCO 2 AF7 VCCO 2 144 2 AD21 0 2 VCCO 2 2 IO L45P 2 AD22 0 2 VCCO 2 AE11 VCCO 2 IO LO1P 2 M1 DUAL 2 VCCO 2 16 2 IO LO8P 2 AC6 I O 2 VCCO 2 AE22 VCCO DS610 4 v2 0 July 16 2007 www xilinx com 87 Product Specification Pinout Descriptions 5 X
50. SPARTAN 3A DSP www xilinx com spartan3adsp DS610 4 v2 0 July 16 2007 www xilinx com 97 Product Specification Pinout Descriptions 5 98 www xilinx co m DS610 4 v2 0 July 16 2007 Product Specification
51. T17 1 IO 1264 1 15 H18 DUAL 1 lO LO5P 1 T18 1 IO L32N 1 H20 1 lO LO9N 1 T20 1 1 VREF 1 H21 VREF 1 lO L11N 1 VREF 1 T22 VREF 1 IO L28P 1 H22 y o 1 LO1P 1 HDC U18 DUAL 1 IO L29N 1 A17 J17 DUAL 1 LO1N 1 LDC2 U19 DUAL 1 IO L32P 1 J19 y o 1 LO9P 1 U20 1 125 1 13 420 DUAL 1 IP_LO8N_1 VREF_1 U21 VREF 1 IP_L27P_1 421 INPUT 1 lO L11P 1 U22 1 L27N 4 922 INPUT 1 SUSPEND 19 PWRMGMT DS610 4 v2 0 July 16 2007 www xilinx com 63 Product Specification Pinout Descriptions 5 XILINX Table 60 Spartan 3A DSP CS484 Pinout Continued Table 60 Spartan 3A DSP CS484 Pinout Continued Bank Pin Name S Type Bank Pin Name EM Type 1 IO LO3N 1 1 V20 DUAL 2 lO L27P 2 AB19 1 IP_LO8P_1 V22 INPUT 2 2 20 1 IO LO3P 1 0 W19 DUAL 2 IO 102 2 CSO B U7 DUAL 1 LOAN 1 VREF 1 W20 VREF 2 L11N 2 U8 1 IP 104 1 W21 INPUT 2 IO_L10N_2 09 y o 1 IO 106 1 W22 y o 2 L14N 2 04 U10 DUAL 1 IO LO2P 1 LDC1 Y21 DUAL 2 L17P 2 GCLKO U12 GCLK 1 IO LO6N 1 Y22 y o 2 L20P 2 U13 1 VCCO 1 21 VCCO 2 lO L25P 2 U14 1 VCCO 1 918 VCCO 2 lO L25N 2 U15 1 VC
52. Waveforms for Serial Peripheral Interface SPI Configuration Table 51 Timing for Serial Peripheral Interface SPI Configuration Mode Symbol Description Minimum Maximum Units Initial CCLK clock period see Table 45 CCLK clock period after FPGA loads ConfigRate setting see Table 45 Setup time on RDWR M 2 0 mode pins before the rising 50 ns edge of INIT_B Hold time RDWR B M 2 0 mode pins after the rising edge 0 ns of INIT B Tcco Address A 25 0 outputs valid after CCLK falling edge See Table 49 Tpcc Setup time on D 7 0 data inputs before CCLK falling edge See Table 49 Hold time D 7 0 data inputs after CCLK falling edge See Table 49 52 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification 5 XILINX DC and Switching Characteristics Table 52 Configuration Timing Requirements for Attached SPI Serial Flash Symbol Description Requirement Units T SPI serial Flash PROM chip select time ns ces amp Tucci Teco SPI serial Flash PROM data input setup time lt 5 DSU MCCL1 SPI serial Flash PROM data hold time Tae 5 DH SPI serial Flash PROM clock to output time T lt T T ns V MCCLn DCC fc or fg Maximum SPI serial Flash PROM clock frequency also
53. XC3SD3400A device Please see the Footprint Migration Differences section for more information Bank 3 3 4 5 6 8 9 10 11 12 INPUT Losn_s INPUT INPUT V V 13 yo vo vO nai Vo 128 0 GCLK10 128 0 GCLK11 vo L30P 0 P LHCLK2 vo L36P_3 VREF 3 T 133 3 IRDY2 LHCLK3 134 3 5 134 3 LHCLK4 1327 3 LHCLKO L32N 3 LHCLK1 yo vo 115 3 GND GND 135 3 GND VCCINT LHCLK6 13543 VCCINT GND LHCLK7 GND VCCINT VCCINT GND vo GND VCCINT vo L13P_2 lt INPUT L66P_3 gt gt OF gt gt gt INPUT L62P_3 vo 106 _2 INPUT 162 3 vo LO7P 2 yo yo vo VCCINT VCCINT VCCINT VCCINT INPUT GND 125 2 GCLK13 L25P 2 GCLK12 ME INPUT vo V L18N 2 Bank 2 Figure 17 FG676 Package Footprint for XC3SD1800A FPGA top view GND 126 2 GCLK15 126 2 GCLK14 DS610 4 v2 0 July 16 2007 Product Specification www xilinx com 81 Pinout Descriptions Bank 0 14 15
54. before the active transition at the 0 64 0 75 5 H CLK input of the block RAM TRcck nEGcE Setup time for the CE input before the active transition at the 0 34 0 40 5 CLK input of the block RAM TRcck Setup time for the RST input before the active transition at 0 22 0 25 ns the CLK input of the block Hold Times ADDR Hold time on the ADDR inputs after the active transition at 0 09 0 10 ns 7 the CLK input DIB Hold time on the DIN inputs after the active transition at the 0 09 0 10 ns i CLK input ENB Hold time on the EN input after the active transition at the 0 09 0 10 ns i CLK input WEB Hold time on the WE input after the active transition at the 0 09 0 10 ns i CLK input TRckc nEGcE time on the CE input after the active transition at the 0 09 0 10 ns CLK input Hold time on the RST input after the active transition at the 0 09 0 10 5 Clock Timing High pulse width of the CLK signal 1 56 1 79 5 5 TBPWL Low pulse width of the CLK signal 1 56 1 79 ns Clock Frequency Block RAM clock frequency 0 320 0 280 MHz Notes 1 numbers in this table are based the operating conditions set forth in Table 7 38 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification x XILINX DC and Switching Characteristics DSP48A Timing To reference the DSP48A block di
55. between the DFS CLKFX180 output and the DLL All 1 1 of ps CLKO output when both the DFS and DLL are used CLKFX CLKFX period period 200 200 Lock Time LOCK_FX 2 3 The time from deassertion at the DCM s 5 2 lt 5 5 ms Reset input to the rising transition at its lt 15 MHz LOCKED output The DFS asserts LOCKED zu when the CLKFX and CLKFX180 signals are gt 15 MHz 5 450 450 HS valid If using both the DLL and the DFS use the longer locking time Notes 1 numbers in this table are based on the operating conditions set forth in Table 7 and Table 37 2 DFS performance requires the additional logic automatically added by ISE 9 1i and later software revisions 3 For optimal jitter tolerance and faster lock time use the CLKIN_PERIOD attribute 4 Maximum output jitter is characterized within a reasonable noise environment 40 SSOs and 25 CLB switching on an FPGA Output jitter strongly depends on the environment including the number of SSOs the output drive strength CLB utilization CLB switching activities switching frequency power supply and PCB design The actual maximum output jitter depends on the system application 5 The CLKFX and CLKFX180 outputs always have an approximate 50 duty cycle 6 duty cycle and alignment specifications include a percentage of the CLKFX output period For example the data sheet specifies a maximum CLKFX jitter of
56. cascade capabilities for various DSP applications e Block RAM provides data storage in the form of 18 Kbit dual port blocks e Configurable Logic Blocks CLBs contain flexible Look Up Tables LUTs that implement logic plus storage elements used as flip flops or latches CLBs perform a wide variety of logical functions as well as store data e Input Output Blocks IOBs control the flow of data between the I O pins and the internal logic of the device 085 support bidirectional data flow plus 3 state operation Supports a variety of signal standards including several high performance differential standards Double Data Rate DDR registers are included e Digital Clock Manager DCM Blocks provide self calibrating fully digital solutions for distributing delaying multiplying dividing and phase shifting clock signals These elements are organized as shown in Figure 1 A dual ring of staggered IOBs surrounds a regular array of CLBs The XC3SD1800A has four columns DSP48As and the XC3SD3400A has five columns of DSP48As Each DSP48A has an associated block RAM The DCMs positioned in the center with two at the top and two at the bottom of the device and in the two outer columns of the 4 or 5 columns of block RAM and DSP48As The Spartan 3A DSP family features a rich network of routing that interconnect all five functional elements transmitting signals among them Each functional element has an associated switch ma
57. for setting the input switching threshold the input voltage that indicates a Low logic level the input voltage that indicates a High logic level 2 general the rails supply only output drivers not input circuits The exceptions for IVVCMOS25 inputs when 3 3V range and for PCI standards 3 For device operation the maximum signal voltage max be as high as max See Table 3 There is approximately 100 mV of hysteresis on inputs using LYCMOS33 and LVCMOS25 standards gt 5 Dedicated pins DONE SUSPEND TDI and TMS draw power from the and use the 525 or 33 standard depending on Dual Purpose configuration pins use the LVCMOS25 standard before the User mode When using these pins as part a standard 2 5V configuration interface apply 2 5V to the lines of Banks 0 1 and 2 at power on as well as throughout configuration DS610 3 v2 0 July 16 2007 Product Specification www xilinx com 15 Switching Characteristics 5 XILINX Table 11 DC Characteristics of User I Os Using Single Ended Standards Table 11 DC Characteristics of User I Os Using Single Ended Standards Continued
58. input to P register CLK Yes Yes Yes 6 25 7 18 ns DS610 3 v2 0 July 16 2007 www xilinx com 39 Product Specification DC Switching Characteristics Table 34 Clock to Out Propagation Delays and Maximum Frequency for the DSP48A 5 XILINX Speed Grade 5 4 Symbol Description Preadder Multiplier Postadder Max Max Units Clock to Out from Output Register Clock to Output Pin PP CLK PREG to output 1 26 1 44 5 Clock to Out from Pipeline Register Clock to Output Pins TpsPCKO PM CLK MREG to P output Yes Yes 3 16 3 63 ns Yes No 1 94 2 23 ns Clock to Out from Input Register Clock to Output Pins TpsPCKO PA CLK AREG to P output Yes Yes 6 33 7 27 ns 5 _ CLK BREG to output Yes Yes Yes 7 45 8 56 ns TpsPcko PC CLK to P output 3 37 3 87 5 CLK output Yes Yes Yes 7 33 8 42 ns Combinatorial Delays from Input Pins to Output Pins AP input to output Yes 2 78 3 19 ns TDSPDO_BP Yes No 4 59 5 28 ns Yes Yes 5 65 6 49 ns TpsPpo BP B input to P output Yes No No 3 49 4 01 ns Yes Yes No 5 79 6 65 ns Yes Yes Yes 6 74 7 74 ns TpsPpo cP C input to P output Yes 2 76 3 17 ns pP D input to output Yes Yes Yes 6 81 7 82 ns TpsPpo oPP OPMODE input to P output Yes Yes Yes 7 12 8
59. publications s3adsp_pin zip Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued 2 2 Bank XC3SD3400A Pin Name 06786 Bank XC3SD3400A Pin FGS76 B NN 0 IO L52P O VREF 0 F8 Oy 105 IO L3IN O F12 0 L39N 0 K12 10 0 IO L27P 0 GCLK8 F13 GCLK 0 IO L25P 0 GCLK4 GCLK 0 a 6 O K16 120 0 F15 0 J10 0 IO L13P 0 F17 0 IO L43P 0 J11 0 LO2N 0 F19 _ 65820 Zu Me IO LOIN O F20 1 0 0 J13 HNPUT 0 IO 148 0 E7 0 IO 125 0 GCLK5 GCLK a 0 IP_0 J15 INPUT 0 E11 INPUT 0 IO J16 10 0 IO E12 0 0 0 J17 VREF 119 L20N 0 E15 VREF 0 L46N 0 H10 0 0 IO L13N 0 E17 0 0 IO 135 0 H12 1O o HIS INPUT O L10P E21 0 IO L16N O H15 T SEPT po 0 IO 108 0 H17 Wo 0 0 07 o 1 0 INPUT 10 140 D8 0 152 G8 DUAL a ONG 0 1O_L34N_0 D10 Vo 0 IO 146 0 010 VO 0 IO L32N O VREF 0 011 VREF 0 IP O VREF 0 G11 VREF Po BE 10 130 D13 10 0 IO 12
60. standard to times that correspond to other signal standards www xilinx com DS610 3 v2 0 July 16 2007 Product Specification XILINX Switching Characteristics Table 22 Timing for the Output Path Speed Grade 5 4 Symbol Description Conditions Device Max Max Units Clock to Output Times When reading from the Output LVCMOS25 2 12 mA output All 2 87 3 13 ns Flip Flop OFF the time from the drive Fast slew rate active transition at the OCLK input to data appearing at the Output pin Propagation Times Tioop The time it takes for data to travel from 52502 12 mA output All 2 78 2 91 ns the IOB s O input to the Output pin drive Fast slew rate The time it takes for data to travel from 2 70 2 85 ns the O input through the OFF latch to the Output pin Set Reset Times Time from asserting the OFF s SR LVCMOS25 12 mA output All 3 63 3 89 ns input to setting resetting data at the drive Fast slew rate Output pin Time from asserting the Global Set 8 62 9 65 ns Reset GSR input on the STARTUP_SPARTANSA primitive to setting resetting data at the Output pin Notes 1 The numbers in this table are tested using the methodology presented in Table 25 and are based on the operating conditions set forth in Table 7 and Table 10 2 This time requires adjustment whenever a s
61. time 5259 XC3SD1800A 2 98 3 39 ns from the setup of data at the IFD_DELAY_VALUE 6 Input pin to an active transition without DCM XC3SD3400A 2 78 3 08 ns at the Global Clock pin The DCM is not in use The Input Delay is programmed Hold Times When writing to IFF the time 52509 XC3SD1800A 0 38 0 38 ns from the active transition at the IFD DELAY VALUE 0 Global Clock pin to the point with XC3SD3400A 0 26 0 26 ne when data must be held at the Input pin The DCM is in use No Input Delay is programmed When writing to IFF the time 52509 XC3SD1800A 0 71 0 71 ns from the active transition at the IFD DELAY VALUE 6 Global Clock pin to the point without DCM XC3SD3400A 0 65 0 65 when data must held at the Input pin The DCM is not in use The Input Delay is programmed Notes 1 The numbers in this table are tested using the methodology presented in Table 25 and are based on the operating conditions set forth in Table 7 and Table 10 2 This setup time requires adjustment whenever a signal standard other than LYCMOS25 is assigned to the Global Clock Input or the data Input If this is true of the Global Clock Input subtract the appropriate adjustment from Table 21 If this is true of the data Input add the appropriate Input adjustment from the same table 3 This hold time requires adjustment whenever a signal standard other than LIVC
62. view Unrestricted 314 general purpose user I O INPUT Unrestricted general purpose input pin DUAL Configuration AWAKE pins then possible user I O VREF User I O or input voltage reference for bank 4 CLK User I O input or clock buffer input CONFIG Dedicated configuration pins SUSPEND pin JTAG Dedicated JTAG port pins GND Ground 100 VCCO Output voltage supply for bank VCCINT Internal core supply voltage 1 2V VCCAUX Auxiliary supply voltage Note The boxes with question marks inside indicate pin differences from the XC3SD1800A device Please see the Footprint Migration Differences section for more information Bank 3 gt Vo Vo L51P O L45P 0 V B vo vo vo vo LO2N 3 102 _3 L51N_O L45N_0 Pinout Descriptions 128 0 GCLK10 INPUT c 144 _0 VCCINT TMS vo 144 0 VCCINT V vo GND yo a i _ vo J L13N_3 5 vo LO3N 3 128 0 GCLK11 INPUT yo VREF 0 L30P 0 vo L48N_0 vo L48P 0 TDI vo L10P 3 vo L13P_3 GND VCCINT GND VCCINT GND _ VCCINT 3 E GND VCCINT VCCINT L35N 3 VCCINT GND GND VCCINT GND VCCINT GND VCCINT L M GND L32P_3 TRDY2 LHCLKO LHCLKi
63. 1 IP L65N 1 1 GND GND B25 B26 IP L65P 1 1 IP L65P 1 1 IP 1 VREF 1 1 B26 VREF 1 VREF 1 DS610 4 v2 0 July 16 2007 www xilinx com 95 Product Specification Pinout Descriptions 5 XILINX Table 67 FG676 Footprint Migration Differences Continued Spartan 3A Spartan 3A DSP Spartan 3A DSP FG676 XC3S1400A XC3S1400A XC3SD1800A XC3SD1800A XC3SD3400A XC3SD3400A FG676 Ball Type Bank Type Bank Type Bank Ball Y8 N C N C 2 2 Y8 Y11 2 2 2 2 Y11 Y18 N C N C 2 2 VCCINT VCCINT Y18 Y19 N C N C 2 VREF 2 2 Y19 W18 N C N C 2 2 VCCINT VCCINT W18 AF2 2 2 2 2 AF2 AF7 IP_2 2 IP_2 2 VCCO 2 2 AF7 AD5 N C N C 2 2 GND GND AD5 AD23 N C N C IP_2 2 GND GND AD23 AC5 N C N C 2 2 GND AC5 AC7 IP_2 2 IP_2 2 GND GND AC7 AC18 IP_2 2 IP_2 2 GND GND AC18 AB10 IP 2 VREF 2 2 2 VREF 2 2 GND GND AB10 AB17 2 2 2 2 VCCAUX VCCAUX AB17 AB20 2 2 2 2 GND GND AB20 2 2 19 2 2 2 2 GND GND AA19 AC22 N C N C 2 2 2 2 22 154 3 3 IP_L54P_3 3 IP_3 3 Y3 Y4 IP_L54N_3 3 IP_L54N_3 3 VCCINT Y4 H4 IP_L12N_3 3 IP_L12N_3 3 IP S VREF 3 3 H4 VREF 3 VREF 3 G1
64. 106 0 23 0 A23 INPUT 0 IO L51N 0 B3 0 F9 INPUT 0 L45N 0 B4 0 E20 INPUT 0 IO 0 B6 O 0 A24 INPUT 0 IO L42P 0 B7 O 0 618 0 IO L38N 0 B8 0 10 INPUT 0 IO 136 0 0 F18 INPUT 0 IO L33N 0 B10 0 E6 INPUT 0 IO L29N 0 B12 0 05 INPUT 0 IO L28P 0 GCLK10 B13 GCLK 0 C4 INPUT 0 IO L26P 0 GCLK6 B14 VCCO 0 H11 0 IO L23P 0 B15 VCCO O H16 VCCO 0 IO L19N 0 B17 O 0 0 IO L18P 0 B18 VCCO O E13 VCCO 0 IO L15P 0 B19 9 VCCO O E19 0 IO 0 B20 VREF VCCO 0 5 0 109 0 21 VCCO 0 B11 72 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout Descriptions Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued Bank XC3SD1800A Pin 70616 Bank XC3SD1800A Pin 70616 0 0 VCCO 1 L25N 1 A3 R22 DUAL 0 VCCO 0 B22
65. 141 Operating Range DS610 1_02_070607 Figure 2 Spartan 3A DSP FPGA Package Marking Example Ordering Information Spartan 3A DSP FPGAs are available in both standard and Pb free packaging options for all device package combinations The Pb free packages include a G character in the ordering code Standard Packaging Example XC3SD1800A 4 CS 484 LI Device Power Temperature Range Speed Grade a 4 Standard Performance 5 High Performance Commercial only LI Low power Industrial CS484 only Package Type Number of Pins DS610 1_05_070607 Pb Free Packaging Example XC3SD1800A 4 CS G 484 LI Device Type Power Temperature Range C Commercial Speed Grade Industrial 4 Standard Performance Low power Industrial CSG484 5 High Performance Commercial only Number of Pins Pb free Package Type DS610 1 04 070 Device Speed Grade Package Type Number of Pins Power T ics na Range XC3SD1800A 4 Standard Performance CS G 484 484 ball Chip Scale Ball Grid Array CSBGA Commercial 0 C to 85 XC3SD3400A 5 High Performance FG G 676 676 ball Fine Pitch Ball Grid Array FBGA Industrial 40 C to 100 C Low power Industrial 40 to 100 C L Notes 1 5 speed grade is exclusively available in the Commercial temperature range 2 The L Low power option is exclu
66. 2 XILINX Spartan 3A DSP FPGA Family Data Sheet DS610 July 16 2007 Module 1 Introduction and Ordering Information DS610 1 v2 0 July 16 2007 e Introduction e Features e Architectural Overview e Configuration Overview e General I O Capabilities e Supported Packages and Package Marking e Ordering Information Module 2 Functional Description DS610 2 v2 0 July 16 2007 The functionality of the Spartan 3A DSP FPGA family is described in the following documents e 09331 Spartan 3 Generation FPGA User Guide Clocking Resources Digital Clock Managers DCMs Block Configurable Logic Blocks CLBs Distributed RAM SRL16 Shift Registers Carry and Arithmetic Logic O Resources Programmable Interconnect SETM Software Design Tools and IP Cores Embedded Processing and Control Solutions Pin Types and Package Overview Package Drawings Powering FPGAs Power Management 00431 XtremeDSP DSP48A for Spartan 3A DSP FPGAs User Guide Slice Design Considerations DSP48A Architecture Highlights 18 x 18 Bit Multipliers 48 Bit Accumulator 18 bit Pre Adder DSP48A Application Examples Product Specification 09332 Spartan 3 Generation Configuration User Guide Configuration Overview Configuration Pins and Behavior Bitstream Sizes A Detailed Descriptions by Mode Master Serial Mode using Platform Flash PROM Master SPI
67. 3 and VccAux 2 5V The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with 1 26V Veco 3 6V and 3 6V The FPGA is programmed with a blank configuration data file that is a design with no functional elements instantiated For conditions other than those described above for example a design including functional elements measured quiescent current levels will be different than the values in the table 3 There are two recommended ways to estimate the total power consumption quiescent plus dynamic for a specific design a The Spartan 3A DSP FPGA XPower Estimator provides quick approximate typical estimates and does not require a netlist of the design b XPower Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power on successfully 5 For information on the power saving Suspend mode see XAPP480 Using Suspend Mode in Spartan 3 Generation FPGAs Suspend mode typically saves 4095 total power consumption compared to quiescent current 14 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification XILINX Switching Characteristics Single Ended I O Standards Table 10 Recommended Operating Conditions for User I Os Using Si
68. 36 sound board lay out practice This table assumes the following POIBS3 6 6 parasitic factors combined PCB trace and land inductance per and GND pin of 1 0 nH receiver capacitive load of 15 pF 66 3 13 Test limits are the Vi voltage limits for the respective I O PCIX standard _ 11 3 than one signal standard is assigned to the I Os a given 20 bank refer to XAPP689 Managing Ground Bounce Large HSTL iii FPGAs for information on how to perform weighted average SSO m 8 calculations HSTL 1 18 17 17 HSTL Il 18 5 HSTL 18 10 8 5511181 7 15 55817118 11 3 SSTL2 18 18 5581712 II 9 SSTL3 8 10 SSTL3 II 6 7 Differential Standards Number of I O Pairs or Channels LVDS 25 22 LVDS_33 27 BLVDS 25 4 4 MINI LVDS 25 22 MINI 1 08 33 27 LVPECL_25 Inputs Only 35 DC Switching Characteristics Configurable Logic Block CLB Timing Table 28 CLB SLICEM Timing 5 XILINX Speed Grade 5 4 Symbol Description Min Max Min Max Units Clock to Output Times When reading from the FFX FFY Flip Flop the time 0 60 0 68 ns from the active transition at the CLK input to data appearing at the XQ YQ output Setup Times Tas Time from the setup of data at the F or G input to the 0 18 0 36 ns active transition at the CLK input of the CLB
69. 7 0 GCLK9 G13 GCLK 5 0 0 614 INPUT 0 IO L22P 0 D16 10 0 IO 116 0 615 0 0 IO 121 0 017 0 0 0 017 10 0 IO L17P 0 D18 0 IO LO2P 0 G19 VREF 0 Lo1F 0 620 10 0 IO L10N 0 D21 DS610 4 v2 0 July 16 2007 www xilinx com 83 Product Specification Pinout Descriptions 5 XILINX Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued Bank XC3SD3400A Pin Name 9916 Bank XC3SD3400A Pin Name 76676 0 IO LO5P 0 022 0 IO L33P 0 A10 0 IO 106 0 023 0 IO L29P 0 A12 0 0 IO 144 0 c5 0 13 INPUT 0 IO L41N O 0 IO L26N O GCLK7 A14 GCLK 0 IO L42N 0 0 IO L23N 0 A15 0 IO L40P 0 0 0 A17 INPUT 0 134 0 C10 10 0 IO L18N 0 A18 0 IO 132 _0 Cii 10 0 IO L15N 0 A19 0 L30N 0 C12 10 0 IO L14N 0 A20 0 IO 128 0 GCLK11 C13 GCLK 0 IO LO7N 0 A22 VO 0 IO L22N 0 C15 VCCO 0 H11 VCCO 0 IO L21N 0 VCCO 0 VCCO 0 IO L19P 0 C17 VCCO 0 E8 0 IO L17N 0
70. 8 VCCINT VCCAUX VCCAUX AF2 VCCAUX VCCINT VCCINT E6 VCCINT VCCAUX VCCAUX VCCAUX VCCINT VCCINT 05 VCCINT VCCAUX VCCAUX 5 VCCAUX C4 VCCAUX VCCAUX AB11 VCCAUX VCCINT VCCINT VCCAUX VCCAUX 17 VCCAUX VCCAUX VCCAUX 22 VCCAUX VCCAUX VCCAUX A24 VCCAUX VCCINT VCCINT Y8 VCCINT Y11 VCCINT VCCINT VCCINT Y18 VCCINT VCCINT VCCINT Y19 VCCINT VCCINT W18 VCCINT VCCINT VCCINT 012 VCCINT DS610 4 v2 0 July 16 2007 www xilinx com 91 Product Specification Pinout Descriptions 5 XILINX User I Os by Bank Table 66 indicates how the available user I O pins are distributed between the four I O banks on the FG676 package The AWAKE pin is counted as a Dual Purpose Table 66 User I Os Per Bank the XC3SD3400A in the FG676 Package Maximum I Os All Possible I O Pins by Type Package and 7 Edge Bank Input Only yo INPUT oua ver MEETHAM CLK Top 0 111 82 11 1 9 8 Right 1 123 67 8 30 10 8 Bottom 2 112 68 6 21 9 8 Left 3 123 97 9 0 9 8 TOTAL 469 314 34 52 37 32 Notes 1 26 VREF on INPUT pins 92 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX FG676 Footprint XC3SD3400A FPGA Left Half of Package top
71. A 2 26 2 26 ns 4 mA 3 05 3 05 ns Fast 2mA 4 36 4 36 ns 6 mA 1 95 1 95 ns 4 mA 1 76 1 76 ns 8 1 60 1 60 ns 6 mA 1 25 1 25 ns 12 mA 1 30 1 30 ns 8 0 38 0 38 ns QuietlO 2 34 11 34 11 ns 12 mA 0 00 0 00 ns 4 mA 25 66 25 66 ns 16 mA 0 01 0 01 ns 6 mA 24 64 24 64 ns 24 mA 0 01 0 01 ns 8 22 06 22 06 ns QuietlO 2 25 92 25 92 5 12 20 64 20 64 ns 4mA 25 92 25 92 ns LVCMOS12 Slow 2mA 7 14 7 14 ns 6mA 25 92 25 92 ns 4mA 4 87 4 87 ns 8 15 57 15 57 5 6 mA 5 67 5 67 ns 12 mA 15 59 15 59 ns Fast 2mA 6 77 6 77 ns 16 mA 14 27 14 27 ns 4mA 5 02 5 02 ns 24 11 37 11 37 ns 6 mA 4 09 4 09 ns LVCMOS18 Slow 2 mA 4 48 4 48 ns QuietlO 2 50 76 50 76 ns 4 mA 3 69 3 69 ns 4 mA 43 17 43 17 ns 6 mA 2 91 2 91 ns 6 mA 37 31 37 31 ns 8 mA 1 99 1 99 ns PCI33 3 0 34 0 34 ns 12 mA 1 57 1 57 ns 66 3 0 34 0 34 ns 16 mA 1 19 1 19 ns PCIX 0 34 0 34 ns Fast 2 mA 3 96 3 96 ns HSTL I 0 78 0 78 ns 4 mA 2 57 2 57 ns HSTL Ill 1 16 1 16 ns 6 mA 1 90 1 90 ns HSTL 1 18 0 35 0 35 ns 8 mA 1 06 1 06 ns HSTL Il 18 0 30 0 30 ns 12 mA 0 83 0 83 ns HSTL 18 0 47 0 47 ns 16 mA 0 63 0 63 ns SSTL18 0 40 0 40 ns QuietlO 2 mA 24 97 24 97 ns SSTL18 11 0 30 0 30 ns 4 24 97 24 97 ns SSTL2 0 00 0 00 ns 6 mA 24 08 24 08 ns 5812 II 0 05 0 05 ns 8mA 16 43 16 43 ns SSTL3 I 0 00 0 00 ns 12 mA 14 52 14 52 ns SSTL3 II 0 17 0 17 ns 16 mA 13 41 13 41 ns DS610 3 v2 0 July 16 2007 www xilinx com 29 Product Specifi
72. A14 0 IO LO8P 0 D15 0 15 INPUT 0 017 INPUT 0 IO LOGP O VREF 0 A16 VREF 0 018 INPUT 0 IO 06 0 A17 0 IO 101 0 019 0 18 INPUT 0 IP_O INPUT 0 IO LO7N 0 A19 O 0 IO O VREF 0 7 VREF 0 20 0 127 0 lO 0 L30P 0 B3 0 0 10 INPUT 0 IO L28P 0 B4 0 IO L19N 0 GCLK9 E11 GCLK 0 L24P 0 B6 0 IO 17 0 GCLK4 E12 GCLK 0 IO L20N O GCLK1 1 B8 GCLK 0 lO LO9P 0 E13 0 IO L18N O GCLK7 B9 GCLK 0 lO LO5P 0 E15 0 L15P 0 B11 0 104 0 16 0 lO L11N 0 B13 0 0 17 INPUT 0 IO L10N 0 B15 0 IO L31N B F7 DUAL 0 IO LOS3P 0 B17 0 lO L27P 0 F8 0 102 0 19 0 lO L23N 0 F9 0 IO LO07P 0 B20 0 IO L19P 0 GCLK8 F10 GCLK 62 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification 5 XILINX Pinout Descriptions Table 60 Spartan 3A DSP CS484 Pinout Continued Table 60 Spartan 3A DSP CS484 Pinout Continued Bank Pin Name S Type Bank Pin Name EM Type 0 IO 117 0 GCLK5 F11 GCLK 1 L29P 1 A16 K16 DUAL 0 12 INPUT 1 IP_L23N_1 K17 INPUT 0 IO L13N 0 F13 1 124 1 18 0
73. AUX 79 Pinout Descriptions 5 XILINX User I Os by Bank Table 64 indicates how the available 1 pins are distributed between the four I O banks on the FG676 package The AWAKE pin is counted as a Dual Purpose Table 64 User I Os Per Bank the XC3SD1800A in the FG676 Package Maximum I Os All Possible I O Pins by Package and Edge Bank Input Only INPUT pu veer CLK Top 0 128 82 28 1 9 8 Right 1 130 67 15 30 10 8 Bottom 2 129 68 21 21 11 8 Left 3 132 97 18 0 9 8 TOTAL 519 314 82 52 39 32 Notes 1 28 VREF are on INPUT pins 80 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout Descriptions FG676 Footprint XC3SD1800A FPGA Left Half of Package top view Unrestricted 314 general purpose user I O INPUT Unrestricted 82 general purpose input pin DUAL Configuration AWAKE pins then possible user I O VREF User I O or input voltage reference for bank CLK User input or clock buffer input 4 CONFIG Dedicated configuration pins SUSPEND pin JTAG Dedicated JTAG port pins GND Ground 77 VCCO Output voltage supply for bank VCCINT Internal core supply voltage 1 2V VCCAUX Auxiliary supply voltage Note The boxes with triangles inside indicate pin differences from the
74. CINT VCCINT T13 VCCINT VCCAUX DONE 21 CONFIG T15 VCCAUX PROG B A2 CONFIG VCCINT VCCINT R12 VCCINT VCCAUX G7 R14 VCCAUX TDO E23 JTAG R16 VCCAUX TMS P11 VCCAUX A25 STAG VCCINT VCCINT VCCINT VCCAUX _________ W26 VCCAUX VCCINT VCCINT P14 VCCINT VCCAUX VCCAUX V9 VCCAUX VCCINT VCCINT P15 VCCINT VCCAUX VCCAUX U14 VCCAUX VCCINT VCCINT N12 VCCINT VCCAUX VCCAUX T22 VCCAUX VCCINT VCCINT N13 VCCINT VCCAUX VCCAUX 17 VCCAUX VCCINT VCCINT N14 VCCINT VCCAUX VCCAUX N10 VCCAUX N16 VCCINT VCCAUX VCCAUX L5 VCCAUX VCCINT VCCINT M11 VCCINT VCCAUX VCCAUX M13 VCCINT VCCAUX VCCAUX J18 VCCAUX VCCINT VCCINT M15 VCCINT VCCAUX VCCAUX VCCAUX VCCINT VCCINT M17 VCCINT VCCAUX VCCAUX G26 VCCAUX VCCINT VCCINT L12 VCCINT VCCAUX VCCAUX F9 VCCAUX L14 VCCINT VCCAUX VCCAUX E5 VCCAUX L16 VCCAUX VCCAUX E16 VCCAUX VCCINT VCCINT K15 VCCINT VCCAUX VCCAUX E20 VCCAUX VCCINT VCCINT G18 VCCINT VCCAUX VCCAUX E22 VCCAUX VCCINT VCCINT F10 VCCINT VCCAUX VCCAUX Di VCCAUX VCCINT VCCINT 1
75. CLK6 P18 RHCLK 1 L41N 1 K26 0 1 IO L30N 1 RHCLK1 P20 RHCLK 1 IO L59P 1 J19 1 IO L30P 1 RHCLKO P21 RHCLK 1 L59N 1 J20 10 1 L37P 1 P22 1 IO L62P 1 A20 J21 DUAL 1 IO L33P 1 RHCLK4 P23 RHCLK 1 L49N 1 J22 0 1 IO_L31N_1 TRDY1 RHCLK3 P25 RHCLK 1 IO L49P 1 J23 0 1 IO L31P 1 RHCLK2 P26 RHCLK 1 IO 143 1 A19 J25 DUAL 1 IO 139 1 A15 N17 DUAL 1 IO L43P 1 A18 J26 DUAL 1 IO L39P 1 A14 N18 DUAL 1 IO L64P 1 A24 H20 DUAL 1 IO 134 1 RHCLK7 N19 RHCLK 1 IO 162 1 A21 H21 DUAL 1 IO L42P 1 A16 N20 DUAL 1 IP 1 H24 INPUT 1 IO L37N 1 1 1 IP_1 VREF_1 H26 VREF 1 IP_L36N_1 23 INPUT 1 IO 164 1 A25 G21 DUAL 1 IO L33N 1 RHCLK5 N24 RHCLK 1 IO L58N 1 G22 1 IP_L32N_1 N25 INPUT 1 IO L51P 1 G23 1 0 1 IP L32P 1 N26 INPUT 1 IO L51N 1 624 1 0 DS610 4 v2 0 July 16 2007 www xilinx com 85 Product Specification Pinout Descriptions 5 XILINX Table 65 Spartan 3A DSP FG676 Pinout for Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued XC3SD3400A FPGA Continued Bank XC3SD3400A Pin Name FG9 9 Bank XC3SD3400A Pin 76676 1 IP 1 VREF 1 G25 VREF 2 L12P 2 Y10 10
76. CO 1 21 VCCO 2 L28P 2 U16 1 VCCO 1 18 VCCO 2 102 2 M2 V6 DUAL 1 VCCO 1 P21 VCCO 2 L11P 2 V7 1 VCCO 1 V21 VCCO 2 106 2 V8 2 IO LO1P 2 1 DUAL 2 _110 _2 V10 2 IO 104 2 4 y o 2 lO L14P 2 D5 V11 DUAL 2 IP 2 6 2 lO L17N 2 GCLK1 V12 GCLK 2 IO 2 y o 2 L20N 2 MOSI CSI B V13 DUAL 2 IO 2 D6 AA10 DUAL 2 IP 2 VREF 2 V15 VREF 2 IO L16P 2 GCLK14 AA12 GCLK 2 L28N 2 V16 2 IO 118 2 GCLK3 14 GCLK 2 lO 2 CCLK V17 DUAL 2 IO L19P 2 AA15 y o 2 IP 2 VREF 2 WA VREF 2 IO L22P 2 AWAKE AA17 PWRMGMT 2 IO LO3P 2 W5 2 127 2 19 y o 2 107 2 VS2 W6 DUAL 2 IO L30P 2 AA20 y o 2 IO 106 2 W8 2 IP 2 VREF 2 AB2 VREF 2 IP 2 VREF 2 W9 VREF 2 IO LO1N 2 0 DUAL 2 IP_2 W10 INPUT 2 104 2 4 y o 2 IP 2 VREF 2 W13 VREF 2 IO LO5P 2 AB5 y o 2 L21N 2 W14 2 105 2 6 y o 2 IO L24P 2 INIT B W15 DUAL 2 IO 108 2 AB7 y o 2 IO 2 DO DIN MISO W17 DUAL 2 IO LO9P 2 VS1 AB8 DUAL 2 IP 2 VREF 2 W18 VREF 2 IO 109 2 VSO AB9 DUAL 2 IO LO3N 2 Y4 2 IO L12P 2 07 AB10 DUAL 2 IO 107 2 RDWR B Y5 DUAL 2 IP 2 VREF 2 AB11 VREF 2 IP 2 Y6 INPUT 2 IO 116 2 GCLK15 AB12 GCLK 2 IP 2 Y7 INPUT 2 IO 8 2 GCLK2 AB13 GCLK 2 IO L13P 2 Y8 2 IO L1N 2 AB14 y o 2 2 Y9 2 2 15 2 IO_L15N_2 GCLK13 Y10 GCLK 2 IO_L22N_2 DOUT AB16 DUAL 2 lO L15P 2 GCLK12 Y11 GCLK 2 IO L23P 2 AB17 y
77. DFS outputs CLKFX CLKFX180 are used 2 If both DFS and DLL outputs are used on the same follow the more restrictive CLKIN_FREQ_DLL specifications in Table 35 3 CLKIN input jitter beyond these limits may cause the DCM to lose lock 4 The DCM specifications are guaranteed when both adjacent DCMs are locked Table 38 Switching Characteristics for the DFS Speed Grade 5 E Symbol Description Device Min Max Min Units Output Frequency Ranges CLKOUT FREQ FX 2 Frequency for the CLKFX and CLKFX180 outputs All 5 350 5 311 MHz Output Clock Jitter 3 4 CLKOUT PER JITT FX Period jitter at the CLKFX and CLKFX180 tputs T CLKIN Use the Spartan 3A Jitter Calculator ps 20 MHz www xilinx com bvdocs publications s3a jitter calc zip CLKIN 1 of 1 of x 196 of 1 ps gt 20 MHz CLKFX CLKFX CLKFX CLKFX period period period period 100 200 100 200 Duty Cycle 6 CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs All 1 of 1 of ps including the BUFGMUX and clock tree duty cycle distortion CLKFX CLKFX period period 350 350 Phase Alignment CLKOUT PHASE FX Phase offset between the DFS CLKFX output and the DLL CLKO 200 200 5 output when both the DFS and DLL are used CLKOUT_PHASE_FX180 Phase offset
78. Descriptions Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued Bank XC3SD1800A Pin 70616 Bank XC3SD1800A Pin Name 76676 2 IO 146 2 W17 2 L26N 2 GCLK15 AE13 GCLK 2 IO LO9P 2 V10 O 2 IO_L28N_2 GCLK3 AE14 GCLK 2 IO 2 11 2 IO 1 2 DOUT AE15 DUAL 2 IO L16P 2 12 2 IO 133 2 17 O 2 IO L20P 2 V13 O 2 IO_L36N_2 D1 AE18 DUAL 2 IO_L31P_2 V14 O 2 IO_L37N_2 AE19 O 2 IO L35P 2 V15 2 IO L39N 2 20 O 2 IO L42P 2 V16 O 2 IO_L44P_2 21 O 2 IO_L46N_2 V17 2 IO L48N 2 AE23 O 2 IO L13N 2 Ut1 2 IO 152 2 24 DUAL 2 IO L35N 2 U15 2 IO L51N 2 25 O 2 IO_L42N_2 U16 2 _101 _2 AD4 DUAL 2 106 2 2 IO LO8N 2 AD6 O 2 IO LO7N 2 AF4 O 2 IO_L11P_2 AD7 O 2 IO L10P 2 AF5 2 2 AD9 INPUT 2 IP 2 AF7 INPUT 2 2 AD10 INPUT 2 IO L18N 2 AF8 O 2 IO L23P 2 AD11 O 2 IO L19N 2 VSO AF9 DUAL 2 IP 2 VREF 2 ADi2 VREF 2 IO L22N 2 D6 AF10 DUAL 2 IO L29P 2 AD14 O 2 IO L24P 2 D5 AF12 DUAL 2 IO L32P 2 AWAKE AD15 PWRMGMT 2 IO L26P 2 GCLK14 AF13 GCLK
79. E2 GND GND K17 GND 3 VCCO_3 AB2 GND GND J24 GND GND GND W8 GND GND GND H3 GND GND GND W14 GND GND GND H8 GND GND GND W19 GND GND GND H14 GND GND GND W24 GND GND GND H19 GND GND GND GND GND GND F1 GND GND GND U10 GND GND GND F6 GND GND GND U13 GND GND GND F11 GND GND GND U17 GND GND GND F16 GND 78 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout Descriptions Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued DS610 4 v2 0 July 16 2007 Product Specification www xilinx com Bank XC3SD1800A Pin 9916 Bank XC3SD1800A Pin Name 76676 GND GND 21 GND VCCAUX VCCAUX P17 VCCAUX GND GND F26 GND VCCAUX VCCAUX N10 VCCAUX GND GND C3 GND VCCAUX VCCAUX L5 VCCAUX GND GND C9 GND VCCAUX VCCAUX K13 VCCAUX GND GND C14 GND VCCAUX VCCAUX J18 VCCAUX GND GND 19 GND VCCAUX VCCAUX E5 VCCAUX GND GND C24 GND VCCAUX VCCAUX E16 VCCAUX GND GND AF1 GND VCCAUX VCCAUX E22 VCCAUX GND GND AF6 GND VCCAUX VCCAUX 5 VCCAUX GND GND AF11 GND
80. EF 3 124 3 6 y o 3 IO 09 3 E3 y o 3 L21N S LHCLK7 N7 LHCLK 3 IO 109 3 4 y o 3 lO L25P 3 P1 y o 3 IO 106 3 F1 3 lO L25N 3 P2 y o 3 IO 106 3 F2 y o 3 3 101 3 y o 3 lO L32P 3 VREF 3 P4 VREF 3 IO LO3P 3 F4 y o 3 lO L26P 3 P6 3 IO 103 3 F5 y o 3 lO L28N 3 R1 3 IO L11P 3 G1 y o 3 lO L28P 3 R2 3 IO 101 3 G3 3 134 3 3 IO 107 3 G5 y o 3 lO L32N 3 R5 3 IO LO7N 3 G6 y o 3 126 3 R6 y o 3 IO 3 H1 y o 3 lO L30P 3 T1 y o 3 IO 3 H2 y o 3 IP L27P 3 T3 INPUT 3 IO 105 3 H3 y o 3 L34N 3 4 3 IO_LO5N_3 H4 y o 3 L29N 3 5 3 IO L10P 3 H5 y o 3 L29P 3 T6 3 IO L10N 3 H6 3 lO L30N 3 U1 y o 3 IO L14N S VREF 3 J1 VREF 3 lO L33P 3 U2 3 IP_L16P_3 J3 INPUT 3 IP_L27N_3 U3 INPUT 3 IP_L16N_3 J4 INPUT 3 138 3 04 3 IP_L12P_3 96 INPUT 3 lO L38N 3 U5 3 IP_L12N_3 VREF_3 J7 VREF 3 lO L33N V1 y o 3 2 K1 LHCLK 3 lO 136 3 V3 DS610 4 v2 0 July 16 2007 www xilinx com 65 Product Specification Pinout Descriptions 5 XILINX Table 60 Spartan 3A DSP CS484 Pinout Continued Table 60 Spartan 3A DSP CS484 Pinout Continued
81. ILINX Table 65 Spartan 3A DSP FG676 Pinout for Table 65 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Continued XC3SD3400A FPGA Continued Bank XC3SD3400A Pin 9916 Bank XC3SD3400A Pin Name FG676 2 2 VCCO 3 lO L37N 3 R4 2 VCCO 2 14 VCCO 3 L40P 3 R5 o 2 VCCO 2 AB19 VCCO 3 140 Re O 3 lO L53P 3 Yi VO 3 L45N 3 R7 O 3 L53N 3 Y2 3 IO 145 3 O 3 IP 3 INPUT 3 IO 143 O 3 IO_L57P_3 Y5 3 IO L43P 3 VREF 3 R10 VREF 3 L57N 3 VO 3 IO L33P 3 LHCLK2 P1 3 IP 150 3 Wi L33N SIRDY2 LHCLK3 P2 LHCLK 3 IP 150 W2 VREF 3 IO 134 S LHCLK5 P3 LHCLK 3 IO 152 3 w3 3 IO L34P S LHCLK4 P4 LHCLK 3 L52N 3 w4 o 3 IO_L39N_3 Pe o 3 IO_L63N_3 we 3 IO_L39P_3 P7 o 3 IO_L63P_3 w7 3 141 3 PB o 3 IO L47P 3 vi o 3 IO L41N 3 P9 o 3 147 3 v2 Vo 3 IO 135 S LHCLK7 P10 3 IP L46N 3 INPUT 3 IO 3 N1 3 IO L49N 3 v5 Vo 3 L31N 3 O 3 IO L59N 3 VO 3 L30N 3 N4 3 IO L59P 3 v7 3 IO L30P 3 O 3 161 3 3 IO L32P 3 LHCLKO LHCLK
82. MOS25 is assigned to the Global Clock Input or the data Input If this is true of the Global Clock Input add the appropriate Input adjustment from Table 21 If this is true of the data Input subtract the appropriate Input adjustment from the same table When the hold time is negative it is possible to change the data before the clock s active edge 4 output jitter is included in all measurements DS610 3 v2 0 July 16 2007 www xilinx com 23 Product Specification and Sw itching Characteristics 5 XILINX Table 19 Setup and Hold Times for the IOB Input Path Speed Grade 5 4 IFD_DELAY_ Symbol Description Conditions VALUE Device Min Min Units Setup Times TioPICK Time from the setup of data at LYCMOS25 0 All 1 36 1 74 ns the Input pin to the active transition at the ICLK input of the Input Flip Flop IFF No Input Delay is programmed Tiopickp Time from the setup of data at 525 2 1 All 1 79 2 17 ns the Input pin to the active transition at the ICLK input of 2 All 2 55 2 92 ns the Input Flip Flop IFF The Input Delay is programmed Al SP 976 ns 4 All 3 75 4 32 ns 5 All 3 81 4 19 ns 6 All 4 39 5 09 ns 7 All 5 16 5 98 ns 8 All 5 69 6 57 ns Hold Times Time from the active transition 525 2 0 All 0 71 0 71 ns at the ICLK input of the Input Flip Flop IFF to the point w
83. Mode using Commodity Serial Flash Master BPI Mode using Commodity Parallel Flash Slave Parallel SelectMAP using a Processor Slave Serial using a Processor JTAG Mode ISE iMPACT Programming Examples MultiBoot Reconfiguration Design Authentication using Device Module 3 DC and Switching Characteristics 05610 3 v2 0 July 16 2007 e DC Electrical Characteristics Absolute Maximum Ratings Supply Voltage Specifications Recommended Operating Conditions e Switching Characteristics Timing Configurable Logic Block Timing Digital Clock Manager DCM Timing Block RAM Timing XtremeDSP Slice Timing Configuration and JTAG Timing Module 4 Pinout Descriptions DS610 4 v2 0 July 16 2007 e Pin Descriptions e Package Overview e Pinout Tables e Footprint Diagrams SPARTAN 3 224 SPARTAN 3A DSP www xilinx com spartan3adsp 2007 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm All other trademarks are the property of their respective owners All specifications are subject to change without notice DS610 July 16 2007 Product Specification www xilinx com 1 Data Sheet 5 XILINX No S NC SS AS of AS 2 XILINX Spartan 3A DSP FPGA Family Introduction and Ordering Information DS610 1 v2 0 July 16 2007
84. O 2 2 INPUT 3 L56N 3 U8 O 2 2 Y18 3 IO L61P 3 U9 O 2 IP_2 VREF_2 19 3 IO L38P 3 T3 O 2 2 W18 3 IO L38N 3 T4 O 2 2 INPUT 3 IO 142 3 T5 O 2 2 w11 VCCO 3 IO L51P 3 T7 O 2 2 wie 3 1 3 O 76 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout Descriptions Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued Bank XC3SD1800A Pin 70616 Bank XC3SD1800A Pin 70616 3 148 3 T10 3 IO L18N 3 L7 3 IO L36P 3 VREF 3 R1 VREF 3 IO L15N 3 L9 O 3 IO_L36N_3 R2 3 IO L15P 3 L10 O 3 IO L37P 3 R3 3 IP_L24N_3 INPUT 3 IO L37N 3 R4 3 IO L23N 3 K2 Te 3 IO 140 3 R5 3 IO 123 3 K3 O 3 IO_L40N_3 R6 3 IO L22N 3 K4 O 3 IO_L45N_3 R7 3 IO L22P 3 K5 Te 3 IO L45P 3 R8 3 IO 3 K6 O 3 IO_L43N_3 R9 3 IO L13P 3 K7 O 3 IO L43P 3 VREF 3 R10 VREF 3 IO LO5N 3 K8 O 3 IO L33P 3 LHCLK2 P1 LHCLK 3 IO LO5P 3 K9 O 3 IO_L33N_3 IRDY2 LHCLK3 P2 LHCLK 3 IP L24P 3 IN
85. O interface supports many popular single ended and differential standards Table 2 shows the number of user I Os as well as the number of differential I O pairs available for each device package combination Some of the user I Os are unidirectional input only pins as indicated in Table 2 Spartan 3A DSP FPGAs support the following single ended standards 3 3V low voltage TTL LVTTL e Low voltage CMOS LVCMOS at 3 3V 2 5V 1 8V 1 5V or 1 2V 3 3V PCI at 33 MHz 66 MHz Il and 1 5V 1 8V commonly used in memory applications SSTLI and 1 8V 2 5V and 3 3V commonly used for memory applications Spartan 3A DSP FPGAs support the following differential standards LVDS mini LVDS RSDS and PPDS at 2 5V or 3 3V e Bus LVDS I O at 2 5V TMDS at 3 3V e Differential HSTL and SSTL I O inputs at 2 5V 3 3V DS610 1 v2 0 July 16 2007 Product Specification 5 Introduction and Ordering Information eee LI DSP48A Slice EAVES m 06 DSP48A Slice Block DS610 1 01 031207 Notes 1 The XC3SD1800A and XC3SD3400A have two DCMs on both the left and right sides as well as the two DCMs the top and bottom of the devices The two on the left and right of the chips are in the middle of the outer Block RAM DSP48A columns of the 4
86. P are ideally suited to a wide range of consumer electronics applications including broadband access home networking display projection and digital television equipment The Spartan 3A DSP family is a superior alternative to mask programmed ASICs FPGAs avoid the high initial cost lengthy development cycles and the inherent inflexibility of conventional ASICs Also FPGA programmability permits design upgrades in the field with no hardware replacement necessary an impossibility with ASICs Features e Very low cost high performance DSP solution for high volume cost conscious applications e 250 MHz XtremeDSP DSP48A Slices Dedicated 18 bit by 18 bit multiplier Table 1 Summary of Spartan 3A DSP FPGA Attributes Product Specification Available pipeline stages for enhanced performance of at least 250 MHz in the standard 4 speed grade 48 bit accumulator for multiply accumulate MAC operation Integration added for complex multiply or multiply add operation Integrated 18 bit pre adder Optional cascaded Multiply or MAC ierarchical SelectRAM memory architecture Up to 2268 Kbits of fast block RAM with byte write enables for processor applications Up to 373 Kbits of efficient distributed RAM Registered outputs on the block RAM with operation of at least 280 MHz in the standard 4 speed grade e Dual range supply simplifies 3 3V only design e Suspend Hibernate modes reduce system powe
87. PUT 3 IO L34N 3 LHCLK5 P3 LHCLK 3 120 3 J2 VREF 3 IO L34P 3 LHCLK4 P4 LHCLK 3 IP L20P 3 J3 INPUT 3 IO L39N 3 P6 3 IO L19N 3 J4 O 3 IO L39P 3 P7 3 IO L19P 3 J5 O 3 IO_L41P_3 P8 3 IO L13N 3 J6 O 3 IO 14 3 P9 3 IO L10P 3 J7 O 3 IO_L35N_3 LHCLK7 P10 LHCLK 3 IO 101 3 J8 O 3 IO L31P 3 N1 3 IO LO1N 3 J9 O 3 IO L31N 3 N2 3 IO L17N 3 H1 O 3 IO_L30N_3 N4 3 IO L17P 3 H2 O 3 IO L30P 3 N5 3 IP_L12N_3 VREF_3 H4 VREF 3 IO L32P 3 LHCLKO N6 LHCLK 3 IO L10N 3 H6 O 3 IO_L32N_3 LHCLK1 N7 LHCLK 3 IO LO3N 3 H7 O 3 IO_L35P_3 TRDY2 LHCLK6 LHCLK 3 IP L16N 3 G1 INPUT 3 IO L29N 3 VREF 3 1 3 3 O 3 IO L29P 3 M2 3 LO9N 3 G4 O 3 IO_L27N_3 M3 3 IO LO3P 3 G6 O 3 IO L27P 3 M4 3 IO L11N 3 F2 O 3 IO L28P 3 M5 3 IO 114 3 F3 O 3 IO_L28N_3 M6 3 IO LO7N 3 F4 O 3 IO L26N 3 M7 3 IO_LO9P_3 5 O 3 IO L26P 3 M8 3 IO L11P 3 E1 O 3 IO L21N 3 M9 3 IO LO7P 3 E3 O 3 IO L21P 3 M10 3 3 4 O 3 IO_L25N_3 L3 3 IO 106 3 D3 O 3 IO L25P 3 L4 3 IP_LO4N_3 VREF_3 DS610 4 v2 0 July 16 2007 www xilinx com 77 Product Specification Pinout Descriptions 5 XILINX
88. UX VCCINT VCCINT M9 VCCINT VCCAUX VCCAUX AA21 VCCAUX VCCINT VCCINT M11 VCCINT VCCAUX B2 VCCAUX VCCINT VCCINT M13 VCCINT VCCAUX VCCAUX B21 VCCAUX VCCINT VCCINT M15 VCCINT VCCAUX VCCAUX D12 VCCAUX VCCINT VCCINT N8 VCCINT VCCAUX VCCAUX E5 VCCAUX VCCINT VCCINT N10 VCCINT VCCAUX VCCAUX E18 VCCAUX VCCINT VCCINT N12 VCCINT VCCAUX VCCAUX G10 VCCAUX VCCINT VCCINT N14 VCCINT VCCAUX VCCAUX G12 VCCAUX VCCINT VCCINT P9 VCCINT VCCAUX VCCAUX G14 VCCAUX VCCINT VCCINT P11 VCCINT VCCAUX VCCAUX J16 VCCAUX VCCINT VCCINT P13 VCCINT VCCAUX VCCAUX K7 VCCAUX VCCINT VCCINT P15 VCCINT VCCAUX VCCAUX 14 VCCAUX VCCINT VCCINT R8 VCCINT VCCAUX VCCAUX L16 VCCAUX VCCINT VCCINT R10 VCCINT VCCAUX VCCAUX M7 VCCAUX VCCINT VCCINT R12 VCCINT VCCAUX VCCAUX M19 VCCAUX VCCINT VCCINT R14 VCCINT VCCAUX VCCAUX N16 VCCAUX VCCINT 7 VCCINT VCCAUX VCCAUX P7 VCCAUX VCCINT VCCINT T16 VCCINT VCCAUX VCCAUX T9 VCCAUX VCCAUX VCCAUX T11 VCCAUX VCCAUX VCCAUX T13 VCCAUX VCCAUX V5 VCCAUX VCCAUX VCCAUX 18 VCCAUX VCCAUX VCCAUX W11 VCCAUX DS610 4 v2 0 July 16 2007 www xilinx com 67 Product Specification Pinout Descriptions User I Os by Bank Table 61 and Table 62 indicates how pins are distributed between the four I O banks on the 5484 Table 61 User I Os Per Bank the XC3SD1800A the CS484 Package 5 XILINX package The AWAKE pin is coun
89. VCCAUX VCCAUX VCCAUX GND GND AF16 GND VCCAUX VCCAUX AB22 VCCAUX GND GND AF21 GND VCCINT VCCINT 012 GND GND AF26 GND VCCINT VCCINT T11 VCCINT GND GND AD3 GND VCCINT VCCINT T13 VCCINT GND GND AD8 GND T15 VCCINT GND GND AD13 R12 GND GND 018 VCCINT VCCINT R14 VCCINT GND GND R16 GND GND AA1 GND VCCINT VCCINT P11 GND GND AAG GND VCCINT VCCINT P13 GND GND AA11 GND VCCINT VCCINT 14 VCCINT GND GND 16 GND 15 GND GND 21 GND VCCINT VCCINT N12 GND GND AA26 GND VCCINT VCCINT N13 VCCINT GND GND A1 GND VCCINT VCCINT N14 VCCINT GND GND A6 GND VCCINT VCCINT N16 VCCINT GND GND 11 GND VCCINT VCCINT M11 GND GND A16 GND VCCINT M13 VCCINT GND GND A21 GND VCCINT VCCINT M15 VCCINT GND GND A26 GND M17 VCCINT VCCAUX DONE AB21 CONFIG VCCINT VCCINT L12 VCCINT VCCAUX PROG B CONFIG L14 VCCINT VCCAUX G7 JTAG VCCINT VCCINT L16 VCCINT VCCAUX TDO E23 JTAG VCCINT VCCINT Ki5 VCCINT VCCAUX TMS D4 JTAG VCCAUX 25 JTAG VCCAUX VCCAUX V9 VCCAUX VCCAUX VCCAUX U14 VCCAUX VCCAUX VCCAUX T22 VCC
90. VTTL 0 62 0 62 ns LVCMOS33 0 54 0 54 ns LVCMOS25 0 00 0 00 ns LVCMOS18 0 83 0 83 ns LVCMOS15 0 60 0 60 ns LVCMOS12 0 31 0 31 ns PCI33 3 0 41 0 41 ns 66 3 0 41 0 41 ns PCIX 0 41 0 41 ns HSTL I 0 72 0 72 ns HSTL Ill 0 77 0 77 ns HSTL 1 18 0 69 0 69 ns HSTL 18 0 69 0 69 ns HSTL Ill 18 0 79 0 79 ns SSTL18 0 71 0 71 ns SSTL18 11 0 71 0 71 ns SSTL2 I 0 68 0 68 ns SSTL2 0 68 0 68 ns SSTL3 I 0 78 0 78 ns SSTL3 II 0 78 0 78 ns 26 Add the Convert Input Time from Adjustment Below role Speed Grade IOSTANDARD 5 4 Units Differential Standards LVDS 25 0 76 0 76 ns LVDS 33 0 79 0 79 ns BLVDS 25 0 79 0 79 ns MINI LVDS 25 0 78 0 78 ns MINI LVDS 33 0 79 0 79 ns LVPECL 25 0 78 0 78 ns LVPECL 33 0 79 0 79 ns RSDS 25 0 79 0 79 ns RSDS_33 0 77 0 77 ns TMDS 33 0 79 0 79 ns PPDS 25 0 79 0 79 ns PPDS 33 0 79 0 79 ns DIFF HSTL 18 0 74 0 74 ns DIFF HSTL 18 0 72 0 72 ns DIFF HSTL 18 1 05 1 05 ns DIFF HSTL 0 72 0 72 ns DIFF HSTL Ill 1 05 1 05 ns DIFF SSTL18 I 0 71 0 71 ns DIFF SSTL18 Il 0 71 0 71 ns DIFF SSTL2 0 74 0 74 ns DIFF SSTL2 1 0 75 0 75 ns DIFF 55113 1 06 1 06 ns DIFF SSTL3 Il 1 06 1 06 ns Notes 1 The numbers this table are tested using the methodology presented in Table 25 and are based on the operating conditions set forth in Table 7 Table 10 and Table 12 These adjustments are used to convert input path times originally specified for the I VCMOS25
91. Vo Vo L30P 3 L27P 3 L34N 3 L29N 3 L29P 3 VCCINT Internal core supply voltage 1 2V vo 5 130 3 L33P_3 127 3 L38P 3 L38N 3 L11N 2 L10N 2 VCCAUX Auxiliary supply 10 vo VO vo WO VO voltag e L33N 3 L36N 3 136 3 L11P 2 106 2 L10P 2 w vo vo vo aM EX wn L35N 3 L37N 3 137 3 VREF 2 LO3P 2 106 2 VREF 2 VO INPUT Vo vo vo L35P_3 139 3 z LO3N_2 L13P_2 113 2 INPUT vo vo ud M vo VO vo INPUT B Gees 2 LO4P_2 LO5P 2 105 2 108 2 Ta 2 Bank 2 Figure 16 5484 Package Footprint top view DS610 4 v2 0 July 16 2007 www xilinx com 69 Product Specification Pinout Descriptions 5 XILINX 12 VCCINT VCCINT VCCINT VCCINT INPUT L16P 2 GCLK14 L16N 2 Bank 0 13 14 15 16 17 18 19 20 Vo vo LO2N O LO7P O GND INPUT GND vo 1 GND VCCINT VCCINT GND VCCINT GND VCCINT GND INPUT VCCINT GND VCCINT VCCINT GND L21N 1 RHCLK7 VCCINT GND VCCINT GND L18N 1 RHCLK1 VCCINT GND VCCINT GND INPUT VCCINT GND GND L12P 1 105 1 vo INPUT v0 VREF 2 28 2 INPUT 2 GND VREF_2 o MEAN vo vo L21P_2 2 129 2 129 2 vo GND GND VCCINT L18N_2 L19P 2
92. agram see the XtremeDSP DSP48A for DSP FPGA User Guide 08431 Table 33 Setup Times for the DSP48A Speed Grade 5 4 Symbol Description Preadder Multiplier Postadder Min Min Units Setup Times of Data Control Pins to the Input Register Clock TDSPDCK_AA A input to A register CLK 0 04 0 04 5 TpsPDCk DB D input to B register CLK Yes E 1 64 1 88 ns TpsPDCK input to register CLK gt 0 05 0 05 5 TpsPpck D input to D register CLK 0 04 0 04 ns Tpsppck_opp OPMODE input to B register CLK Yes 0 37 0 42 5 TpsPpck OPMODE input to OPMODE register CLK 0 06 0 06 5 Setup Times of Data Pins the Pipeline Register Clock TpsPDCK AM A input to M register CLK Yes 3 30 3 79 5 B to M register Yes Yes 4 33 4 97 ns No Yes 3 30 3 79 5 DM input to register CLK Yes Yes 4 41 5 06 5 OPMODE to register CLK Yes Yes 4 72 5 42 ns Setup Times of Data Control Pins to the Output Register Clock TpsPDCK AP A input to P register CLK Yes Yes 4 78 5 49 ns TpsPpck BP B input to P register CLK Yes Yes Yes 5 87 6 74 ns No Yes Yes 4 77 5 48 ns TpsPDCk D input to P register CLK Yes Yes Yes 5 95 6 83 ns C input to P register CLK Yes 1 90 2 18 ns OPMODE
93. and Control Solutions Pin Types and Package Overview Package Drawings Powering FPGAs Power Management Revision History Product Specification UG332 Spartan 3 Generation Configuration User Guide Configuration Overview Configuration Pins and Behavior Bitstream Sizes Detailed Descriptions by Mode Master Serial Mode using Xilinx Platform Flash PROM Master SPI Mode using Commodity SPI Serial Flash PROM Master BPI Mode using Commodity Parallel NOR Flash PROM Slave Parallel SelectMAP using a Processor Slave Serial using a Processor Mode ISE iMPACT Programming Examples MultiBoot Reconfiguration Design Authentication using Device DNA Create a Xilinx MySupport user account and sign up to receive automatic E mail notification whenever this data sheet or the associated user guides are updated The following table shows the revision history for this document Date Version Revision 04 02 07 1 0 Initial Xilinx release 05 25 07 1 0 1 Minor edits 06 18 07 1 2 Updated for Production release 07 16 07 2 0 Added Low power options no changes to this module DS610 2 v2 0 July 16 2007 2007 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm All other trademarks are the property of their respective owners All specifications are subject to change
94. arameters used in Table 25 and Do not confuse the termination voltage from the IBIS model with input switching threshold from the table A fourth parameter is always zero The four parameters describe all relevant output test conditions IBIS models are found in the Xilinx development software as well as at the following link http www xilinx com xInx xil sw updates home jsp Delays for a given application are simulated according to its specific load conditions as follows 1 Simulate the desired signal standard with the output driver connected to the test setup shown in Figure 8 Simultaneously Switching Output Guidelines This section provides guidelines for the recommended maximum allowable number of Simultaneous Switching Outputs 5505 These guidelines describe the maximum number of user pins of a given output signal standard that should simultaneously switch in the same direction while maintaining a safe level of switching noise Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction The output drive transistors all conduct current to a common voltage Low to High transitions conduct to the Veco rail High to Low transitions conduct to the GND rail The resulting cumula
95. arger devices the same package Notes 1 bank number an integer between 0 and Package Pins by Type Each package has three separate voltage supply inputs VCCINT VCCAUX and VCCO and common ground return GND The numbers of pins dedicated to these functions vary by package as shown in Table 57 Table 57 Power and Ground Supply Pins by Package A majority of package pins are user defined I O or input pins However the numbers and characteristics of these I O depend on the device type and the package in which it is available as shown in Table 58 The table shows the maximum number of single ended I O pins available assuming that all INPUT DUAL VREF and Package Device CLK type pins are used as general purpose I O AWAKE is XC3SD1800A 36 24 24 84 counted here a Dual Purpose Likewise the table CS484 shows the maximum number of differential pin pairs XC3SD3400A 36 24 24 84 available on the package Finally the table shows how the XC3SD1800A 23 14 36 77 total maximum 1 are distributed by pin type FG676 XC3SD3400A 36 48 17406 including the number unconnected N C pins the device Table 58 Maximum User I O by Package All Possible I Os by Package Device and Input Differential VREF Input Onl
96. ble 15 For more complete more precise and worst case data use the values reported by the Xilinx static timing analyzer TRACE in the Xilinx development software and back annotated to the simulation netlist Table 15 Spartan 3A DSP v1 29 Speed Grade Designations Device Preview Advance Preliminary Production XC3SD1800A 4 5 XC3SD3400A 4 5 Table 16 provides the recent history of the Spartan 3A DSP FPGA speed files Table 16 Spartan 3A DSP Speed File Version History ISE Version Release Description Production Speed Files for 4 and 5 1 29 ISE 9 2 01i speed grades 1 28 ISE 9 2 Minor updates Advance Speed Files for 4 speed 1 27 ISE 9 1 03i grade DS610 3 v2 0 July 16 2007 www xilinx com 21 Product Specification and Switching Characteristics 5 Timing Table 17 Clock to Output Times for the Output Path Speed Grade 5 4 Symbol Description Conditions Device Max Max Units Clock to Output Times TICKOFDCM When reading from the Output LVCMOS25 2 12mA XC3SD1800A 3 28 3 51 ns Flip Flop OFF the time from the output drive Fast slew active transition on the Global rate with XC3SD3400A 3 36 3 82 ns Clock pin to data appearing at the Output pin The DCM is in use TickoF When reading from OFF the time VCMOS250 12 XC3SD1800A 5 23 5 58 ns from the active transition
97. cation Switching Characteristics 5 XILINX Table 24 Output Timing Adjustments for Continued Add the Adjustment Convert Output Time from Below wit Dr Speed Grade Signal Standard IOSTANDARD 5 4 Units Differential Standards LVDS_25 1 16 1 16 ns LVDS_33 0 46 0 46 ns BLVDS_25 0 11 0 11 ns MINI LVDS 25 0 75 0 75 ns MINI LVDS 33 0 40 0 40 ns LVPECL 25 nputs Only LVPECL 33 RSDS 25 1 42 1 42 ns RSDS 33 0 58 0 58 ns TMDS 33 0 46 0 46 ns PPDS 25 1 07 1 07 ns PPDS 33 0 63 0 63 ns DIFF HSTL 18 0 43 0 43 ns DIFF HSTL 18 0 41 0 41 ns DIFF HSTL 18 0 36 0 36 ns DIFF HSTL 1 01 1 01 ns DIFF HSTL 0 54 0 54 ns DIFF SSTL18 0 49 0 49 ns DIFF SSTL18 Il 0 41 0 41 ns DIFF SSTL2 0 82 0 82 ns DIFF SSTL2 II 0 09 0 09 ns DIFF SSTL3 I 1 16 1 16 ns DIFF SSTL3 II 0 28 0 28 ns Notes 1 The numbers in this table are tested using the methodology presented in Table 25 and are based on the operating conditions set forth in Table 7 Table 10 and Table 12 2 These adjustments are used to convert output and three state path times originally specified for LYVCMOS25 standard with 12 mA drive and Fast slew rate to times that correspond to other signal standards Do not adjust times that measure when outputs go into a high impedance state 30 www xilinx com DS610 3 v2 0 Ju
98. cteristics Configuration and JTAG Timing General Configuration Power On Reconfigure Timing VCCINT 1 2V Supply EON 2 5 Supply 2 0V 33V Vcco Bank 2 Supply PROG B Input INIT_B Open Drain peo CCLK Output DS529 3_01_112906 Notes 1 The Vecaux Veco supplies can be applied any order 2 The Low going pulse on PROG_B is optional after power on but necessary for reconfiguration without a power cycle 3 rising edge of INIT B samples the voltage levels applied to the mode pins M2 Figure 10 Waveforms for Power On and the Beginning of Configuration Table 44 Power On Timing and the Beginning of Configuration All Speed Grades Symbol Description Device Min Max Units 2 The time from the application of Vecaux and Veco All 18 ms Bank 2 supply voltage ramps whichever occurs last to the rising transition of the INIT_B pin width of the low going pulse on PROG B pin All 0 5 us Tp 2 The time from the rising edge of the PROG_B pin to the XC3SD1800A 2 ms rising transition on the INIT_B pin XC3SD3400A E 2 ms Minimum Low pulse width on INIT output All 300 5 The time from the rising edge of the pin to the All 0 5 4 us generation of the configuration clock signal at the CCLK output pin
99. data appearing 1 44 1 72 ns the distributed RAM output Setup Times Setup time data at the input before the active 0 07 0 02 ns transition at the CLK input of the distributed RAM Tas Setup time of the F G address inputs before the active transition 0 18 0 36 ns at the CLK input of the distributed RAM Tws Setup time of the write enable input before the active transition at 0 30 0 59 ns the CLK input of the distributed RAM Hold Times Hold time of the BY data inputs after the active transition 0 13 0 13 5 at the CLK input of the distributed Hold time of the F G address inputs or the write enable input after 0 01 0 01 ns the active transition at the CLK input of the distributed RAM Clock Pulse Width TwPL Minimum High or Low pulse width at CLK input 0 88 1 01 5 Table 30 Shift Register Switching Characteristics 5 4 Symbol Description Min Max Min Max Units Clock to Output Times TREG Time from the active edge at the CLK input to data appearing on 4 11 4 82 ns the shift register output Setup Times Tsni ps Setup time of data at the BX or BY input before the active 0 13 0 18 ns transition at the CLK input of the shift register Hold Times TsRLDH Hold time of the BX or BY data input after the active transition at 0 16 0 15 5 the CLK input of the shift register Clock Pulse Width Minimum High or Low p
100. data appearing at the pin 1 0 11 0 ns Setup Times The time from the setup of data at the All functions except those shown below 7 0 ns Ten the rising transition at the Boundary scai command 130 INTEST SAMPLE Ttmstck The time from the setup of a logic level at the TMS pin to the rising transition at the pin 7 0 ns Hold Times The time from the rising transition at All functions except those shown below 0 ns Configuration commands ISC_PROGRAM 3 5 from the rising transition at the pin to the point when a logic level is last held at the 0 5 Clock Timing The High pulse width the All functions except ISC_DNA command 5 ns The Low pulse width at the pin 5 ns The High pulse width at the During ISC_DNA command 10 10 000 ns Low pulse width at the pin 10 10 000 ns Frequency of the signal BYPASS or HIGHZ instructions 0 33 MHz All operations except for BYPASS or HIGHZ instructions 20 Notes 1 The numbers in this table are based on the operating conditions set forth in Table 7 56 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification 5 XILINX Switching Characteristics Revision History The following table shows the revision history for this document
101. depends on 1 MHz specific read command used CCLKn min Notes 1 These requirements are for successful FPGA configuration in SPI mode where the FPGA generates the CCLK signal The post configuration timing can be different to support the specific needs of the application loaded into the FPGA 2 additional printed circuit board routing delay as required by the application DS610 3 v2 0 July 16 2007 www xilinx com 53 Product Specification and Switching Characteristics 5 XILINX Byte Peripheral Interface Configuration Timing PROG_B Input X X X X X X X X PUDC B must be stable before INIT B goes High and constant throughout the configuration process M 2 0 v NN Mode input pins M 2 0 are sampled when INIT goes High After this point Input IN T eee input values do not matter until DONE goes High at which point the mode pins MINIT become 1 pins INIT B Open Drain T Pin initially pulled High by internal pull up resistor if input is Low Pin initially high impedance Hi Z if PUDC_B input is High LDC 2 0 ecccccccccccccccccccccccccce ME Ln E CSO New ConfigRate active Toop Data 1 S
102. design authentication Load multiple bitstreams under FPGA control and PicoBlaze embedded processor cores and CSP packaging with Pb free options footprints support easy density migration I CLB Array Four 5 Distributed Block System Equivalent Total Total RAM RAM Maximum Differential Device Gates Logic Cells Rows Columns CLBs Slices Bits DSP48As DCMs Pairs 501800 1800K 37 440 88 48 4160 16640 260 1512 84 8 519 227 503400 3400K 53 712 104 58 5968 23872 373 2268 126 8 469 213 Notes 1 By convention Kb is equivalent to 1 024 bits 2007 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm All other trademarks are the property of their respective owners All specifications are subject to change without notice DS610 1 v2 0 July 16 2007 Product Specification www xilinx com Introduction and Ordering Information Architectural Overview The Spartan 3A DSP family architecture consists of five fundamental programmable functional elements XtremeDSP DSP48A Slice provides 18 bit x 18 bit multiplier 18 bit pre adder 48 bit post adder accumulator and
103. difference between the ambient package offerings This information is also available using environment and the junction temperature The value is the Thermal Query tool at reported at different air velocities measured in linear feet http www xilinx com cgi bin thermal thermal pl per minute The Still Air 0 column shows the value in a system without a fan The thermal resistance drops with increasing air flow Table 59 Spartan 3A DSP Package Thermal Characteristics Junction to Ambient 0 4 ar TOT at Different Air Flows Package Device aaa 9 Board 0 4 Still Al Units ill Air 0 LFM 250 500 750 LFM CS484 XC3SD1800A 3 5 7 5 18 5 13 5 12 5 12 0 C W CSG484 XC3SD3400A 3 0 6 5 18 0 12 5 11 5 11 0 C W FG676 XC3SD1800A 5 0 8 5 16 5 12 0 11 0 10 5 C W FGG676 XC3SD3400A 4 0 7 0 15 5 11 0 10 0 9 5 C W Notes 1 Advance data based on simulation check for updates in the Thermal Query tool DS610 4 v2 0 July 16 2007 www xilinx com 61 Product Specification Pinout Descriptions 5 XILINX CS484 484 Ball Chip Scale Ball Grid Array The 484 ball chip scale ball grid array CS484 supports Table 60 Spartan 3A DSP CS484 Pinout Continued
104. e Max Max Units Propagation Times The time it takes for data to 525 2 0 All 1 50 1 97 ns travel from the Input pin through the IFF latch to the output with no input delay programmed The time it takes for data to LVCMOS25 2 1 All 1 93 2 40 ns travel from the Input pin through the IFF latch to the 2 All 2 69 3 15 ns output with the input delay 3 All 3 52 3 99 ns programmed 4 All 3 89 4 55 ns 5 All 3 95 4 42 ns 6 All 4 53 5 32 ns 7 All 5 30 6 21 5 8 All 5 83 6 80 ns Notes 1 numbers in this table are tested using the methodology presented in Table 25 and are based on the operating conditions set forth in Table 7 and Table 10 2 This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input When this is true add the appropriate Input adjustment from Table 21 DS610 3 v2 0 July 16 2007 www xilinx com 25 Product Specification Switching Characteristics 5 XILINX Table 21 Input Timing Adjustments IOSTANDARD Table 21 Input Timing Adjustments by IOSTANDARD Convert Input Time from LVCMOS25 to the Following Add the Adjustment Below Signal Standard Speed Grade IOSTANDARD 5 4 Units Single Ended Standards L
105. e used in a production quality system Whenever a speed file designation changes as a device matures toward Production status rerun the latest Xilinx ISE software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates Production designs will require updating the Xilinx ISE development software with a future version and or Service Pack All parameter limits are representative of worst case supply voltage and junction temperature conditions Unless otherwise noted the published parameter values apply to all Spartan 3A DSP devices AC and DC characteristics are specified using the same numbers for both commercial and industrial grades DS610 3 v2 0 July 16 2007 Product Specification 5 XILINX DC and Switching Characteristics To create a Xilinx MySupport user account and sign up for automatic E mail notification whenever this data sheet is updated e Sign Up for Alerts on Xilinx MySupport www xilinx com xInx xil ans display jsp getPagePath 19380 Timing parameters and their representative values are selected for inclusion below either because they are important as general design requirements or they indicate fundamental device performance characteristics The Spartan 3A DSP FPGA speed files v1 29 part of the Xilinx Development Software are the original source for many but not all of the values The speed grade designations for these files are shown in Ta
106. el NOR Flash PROM read access time ns 1 4 For x8 x16 PROMs only BYTE to output valid time T lt 5 BYTE Notes 1 These requirements for successful FPGA configuration in mode where the FPGA generates the CCLK signal The post configuration timing can be different to support the specific needs of the application loaded into the FPGA 2 Subtract additional printed circuit board routing delay as required by the application 3 initial BYTE timing can be extended using an external appropriately sized pull down resistor on the FPGA s LDC2 pin The resistor value also depends on whether the FPGA s PUDC B pin is High or Low DS610 3 v2 0 July 16 2007 Product Specification www xilinx com 55 and Switching Characteristics 5 XILINX IEEE 1149 1 1553 JTAG Test Access Port Timing TCK Input th Input Input TCKTDO TDO Output 05099 06 040703 Figure 15 JTAG Waveforms Table 55 Timing for the JTAG Test Access Port All Speed Grades Symbol Description Min Max Units Clock to Output Times The time from the falling transition on the pin to
107. es shown in parentheses are used in the IBIS file Figure 8 Output Test Setup Inputs and Signal Standard Inputs Outputs Outputs V 0 Single Ended LVTTL 0 3 3 1M 0 1 4 LVCMOS33 0 3 3 1 0 1 65 LVCMOS25 0 2 5 1 0 1 25 LVCMOS18 0 1 8 1M 0 0 9 LVCMOS15 0 1 5 1M 0 0 75 LVCMOS12 0 1 2 1M 0 0 6 3 Rising Note 3 Note 3 25 0 0 94 Falling 25 3 3 2 03 PCI66_3 Rising Note 3 Note 3 25 0 0 94 Falling 25 3 3 2 03 PCIX Rising Note 3 Note 3 25 0 0 94 Falling 25 3 3 2 03 0 75 0 5 0 5 50 0 75 VREF HSTL 0 9 0 5 0 5 50 1 5 VREF HSTL_I_18 0 9 0 5 0 5 50 0 9 VREF HSTL Il 18 0 9 0 5 0 5 25 0 9 VREF HSTL_III_18 1 1 0 5 0 5 50 1 8 VREF SSTL18_ 0 9 0 5 0 5 50 0 9 VREF SSTL18_ll 0 9 Vper 0 5 0 5 25 0 9 VREF 55112 1 25 Vngr 0 75 Veer 0 75 50 1 25 VREF SSTL2 II 1 25 Vngr 0 75 Vngr 0 75 25 1 25 VREF DS610 3 v2 0 July 16 2007 Product Specification www xilinx com 31 Switching Characteristics Table 25 Test Methods for Timing Measuremeni at I Os Continued 5 XILINX
108. esse 127 2 L43N 2 V V 9 vo vo L43P_2 147 2 V Bank 0 vo L15N_0 GND 107 0 L15P O B INPUT H J K L vo vo M L47N_1 L47P_1 L45P_1 L45N_1 Lo INPUT INPUT N L37N 1 L36N 1 L32N 1 vo vo IRDY1 Poor E p P RHCLK6 RHCLK1 RHCLKO RHCLK4 RHCLK3 R GND INPUT 1 0 VREF_1 U L14P_1 INPUT vREF 1 L10P 1 V GND LO4N_1 INPUT GND A vo vo L47P_2 1 B GND vo vo LO5N 1 LO6P 1 vo 105 1 vo A L48N_2 E INPUT 1 0 A VREF 2 148 2 2 1 Right Half FG676 Package top view 94 nx com DS610 4 v2 0 July 16 2007 Product Specification XILINX Pinout Descriptions Footprint Migration Differences There are multiple migration footprint differences between the XC3SD1800A and the XC3SD3400A in the FG676 package These migration footprint differences are shown in Table 67 Migration from the XC3S1400A Spartan 3A Table 67 FG676 Footprint Migration Differences device in the FG676 package to a Spartan 3A DSP device in the FG676 package is also possible The XC3S1800A pin migration differences have been added to Table 67 for designs migrating between these devices
109. f the clock signal No bitstream compression 0 80 MHz at the CCLK input pin EU With bitstream compression 0 80 MHz Notes 1 The numbers in this table are based the operating conditions set forth in Table 7 2 Some Xilinx documents refer to Parallel modes as SelectMAP modes DS610 3 v2 0 July 16 2007 www xilinx com 51 Product Specification and Switching Characteristics 5 XILINX Serial Peripheral Interface SPI Configuration Timing PROG_B Input PUDC_B X X X X X X X X PUDC B must be stable before INIT B goes High and constant throughout the configuration process Input VS 2 0 Input Mode input pins M 2 0 and variant select input pins VS 2 0 are sampled when INIT B goes High After this point input values do not matter until DONE goes High at which oint these pins become user l O pins UT DD Input INIT_B Open Drain New ConfigRate active EUER RET Input 1 71 T MOSI Pin initially pulled High by internal pull up resistor if input is Low Pin initially high impedance Hi Z if PUDC_B input is High External pull up resistor required on CSO_B Shaded values indicate specifications on attached SPI Flash PROM DS529 3 06 102506 Figure 13
110. fting MAX STEPS e ns DCM DELAY STEP MAX Notes 1 The numbers in this table are based on the operating conditions set forth in Table 7 and Table 39 2 The maximum variable phase shift range MAX STEPS is only valid when the DCM is has no initial fixed phase shifting that is the PHASE SHIFT attribute is set to O 3 The DCM DELAY STEP values are provided at the bottom of Table 36 Miscellaneous DCM Timing Table 41 Miscellaneous DCM Timing Symbol Description Min Max Units 5 PW MIN Minimum duration of a RST pulse width 3 CLKIN cycles 44 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification XILINX DC Switching Characteristics DNA Port Timing Table 42 DNA_PORT Interface Timing Symbol Description Min Max Units TpNAssU Setup time on SHIFT before the rising edge of CLK 1 0 5 TpNAsH Hold time on SHIFT after the rising edge of CLK 0 5 5 TpNADSU Setup time on DIN before the rising edge of CLK 1 0 5 TpNADH Hold time on DIN after the rising edge of CLK 0 5 5 TpNARSU Setup time on READ before the rising edge of CLK 5 0 10 000 ns TpNARH Hold time on READ after the rising edge of CLK 0 0 5 TpNADCKO Clock to output delay on DOUT after rising edge of CLK 0 5 1 5 ns TDNACLKE CLK frequency 0 0 100 MHz CLK High time 1 0 5 TpNACLKH CLK Low time 1 0 5
111. g Characteristics x XILINX Power Supply Specifications Table 4 Supply Voltage Thresholds for Power On Reset Symbol Description Min Max Units Threshold for the supply 0 4 10 VCCAUXT Threshold for the Vecaux supply 0 8 2 0 V Threshold for the Bank 2 supply 0 8 20 V Notes 1 VccAUx and Veco supplies to the FPGA can be applied in any order However the FPGA s configuration source Platform Flash SPI Flash parallel NOR Flash microcontroller might have specific requirements Check the data sheet for the attached configuration source Apply last for lowest overall power consumption see the UG331 chapter titled Powering Spartan 3 Generation FPGAs for more information 2 ensure successful power on Bank 2 and supplies must rise through their respective threshold voltage ranges with no dips at any point Table 5 Supply Voltage Ramp Rate Symbol Description Min Max Units Ramp rate from GND to valid supply level 0 2 100 ms VCCAUXR Ramp rate from GND to valid supply level 0 2 100 ms Ramp rate from GND to valid Veco Bank 2 supply level 0 2 100 ms Notes 1 Vecaux and Veco supplies to the FPGA can be applied any order However FPGA s configuration source Platform Flash SPI Flash para
112. haded values indicate specifications on attached parallel NOR Flash PROM DS529 3 05 112906 Figure 14 Waveforms for Byte wide Peripheral Interface Configuration Table 53 Timing for Byte wide Peripheral Interface BPI Configuration Mode Symbol Description Minimum Maximum Units Initial CCLK clock period see Table 45 CCLK clock period after FPGA loads ConfigRate setting see Table 45 Setup time on M 2 0 mode pins before the rising edge of INIT 50 ns Hold time M 2 0 mode pins after the rising edge of 0 ns Minimum period of initial A 25 0 address cycle LDC 2 0 and HDC are asserted 5 5 and valid cycles Toco Address A 25 0 outputs valid after CCLK falling edge See Table 49 Setup time on D 7 0 data inputs before falling edge See Table 50 Hold time D 7 0 data inputs after CCLK falling edge 0 ns 54 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification 5 XILINX Switching Characteristics Table 54 Configuration Timing Requirements for Attached Parallel NOR Flash Symbol Description Requirement Units Tce Parallel NOR Flash PROM chip select time 1 lt 5 INITADDRh Parallel NOR Flash PROM output enable time T lt 5 OE INITADDR Parall
113. here data must be held at the Input pin No Input Delay is programmed Tioickpp Time from the active transition LVCMOS25 1 All 1 60 1 60 ns at the ICLK input of the Input Flip Flop IFF to the point 2 All 2 06 2 06 5 where must be held the Input pin The Input Delay is 9 e ns programmed 4 All 2 86 2 86 ns 5 All 2 88 2 88 ns 6 All 3 24 3 24 ns 7 All 3 55 3 55 ns 8 All 3 89 3 89 ns Set Reset Pulse Width Trew iog Minimum pulse width to SR All 1 33 1 61 ns control input Notes 1 The numbers in this table are tested using the methodology presented in Table 25 and are based on the operating conditions set forth in Table 7 and Table 10 2 This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input If this is true add the appropriate Input adjustment from Table 21 3 These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input If this is true subtract the appropriate Input adjustment from Table 21 When the hold time is negative it is possible to change the data before the clock s active edge 24 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification 5 XILINX DC and Switching Characteristics Table 20 Propagation Times for the IOB Input Path Speed Grade 5 4 Symbol Description Conditions IFD_Delay_Value Devic
114. ignal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output When this is true add the appropriate Output adjustment from Table 24 Table 23 Timing for the Three State Path Speed Grade 5 4 Symbol Description Conditions Device Max Max Units Synchronous Output Enable Disable Times TIOCKHZ Time from the active transition at the LVCMOS25 12 mA All 1 13 1 39 ns input of the Three state Flip Flop to when output drive Fast slew the Output pin enters the high impedance state rate 2 Time from the active transition at TFF s All 3 08 3 35 ns input to when the Output pin drives valid data Asynchronous Output Enable Disable Times Time from asserting Global Three State LVCMOS25 12 mA All 9 47 10 36 ns GTS input on the STARTUP_SPARTAN3A output drive Fast slew primitive to when the Output pin enters the rate high impedance state Set Reset Times Time from asserting TFF s SR input to when LVCMOS25 12 mA All 1 61 1 86 ns the Output pin enters a high impedance state output drive Fast slew rate Time from asserting SR input at TFF to All 3 57 3 82 ns when the Output pin drives valid data Notes 1 numbers in this table are tested using the methodology presented in Table 25 and are based on the operating conditions set fo
115. in to write protect lock on all writable clocked lt 5 elements TsUSPEND DISABLE Rising edge of the SUSPEND pin to FPGA input pins and interconnect 340 ns disabled Exiting Suspend Mode TsusPENDLOW AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin Does 4 to 108 us include DCM lock time TsUSPEND ENABLE Falling edge of the SUSPEND pin to FPGA input pins and interconnect 13 710109 7 re enabled TAWAKE GWE1 Rising edge of the AWAKE pin until write protect lock released on all writable 67 7 clocked elements using sw clk InternalClock sw 1 TAWAKE GWEB12 Rising edge of the AWAKE pin until write protect lock released on all writable 14 5 clocked elements using sw_clk InternalClock and sw_gwe_cycle 512 TAWAKE GTS1 Rising edge of the AWAKE pin until outputs return to the behavior described 57 ns 7 the FPGA application using sw clk InternalClock and sw gts 1 TAWAKE GTS512 Rising edge of the AWAKE pin until outputs return to the behavior described 14 us the FPGA application using sw clk InternalClock and sw_gts_cycle 512 Notes 1 These parameters based on characterization 2 For information on using the Spartan 3A DSP Suspend feature see XAPP480 Using Suspend Mode in Spartan 3 Generation FPGAs 46 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification 5 XILINX DC and Switching Chara
116. ional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied Exposure to absolute maximum conditions for extended periods of time adversely affects device reliability Symbol Description Conditions Min Max Units Vecint Internal supply voltage 0 5 1 32 V Vccaux Auxiliary supply voltage 0 5 3 75 V Output driver supply voltage 0 5 3 75 V Input reference voltage 0 5 0 5 V Voltage applied to all User pins and Driver in a high impedance state 20 05 46 V Dual Purpose pins Voltage applied to all Dedicated pins 0 5 4 6 V Vesp Electrostatic Discharge Voltage Human body model 2000 V Charged device model 500 V Machine model 200 V Junction temperature 125 C Storage temperature 65 150 Notes 1 For soldering guidelines see UG112 Device Packaging and Thermal Characteristics and XAPP427 Implementation and Solder Reflow Guidelines for Pb Free Packages 2007 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at http www xilinx com legal htm All other trademarks are the property of their respective owners All specifications are subject to change without notice DS610 3 v2 0 July 16 2007 Product Specification www xilinx com 11 and Switchin
117. ions of samples In a histogram of period jitter the mean value is the clock period Cycle cycle jitter is the worst case difference in clock period between adjacent clock cycles in the collection of clock periods sampled In a histogram of cycle cycle jitter the mean value is zero Table 35 Recommended Operating Conditions for the DLL Symbol Description Input Frequency Ranges Speed Grade 5 4 Units FREQ DLL Frequency of the CLKIN clock input 5 2 2800 5 2 2503 MHz Input Pulse Requirements CLKIN_PULSE CLKIN pulse width as a lt 150 MHz 40 60 40 60 9 ofthe 150 MHz 45 55 45 55 Input Clock Jitter Tolerance and Delay Path Variation CLKIN_CYC_JITT_DLL_LF Cycle to cycle jitter at the lt 150 MHz 300 300 ps CLKIN_CYC_JITT_DLL_HF CERIN input gt 150 2 ___ 150 5 150 5 CLKIN PER JITT DLL Period jitter at the CLKIN input 1 1 5 CLKFB DELAY VAR EXT Allowable variation of off chip feedback delay from 1 1 ns the DCM output to the CLKFB input Notes 1 DLL specifications apply when any of the DLL outputs CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV are in use 2 DFS when operating independently of the DLL supports lower FCLKIN frequencies See Table 37 3 To
118. llel NOR Flash microcontroller might have specific requirements Check the data sheet for the attached configuration source Apply last for lowest overall power consumption see the UG331 chapter titled Powering Spartan 3 Generation FPGAs for more information 2 ensure successful power on Bank 2 and supplies must rise through their respective threshold voltage ranges with no dips at any point Table 6 Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch CCL Contents and RAM Data Symbol Description Min Units level required to retain CMOS Configuration Latch CCL and RAM data 1 0 V VpRAUX level required to retain CMOS Configuration Latch CCL and RAM data 2 0 V General Recommended Operating Conditions Table 7 General Recommended Operating Conditions Symbol Description Min Nominal Max Units Tj Junction temperature Commercial 0 85 Industrial 40 100 Internal supply voltage 1 140 1 200 1 260 V Output driver supply voltage 1 100 3 600 V VCCAUX Auxiliary supply voltage Vocaux 2 5 2 250 2 500 2 750 V Vecaux 3 3 3 000 3 300 3 600 V TiN Input signal transition time 2 500 ns Notes 1 This range spans the lowest and highest operating voltages for all supported I O standards Table 10 lists the rec
119. ly 16 2007 Product Specification lt XILINX DC and Switching Characteristics Timing Measurement Methodology When measuring timing parameters at the programmable I Os different signal standards call for different test conditions Table 25 lists the conditions to use for each standard open connection is set to zero The same measurement point Vy that was used at the Input is also The method for measuring Input timing is as follows A signal that swings between a Low logic level of V and a High logic level of is applied to the Input under test Some standards also require the application of a bias voltage to the pins of a given bank to properly set the input switching threshold The measurement point of the Input signal is commonly located halfway between V and The Output test setup is shown in Figure 8 A termination voltage V4 is applied to the termination resistor the other end of which is connected to the Output For each standard and generally take on the standard values recommended for minimizing signal reflections If the standard does not ordinarily use terminations for example LVCMOS LVTTL then is set to 1 to indicate an Table 25 Test Methods for Timing Measurement at 5 used at the Output FPGA Output idi 5 T C DS312 3 04 102406 Notes 1 The nam
120. mbers in this table are based on the conditions set forth in Table 7 and Table 10 Descriptions of the symbols used in this table are as follows lo output current condition under which Vo is tested the output current condition under which is tested Vo the output voltage that indicates a Low logic level the output voltage that indicates a High logic level the input voltage that indicates a Low logic level the input voltage that indicates a High logic level the supply voltage for output drivers Vrer the reference voltage for setting the input switching threshold the voltage applied to a resistor termination For the LVCMOS and LVTTL standards the same and limits apply for both the Fast and Slow slew attributes These higher drive output standards are supported only on FPGA banks 1 and 3 Inputs are unrestricted See the chapter Using I O Resources in UG331 Tested according to the relevant PCI specifications DS610 3 v2 0 July 16 2007 Product Specification 5 XILINX DC and Switching Characteristics Differential I O Standards is Internal Logic X P Differential N I O Pair Pins GND level ine Input common mode voltage Differential input voltage 7 Vinn DS610 3_03_061507 Figure 3 Differential Input Voltages
121. ngle Ended Standards Veco for Drivers VREF Attribute Min V Nom V Max V Min V Nom V Max V Max V Min V 3 0 33 3 6 0 8 2 0 LVCMOS33 4 3 0 33 3 6 0 8 2 0 825 45 2 3 2 5 2 7 0 7 1 7 LVCMOS18 9 1 65 1 8 1 95 0 38 0 8 LVCMOS15 9 14 1 5 1 6 0 38 0 8 LVCMOS12 4 1 1 1 2 1 3 0 38 0 8 PCI33 3 3 0 3 3 3 6 0 3 Vcco 0 5 66 3 3 0 3 3 3 6 0 3 0 5 3 0 3 3 3 6 0 35 0 5 HSTL 1 4 1 5 1 6 0 68 0 75 0 9 0 1 0 1 HSTL Ill 14 1 5 1 6 0 9 0 1 0 1 HSTL 18 1 7 1 8 1 9 0 8 0 9 1 1 0 1 Vper 0 1 HSTL Il 18 1 7 1 8 1 9 0 9 0 1 0 1 HSTL 18 1 7 1 8 1 9 1 1 0 1 0 1 551118 17 1 8 1 9 0 833 0 900 0 969 0 125 0 125 551 18 II 1 7 1 8 1 9 0 833 0 900 0 969 0 125 0 125 55712 23 2 5 27 1 15 1 25 1 38 0 150 Vag 0 150 SSTL2_II 23 2 5 2 7 1 15 1 25 1 38 0 150 0 150 55113 3 0 3 6 13 1 5 17 0 2 0 2 SSTL3 II 3 0 3 3 3 6 1 3 1 5 1 7 Vper 0 2 0 2 Notes 1 Descriptions of the symbols used in this table are as follows the supply voltage for output drivers the reference voltage
122. o 2 IP 2 Y12 INPUT 2 IO L23N 2 AB18 y o 2 lO L21P 2 Y13 64 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification 5 XILINX Pinout Descriptions Table 60 Spartan 3A DSP CS484 Pinout Continued Table 60 Spartan 3A DSP CS484 Pinout Continued Bank Pin Name a Type Bank Pin Name EM Type 2 IP 2 VREF 2 Y14 VREF lO L17P 3 K2 2 IO L24N 2 03 Y15 DUAL 3 L17N 3 K3 2 129 2 16 y o 3 lO L13P 3 2 129 2 17 yo 3 3 5 2 IO L26P 2 D2 Y18 DUAL 3 lO L15P 3 K6 y o 2 IO L26N 2 D1 Y19 DUAL 3 L19N S IRDY2 LHCLKS 111 LHCLK 2 VCCO 2 5 VCCO 3 L20P 3 LHCLK4 L3 LHCLK 2 VCCO 2 AA9 VCCO 3 lO L15N 3 L5 y o 2 VCCO 2 AA13 VCCO 3 lO L18P 3 LHCLKO L6 LHCLK 2 VCCO 2 AA18 VCCO 3 lO L22P 3 VREF 3 M1 VREF 2 VCCO 2 V9 VCCO 3 L20N S LHCLK5 M2 LHCLK 2 VCCO 2 V14 VCCO 3 IP L23P 3 INPUT 3 IP_L389N_3 VREF_3 1 3 L18N S LHCLK1 M5 LHCLK 3 IO LO2N C1 y o 3 2 3 TRDY2 LHCLK6 M6 LHCLK 3 IO LO2P 3 C2 y o 3 lO L22N 3 N1 3 IP_LO4P_3 D1 INPUT 3 IP_L31P_3 N3 INPUT 3 IP_LO8P_3 D3 INPUT 3 IP_L23N_3 N4 INPUT 3 IP_LO8N_3 D4 INPUT 3 124 3 5 3 IP_LO4N_3 VREF_3 E1 VR
123. ommended range specific to each of the single ended 1 standards and Table 12 lists that specific to the differential standards 2 Measured between 10 and 90 12 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification XILINX General DC Characteristics for I O Pins DC and Switching Characteristics Table 8 General DC Characteristics of User I O Dual Purpose and Dedicated Pins Symbol Description Test Conditions Min Typ Max Units IL Leakage current at User I O Driver is in a high impedance state 10 10 Input only Dual Purpose and Vin OV Veco sample tested Dedicated pins powered lus Leakage current on pins during All pins except INIT_B PROG_B DONE and JTAG pins 10 10 hot socketing FPGA unpowered When PUDC B 1 INIT_B PROG_B DONE and JTAG pins or other pins Add lus _ 0 Current through pull up resistor Vin GND Vecaux 3 0V to 3 6 151 315 710 pA at User I O Dual Purpose Input only and Dedicated pins Vecaux 2 3V to 2 7 82 182 437 Dedicated pins powered by V 1 7V to 1 9V 36 88 226 269 E is 14V to 1 6V 22 56 148 1 14 10 1 26 11 31
124. on FPGA User Guide http www xilinx com bvdocs userguides ug331 pdf Spartan 3A DSP FPGAs are available in both standard and Product Specification Except for the thermal characteristics all information for the standard package applies equally to the Pb free package Pin Types Most pins on a Spartan 3A DSP FPGA are general purpose user defined pins There however up to 12 different functional types of pins on Spartan 3A DSP packages as outlined in Table 56 In the package footprint drawings that follow the individual pins Pb free RoHS versions of each package with the Pb free version adding a to the middle of the package code Table 56 Types of Pins on Spartan 3A DSP FPGAs are color coded according to pin type as in the table connected Description Pin Name s in Type Unrestricted general purpose pin Most pins can be paired together to form differential I Os IO Lxxy INPUT Unrestricted general purpose input only pin This pin does not have an output structure IP or PCI clamp diode Lxxy Dual purpose pin used in some configuration modes during the configuration process and M 2 0 then usually available as a user after configuration If the pin is not used during PUDC B configuration this pin behaves as an pin See UG332 Spartan 3 Generation CCLK Configuration User Guide for additional information on these signal
125. on Input only pairs 2 5V 10 LVDS 25 1 8 25 90 110 Q RSDS_25 Notes 1 The numbers in this table are based on the conditions set forth in Table 7 2 This parameter is based on characterization The pull up resistance Vcco Igpy The pull down resistance Rpp Vin DS610 3 v2 0 July 16 2007 www Xilinx com 13 Product Specification and Switching Characteristics 5 XILINX Quiescent Current Requirements Table 9 Quiescent Supply Current Characteristics Commercial Industrial Symbol Description Device Power Typical 2 Maximum Maximum Units Quiescent Supply current XC3SD1800A 55 30 80 mA LI 45 175 mA XC3SD3400A 80 550 725 Ll 70 300 Quiescent supply current XC3SD1800A 0 4 4 5 Ll 0 2 5 mA XC3SD3400A 0 4 4 5 Ll 0 2 5 mA lecauxo Quiescent VccAux supply current XC3SD1800A 42 90 110 mA Ll 38 72 mA XC3SD3400A 70 130 160 Ll 65 105 mA Notes 1 The numbers in this table are based the conditions set forth in Table 7 2 Quiescent supply current is measured with all I O drivers in a high impedance state and with all pull up pull down resistors at the I O pads disabled Typical values are characterized using typical devices at ambient room temperature T4 of 25 C at 1 2V Veco 3
126. on the output drive Fast slew Global Clock pin to data appearing rate without DCM XC3SD3400A 5 51 6 13 ns at the Output pin The DCM is not in use Notes 1 The numbers in this table are tested using the methodology presented in Table 25 and are based on the operating conditions set forth in Table 7 and Table 10 2 This clock to output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output If the former is true add the appropriate Input adjustment from Table 21 If the latter is true add the appropriate Output adjustment from Table 24 3 DOM output jitter is included in all measurements 22 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification 5 and Switching Characteristics Table 18 Pin to Pin Setup and Hold Times for the IOB Input Path System Synchronous Speed Grade 5 4 Symbol Description Conditions Device Min Min Units Setup Times TPspcM When writing to the Input LVCMOS256 XC3SD1800A 2 65 3 11 ns Flip Flop IFF the time from IFD DELAY VALUE 0 the setup of data the Input with DOM XC3SD3400A 2 25 2 49 ns pin to the active transition at a Global Clock pin The DCM is use No Input Delay is programmed When writing IFF the
127. or 5 columns in the selected device as shown in the diagram above 2 A detailed diagram of the DSP48A can be found in UG431 XtremeDSP DSP48A for Spartan 3A DSP FPGAs User Guide Figure 1 Spartan 3A DSP Family Architecture Table 2 Available User I Os and Differential Diff Pairs CS484 FG676 Device EDT ee User Diff User Diff 309 140 519 227 XC3SD1800A 60 78 110 131 309 140 469 213 XC3SD3400A 60 78 60 117 Notes 1 The number shown bold indicates the maximum number of I O and input only pins The number shown in italics indicates the number of input only pins The differential Diff pin count includes both differential pairs on input only pins and differential pairs on pins within I O banks that are restricted to differential inputs DS610 1 v2 0 July 16 2007 www xilinx com 5 Product Specification Introduction Ordering Information XILINX Package Marking Figure 2 shows the top marking for Spartan 3A DSP The Sc and 41 Speed Grade Temperature Range part FPGAs Use the seven digits of the Lot Code to access combinations may be dual marked as 5 4 additional information for a specific device using the Xilinx web based Genealogy Viewer Mask Revision BGA Ball A1 Fabrication 5 Date Code Low Power optional
128. r Low power option reduces quiescent current e Multti voltage multi standard SelectlO M interface pins Up to 519 I O pins or 227 differential signal pairs LVCMOS LVTTL HSTL and SSTL single ended 3 3V 2 5V 1 8V 1 5V 1 2V signaling Selectable output drive up to 24 mA per pin QUIETIO standard reduces I O switching noise Full 3 3V 1096 compatibility and hot swap compliance 622 Mb s data transfer rate per differential I O LVDS RSDS mini LVDS HSTL SSTL differential I O with integrated differential termination resistors Enhanced Double Data Rate DDR support DDR DDR2 SDRAM support up to 333 Mb s Fully compliant 32 64 bit 33 66 MHz PCI support Abundant flexible logic resources Densities up to 53712 logic cells including optional shift register Efficient wide multiplexers wide logic Fast look ahead carry logic IEEE 1149 1 1532 JTAG programming debug port e Eight Digital Clock Managers DCMs Clock skew elimination delay locked loop Frequency synthesis multiplication division High resolution phase shifting Wide frequency range 5 MHz to over 320 MHz e low skew global clock networks eight additional clocks per half device plus abundant low skew routing e Configuration interface to industry standard PROMs Low cost space saving SPI serial Flash PROM 8 8 16 parallel NOR Flash PROM Low cost Xilinx Platform Flash with JTAG Unique Device DNA identifier for
129. ristics of User l Os Using Differential Signal Standards Vop VoL IOSTANDARD Attribute Min mV Typ mV Max mV Min V Typ V Max V Min V Max V 1906825 247 350 454 115 185 LVDS 33 247 350 454 1 125 1 375 BLVDS_25 240 350 460 1 30 MINI LVDS 25 300 600 1 0 1 4 MINI LVDS 33 300 600 1 0 1 4 RSDS 25 100 400 1 0 1 4 0 _33 100 400 1 0 1 4 TMDS_33 400 800 Veco 0 405 Vcco 0 190 PPDS 25 100 400 0 5 0 8 1 4 PPDS_33 100 400 0 5 0 8 1 4 DIFF HSTL I 18 Veco 0 4 0 4 DIFF HSTL 18 Vcco 0 4 0 4 DIFF HSTL Ill 18 Veco 0 4 0 4 DIFF HSTL Veco 0 4 0 4 DIFF HSTL III Veco 0 4 0 4 DIFF 551118 0 475 0 475 DIFF SSTL18 1 0 475 0 475 DIFF SSTL2 0 61 0 61 DIFF SSTL2 Il 0 81 0 81 DIFF 55113 0 6 0 6 DIFF SSTL3 Il Vr 0 8 0 8 5 1 The numbers in this table are based on the conditions set forth Table 7 and Table 12 2 See External Termination Requirements for Differential 3 Output voltage measurements for all differential standards are made with a termination resi
130. rth in Table 7 and Table 10 2 This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output When this is true add the appropriate Output adjustment from Table 24 DS610 3 v2 0 July 16 2007 Product Specification www xilinx com 27 and Switching Characteristics 5 Table 24 Output Timing Adjustments for Table 24 Output Timing Adjustments for Continued Add the Add the Adjustment Adjustment Convert Output Time from Below Convert Output Time from Below Pact Slew Rate tothe Following Peed Grade Fast Slew Rate to the Following Speed Grade Signal Standard J OSTANDARD 5 4 Units Signal Standard IOSTANDARD 5 4 Units Single Ended Standards 1 33 Slow 2mA 558 558 ns LVTTL Slow 2 5 58 5 58 ns 4 mA 3 17 3 17 ns 4 mA 3 16 3 16 ns 6 mA 3 17 3 17 ns 6 mA 3 17 3 17 ns 8 2 09 2 09 ns 8 2 09 2 09 ns 12 mA 1 24 1 24 ns 12 mA 1 62 1 62 ns 16 mA 1 15 1 15 ns 16 mA 1 24 1 24 ns 24 mA 2 55 2 55 ns 24 mA 2 74 2 74 ns Fast 2 mA 3 02 3 02 ns Fast 2 mA 3 03 3 03 ns 4 mA 1 71 1 71 ns 4 mA 1 71 1 71 ns 6 mA 1 72 1 72 ns 6 mA 1 71 1 71 ns 8 0 53 0 53 ns 8 0 53 0 53 ns 12 mA 0 59 0 59 ns 12 mA 0 53 0 53 ns 16 mA
131. s MOSI CSI B D 7 1 DO DIN CSO B RDWR B INIT B A 25 0 VS 2 0 LDC 2 0 HDC Dual purpose pin that is either a pin or Input only pin or along with all other IP VREF VREF pins in the same bank provides a reference voltage input for certain I O standards Lxxy amp VREF s If used for a reference voltage within a bank all VREF pins within the bank must be IO VREF Lxxy Either a or an input to a specific clock buffer driver Packages have 16 global clock inputs that optionally clock the entire device The RHCLK inputs optionally clock the right half of the device The LHCLK inputs optionally clock the left half of the device See the Using Global Clock Resources chapter in UG331 Spartan 3 Generation FPGA User Guide for additional information on these signals IO Lxxy amp GCLK 15 0 IO Lxxy amp LHCLK 7 0 IO Lxxy amp RHCLK 7 0 Dedicated configuration pin two per device Not available as a pin Every package has two dedicated configuration pins These pins are powered See the UG332 Spartan 3 Generation Configuration User Guide for additional information on the DONE and PROG B signals DONE PROG B Control and status pins for the power saving Suspend mode SUSPEND is a dedicated pin AWAKE is a Dual Purpose pin Unless Suspend mode is enabled in the application AWAKE is available as a pin SUSPEND AWAKE
132. s supply only differential output drivers not input circuits 2 must be less than 3 These true differential output standards are supported only on FPGA banks 0 and 2 Inputs are unrestricted See the chapter Using I O Resources in UG331 4 External Termination Requirements for Differential I O 5 LVPECL is supported on inputs only not outputs Requires Vocayx 3 3V 10 6 LVPECL 33 maximum Vccaux Vip 2 7 Requires 3 3V 10 Vecaux 300 mV lt Vicm lt 37 mV 8 These higher drive output standards are supported only on FPGA banks 1 3 Inputs are unrestricted See the chapter Using I O Resources 00331 9 Vngr inputs are used for the DIFF SSTL and DIFF_HSTL standards The settings are the same as for the single ended versions in Table 11 Other differential standards do not use DS610 3 v2 0 July 16 2007 www xilinx com 17 Product Specification and Switching Characteristics 5 XILINX Logic V OUTP e t Differential Internal N Pair Pins VourP GND level Voure VourN 2 Output differential voltage Voutn Output common mode voltage Output voltage indicating a High logic level VoL Output voltage indicating a Low logic level DS312 3 03 102406 Figure 4 Differential Output Voltages Table 13 DC Characte
133. sively available in the CS G 484 package and Industrial temperature range 6 www xilinx com DS610 1 v2 0 July 16 2007 Product Specification 5 XILINX Introduction and Ordering Information Revision History The following table shows the revision history for this document Date Version Revision 04 02 07 1 0 Initial Xilinx release 05 25 07 1 0 1 Minor edits 06 18 07 1 2 Updated for Production release 07 16 07 2 0 Added Low power options DS610 1 v2 0 July 16 2007 Product Specification www xilinx com Introduction and Ordering Information 5 XILINX 8 www xilinx com DS610 1 v2 0 July 16 2007 Product Specification 2 XILINX Spartan 3A DSP FPGA Family Functional Description DS610 2 v2 0 July 16 2007 Introduction The functionality of the Spartan 3A DSP FPGA family is described in the following documents The topics covered in each guide are listed below UG431 XtremeDSP DSP48A for Spartan 3A DSP FPGAs User Guide XtremeDSP DSP48A Slices XtremeDSP DSP48A Pre Adder e UG331 Spartan 3 Generation FPGA User Guide 9 Clocking Resources Digital Clock Managers DCMs Block RAM Configurable Logic Blocks CLBs Distributed RAM 5 16 Shift Registers Carry and Arithmetic Logic Resources Programmable Interconnect ISE Software Design Tools IP Cores Embedded Processing
134. stor of 1000 across the and P pins of the differential signal pair 4 Atany given time no more than two of the following differential output standards can be assigned to an bank LVDS 25 RSDS 25 MINI LVDS 25 PPDS 25 when 2 5 or LVDS 33 505 33 MINI LVDS 33 TMDS 33 PPDS 33 when 3 3V 18 www xilinx com DS610 3 v2 0 July 16 2007 Product Specification 5 XILINX DC and Switching Characteristics External Termination Requirements for Differential I O LVDS RSDS MINI_LVDS and PPDS I O Standards Bank 0 and 2 th of Bourns i No yoco Restrictions ar LVDS 33 LVDS 25 ALTER Zo 500 16 4 4 1 05 a MINI LVDS 25 Vcco 3 3V 2 5 503 33 1505 25 LVDS_ 33 LVDS_25 1 000 MINI LVDS 33 MINI LVDS 25 70 500 1 1 1 8 08 33 RSDS_25 PPDS_33 PPDS_25 0 DIFF_TERM No a Input only differential pairs or pairs not using DIFF_TERM Yes constraint 3 3 2 5 Zo 500 LVDS_33 LVDS_25 33 25 M 09 MINLIVDS 25 MIN LVBS_38 MINLIVDS 2 1 08 33 08 25 8508 33 8508 25 20 500 PPDS 33 PPDS 25 K 0 DIFF_TERM Yes b Differential pairs using DIFF_TERM Yes constraint DS529 3_09_020107 Figure 5 External Input Termination for LVDS RSDS MINI_LVDS and PPDS Standards BLVDS_25 Standard
135. subtract the increase or decrease in delay to or from the appropriate Output standard adjustment Table 24 to yield the worst case delay of the PCB trace Generally the left and right banks Banks 1 and 3 support higher output drive current Multiply the appropriate numbers from Table 26 and Table 27 to calculate the maximum number of SSOs allowed within an I O bank Exceeding these SSO guidelines might result in increased power or ground bounce degraded signal integrity or increased system jitter 55 Bank Table 26 x Table 27 The recommended maximum SSO values assumes that the FPGA is soldered on the printed circuit board and that the board uses sound design practices The SSO values do not apply for FPGAs mounted in sockets due to the lead inductance introduced by the socket Table 26 Equivalent Vcco GND Pairs per Bank Package Style including Pb free Device CS484 FG676 XC3SD1800A 6 9 XC3SD3400A 6 10 www xilinx com 33 and Switching Characteristics x XILINX Table 27 Recommended Number of Simultaneously Table 27 Recommended Number of Simultaneously Switching Outputs per Vcco
136. support double the maximum effective FCLKIN limit set the CLKIN DIVIDE BY 2 attribute to TRUE This attribute divides the incoming clock period by two as it enters the DCM The CLK2X output reproduces the clock frequency provided on the CLKIN input 4 input jitter beyond these limits might cause the DCM to lose lock 5 The specifications are guaranteed when both adjacent DCMs are locked DS610 3 v2 0 July 16 2007 www xilinx com 41 Product Specification Switching Characteristics Table 36 Switching Characteristics for the DLL 5 XILINX Speed Grade 5 4 Description Device Min Max Min Max Units Output Frequency Ranges CLKOUT_FREQ_CLKO Frequency for the CLKO and CLK180 outputs All 5 280 5 250 MHz CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs 5 200 5 200 MHz CLKOUT FREQ 2X Frequency for the CLK2X and CLK2X180 outputs 10 334 10 334 MHz CLKOUT FREQ DV Frequency for the CLKDV output 0 3125 186 0 3125 166 MHz Output Clock Jitter 2 3 4 CLKOUT PER JITT 0 Period jitter at the CLKO output All 100 100 5 CLKOUT PER JITT 90 Period jitter at the CLK90 output 150 150 5 180 Period jitter the CLK180 output 150 2150 ps CLKOUT_PER_JITT_270 Period jitter at the CLK270 output 2150 2150 5 CLKOUT PER
137. ted as a Dual Purpose Maximum I Os Possible I O Pins by Type Package and Edge Bank Input Only INPUT oua vero CLK Top 0 77 49 13 1 6 8 Right 1 78 23 9 30 8 8 Bottom 2 76 33 6 21 8 8 Left 3 78 51 13 0 6 8 TOTAL 309 156 41 52 28 32 Notes 1 19 VREF on INPUT pins Table 62 User I Os Per Bank for the XC3SD3400A in the CS484 Package Maximum All Possible I O Pins by Type Package and Edge Bank Input Only INPUT oval veer CLK Top 0 77 49 13 1 6 8 Right 1 78 23 9 30 8 8 Bottom 2 76 33 6 21 8 8 Left 3 78 51 13 0 6 8 TOTAL 309 156 41 52 28 32 Notes 1 19 VREF are on INPUT pins Footprint Migration Differences There are no migration footprint differences between the XC3SD1800A and the XC3SD3400A in the CS484 package DS610 4 v2 0 July 16 2007 Product Specification 68 www xilinx com lt XILINX Pinout Descriptions CS484 Footprint Bank 0 1 2 3 4 5 6 7 8 9 10 11 Left Half of Package vo vo vo vo 19 5 9 L2eN 125 126 0 124 0 INPUT VREF_O 0 6 vo vo vo Vo 0 128 0 L24P 0 um 5 L15P 0 Unrestricted 156 general purpose user c o ME YO vO vo
138. timates only and should not be used for timing analysis Advance These specifications are based on simulations only and are typically available soon after establishing FPGA specifications Although speed grades with this designation are considered relatively stable and conservative some under reporting might still occur Preliminary These specifications are based on complete early silicon characterization Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon The probability of under reporting preliminary delays is greatly reduced compared to Advance data Production These specifications are approved once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots There is no under reporting of delays and customers receive formal notification of any subsequent changes Typically the slowest speed grades transition to Production before faster speed grades 20 www xilinx com Software Version Requirements Production quality systems must use FPGA designs compiled using a speed file designated as PRODUCTION status FPGAs designs using a less mature speed file designation should only be used during system prototyping or pre production qualification FPGA designs with speed files designated as Preview Advance or Preliminary should not b
139. tive current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return The inductance is associated with bonding wires the package lead frame and any other signal routing inside the package Other variables contribute to SSO noise levels including stray inductance on the PCB as well as capacitive loading at receivers Any SSO induced voltage consequently affects internal switching noise margins and ultimately signal quality Table 26 and Table 27 provide the essential SSO guidelines For each device package combination Table 26 provides the number of equivalent Vcco GND pairs For each output signal standard and drive strength Table 27 recommends the maximum number of 5505 switching the same direction allowed per Vcco GND pair within an bank The guidelines in Table 27 are categorized by package style slew rate and output drive current Furthermore the number of SSOs is specified by bank DS610 3 v2 0 July 16 2007 Product Specification Use parameter values Ry and from Table 25 is zero Record the time to Vy Simulate the same signal standard with the output driver connected to the PCB trace with load Use the appropriate IBIS model including Vacs and values or capacitive value to represent the load 4 Record the time to 5 Compare the results of steps 2 and 4 Add or
140. trix that permits multiple connections to the routing Configuration Spartan 3A DSP FPGAs are programmed by loading configuration data into robust reprogrammable static CMOS configuration latches CCLs that collectively control all functional elements and routing resources The FPGA s configuration data is stored externally PROM or some other non volatile medium either on or off the board 4 www xilinx com 5 XILINX After applying power the configuration data is written to the FPGA using any of seven different modes e Master Serial from a Xilinx Platform Flash PROM e Serial Peripheral Interface SPI from an industry standard SPI serial Flash e Byte Peripheral Interface BPI Up from an industry standard x8 or x8 x16 parallel NOR Flash Slave Serial typically downloaded from a processor e Slave Parallel typically downloaded from a processor e Boundary Scan JTAG typically downloaded from a processor or system tester Furthermore Spartan 3A DSP FPGAs support MultiBoot configuration allowing two or more FPGA configuration bitstreams to be stored in a single SPI serial Flash or a parallel NOR Flash The FPGA application controls which configuration to load next and when to load it Additionally each Spartan 3A DSP FPGA contains a unique factory programmed Device DNA identifier useful for tracking purposes anti cloning designs or IP protection Capabilities The Spartan 3A DSP FPGA Selectl
141. ulse width at CLK input 0 90 1 01 5 Clock Buffer Multiplexer Switching Characteristics Table 31 Clock Distribution Switching Characteristics Maximum Speed Grade Description Symbol Minimum 5 4 Units BUFGMUX BUFGCE input to 0 22 0 23 inputs Same as BUFGCE enable Tosi 056 068 ns Frequency of signals distributed on global buffers all sides Faure 0 350 333 MHz DS610 3 v2 0 July 16 2007 www xilinx com 37 Product Specification Switching Characteristics Block RAM Timing Table 32 Block RAM Timing 5 XILINX Speed Grade 5 4 Symbol Description Min Max Min Max Units Clock to Output Times poA When reading from block RAM the delay from the active 2 38 2 80 ns mn transition at the CLK input to data appearing at the DOUT output DOA Clock CLK to DOUT output with output register 1 24 1 45 ns Setup Times ADDR Setup time for the ADDR inputs before the active transition 0 40 0 46 ns i at the CLK input of the block RAM Setup time for data the DIN inputs before the active 0 29 0 33 5 E transition at the CLK input of the block RAM ENB Setup time for the EN input before the active transition at the 0 51 0 60 5 7 CLK input of the block RAM WEB Setup time for the WE input
142. without notice Product Specification www xilinx com Functional Description 5 XILINX 10 www xilinx co m DS610 2 v2 0 July 16 2007 Product Specification 2 XILINX Spartan 3A DSP FPGA Family DC and Switching Characteristics DS610 3 v2 0 July 16 2007 DC Electrical Characteristics In this section specifications may be designated as Advance Preliminary or Production These terms are defined as follows Advance Initial estimates are based on simulation early characterization and or extrapolation from the characteristics of other families Values are subject to change Use as estimates not for production Preliminary Based on characterization Further changes are not expected Production These specifications are approved once the silicon has been characterized over numerous production lots Parameter values are considered stable with no future changes expected Table 3 Absolute Maximum Ratings Product Specification All parameter limits are representative of worst case supply voltage and junction temperature conditions Unless otherwise noted the published parameter values apply to all Spartan 3A DSP devices AC and DC characteristics are specified using the same numbers for both commercial and industrial grades Absolute Maximum Ratings Stresses beyond those listed under Table 3 Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only funct
143. xilinx com 71 Product Specification Pinout Descriptions 5 XILINX Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued Table 63 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Continued Bank XC3SD1800A Pin 70616 Bank XC3SD1800A Pin 70616 0 IO L22P 0 D16 0 IO LO7P 0 B23 0 IO 121 0 017 0 IO L51P 0 A3 lO 0 IO L17P 0 D18 0 IO 145 0 4 O 0 IO L11P 0 D20 0 7 INPUT 0 IO L10N 0 021 0 IO L38P 0 A8 O 0 IO 105 0 022 0 IO L36P 0 A9 O 0 IO 106 0 023 0 IO L33P 0 A10 lO 0 144 0 C5 0 IO L29P 0 A12 Te 0 IO L41N 0 C6 0 13 0 IO 142 0 C7 0 IO L26N 0 GCLK7 14 GCLK 0 IO L40P 0 C8 0 IO L23N 0 A15 O 0 134 0 C10 0 17 0 IO 132 _0 Ci 0 IO L18N 0 A18 lO 0 L30N 0 C12 0 IO L15N 0 A19 O 0 IO L28N O GCLK11 C13 0 IO L14N 0 A20 O 0 IO L22N 0 C15 0 IO LO7N 0 A22 O 0 IO L21N 0 C16 0 616 0 IO L19P 0 C17 0 9 INPUT 0 IO L17N 0 C18 9 0 015 0 IO L11N 0 C20 0 D19 0 IO LO9P 0 C21 0 B24 INPUT 0 IO LO5N 0 C22 0 A5 INPUT 0
144. y Only Pairs XC3SD1800A 309 60 140 156 41 CS484 XC3SD3400A 309 60 140 156 41 XC3SD1800A 519 110 227 314 82 FG676 XC3SD3400A 469 60 213 314 34 Notes 1 Some VREFs are on INPUT pins See pinout tables for details Electronic versions of the package pinout tables and foot prints are available for download from the Xilinx website Using a spreadsheet program the data can be sorted and reformatted according to any specific needs Similarly the ASCII text file is easily parsed by most scripting programs http Awww xilinx com bvdocs publications s3adsp_pin zip 60 www xilinx com DS610 4 v2 0 July 16 2007 Product Specification 5 Pinout Descriptions Package Thermal Characteristics The power dissipated by an FPGA application has The junction to case thermal resistance indicates the implications on package selection and system design The difference between the temperature measured on the power consumed by a Spartan 3A DSP FPGA is reported package body case and the die junction temperature per using either the XPower Power Estimator or the XPower watt of power consumption The junction to board Analyzer calculator integrated in the Xilinx ISE value similarly reports the difference between the board and development software Table 59 provides the thermal junction temperature The junction to ambient value characteristics for the various Spartan 3A DSP device reports the temperature

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