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VXI VM4016 User's Manual

1. FIGURE 5 1 INPUT RANGE SELECTION 4016 Theory of Operation 89 VXI Technology Inc SIGNAL COMPARISON Signal comparison between the input signal and a user defined reference voltage 15 accomplished by a differential amplifier an 8 bit Digital to Analog Converter or DAC and a voltage comparator see Figure 5 2 The DAC US is loaded by the control FPGA U3 and provides the reference voltage TRIGLEVI FROM FRONT CH1 PANEL CONNECTOR CH VMIP BUS 47K CONTROL DACDATA l TRIGLEV1 FPGA DACLOAD gt DACCLK COMPCH1 U3 CONTROL 4 I CONTROL BUFFER Ut Data 0 15 DATA BUFFER FIGURE 5 2 SIGNAL COMPARISON The command to specify the reference voltage is received in the data and command buffers and subsequently transferred to the control FPGA at U3 U3 then converts the parallel data to an 8 bit serial data word DACDATA and synchs the output of this word to the 10 MHz gated clock DACCLK Signal DACLOADI for Channel 1 goes high providing the control necessary to shift the serial data into DAC 1 The output TRIGLEV1 of the U8 is used by the comparator U13A as the reference 90 4016 Theory of Operation www vxitech com The input voltage or signal is applied to the non inverting input of the differential amplifier UI7A T
2. TRG Purpose Causes a trigger event to occur Type IEEE 488 2 Common Command Command Syntax TRG 5 N A RST Value N A Query Syntax N A Query Parameters N A Query Response N A Description The Trigger command causes a trigger event to occur Examples Command Quer Response Description Triggers an event Related Commands N A 60 VM4016 Command Dictionary www vxitech com TST Purpose Causes a self test procedure to occur and queries the results Type IEEE 488 2 Common Command Command Syntax N A N A RST Value N A Query Syntax TST Query Parameters N A Query Response Numeric ASCII value from 0 to 143 Description The Self Test query causes the VM4016 to run its self test procedures and report the results Examples Command Quer Response Description ST O Begins the self test procedure returns the result Related Commands N A VM4016 Command Dictionary 61 VXI Technology Inc WAI Purpose Halts execution of additional commands and queries until the No Operation Pending message is true Type IEEE 488 2 Common Command Command Syntax WAI Command Parameters N A RST Value N A Query Syntax N A Query Parameters N A Query Response N A Description The Wait to Continue command halts the execution of commands and queries u
3. 44 VMA016 Programming www vxitech com ViPInt16 first latched reg This parameter returns the first input channel which crosses the programmed threshold voltage ViPIntl16 raw data This returns the 16 bit value that represents the current unconditioned raw state of the inputs ViPIntl6 conditioned data This returns the 16 bit value that represents the current conditioned state of the inputs Return Values Returns VI SUCCESS if successful else returns error value Description This is an application function that shows how the ACkCkk kk kkkkkt k ViStatus VI Variable ViStat Reset to status return Function status vtvm40 return user can use core functions to enable disable the specified channels for interrupt generation and configure the specified channels various parameters such as offset polarity and voltage range It returns the value of the First Latched register which records the first input channel to cross its threshold and queries the current state of the inputs Note that this function resets the module to its default state KCKCKCKCKCKCkCkCk Ck kCkCk kCkCkCkCkCK Ck kCk Ck kCk Ck kCk Ck Ck k CK Ck kCk k kCk Ck k kc k kck I A RK FUNC vtvm4016 setup and read data ViSession instr hnadl Vilnt16 channel list ViInt16 num of channels ViReal32 offset Vilntl16 polarity Vilnt16 voltage range ViPIntl6 first latched reg ViPIntl16 raw data
4. nnne nennen 78 1 A teen reinen 79 STATUS OPERation EVENT tst hn n o E rU ct E bor t s 80 STA Tus PRES et 81 STATus QUEStionable CONDition iesise tae iie 82 STATus QUEStionable ENABle 5 itt me ree COH Te ERR Hee egre 83 STATus QUEStionable EVENt enne tnnt tnnt ett 84 SY STEM ERROR E 85 SYSTem VERSIOB et et tet edet ec en Et tet A eis 86 SECTION p cH 87 Jhe ory of Operation eter eee Cis n eb e eiut e E o de eR a 87 IntrOdUCtlOof iosuada nest eite e eve ede i re n E eer atv rc ilte op is 87 RR ERE we 88 Comparision Et E eco 90 Interrupt Gieneration einge ue ere RE E ee e HERR ER I e Re e Re e ERE 91 93 VM4016 Preface www vxitech com CERTIFICATION VXI Technology Inc VTI certifies that this product met its published specifications at the time of shipment from the factory VTI further certifies that its calibration measurements are traceable to the United States National Institute of Standards and Technol
5. 61 62 Instrument Specific 0 e E edere deren s 63 gei et 63 uei RU mI RU IB 64 FETChiRAW eic anta eR etie Ra Ut S 65 INHOUSE CEEARJEXTCH e teen danti RI AAT 66 INHOUSE PSEUDO nin nosci eee 67 INHOUSE REGINT 4 nece e Reti e eee RR E Ee Erde ee 68 INHOUSE REG eese enne enne enne trennt enne 69 INPut DEBOURDCE ent e een eani E 70 INP t MASK nennen ete e tte 71 72 73 INPUt POLarity ette ient 74 c Y 75 OUTPut POLarity EXTernal IN Terr pt nce ette cre De TR e d OU De Dea 76 OUTPaut POLarity EXTer ial EATChed ene bo RA hes T Required SCPI Conr imands eie usc eee ete e Te Ried i eei ic re 78 STATus OPERation CONDition 2 trennen
6. VMA016 Command Dictionary 85 VXI Technology Inc SYSTem VERSion Purpose Queries the SCPI version number to which the VM4016 complies Type Required SCPI command Command Syntax None query only N A RST Value N A Query Syntax SYSTem VERSion Query Parameters None Query Response Numeric ASCII value Description The System Version query reports version of the SCPI standard to which the VM4016 complies Examples Command Quer Response Description SYST VERS 19940 Related Commands None 86 VM4016 Command Dictionary www vxitech com SECTION 5 THEORY OF OPERATION INTRODUCTION The VM4016 is a high performance Analog Comparator module with 16 input channels per VMIP daughter module Each input channel consists of a differential amplifier with a gain of 1 or 0 1 giving an input range of 10 volts or 100 volts Each input is compared against a reference voltage derived from an independent 8 bit DAC The VM4016 has a resolution of 78 mV Each input signal is digitally debounced for a programmed time ranging from approximately 10 us to 0 5 s This prevents input signal noise from causing undesired interrupts After debounce the signal may be programatically inverted to select the input transition edge of interest rising or falling edge and masked to prevent unused channels from causing interrupts All the masked inputs are OR ed together to produce
7. 34 OUTPut POLarity EXTernal LATChed 33 49 77 pseudo register access R Register Access 41 relay diivVers nece des 36 39 88 STATus OPERation CONDition sss 50 78 STATus OPERation ENABle STATus OPERation EVENt 25 STAT s PRESGt en nione te ate eoe tae STATus QUEStionable CONDition STATus QUEStionable ENABle STATus QUEStionable EMENt Ae 84 50 STB ze Aeon RORIS IPIE GIG 48 SYSTem ERRor 50 85 SYSTEM VERSION 50 SYSTem VERSIO nnn a 86 T ng sera 48 V 11 12 16 37 40 87 88 11 12 15 16 63 64 71 87 VXIplug amp play Driver 44 W WAT ce cetus deb 48 VM4016 Index 93
8. Command Parameters N A 5 Value N A Query Syntax STATus OPERation EVENt Query Parameters None Query Response 0 Description The Status Operation Event Register query is included for SCPI compliance The VM4016 does not alter any of the bits in this register and always reports a 0 Examples Command Quer Response Description STAT OPER Related Commands None 80 VM4016 Command Dictionary www vxitech com Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands STATus PRESet Presets the Status Registers Required SCPI command STATus PRESet None N A None command only N A N A The Status Preset command presets the Status Registers The Operational Status Enable Register is set to 0 and the Questionable Status Enable Register is set to 0 This command is provided for SCPI compliance only Command Quer Response Description STAT PRES Presets the Status Registers None VM4016 Command Dictionary VXI Technology Inc STATus QUEStionable CONDition Purpose Queries the Questionable Status Condition Register Type Required SCPI command Command Syntax None query only Command Parameters N A 5 Value N A Query Syntax STATus QUEStionable CONDition Query Parameter
9. RAW DATA data nstr hndl D CONDITIONED DATA conditioned data ERROR READING CONDITIONED DATA 46 VMA016 Programming www vxitech com SECTION 4 COMMAND DICTIONARY INTRODUCTION This section presents the instrument command set It begins with an alphabetical list of all the commands supported by the VM4016 divided into three sections IEEE 488 2 commands the instrument specific SCPI commands and the required SCPI commands With each command is a brief description of its function whether the command s value is affected by the RST command and its RST value The remainder of this section is devoted to describing each command one per page in detail Every command entry describes the exact command and query syntax the use and range of parameters and a complete description of the command s purpose ALPHABETICAL COMMAND LISTING The following tables provide an alphabetical listing of each command supported by the VM4016 along with a brief description If an X is found in the column titled RST then the value or setting controlled by this command is possibly changed by the execution of the RST command If no X is found then RST has no effect The default column gives the value of each command s setting when the unit is powered up or when a RST command is executed VM4016 Command Dictionary 47 CLS ESE ESR IDN OPC RST SRE STB TRG TST WAI Command VXI Techn
10. 15 Calculating System Power and Cooling Requirements sss 15 Setting the Chassis Backplane Jumpers srren eo eR ERES PR ee te E 16 Setting the Logical Address oerte rte ee dre eene eese eee 16 Front Panel Interface Wiring eene eee dieit de eese e ee E Ere deine reet 16 he BY H LOD ES PIET A ES ET 19 P ER 19 SCPI C mmandS seccina e 19 FETCH CONDITIONED ieee EET E N 19 EETCHEDATGCHEDJ ertet tote A neues conten E A ness ANA EE ese ere ed 20 PEECHRAW 21 INHOUSE PSEUDO eret 22 INHOUSE REGINST sente scenes 23 INHQUSE REG ENABLE terit eerte ne er FO Ee Hee ere e oerte ee ele rois 24 TNHOUSE GLEAR LATCH tr pde rtt eme a ter eae pierre rotate ge 25 INPUT DI BOUNCE EATUR E TO mr EG rt ren 26 INPUT MASK ne rio on dE etre ed dut isto enit ite ritas 27 INPUT MASK INTERRUPT 5 irren cele torre a 28 INPUT OFFSET M 29 INPUT PODAREDY eet d e e e der tn 30 INPUT RANGE ertet nre ded nti e A a ted e t 31 OUTPUT POLARITY EXTERNAL INTERRUPT 2 4 12 40 2104000000000000000000000000040000000000000005000 32 OUTPUT POLARITY EXTERNAL LATCHED 33 Application Ex
11. Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands VXI Technology Inc INPut DEBounce Sets the debounce time Setting INPut DEBounce lt value gt value 9 6 us to 0 6291456 s 19 2 us INPut DEBounce N A Numeric ASCII value from 0 0000096 to 0 6291456 The INPut DEBounce command sets the time period for the digital debounce circuitry By programming a debounce time of 1 ms an input must exceed its threshold level for a period of 1 ms before it is recognized as a valid input The debounce resolution 15 9 6 us The debounce time set is applied to all channels Command Quer INP DEB 9 6e 6 INP DEB Sets a digital debounce time of 9 6 us 0 000009 Indicates that the debounce time is set to 9 6 us 70 VMA016 Command Dictionary www vxitech com INPut MASK Purpose Masks unused input channels Type Setting Command Syntax INPut MASK lt state gt lt channel_list gt lt channel list gt standard channel list syntax supporting channels 1 to 16 lt state gt ON 1 OFF 0 RST Value 0 for all channels Query Syntax INPut MASK lt channel gt Query Parameters lt channel gt to 16 Query Response Numeric ASCII value of 1 or 0 Description The INPut MASK command selects which channels are enabl
12. E Technology VM4016 ANALOG COMPARATOR USER S MANUAL 82 0022 000 Rev December 1 2003 VXI Technology Inc 2031 Main Street Irvine CA 92614 6509 949 955 1894 www vxitech com TABLE OF CONTENTS INTRODUCTION Certification cases ER 5 5 Limitation of Warranty esee einen fe ee ERR Hte GEI RR IR Ee dT A deeds 5 Restricted Rights Legend 5 Declaration of Conformity e ene ttt e e e a uei eet cU Bed tS 6 General Safety Instructions ee eM e EAR NR E daa teu Un ER QE E tee das ted 7 Terms and Symbols et ei eitis qe Rete ette 7 Warning 7 Support Resourees nete ero tu se rere m OL 9 SECTION B eoe 11 D e 11 Introduction eroe ERE IR E PEE UR Fee Ron HR E Fee eec e odes 11 d E T e UI 12 4016 General Specifications sese ic cane EU ER de ne d ede e e te dece edes 14 SECTION pP 15 Preparation for Use eiecit eec UR ee Tee Ue HE edet edere te coc UR PA 15 Installation TI
13. polarity is either NORMdal or INVerted EXAMPLES OUTPucPOLarity EXTemal LATChed NORM Sets the external latched output polarity to low when an interrupt occurs OUTPutPOLanity EXTemal LATChed Returns the external latched output NORM polarity as NORMal OUTP POL EXT LATC INV Sets the external latched output polarity to high when an interrupt occurs OUTP POL EXT LATC Returns the external latched output INV polarity as INVert VM4016 Programming 33 VXI Technology Inc APPLICATION EXAMPLES This section contains examples of using SCPI command strings for programming the VM4016 module The code is functional and will contain a brief description about the operation Example 1 In this example the 4016 sets the output interrupt polarity on the front panel and the debounce time period for the digital debounce circuitry OUTPut POLarity EXTernal INTerrupt NORM INPut DEBounce 25e 6 Example 2 Sets the external interrupt output polarity to high pulse when an interrupt occurs Sets input debounce time for all channels to 25 us This will not allow a signal to generate an interrupt unless the channel is active for greater than 25 us In this example the VM4016 enables or disables the specified channels for interrupt generation sets the offset polarity and voltage range It returns the value of First Latched register which records the first input channel to cross its threshold and queries the current s
14. COMPCH2 is routed to the debounce circuitry inside U3 Note that the only difference in the way these two circuits are working is the output of the comparator U13B is inverted from the output of U13A This inversion will allow us to determine if an under voltage has occurred Assume that CH2 has fallen below 4 75 V The output of U13B is now high The debounce circuitry will count down for 750 us before clocking through COMPCH2 When the 750 us time limit has expired U3 clocks COMPCH2 into the mask register The mask register will AND 2 with the mask value 0003 The mask register passes to a 16 input OR ing function that determines which channel was first to cross its threshold in this case COMPCH2 The output of this ing then latches into the First Latch Register This signal arbitrarily named FIRSTLATCHED clocks a series of internal latches that will stretch the pulse to 500 ns This pulse drives the base of Q33 low causing Q33 to shut off and the pull up resistor provides a high on the front panel connector signal EXTIRQ When an interrupt condition is detected by U3 a VXI IRQ is generated to the VMIP bus 40 VMA016 Programming www vxitech com REGISTER ACCESS EXAMPLES TABLE 3 1 REGISTER MAP __ ooo ee pu 2 2 p VM4016 Programming 41 VXI Technology Inc The VM4016 module supports direct register acc
15. INHOUSE PSEUDO N A ASCII numeric 0 or 1 If INHOUSE PSEUDO is set true 1 or ON the instrument uses the pseudo register interface If false 0 or OFF the instrument uses the hardware register interface The value set is implemented upon the next power cycle This command does not take effect immediately The pseudo register interface allows use of the REG_ENABLE capability as well as the CLEAR LATCH capability from the registers These capabilities are not available with the hardware register interface The hardware register interface is much faster than the pseudo register interface speeds are controller dependent but as an example with one controller a hardware register access takes about 0 5 us while a pseudo register access takes about 25 us The hardware register however interface lacks the above two features Pseudo registers are needed if the user wants to perform a register read or a word serial FETch LATChed of FIRST LATCHED data in order to allow another FIRST LATCHED to occur If pseudo is not set then the user can read registers at hardware register speed but a word serial read FETCh LATChed 15 required to allow another FIRST LATCHED to occur If pseudo is set then the user can read the registers at pseudo register speed but the read of the latched data will allow a new FIRST LATCHED to occur Pseudo also allows a register write to control the masking of interrupts for REGINT Note All letters of the comm
16. FPGA decodes the control bits and drives the RELAYENA signal low This signal enables the relay drivers U15 and U16 to receive the incoming data and control signals U3 then converts the parallel data from the VMIP Bus to a 16 bit serial data word This serial data word RELAYDATA is synched to the 10 MHz gated relay clock RELAY LK and sent to the relay drivers The relay drivers are cascaded so that the serial output from 015 feeds the serial input of U16 The parallel outputs from the relay drivers will drive either low or high thereby energizing or de energizing the appropriate relays K1 through K16 in this case K9 The relay 15 divided into three 3 sections for ease of analysis The reference designator K9 A 15 given to the relays coil K9 B and K9 C are given to the relay s contacts When energized the K9 relay selects a 10 resistor on both of the inputs to the differential amplifier This provides for a gain of 0 1 thus allowing for input voltage range of 100 V When the K9 relay is de energized it will default to a 100 resistor that provides a gain of 1 thereby allowing 10 V input voltage range 88 4016 Theory of Operation www vxitech com FROM FRONT PANEL CONNECTORS TO U13A CH1 VMIP BUS COMMAND BUFFER 15 RELAYDATA 0 5 29 RELAYUPDATE RELAY DRIVER RELAYCLK RELAYENA o CONTROL FPGA SEROUT DATA BUFFER gt
17. NORM to cause U3 to treat the input signal as an active high The commands and data for SCPI command INP OFFS are received by the control U1 and data U4 buffers and routed to the control FPGA U3 The control FPGA will convert the parallel data for the DAC U8 into a serial data stream This data DACDATA is synched to the 10 MHz gated clock DACCLK and loaded into the DAC when the DACLOAD signal goes high The command for the SCPI command OUTP POL EXT LATC is received by the control U1 and data U4 buffers and routed to the control FPGA U3 The latch register uses this command to determine whether the output signal should be an active high or an active low This was programmed for INV to cause U3 to output an active low EXTLATIRQ signal to the front panel connector when an interrupt occurs Now that the VM4016 is configured it can be determined how this works The output of the differential amplifier U17A is voltage divided by 4 Since the gain of U17A is 0 1 this makes BUFCHI 0 875 V when CH1 reaches 35 0 V BUFCHI is compared with the output of U8 TRIGLEV1 by comparator U13A When BUFCHI is greater than TRIGLEVI the output of goes low COMPCHI is routed to the debounce circuitry inside U3 The debounce circuitry will count down for 250 ms before clocking through COMPCHI This circuitry is used to mask out transients from generating false interrupts When the 250 ms time limit has
18. OFF Set command sets the input threshold for a channel or group of channels over which the input signal must cross to cause an interrupt event This command sets the value in the 8 bit DAC to which the input signal is compared It is important to note that the actual input offset value is affected by the INPut RANGe command as the response has been normalized to 10 V range The actual input offset for the allowable ranges are as follows Range Entered Threshold Actual Threshold 10 0 X 1 0 100 0 X 10 0x INPut OFF Set voltage level channel list Where voltage level ranges from 10 00 volts to 9 96 volts Where channel list is the standard channel list format supporting Channels 1 through 16 EXAMPLES INPucRANGe 100 5 10 INPucOFFSet 5 0 95 10 INP OFFS 9 5 000 INP RANG 10 91 4 INP OFFS 5 0 1 4 INP OFFS 3 5 000 Sets the input range for Channels 5 through 10 to 100 V Sets the input offset for Channels 5 through 10 to 50 V Returns the normalized input offset of 50 V for Channel 9 Sets the input range for Channels 1 through 4 to 10 V Sets the input offset for Channels 1 through 40 5 Returns the normalized input offset of 5 V for Channel 3 VM4016 Programming 29 INPUT POLARITY VXI Technology Inc The input polarity command selects the input polarity for one or more channels When a channel 15 programmed for normal polarity
19. Value N A Query Syntax IDN Query Parameters N A Query Response ASCII character string Description The Identification IDN query returns the identification string of the module The response is divided into four fields separated by commas The first field is the manufacturer s name the second field is the model number the third field is an optional serial number and the fourth field is the firmware revision number If a serial number is not supplied the third field 15 set to 0 zero Examples Command Quer VXI Technology Inc VIV4016 0 1 0 The revision listed here is for reference only the response will always be the current revision of the instrument Related Commands VMA016 Command Dictionary 55 VXI Technology Inc OPC Purpose Sets the OPC bit in the Event Status Register Type IEEE 488 2 Common Command Command Syntax OPC N A RST Value N A Query Syntax OPC Query Parameters N A Query Response 1 Description The Operation Complete OPC command sets the OPC bit in the Event Status Register when all pending operations have completed The OPC query will return a 1 to the output queue when all pending operations have completed Examples Command Quer Response Description Sets the OPC bitin the Event Status Register 1 Returns the value of the Event Status Register Related Commands 56 VMA016 Comman
20. ViPIntl6 conditioned data used to store return status of the function us status VI NULL the default state vtvm4016 reset instr hndl if status VI SUCCESS Status to enable the selected channels to cause interrupt vtvm4016 enable disable channels instr hndl 16 ENABLE CHANNEL channel list num of channels if status VI SUCCESS vtvm4016 ERROR MASK OR UNMASK CHANNELS VM4016 Programming 45 Function to set the Status vtvm401 if status Function to query t status vtvm401 if status return vtvm4016 1 Function to query t status vtvm401 if status Function to query t status vtvm401 if status return vtvm4016 return VI SUCCES VXI Technology Inc offset polarity and voltage range to the channels 6 config channels instr hndl channel list num of channels offset polarity voltage range VI SUCCE VI SUCCE he Raw data 6 read data vtvm4016 VI SUCCE he Conditio 6 read data vtvm4016 VI SUCCE 5 55 55 1 55 return vtvm4016 ERROR READING _ ned i REA SS return vtvm4016 ERROR SETTING CHANNELS he first latched register 6 query latched reg instr hndl first latched reg ERROR QUERYING LATCHED REG nstr hndl D RAW DATA raw data
21. a serial data stream This data RELAYDATA 15 synched to the 10 MHz RELAYCLK and written into the relay drivers when RELAYENA goes low The relay drivers de energize relays 9 and selecting a gain of 1 0 for the differential amplifiers at U17A and U17B The command and data for the SCPI command INP DEB are received by the control U1 and data U4 buffers and routed to the control FPGA U3 The register for the debounce circuitry 1s contained internally in the control FPGA The register will be loaded with a value that corresponds to a 750 us time delay 4016 Programming 39 VXI Technology Inc The commands for the SCPI commands INP MASK are received by the control U1 and data U4 buffers and routed to the control FPGA U3 The mask register circuitry is contained internally in the control FPGA This register will be loaded so that Channels 3 through 16 are disabled or masked out The command for the SCPI command INP POL is received by the control U1 and data U4 buffers and routed to the control FPGA U3 Channel 1 has been programmed this to NORM so that the debounce and mask circuitry will treat as an active high Channel 2 has been programmed as INV causing the debounce and mask circuitry to treat Channel 2 as an active low The command and data for the SCPI command INP OFFS are received by the control U1 and data U4 buffers and routed to the control FPGA U3 The control FPGA will convert the para
22. expired U3 clocks COMPCHI into the mask register The mask register will AND with the mask value 0001 The mask register passes COMPCHI to a 16 input function that determines which Channel was first to cross its threshold The output of this OR ing then latches into the First Latch Register This signal arbitrarily called FIRSTLATCHED clocks an internal latch that drives the base of Q34 Q34 conducts and drives a low out on the front panel connector signal EXTLATIRQ When an interrupt condition is detected by U3 a VXI IRQ is generated to the VMIP bus 4016 Programming 37 VXI Technology Inc BRACKETING VOLTAGE In this example an input voltage level will be bracketed for an over or under voltage error condition The input voltage of 5 0 V will be monitored for an over voltage of 5 25 V and an under voltage of 4 75 V The error condition must be true for longer than 750 us An interrupt will be generated if either of these conditions occur Channel 1 will use for an over voltage and Channel 2 for an under voltage Channel 1 and Channel 2 positive sides will be tied together externally Channel 1 and Channel 2 negative sides will be grounded The output interrupt will not be latched but will be pulsed COMMANDS DESCRIPTION INP RANG 10 1 2 Selects 10 Volts as the input range for Channel 1 and 2 INP DEB 75e 5 Sets the debounce time limit to 750 us INP MASK 1 1 2 Enables Cha
23. register Type Setting Command Syntax INHOUSE CLEAR LATCH lt boolean gt WIE lt boolean gt 0 1 OFF ON RST Value 0 Query Syntax INHOUSE CLEAR LATCH Query Parameters N A Query Response ASCII numeric 0 or 1 Description CLEAR LATCH determines whether the first latched information will be cleared when the information is read For some this provides confidence that another interrupt has not occurred The information is cleared with the word serial FETCh LATChed command It is also cleared 1f PSEUDO is set and a register read of the first latched information occurs The information is not cleared if a hardware register read is used When the information is cleared all following reads will return a value of 0 until a new first latched event occurs Note All letters of the command are required there is no short form of the command Examples Command Query INHOUSE CLEAR LATCH 1 INHOUSE CLEAR LATCH Related Commands INHOUSE PSEUDO FETCh LATChed 66 VMA016 Command Dictionary www vxitech com Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands INHOUSE PSEUDO Controls the use of the register interface Setting INHOUSE PSEUDO lt boolean gt lt boolean gt 0 1 OFF ON Factory Default 1 N A
24. 0 Description The Operation Status Condition Register query is provided for SCPI compliance only The VM4016 does not alter the state of any of the bits in this register and always reports a 0 Examples Command Query Response Description STAT OPER COND 0 Related Commands None 78 VMA016 Command Dictionary www vxitech com STATus OPERation ENABle Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands Sets the Operation Status Enable Register Required SCPI command STATus OPERation ENABle lt NRf gt lt NRf gt numeric ASCII value from 0 to 32767 NRf must be specified STATus OPERation ENABle None Numeric ASCII value from 0 to 32767 The Operation Status Enable Register is included for SCPI compatibility and the VM4016 does not alter any of the bits in this register The register layout is as follows Bit 0 Calibrating Bit 1 Setting Bit 2 Ranging Bit 3 Sweeping Bit 4 Measuring Bit 5 Waiting for trigger Bit 6 Waiting for arm Bit 7 Correcting Command Quer Response Description STAT OPER ENAB 0 0 VMA016 Command Dictionary VXI Technology Inc STATus OPERation EVENt Purpose Queries the Operation Status Event Register Type Required SCPI command Command Syntax None query only
25. I value from 0 to 255 The Event Status Register ESR query queries and clears the contents of the Standard Event Status Register This register is used in conjunction with the ESE register to generate the Event Status Bit ESB in the Status Byte The layout of the ESR 15 Bit 0 Operation Complete Bit 1 Request Control Bit 2 Query Error Bit 3 Device Dependent Error Bit 4 Execution Error Bit 5 Command Error Bit 6 User Request Bit 7 Power On The Operation Complete bit is set when it receives an OPC command The Query Error bit is set when data is over written in the output queue This could occur if one query is followed by another without reading the data from the first query The Execution Error bit is set when an execution error is detected Errors that range from 200 to 299 are execution errors The Command Error bit is set when a command error is detected Errors that range from 100 to 199 are command errors The Power On bit is set when the module is first powered on or after it receives a reset via the VXI Control Register Once the bit is cleared by executing the ESR command it will remain cleared Command Query Response Description 54 VM4016 Command Dictionary www vxitech com DN Purpose Queries the module for its identification string Type IEEE 488 2 Common Command Command Syntax N A N A RST
26. N61010 2001 EMC EN61326 1997 w A1 98 Class A CISPR 22 1997 Class A VCCI April 2000 Class A ICES 003 Class A ANSI C63 4 1992 AS NZS 3548 1 amp A2 97 Class FCC Part 15 Subpart B Class A EN 61010 1 2001 The product was installed into a C size VXI mainframe chassis and tested in a typical configuration I hereby declare that the aforementioned product has been designed to be in compliance with the relevant sections of the specifications listed above as well as complying with all essential requirements of the Low Voltage Directive December 2003 C Jerry Patton QA Manager 6 VM4016 Preface www vxitech com GENERAL SAFETY INSTRUCTIONS Review the following safety precautions to avoid bodily injury and or damage to the product These precautions must be observed during all phases of operation or service of this product Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of the product Service should only be performed by qualified personnel TERMS AND SYMBOLS These terms may appear in this manual WARNING Indicates that a procedure or condition may cause bodily injury or death CAUTION Indicates that a procedure or condition could possibly cause damage to equipment or loss of data These symbols may appear on the product ATTENTION Important safety instructions mu Frame or c
27. NT 1 INHOUSE REGINT Sets REGINT to true 1 Indicates that REGINT is set to true Related Commands INHOUSE REG_ENABLE INHOUSE PSEUDO 68 VMA016 Command Dictionary www vxitech com INHOUSE REG ENABLE Purpose Controls the masking of REGINT Type Setting Command Syntax INHOUSE REG ENABLE lt boolean gt lt boolean gt 0 1 OFF RST Value 0 Query Syntax INHOUSE REG ENABLE Query Parameters N A Query Response ASCII numeric 0 or 1 Description REG ENABLE controls the masking of REGINT If ENABLE is zero then backplane interrupt can be generated If ENABLE is a non zero number then a backplane interrupt can be generated If PSEUDO is set to on then a write to the register at offset 0x38 also controls the masking zero disables a non zero enables This command is included for completeness Enable disable capabilities are provided in the pseudo register interface to allow a complete register interface This command just provides that same capability in the word serial interface Note All letters of the command are required there is no short form of the command Examples Command Query INHOUSE REG ENABLE 1 INHOUSE REG ENABLE Response Description Related Commands INHOUSE PSEUDO INHOUSE REGINT VMA016 Command Dictionary 69 Purpose Type Command Syntax
28. SIGNAL GROUND CHANNEL 11 CHANNEL 11 CHANNEL 14 CHANNEL 14 GROUND CHANNEL 16 CHANNEL 16 CHANNEL 3 CHANNEL 3 GROUND CHANNEL 6 CHANNEL 6 CHANNEL 9 CHANNEL 9 GROUND CHANNEL 12 4 CHANNEL 12 CHANNEL 15 CHANNEL 15 GROUND LATCHED IRQ OUT PIN NUMBER 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VMA016 Preparation for Use 17 VXI Technology Inc The mating connector to J200 J201 or J202 is available from the following company Assmann Electronic Inc P N AHDS44LL T Mating Connector The pin locations for J200 J201 and J202 are shown in Figure 2 2 16 31 0000000000000 A e FIGURE 2 2 J200 J201 AND J202 PIN LOCATIONS VM4016 Preparation for Use www vxitech com 3 PROGRAMMING EXAMPLES OF SCPI COMMANDS FETCH CONDITIONED The FETCh CONDition query returns the 16 bit value that represents the current conditioned masked and inverted state of the inputs It is important to note that this information is also available at the VXIbus register level at offset 0x28 FETCh CONDitioned No query parameters EXAMPLES FETCh CONDitioned Returns the state of the conditioned 0 masked and inverted inputs VM4016 Programming 19 VXI Technology Inc FETCH LATCHED The FETCh LATChed query retu
29. VM4016 Programming 43 VXI Technology Inc VXIPLUG amp PLAY DRIVER EXAMPLES KK KK KKK KK KK KR KCKCk KCKCK IR I KCKCKCkCKCKCkCKCk ck kCk Ck k kc k Ck kc k kckck ck kck ck kokck kok ck ck oko ko Function vtvm4016 setup and read data Formal Parameters ViSession instr hndl valid sessionandle to the instrument Vilntl16 channel list This parameter specifies the channels which are to be setup Only the specified channels will be enabled the rest will be disabled Each channel number in the array has the range vtvm4016 MIN CHANNEL NO 1 to vtvm4016 MAX CHANNEL NO 16 Vilntl16 num of channels This parameter specifies the number of channels in the channel List Valid Range vtvm4016_MIN_CHANN vtvm4016 MAX CHANN trj ViReal32 offset This parameter specifies the offset voltage to be configured for the input channels Valid Range vtvm4016 MIN VOLTAGE LEVEL 10 00 V to vtvm4016 MAX VOLTAGE LEVEL 9 96 V Vilntl16 polarity This parameter specifies the polarity to be configured for the Specified channels Valid Range vtvm4016 INVERTED POLARITY 0 or vtvm4016 NORMAL POLARITY 1 Vilntl16 voltage This parameter specifies the voltage range to be configured for the specified channels Valid Range vtvm4016 10VOLTS RANGE 0 or vtvm4016 100VOLTS RANG
30. a single interrupt signal This interrupt signal is used to generate a VXIbus interrupt as well as the front panel interrupt outputs Special logic will latch the first input to cross its threshold into the First Latched Register This records the originating input The First Latched Register can be cleared by querying the Latched Register contents using the word serial command FETCh LATched or by querying the data via Pseudo Register Access with the INHOUSE CLEAR LATCH set to 1 or ON The state of each channel s debounced input and the inverted and masked status may be read directly in the user defined area of the VXIbus registers as can the First Latched register This information may also be retrieved using the message based word serial interface All channels on the VM4016 are identical in functionality therefore descriptions in this theory of operation will pertain to Channel 1 CH1 only VM4016 Theory of Operation 87 VXI Technology Inc INPUT RANGE CONTROL The Input Range or gain control for each of the sixteen channels is accomplished by U3 the control FPGA the data and command buffers U4 and 01 the relay drivers U15 and 016 and relays K1 through K16 see Figure 5 1 The command to select the 100 volt range is latched into the data buffer at U4 and the control bits are latched into the command buffer at U1 The data out enable line 15 driven low transferring the data and control bits to the control FPGA U3 The control
31. amples iei e Tee ee ee Eee 34 Single Channel Operation nee eie de UR Hee e E ER 35 Bracketine Voltage time Rei 38 Register Access Examples OU DR RU D OE a GEN HUN ae 41 Pseudo Register ACCESS e sete E IHRER 43 VXIplug amp play Driver Examples 3 eR ede ite de EE EI 44 PH O 47 Command Dictionary econtra p da eere o iiem ete dbi 47 8 0 47 Alphabetical Command Listing 47 Command Dictionary d dede eene redde ie PR E Oe e Ee Unde erede deest verd 51 VM4016 Preface 3 VXI Technology Inc Common SCPE Commatids dte i ERR E ev nee TIEREN eR TI Tee eed 52 iie ete con te BI Fee eeu ete ete nde ade ei e Hr e e EE RO Fete a ee o re egre Ure waar eg e te o des 52 ESE 2 5 n dedo dai e deleri rt a QU deleted ie ER TON EE GG ORT EDEN a ee Fe e RE Gd 53 CRM LE ME 54 EET 55 Ql om PE 56 opted etes RE 57 SRE 58 cer d M e ru 59 ohne din Mo e 60
32. an interrupt will be generated when the input voltage 15 greater than the programmed input offset for the channel The invert polarity will cause an interrupt when the input voltage is less than the programmed input offset for the channel INPut POLarity polarity channel list Where polarity is either NORMal or INVerted Where channel list is the standard channel list format supporting channels 1 through 16 EXAMPLES INPutPOLarity NORM 3 5 INPu POLarity 5 NORM INP POL INV 6 Sets the input polarity for Channels 3 through 5 to NORMal This will generate an interrupt when the input signal on Channels 3 4 or 5 is greater than the input offset Returns the input polarity for Channel 5 as NORMal Sets input polarity for Channel 6 to invert 30 VMA016 Programming www vxitech com INPUT RANGE The input range command selects the input range of one or more channels The input range may be either set for 10 volts or 100 volts It is important to note that the input offset is normalized to 10 volt range The actual input offset in the 100 volt range is ten times the set value INPut RANGe lt range gt lt channel_list gt Where range is 10 V 100 V Where channel list is the standard channel list format supporting channels 1 through 16 EXAMPLES INPutRANGe 100 91 16 Sets the input range for Channels 1 through 16 to 100 V INPutRANGe 7 Returns the input range
33. and are required there is no short form of the command Command Query Response Description INHOUSE PSEUDO 1 INHOUSE PSEUDO Selects the PSEUDO register l Indicates that the PSEUDO register is selected INHOUSE REG_ ENABLE INHOUSE CLEAR LATCH VMA016 Command Dictionary 67 VXI Technology Inc INHOUSE REGINT Purpose Controls the module s response type to an interrupt acknowledge cycle Type Setting Command Syntax INHOUSE REGINT lt boolean gt lt gt 0 1 OFF RST Value 0 Query Syntax INHOUSE REGINT Query Parameters N A Query Response ASCII numeric 0 or 1 Description The INHOUSE REGINT command controls the module s response type to an interrupt acknowledge cycle When REGINT is set to false the module uses reqt reqf request true request false provided the latched interrupt bit is set tin the SRE reqt upper 8 bits are 0x7D is generated for every latched event and a reqf upper 8 bits are 0x7C is generated for every reading of the latched information using either pseudo register access or word serial FETch LATChed Command When REGINT is set to true only one interrupt is generated every time a latching occurs The upper 8 bits of the 16 bit SRE register on 0x7B Note All letters of the command are required there is no short form of the command Examples Command Query INHOUSE REGI
34. at is used to inhibit the remote power source COMMANDS DESCRIPTION INP RANG 100 1 Selects 100 volts as the input range for Channel 1 INP DEB 0 25 Sets the debounce time limit to 250 ms INP MASK 1 1 Enables Channel I to generate an interrupt INP MASK 0 2 16 Disables Channels 2 through 16 from generating an interrupt INP POL NORM 1 Selects Channel 1 to generate an interrupt when Channel 1 is greater than the offset voltage INP OFFS 3 5 1 Selects 35 0 volts as the offset reference voltage OUTP POL EXT LATC INV Sets the external latched output to be active low Figure 3 1 and the explanation that follows illustrates what is occurring during this example 4016 Programming 35 VXI Technology Inc 10K 10K 10pf FRONT PANEL CONNECTOR CH1 10K U17A K CH1 10K m 100K K9 10K L AMS BUFCH1 AX CONTROL DACDATA A DAC TRIGLEV1 by IRQ DACLOAD Fl DACCLK 470K U8 I COMPCH1 vcc RELAYCLK 10K RELAYDATA LATIRQOUT TO FRONT PANEL RELAYENA CONNECTOR 1 47K 4 1K DATA 0 15 DATA BUFFER RELAY DRIVER DOE e gt TO RELAY CEES u15 ADDRESS CONTROL BUFFER CONTROL CONTROL Ut FIGURE 3 1 SINGLE CHANNEL OPERATION Due to the type of signal being monitore
35. by qualified personnel The operator of this instrument is advised that if equipment is used in a manner not specified in this manual the protection provided by this equipment be may be impaired VM4016 Preface www vxitech com SUPPORT RESOURCES Support resources for this product are available on the Internet and at VXI Technology customer support centers VXI Technology World Headquarters VXI Technology Inc 2031 Main Street Irvine CA 92614 6509 Phone 949 955 1894 Fax 949 955 3041 VXI Technology Cleveland Instrument Division VXI Technology Inc 7525 Granger Road Unit 7 Valley View OH 44125 Phone 216 447 8950 Fax 216 447 8951 VXI Technology Lake Stevens Instrument Division VXI Technology Inc 1924 203 Bickford Snohomish WA 98290 Phone 425 212 2285 Fax 425 212 2289 Technical Support Phone 949 955 1894 Fax 949 955 3041 E mail support vxitech com Visit http www vxitech com for worldwide support sites and service plan information VM4016 Preface VXI Technology Inc VM4016 Preface www vxitech com SECTION 1 INTRODUCTION INTRODUCTION The VM4016 is a high performance Analog Comparator module which has been designed to monitor analog signals and cause VXIbus interrupts to occur when programmed input limits have been exceeded The instrument uses the message based word serial interface for programming and data movement as well as
36. command selects the input range of one or more channels The input range may be set for 10 volts or 100 volts Note The input offset is normalized to the 10 volt range The actual input offset in the 100 volt range is ten times the set value Examples Command Query INP RANG 100 91 35 7 Response Description Sets the input range for Channels 1 3 5 and 7 to 100 V INP RANG 7 100 Returns the set input range for Channel 7 Related Commands INPut OFFset voltage level channel list VMA016 Command Dictionary 75 VXI Technology Inc OUTPut POLarity EXTernal INTerrupt Purpose Sets the interrupt output polarity on the front panel Type Setting Command Syntax OUTPut POLarity EXTernal INTerrupt lt polarity gt lt polarity gt NORMal INVert RST Value NORMal Query Syntax OUTPut POLarity EXTernal INTerrupt Query Parameters N A Query Response ASCII string NORM INV Description The OUTput POLarity EXTernal INTerrupt command sets the polarity of the front panel interrupt output When the polarity 15 set for normal the output will be high when there 15 an interrupt event When set for invert the output will be low when there 15 an interrupt event Examples Command Query OUTP POL EXT INT NORM OUTP POL EXT INT Sets the front panel interrupt output polarity to normal NORM Returns the set val
37. d This interrupt will be ignored when INPut MASK INTerrupt is set to 0 Only when the channel s input goes below its threshold and then goes above the threshold for a period longer than the INPut DEBounce time will an interrupt be generated Example 2 If a channel is set for NORMal polarity and the channel s input is higher than its threshold an interrupt is generated This interrupt will be recognized when INPut MASK INTerrupt is set to 1 When the channel s input goes below its threshold and then goes above the threshold for a period longer than the INPut DEBounce time another interrupt will be generated Examples Command Quer INP MASK INT 1 Enables interrupt generation while changing mask values INP MASK INT 1 Indicates that Input Mask Interrupt is enabled Related Commands All INPut commands 72 VMA016 Command Dictionary www vxitech com INPut OFFSet Purpose Sets the input threshold for a group of channels Type Setting Command Syntax INPut OFFSet voltage level channel list voltage level 9 96 volts to 10 00 volts channel 115 gt standard channel list syntax supporting channels 1 to 16 RST Value 0 496V for all channels Query Syntax INPut OFFSet lt channel gt Query Parameters lt channel gt to 16 Query Response ASCII numeric value from 10 00 to 9 96 Description The INPut OFFSet command se
38. d input channel 1 is grounded The command and data for the SCPI command INP RANG is received by the control U1 and data U4 buffers and routed to the control FPGA U3 The control FPGA converts the parallel data for the relay This data RELAYDATA is synched to the 10 MHz drivers into a serial data stream RELAYCLK and written into the relay drivers when RELAYENA goes low The relay drivers will energize relay K9 selecting a gain of 0 1 for the differential amplifier U17A 36 VMA016 Programming www vxitech com The command and data for the SCPI command INP DEB is received by the control U1 and data U4 buffers and routed to the control FPGA U3 The register for the debounce circuitry is contained internally in the control FPGA The debounce register will be loaded with a value that corresponds to a 250 ms time delay The commands and data for the SCPI commands INP MASK are received by the control U1 and data U4 buffers and routed to the control FPGA U3 The mask register circuitry is contained internally in the control FPGA This register will be loaded so that Channels 2 through 16 are disabled or masked out The command for the SCPI command INP POL is received by the control U1 and data U4 buffers and routed to the control FPGA U3 The mask register and debounce circuitry uses this command to determine whether the input signal is an active high or an active low The input polarity has been programmed to
39. d Dictionary www vxitech com RST Purpose Resets the module s hardware and software to a known state Type IEEE 488 2 Common Command Command Syntax RST N A RST Value N A Query Syntax N A Query Parameters N A Query Response N A Description The Reset RST command resets the module s hardware and software to a known state See the command index at the beginning of this chapter for the default parameter values used with this command Examples Command Quer Response Description ARST Resets the module Related Commands N A VMA016 Command Dictionary 57 VXI Technology Inc SRE Purpose Sets the service request enable register Type IEEE 488 2 Common Command Command Syntax SRE lt mask gt lt gt Numeric ASCII value from 0 to 255 RST Value None Required Parameter Query Syntax SRE Query Parameters N A Query Response Numeric ASCII value from 0 to 255 Description The Service Request Enable SRE mask is used to control which bits in the status byte generate back plane interrupts If a bit is set in the mask that newly enables a bit set in the status byte and interrupts are enabled the module will generate a REQUEST TRUE event via an interrupt See the STB Command for the layout of bits Note Bit 6 1s always internally cleared to zero as required by IEEE 488 2 section 11 3 2 3 The layou
40. d to be in good condition it may be installed into an appropriate C size or D size VXIbus chassis in any slot other than slot 0 The chassis should be checked to ensure that it is capable of providing adequate power and cooling for the VM4016 Once the chassis is found be adequate the VM4016 s logical address and the chassis backplane jumpers should be configured prior to the VM4016 s installation CALCULATING SYSTEM POWER AND COOLING REQUIREMENTS It is imperative that the chassis provide adequate power and cooling for this module Referring to the chassis user s manual confirm that the power budget for the system the chassis and all modules installed therein is not exceeded and that the cooling system can provide adequate airflow at the specified backpressure It should be noted that if the chassis cannot provide adequate power to the module the instrument may not perform to specification or possibly not operate at all In addition if adequate cooling is not provided the reliability of the instrument will be jeopardized and permanent damage may occur Damage found to have occurred due to inadequate cooling would also void the warranty of the module VM4016 Preparation for Use 15 VXI Technology Inc SETTING THE CHASSIS BACKPLANE JUMPERS Please refer to the chassis User s Manual for further details on setting the backplane jumpers SETTING THE LOGICAL ADDRESS The logical address of the VM4016 is set by a single 8 posit
41. ed SCPI command Command Syntax None Query Only Command Parameters N A 5 Value N A Query Syntax STATus QUEStionable EVENt Query Parameters None Query Response 0 Description The Questionable Status Event Register is provided for SCPI compliance only The VM4016 does not alter the bits in this register and queries always report a 0 Examples Command Quer Response Description STAT QUES 0 Related Commands None 84 VM4016 Command Dictionary www vxitech com SYSTem ERRor Purpose Queries the Error Queue Type Required SCPI command Command Syntax None query only Command Parameters N A 5 Value N A Query Syntax SYSTem ERRor Query Parameters None Query Response ASCII string Description The System Error query is used to retrieve error messages from the error queue The error queue will maintain the two error messages If additional errors occur the queue will overflow and the second and subsequent error messages will be lost In the case of an overflow an overflow message will replace the second error message See the SCPI standard Volume 2 Command Reference for details on errors and reporting them Refer to the Error Messages section of this manual for specific details regarding the reported errors Examples Command Quer Response Description SYST ERR 350 Queue overflow Related Commands None
42. ed for input voltage comparison When a channel is programmed to be ON or 1 then it is enabled to generate interrupts If a channel is programmed to be OFF or 0 then it cannot generate VXiIbus interrupts Examples Command Query INP MASK 0 1 8 Makes Channels 1 8 incapable of generating VXIbus interrupts O Indicates that Channel 3 is incapable of generating VXIbus interrupts INP MASK 3 Related Commands VM4016 Command Dictionary 71 VXI Technology Inc INPut MASK INTerrupt Purpose Enable or disable interrupt generation when changing MASKs Type Setting Command Syntax INPut MASK INTerrupt lt boolean gt Niue lt gt 0 1 OFF RST Value 0 Query Syntax INPut MASK INTerrupt Query Parameters N A Query Response ASCII numeric 0 or 1 Description The INPut MASK INTerrupt command enables or disables interrupt generation when changing MASK values When set to 0 the RST state interrupts are temporarily disabled whenever MASK values are changed When set to 1 interrupts are generated even as MASK values are changed When a MASK is first enabled an interrupt 15 generated 1f a channel is beyond its threshold To create an interrupt when this occurs set this command to 1 Example 1 If a channel is set for NORMal polarity and channel s input is higher than its threshold an interrupt is generate
43. ed to the control FPGA at U3 The input signal COMPCHI has been compared with the reference voltage TRIGLEV1 as previously discussed and is routed to the debounce circuitry inside U3 see Figure 5 3 The debounce circuitry will not allow COMPCHI to pass through unless it is low for longer than the specified amount of time This circuitry is very useful in blocking out transients from generating false interrupt requests When the specified time limit has elapsed and COMPCHI 15 still active it will then be compared with the programmed value in the mask register Since COMPCHI 15 not masked out it is then OR ed with the remaining unmasked channels The first channel COMPCH1 to pass through the debounce circuitry and mask register will latch into an internal register called First Latch Register This register is available to the user for determination of the interrupting channel COMPCHI is used to clock an internal latch that in turn drives the LATIRQOUT signal on the front panel connector COMPCHI 15 also used in the pulse generation circuitry that generates the Interrupt Request IRQOUT pulse that is 500 ns wide When signal inversion is selected the interrupt will be generated when COMPCHI is less than the reference voltage TRIGLEVI The debounce circuitry and the mask register use this signal INV to determine polarity see Figure 5 3 INV determines whether COMPCHI is treated as an active low for normal and active high for an inverted s
44. egister Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands The Event Status Enable ESE command is used to set the bits of the Event Status Enable Register See ANSI IEEE 488 2 1987 section 11 5 1 for a complete description of the ESE register A value of 1 in a bit position of the ESE register enables generation of the Event Status Bit ESB in the Status Byte by the corresponding bit in the Event Status Register ESR If the ESB is set in the Service Request Enable SRE register then an interrupt will be generated See the ESR command for details regarding the individual bits The ESE register layout 15 Bit 0 Operation Complete Bit 1 Request Control Bit 2 Query Error Bit 3 Device Dependent Error Bit 4 Execution Error Bit 5 Command Error Bit 6 User Request Bit 7 Power On The Event Status Enable query reports the current contents of the Event Status Enable Register Command Query Response Description ESE 36 36 Returns the value of the event status enable register VMA016 Command Dictionary 53 Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands VXI Technology Inc ESR Queries and clears the Standard Event Status Register IEEE 488 2 Common Command N A Numeric ASCI
45. ess The module can be instructed to clear the first latched register on register access WS read using the INHOUSE CLEAR LATCH command When VXIbus backplane interrupting is enabled the module will generate interrupts whenever latching of the first latched register takes place If a Pseudo register access of the first latched register at offset 0x30 is performed or a Word Serial read using FETC LATC is performed the latch register gets cleared allowing further latching to occur provided the module has been instructed to clear the first latched register If the clearing of the first latched register is disabled after the first latching takes place the module cannot generate backplane interrupts Using the Direct Register Access backplane interrupts are generated when the latching takes place for the first time For further interrupting to occur the Word Serial FETC LATC query must be performed Two types of backplane interrupts can be generated They are a the reqt reqf in response to an IACK cycle or b a single backplane interrupt This can be configured using the INHOUSE REGINT command However it must be noted that the module can be configured for only for mode at any given point of time The former mode provides compatibility with the VXI standards and is the default mode The latter allows for faster processing since it cuts down servicing of interrupts by 5096 since only 1 interrupt needs to be serviced for each latch event
46. ess for very high speed data retrieval The register map is as specified in Table 3 1 In order to access the raw data using register access the register at offset 0x20 must be read Each bit in this register corresponds to the state of the 16 channel inputs unmasked and non inverted Bit 1 corresponds to Channel 1 Bit 2 corresponds to Channel 2 and so on This information can also be accessed using the Word Serial FETC RAW query In order to access the conditioned data using register access the register at offset 0x28 must be read Each bit in this register corresponds to the state of the 16 channel inputs masked and inverted Bit 1 corresponds to Channel 1 Bit 2 corresponds to Channel 2 and so on This information can also be accessed using the Word Serial FETC COND query In order to access the first latched information using register access the register at offset 0x30 must be read Each bit in this register corresponds to the state of the 16 channel inputs Bit 1 corresponds to Channel 1 Bit 2 corresponds to Channel 2 and so on This information can also be accessed using the Word Serial FETC LATC query For example a ifa value of 0x8000 is read from the first latched register then it means that Channel 16 s input has caused a latching b ifa value of OxF000 is read from the first latched register then it means that Channels 13 through 16 have caused a latching The Interrupt Enable register is a write only register on w
47. fferential 100 Single ended INPUT POLARITY Rising or Falling Edge DEBOUNCE TIME 9 6 us to 0 6291456 s 9 6 us resolution IRQ OUTPUT Open Collector Driver 200 mA max sink Internally pulled up to 5 V with 10 k resistor LATCHED IRQ OUTPUT Open Collector Driver 200 mA max sink Internally pulled up to 5 V with 10 k resistor VXI INTERFACE Message based word serial interface Direct register access in the user defined area of the VXIbus register map LOGICAL ADDRESSING Static or Dynamic Configuration RAW DATA REGISTER Logical Address 20H MASKED DATA REGISTER Logical Address 28H FIRST LATCHED REGISTER Logical Address 30H POWER REQUIREMENTS 4016 1 5 V 1 43 5 2 V 0 17 A 24 V 0 05 24 0 05 4016 2 5 V 2 12 A 5 2 V 0 29 A 24 V 0 10 A 24 0 10 A 4016 3 5 2 81 A 5 2 V 0 41 24 0 15 24 0 15 COOLING REQUIREMENTS VM4016 1 See Power Cooling Table VM4016 2 See Power Cooling Table VM4016 3 See Power Cooling Table 14 4016 Preparation for Use www vxitech com Section 2 SECTION 2 PREPARATION FOR USE INSTALLATION When the VM4016 is unpacked from its shipping carton the contents should include the following items One VM4016 VXIbus module One VM4016 Analog Comparator Module User s Manual this manual All components should be immediately inspected for damage upon receipt of the unit Once the VM4016 is assesse
48. for Channel 7 as 100 100 V INP RANG 10 4 6 Sets the input range for Channels 4 through 6 to 10 V INP RANG 5 Returns the input range for Channel 5 as 10 10 V VM4016 Programming 31 VXI Technology Inc OUTPUT POLARITY EXTERNAL INTERRUPT The output polarity external interrupt command sets the polarity of the front panel interrupt output When the poarity 1s set to normal the output will be low when there is an interrupt event When the polarity is set to invert the output will be high when there is an interrupt event OUTPut POLarity EXTernal INTerrupt polarity Where polarity is either NORMdal or INVert EXAMPLES OUTPucPOLarity EXTemal INTerrupt NORM Sets the external interrupt output polarity to a low pulse NORMal when an interrupt occurs OUTPutPOLarityEXTemal INTemupt Returns the external interrupt NORM output polarity as NORMal OUTP POL EXT INT INV Sets the external interrupt output polarity to INVert OUTP POL EXT INT Returns the polarity of the external INV interrupt output as INVert 32 VM4016 Programming www vxitech com OUTPUT POLARITY EXTERNAL LATCHED The output polarity external latched command sets the polarity of the front panel latched interrupt output When the polarity is set to normal the output will be low when there is an interrupt event When set to invert the output will be high when there is an interrupt event OUTPut POLarity EXTernal LATChed polarity Where
49. hassis ground WARNINGS Follow these precautions to avoid injury or damage to the product Use Proper Power Cord To avoid hazard only use the power cord specified for this product Use Proper Power Source avoid electrical overload electric shock or fire hazard do not use a power source that applies other than the specified voltage Use Proper Fuse To avoid fire hazard only use the type and rating fuse specified for this product VM4016 Preface WARNINGS CONT Avoid Electric Shock Ground the Product Operating Conditions Improper Use VXI Technology Inc To avoid electric shock or fire hazard do not operate this product with the covers removed Do not connect or disconnect any cable probes test leads etc while they are connected to a voltage source Remove all power and unplug unit before performing any service Service should only be performed by qualified personnel This product is grounded through the grounding conductor of the power cord To avoid electric shock the grounding conductor must be connected to earth ground To avoid injury electric shock or fire hazard Do not operate in wet or damp conditions Do not operate in an explosive atmosphere Operate or store only in specified temperature range Provide proper clearance for product ventilation to prevent overheating DO NOT operate if you suspect there is any damage to this product Product should be inspected or serviced only
50. he output voltage of U17A is divided by four 4 for compensation of DAC s full range output of 3 V Now that the flow of the circuitry has been established it can be observed how the circuitry works during normal operation For this example the signal 1 will be tied to ground A 5 VDC digital supply line will be monitored for voltage surges in excess 0 25 V The DAC is loaded with the binary serial data word 01101000 This provides a trigger level that is 1 313 The 5 input signal is applied to U17A s non inverting input The output BUFCHI of this amplifier is divided by 4 thus BUFCHI is equal to 1 25V This is compared with the reference voltage TRIGLEV1 of 1 313V Since TRIGLEV1 is higher than BUFCHI the comparator s output COMPCHI remains at 5V When the voltage on exceeds 5 25V BUFCHI will then be higher than TRIGLEVI This will drive the comparator to saturation and COMPCHI will equal 0 V INTERRUPT GENERATION interrupt generation circuitry is contained within U3 the control FPGA For the first part of the interrupt generation section Channel 1 COMPCHI polarity is normal The input channel signal inversion will be examined during the second part of this section It will be assumed that Channel 1 is the only activated channel and all others are masked out The command to specify the debounce time and input polarity is received in the data and command buffers and subsequently transferr
51. hich write operations take effect only in the Pseudo mode In order to enable backplane interrupting any non zero value must be written to this register at offset 0x38 Writing a zero to this register will disable any backplane interrupting It must be noted that in non pseudo mode any writes to this register will take no effect Backplane interrupting can also be enabled disabled using the Word Serial INHOUSE REG_ENABLE command 42 VM4016 Programming www vxitech com PSEUDO REGISTER ACCESS The VM4016 can be operated upon using a Word Serial Commands or b Register Access The VM4016 allows two types of register accesses a Direct Register Access using Hardware registers b Pseudo Register Access This can be configured using the INHOUSE PSEUDO command Direct Register Access is much faster than Pseudo Register Access However the former does not provide certain features provided by the latter Using Pseudo Register Access a a register read of FIRST LATCHED data allow another FIRST LATCHED event to occur b allows for clearing of the first latched register upon register access rather than a Word Serial FETC LATC and c allows configuration of the type of backplane interrupting The module can be enabled for backplane interrupts using the INHOUSE REG_ENABLE command It can also be done by writing a non zero value to the Interrupt Enable Register at offset 0x38 provided the module has been configured for Pseudo register acc
52. ic ASCII in the range 0 to 65535 Description The FETCh LATChed query reports the active signals in the First Latched register The First Latched register records the active signals when the first new input channel s crosses its threshold This information is also available at the VXIbus register level at offset 0x30 Examples Command Quer Response Description FETC LATC 1 Returns the active signal in the First Latched register Related Commands INHOUSE CLEAR LATCH 64 VM4016 Command Dictionary www vxitech com FETCh RAW Purpose Returns the state of the unconditioned unmasked and non inverted inputs Type Query Command Syntax N A N A RST Value N A Query Syntax FETCh RAW Query Parameters N A Query Response Numeric ASCII in the range 0 to 65535 Description The FETCh RAW query reports the 16 bit value that represents the current unconditioned unmasked and non inverted state of the inputs This information is also available at the register level at offset 0x20 Examples Command Quer Response Description FETC RAW 1 Returns the current unconditioned state of the inputs Related Commands FETch CONDitioned VMA016 Command Dictionary VXI Technology Inc INHOUSE CLEAR LATCH Purpose Controls whether the first latched information will be cleared when read by word serial or pseudo register access of the first latched
53. ignal 4016 Theory of Operation 91 FIGURE 5 3 INTERRUPT GENERATION VXI Technology Inc 92 4016 Theory of Operation www vxitech com C Command Dictionary essere 51 dee eaae deest deca irap Ran prego 15 D debounce circuitry sese direct register access Direct Register Access 48 sup SEDI oda 48 F FETCh CONDitioned sess 19 49 63 FETch LATChed m 20 FETCHhILATC d 49 64 EEICHRAWSJ2 eet eorpore tees 49 65 teen ee etes eei 21 I oo obti o so ERU d 48 INHOUSE CLEAR LATCH 25 49 66 INHOUSE PSEUDO 22 49 67 INHOUSE REG ENABLE sese 24 49 69 INHOUSE REGINT eee 23 49 68 Input Range 75 88 89 T put voltage ted ted erf 91 INPut DEbBounce 26 49 70 INPut 27 49 71 INPut MASK INTerrupt 28 49 72 INPut OFFSet 29 49 73 INPut POLarity 30 49 74 ete te hp 31 49 75 interrupt generation CH PARE ret RIPE L latched register logical address M mask register 0 37 40 OUTPut POLarity EXTernal INTerrupt OUTPut POLarity EXTernal INTerrupt NORM
54. ion DIP switch located near the module s backplane connectors this 15 the only switch on the module The switch is labeled with positions 1 through 8 and with an ON position A switch pushed toward the ON legend will signify a logic 1 switches pushed away from the ON legend will signify a logic 0 The switch located at position 1 is the least significant bit while the switch located at position 8 is the most significant bit See Figure 2 1 for examples of setting the logical address switch an m Eos ewer osition alue fna 12345678 12345678 1 1 SET 4 SET TO 8 2 2 3 4 4 8 ON ON 5 16 aid hh 6 32 12345678 12345678 7 64 SET TO 168 SET TO 255 8 128 Dynamic FIGURE 2 1 LOGICAL ADDRESS SWITCH SETTING EXAMPLES The VMIP may contain three separate instruments and will allocate logical addresses as required by the VXIbus specification revisions 1 3 and 1 4 It is necessary that the address of the first instrument the instrument closest to the top of the module be set at an address which is divisible by 4 and not set to 0 Switch positions 0 and 1 must always be set to the OFF position Therefore only addresses of 4 8 12 16 252 are allowed The address switch should be set for one of these legal addresses and the address for the second instrument the instrument in the center position will automatically be set to the switch set address plus one while the third instrument the instrument in the lowest po
55. leared if a hardware register read is used When the first latched information is cleared all the following reads will return a value of 0 until a new first latched event occurs It is important to note that all letters in the command must be provided as there is no short form for this command INHOUSE CLEAR_LATCH lt boolean gt Where boolean is 0 OFF 111 ON EXAMPLES INHOUSE CLEAR LATCH 1 Clears the first latched information on a read INHOUSE CLEAR LATCH Returns 1 stating that the first latched 1 information will be cleared on a read FETC LATC Reading the first latched information This 1 also clears the latched information FETC LATC Reading the first latched information 0 returns a value of 0 once the clearing of latch information was enabled assuming no further latching occurred VM4016 Programming 25 VXI Technology Inc INPUT DEBOUNCE The INPut DEBounce command sets the time period for the digital debounce circuitry This command affects all the 16 channels of the instrument It is important to note that the debounce resolution is 9 6 5 INPut DEBounce value Where value ranges from 9 6 us i e 0 0000096 s to 0 6291456 s EXAMPLES INPutDEBounce 9 6e 6 Sets the input debounce time for all channels to 0 0000096 s This will not allow a signal to generate an interrupt unless the input signal crosses the signal for more than 9 6 e 6 seconds INP DEB 0 6 Setting input debounce time to 0 6
56. llel data for the DAC U8 into a serial data stream This data DACDATA is synched to the 10 MHz gated clock DACCLK and loaded into the DAC when the DACLOAD signal goes high The DAC output TRIGLEV where is equal to the Channel number The DAC will output TRIGLEV 1 for the comparator at U13A and TRIGLEV2 for the comparator at U13B The commands for the SCPI command OUTP POL EXT INT are received by the control U1 and data U4 buffers and routed to the control FPGA U3 U3 uses this command to determine whether the external interrupt signal should be an active high or an active low This has been programmed to NORM so as to cause U3 to output an active high EXTIRQ signal to the front panel connector when an interrupt occurs This signal will be a pulse 500 ns wide The output of the differential amplifier U17A BUFCHI is voltage divided by 4 Since the gain of U17A is 1 0 this makes BUFCHI 1 250 V when reaches 5 0 V BUFCHI is compared with the output of U8 TRIGLEVI by comparator U13A When BUFCHI is greater than TRIGLEV1 the output of COMPCHI goes low is routed to debounce circuitry inside U3 The output of the differential amplifier U17B BUFCH2 15 voltage divided by 4 Since the gain of U17B is 1 0 this makes BUFCH2 1 250 V when CH2 reaches 5 0 V BUFCH2 is compared with the output of U8 TRIGLEV2 by comparator U13B When BUFCH2 is less than TRIGLEVZ2 the output of U13B COMPCH2 goes high
57. nnel lor 2 to generate an interrupt INP MASK 0 3 16 Disables Channels 3 through 16 from generating an interrupt INP POL NORM 1 Selects Channel 1 to generate an interrupt when Channel 1 is greater than the offset voltage INP POL INV 2 Selects Channel 2 to generate an interrupt when Channel 2 is less than the offset voltage INP OFFS 5 25 1 Selects 5 25 volts as the offset reference voltage for Channel 1 INP OFFS 4 75 2 Selects 4 75 volts as the offset reference voltage for Channel 2 OUTP POL EXT INT NORM Sets the external interrupt output to be active high Figure 3 2 and the explanation that follows illustrates what is occurring during this example 38 VM4016 Programming www vxitech com INPUT SIGNAL FROM FRONT PANEL CONNECTOR CH1 IRQ CONTROL DACDATA TO lt BUS DACLOAD DACCLK K9 DAC BUFCH1 gt TRIGLEV1 1K TRIGLEV2 S gt 1 a CONTROL DATA 0 15 8 100K FIGURE 3 2 BRACKETING AN INPUT VOLTAGE TRIGLEV2 BUFCH2 470K VCC 47K 47K IRQOUT COMPCH2 1K The command and data for the SCPI command INP RANG are received by the control U1 and data U4 buffers not shown for clarity and routed to the control FPGA U3 The control FPGA converts the parallel data for the relay drivers into
58. ntil the No Operation Pending message is true This command makes sure that all previous commands have been executed before proceeding It provides a way of synchronizing the module with its commander Examples Command Query Response Description Pauses the execution of additional commands until the No Operation Pending message is true Related Commands 62 VMA016 Command Dictionary www vxitech com INSTRUMENT SPECIFIC SCPI COMMANDS FETCh CONDitioned Purpose Returns the state of the conditioned masked and inverted inputs Type Query Command Syntax N A N A RST Value N A Query Syntax FETCh CONDitioned Query Parameters None Query Response Numeric ASCII in the range of 0 to 65535 Description The FETCh CONDitioned query reports the 16 bit value that represents the current conditioned masked and inverted state of the inputs This information is also available at the VXIbus register level at offset 0x28 Examples Command Query Response Description FETC COND O Returns the current conditioned state of the inputs Related Commands FETch RAW VM4016 Command Dictionary VXI Technology Inc FETCh LATChed Purpose Reports the active signals in the First Latched register Type Query Command Syntax N A N A RST Value N A Query Syntax FETCh LATChed Query Parameters N A Query Response Numer
59. ogy formerly National Bureau of Standards to the extent allowed by that organization s calibration facility and to the calibration facilities of other International Standards Organization members WARRANTY The product referred to herein is warranted against defects in material and workmanship for a period of three years from the receipt date of the product at customer s facility The sole and exclusive remedy for breach of any warranty concerning these goods shall be repair or replacement of defective parts or a refund of the purchase price to be determined at the option of VTI For warranty service or repair this product must be returned to a VXI Technology authorized service center The product shall be shipped prepaid to VTI and VTI shall prepay all returns of the product to the buyer However the buyer shall pay all shipping charges duties and taxes for products returned to VTI from another country VTI warrants that its software and firmware designated by VTI for use with a product will execute its programming when properly installed on that product VTI does not however warrant that the operation of the product or software or firmware will be uninterrupted or error free LIMITATION OF WARRANTY The warranty shall not apply to defects resulting from improper or inadequate maintenance by the buyer buyer supplied products or interfacing unauthorized modification or misuse operation outside the environmental specifications for
60. ology Inc TABLE 4 1 IEEE 488 2 COMMON COMMANDS Description Clears the Status Register Sets the Event Status Enable Register Query the Standard Event Status Register Query the module identification string Set the OPC bit in the Event Status Register X Query the Status Byte Register Starts and reports a self test procedure Halts execution and queries RST RST Value N A N A N A N A 48 VMA016 Command Dictionary www vxitech com TABLE 4 2 INSTRUMENT SPECIFIC SCPI COMMANDS Command Description RST RST Value FETCh CONDitioned Reads back the 16 bit value that represents the current conditioned masked and inverted output state of the comparators in the group FETCh LATChed Read back the 16 bit value that was latched when the first input s in the group caused an active edge FETCh RAW Reads back the 16 bit value that represents the current unconditioned no masking or inversion output state of the comparators in the group INHOUSE PSEUDO Sets the type of register interface used INHOUSE REGINT Controls type of interrupt response 0 INHOUSE REG ENABLE Interrupt masking X information group of the analog comparators channels when changing MASKs group of channels INPut POLarity Sets the polarity for a group of X NORMAL channels INPut RANGe 100 OUTPut POLarity EXTernal INTerrupt Sets the polarit
61. rns a 16 bit value that reports the active signals in the First Latched register The First Latched register records the active signals when the first new input channel crossed its threshold It is important to note that the above information is also available at the VXIbus register level at offset 0x30 FETch LATChed No query parameters EXAMPLES FETChLATChed Returns the active signals in the First 1 Latched register Channel 1 FETCLATC Returns the active signals in the First 3 Latched Register Channels 1 and 2 20 VMA016 Programming www vxitech com FETCH RAW The FETCh RAW query returns the 16 bit value that represents the current unconditioned unmasked and non inverted state of the inputs It is important to note that the above information is also available at the register level at offset 0x20 FETCH RAW No query parameters EXAMPLES FETch RAW Returns the state of the unconditioned 1 unmasked and non inverted inputs Channel 1 FETCRAW All 16 channels crossed the programmed 65535 threshold VM4016 Programming 21 VXI Technology Inc INHOUSE PSEUDO The INHOUSE PSEUDO command controls the use of the register interface Pseudo set true specifies that pseudo register interface should be used Pseudo set false specifies that the hardware register interface should be used The value set takes effect next time the unit powers up does not take effect immediately The pseudo register interface allo
62. rt channel 115 gt standard channel list syntax supporting channels 1 to 16 RST Value for all channels Query Syntax INPut POLarity lt channel gt Query Parameters lt channel gt to 16 Query Response ASCII string NORM INV Description The INPut POLarity command selects the input polarity for one or more channels When a channel is programmed for normal polarity an interrupt will occur when the input voltage is greater than the programmed input offset for the channel The invert polarity will cause an interrupt when the input voltage is less than the programmed input offset for the channel Examples Command Query INP POL INV 5 12 INP POL 6 Response Description Inverts the input polarity for Channels 5 12 INV Indicates the polarity for Channel 6 is inverted Related Commands INPut OFFset INPut RANGe 74 VM4016 Command Dictionary www vxitech com INPut RANGe Purpose Sets the input range for one or more channels Type Setting Command Syntax INPut RANGe lt range gt lt channel_list gt lt range gt 10 100 lt channel_list gt standard channel list syntax supporting channels to 16 RST Value 100 for all channels Query Syntax INPut RANGe channel Query Parameters channel 1 to 16 Query Response Numeric ASCII value 10 100 Description The Input Range
63. s INP DEB Returns the input debounce time as 0 6 s 0 6 26 VMA016 Programming www vxitech com INPUT MASK The INPut MASK command enables or disables input channels from generating interrupts or recording data in the conditional register If a channel is programmed to be ON or 1 then it is enabled to generate interrupts If a channel is programmed to be OFF or 0 then it cannot generate VXIbus interrupts INPut MASK lt state gt lt channel_list gt Where state is 0 OFF 11 ON Where lt channel_list gt is standard channel list format supporting channels 1 through 16 EXAMPLES INPuc MASK ON 1 8 Enables channels 1 through 8 to generate interrupts INPutMASK 3 Reports that channel 3 is enabled for 1 voltage comparison INP MASK 9 Reports that channel 9 is not enabled for 0 voltage comparison VM4016 Programming 27 VXI Technology Inc INPUT MASK INTERRUPT The INPut MASK INTerrupt command enables or disables interrupt generation when changing MASK values When set to 0 the RST state interrupts are temporarily disabled whenever MASK values are changed When set to 1 interrupts are generated even as MASK values are changed INPut MASK INTerrupt boolean Where boolean is 0 OFF 1 ON EXAMPLES INPuc MASK INT Disables interrupt generation INPutMASK INT Reports that interrupt generation is disabled 0 28 VM4016 Programming www vxitech com INPUT OFFSET The JNPut
64. s None Query Response 0 Description The Questionable Status Condition Register query is provided for SCPI compliance only The VM4016 does not alter any of the bits in this register and a query always reports a 0 Examples Command Quer Response Description STAT QUES COND 0 Related Commands None 82 VMA016 Command Dictionary www vxitech com STATus QUEStionable ENABle Purpose Sets the Questionable Status Enable Register Type Required SCPI command Command Syntax STATus QUEStionable ENABle lt NRf gt Command Parameters lt NRf gt numeric ASCII value from 0 to 32767 RST Value NRf must be supplied Query Syntax STATus QUEStionable ENABle Query Parameters None Query Response Numeric ASCII value from 0 to 32767 Description The Status Questionable Enable command sets the bits in the Questionable Status Enable Register This command is provided only to comply with the SCPI standard The Status Questionable Enable query reports the contents of the Questionable Status Enable Register The VM4016 does not alter the bit settings of this register and will report the last programmed value Examples Command Quer STAT QUES ENAB 64 STAT QUES ENAB Related Commands None VMA016 Command Dictionary 83 VXI Technology Inc STATus QUEStionable E VE Nt Purpose Queries the Questionable Status Event Register Type Requir
65. s communication status When a successful Access occurs the LED will blink green during data transfer and command query operations In the event of an unrecognized command or other data related error the ACC ERR LED will illuminate red If there is no command query activity and no errors the ACC ERR LED will be extinguished The normal state of the LEDs on a properly functioning idle instrument is for the FAIL LED to be green and the ACC ERR LED to be off DESCRIPTION The 4016 is a high performance Analog Comparator module with 16 input channels per VMIP daughter module Each input channel consists of a differential amplifier with a gain of 1 or 0 1 giving an input range of 10 volts or 100 volts Each input is compared against a reference voltage derived from an independent 8 bit DAC Each input signal is digitally debounced for a programmed time ranging from approximately 10 ws to 0 5 seconds This prevents input signal noise from causing undesired interrupts After debounce the signal may be programmatically inverted to select the input transition edge of interest rising or falling edge and masked to prevent unused channels from causing interrupts of the masked inputs are OR d together to produce a single interrupt signal This interrupt signal is used to generate a VXIbus interrupt as well as the front panel interrupt outputs All active input is recorded as a 1 Once the V XIbus interrupt 15 serviced by the slot 0 con
66. sition will automatically be set to the switch set address plus two If dynamic address configuration is desired the address switch should be set for a value of 255 Upon power up the slot 0 resource manager will assign logical addresses to each instrument in the VMIP module FRONT PANEL INTERFACE WIRING The VM4016 s interface is made available on the front panel of the instrument The 16 channel version VM4016 1 will have J201 that contains all signals for this instrument The 32 channel version 4016 2 will have J201 and 1202 provided while the 48 channel version 4016 3 will have J200 J201 and J202 The wiring for each of these connectors is identical and since each group of 16 channels is treated as a separate instrument the module will have three Channel 1s three Channel 2s three Channel 35 etc VM4016 Preparation for Use www vxitech com The connector used in the VM4016 is a commonly available 44 pin high density DSUB receptacle connector A mating solder cup pin connector from AMP is included crimp type connectors are available from a variety of sources TABLE 2 1 ANALOG COMPARATOR PIN OUTS SIGNAL CHANNEL 1 CHANNEL 1 GROUND CHANNEL 4 CHANNEL 4 CHANNEL 7 CHANNEL 7 GROUND CHANNEL 10 CHANNEL 10 CHANNEL 13 4 CHANNEL 13 GROUND IRQ OUTPUT GROUND CHANNEL 2 CHANNEL 2 GROUND CHANNEL 5 CHANNEL 5 CHANNEL 8 CHANNEL 8 PIN NUMBER
67. sponse as two backplane interrupts for each latched event INHOUSE REGENT Returns the type of module interrupt 0 response as 0 VM4016 Programming 23 VXI Technology Inc INHOUSE REG ENABLE The INHOUSE REG ENABLE command controls the masking for REGINT REG ENABLE 0 means that backplane interrupts cannot be generated If the REG ENABLE 15 1 then backplane interrupts can be generated If PSEUDO is set then a write to the register at offset 0x38 also controls the masking Enable or disable capabilities are provided in the pseudo register interface to allow a complete register interface It is important to note that all letters of the command must be provided as there is no short form for this command INHOUSE REG ENABLE boolean Where boolean is 0 OFF 1 ON EXAMPLES INHOUSE REG ENABLE 1 Enables the REGINT type interrupt generation INHOUSE REG ENABLE Returns 1 to state that backplane 1 interrupting is currently enabled INHOUSE REG ENABLE 0 Disabling REGINT interrupt generation INHOUSE REG ENABLE Returns 0 to state that backplane 0 interrupting is currently disabled 24 VMA016 Programming www vxitech com INHOUSE CLEAR_LATCH The INHOUSE CLEAR LATCH command determines whether the first latched information will be cleared when the information is read by word serial FETch LATChed Command or if pseudo is set and a register read of the first latched information occurs The information will not be c
68. supporting direct register access for very high speed data retrieval The VM4016 command set conforms with the SCPI standard for consistency and ease of programming The VM4016 is a member of the VXI Technology VMIP VXI Modular Instrumentation Platform family and is available as a 16 32 or 48 channel single wide VXIbus instrument In addition to these three standard configurations the VM4016 may be combined with any of the other members of the VMIP family to form a customized and highly integrated instrument see Figure 1 1 This allows the user to reduce system size and cost by combining the VM4016 with two other instrument functions in a single wide C size VXIbus module Figure 1 2 shows the 48 channel version of the VM4016 The 32 channel version would not have J200 and its associated LEDs and nomenclature while the 16 channel version would also eliminate J202 FIGURE 1 1 VMIP PLATFORM VM4016 Preparation for Use 11 VXI Technology Inc Regardless of whether the VM4016 is configured with other VM4016 modules or with other VMIPmodules each group of 16 channels is treated as an independent instrument in the VXIbus chassis and as such each group has its own FAIL and ACCESS light The FAIL LED 15 a Power Fault indicator When normal power up conditions exist the FAIL LED will illuminate green When a power on fault condition occurs the FAIL LED will illuminate red The ACC ERR LED indicate
69. t of the Service Request Enable Register is Bit 0 Unused Bit 1 Unused Bit 2 Error Queue Has Data Bit 3 Questionable Status Summary Not Used Bit 4 Message Available Bit 5 Event Status Summary Bit 6 0 per IEEE 488 2 section 11 3 2 3 Bit 7 Operation Status Summary Examples Command Query Response Description SRE 4 Sets the service request enable register SRE 4 Returns the value of the SRE register Related Commands N A 58 VMA016 Command Dictionary www vxitech com STB Purpose Queries the Status Byte Register Type IEEE 488 2 Common Command Command Syntax N A 5 N A RST Value N A Query Syntax STB Query Parameters N A Query Response Numeric ASCII value from 0 to 255 Description The Read Status Byte STB query fetches the current contents of the Status Byte Register See the IEEE 488 2 specification for additional information regarding the Status byte Register and its use The layout of the Status Register is Bit 0 Unused Bit 1 Unused Bit 2 Error Queue Has Data Bit 4 Questionable Status Summary not used Bit 5 Message Available Bit 6 Master Summary Status Bit 7 Operation Status Summary Examples Command Quer Response Description 16 Queries the Status Byte Register Related Commands N A VM4016 Command Dictionary 59 VXI Technology Inc
70. tails the exact command format Describes the parameters sent with the command and their legal range Describes the values assumed when the RST command is sent Details the exact query form of the command Describes the parameters sent with the command and their legal range The default parameter values are assumed the same as in the command form unless described otherwise Describes the format of the query response and the valid range of output Describes in detail what the command does and refers to additional sources Present the proper use of each command and its query when available Lists commands that affect the use of this command or commands that are affected by this command VMA016 Command Dictionary 51 VXI Technology Inc COMMON SCPI COMMANDS CLS Purpose Clears all status and event registers Type IEEE 488 2 Common Command Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description This command clears the Status Event Register Operation Status Register and the Questionable Data Signal Register It also clears the OPC flag and clears all queues except the output queue Examples Command Query Response Descriptions ACLS Clears all status and event registers Related Commands N A 52 VMA016 Command Dictionary www vxitech com Purpose ESE Sets the bits of the Event Status Enable R
71. tate of inputs NP MASK 1 1 2 NP MASK 0 3 16 NP RANG 10 1 2 NP OFFS 5 25 1 2 NP POL NORM 1 2 FETC LATC FETC RAW 65535 FETC COND 3 Enables Channels 1 and 2 for interrupt generation Disables Channels 3 through 16 from generating an interrupt Selects 10 volts as the input range for Channel 1 and 2 Selects 5 25 volts as the offset voltage for Channels 1 and 2 Selects both Channel 1 and 2 to generate an interrupt when Channels 1 and 2 are greater than the offset voltage Returns the active signal in the First Latched Register Returns the State of unconditioned ummasked and non inverted inputs Returns the state of masked and inverted inputs 34 VM4016 Programming www vxitech com SINGLE CHANNEL OPERATION This example is for controlling a device that can tolerate a maximum input voltage level at 35 VDC for a maximum time of 250 ms before damage will occur The input power to this device is provided from a remote source that can be disabled A low signal applied to the power source remote inhibit will disable its output The controller will then be notified that an out of tolerance condition has occurred and the device was shut down The following code is for monitoring a single input for voltage level that exceeds 35VDC for longer than 250 ms A low latched output is required to be generated upon detection of the interrupt th
72. the product or improper site preparation or maintenance VXI Technology Inc shall not be liable for injury to property other than the goods themselves Other than the limited warranty stated above VXI Technology Inc makes no other warranties express or implied with respect to the quality of product beyond the description of the goods on the face of the contract VTI specifically disclaims the implied warranties of merchantability and fitness for a particular purpose RESTRICTED RIGHTS LEGEND Use duplication or disclosure by the Government is subject to restrictions as set forth in subdivision b 3 11 of the Rights in Technical Data and Computer Software clause in DFARS 252 227 7013 VXI Technology Inc 2031 Main Street Irvine CA 92614 6509 U S A VM4016 Preface 5 VXI Technology Inc DECLARATION OF CONFORMITY Declaration of Conformity According to ISO IEC Guide 22 and EN 45014 MANUFACTURER S NAME VXI Technology Inc MANUFACTURER S ADDRESS 2031 Main Street Irvine California 92614 6509 PRODUCT NAME Analog Comparator MODEL NUMBER S VMA016 PRODUCT OPTIONS All PRODUCT CONFIGURATIONS All VXI Technology Inc declares that the aforementioned product conforms to the requirements of the Low Voltage Directive 73 23 EEC and the EMC Directive 89 366 EEC inclusive 93 68 EEC and carries the CE mark accordingly The product has been designed and manufactured according to the following specifications SAFETY E
73. troller the First Latched Register will be cleared The state of each channel s debounced input and the inverted and masked status may be read directly in the user defined area of the VXIbus registers as can the First Latched register This information may also be retrieved using the message based word serial interface The block diagram of Figure 1 3 shows the overall functionality of the VM4016 Analog Comparator instrument FIGURE 1 2 FRONT PANEL LAYOUT VM4016 Preparation for Use www vxitech com VXI MODULE PANEL CHANNEL 1 OF TO VxIBUS COMPARE REGISTERS DIFFERENTIAL AMPLIFIER X1 OR DEBOUNCE COMPARATOR 160810058 8BITDAC INVERT REGISTER MASK REGISTER WIERRUPT Vitus AND FIRST FRIST INTERRUPT CHANNEL 16 OF ERU INVERT REGISTER LATON INTERRUPT REGISTER REGISTER INVERT REGISTER FIGURE 1 3 VM4016 BLOCK DIAGRAM VM4016 Preparation for Use 13 VXI Technology Inc VM4016 GENERAL SPECIFICATIONS GENERAL SPECIFICATIONS CHANNELS VM4016 1 16 VM4016 2 32 VM4016 3 48 INPUT RANGE 10 0 V 100 V INPUT THRESHOLD 10 0 V 78 mV 100 0 V 780 mV INPUT TYPE Differential may be configured for single ended by grounding the negative input INPUT IMPEDANCE 200 kQ Di
74. ts the input threshold for a channel or group of channels over which the input signal must cross to cause an interrupt event This command sets the value in the 8 bit DAC to which the input signal is compared It is important to note that the actual input offset value is affected by the INPut RANGe command as the response has been normalized to 10 V range The actual input offset for the allowable ranges are as follows Range Entered Threshold Actual Threshold 10 0 X 1 0x 100 0 Examples INP RANG 100 9 16 Selects an input range of 100 V for Channels 9 16 Selects an input threshold of 25 V for Channels 9 16 2 500 Returns the set input threshold for Channel 11 of 25 V Selects an input range of 10 V for Channels 1 8 Selects an input threshold of 2 5 V for Channels 1 8 2 500 Returns the set input threshold for Channel 110f2 5 V INP OFFS 2 5 99 16 INP OFFS 11 INP RANG 10 1 8 INP OFFS 2 5 1 8 INP OFFS 5 Related Commands INPut RANGe lt range gt lt channel_list gt INPut POLarity lt polarity gt lt channel_list gt VMA016 Command Dictionary 73 VXI Technology Inc INPut POLarity Purpose Sets the input polarity for one or more channels Type Setting Command Syntax INPut POLarity lt polarity gt lt channel_list gt lt polarity gt NORMal INVe
75. ue for the front panel interrupt output polarity Related Commands 76 VMA016 Command Dictionary www vxitech com OUTPut POLarity E XTernal LATC hed Purpose Sets the latched interrupt output polarity on the front panel Type Setting Command Syntax OUTPut POLarity EXTernal LATChed lt polarity gt lt polarity gt NORMal INVert 5 Value NORMal Query Syntax OUTPut POLarity EXTernal LATChed Query Parameters N A Query Response ASCII string NORM INV Description The OUTput POLarity EXTernal LATChed command sets the polarity of the front panel latched interrupt output When the polarity is set for normal the output will be high when there is an interrupt event When set for invert the output will be low when there is an interrupt event Examples Command Query Response Description Sets the polarity of the front panel latched interrupt output to inverted INV Returns the value for the front panel latched interrupt output Related Commands VMA016 Command Dictionary TI VXI Technology Inc REQUIRED SCPI COMMANDS STATus OPERation CONDition Purpose Queries the Operation Status Condition Register Type Required SCPI command Command Syntax None query only Command Parameters N A RST Value N A Query Syntax STATus OPERation CONDition Query Parameters None Query Response
76. ws the use of REG ENABLE and CLEAR LATCH capability from the registers Although the hardware register interface 15 much faster than the pseudo register interface it lacks the above two features It is important to note that when the module is shipped from the factory pseudo is set to 1 It is also important to note that all letters of the command must be provided as there is no short form for this command INHOUSE PSEUDO boolean Where boolean is 0 OFF 111 ON EXAMPLES INHOUSE PSEUDO 1 Sets the pseudo register interface ON The unit must be powered for the change to take effect INHOUSE PSEUDO Returns 1 which states that the register 1 interface is set to pseudo 22 VMA016 Programming www vxitech com INHOUSE REGINT The INHOUSE REGINT command controls the type of module s response to an interrupt acknowledge cycle ack cycle When regint is set to false the module uses reqt reqf request true request false provided the latched interrupt bit is set in the SRE It is important to note that all the letters of the command must be provided as there is no short form for this command INHOUSE REGINT lt boolean gt Where boolean is 0 OFF 111 ON EXAMPLES INHOUSE REGINT 1 Sets the type of module interrupt response to one backplane interrupts for every first latched event INHOUSE REGINT Returns the type of module interrupt 1 response as 1 INHOUSE REGINT O Sets the type of module interrupt re
77. y for the interrupt X NORMAL output on the front panel for one of the three groups OUTPut POLarity EXTernal LATChed Sets the polarity for latched interrupt X NORMAL output on the front panel for one of the three groups VMA016 Command Dictionary 49 VXI Technology Inc TABLE 4 3 SCPI REQUIRED COMMANDS Command STATus OPERation STATus OPERation ENABle STATus OPERation EVENt STATus PRESet STATus QUEStionable CONDition STATus QUEStionable EN ABle STA Tus QUEStionable EVENt SYSTem ERRor SYSTem VERsion Description RST RST Value Queries the Operation Status Condition Register Sets the Operation Status Enable Register Queries the Operation Status Event Register X Presets the Status Register Queries the Questionable Status X Condition Register Sets the Questionable Status Enable X Register X Queries the Questionable Status Event Register Queries the Error Queue X Clears Queue Queries which version of the SCPI N A standard the module complies with 50 VMA016 Command Dictionary www vxitech com COMMAND DICTIONARY The remainder of this section is devoted to the actual command dictionary Each command is fully described on its own page In defining how each command is used the following items are described Describes the purpose of the command Describes the type of command such as an event or setting De

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