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Texas Instruments SM320C6455-EP User's Manual

1. INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 3 C6455 EDMAS3 Channel Synchronization Events continued EDMA BINARY EVENT NAME EVENT DESCRIPTION CHANNEL 18 19 20 001 0100 INTDST1 RapidlO Interrupt 1 21 27 None 28 001 1100 VCP2REVT VCP2 receive event 29 001 1101 VCP2XEVT VCP2 transmit event 30 001 1110 TCP2REVT TCP2 receive event 31 001 1111 TCP2XEVT TCP2 transmit event 32 010 0000 UREVT UTOPIA receive event 33 39 40 010 1000 transmit event 41 43 None 44 010 1100 ICREVT 2 receive event 45 010 1101 ICXEVT 2 transmit event 46 47 48 011 0000 GPINTO GPIO event 0 49 011 0001 GPINT1 GPIO event 1 50 011 0010 GPINT2 GPIO event 2 51 011 0011 GPINT3 GPIO event 3 52 011 0100 GPINT4 GPIO event 4 53 011 0101 GPINT5 GPIO event 5 54 011 0110 GPINT6 GPIO event 6 55 0110111 GPINT7 GPIO event 7 56 011 1000 GPINT8 GPIO event 8 57 011 1001 GPINT9 GPIO event 9 58 011 1010 GPINT10 GPIO event 10 59 011 1011 GPINT11 GPIO event 11 60 011 1100 GPINT12 GPIO event 12 61 011 1101 GPINT13 GPIO event 13 62 011 1110 GPINT14 GPIO event 14 63 011 1111 GPINT15 GPIO event 15 7 43 EDMAS Peripheral Register Description s Table 7 4 EDMA3 Channel Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME
2. HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 0220 RIO_DOORBELL2_ICSR DOORBELL Interrupt Condition Status Register 2 02D0 0224 Reserved 02D0 0228 RIO_DOORBELL2_ICCR DOORBELL Interrupt Condition Clear Register 2 02D0 022C Reserved 02D0 0230 RIO_DOORBELL3_ICSR DOORBELL Interrupt Condition Status Register 3 02D0 0234 Reserved 02D0 0238 RIO_DOORBELL3_ICCR DOORBELL Interrupt Condition Clear Register 3 02D0 023C Reserved 02D0 0240 RIO_RX_CPPI_ICSR RX CPPI Interrupt Condition Status Register 02D0 0244 Reserved 02D0 0248 RIO_RX_CPPI_ICCR RX CPPI Interrupt Condition Clear Register 02D0 024c Reserved 02D0 0250 RIO TX CPPI ICSR TX CPPI Interrupt Condition Status Register 02D0 0254 Reserved 02D0 0258 RIO TX CPPI ICCR TX CPPI Interrupt Condition Clear Register 02D0 025C Reserved 02D0 0260 RIO LSU ICSR LSU Interrupt Condition Status Register 02D0 0264 Reserved 02D0 0268 RIO LSU ICCR LSU Interrupt Condition Clear Register 02D0 026C Reserved 02D0 0270 RIO ERR RST EVNT ICSR Error Reset and Special Event Interrupt Condition Status Register 02D0 0274 ia Reserved 02D0 0278 RIO_ERR_RST_EVNT_ICCR Error Reset and Special Event Interrupt Condition Clear Register 02D0 027 Reserved 02D0 0280 RIO_DOORBELLO_ICRR DOORBELLO Interrupt Condition Routing Register 02D0 0284 RIO DOORBELLO ICRR2 DOORBELL 0 Interrupt Condition Routing Register 2 0200 0288 0200 028C Reser
3. 165 7 10 3 2 Programmable Synchronous Interface Timing 168 7 10 4 i de TR RE ERE caches 171 7 1405 IB ize 172 2 no 2172 TATA 5 7 11 2 12C Peripheral Register Description s 72 FAVS 12C Electrical Data Timihig 176 7 11 31 Inter Integrated Circuits I2C Timing 176 Host Port Interface HPI Peripheral JI LULU sas asiaaisa sa mamaiaisawwsawassqsatagakguwwswsaa 179 7121 HPI Device Specgific INFOFMALION nenne sensn EEEE 179 7 12 2 HPI Peripheral Register Description s 178 Z12339 180 Multichannel Buffered Serial Port MCBSP
4. HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0000 TXIDVER Transmit Identification and Version Register 02C8 0004 TXCONTROL Transmit Control Register 02C8 0008 TXTEARDOWN Transmit Teardown Register 02C8 000F Reserved 02C8 0010 RXIDVER Receive Identification and Version Register 02C8 0014 RXCONTROL Receive Control Register 02C8 0018 RXTEARDOWN Receive Teardown Register 02C8 001C Reserved 02C8 0020 02C8 007 Reserved 02C8 0080 TXINTSTATRAW Transmit Interrupt Status Unmasked Register 02C8 0084 TXINTSTATMASKED Transmit Interrupt Status Masked Register 02C8 0088 TXINTMASKSET Transmit Interrupt Mask Set Register 02C8 008G TXINTMASKCLEAR Transmit Interrupt Mask Clear Register 02C8 0090 MACINVECTOR MAC Input Vector Register 02C8 0194 02C8 019 Reserved 02C8 01A0 RXINTSTATRAW Receive Interrupt Status Unmasked Register 01C8 01A4 RXINTSTATMASKED Receive Interrupt Status Masked Register 01C8 01A8 RXINTMASKSET Receive Interrupt Mask Set Register 01C8 01AC RXINTMASKCLEAR Receive Interrupt Mask Clear Register 01C8 01BO MACINTSTATRAW MAC Interrupt Status Unmasked Register 01C8 01B4 MACINTSTATMASKED MAC Interrupt Status Masked Register 01C8 01B8 MACINTMASKSET MAC Interrupt Mask Set Register 01C8 01BC MACINTMASKCLEAR MAC Interrupt Mask Clear Register 02C8 00 0 02C8 00 Reserved 02C8 0100 RXMBPENABLE Receive Multicast Broadcast Promiscuous Channel Enable Register 02C8 0104 RXUNICASTSET
5. 216 7 14 4 3 Electrical Data Timing U 217 EI Y 218 7 15 1 Timers Device Specific Information U 218 7 15 2 Timers Peripheral Register Description s 218 7 15 3 Timers Electrical Data Timing 2 IH HI mH emen nnn nnn 219 Enhanced Viterbi Decoder Coprocessor VCP2 220 7 16 1 VCP2 Device Specific 220 716 2 VCP2 Peripheral Register Description s 1 220 Contents 5 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 17 Enhanced Turbo Decoder Coprocessor TCP2 221 7 17 1 2 Device Specific Information UU 221 7 17 2 TCP2 Peripheral Register Description s 222 7 18 Peripheral Component Interconnect PCI 223
6. 720 850 A 1000 1000 NO 1200 1000 Mbps GMII Only 100 Mbps 10 Mbps MIN MAX MIN MAX MIN MAX 1 tc MRCLK Cycle time MRCLK 8 40 400 ns 2 tw MRCLKH Pulse duration MRCLK high 2 8 14 140 ns 3 tw MRCLKL Pulse duration MRCLK low 2 8 14 140 ns 4 ty MRCLK Transition time MRCLK 1 3 3 ns 4 b 1 d MRCLK Input Figure 7 59 MRCLK Timing Receive MII and GMII Operation Table 7 76 Timing Requirements for MTCLK MII and GMII Operation see Figure 7 60 720 850 A 1000 1000 NO 1200 UNIT 100 Mbps 10 Mbps MIN MAX MIN MAX 1 te MTCLK Cycle time MTCLK 40 400 ns 2 tw MTCLKH Pulse duration MTCLK high 14 140 ns 3 tw MTCLKL Pulse duration MTCLK low 14 140 ns 4 Transition time 3 3 ns 1 T 4 x Input Figure 7 60 MTCLK Timing EMAC Transmit MII and GMII Operation 208 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 77 Switching Characteristics Over Recommended Operating Conditions for GMTCLK GMII Operation see Figure 7 61 720 850 1000 1000 NO 1200 UNIT 1000 Mbps MIN MAX 1 c GMTCLK Cy
7. 190 7 13 1 McBSP Device Specific Information 191 7 13 1 1 McBSP Peripheral Register Description s 191 7 13 2 McBSP Electrical Data TImihg uuu UU akasqan re nna qawa e a 299 7 13 2 1 Multichannel Buffered Serial Port MCBSP Timing 193 Ethernet EMAC D 200 7 14 4 EMAC Device Specific Information 201 7 14 2 Peripheral Register Description s 204 7 14 3 Electrical Data Timing sa u nie onere ron nu sami 208 7 14 31 EMAC and GMII Electrical Data Timing 208 7 14 3 2 RMII Electrical Data Timing 211 7 14 8 3 RGMII Electrical 0 213 7 14 4 Management Data Input Output MDIO 216 7 14 4 1 MDIO Device Specific Information 216 7 14 4 2 MDIO Peripheral Register Description s
8. Bit Field Value Description 31 8 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 7 Reserved Reserved Writes to this register must keep this bit as 0 6 Reserved Reserved The reserved bit location is always read as 1 A value written to this field has no effect 5 4 Reserved Reserved Writes to this register must keep this bit as 0 3 PLLRST PLL reset bit 0 PLL reset is released 1 PLL reset is asserted 2 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 1 PLLPWRDN PLL power down mode select bit 0 PLL is operational 1 PLL is placed in power down state i e all analog circuitry in the PLL is turned off 0 PLLEN PLL enable bit 0 Bypass mode Divider PREDIV and PLL are bypassed All the system clocks SYSCLKn are divided down directly from input reference clock PLL mode Divider PREDIV and PLL are not bypassed PLL output path is enabled All the system clocks SYSCLKn are divided down from PLL output 140 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 7 3 2 PLL Multiplier Control Register The PLL multiplier control register PLLM is shown in Figure 7 12 and described in Table 7 20 The PLL
9. 720 850 A 1000 1000 NO 1200 UNIT MASTER SLAVE MIN MAX MIN MAX tsu DRV CKXH Setup time DR valid before CLKX high 12 2 18P ns th CKXH DRV Hold time DR valid after CLKX high 4 5 36P ns 1 2 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 Table 7 67 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave CLKSTP 10b CLKXP 12 see Figure 7 56 720 850 A 1000 1000 NO PARAMETER 1200 UNIT MASTER O SLAVE MIN MAX MIN MAX 1 thiCKXH FXL Hold time FSX low after CLKX high T 2 T 3 ns 2 la EXL CKXL Delay time FSX low to CLKX low H 2 H 3 ns 3 ta CKXL DXV Delay time CLKX low to DX valid 2 4 18P 2 8 17 ns Disable time DX high impedance following 6 last data bit from CLKX high nece H 3 ns Disable time DX high impedance following 7 ldis FXH DXHZ last data bit from FSX high 6R aa TBR FAE SES 8 la FXL DXV Delay time FSX low to DX valid 12P 2 24P 17 ns P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 3 S Sample rate generator input clock 6P if CLKSM 1 P
10. HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 2130 02D1 OFFC Reserved Implementation Registers 02D1 1000 02D1 1FFC Reserved 02D1 2000 RIO SP IP DISCOVERY TIMER Port IP Discovery Timer in 4x mode 02D1 2004 RIO SP IP MODE Port IP Mode CSR 02D1 2008 RIO IP PRESCAL Port IP Prescaler Register 02D1 200C Reserved 02D1 2010 RIO SP IP PW IN CAPTO Port Write In Capture CSR Register 0 02D1 2014 RIO SP IP PW IN CAPT1 Port Write In Capture CSR Register 1 02D1 2018 RIO SP IP PW IN CAPT2 Port Write In Capture CSR Register 2 02D1 201C RIO SP IP PW IN Port Write In Capture CSR Register 3 02D1 2020 02D1 3FFC Reserved 02D1 4000 RIO SPO RST OPT Port 0 Reset Option CSR 02D1 4004 RIO SPO CTL INDEP Port 0 Control Independent Register 02D1 4008 RIO SPO SILENCE TIMER Port 0 Silence Timer Register 02D1 400C RIO SPO MULT EVNT CS Port 0 Multicast Event Control Symbol Request Register 02D1 4010 Reserved 02D1 4014 RIO SPO CS TX Port 0 Control Symbol Transmit Register 02D1 4018 02D1 40FC Reserved 02D1 4100 RIO SP1 RST OPT Port 1 Reset Option CSR 02D1 4104 RIO SP1 CTL INDEP Port 1 Control Independent Register 02D1 4108 RIO SP1 SILENCE TIMER Port 1 Silence Timer Register 02D1 410C RIO SP1 MULT EVNT CS Port 1 Multicast Event Control Symbol Request Register 02D1 4110 Reserved 02D1 4114 RIO SP1 CS TX Port 1 Control Symbol Transmit Register 02D1 4118 02D1 41FC Reserved 02D1 4200 RIO SP2 RST OPT Port 2
11. 720 850 A 1000 1000 NO PARAMETER 1200 UNIT 100 10 Mbps MIN MAX 1 ta MTCLKH MTXD Delay time MTCLK high to transmit selected signals valid 5 25 ns 1 For Transmit selected signals include MTXD 3 0 and MTXEN For Transmit selected signals include GMTXD 7 0 and MTXEN i 1 1 MTCLK Input A 502 MTXD7 MTXD4 GMII only _ T YAY MTXD3 MTXDO 90000 Outputs Figure 7 63 EMAC Transmit Interface Timing MII GMII Operation Table 7 80 Switching Characteristics Over Recommended Operating Conditions for EMAC GMII Transmit 1000 Mbit s see Figure 7 64 720 850 A 1000 1000 NO PARAMETER 1200 UNIT 1000 Mbps MIN MAX 1 Delay time GMTCLK high to transmit selected signals valid 0 5 5 ns 1 For GMIl Transmit selected signals include GMTXD 7 0 and MTXEN t 1 GMTCLK Output 22 27 MTXD7 MTXDO OOOO CXXXXXXXXX MTXEN Outputs Figure 7 64 Interface Timing GMII Operation 210 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 14 3 2 EMAC RMII Electrical Data Timing pin is used to source a clock to the EMAC w
12. HEX ADDRESS RANGE ACRONYM REGISTER NAME 7000 0000 MIDR Module ID and Revision Register 7000 0004 STAT Status Register 7000 0008 Reserved 7000 000C 7000 001G Reserved 7000 0020 BURST PRIO Burst Priority Register 7000 0024 7000 004C Reserved 7000 0050 7000 007C Reserved 7000 0080 CE2CFG EMIFA CE2 Configuration Register 7000 0084 CE3CFG EMIFA CE3 Configuration Register 7000 0088 CE4CFG EMIFA CE4 Configuration Register 7000 008 CE5CFG EMIFA CE5 Configuration Register 7000 0090 7000 009 Reserved 7000 00A0 AWCG EMIFA Async Wait Cycle Configuration Register 7000 00A4 7000 00BC Reserved 7000 00C0 INTRAW EMIFA Interrupt RAW Register 7000 00C4 INTMSK EMIFA Interrupt Masked Register 7000 00C8 INTMSKSET EMIFA Interrupt Mask Set Register 7000 00CG INTMSKCLR EMIFA Interrupt Mask Clear Register 7000 00D0 7000 00DG Reserved 7000 00E0 77FF FFFF Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 163 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 10 3 EMIFA Electrical Data Timing Table 7 42 Timing Requirements for for 1 2 see Figure 7 31 720 850 NO A 1000 1000 UNIT 1200 MIN MAX 1 c EKI Cycle time AECLKIN 6 40 ns 2 tw EKIH Pulse duration AECLKIN high 2 7 ns 3 tw EKIL Pulse durati
13. or 0 V 20 20 CVpp 1 25 V CPU frequency 1200 MHz Us CVpp 1 25 V 6 CPU frequency 1000 MHz Dur il Pcpp Core supply power 9 CVpp 1 2 V 130 CPU frequency 850 MHz CVpp 1 2 V CPU frequency 720 MHz TB DVppss 3 3 V DVppis DVppr 1 8 V PLLV1 2 11 0 54 w AVpiio 1 8 V CPU frequency 1200 MHz DVppss 3 3 V DVppis DVppr 1 8 V PLLV1 PLLV2 AVptui 0 54 w 2 1 8 V 6 CPU frequency 1000 MHz Pppp IO supply power 9 DVppss 3 3 V DVppis DVppr 1 8 V PLLV1 PLLV2 0 53 Ww AVpiio 1 8 V CPU frequency 850 MHz DVppss 3 3 V DVppts8 DVppr 1 8 V PLLV1 PLLV2 0 52 w 1 8 V CPU frequency 720 MHz Input capacitance 10 pF Co Output capacitance 10 pF 5 loz applies to output only pins indicating off state hi Z output leakage current Assumes the following conditions 60 CPU utilization DDR2 at 50 utilization 250 MHz 50 writes 32 bits 50 bit switching two 2 MHz McBSPs at 100 utilization 50 switching two 75 MHz Timers at 100 utilization device configured for 2 mode with pull up resistors on HPI pins room temperature 25 C The actual current draw is highly application dependent For more details on core and I O activity see the 7MS320C6455 54 Power Consumption Summary application report literature number SPRAAES 104 Device Operating Conditions Submit Documentat
14. 3 1 Applies to both descriptor and data accesses by the SRIO peripheral 43 Configuration Switch Fabric Figure 4 2 shows the connection between the C64x Megamodule and the configuration switched central resource SCR The configuration SCR is mainly used by the C64x Megamodule to access peripheral registers The data SCR also has a connection to the configuration SCR which allows masters to access most peripheral registers The only registers not accessible by the data SCR through the configuration SCR are the device configuration registers and the PLL1 and PLL2 controller registers these can be accessed only by the C64x Megamodule The configuration SCR uses 32 bit configuration buses running at SYSCLK2 frequency SYSCLK2 is supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency divided by 3 84 System Interconnect Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com CFG SCR 32 bit SYSCLK2 32 SYSCLK2 Megamodule 32 SYSCLK2 Data SCR a Configuration Bus Data Bus A Only accessible by the C64x Megamodule B All clocks in this figure are generated by the PLL1 controller 32 SYSCLK2 32 SYSCLK3 SYSCLK2 32 SYSCLK2 32 SYSCLK2 n lt r A n lt o r A e e lt an r A SM320C6455 EP FIXED POINT
15. 2 HD 15 0 _ _ac gt ax 7 36 l 6 m HRDY B HSTROBE refers to the following logical operation HCS HDS1 and 052 NOT HDS1 XOR HDS2 OR HCS Depending the type of write read operation HPID without auto incrementing HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 45 16 Read Timing HAS Used Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 183 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 HC N N HAS Mew X X X X j e HRIW um a s ew n AX Wa o l pi 16 46 16 gt 15 e 15 37 13 gt 4 5 37 lt 14 gt HSTROBE AC lt gt 18 gt 18 7 e 17 4 lt 38 M 34 4 5 I 35 5 e Hp _____ 2 27 X xc HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID wit
16. 4 0 1 3 HD 31 0 output S00 k 7 86 38 4 6 I 36 HRDY output 4 2 HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 C The timing twiHSTBH HSTROBE high pulse duration must be met between consecutive HPI accesses in HPI32 mode Figure 7 49 HPI32 Read Timing HAS Used Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 187 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 HAS input 16 154 t HCNTLI1 0 Y X mu 9 input 6 INSTRUMENTS www ti com HR W input m 4 13 gt HSTROBE N input 17 lt 4 18 pl HD 31 0 input Pt gt 4 38 3 5 35 P lg 5 4 A HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS B Depending on the type of write or read operation HPID without
17. 14 pin controls the HPI_WIDTH allowing the user to configure the HPI as a 16 bit or 32 bit peripheral Software handshaking via the HRDY bit of the Host Port Control Register HPIC is not supported on the C6455 An HPI boot is terminated using a DSP interrupt The DSP interrupt is registered in bit 0 channel 0 of the EDMA Event Register ER This event must be cleared by software before triggering transfers on DMA channel 0 7 12 2 HPI Peripheral Register Description s Table 7 54 HPI Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0288 0000 Reserved The CPU has read write access to the 0288 0004 PWREMU_MGMT HPI power and emulation management register PWREMU MGWMT register the Host does not have any access to this register 0288 0008 0288 0024 Reserved 0288 0028 Reserved 0288 002C Reserved The Host and the CPU have 0288 0030 HPIC HPI control register read write access to the HPIC register HPIA HPI address register The Host has read write 0288 0034 HPlAW 2 Write access to the HPIA registers HPIA HPI address register The CPU has only read 0288 0038 HPIAR 9 Read 2 access to the HPIA registers 0288 000C 028B 007F Reserved 0288 0080 028B FFFF Reserved 1 The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear acknowledge an interrupt from the host 2 There ar
18. PERAVE poevsec PSTOP Vss vss vs U T RSV15 RSV16 id Vss DVppss CVpp Vss CVpp Vss CVpp DVpp33 Vss pcenis UPON UND DVppas Vss Vss CVpp Vss CVpp Vss R GP 12 GP 13 1 E 204 5 6 7 8 9 10 11 12 13 14 5 kun cc Figure 2 2 C6455 Pin Map Bottom View Quadrant A 20 Device Overview Submit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 16 17 18 19 20 21 22 23 24 25 26 27 28 29 AJ Vss RIORX2 RIORX2 Vss RIORX1 RIORX1 AVppr Vss DVDp33 AED5 AED6 AED20 DVpps3 AJ DVppss RIORX3 RIORX3 Vss Vss RIORX0 RIORX0 DVpp33 Vss AED14 AED2 AED18 Vss AH AG Vss DVpp33 RIOTX2 RIOTX2 Vss RIOTX1 RIOTX1 DVpp33 Vss AED3 SCL AED9 AED16 AED30 AG AF DVpp33 RIOTX3 RIOTX3 Vss AVDDT Vss RIOTXO RIOTXO DVpp33 AED1 SDA AED10 AED15 AEDi9 AE Vss Vss AVppr Vss RSV17 Vss AVppr Vss AED7 AED12 AED4 AED13 AE AD AVpDA Vss DVpp33 Vss DVppR Vss DVpp33 Vss DVpp33 AED0 AED11 AED8 AED22 AED21 AD AC Vss AVDDA Vss DVpp33 Vss DVpp33 Vss DVpp33 Vss AED24 AED26 AED28 Vss DVppa AB Vss DVppss AED25 AED27 AED29 ASWE AA DVpp33 Vss ABE1 ABE0 AED31 ABE2 ABE3 AA AAOE Y V
19. 52 Device Overview Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION U15 U17 U19 U24 V2 V6 V12 V14 V16 V18 V23 W7 W11 W13 W15 W17 W19 W24 Y6 Y23 AA2 AA7 AA24 AB6 AB23 AC7 AC8 AC10 AC12 AC14 AC16 AC18 GND Ground pins Submit Documentation Feedback Device Overview 53 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued 6 INSTRUMENTS www ti com SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION AC20 AC22 AC24 AC28 AD6 AD13 AD15 AD17 AD19 AD21 AD23 AE4 AE7 AE16 AE18 AE20 AE22 AE24 AF2 AF19 AF21 AG13 16 20 24 1 15 19 21 25 29 AJ8 AJ14 AJ16 AJ20 AJ24 GND Ground pins 54 Device Overview Submit Documentation Feedba
20. Table 7 23 PLL Controller Divider 5 Register PLLDIV5 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 Dn4EN Divider 4 enable bit 0 Divider 4 is disabled No clock output 1 Divider 4 is enabled 14 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 RATIO O 1Fh Divider ratio bits 0 1 Divide frequency by 1 th 2 Divide frequency by 2 2h 3 Divide frequency by 3 3h 4 Divide frequency by 4 4h 7h 5 to 8 Divide frequency by 5 to divide frequency by 8 8h 1Fh Reserved do not use 144 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 7 3 6 PLL Controller Command Register The PLL controller command register PLLCMD contains the command bit for GO operation PLLCMD is shown in Figure 7 16 and described in Table 7 24 31 16 Reserved R 0 15 2 1 0 Reserved Rsvd GOSET R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 7 16 PLL Controller Command Register PLLCMD Hex Address 029A 0138 Table 7 24 PLL Controller Command Register PLLCMD Fi
21. 0 SYSCLKn is gated 1 SYSCLKn is on Bit Field Value Description 31 4 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 41 SYSnON SYSCLKn on status 0 Reserved 1 Reserved The reserved bit location is always read as 1 A value written to this field has no effect Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 149 SM320C6455 EP 79 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 7 4 PLL1 Controller Input and Output Clock Electrical Data Timing Table 7 29 Timing Requirements for CLKIN1 Devices 99 see Figure 7 21 720 850 1000 1000 1200 NO PLL MODES UNIT x1 Bypass x15 x20 x25 x30 x32 MIN MAX 1 Cycle time CLKIN1 15 30 3 ns 2 tw CLKIN1H Pulse duration CLKIN1 high 0 4C ns 3 tw CLKIN1L Pulse duration CLKIN1 low 0 4C ns 4 Transition time CLKIN1 12 ns 5 L CLKIN1 Period jitter peak to peak CLKIN1 100 ps 1 The reference points for the rise and fall transitions are measured at 3 3 V Vy MAX and MIN 2 For more details on the PLL multiplier factors x1 BYPASS x 15 x20 x25 x30 x32 see Section 7 7 1 2 PLL1 Controller Operating Modes 3 C CLKIN1 cycle time in ns For example when CLKIN1 frequency is 50 MHz use C 20 ns The
22. 4 6 INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 71 Ethernet MAC EMAC Control Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0158 RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register 02C8 015C RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register 02C8 0160 MACCONTROL MAC Control Register 02C8 0164 MACSTATUS MAC Status Register 02C8 0168 EMCONTROL Emulation Control Register 02C8 016C FIFOCONTROL FIFO Control Register Transmit and Receive 02C8 0170 MACCOMFIG MAC Configuration Register 02C8 0174 SOFTRESET Soft Reset Register 02C8 0178 02C8 01CC Reserved 02C8 01D0 MACSRCADDRLO MAC Source Address Low Bytes Register Lower 32 bits 02C8 01D4 MACSRCADDRHI MAC Source Address High Bytes Register Upper 32 bits 02C8 01D8 MACHASH1 MAC Hash Address Register 1 02C8 01DC MACHASH2 MAC Hash Address Register 2 02C8 01 0 BOFFTEST Back Off Test Register 02C8 01 4 TPACETEST Transmit Pacing Algorithm Test Register 02C8 01 8 RXPAUSE Receive Pause Timer Register 02C8 01EC TXPAUSE Transmit Pause Timer Register 02 8 01 0 02C8 01FC Reserved 02C8 0200 02C8 02FC see Table 7 72 EMAC Statistics Registers 02C8 0300 02C8 03FC Reserved 02C8 0400 02C8 04FC Reserved MAC Address Low Bytes Register used in receive address 02
23. MCBSP1 EN McBSP1 Enable MCBSP1 EN status bit Shows the status of which function is enabled on the McBSP1 GPIO muxed pins GPIO pin functions enabled default McBSP1 pin functions enabled 13 66 PCI Frequency Selection PCI66 status bit Shows the PCI operating frequency selected at reset PCI operates at 33 MHz default PCI operates at 66 MHz 12 Reserved Reserved Read only writes have no effect 11 PCI EEAI PCI I2C EEPROM Auto Initialization PCI EEAI status bit Shows whether the PCI auto initialization via external 2 EEPROM is enabled disabled PCI auto initialization through external 2 EEPROM is disabled the PCI peripheral uses the specified PCI default values default PCI auto initialization through external 2 EEPROM is enabled the PCI peripheral is configured through external 2 EEPROM provided the PCI peripheral pin is enabled PCI EN 1 10 9 MACSEL 1 0 00 01 10 11 EMAC Interface Select MACSEL 1 0 status bits Shows which interface mode has been selected 10 100 EMAC MDIO with MII Interface default 10 100 EMAC MDIO with RMII Interface 10 100 1000 EMAC MDIO with GMII Interface 10 100 1000 EMAC MDIO with RGMII Mode Interface RGMII interface requires a 1 8 V or 1 5 V I O supply Reserved Reserved Read only writes have no effect UTOPIA EN UTOPIA enable UTOPIA EN status bit Shows the status of which function is enab
24. Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 233 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 20 Serial RapidlO SRIO Port The SRIO port on the C6455 device is a high performance low pin count interconnect aimed for embedded markets The use of the Rapid interconnect in baseband board design can create a homogeneous interconnect environment providing even more connectivity and control among the components Rapid I O is based on the memory and device addressing concepts of processor buses where the transaction processing is managed completely by hardware This enables the Rapid interconnect to lower the system cost by providing lower latency reduced overhead of packet data processing and higher system bandwidth all of which are key for wireless interfaces The Rapid I O interconnect offers very low pin count interfaces with scalable system bandwidth based on 10 Gigabit per second Gbps bidirectional links The PHY part of the RIO consists of the physical layer and includes the input and output buffers each serial link consists of a differential pair the 8 bit 10 bit encoder decoder the PLL clock recovery and the parallel to serial serial to parallel converters The RapidlO interface should be designed to operate at a data rate of 3125 Gbps per differential pair This equals 12 5 raw GBaud s fo
25. 0184 103F Reserved 0184 1040 L1DCPUARBD 110 CPU Arbitration Control Register 0184 1044 L1DIDMAARBD 110 IDMA Arbitration Control Register 0184 1048 L1DSDMAARBD L1D Slave DMA Arbitration Control Register 0184 104C L1DUCARBD 110 User Coherence Arbitration Control Register Table 5 11 Device Configuration Registers Chip Level Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 02A8 0000 DEVSTAT Device Status Register o RI UT 02 8 0004 PRI ALLOC Priority Allocation Register Sets priority for Master peripherals 02A8 0008 JTAGID BE BSDL Identification Provides 32 bit JTAG ID of 02A8 000C 02AB FFFF 5 Reserved 02AC 0000 Reserved 02AC 0004 PERLOCK Peripheral Lock Register 02 0008 Configuration Register 0 02 000 Reserved 02 0010 Reserved 02 0014 PERSTATO Peripheral Status Register 0 02AC 0018 PERSTAT1 Peripheral Status Register 1 02 001C 02 001 Reserved 02AC 0020 EMACCFG EMAC Configuration Register 02 0024 02 002B Reserved 02AC 002G PERCFG1 Peripheral Configuration Register 1 02AC 0030 02AC 0053 Reserved 02AC 0054 EMUBUFPD Emulator Buffer Powerdown Register 02AC 0058 Reserved 100 C64x Megamodule Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 Device Operating Conditions 6 1 Absolut
26. 02 0 013B Reserved 02C0 013G PCILGINTMIR PCI Max Latency Min Grant Interrupt Pin Interrupt Line Mirror Register 02 0 0140 02C0 017F Reserved 02 0 0180 PCISLVCNTL PCI Slave Control Register 02C0 0184 02C0 01BF Reserved 02 0 01CO PCIBAROTRL PCI Slave Base Address 0 Translation Register 02 0 01C4 PCIBAR1TRL PCI Slave Base Address 1 Translation Register 02 0 01C8 PCIBAR2TRL PCI Slave Base Address 2 Translation Register 02C0 01CC PCIBARSTRL PCI Slave Base Address 3 Translation Register 02 0 01D0 PCIBARATRL PCI Slave Base Address 4 Translation Register 02 0 0104 PCIBAR5TRL PCI Slave Base Address 5 Translation Register 02 0 01D8 02C0 01DF Reserved 02 0 01E0 PCIBAROMIR PCI Base Address Register 0 Mirror Register 02 0 01 4 PCIBAR1MIR PCI Base Address Register 1 Mirror Register 02 0 01 8 PCIBAR2MIR PCI Base Address Register 2 Mirror Register 02 0 01EC PCIBARS3MIR PCI Base Address Register 3 Mirror Register 02 0 01F0 PCIBARAMIR PCI Base Address Register 4 Mirror Register 02 0 01F4 5 PCI Base Address Register 5 Mirror Register 02C0 01F8 02C0 02FF Reserved 02C0 0300 PCIMCFGDAT PCI Master Configuration IO Access Data Register 02C0 0304 PCIMCFGADR PCI Master Configuration IO Access Address Register Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 225 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2
27. 02C8 067C RX7CP Receive Channel 7 Completion Pointer Interrupt Acknowledge Register 02C8 0680 02C8 06FC Reserved 02C8 0700 02C8 077C Reserved was State RAM Test Access Registers Processor Read and Write Access to Head Descriptor Pointers and Interrupt Acknowledge Registers 02C8 0780 02C8 OFFF Reserved Table 7 72 EMAC Statistics Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0200 RXGOODFRAMES Good Receive Frames Register Broadcast Receive Frames Register 0208 0204 BERBERS Innes Total number of good broadcast frames received Multicast Receive Frames Register 0208 0208 HAMGASIFRAMES Total number of good multicast frames received 02C8 020C RXPAUSEFRAMES Pause Receive Frames Register Receive CRC Errors Register Total number of frames received with 02C8 0210 RXCRCERRORS CRC errors Receive Alignment Code Errors Register 0208 0214 RXALIGNCODEERRORS Total number of frames received with alignment code errors Receive Oversized Frames Register 0268 0218 RXOVERSIZED Total number of oversized frames received Receive Jabber Frames Register 02C8 021C MAJABBER Total number of jabber frames received Receive Undersized Frames Register USERS RXUNDERSIZED Total number of undersized frames received 02C8 0224 RXFRAGMENTS Receive Frame Fragments Register 02C8 0228 RXFILTERED Filtered Receive Frames Register 02C8 022G RXQOSFILTERED Received QOS Filtere
28. 1 CPU clock frequency S Sample rate generator input clock P clks if CLKSM 0 P clks period T CLKX period 1 CLKGDV S H CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even H CLKGDV 1 2 S if CLKGDV is odd L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd 4 FSRP FSXP 1 As SPI Master FSX is inverted to provide active low slave enable output As a Slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master McBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP 5 FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock CLKX CLKX 4 E NEN LS 24 le FSX gt k7 6 8 gt F 3 DX _ Bio i C Bit n 1 X n2 X n3 X n4 X 4 b 5 DR EBito C Bit n X n2 X n3 X n4 X Figure 7 56 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 1 198 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 68 Timing Requirements for McBSP as SPI Master or Slave CLKSTP 11b CLKXP 10 see Figure 7 57 720 850 A 1000 1000
29. 17 2 4 2 2nd Level Bootloaders 19 2 5 II pcc 20 2 5 1 Pim MaD 21 Y 20 2 6 Signal Groups D scription eL 24 2 7 Terminal FUNCIONS iesen ua dude wa aqsu 30 2 8 Developments e s vd wed aw wawa P 53 2 8 1 Development Sasu saan Quos ing ada 55 282 Device elio Mm 55 2 8 2 1 Device and Development Support Tool Nomenclature 55 28 22 Documentation Support soie repro pen vies tee eine IA Rn 56 D vice Gonfig rati nm uu uu ETT 59 3 1 Device Gonfiguration at Device Reset y u uuu u Mes ROUES 59 3 2 Peripheral Configuration at Device Reset U 61 3 3 Peripheral Selection After Device Reset 63 3 4 Device State Control Registers re QN EN ERE ER 65 3 4 1
30. 2 module provides an interface between a C64x DSP and other devices compliant with Philips Semiconductors Inter IC bus bus specification version 2 1 and connected by way of an I C bus External components attached to this 2 wire serial bus transmit receive up to 8 bit data to from the DSP through the 2 module 7 11 1 2 Device Specific Information The C6455 device includes an 2 peripheral module 2 NOTE when using the 2 module ensure there are external pullup resistors on the SDA and SCL pins 2 modules on the C6455 be used by the DSP to control local peripherals ICs DACs ADCs etc or may be used to communicate with other controllers in a system or to implement a user interface The 2 port supports e Compatible with Philips 2 Specification Revision 2 1 January 2000 Fast Mode up to 400 Kbps no fail safe I O buffers e Noise Filter to remove noise 50 ns or less e 7 and 10 Bit Device Addressing Modes e Multi Master Transmit Receive and Slave Transmit Receive Functionality e Events DMA Interrupt or Polling e Slew Rate Limited Open Drain Output Buffers Figure 7 41 is a block diagram of the 2 module Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 173 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 174 2 Module SCL 12C Clock X Noise Fil
31. A8 A11 A20 A23 B1 B29 C5 D1 E5 E7 E19 E25 E29 F4 F6 F8 F10 F12 F14 F16 GND Ground pins 50 Device Overview Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL NAME NO F20 F22 F24 G1 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 H6 H24 Vss H29 GND Ground pins J7 J23 K2 K6 K24 L7 L11 L13 L15 L17 L19 L23 M6 M12 M14 TYPE IPD IPU DESCRIPTION Submit Documentation Feedback Device Overview 51 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued 6 INSTRUMENTS www ti com SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION M16 M18 M24 M26 M29 N2 N13 N15 N17 N19 N23 P7 P12 P14 P16 P18 P29 R2 R7 R11 R13 R15 R17 R19 R24 T6 T12 T14 T16 T18 T23 U7 U11 U13 GND Ground pins
32. Controls EMIFA CES Range DF00 0000 DFFF FFFF 0184 8380 MAR224 Controls DDR2 Range E000 0000 EOFF FFFF 0184 8384 MAR225 Controls DDR2 Range E100 0000 E1FF FFFF 0184 8388 MAR226 Controls DDR2 Range E200 0000 E2FF FFFF 0184 838C MAR227 Controls DDR2 Range E300 0000 E3FF FFFF 0184 8390 MAR228 Controls DDR2 Range E400 0000 E4FF FFFF 0184 8394 MAR229 Controls DDR2 Range E500 0000 FFFF 0184 8398 MAR230 Controls DDR2 Range E600 0000 E6FF FFFF 0184 839C MAR231 Controls DDR2 Range E700 0000 E7FF FFFF 0184 83A0 MAR232 Controls DDR2 Range E800 0000 E8FF FFFF 0184 83A4 MAR233 Controls DDR2 Range E900 0000 E9FF FFFF 0184 83A8 MAR234 Controls DDR2 Range EA00 0000 EAFF FFFF 0184 83AC MAR235 Controls DDR2 Range EBOO 0000 EBFF FFFF 0184 83B0 MAR236 Controls DDR2 Range EC00 0000 ECFF FFFF 0184 83B4 MAR237 Controls DDR2 Range ED00 0000 EDFF FFFF 0184 83B8 MAR238 Controls DDR2 CEO Range 00 0000 EEFF FFFF 0184 83BC MAR239 Controls DDR2 Range EF00 0000 EFFF FFFF 0184 83 0 0184 83FC 4 Reserved Table 5 9 Megamodule L1 L2 Memory Protection Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 A000 L2MPFAR L2 memory protection fault address register 0184 A004 L2MPFSR L2 memory protection fault status register 0184 A008 L2MPFC
33. Internal pulldown Internal pullup For most systems a 1 kQ resistor be used to oppose the IPU IPD For more detailed information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see Section 3 7 Pullup Pulldown Resistors Submit Documentation Feedback Device Configuration 59 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 3 1 C6455 Device Configuration Pins AEA 19 0 ABA 1 0 and PCI EN continued CONFIGURATION IPD PIN NO Ipu FUNCTIONAL DESCRIPTION HPI peripheral bus width select HPI WIDTH 0 HPI operates 16 mode default HPI bus is 16 bits wide HD 15 0 pins are used and the remaining HD 31 16 AEA14 R25 IPD pins are reserved pins in the Hi Z state 1 HPI operates in HPI32 mode HPI bus is 32 bits wide HD 31 0 pins are used Applies only when HPI function of HPI PCI multiplexed pins is selected PCI EN pin 0 Device Endian mode LENDIAN AEA13 R27 IPU 0 System operates in Big Endian mode 1 System operates in Little Endian mode default UTOPIA pin function enable bit UTOPIA EN This pin selects the function of the UTOPIA EMAC and UTOPIA MDIO multiplexed pins 0 UTOPIA pin function disabled EMAC and MDIO pin function enabled default This means all multiplexed UTOPIA EMAC and UTOPIA MDIO pins function as AEA12 R28
34. Output of event combiner 1 in interrupt controller for events 32 63 20 EVT2 Output of event combiner 2 in interrupt controller for events 64 95 30 EVT3 e of event combiner 3 in interrupt controller for events 96 4 8 Besarved 2 These system events not connected therefore EMU interrupt for g0 EMU_DTDMA 1 Host scan access 2 DTDMA transfer complete AET interrupt 10 None This system event is not connected and therefore not used 110 EMU RTDXRX EMU real time data exchange RTDX receive complete 1200 EMU RTDXTX EMU RTDX transmit complete 130 IDMAO IDMA channel 0 interrupt 140 IDMA1 IDMA channel 1 interrupt 15 DSPINT HPI PCI to DSP interrupt 16 I2CINT 2 interrupt 17 MACINT Ethernet MAC interrupt 18 AEASYNCERR EMIFA error interrupt 19 Reserved This system event is connected therefore 20 INTDSTO RapidlO interrupt 0 21 INTDST1 RapidlO interrupt 1 22 INTDST4 RapidlO interrupt 4 23 Reserved P This system event is not connected and therefore not 24 EDMA3CC_GINT EDMAS channel global completion interrupt 25 31 Reserved reden These system events are not connected and therefore 32 VCP2 INT VCP2 error interrupt 33 TCP2 INT TCP2 error interrupt 34 35 22 These system events not connected and therefore 36 UINT UTOPIA interrupt 37 39 Reserved These system events connected therefore 40 RINTO McBSPO receive interrupt 1
35. 0 14 0 HPI operates as an 16 default HPI bus is 16 bits wide HD 15 0 pins are used and the remaining HD 31 16 pins are reserved pins in the Hi Z state 1 HPI operates as an 2 Device Endian mode LENDIAN AEA13 0 System operates in Big Endian mode 1 System operates in Little Endian mode default UTOPIA Enable bit UTOPIA_EN 12 UTOPIA peripheral enable functional 0 UTOPIA disabled Ethernet MAC EMAC and MDIO enable default This means all multiplexed EMAC UTOPIA and MDIO UTOPIA pins function as EMAC and MDIO Which EMAC MDIO configuration interface or the standalone RGMII is controlled by the MACSEL 1 0 bits 1 UTOPIA enabled EMAC and MDIO disabled except when the MACSEL 1 0 bits 11 then the EMAC MDIO RGMII interface is still functional This means all multiplexed EMAC UTOPIA and MDIO UTOPIA pins now function as UTOPIA And if MACSEL 1 0 11 the RGMII standalone pin functions can be used 34 Device Overview Submit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL IPD IPU DESCRIPTION NAME NO AEA10 MACSEL1 M25 EMAC MDIO interface select bits MACSEL 1 0 AEA9 MACSELO M27 If the EMAC and MDIO peripherals are enabled AEA12
36. 0 EMIFACTL Mode control for EMIFA Once this bit is set to 1 it cannot be changed to O This bit defaults to 1 if EMIFA 8 bit ROM boot is used BOOTMODE 3 0 0100b 0 Set EMIFA to disabled Set EMIFA to enabled Submit Documentation Feedback Device Configuration 69 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 3 4 4 Peripheral Status Registers Description 6 INSTRUMENTS www ti com The Peripheral Status Registers PERSTATO PERSTAT1 show the status of the C6455 peripherals 31 30 29 27 26 24 Reserved HPISTAT McBSP1STAT R 0 R 0 R 0 23 21 20 18 17 16 McBSPOSTAT I2CSTAT GPIOSTAT R 0 R 0 R 0 15 14 12 11 9 8 GPIOSTAT TIMER1STAT TIMEROSTAT EMACSTAT R 0 R 0 R 0 R 0 1 6 5 3 2 0 EMACSTAT VCPSTAT TCPSTAT R 0 R 0 R 0 LEGEND R Read only n value after reset Figure 3 6 Peripheral Status Register 0 PERSTATO 0x02AC 0014 Table 3 9 Peripheral Status Register 0 PERSTATO Field Descriptions Bit Field Value Description 31 30 Reserved Reserved 29 27 HPISTAT HPI status 000 is the disabled state 001 HPI is in the enabled state 011 HPI is in the static powerdown state 101 HPI is in the enable in progress state Others Reserved 26 24 McBSP1STAT McBSP1 status 000 McBSP1 is in the disabled state 001 McBSP1 is
37. 1 168 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 READ latency 2 AEcLKOUT X N f A N JO A Ls UN _ 1 1 ACEx i 4 2 ABE 7O 7 BEI X BE X X BE 4 k 5 AEA 19 0 ABA 1 0 _____X_EA1 X EA2 X EAS X EAM 0 AED 63 0 C QI X Q X Q X Q g pr 8 ASADS ASRE B 4 7 4 k 9 KS 9 AAOE ASOE B N AAWE ASWEB A following parameters are programmable via the EMIFA Chip Select n Configuration Register CESECn Read latency R_LTNCY 1 2 or 3 cycle read latency Write latency W_LTNCY 0 1 2 or 3 cycle write latency ACEx assertion length EXT For standard SBSRAM or ZBT SRAM interface ACEx goes inactive after the final command has been issued CE_EXT 0 For synchronous FIFO interface ACEx is active when ASOE is active CE_EXT 1 Function of ASADS ASRE R_ENABLE For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles R_ENABLE 0 For FIFO interface ASADS ASRE acts as SRE with NO deselect cycles R_ENABLE 1 In this figure R LTNCY 2 CE EXT 0 R ENABLE 0 and SSEL 1 AAOE ASOE and AAWE ASWE operate as ASOE ASWE respectively during programmable synchronous interf
38. 101 is in the enable in progress state Others Reserved 8 6 EMACSTAT EMAC MDIO status 000 EMAC MDIO is the disabled state 001 EMAC MDIO is in the enabled state 011 EMAC MDIO is in the static powerdown state 101 EMAC MDIO is in the enable in progress state Others Reserved 5 3 VCPSTAT VCP status 000 VCP is in the disabled state 001 VCP is in the enabled state 011 VCP is in the static powerdown state 101 VCP is in the enable in progress state Others Reserved 2 0 TCPSTAT TCP status 000 TCP is in the disabled state 001 TCP is in the enabled state 011 TCP is in the static powerdown state 101 TCP is in the enable in progress state Others Reserved Submit Documentation Feedback Device Configuration 71 SM320C6455 EP R3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 31 16 Reserved R 0 15 6 5 3 2 0 Reserved UTOPIASTAT PCISTAT R 0 R 0 R 0 LEGEND R Read only n value after reset Figure 3 7 Peripheral Status Register 1 PERSTAT1 0x02AC 0018 Table 3 10 Peripheral Status Register 1 PERSTAT1 Field Descriptions Bit Field Value Description 31 6 Reserved Reserved 5 3 UTOPIASTAT UTOPIA status 000 UTOPIA is in the disabled state 001 UTOPIA is in the enabled state 011 UTOPIA is in the static powerdown state 101 UTOPIA is in the enable in progress state Others Reserved
39. 2 0 PCISTAT PCI status 000 PCl is in the disabled state 001 PCI is in the enabled state 011 PCI is in the static powerdown state 101 PCI is in the enable in progress state Others Reserved 72 Device Configuration Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 3 4 5 EMAC Configuration Register EMACCFG Description SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 The EMAC Configuration Register EMACCFG is used to assert deassert the reset of the Reduced Media Independent Interface RMII logic of the EMAC For more details on how to use this register see Section 7 14 Ethernet MAC EMAC 31 24 Reserved R W 0 23 19 18 17 16 Reserved RMII_RST Reserved R W 0001b R W 1 R W 0 15 0 Reserved R W 0 LEGEND R W Read Write R Read only n value after reset Figure 3 8 EMAC Configuration Register EMACCFG 0x02AC 0020 Table 3 11 EMAC Configuration Register EMACCFG Field Descriptions Bit Field Value Description 31 19 Reserved Reserved Writes to this register must keep the default values of these bits 18 RMII RST RMII reset bit This bit is used to reset the RMII logic of the EMAC 0 RMII logic reset is released 1 RMII logic reset is asserted 17 0 Reserved Reserved Writes to this register must keep this bit as 0 Submit Documentat
40. 7 18 1 PCI Device Specific Information U 223 7 18 2 PCI Peripheral Register Description s U 224 7 18 3 PCI Electrical 0 nnne nennen hene nnne nnns nennen 229 7 19 wc EE 230 7 19 1 UTOPIA Device Specific Information 230 7 19 2 UTOPIA Peripheral Register Description s 230 7 19 9 UTOPIA Electrical Data Timihg tetra a V SS Ee 231 7 00 uuu iR ire sa DUE Dex oe awe ten 234 7 20 1 Serial RapidlO Device Specific Information 234 7 20 2 Serial RapidIO Peripheral Register Description s 234 7 20 3 Serial RapidIO Electrical Data Timing 244 7 21 General Purpose Input Output e aai a a 246 721 1 GPIO Device Specific InformaliOn eiue retineri a
41. AECLKIN AECLKOUT ASWE AAWE AARDY AR W AAOE ASOE ASADS ASRE AHOLD AHOLDA ABUSREQ DDR2CLKOUT DDR2CLKOUT DSDCKE DSDCAS DSDRAS DSDWE DSDDOQS 3 0 DSDDQGS 3 0 DSDDQGATE 0 DSDDQGATE 1 DSDDQGATE 2 DSDDQGATE 3 DEODT 1 0 DBA 2 0 Figure 2 8 EMIFA DDR2 Memory Controller Peripheral Signals Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 HPI A HD 15 0 AD 15 0 Host Port Interface HD 31 16 AD 31 16 HAS PPAR HCNTLO P P HR W PCBE2 HONTLI PDEVSEL _ Register Select HCS PPERR Control HDS1 PSERR HDS2 PCBE1 Half Word HRDY PIRDY HHWIL PCLK HPI16 ONLY Select HINT PFRAME McBSPO CLKX1 GP 3 CLKXO FSX1 GP 11 FSX0 DX1 GP 9 DX0 CLKR1 GP 0 CLKR0 FSR1 GP 10 FSR0 DR1 GP 8 DR0 CLKS SHARED Multichannel Buffered Serial Ports B SCL SDA 12C A These HPI pins are muxed with the PCI peripheral By default these pins function as HPI When the HPI is enabled the number of HPI pins used depends on the HPI configuration 116 or 2 For more details on these muxed pins see the Device Configuration section of this document B These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins For more details see the Device Configuration section of this document Figure 2 9 HPI McBSP I2C Perip
42. AJ23 A1 23 1 8 V or 1 5 V I O supply voltage for the RGMII function of the EMAC D2 NOTE If the RGMII mode of the EMAC is not used the DVppis VREFHSTL DV D5 S RSV13 and RSV14 pins can be connected to directly ground Vss to save DDIS power However connecting these pins directly to ground prevents F5 boundary scan from functioning on the RGMII pins of the EMAC To preserve G6 boundary scan functionality on the RGMII pins see Section 7 3 4 H7 B8 B11 B20 B23 E10 E12 E22 E24 F7 F11 F13 F15 F17 5 1 8 V I O supply voltage DDR2 Memory Controller F19 F23 G8 G10 G12 G14 G16 G18 G20 G22 G24 Submit Documentation Feedback Device Overview 47 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued 6 INSTRUMENTS www ti com SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION A29 E26 E28 G2 H23 H28 46 J24 K1 K7 K23 L24 M7 M23 M28 N24 P6 P28 R1 R6 R23 DVppss T7 T24 U23 V1 V7 V24 W23 Y7 Y24 AAI AA6 AA23 AB7 AB24 AC6 AC9 AC11 AC13 AC19 AC21 AC23 AC29 3 3 V I O supply voltage 48 Device Overview Submit Docu
43. All memory with the exceptions previously described may be written to and read by the host This allows for the host to verify what it sends to the DSP if required After the CPU is out of the stalled state the CPU needs to clear the DSPINT otherwise no more DSPINTs can be received As previously mentioned for the C6455 device the Host Port Interface HPI and the Peripheral Component Interconnect PCI interface can be used for host boot To use the HPI for host boot the PCI EN pin 29 must be low default enabling the HPI peripheral and BOOTMODE 3 0 must be set to 0001b at device reset Conversely to use the PCI interface for host boot the PCI_EN pin Y29 must be high enabling the PCI peripheral and 3 0 must be set to 0111b at device reset For the HPI host boot the DSP interrupt can be generated through the use of the DSPINT bit in the HPI Control HPIC register For the HPI host boot the CPU is actually held in reset until a DSP interrupt is generated by the host The DSP interrupt can be generated through the use of the DSPINT bit in the HPI Control HPIC register Because the CPU is held in reset during HPI host boot it does not respond to emulation Submit Documentation Feedback Device Overview 17 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 software such as Code Composer Studio For the PCI host boot the CPU
44. CLKGDV S H CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even H CLKGDV 1 2 S if CLKGDV is odd L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd 4 FSRP FSXP 1 As a SPI Master FSX is inverted to provide active low slave enable output As a Slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master McBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP 5 FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock CLKX CLKX N f 4 FSX p Submit Documentation Feedback WEE 4 5 DR Bito Bin n2 X m3 X 4 Xj Figure 7 57 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 1 C64x Peripheral Information and Electrical Specifications 6 F 74 83 DX Bio Bitn 1 X 2 X n3 X n4 X 199 SM320C6455 EP 9 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 14 Ethernet MAC EMAC 200 www ti com The Ethernet Media Access Controller EMAC module provides an efficient interface between the C6455 DSP core processor and the networked community The EMAC supports 10Base T 10 Mbits second Mbps and 100BaseTX 100 Mbps in either half or full duplex mode and 1000BaseT 1000 Mbps
45. NO 1200 UNIT MASTER SLAVE MIN MAX MIN MAX tsu DRV CKXH Setup time DR valid before CLKX high 12 2 18P ns th CKXH DRV Hold time DR valid after CLKX high 4 5 36P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 Table 7 69 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave CLKSTP 11b CLKXP 1 see Figure 7 57 720 850 A 1000 1000 NO PARAMETER 1200 UNIT MASTER SLAVE MIN MAX MIN MAX 1 thiCKXH FXL Hold time FSX low after CLKX high H 2 H 3 ns 2 la EXL CKXL Delay time FSX low to CLKX low T 2 T 1 ns 3 la CKXH DXV Delay time CLKX high to DX valid 2 4 18P 2 8 17 ns Disable time DX high impedance following E 6 ldis CKXH DXHZ last data bit from CLKX high 2 4 18P 3 17 ns 7 la FXL DXV Delay time FSX low to DX valid L 2 L 4 12P 2 24P 17 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 3 S Sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P clks if CLKSM 0 P clks period T CLKX period 1
46. PLL Pre Divider Control Register PREDIV Hex Address 029A 0114 Table 7 21 PLL Pre Divider Control Register PREDIV Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 PREDEN Pre divider enable bit 0 Pre divider is disabled No clock output 1 Pre divider is enabled 14 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 RATIO O 1Fh Divider ratio bits 0 1 Divide frequency by 1 1h 2 Divide frequency by 2 2h 3 Divide frequency by 3 3h 1Fh Reserved do not use 142 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 7 3 4 PLL Controller Divider 4 Register The PLL controller divider 4 register PLLDIV4 is shown in Figure 7 14 and described in Table 7 22 Besides being used as the EMIFA internal clock SYSCLKA is also used in other parts of the system Disabling this clock will cause unpredictable system behavior Therefore the PLLDIV4 register should never be used to disable SYSCLK4 31 16 Reserved R 0 15 14 5 i 0 D4EN Reserved RATIO R W 1 R 0 R W 3 LEGEND R W Read Write R Read onl
47. Physically smaller caps are better such as 0402 but need to be evaluated from a yield manufacturing point of view Parasitic inductance limits the effectiveness of the decoupling capacitors therefore physically smaller capacitors should be used while maintaining the largest available capacitance value As with the selection of any component verification of capacitor availability over the product s production lifetime should be considered 7 3 3 Power Down Operation One of the power goals for the C6455 is to reduce power dissipation due to unused peripherals There are different ways to power down peripherals on the C6455 device Some peripherals can be statically powered down at device reset through the device configuration pins see Section 3 1 Device Configuration at Device Reset Once in a static power down state the peripheral is held in reset and its clock is turned off Peripherals cannot be enabled once they are in a static power down state To take a peripheral out of the static power down state a device reset must be executed with a different configuration pin setting After device reset all peripherals on the C6455 device are in a disabled state and must be enabled by software before being used It is possible to enable only the peripherals needed by the application while keeping the rest disabled Note that peripherals in a disabled state are held in reset with their clocks gated For more information on how to enable peripherals
48. TEXAS INSTRUMENTS SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR Data Manual JANUARY 2008 SPRS462B SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR Data Manual Literature Number SPRS462B SEPTEMBER 2007 Revised JANUARY 2008 PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters 3 TEXAS INSTRUMENTS SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Contents Feat oS u 7 1 1 ZTZ GTZ BGA Package Bottom eeeeeeeeeeeeeenaeeeaeeeeeeeeeaeeeeeeeenaeeeseneeneee 8 1 2 Descripli rikuu a u 8 1 3 Functional Block Diagram LULU nhe nme hh enne hme nnn nn nne nnn nnn nnn 10 Deyice OVERVIOW 11 2 1 Device GianracieniStiCs c 11 2 2 GPD DSP Coke 6 6 diisi 12 2 3 Memory Map Summary u t mn a ne sanisincaanininesnamainecanmdanins 15 2 4 Boot SQQUCNCE rrira e a aE EAA E E a sai Ea AZ 2 4 1 Boot Modes Supported
49. UXADDRO PTRDY P4 PCI command byte enable 3 PCBE3 I O Z PCI initialization device select PIDSEL I and PCI target ready PTRDY I O Z 40 Device Overview Submit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO UXDATA7 MTXD7 N5 UXDATA6 MTXD6 M3 UTOPIA 8 bit transmit data bus 1 0 2 default or EMAC MII 4 bit transmit data bus I O Z default or GMII 8 bit transmit data bus EMAC RMII 2 bit CXDATAS MTXDS ES transmit data bus 0 2 UXDATA4 MTXD4 L3 Using the Transmit Data Bus the UTOPIA Slave on the rising edge of the UXDATAS MTXD3 K4 O Z UXCLK transmits the 8 bit ATM cells to the Master ATM Controller DADATAAMUADE M4 When the UTOPIA peripheral is disabled UTOPIA_EN AEA12 pin 0 these UXDATA1 MTXD1 L4 pins function as EMAC pins and are controlled by the MACSEL 1 0 AEA 10 9 RMTXD1 pins to select the MII GMII RGMII EMAC interface For more details UXDATAO MTXDO see Section 3 Device Configuration RMTXDO Ml UTOPIA SLAVE ATM CONTROLLER RECEIVE INTERFACE Source clock for UTOPIA receive driven by Master ATM Controller URCLK MRCLK H1 VO Z When the UTOPIA peripheral is disabl
50. UXDATA4 UXDATAS b MRXD4 MRXD5 MTXD4 MTXD5 00 58 DD 55 RMTXD1 UXSOC UXDATA3 UXCLAV K pv Vi Vi DVI poss 85 MCOL MTXD3 GMTCLK 98 URDATA0 URCLAV UXENB J picked MRXDO ee MCRS MTXEN DVppag Vss RMRXD0 RMCRSDV RMTXEN H URCLK URDATA6 URSOC MRXDV MRXER Vss DVppis RMRXD1 RMRXER 8 Vss CLKIN2 RSV07 Vss DVpp15 Vss DVpp18 Vss DVpp18 Vss DVpp18 Vss DVppis Vss F RSVi4 RSV13 DVppismon Vss DVppts Vss Vss DED11 Vss DVppi8 Vss DVpp18 Vss DVDp18 E RGRXDO RGRXDi RGRXC RGRXD2 Vss RSV34 Vss DSDDQS1 DED10 DVppis DSDDQSO DVppis RSV18 DCEO DBA2 D Vss DVppis RGTXCTL RGTXC DVpp15 RSV35 DED14 DSDDQS1 DED9 DED7 0500050 DED3 DSDCAS DsDCKE DBA1 C RGRXD3 RGRXCTL RGTXD2 RGREFCLK Vss RSV25 DED15 DSDDOM DED8 DED6 DSDDQMO DED2 DSDRAS Vntrssm DBAO DSDDQ DDR2 B Vss RGTXD1 RGMDCLK DVppis RSV24 DED12 DVpp18 GATES DEDS DVppis DED1 DSDWE DEA 8 Dv RGTXD3 RGTXDO RGMDIO PLLV2 RSV21 DED13 v Dee DED4 DED0 AV DDR2 DEA12 DD15 SS GATE0 ss DLL1 CLKOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SM320C6455 EP Figure 2 5 C6455 Pin Map Bottom View Quadrant D Submit Documentation Feedback Device Ov
51. Whenever a different ratio is written to the PLLDIV1 register the PLLCTRL flags the change in the DCHANGE status register During the GO operation the PLL controller will only change the divide ratio SYSCLK1 if SYS1 DCHANGE is 1 The PLLDIV divider ratio change status register is shown in Figure 7 28 and described in Table 7 37 31 16 Reserved R 0 15 1 0 Reserved SYS1 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Figure 7 28 PLLDIV Divider Ratio Change Status Register DCHANGE Hex Address 029C 0144 Table 7 37 PLLDIV Divider Ratio Change Status Register DCHANGE Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 SYS1 SYSCLK1 divide ratio has been modified SYSCLK1 ratio will be modified during GO operation 0 SYSCLK1 ratio has not been modified When GOSET is set SYSCLK1 will not be affected 1 SYSCLK1 ratio has been modified When GOSET is set SYSCLK1 will change to the new ratio Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 157 SM320C6455 EP 49 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 8 3 6 SYSCLK Status Register The SYSCLK status register SYSTAT shows the status of the system clock SYSCLK1 SYSTAT is sho
52. fetching the second instruction from external memory may stall the instruction long enough such that PERCFGO register will be locked before the instruction is executed 31 LOCKVAL R W F0F0 FOFO LEGEND R W Read Write n value after reset Figure 3 3 Peripheral Lock Register PERLOCK 0x02AC 0004 Table 3 6 Peripheral Lock Register PERLOCK Field Descriptions Bit Field Value Description 31 0 LOCKVAL When programmed with 0x0F0A 0B00 allows one write to the PERCFGO register within 16 SYSCLK3 clock cycles 66 Device Configuration Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 3 4 2 Peripheral Configuration Register 0 Description The Peripheral Configuration Register PERCFGO is used to change the state of the peripherals One write is allowed to this register within 16 SYSCLKS cycles after the correct key is written to the PERLOCK register NOTE The instructions that write to the PERLOCK and PERCFGO registers must be in the same fetch packet if code is being executed from external memory If the instructions are in different fetch packets fetching the second instruction from external memory may stall the instruction long enough such that PERCFGO register will be lock
53. in full duplex mode with hardware flow control and quality of service QOS support The EMAC module conforms to the IEEE 802 3 2002 standard describing the Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Physical Layer specifications The IEEE 802 3 standard has also been adopted by ISO IEC and re designated as ISO IEC 8802 3 2000 E Deviation from this standard the EMAC module does not use the Transmit Coding Error signal MTXER Instead of driving the error pin when an underflow condition occurs on a transmitted frame the EMAC will intentionally generate an incorrect checksum by inverting the frame CRC so that the transmitted frame will be detected as an error by the network The EMAC control module is the main interface between the device core processor the MDIO module and the EMAC module The relationship between these three components is shown in Figure 7 58 The EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory plus it controls device interrupts The EMAC control module incorporates 8K bytes of internal RAM to hold EMAC buffer descriptors The relationship between these three components is shown in Figure 7 58 Interrupt Configuration Bus u Peripheral Bus nterrupt MDIO Module p EMAC Control Module EMAC MDIO EMAC Module Ethernet Bus MDIO Bus Figure 7 58 EMAC MDIO and EMAC Co
54. low DBA2 E15 O Z DBA1 D15 O Z DDR2 Memory Controller bank address control DBAO C15 O Z DDR2CLKOUT B14 O Z DDR2 Memory Controller output clock CLKIN2 frequency x 10 DDR2CLKOUT 14 O Z Negative DDR2 Memory Controller output clock CLKIN2 frequency x 10 DSDCAS D13 O Z DDR2 Memory Controller SDRAM column address strobe DSDRAS C13 O Z DDR2 Memory Controller SDRAM row address strobe DSDWE B13 O Z DDR2 Memory Controller SDRAM write enable DSDCKE D14 O Z DDR2 Memory Controller SDRAM clock enable used for self refresh mode DEODT1 A17 O Z On die termination signals to external DDR2 SDRAM These pins should not be connected to the DDR2 SDRAM DEODTO E16 O Z Note There are no on die termination resistors implemented on the C6455 DSP die DSDDQGATE3 F21 l DSDDQGATE2 E21 O Z DDR2 Memory Controller data strobe gate 3 0 For hookup of these signals please refer to the Implementing DDR2 PCB DSDDQGATE1 B9 l Layout on the TMS320C6455 application report literature number SPRAAAT DSDDQGATEO A9 O Z DSDDQM3 C23 O Z DDR2 Memory Controller byte enable controls DSDDQM2 C20 O Z e Decoded from the low order address bits The number of address bits or byte enables used depends on the width of external memory DSDDOM 1 C8 O Z e Byte write enables for most types of memory DSDDQMO C11 O Z Can be directly connected to SDRAM read and write mask signal SDQM Submit Documentation Feedback Device Overview 37 SM320C6455 EP 3 TEXAS FIX
55. see Section 7 3 4 Reserved This pin must be connected to the 1 8 V I O supply DVppig via a 200 0 resistor for proper device operation NOTE If the DDR2 Memory Controller is not used the Vagessr RSV11 and RSV12 C24 RSV12 pins can be connected directly to ground Vss to save power However connecting these pins directly to ground will prevent boundary scan from functioning on the DDR2 Memory Controller pins To preserve boundary scan functionality on the DDR2 Memory Controller pins see Section 7 3 4 44 Device Overview Submit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENT S FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE iPD IPU 2 DESCRIPTION NAME NO Reserved This pin must be connected to ground Vss via a 200 0 resistor for proper device operation NOTE If the RGMII mode of the EMAC is not used the DVppis VREFHSTL RSV13 F2 RSV13 and RSV14 pins can be connected to directly ground Vss to save power However connecting these pins directly to ground prevents boundary scan from functioning on the RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins see Section 7 3 4 Reserved This pin must be connected to the 1 5 1 8 V I O supply DVppis via a 200 resistor for prope
56. 0 ABA 1 0 and for EMIFA writes also include AR W AED 63 0 k Strobe 4 Setup 177 f Hold 1 AECLKOUT N 2 N K 2 4 _ Lar cs ACEx T Xu d __ __ k fe K 2 ABE 7 0 1 K 2 ge C ABA 1 0 3 4 AED 63 0 10 1077 AAOE ASOEA UUU 12 AAWE ASWE A AR W AARDY B DEASSERTED AAOE ASOE and AAWE ASWE operate as AAOE identified under select signals and AAWE respectively during asynchronous memory accesses B Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register AWCC Figure 7 33 Asynchronous Memory Read Timing for EMIFA 166 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Strobe 4 1 4 k Hold 1 4 AECRKOUTZ N f N f NA NA f ANA N 11 m 7 ACEx e v U 12 Y ABE 7 0 LEX Enables gt 11 AEA 19 0 TE ABA 1 0 1 k AED 63 0 Write D AAOE ASOEU E 13 4 AAWE ASWE A 38 __ 11 4 ARW AA _ 5 A AAOE ASOE and AAWE ASWE operate a
57. 0 A value written to this field has no effect 4 SYS5 Identifies when the SYSCLKS5 divide ratio has been modified 0 SYSCLKS5 ratio has not been modified When GOSET is set SYSCLK5 will not be affected SYSCLKS5 ratio has been modified When GOSET is set SYSCLK5 will change to the new ratio 3 SYS4 Identifies when the SYSCLK4 divide ratio has been modified 0 SYSCLK4 ratio has not been modified When GOSET is set SYSCLK4 will not be affected SYSCLK4 ratio has been modified When GOSET is set SYSCLK4 will change to the new ratio 2 0 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 148 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 www ti com 7 7 3 10 SYSCLK Status Register The SYSCLK status register SYSTAT shows the status of the system clocks SYSCLKn SYSTAT shown in Figure 7 20 and described in Table 7 28 is 31 16 Reserved R 0 15 8 Reserved R 0 7 5 4 3 2 1 0 Reserved SYS5ON SYS4ON SYS3ON SYS2ON Reserved R 0 R 1 R 1 R 1 R 1 R 1 LEGEND R Read only n value after reset Figure 7 20 SYSCLK Status Register SYSTAT Hex Address 029A 0150 Table 7 28 SYSCLK Status Register SYSTAT Field Descriptions
58. 0 0144 DCHMAP17 DMA Channel 17 Mapping Register 02A0 0148 DCHMAP18 DMA Channel 18 Mapping Register 02A0 014C DCHMAP19 DMA Channel 19 Mapping Register 02A0 0150 DCHMAP20 DMA Channel 20 Mapping Register 02A0 0154 DCHMAP21 DMA Channel 21 Mapping Register 02A0 0158 DCHMAP22 DMA Channel 22 Mapping Register 02A0 015C DCHMAP23 DMA Channel 23 Mapping Register 02A0 0160 DCHMAP24 DMA Channel 24 Mapping Register 02A0 0164 DCHMAP25 DMA Channel 25 Mapping Register 02A0 0168 DCHMAP26 DMA Channel 26 Mapping Register 02A0 016C DCHMAP27 DMA Channel 27 Mapping Register 02A0 0170 DCHMAP28 DMA Channel 28 Mapping Register 02A0 0174 DCHMAP29 DMA Channel 29 Mapping Register 02A0 0178 DCHMAP30 DMA Channel 30 Mapping Register 02A0 017C DCHMAP31 DMA Channel 31 Mapping Register 02A0 0180 DCHMAP32 DMA Channel 32 Mapping Register 02A0 0184 DCHMAP33 DMA Channel 33 Mapping Register 02A0 0188 DCHMAP34 DMA Channel 34 Mapping Register 02A0 018C DCHMAP35 DMA Channel 35 Mapping Register 02A0 0190 DCHMAP36 DMA Channel 36 Mapping Register 02A0 0194 DCHMAP37 DMA Channel 37 Mapping Register 02A0 0198 DCHMAP38 DMA Channel 38 Mapping Register 02A0 019C DCHMAP39 DMA Channel 39 Mapping Register 02A0 01A0 DCHMAP40 DMA Channel 40 Mapping Register 02A0 01A4 DCHMAP41 DMA Channel 41 Mapping Register 02A0 01A8 DCHMAP42 DMA Channel 42 Mapping Register 02A0 01AC DCHMAP43 DMA Channel 43 Mapping Register 02A0 01 0 DCHMAP44 DMA Channel 44 Mapping Register 02A0 01B4 DCHMAP45 DMA Channel 45 Mapping Reg
59. 0 Go operation is not in progress SYSCLK divide ratios are not being changed 1 GO operation is in progress SYSCLK divide ratios are being changed 7 8 3 4 PLL Controller Clock Align Control Register The PLL controller clock align control register ALNCTL is shown in Figure 7 27 and described in Table 7 36 31 16 Reserved R 0 15 1 0 Reserved ALN1 R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Figure 7 27 PLL Controller Clock Align Control Register ALNCTL Hex Address 029C 0140 Table 7 36 PLL Controller Clock Align Control Register ALNCTL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 ALN1 SYSCLK1 alignment Do not change the default values of these fields 0 Do not align SYSCLK1 during GO operation If SYS1 in DCHANGE is set to 1 SYSCLK1 switches to the new ratio immediately after the GOSET bit in PLLCMD is set 1 Align SYSCLK1 when the GOSET bit in PLLCMD is set The SYSCLK1 ratio is set to the ratio programmed in the RATIO bit in PLLDIV1 156 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 8 3 5 PLLDIV Ratio Change Status Register
60. 0184 82E0 MAR184 Controls EMIFA CE3 Range B800 0000 B8FF FFFF 0184 82E4 MAR185 Controls EMIFA CE3 Range B900 0000 B9FF FFFF 0184 82E8 MAR186 Controls EMIFA CE3 Range BA00 0000 BAFF FFFF 0184 82EC MAR187 Controls EMIFA CE3 Range BB00 0000 BBFF FFFF 0184 82F0 MAR188 Controls EMIFA CE3 Range BC00 0000 BCFF FFFF 0184 82F4 MAR189 Controls EMIFA CE3 Range BD00 0000 BDFF FFFF 0184 82F8 MAR190 Controls EMIFA CE3 Range BE00 0000 BEFF FFFF 0184 82FC MAR191 Controls EMIFA CE3 Range BF00 0000 BFFF FFFF 0184 8300 MAR192 Controls EMIFA 4 Range C000 0000 FFFF 0184 8304 MAR193 Controls EMIFA CE4 Range C100 0000 C1FF FFFF 0184 8308 MAR194 Controls EMIFA CE4 Range C200 0000 C2FF FFFF 0184 830 MAR195 Controls EMIFA CE4 Range C300 0000 C3FF FFFF 0184 8310 MAR196 Controls EMIFA CE4 Range C400 0000 C4FF FFFF 0184 8314 MAR197 Controls EMIFA CE4 Range C500 0000 C5FF FFFF 0184 8318 MAR198 Controls EMIFA CE4 Range C600 0000 C6FF FFFF 0184 831 MAR199 Controls EMIFA CE4 Range C700 0000 C7FF FFFF 0184 8320 MAR200 Controls EMIFA CE4 Range C800 0000 C8FF FFFF 0184 8324 MAR201 Controls EMIFA CE4 Range C900 0000 C9FF FFFF 0184 8328 MAR202 Controls EMIFA CE4 Range CA00 0000 CAFF FFFF 0184 832 MAR203 Controls EMIFA CE4 Range CB00 0000 CBFF FFFF 0184 8330 MAR204 Controls EMIFA CE4 Range CC00 0000 CCFF FFFF 0184 8334 MAR205 Controls EMIFA CE4 Range CD00 0000 CDFF FFFF 0184 8338 MAR206 Controls EMIFA CE4 Range CE00 0000 CEFF F
61. 02A0 0000 PID Peripheral ID Register 02A0 0004 CCCFG EDMA3CC Configuration Register 02 0 0008 02 0 00 Reserved 02A0 0100 DCHMAPO DMA Channel 0 Mapping Register 02A0 0104 DCHMAP1 DMA Channel 1 Mapping Register 02A0 0108 DCHMAP2 DMA Channel 2 Mapping Register 02A0 010C DCHMAP3 DMA Channel 3 Mapping Register 02A0 0110 DCHMAP4 DMA Channel 4 Mapping Register 02A0 0114 DCHMAP5 DMA Channel 5 Mapping Register 02A0 0118 DCHMAP6 DMA Channel 6 Mapping Register 02A0 011C DCHMAP7 DMA Channel 7 Mapping Register Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 111 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 7 4 EDMA3 Channel Controller Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0120 DCHMAP8 DMA Channel 8 Mapping Register 02A0 0124 DCHMAP9 DMA Channel 9 Mapping Register 02A0 0128 DCHMAP10 DMA Channel 10 Mapping Register 02A0 012C DCHMAP 1 1 DMA Channel 11 Mapping Register 02A0 0130 DCHMAP12 DMA Channel 12 Mapping Register 02A0 0134 DCHMAP13 DMA Channel 13 Mapping Register 02A0 0138 DCHMAP14 DMA Channel 14 Mapping Register 02A0 013C DCHMAP15 DMA Channel 15 Mapping Register 02A0 0140 DCHMAP16 DMA Channel 16 Mapping Register 02
62. 02A2 8128 ERRCLR Error Clear Register 02A2 812C ERRDET Error Details Register 02A2 8130 ERRCMD Error Interrupt Command Register 02A2 8134 02A2 813C Reserved 02A2 8140 RDRATE Read Rate Register 02A2 8144 02A2 823C Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 119 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 7 7 EDMA3 Transfer Controller 1 Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 8240 SAOPT Source Active Options Register 02A2 8244 SASRC Source Active Source Address Register 02A2 8248 SACNT Source Active Count Register 02A2 824C SADST Source Active Destination Address Register 02A2 8250 SABIDX Source Active Source B Index Register 02A2 8254 SAMPPRXY Source Active Memory Protection Proxy Register 02A2 8258 SACNTRLD Source Active Count Reload Register 02A2 825C SASRCBREF _ Source Active Source Address B Reference Register 02A2 8260 SADSTBREF Source Active Destination Address B Reference Register 02A2 8264 02A2 827C Reserved 02A2 8280 DFCNTRLD Destination FIFO Set Count Reload 02A2 8284 DFSRCBREF _ Destination FIFO Set Destination Address B Reference Register 02A2 8288 DFDSTBREF Destination FIF
63. 02C8 0648 TX2CP Transmit Channel 2 Completion Pointer Interrupt Acknowledge Register Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 205 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 71 Ethernet MAC EMAC Control Registers continued 6 INSTRUMENTS www ti com HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 064 TX3CP E Channel 3 Completion Pointer Interrupt Acknowledge egister 02C8 0650 TX4CP a Channel 4 Completion Pointer Interrupt Acknowledge egister 02C8 0654 TX5CP sa sa Channel 5 Completion Pointer Interrupt Acknowledge egister 02C8 0658 TX6CP 2 Channel 6 Completion Pointer Interrupt Acknowledge egister 02C8 065C TX7CP EE Channel 7 Completion Pointer Interrupt Acknowledge egister 02C8 0660 RXOCP Haag Channel 0 Completion Pointer Interrupt Acknowledge egister 02C8 0664 RX1CP 2 Channel 1 Completion Pointer Interrupt Acknowledge egister 02C8 0668 RX2CP 5 Channel 2 Completion Pointer Interrupt Acknowledge egister 02C8 066C RX3CP D d Channel 3 Completion Pointer Interrupt Acknowledge egister 02C8 0670 RX4CP s Channel 4 Completion Pointer Interrupt Acknowledge egister 02C8 0674 RX5CP Channel 5 Completion Pointer Interrupt Acknowledge egister 02C8 0678 RX6CP Ba Channel 6 Completion Pointer Interrupt Acknowledge egister
64. 02D0 0330 RIO INTDST4 RATE CNTL INTDST Interrupt Rate Control Register 4 02D0 0334 RIO INTDST5 RATE CNTL INTDST Interrupt Rate Control Register 5 02D0 0338 RIO INTDST6 RATE CNTL INTDST Interrupt Rate Control Register 6 02D0 033C RIO INTDST7 RATE CNTL INTDST Interrupt Rate Control Register 7 020 0340 0200 03FC Reserved 02D0 0400 RIO LSU1 REGO LSU1 Control Register 0 02D0 0404 RIO LSU1 REG1 LSU1 Control Register 1 02D0 0408 RIO LSU1 REG2 LSU1 Control Register 2 0200 040C RIO LSU1 LSU1 Control Register 02D0 0410 RIO LSU1 REG4 LSU1 Control Register 4 02D0 0414 RIO LSU1 REG5 LSU1 Control Register 5 0200 0418 RIO LSU1 REG6 LSU1 Control Register 6 02D0 041C RIO LSU1 FLOW MASKS LSU1 Congestion Control Flow Mask Register 02D0 0420 RIO LSU2 REGO LSU2 Control Register 0 02D0 0424 RIO LSU2 REG 1 LSU2 Control Register 1 02D0 0428 RIO LSU2 REG2 LSU2 Control Register 2 0200 042C RIO LSU2 REGS3 LSU2 Control Register 3 02D0 0430 RIO LSU2 REG4 LSU2 Control Register 4 02D0 0434 RIO LSU2 REG5 LSU2 Control Register 5 02D0 0438 RIO LSU2 REG6 LSU2 Control Register 6 02D0 043C RIO LSU2 FLOW MASKS1 LSU2 Congestion Control Flow Mask Register 02D0 0440 RIO LSU3 REGO LSU3 Control Register 0 02D0 0444 RIO LSU3 REG 1 LSU3 Control Register 1 02D0 0448 RIO 1503 REG2 LSU3 Control Register 2 0200 044C RIO LSU3 REGS3 LSU3 Control Register 3 02D0 0450 RIO 1503 REG4 LSUS Control Register 4 02D0 0454 RIO LSU3 REG5 LSU3 Control Register 5 02D0
65. 0458 RIO 1503 REG6 LSU3 Control Register 6 02D0 045C RIO 1503 FLOW MASKS2 1503 Congestion Control Flow Mask Register Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 237 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 112 RapidIO Control Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 0460 RIO_LSU4_REGO LSU4 Control Register 0 02D0 0464 RIO_LSU4_REG1 LSU4 Control Register 1 02D0 0468 RIO_LSU4_REG2 LSU4 Control Register 2 02D0 046C RIO 1504 REGS3 1504 Control Register 02D0 0470 RIO LSUA REG4 1504 Control Register 4 02D0 0474 RIO LSUA REG5 1504 Control Register 5 02D0 0478 RIO 1504 REG6 1504 Control Register 6 02D0 047C RIO LSU4 FLOW 5 1504 Congestion Control Flow Mask Register 02D0 0480 0200 04 Reserved 02D0 0500 RIO_QUEUE0_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 0 02D0 0504 RIO_QUEUE1_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 1 02D0 0508 RIO_QUEUE2_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 2 02D0 050C RIO_QUEUE3_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 3 02D0 0510 R
66. 246 7 21 2 GPIO Peripheral Register Description s l 246 7 21 9 GPIO Electrical JData Tiimilig uu Aa S UEM DEM ERI REPRE DEN EG 247 7 22 Emulation Features and Capability eee eee erence eee U nn IH I mI nem 248 7 22 1 Advanced Event Triggering 4 4 4 2144411 248 Tea MEC 248 7 22 3 6 249 7 22 31 JTAG Device Specific 249 7 22 4 JTAG Peripheral Register Description s 249 7 22 5 JTAG Electrical a 249 Revision HISIOPV um u eg 250 8 Mechanical D lu E Ker 251 8 1 Thermal Data 251 8 2 Packaging Information 251 6 Contents Submit Documentatio
67. 38 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 1 ta EKOH CEV Delay time AECLKOUT high to ACEx valid 1 3 4 9 ns 2 ta EKOH BEV Delay time AECLKOUT high to ABEx valid 4 9 ns 3 la EKOH BEIV Delay time AECLKOUT high to ABEx invalid 1 3 ns 4 ta EKOH EAV Delay time AECLKOUT high to AEAx valid 49 ns 5 la EKOH EAIV Delay time AECLKOUT high to AEAx invalid 1 3 ns 8 la EKOH ADSV Delay time AECLKOUT high to ASADS ASRE valid 1 3 4 9 ns 9 la EKOH OEV Delay time AECLKOUT high to ASOE valid 1 3 4 9 ns 10 ta EKOH EDV Delay time AECLKOUT high to AEDx valid 4 9 ns 11 la EKOH EDIV Delay time AECLKOUT high to AEDx invalid 1 3 ns 12 la EKOH WEV Delay time AECLKOUT high to ASWE valid 1 3 4 9 ns 1 following parameters are programmable via the EMIFA CE Configuration registers CEnCFG e Read latency R_LTNCY 0 1 2 or 3 cycle read latency e Write latency W_LTNCY 0 1 2 or 3 cycle write latency e assertion length CE EXT For standard SBSRAM or ZBT SRAM interface ACEx goes inactive after the final command has been issued CE EXT 0 For synchronous FIFO interface with glue ACEx is active when ASOE is active CE EXT 1 e Function of ASADS ASRE R ENABLE For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles ENABLE 0 For FIFO interface ASADS ASRE acts ASRE with NO deselect cycles ENABLE
68. 7 0184 A220 L2MPPA8 L2 memory protection page attribute register 8 0184 A224 L2MPPAQ L2 memory protection page attribute register 9 0184 A228 L2MPPA10 L2 memory protection page attribute register 10 0184 A22C L2MPPA11 L2 memory protection page attribute register 11 0184 A230 L2MPPA12 L2 memory protection page attribute register 12 0184 A234 L2MPPA13 L2 memory protection page attribute register 13 0184 A238 L2MPPA14 L2 memory protection page attribute register 14 0184 A23C L2MPPA15 L2 memory protection page attribute register 15 0184 A240 L2MPPA16 L2 memory protection page attribute register 16 0184 A244 L2MPPA17 L2 memory protection page attribute register 17 0184 A248 L2MPPA18 L2 memory protection page attribute register 18 0184 A24C L2MPPA19 L2 memory protection page attribute register 19 0184 A250 L2MPPA20 L2 memory protection page attribute register 20 0184 A254 L2MPPA21 L2 memory protection page attribute register 21 0184 A258 L2MPPA22 L2 memory protection page attribute register 22 0184 A25C L2MPPA23 L2 memory protection page attribute register 23 0184 A260 L2MPPA24 L2 memory protection page attribute register 24 0184 A264 L2MPPA25 L2 memory protection page attribute register 25 0184 A268 L2MPPA26 L2 memory protection page attribute register 26 0184 A26C L2MPPA27 L2 memory protection page attribute register 27 0184 A270 L2MPPA28 L2 memory protection page attribute register 28 0184 A274 L2MPPA29 L2 memory protection page attribute register 29 0184
69. 7 3 8 PLL Controller Clock Align Control Register 147 7 7 3 9 PLLDIV Ratio Change Status 2 148 77 3 10 SYSGEK Status Hegislet squa Suasana qua Quq a 149 7 7 4 PLL1 Controller Input and Output Clock Electrical Data Timing 150 7 8 PEE2 ahd PELA Controllers u etn 151 7 8 1 PLL2 Controller Device Specific Information 152 7 8 1 1 Internal Clocks and Maximum Operating Frequencies 152 7 8 1 2 PLL2 Controller Operating Modes 1 152 4 Contents Submit Documentation Feedback 7 9 7 10 7 11 7 12 7 13 7 14 7 15 7 16 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 8 2 PLL2 Controller Memory III hh hne hn nnne nnne nnne nnn 153 7 8 8 PLL2 Controller Register Descriptions 158 7 8 3 1 PLL Controller Divider 1 4 24 154 7 8 3 2 PLL Controller Command Register l 155 7 8 3 3 PLL Co
70. A278 L2MPPA30 L2 memory protection page attribute register 30 0184 A27C L2MPPA31 L2 memory protection page attribute register 31 0184 A280 0184 A2FC Reserved 0184 0300 0184 A3FF Reserved 0184 A400 L1PMPFAR L1 program L1P memory protection fault address register 0184 A404 L1PMPFSR L1P memory protection fault status register 0184 A408 L1PMPFCR L1P memory protection fault command register 0184 A40C 0184 A4FF Reserved 0184 A500 L1PMPLKO L1P memory protection lock key bits 31 0 0184 A504 L1PMPLK1 L1P memory protection lock key bits 63 32 0184 A508 L1PMPLK2 L1P memory protection lock key bits 95 64 0184 A50C L1PMPLKS L1P memory protection lock key bits 127 96 0184 A510 L1PMPLKCMD L1P memory protection lock key command register 0184 A514 L1PMPLKSTAT L1P memory protection lock key status register 0184 A518 0184 A5FF Reserved 0184 A600 0184 A63C 2 Reserved 0184 A640 L1PMPPA16 L1P memory protection page attribute register 16 0184 A644 L1PMPPA17 L1P memory protection page attribute register 17 1 These addresses correspond to the L2 memory protection page attribute registers 32 63 L2MPPA32 L2MPPA63 of the C64x megamaodule These registers are not supported for the C6455 device 2 These addresses correspond to the L1P memory protection page attribute registers 0 15 L1TPMPPAO L1PMPPA15 of the C64x megamaodule These registers are not supported for the C6455 device 98 C64x Megamodule Submit Documentation Fe
71. B21 DED20 A21 DED19 D19 DED18 C19 DED17 A19 DED16 B19 VO Z DDR2 Memory Controller external data DED15 C7 DED14 D7 DED13 A7 DED12 B7 DED11 F9 DED10 E9 DED9 D9 DED8 C9 DED7 D10 DED6 C10 DED5 B10 DED4 A10 DED3 D12 DED2 C12 DED1 B12 DED0 A12 TIMER 1 TOUTL1 AG7 O Z IPD Timer 1 output pin for lower 32 bit counter TINPL1 AJ6 IPD Timer 1 input pin for lower 32 bit counter TIMER 0 TOUTLO AF8 O Z IPD Timer 0 output pin for lower 32 bit counter TINPLO AH6 IPD Timer 0 input pin for lower 32 bit counter INTER INTEGRATED CIRCUIT I2C SCL AG26 VO Z I2C clock When the I2C module is used use an external pullup resistor SDA AF26 VO Z I2C data When 2 is used ensure there is an external pullup resistor Submit Documentation Feedback Device Overview 39 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU DESCRIPTION MULTICHANNEL BUFFERE D SERIAL PORT 1 AND MULTICHANNEL BUFFERED SERIAL PORT 0 McBSP1 and McBSPO McBSP external clock source as opposed to internal I CLKS AJ IPD shared by McBSP1 and McBSPO MULTICHANNEL BUFFERED SERIAL PORT 1 McBSP1 CLKR1 GP 0 AF4 VO Z IPD McBSP1 receive clock 2 or GP 0 I O Z default FSR1 GP 10 AE5 VO Z IPD McBSP1 rece
72. Configuration Switch E 84 4 4 BUS PHONG Su u ce Pave 86 C64x Megamodule 87 5 1 Memory Architecture sssssssssssssssssssssssasaaaa 87 5 2 Memory Protection 90 5 3 Bandwidth Management 90 5 4 Power Downi Control Su up iu GARDE 91 5 5 Megamodule s 91 5 6 Megamodul REVISION ott cC 92 5 7 C64x Megamodule Register Description s 4 4 11 1 nenne 93 Device Operating Conditions 101 6 1 Absolute Maximum Ratings Over Operating Case Temperature Range Unless Otherwise Noted 101 Contents 3 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 2 Recommended Operating Conditions 1 U 101 6 3 Electrical Character
73. DVpp33 AED38 AED46 AED44 AED42 AED40 J H DVpp33 Vss AED47 AED45 AED43 DVDD33 Vss H G Vss DVpp18 Vss DVpp18 Vss DVppie Vss DVDp18 AED55 AED54 AED50 AED48 AED35 G F DSDDQ F Vss DVpp18 RSV19 Vss uS Vss DVpp18 Vss AED63 AED36 AED56 AED52 AED37 E DSDDQ E DEODTO DEA4 AVpLL2 Vss DSDDQS2 Gates DVppig DSDDQS3 DVppis Vss AED59 DVppaa Vss D DEA8 DEA5 DEA0 DED19 DSDDQS2 DED23 DED27 DSDDQS3 RSV11 RSV32 5 09 AED57 AED58 AED39 D DEA9 DEA6 DEA1 DEDi8 DSDDQM2 DED22 DED26 DSDDQM3 RSV12 RSV33 RSV23 AED61 AED60 AED41 DEA10 DEA7 DEA2 DED16 DED21 DED25 DVDpp18 DED29 DED31 RSv22 AED49 AED51 Vss B DEAN DEODT1 DEA3 DED17 Vss DED20 DED24 Vss DED28 DED30 DVppismon AED62 AED53 DVppas 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Figure 2 4 C6455 Pin Map Bottom View Quadrant C 22 Device Overview Submit Documentation Feedback 4 TEXAS INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 ee ee 4 5 6 7 8 9 10 11 12 13 14 15 URADDR4 URADDR3 URADDR2 UXADDRO UXADDR2 P PCBEO PREQ PINTA PCBES DVpp33 Vss RSVO5 Vss CVpp Vss CVpp GP GP 15 GP 14 UXCLK UXADDR3 N CVppmon Vss MDIO MTCLK cee RSV29 RSV28 RSV04 CVpp Vss CVpp Vss RMREFCLK UXDATA0 URDATA7 UXDATA6 UXDATA2 UXADDR4 M MRXD7 MTXD6 MTXD2 MDCLK Vss DVppss Vop Vss Vss RMTXDO L URDATA4 URDATAS
74. Device Overview 19 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR TExAS INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 2 5 Pin Assignments 2 5 1 Pin Map Figure 2 2 through Figure 2 5 show the C6455 pin assignments in four quadrants A B C and D 10 11 12 13 14 15 AJ DVppss GP 5 FSXO CLKS DRO TINPL1 DVppss Vss TMS RSV26 RSV40 TO Vss DVppss AJ AH Vss GP 4 FSR0 NMI pun TINPLO TRST TDO TDI EMU17 RSV27 EMU16 EMU9 DVpp33 Vss AH AG CLkKRO GP 7 GPI6 red TOUTLI EMU6 EMU2 RSV38 RSV39 DVppsa Vss RESET AG AF DVppag Vss 1 ped pena EMUO TOUTLO EMUA EMU3 EMU8 EMU7 EMU14 POR RIOCLK AF ieee pee pos i Vss cna Vss DVppss 15 EMU12 EMU5 EMU18 RESETSTAT Dvpps AE AD bs jer jer dein DVppas Vss DVppss EMU13 RSV37 EMU10 RSV36 EMU11 Vss DVppas Vss AD AC 7 pete ju DVppaa Vss Vss DVppaa Vss DVppsa Vss DVpp3s Vss AVDDA AC AB HD17 HD15 HD9 HD7 HD1 M ETEN AB AD17 AD15 AD9 AD7 AD1 mal em e ve m y ime jo 8 HD16 HD6 HD4 A Dt y 18 AD16 AD6 AD4 W p Ano 979 apu ap Vs Vs vs V DVpps3 Vss pd pel RSVo2 Vss DVpp33 CVpp Vss CVpp Vss DVpprm V V poser
75. EDMAS Device Specific Information eene nennen hne 110 7 4 2 EDMAS3 Channel Synchronization Events 110 7 4 8 EDMAS Peripheral Register Description s 111 7 5 124 7 5 1 Interrupt Sources and Interrupt Controller 1 124 7 5 2 External Interrupts Electrical Data Timing 127 7 6 PRESET COMTONG Tas s c 128 764 Power on Reset POR 128 7 6 2 Warm Reset RESET 129 7 6 3 MIEPMIRCII AM TT 130 7 6 4 System ResSeluuuuu u u l Ri EEE KETENE NENIE 130 76 5 CR 130 7 6 6 Reset Priority 181 7 6 7 Reset Controller R gister PRI PR 132 7 6 7 1 Reset Type Status Register Description 132 7 6 8 Reset Electrical Data Timing auci rw
76. EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 7 62 Timing Requirements for McBSP as SPI Master or Slave CLKSTP 10b CLKXP 0 see Figure 7 54 720 850 A 1000 1000 NO 1200 UNIT MASTER SLAVE MIN MAX MIN MAX tsu DRV CKXL Setup time DR valid before CLKX low 12 2 18 ns th CKXL DRV Hold time DR valid after CLKX low 4 5 36P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 Table 7 63 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave CLKSTP 10b CLKXP 0 2 see Figure 7 54 720 850 1000 1000 NO PARAMETER 1200 UNIT MASTER SLAVE MIN MAX MIN MAX 1 thiCKXL FXL Hold time FSX low after CLKX low T 2 T 3 ns 2 la EXL CKXH Delay time FSX low to CLKX high L 2 L 3 ns 3 la CKXH DXV Delay time CLKX high to DX valid 2 4 18P 2 8 17 ns Disable time DX high impedance following _ 6 tais ckxL oxHZ data bit from CLKX low noe ns Disable time DX high impedance following 7 ldis FXH DXHZ last data bit from FSX high 6R aa TBR FAE SES 8 la FXL DXV Delay time FSX low to DX valid 12P 2 24P 17 ns 1 1 CPU clock fre
77. FIFO lengths For more detailed information on the VCP2 see the TMS320C645x DSP Viterbi Decoder Coprocessor 2 VCP2 Reference Guide literature number SPRU972 7 16 2 VCP2 Peripheral Register Description s Table 7 96 VCP2 Registers HEX ADDRESS RANGE HEXADDRESSRANGE ACRONYM REGISTER 5800 0000 VCPIC0 VCP2 Input Configuration Register 0 5800 0004 VCPIC1 VCP2 Input Configuration Register 1 5800 0008 VCPIC2 VCP2 Input Configuration Register 2 5800 000 VCPIC3 VCP2 Input Configuration Register 3 5800 0010 VCPIC4 VCP2 Input Configuration Register 4 5800 0014 VCPIC5 VCP2 Input Configuration Register 5 5800 0018 5800 0044 Reserved 5800 0048 VCPOUTO VCP2 Output Register 0 5800 004 VCPOUT1 VCP2 Output Register 1 5800 0050 5800 007 Reserved 5800 0080 N A VCPWBM VCP2 Branch Metrics Write FIFO Register 5800 0084 5800 009C Reserved 5800 00 0 N A VCPRDECS VCP2 Decisions Read FIFO Register N A 02B8 0018 VCPEXE VCP2 Execution Register N A 02B8 0020 VCPEND VCP2 Endian Mode Register N A 02B8 0040 VCPSTATO VCP2 Status Register 0 N A 02B8 0044 VCPSTAT1 VCP2 Status Register 1 N A 02B8 0050 VCPERR VCP2 Error Register Reserved N A 02B8 0060 VCPEMU VCP2 Emulation Control Register N A 02B8 0064 02B9 FFFF Reserved 220 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33
78. H2 URDATA6 MRXD6 MRXD6 M2 URDATA7 MRXD7 MRXD7 M1 UXDATAO MTXDO RMTXDO MTXDO RMTXDO MTXDO L4 UXDATA1 MTXD1 RMTXD1 MTXD1 RMTXD1 MTXD1 M4 UXDATA2 MTXD2 MTXD2 MTXD2 K4 UXDATA3 MTXD3 MTXD3 MTXD3 L3 UXDATA4 MTXD4 MTXD4 L5 UXDATA5 MTXD5 MTXD5 M3 UXDATA6 MTXD6 MTXD6 N5 UXDATA7 MTXD7 MTXD7 H4 URSOC MRXER RMRXER MRXER RMRXER MRXER H5 URENB MRXDV MRXDV MRXDV J5 UXENB MTXEN RMTXEN MTXEN RMTXEN MTXEN J4 URCLAV MCRS RMCRSDV MCRS RMCRSDV MCRS K3 UXSOC MCOL MCOL MCOL K5 UXCLAV GMTCLK GMTCLK H1 URCLK MRCLK MRCLK MRCLK N4 UXCLK MTCLK REFCLK MTCLK RMREFCLK MTCLK N3 UXADDR3 GMDIO MDIO MDIO MDIO M5 UXADDR4 GMDCLK MDCLK MDCLK MDCLK Using the RMII Mode of the EMAC The Ethernet Media Access Controller EMAC contains logic that allows it to communicate using the Reduced Media Independent Interface RMII protocol This logic must be taken out of reset before being used To use the RMII mode of the EMAC follow these steps 1 Enable the EMAC MDIO through the Device State Control Registers Unlock the PERCFGO register by writing OxOFOA 0B00 to the PERLOCK register Set bit 4 in the PERCFGO register within 16 SYSCLKS clock cycles to enable the EMAC MDIO Poll the PERSTATO register to verify state change 2 Initialize the EMAC MDIO as needed 3 Release the RMII logic from reset by clearing the bit of the EMAC Configuration Register see Section 3 4 5 As described in the previous section the RMII mode of the EMAC must
79. IPD EMAC and MDIO pins The interface used by EMAC MDIO MII RMII GMII or the standalone RGMII is controlled by the MACSEL 1 0 pins AEA 10 9 1 UTOPIA pin function enabled EMAC and MDIO pin function disabled This means all multiplexed UTOPIA EMAC and UTOPIA MDIO pins now function as UTOPIA The EMAC MDIO peripheral can still be used with RGMII MACSEL 1 0 11 For proper C6455 device operation this pin must be externally pulled up with a 1 resistor Te pH at device reset EMAC Interface Selects MACSEL 1 0 These pins select the interface used by the EMAC MDIO peripheral 00 10 100 EMAC MDIO with MII Interface default 01 10 100 EMAC MDIO with RMII Interface 10 10 100 1000 EMAC MDIO with GMII Interface AEA 10 9 25 IPD M27 11 10 100 1000 EMAC MDIO with RGMII Interface If the UTOPIA pin function is selected UTOPIA EN AEA12 pin 1 for multiplexed UTOPIA EMAC and UTOPIA MDIO pins the EMAC MDIO peripheral can only be used with RGMII For more detailed information on the UTOPIA and MAC SEL 1 0 control pin selections see Table 3 3 PCI I2C EEPROM Auto Initialization PCI EEAI PCI auto initialization via external 2 EEPROM 0 PCI auto initialization through external 2 EEPROM is disabled The PCI peripheral uses the specified PCI default values default AEA8 P25 IPD NM DM 1 PCI auto initialization through external 2 EEPROM is enabled The PCI peripheral is configured through external I2C EEP
80. JANUARY 2008 Table 7 112 RapidlO Control Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 02 0 RIO ERR RST EVNT ICRR Error Reset and Special Event Interrupt Condition Routing Register 02D0 02F4 RIO ERR RST EVNT ICRR2 Error Reset and Special Event Interrupt Condition Routing Register 2 02D0 02 8 RIO ERR RST EVNT ICRRS3 Error Reset and Special Event Interrupt Condition Routing Register 3 02D0 02FC Reserved 02D0 0300 RIO INTDSTO DECODE INTDST Interrupt Status Decode Register 0 02D0 0304 RIO INTDST1 DECODE INTDST Interrupt Status Decode Register 1 02D0 0308 RIO INTDST2 DECODE INTDST Interrupt Status Decode Register 2 02D0 030C RIO INTDST3 DECODE INTDST Interrupt Status Decode Register 3 02D0 0310 RIO INTDST4 DECODE INTDST Interrupt Status Decode Register 4 02D0 0314 RIO INTDST5 DECODE INTDST Interrupt Status Decode Register 5 02D0 0318 RIO INTDST6 DECODE INTDST Interrupt Status Decode Register 6 02D0 031C RIO INTDST7 DECODE INTDST Interrupt Status Decode Register 7 02D0 0320 RIO INTDSTO RATE CNTL INTDST Interrupt Rate Control Register 0 02D0 0324 RIO INTDST1 RATE CNTL INTDST Interrupt Rate Control Register 1 02D0 0328 RIO INTDST2 RATE CNTL INTDST Interrupt Rate Control Register 2 02D0 032C RIO INTDST3 RATE CNTL INTDST Interrupt Rate Control Register 3
81. L1D memory protection page attribute register 28 0184 AE74 L1DMPPA29 L1D memory protection page attribute register 29 0184 AE78 L1DMPPA30 L1D memory protection page attribute register 30 0184 AE7C L1DMPPA31 L1D memory protection page attribute register 31 0184 80 0185 FFFF Reserved 3 These addresses correspond to the L1D memory protection page attribute registers 0 15 L1TDMPPAO L1DMPPA15 of the C64x megamaodule These registers are not supported for the C6455 device Submit Documentation Feedback C64x4 Megamodule 99 SM320C6455 EP 3 TEXAS FIXED POINT DIGITAL SIGNAL PROCESSOR INSTR MENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 5 10 CPU Megamodule Bandwidth Management Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0182 0200 EMCCPUARBE CPU Arbitration Control Register 0182 0204 EMCIDMAARBE EMC IDMA Arbitration Control Register 0182 0208 EMCSDMAARBE EMC Slave DMA Arbitration Control Register 0182 020C EMCMDMAARBE EMC Master DMA Arbitration Control Register 0182 0210 0182 02FF Reserved 0184 1000 L2DCPUARBU 120 CPU Arbitration Control Register 0184 1004 L2DIDMAARBU L2D IDMA Arbitration Control Register 0184 1008 L2DSDMAARBU L2D Slave DMA Arbitration Control Register 0184 100C L2DUCARBU L2D User Coherence Arbitration Control Register 0184 1010
82. PLL1 controller is shown in Table 7 18 Note that only registers documented here are accessible on the C6455 Other addresses in the PLL1 controller memory map should not be modified Table 7 18 PLL1 Controller Registers Including Reset Controller HEX ADDRESS RANGE ACRONYM REGISTER NAME 029A 0000 029A 00E3 Reserved 029A 00E4 RSTYPE Reset Type Status Register Reset Controller 029A 00E8 029A 00FF Reserved 029A 0100 PLLCTL PLL Control Register 029A 0104 i Reserved 029A 0108 Reserved 029A 010G Reserved 029A 0110 PLLM PLL Multiplier Control Register 029A 0114 PREDIV PLL Pre Divider Control Register 029A 0118 Reserved 029A 011G Reserved 029A 0120 Reserved 029A 0124 Reserved 029A 0128 Reserved 029A 012G Reserved 029A 0130 Reserved 029A 0134 Reserved 029A 0138 PLLCMD PLL Controller Command Register 029A 013G PLLSTAT PLL Controller Status Register 029A 0140 ALNCTL PLL Controller Clock Align Control Register 029A 0144 DCHANGE PLLDIV Ratio Change Status Register 029A 0148 Reserved 029A 014G Reserved 029A 0150 SYSTAT SYSCLK Status Register 029A 0154 5 Reserved 029A 0158 Reserved 029A 015G Reserved 029A 0160 PLLDIV4 PLL Controller Divider 4 Register 029A 0164 PLLDIV5 PLL Controller Divider 5 Register 029A 0168 029B FFFF Reserved Submit Documentation Feedback C64x Peripheral Infor
83. PLL1 multiplier factors x1 BYPASS x 15 x20 x25 x30 x32 further limit the MIN and MAX values for tc cLkIN1 For more detailed information on these limitations see Section 7 7 1 1 Internal Clocks and Maximum Operating Frequencies 5 4 1 gt i WEN x k 3 1 4 3 le Figure 7 21 CLKIN1 Timing Table 7 30 Switching Characteristics Over Recommended Operating Conditions for SYSCLK4 CPU 8 CPU 12 see Figure 7 22 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 2 tw CKO3H Pulse duration SYSCLK4 high 4P 0 7 0 7 ns 3 lw CKO2L Pulse duration SYSCLK4 low 07 6P 0 7 ns 4 tircKO3 Transition time SYSCLK4 1 ns 1 reference points for the rise and fall transitions are measured at 3 3 V MAX and Vor MIN 2 P 1 CPU clock frequency in nanoseconds ns 4 1 sse N NX NA f NN Z N k 3 l 4 9 le Figure 7 22 SYSCLKA Timing 150 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR 7 8 www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 PLL2 and PLL2 Controller The secondary PLL controller generates interface clocks for the Ethernet media access controller EMAC and the DDR2 memory controller As shown in Figure 7 23 the PLL2 controller features a PLL multiplier controller and one
84. Peripheral Lock Register Description 66 3 4 2 Peripheral Configuration Register O Description 67 3 4 3 Peripheral Configuration Register 1 Description 69 3 4 4 Peripheral Status Registers 70 3 4 5 EMAC Configuration Register Description 78 3 4 6 Emulator Buffer Powerdown Register EMUBUFPD Description 74 3 5 Device Status Register Description U Fi 3 6 JTAG ID JTAGID Register 3 7 Pullup Pulldown Resist rs uu ph uar ka ah 78 3 8 e cite tard Rua deta e cM 78 Y ECHTE 81 4 1 Internal Buses Bridges and Switch Fabrics ua ence ee eee ee eee dadi nn nnne 81 4 2 Data Switch Fabric Connections uuu uy e E EE eaa RE 82 4 3
85. R served ee These system events are not connected and therefore 1160 L2 ED1 L2 single bit error detected 1170 12 2 L2 two bit error detected 1180 PDC_INT Powerdown sleep interrupt 119 Reserved Rd These system events are not connected and therefore 1200 L1P_CMPA L1P CPU memory protection fault 1210 L1P_DMPA L1P DMA memory protection fault 1220 L1D_CMPA L1D CPU memory protection fault 1234 L1D_DMPA L1D DMA memory protection fault 12401 12 L2 CPU memory protection fault 1254 L2 DMPA L2 DMA memory protection fault 1264 IDMA_CMPA IDMA CPU memory protection fault 1270 IDMA_BUSERR IDMA bus error interrupt 126 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 5 2 External Interrupts Electrical Data Timing Table 7 11 Timing Requirements for External Interrupts see Figure 7 6 720 850 NO A 1000 1000 UNIT 1200 MIN MAX tw NMIL Width of the NMI interrupt pulse low 6P ns 2 tw NMIH Width of the NMI interrupt pulse high 6P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns pos Figure 7 6 NMI Interrupt Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 127 SM320C645
86. REVISED JANUARY 2008 Table 7 4 EDMA3 Channel Controller Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02 0 200 ECRH Event Clear Register High 02A0 2010 ESR Event Set Register 02A0 2014 ESRH Event Set Register High 02A0 2018 CER Chained Event Register 02 0 201 CERH Chained Event Register High 02A0 2020 EER Event Enable Register 02A0 2024 EERH Event Enable Register High 02A0 2028 EECR Event Enable Clear Register 02A0 202C EECRH Event Enable Clear Register High 02A0 2030 EESR Event Enable Set Register 02A0 2034 EESRH Event Enable Set Register High 02A0 2038 SER Secondary Event Register 02A0 203C SERH Secondary Event Register High 02A0 2040 SECR Secondary Event Clear Register 02A0 2044 SECRH Secondary Event Clear Register High 02A0 2048 02 0 204C Reserved 02A0 2050 IER Interrupt Enable Register 02A0 2054 IERH Interrupt Enable Register High 02A0 2058 IECR Interrupt Enable Clear Register 02A0 205G IECRH Interrupt Enable Clear Register High 02A0 2060 IESR Interrupt Enable Set Register 02A0 2064 IESRH Interrupt Enable Set Register High 02A0 2068 IPR Interrupt Pending Register 02A0 206G IPRH Interrupt Pending Register High 02A0 2070 ICR Interrupt Clear Register 02A0 2074 ICRH Interrupt Clear Register High 02A0 2078 IEVAL Interrupt Evaluate Register 02A0 207G Reserved 02A0 2080 QER QDMA Event Register 02A0 2084 QEER QDMA Event Enable Register 02A0 2088 QEECR QDMA Event Enable Clear Register 02A0 208 QEESR QDMA Event Ena
87. Receive Unicast Enable Set Register 02C8 0108 RXUNICASTCLEAR Receive Unicast Clear Register 02C8 010C RXMAXLEN Receive Maximum Length Register 02C8 0110 RXBUFFEROFFSET Receive Buffer Offset Register 02C8 0114 RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register 02C8 0118 02C8 011C 2 Reserved 02C8 0120 RXOFLOWTHRESH Receive Channel 0 Flow Control Threshold Register 02C8 0124 RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register 02C8 0128 RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register 02C8 012C RXSFLOWTHRESH Receive Channel 3 Flow Control Threshold Register 02C8 0130 RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register 02C8 0134 RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register 02C8 0138 RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register 02C8 013C RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register 02C8 0140 RXOFREEBUFFER Receive Channel 0 Free Buffer Count Register 02C8 0144 RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register 02C8 0148 RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register 02C8 014C RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register 02C8 0150 RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register 02C8 0154 RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR
88. Region Access Enable Register for Region 2 02A0 0354 DRAEH2 DMA Region Access Enable Register High for Region 2 02A0 0358 DRAE3 DMA Region Access Enable Register for Region 3 02A0 035C DRAEH3 DMA Region Access Enable Register High for Region 3 02A0 0360 DRAE4 DMA Region Access Enable Register for Region 4 02A0 0364 DRAEH4 DMA Region Access Enable Register High for Region 4 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 113 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 7 4 EDMA3 Channel Coniroller Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0368 DRAE5 DMA Region Access Enable Register for Region 5 02A0 036C DRAEH5 DMA Region Access Enable Register High for Region 5 02A0 0370 DRAE6 DMA Region Access Enable Register for Region 6 02A0 0374 DRAEH6 DMA Region Access Enable Register High for Region 6 02A0 0378 DRAE7 DMA Region Access Enable Register for Region 7 02A0 037C DRAEH7 DMA Region Access Enable Register High for Region 7 02A0 0380 QRAEO QDMA Region Access Enable Register for Region 0 02A0 0384 QRAE1 QDMA Region Access Enable Register for Region 1 02A0 0388 QRAE2 QDMA Region Access Enable Register for Region 2 02A0 038C Q
89. Register 3 02A2 83D0 DFBIDX3 Destination FIFO BIDX Register 3 02A2 83D4 DFMPPRXY3 _ Destination FIFO Memory Protection Proxy Register 3 02A2 83D8 02A2 FFFF Reserved Table 7 8 EDMA3 Transfer Controller 2 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 0000 PID Peripheral Identification Register 02A3 0004 TCCFG Configuration Register 120 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 8 EDMA3 Transfer Controller 2 Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 0008 02A3 00FC Reserved 02A3 0100 TCSTAT EDMA3TC Channel Status Register 02A3 0104 02A3 011C Reserved 02A3 0120 ERRSTAT Error Register 02A3 0124 ERREN Error Enable Register 02A3 0128 ERRCLR Error Clear Register 02A3 012 ERRDET Error Details Register 02A3 0130 ERRCMD Error Interrupt Command Register 02A3 0134 02A3 013 Reserved 02A3 0140 RDRATE Read Rate Register 02A3 0144 02A3 023C Reserved 02A3 0240 SAOPT Source Active Options Register 02A3 0244 SASRC Source Active Source Address Register 02A3 0248 SACNT Source Act
90. Registers 512 02B4 0000 02B4 01FF Reserved 256K 512 02B4 0200 02B7 FFFF VCP2 Control Registers 128K 02B8 0000 02B9 FFFF TCP2 Control Registers 128K 02BA 0000 02BB FFFF Reserved 256K 02BC 0000 02BF FFFF PCI Control Registers 256K 02C0 0000 02C3 FFFF Reserved 256K 02C4 0000 02C7 FFFF EMAC Control 4K 02C8 0000 02C8 0FFF EMAC Control Module Registers 2K 02C8 1000 02C8 17FF MDIO Control Registers 2K 02C8 1800 02C8 1FFF Submit Documentation Feedback Device Overview 15 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 2 C6455 Memory Map Summary continued MEMORY BLOCK DESCRIPTION BLOCK SIZE BYTES HEX ADDRESS RANGE EMAC Descriptor Memory 8K 02C8 2000 02C8 3FFF Reserved 496K 02C8 4000 02CF FFFF RapidIO Control Registers 256K 02D0 0000 02D3 FFFF Reserved 768K 02D4 0000 02DF FFFF RapidlO CPPI RAM 16K 02E0 0000 02E0 3FFF Reserved 2M 16K 02 0 4000 02FF FFFF Reserved 16M 0300 0000 O3FF FFFF Reserved 192M 0400 0000 0FFF FFFF Reserved 256M 1000 0000 1FFF FFFF Reserved 256M 2000 0000 2FFF FFFF McBSP 0 Data 256 3000 0000 3000 00FF Reserved 64M 256 3000 0100 33FF FFFF McBSP 1 Data 256 3400 0000 3400 00FF Reserved 64M 256 3400 0100 37FF FFFF UTOPIA Receive Rx Data Queue 1K 3C00 0000 3C00 O3FF
91. Reserved 7M 32K 0010 8000 007F FFFF Internal RAM L2 L2 SRAM 2M 0080 0000 009F FFFF Reserved 4M 00A0 0000 OODF FFFF L1P SRAM 32K 00E0 0000 00EO 7FFF Reserved 1M 32K 00 0 8000 OOEF FFFF L1D SRAM 32K 00 0 0000 OOFO 7FFF Reserved 1M 32K OOFO 8000 OOFF FFFF Reserved 8M 0100 0000 017F FFFF C64x Megamodule Registers 4M 0180 0000 01BF FFFF Reserved 12 5M 01 0 0000 0287 FFFF HPI Control Registers 256K 0288 0000 028B FFFF McBSP 0 Registers 256K 028C 0000 028F FFFF McBSP 1 Registers 256K 0290 0000 0293 FFFF Timer 0 Registers 256K 0294 0000 0297 FFFF Timer 1 Registers 128K 0298 0000 0299 FFFF PLL1 Controller including Reset Controller Registers 512 029A 0000 029A 01FF Reserved 256K 512 029A 0200 029B FFFF PLL2 Controller Registers 512 029C 0000 029C 01FF Reserved 64K 029C 0200 029C FFFF EDMA3 Channel Controller Registers 32K 02A0 0000 02A0 7FFF Reserved 96K 02A0 8000 02A1 FFFF EDMAS Transfer Controller 0 Registers 32K 02 2 0000 02 2 7FFF EDMAS Transfer Controller 1 Registers 32K 02A2 8000 02A2 FFFF EDMAS Transfer Controller 2 Registers 32K 02A3 0000 02A3 7FFF EDMAS Transfer Controller 3 Registers 32K 02 8000 02A3 FFFF Reserved 256K 02 4 0000 02A7 FFFF Chip Level Registers 256K 02A8 0000 02AB FFFF Device State Control Registers 256 02 0000 2 FFFF GPIO Registers 16K 02B0 0000 02B0 3FFF I2C Data and Control Registers 256 02 0 4000 02 3 FFFF Control
92. Reset Option CSR 02D1 4204 RIO SP2 CTL INDEP Port 2 Control Independent Register 02D1 4208 RIO SP2 SILENCE TIMER Port 2 Silence Timer Register 02D1 420C RIO SP2 MULT EVNT CS Port 2 Multicast Event Control Symbol Request Register 02D1 4214 RIO SP2 CS TX Port 2 Control Symbol Transmit Register 02D1 4218 02D1 42FC Reserved 02D1 4300 RIO SP3 RST OPT Port 3 Reset Option CSR 02D1 4304 RIO SP3 CTL INDEP Port 3 Control Independent Register 02D1 4308 RIO SP3 SILENCE TIMER Port 3 Silence Timer Register 02D1 430C RIO SP3 MULT EVNT CS Port 3 Multicast Event Control Symbol Request Register 02D1 4310 Reserved 02D1 4314 RIO SP3 CS TX Port 3 Control Symbol Transmit Register 02D1 4318 02D2 OFFF Reserved 02D2 1000 02DF FFFF Reserved 7 20 3 Serial RapidlO Electrical Data Timing The Implementing Serial Rapid I O PCB Layout a TMS320C6455 Hardware Design application report literature number SPRAAAS specifies a complete printed circuit board PCB solution for the C6455 as well as a list of compatible SRIO devices showing two DSPs connected via a 4x SRIO link TI has performed the simulation and system characterization to ensure all SRIO interface timings in this solution are met therefore no electrical data timing information is supplied here for this interface 244 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCE
93. START conditions id 1 3 us 24 t spA Rise time SDA 1000 20 0 10 300 ns 25 Rise time SCL 1000 20 0 104 300 ns 26 tsoa Fall time SDA 300 20 0 10 300 ns 27 Fall time SCL 300 20 0 10 300 ns Delay time SCL high to SDA high for STOP 28 ta scLH SDAH condition 4 0 6 us 29 Capacitance for each 2 10 10 pF 1 Cb total capacitance of one bus line in pF If mixed with HS mode devices faster fall times are allowed Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 177 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 N _ T k 26 rT k t 23 21 19 256 4 gt 20 SCL P k 27 l lke 48 17 kb 18 us Stop Start Repeated Start 178 Figure 7 43 2 Transmit Timings C64x Peripheral Information and Electrical Specifications TExAS INSTRUMENTS www ti com 24 k 28 k Stop Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 12 Host Port Interface HPI Peripheral 7 12 1 HPI Device Specific Information The C6455 device includes a user configurable 16 bit or 32 bit Host port interface 16 2 The
94. Set TCP to enabled mode 68 Device Configuration Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 E P FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 3 4 3 Peripheral Configuration Register 1 Description The Peripheral Configuration Register PERCFG1 is used to enable the EMIFA and DDR2 Memory Controller EMIFA and the DDR2 Memory Controller do not have corresponding status bits in the Peripheral Status Registers The EMIFA and DDR2 Memory Controller peripherals can be used within 16 SYSCLK3 cycles after EMIFACTL and DDR2CTL set to 1 Once EMIFACTL and DDR2CTL are set to 1 they cannot be set to 0 Note that if the DDR2 Memory Controller and EMIFA are disabled at reset through the device configuration pins DDR2 EN ABAO and EMIFA ABA1 they cannot be enabled through the PERCFG1 register 31 8 Reserved R 0x00 7 2 1 0 Reserved DDR2CTL EMIFACTL R 0x00 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 3 5 Peripheral Configuration Register 1 PERCFG1 0 02 002C Table 3 8 Peripheral Configuration Register 1 PERCFG1 Field Descriptions Bit Field Value Description 31 2 Reserved Reserved 1 DDR2CTL Mode Control for DDR2 Memory Controller Once this bit is set to 1 it cannot be changed to 0 0 Set DDR to disabled 1 Set DDR2 to enabled
95. Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 HAS input 15 4 gt 16 HCNTLI1 0 input r HR W input v ra 13 gt HSTROBE input N l4 P 37 HCS input lt 1 3 lt HDI31 0 output A C I gt 4 HRDY B output A HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 C The timing twHsTBH HSTROBE high pulse duration must be met between consecutive HPI accesses in HPI32 mode Figure 7 48 HPI32 Read Timing HAS Not Used Tied High 186 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 gt 10 11 ase D i HCNTL 1 0 input EB X HR W input x lt 9 13 HSTROBE input 4 HCS input
96. UTOPIA Transmit Tx Data Queue 1K 3C00 0400 3C00 07FF Reserved 16M 2K 3C00 0800 3CFF FFFF Reserved 48M 3D00 0000 3FFF FFFF PCI External Memory Space 256M 4000 0000 4FFF FFFF TCP2 Data Registers 128M 5000 0000 57FF FFFF VCP2 Data Registers 128M 5800 0000 5FFF FFFF Reserved 256M 6000 0000 6FFF FFFF EMIFA EMIF64 Configuration Registers 128M 7000 0000 77FF FFFF DDR2 Memory Controller Configuration Registers 128M 7800 0000 7FFF FFFF Reserved 256M 8000 0000 8FFF FFFF Reserved 256M 9000 0000 9FFF FFFF EMIFA CE2 SBSRAM Async 8M A000 0000 A07F FFFF Reserved 256M 8M A080 0000 AFFF FFFF EMIFA SBSRAM Async 8M 000 0000 BO7F FFFF Reserved 256M 8M 080 0000 BFFF FFFF EMIFA CE4 SBSRAM Async 8M C000 0000 C07F FFFF Reserved 256M 8M C080 0000 CFFF FFFF EMIFA CE5 SBSRAM Async 8M 0000 0000 DO7F FFFF Reserved 256M 8M D080 0000 DFFF FFFF DDR2 Memory Controller CE0 DDR2 SDRAM 512M E000 0000 FFFF FFFF 1 The EMIFA and are not functionally supported on the C6455 device and therefore are not pinned out 16 Device Overview Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com 2 4 2 4 1 SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Boot Sequence The boot sequence is a process by which the DSP s internal memory is loaded with program and data sections and the DSP s internal registers are p
97. VCP2 coprocessor offers a very cost effective and synergistic solution when combined with Texas Instruments DSPs The VCP2 can support 1941 12 2 Kbps class A 3G voice channels running at 333 MHZ This document describes the operation and programming of the VCP2 Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 3 Device Configuration On the C6455 device certain device configurations like boot mode pin multiplexing and endianess are selected at device reset The status of the peripherals enabled disabled is determined after device reset By default the peripherals on the C6455 device are disabled and need to be enabled by software before being used 3 4 Device Configuration at Device Reset Table 3 1 describes the C6455 device configuration pins The logic level of the AEA 19 0 ABA 1 0 and PCI_EN pins is latched at reset to determine the device configuration The logic level on the device configuration pins can be set by using external pullup pulldown resistors or by using some control device e g FPGA CPLD to intelligently drive these pins When using a control device care should be taken to ensure there is no contention on the lines when the device is out of reset The device configuration pins are sampled during reset and are driven after the reset is removed To avoid contention the control device should only drive the
98. With Write Latency 0 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 169 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Write Latency 1 8 AEcLKouT __ AA _ f AA A f A N N 1 1 fT st 2 3 ABE70 o X BE X BE X BEA X 4 5 AEA 19 0VABA 1 0 _ X EM EA2 X EA3 X EM 10 71710 s 11 AED 63 0 C X Q X X Q X 8 KL 8 ASADS ASRE B Se s AAOE ASOE B 4 12 12 Ne 2 O ooo following parameters are programmable via the Chip Select n Configuration Register CESECn Read latency R_LTNCY 1 2 or 3 cycle read latency Write latency W_LTNCY 0 1 2 or 3 cycle write latency ACEx assertion length EXT For standard SBSRAM or ZBT SRAM interface ACEx goes inactive after the final command has been issued EXT 0 For synchronous FIFO interface ACEx is active when ASOE is active 1 Function of ASADS ASRE R_ENABLE For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles R_ENABLE 0 For FIFO interface ASADS ASRE acts as SRE with NO deselect cycles R_ENABLE 1 In this figure W_LTNCY 1 CE EXT 0 R ENABLE 0 and SSEL 1 AAOE ASOE and AAWE ASWE operate as ASOE ASWE respect
99. Z IPD EMIFA output clock at EMIFA input clock AECLKIN or SYSCLK4 frequency AAWE ASWE AB25 O Z IPU Asynchronous memory write enable Programmable synchronous interface write enable AARDY K29 IPU Asynchronous memory ready input AR W W25 O Z IPU Asynchronous memory read write AAOE ASOE Y28 O Z IPU Asynchronous Programmable synchronous memory output enable Programmable synchronous address strobe or read enable For programmable synchronous interface the ENABLE field in the Chip Select x Configuration Register selects between ASADS and ASRE ASADS ASRE R26 O Z IPU If R ENABLE 0 then the ASADS ASRE signal functions as the ASADS signal f R ENABLE 1 then the ASADS ASRE signal functions as the ASRE signal Submit Documentation Feedback Device Overview 33 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU DESCRIPTION EMIFA 64 BIT ADDRESS AEA19 BOOTMODE3 N25 AEA18 BOOTMODE2 L26 AEA17 BOOTMODE1 L25 AEA16 BOOTMODEO P26 AEA15 AECLKIN SEL P27 AEA14 HPI WIDTH R25 O Z IPD AEA13 LENDIAN R27 O Z IPU AEA12 UTOPIA_EN R28 AEA11 T25 O Z IPD EMIFA external address word address O Z Controls initialization of the DSP
100. and from the external device to the DSP This round trip delay tends to negatively impact the input setup time margin but also tends to improve the input hold time margins see Table 7 1 and Figure 7 4 Figure 7 4 represents a general transfer between the DSP and an external device The figure also represents board route delays and how they are perceived by the DSP and the external device Table 7 1 Board Level Timing Example see Figure 7 4 NO DESCRIPTION 1 Clock route delay 2 Minimum DSP hold time 3 Minimum DSP setup time 4 External device hold time requirement 5 External device setup time requirement 6 Control signal route delay 7 External device hold time 8 External device access time 9 DSP hold time requirement 10 DSP setup time requirement 11 Data route delay AECLKOUT Output from DSP k 1 Beet A qa EE 0 Input to Ext I Devi Input to External Device 2 Control Signals i Output from DSP 4 pats Control Signals 6 Input to External Device 7 8 4 4 Data Signals _ Output from External Device 9 tio 1 Data Signals B n Input to DSP A Control signals include data for Writes Data signals are generated during Reads from an external device Figure 7 4 Board Level Input Output Timings 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6
101. at the same time The device configuration pins described in Section 3 1 Device Configuration at Device Reset determine which function is enabled for the multiplexed pins Note that when the pin function of a peripheral is disabled at device reset the peripheral is permanently disabled and cannot be enabled until its pin function is enabled and another device reset is executed Also note that enabling the pin function of a peripheral does not enable the corresponding peripheral All peripherals on the C6455 device are disabled by default except when used for boot and must be enabled through software before being used Other peripheral options like PCI clock speed and EMAC MDIO interface mode can also be selected at device reset through the device configuration pins The configuration selected is also fixed at device reset and cannot be changed until another device reset is executed with a different configuration selected The multiply factor of the PLL1 Controller is not selected through the configuration pins The PLL1 multiply factor is set in software through the PLL1 controller registers after device reset The PLL2 multiply factor is fixed For more information see Section 7 7 PLL1 and PLL1 Controller and Section 7 8 PLL2 and PLL2 Controller On the C6455 device the PCI peripheral pins are multiplexed with the HPI pins and partially multiplexed with the UTOPIA pins The PCI EN pin selects the function for the HPI PCI multiplexed pins T
102. be selected by setting MACSEL 1 0 01b at device reset C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Interface Mode Clocking The on chip PLL2 and PLL2 Controller generate the clocks to the EMAC module in RGMII or GMII mode When the EMAC is enabled with these modes the input clock to the PLL2 Controller CLKIN2 must have a 25 MHz frequency For more information see Section 7 8 PLL2 and PLL2 Controller The EMAC uses SYSCLK1 of the PLL2 Controller to generate the necessary clocks for the GMII and RGMII modes When these modes are used the frequency of CLKIN2 must be 25 MHz Also divider D1 should be programmed to 2 mode default when using the GMII mode and to 5 mode when using the RGMII mode Divider D1 is software programmable and if necessary must be programmed after device reset to 5 when the RGMII mode of the EMAC is used Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 203 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 14 2 EMAC Peripheral Register Description s 6 INSTRUMENTS www ti com Table 7 71 Ethernet MAC EMAC Control Registers
103. be used as a maximum performance specification Actual performance of back to back accesses of the GPIO is dependent upon internal bus activity z mo GPOx N Figure 7 78 GPIO Port Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 247 SM320C6455 EP 79 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 www ti com 7 22 Emulation Features and Capability 7 22 1 Advanced Event Triggering AET The C6455 device supports Advanced Event Triggering AET This capability can be used to debug complex problems as well as understand performance characteristics of user applications AET provides the following capabilities Hardware Program Breakpoints specify addresses or address ranges that can generate events such as halting the processor or triggering the trace capture Data Watchpoints specify data variable addresses address ranges or data values that can generate events such as halting the processor or triggering the trace capture e Counters count the occurrence of an event or cycles for performance monitoring e State Sequencing allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences For more information on AET see the following documents Using Advanced Event Triggering to Find and Fix Intermittent Rea
104. device if and only if DXENA 1 in SPCR if DXENA 0 then D1 D2 0 if DXENA 1 then D1 6P D2 12P 194 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 CLKS 1 gt be doc d J FP dX 4 gt PREN gt FSR int 5 63 FSR pt Tr 8 DR __ X n2 X 9 X 34 3 CLKX dt ae ee ce y a 9 ke FSX int J N 11 10 FSX J n FSX XDATDLY 00b gt 13 k 12 4 43 A DX X Bito Bitn K n2 X n3 X A Parameter No 13 applies to the first data bit only when XDATDLY 0 B CLKS signal is shared by both McBSPO and McBSP1 on this device Figure 7 52 McBSP Timing Table 7 61 Timing Requirements for FSR When GSYNC 1 see Figure 7 53 720 850 NO A 1000 1000 UNIT 1200 MIN MAX tsu FRH CKSH Setup time FSR high before CLKS high 4 ns 2 th CKSH FRH Hold time FSR high after CLKS high 4 ns on 7 UA XO 1 5 FSR external 2 CLKR X need to resync CLKR X needs resync Figure 7 53 FSR Timing When GSYNC 1 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 195 SM320C6455
105. device using a shared two wire bus Application software uses the MDIO module to configure the auto negotiation parameters of each PHY attached to the retrieve the negotiation results and configure required parameters in the EMAC module for correct operation The module is designed to allow almost transparent operation of the MDIO interface with very little maintenance from the core processor The EMAC control module is the main interface between the device core processor the MDIO module and the EMAC module The relationship between these three components is shown in Figure 7 58 The MDIO uses the same pins for the MII GMII and RMII modes Standalone pins are included for the RGMII mode due to specific voltage requirements Only one mode be used at a time The mode used is selected at device reset based on the MACSEL 1 0 configuration pins for more detailed information see Section 3 Device Configuration Table 7 70 above shows which multiplexed pin are used in the MII GMII and RMII modes on the MDIO For more detailed information on the EMAC MDIO see the TMS320C645x DSP EMAC MDIO Module Reference Guide literature number SPRU975 7 14 4 4 Device Specific Information Clocking Information The MDIO clock is based on a divide down of the SYSCLK3 from the PLL1 controller and is specified to run up to 2 5 MHz although typical operation is 1 0 MHz Since the peripheral clock frequency is variable the applicat
106. divider D1 The PLL multiplier is fixed to a x20 multiplier rate and the divider D1 can be programmed to a 2 or 5 mode PLL2 power is supplied externally via the PLL2 power supply PLLV2 An external PLL filter circuit must be added to PLLV2 as shown in Figure 7 23 The 1 8 V supply for the EMI filter must be from the same 1 8 V power plane supplying the I O power supply DVppig requires EMI filter manufacturer Murata part number NFM18CC222R1C3 or NFM18CC223R1C3 All PLL external components C161 C162 and the EMI Filter should be placed as close to the C64x DSP device as possible For the best performance TI requires that all the PLL external components be on a single side of the board without jumpers switches or components other than the ones shown For reduced PLL jitter maximize the spacing between switching signals and the PLL external components C161 C162 and the EMI Filter The minimum CLKIN2 rise and fall times should also be observed For the input clock timing requirements see Section 7 8 4 PLL2 Controller Input Clock Electrical Data Timing CAUTION The PLL controller module as described the 7MS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide literature number SPRUE56 includes a superset of features some of which are not supported on the C6455 DSP The following sections describe the features that are supported it should be assumed that any feature not included in thes
107. in the enabled state 011 McBSP1 is in the static powerdown state 101 McBSP1 is in the enable in progress state Others Reserved 23 21 McBSPOSTAT McBSPO status 000 McBSPO is in the disabled state 001 McBSPO is in the enabled state 011 McBSPO is in the static powerdown state 101 McBSPO is in the enable in progress state Others Reserved 20 18 I2CSTAT 12C status 000 12C is in the disabled state 001 12C is in the enabled state 011 12 is in the static powerdown state 101 12 is in the enable in progress state Others Reserved 70 Device Configuration Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 3 9 Peripheral Status Register 0 PERSTATO Field Descriptions continued Bit Field Value Description 17 15 GPIOSTAT GPIO status 000 GPIO is in the disabled state 001 GPIO is in the enabled state 011 GPIO is in the static powerdown state 101 GPIO is in the enable in progress state Others Reserved 14 12 TIMER1STAT status 000 is in the disabled state 001 Timer1 is in the enabled state 011 Timer1 is in the static powerdown state 101 Timer1 is in the enable in progress state Others Reserved 11 9 TIMEROSTAT TimerO status 000 0 is in the disabled state 001 is in the enabled state 011 is in the static powerdown state
108. is out of reset but it executes an IDLE instruction until a DSP interrupt is generated by the host The host can generate a DSP interrupt through the PCI peripheral by setting the DSPINT bit in the Back End Application Interrupt Enable Set Register PCIBINTSET and the Status Set Register PCISTATSET Note that the HPI host boot is a hardware boot mode while the PCI host boot is a software boot mode If PCI boot is selected the on chip bootloader configures the PLL1 Controller such that CLKIN1 is multiplied by 15 More specifically PLLM is set to OEh x15 and RATIO is set to 0 1 in the PLL1 Multiplier Control Register PLLM and PLL1 Pre Divider Register PREDIV respectively The CLKIN1 frequency must not be greater than 50 MHz so that the maximum speed of the internal ROM 750 MHz is not violated The CFGGP 2 0 pins must be set to 000b during reset for proper operation of the PCI boot mode As mentioned previously a DSP interrupt must be generated at the end of the host boot process to begin execution of the loaded application Because the DSP interrupt generated by the HPI and PCI is mapped to the EDMA event DSP_EVT DMA channel 0 it will get recorded in bit 0 of the EDMA Event Register ER This event must be cleared by software before triggering transfers on DMA channel 0 EMIFA 8 bit ROM boot BOOTMODE 3 0 0100b After reset the device will begin executing software out of an Asynchronous 8 bit ROM located in EMIFA space u
109. location is always read as 0 A value written to this field has no effect 0 GOSTAT GO operation status 0 GO operation is not in progress SYSCLK divide ratios are not being changed 1 GO operation is in progress SYSCLK divide ratios are being changed 146 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 7 38 PLL Controller Clock Align Control Register The PLL controller clock align control register ALNCTL is shown in Figure 7 18 and described in Table 7 26 31 16 Reserved R 0 15 5 4 3 2 0 Reserved ALN5 ALN4 Reserved R 0 R 1 R 1 R 1 LEGEND R W Read Write R Read only n value after reset Figure 7 18 PLL Controller Clock Align Control Register ALNCTL Hex Address 029A 0140 Table 7 26 PLL Controller Clock Align Control Register ALNCTL Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 433 ALNn SYSCLKn alignment Do not change the default values of these fields 0 Do not align SYSCLKn to other SYSCLKs during GO operation If SYSn in DCHANGE is set to 1 SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set 1 Align SYSCLKn t
110. modes at reset I via pullup pulldown resistors For more detailed information see Section 3 Device Configuration Note If a configuration pin must be routed out from the device and 3 stated not driven the internal pullup pulldown IPU IPD resistor should not be relied upon TI recommends the use of an external pullup pulldown resistor For more detailed information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see Section 3 7 Pullup Pulldown Resistors Boot mode device boot mode configurations BOOTMODE 3 0 Note the peripheral must be enabled to use the particular boot mode AEA 19 16 0000 No boot default mode 0001 Host boot HPI 0010 Reserved 0011 Reserved 0100 EMIFA 8 bit ROM boot 0101 Master 2 boot 0110 Slave 2 boot 0111 Host boot PCI 1000 thru 1111 Serial Rapid boot configurations For more detailed information on the boot modes see Section 2 4 Boot Sequence CFGGP 2 0 pins must be set to 000b during reset for proper operation of the PCI boot mode EMIFA input clock source select Clock mode select for EMIFA AECLKIN SEL AEA15 0 AECLKIN default mode 1 SYSCLK4 CPU x Clock Rate The SYSCLKA clock rate is software selectable via the Software PLL1 Controller By default SYSCLKA is selected as CPU 8 clock rate HPI peripheral bus width WIDTH select Applies only when HPI is enabled PCI EN pin
111. pin UTOPIA_EN 0 there are two additional configuration pins MACSEL 1 0 to EEAI 25 select the EMAC MDIO interface AEA7 N27 AEA 10 9 MACSEL 1 0 with AEA12 0 AEA6 PCI 27 00 10 100 EMAC MDIO MII Mode Interface default 6166 01 10 100 EMAC MDIO RMII Mode Interface AEAS MCBSP1_EN U28 10 10 100 1000 EMAC MDIO GMII Mode Interface AEA4 11 10 100 1000 with RGMII Mode Interface SYSCLKOUT EN E RGMII interface requires a 1 8 V or 1 5 V I O supply T27 When UTOPIA is enabled AEA12 1 if the MACSEL 1 0 bits 11 then the EMAC MDIO RGMII interface is still functional For more detailed AEA2 CFGGP2 126 information see Section 3 Device Configuration AEA1 CFGGP1 U26 e 2 EEPROM Auto Initialization PCI_EEAI 8 PCI auto initialization via external 2 EEPROM If the PCI peripheral is disabled PCI_EN pin 0 this pin must not be pulled up 0 PCI auto initialization through 2 EEPROM is disabled default 1 PCI auto initialization through I2C EEPROM is enabled e PCI Frequency Selection PCI66 The PCI peripheral needs be enabled PCI_EN 1 to use this function Selects the PCI operating frequency of 66 MHz or 33 MHz PCI operating frequency is selected at reset via the pullup pulldown resistor on the PCI66 pin O Z IPD AEA6 0 PCI operates at 33 MHz default 1 PCI operates at 66 MHz Note If the PCI peripheral is disabled PCI EN 0 this pin must not be pulled
112. register 02B0 4020 ICDXR I2C data transmit register 02B0 4024 ICMDR I2C mode register 02B0 4028 ICIVR I2C interrupt vector register 02B0 402C ICEMDR I2C extended mode register 02B0 4030 ICPSC I2C prescaler register 02B0 4034 ICPID1 I2C peripheral identification register 1 Value 0x0000 0105 02B0 4038 ICPID2 I2C peripheral identification register 2 Value 0 0000 0005 02B0 403C 02 0 405 Reserved 02B0 4060 02B3 407F Reserved 02B0 4080 02B3 FFFF Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 175 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 11 3 2 Electrical Data Timing 7 11 3 1 Inter Integrated Circuits I2C Timing Table 7 52 Timing Requirements for 2 Timings see Figure 7 42 720 850 A 1000 1000 NO 1200 UNIT STANDARD MODE FAST MODE MIN MAX MIN MAX 1 te ScL Cycle time SCL 10 2 5 us Setup time SCL high before SDA low for a 2 isutsotH spAL repeated START condition on 0 6 us 3 t Hold time SCL low after SDA low for a 4 0 6 h SCLL SDAL START and a repeated START condition i H 4 tw SCLL Pulse duration SCL low 4 7 1 3 us 5 tw SCLH Pulse duration SCL high 4 0 6 us 6 tsu SDAV SDLH Setup time SDA valid before SCL high 250 100 ns Hold time SDA valid after SCL low For IC 3 3 4 7 th SD
113. see Section 3 3 Peripheral Selection After Device Reset Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 107 SM320C6455 EP R3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 3 4 108 www ti com Peripherals used for booting like 2 and HPI are automatically enabled after device reset It is not possible to disable these peripherals after the boot process is complete The C64x Megamodule also allows for software driven power down management for all of the C64x megamodule components through its Power Down Controller PDC The CPU can power down part or the entire C64x megamodule through the power down controller based on its own execution thread or in response to an external stimulus from a host or global controller More information on the power down features of the C64x Megamodule can be found in the TMS320C64x Megamodule Reference Guide literature number SPRU871 Preserving Boundary Scan Functionality on RGMII and DDR2 Memory Pins When the RGMII mode of the EMAC is not used the DVpp4s VREFHSTL RSV13 and RSV14 pins can be connected directly to ground Vss to save power However this will prevent boundary scan from functioning on the RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins DVppis Vageusri RSV14 and RSV13 should be connected as follows e DVppis and DV
114. simulation and system characterization to ensure all DDR2 interface timings in this solution are met therefore no electrical data timing information is supplied here for this interface only supports designs that follow the board design guidelines outlined in the SPRAAA7 application report Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 161 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 10 External Memory Interface EMIFA The EMIFA can interface to a variety of external devices or ASICs including e Pipelined and flow through Synchronous Burst SRAM SBSRAM ZBT Zero Bus Turnaround SRAM and Late Write SRAM e Synchronous FIFOs e Asynchronous memory including SRAM ROM and Flash 7 10 1 Device Specific Information Timing analysis must be done to verify all AC timings are met recommends utilizing I O buffer information specification IBIS to analyze all AC timings To properly use IBIS models to attain accurate timing analysis for a given system see the Using IBIS Models for Timing Analysis application report literature number SPRA839 To maintain signal integrity serial termination resistors should be inserted into all EMIF output signal lines for the EMIF output signals see Table 2 3 Terminal Functions A race condition may exist when certain masters write data to th
115. that the weakest output buffer can drive the net to the opposite logic level including margin e Remember to include tolerances when selecting the resistor value e For pullup resistors also remember to include tolerances on the DVpp rail For most systems a 1 resistor can be used to oppose the IPU IPD while meeting the above criteria Users should confirm this resistor value is correct for their specific application For most systems a 20 resistor can be used to complement the IPU IPD on the device configuration pins while meeting the above criteria Users should confirm this resistor value is correct for their specific application For more detailed information on input current lj and the low high level input voltages Vi and Vi for the C6455 device see Section 6 3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature To determine which pins on the C6455 device include internal pullup pulldown resistors see Table 2 3 Terminal Functions Configuration Examples Figure 3 12 and Figure 3 13 illustrate examples of peripheral selections options that are configurable on the C6455 device Device Configuration Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 32 HD 31 0 ial HRDY m 32 Bit HCNTLO HCNTL1 HHWIL HAS HR W HCS HDS1 H
116. the device The C64x Megamodule revision is dependant on the silicon revision being used For more information see the TMS320C6455 Digital Signal Processor Silicon Errata literature number SPRZ234 92 C64x4 Megamodule Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 5 7 C64x Megamodule Register Description s Table 5 4 Megamodule Interrupt Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0000 EVTFLAGO Event Flag Register 0 Events 31 0 0180 0004 EVTFLAG1 Event Flag Register 1 0180 0008 EVTFLAG2 Event Flag Register 2 0180 000C EVTFLAG3 Event Flag Register 3 0180 0010 0180 001C Reserved 0180 0020 EVTSETO Event Set Register 0 Events 31 0 0180 0024 EVTSET1 Event Set Register 1 0180 0028 EVTSET2 Event Set Register 2 0180 002C EVTSET3 Event Set Register 3 0180 0030 0180 003C Reserved 0180 0040 EVTCLRO Event Clear Register 0 Events 31 0 0180 0044 EVTCLR1 Event Clear Register 1 0180 0048 EVTCLR2 Event Clear Register 2 0180 004C EVTCLRS Event Clear Register 3 0180 0050 0180 007C Reserved 0180 0080 EVTMASKO Event Mask Register 0 Events 31 0 0180 0084 EVTMASK1 Event Mask Register 1 0180 0088 EVTMASK2 Event Mask Register 2 0180 008C EVTMASK3 Event Mask
117. the registers which can be initialized through the PCI auto initialization Also shown is the default value of these registers when PCI auto initialization is not used PCI auto initialization is controlled enabled disabled through the PCI EEAI pin P25 For more information on this feature see the TMS320C645x DSP Peripheral Component Interconnect PCI User s Guide literature number SPRUE60 and the TMS320C645x Bootloader User s Guide literature number SPRUEC6 Table 7 98 Default Values for PCI Configuration Registers DEFAULT REGISTER VALUE Vendor ID Device ID Register PCIVENDEV 104C B000h Class Code Revision ID Register PCICLREV 0000 0001h Subsystem Vendor ID Subsystem ID Register 0000 0000h PCISUBID Max Latency Min Grant Interrupt Pin Interrupt Line 0000 0100h Register PCILGINT The on chip Bootloader supports a host boot which allows an external PCI device to load application code into the DSP s memory space The PCI boot is terminated when the Host generates a DSP interrupt The Host can generate a DSP interrupt through the PCI peripheral by setting the DSPINT bit in the Back End Application Interrupt Enable Set Register PCIBINTSET and the Status Set Register PCISTATSET For more information on the boot sequence of the C6455 DSP see Section 2 4 NOTE After the host boot is complete the DSP interrupt is registered in bit 0 channel 0 of the EDMA Event Register ER This event must be cle
118. ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 88 Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit see Figure 7 70 720 850 NO PARAMETER Ao 000 UNIT MIN MAX Setup time transmit selected signals valid before TXC at DSP high low 1 2 ns tsu TXD TXCH 1 2 h TXCH TXD Hold time transmit selected signals valid after TXC at DSP high low 1 For RGMII transmit selected signals include TXD 3 0 and TXCTL TXC at DSP pins Internal TXC 4 TXC at DSP B TXD 3 0 i 2 A Data and control information is transmitted using both edges of the clocks TXD 3 0 carries data bits 3 0 on the rising edge of TXC and data bits 7 4 on the falling edge of TXC Similarly TX_CTL carries TXEN on rising edge of TXC and TXERR of falling edge B TXC is delayed internally before being driven to the TXC pin Figure 7 70 EMAC Transmit Interface Timing RGMII Operation Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 215 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR 6 INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 14 4 Management Data Input Output MDIO The Management Data Input Output MDIO module implements the 802 3 serial management interface to interrogate and controls up to 32 Ethernet PHY s connected to the
119. time UXCLK high to UXDATA valid 3 12 ns 4 ta UXCH UXCLAV Delay time UXCLK high to UXCLAV driven active value 3 12 ns 5 ta UXCH UXCLAVL Delay time UXCLK high to UXCLAV driven inactive low 3 12 ns 6 td UXCH UXCLAVHZ Delay time UXCLK high to UXCLAV going Hi Z 9 18 5 ns 7 tw UXCLAVL UXCLAVHZ Pulse duration low UXCLAV low to UXCLAV Hi Z 3 ns 10 ta UXCH UXSV Delay time UXCLK high to UXSOC valid 3 12 ns ARA f A A JY N gt lt 1 UXDATA 0 P45 X P46 X P4 P48 CH X gt F lt 3 2 UXADDR4O OxitF N X OIF X N X N A OxtF lt 6 gt R 7 gt 4 gt lt 5 UXCLAV ____ Oa 2 9 k 8 UXENB LLL ek NX 4 222 220 10 UXSOC N A The UTOPIA Slave module has signals that are middle level signals indicating a high impedance state i e the UXCLAV and UXSOC signals Figure 7 76 UTOPIA Slave Transmit Timing 232 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 110 Timing Requirements for UTOPIA Slave Receive see Figure 7 77 720 850 NO A 1000 1000 UNIT 1200 MIN MAX tsu URDV URCH Setup time URDATA valid before URCLK high th URCH URDV Hold time URADDR valid after URCLK high tsu URAV URCH Setup time URADDR valid before URCLK high
120. up e McBSP1 Enable bit MCBSP1 EN Selects which function is enabled on the McBSP1 GPIO muxed pins 025 AEAS 0 GPIO pin functions enabled default 1 McBSP1 pin functions enabled e SYSCLKOUT Enable SYSCLKOUT EN Selects which function is enabled on the SYSCLK4 GP 1 muxed pin 4 0 GP 1 pin function of the SYSCLK4 GP 1 pin enabled default 1 SYSCLK4 pin function of the SYSCLK4 GP 1 pin enabled e Configuration GPI CFGGP 2 0 AEA 2 0 These pins are latched during reset and their values are shown in the DEVSTAT register These values can be used by software routines for boot operations Note For proper C6455 device operation the AEA11 pin must be externally pulled up at device reset with a 1 resistor The AEA3 pin must be pulled up at device reset using a 1 kQ resistor if power is applied to the SRIO supply pins If the SRIO peripheral is not used and the SRIO supply pins are connected to Vss the AEAS pin must be pulled down to Vss using a 1 kQ resistor Submit Documentation Feedback Device Overview 35 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESC
121. 0 0 Set HPI to disabled mode 1 Set HPI to enabled mode 17 Reserved 1 Reserved Submit Documentation Feedback Device Configuration 67 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 3 7 Peripheral Configuration Register 0 PERCFGO Field Descriptions continued Bit Field Value Description 16 McBSP1CTL Mode control for McBSP1 0 Set McBSP1 to disabled mode Set McBSP1 to enabled mode 15 Reserved Reserved 14 McBSPOCTL Mode control for McBSPO 0 Set McBSPO to disabled mode Set McBSPO to enabled mode 13 Reserved Reserved 12 I2CCTL Mode control for 12C 0 Set 2 to disabled mode Set 12C to enabled mode 11 Reserved Reserved 10 GPIOCTL Mode control for GPIO 0 Set GPIO to disabled mode Set GPIO to enabled mode Reserved Reserved TIMER1CTL Mode control for Timer 1 0 Set Timer 1 to disabled mode Set Timer 1 to enabled mode Reserved Reserved TIMEROCTL Mode control for Timer 0 0 Set Timer 0 to disabled mode Set Timer 0 to enabled mode 5 Reserved Reserved EMACCTL Mode control for EMAC MDIO 0 Set EMAC MDIO to disabled mode Set EMAC MDIO to enabled mode Reserved Reserved VCPCTL Mode control for VCP 0 Set VCP to disabled mode Set VCP to enabled mode 1 Reserved Reserved 0 TCPCTL Mode control for TCP 0 Set TCP to disabled mode
122. 0 10 100 MII Mode AEA 2 0 CFGGP 2 0 000 default Figure 3 12 Configuration Example A McBSP HPI32 I2C EMIFA DDR2 Memory Controller TIMERS RapidlO EMAC MII MDIO Submit Documentation Feedback Device Configuration 79 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 32 HD 31 0 HRDY HINT HCNTLO HCNTL1 HHWIL HAS HR W HCS HDS1 HDS2 UTOPIA GPIO GP 15 12 2 1 6 INSTRUMENTS www ti com AED 63 0 AECLKIN AARDY AHOLD 22 3 ACE 3 0 ABE 7 0 AECLKOUT ASDCKE AHOLDA ABUSREQ ASADS ASRE AAOE ASOE AAWE ASWE ED 31 0 DEA 21 2 DCE 1 0 DBE 3 0 DDRCLK DDRCLK DSDCKE DDQS DDQS DSDCAS DSDRAS DSDWE CLKIN1 PLLV1 PLL1 and PLL1 and PLL2 CLKIN2 PLLV2 SYSCLK4 Controller Controller CLKR1 FSR1 DR1 CLKS1 TINP1L DX1 FSX1 CLKX1 MeBSP TOUT1L CLKRO FSRO DRO CLKSO TINPO 5 0 CLKXO McBSPO TOUTO MRXD 7 0 MRXER MRXDV MCOL MCRS MTCLK MRCLK MTXD 7 0 MTXEN RIOCLK RIOCLK RIOTX 3 0 RIOTX 3 0 RIORX 3 0 RIORX 3 0 SCL MDIO MDCLK SDA Shading denotes a peripheral module not available for this configuration DEVSTAT Register 0x0061 C161 PCI EN 0 PCI disabled default ABA1 EMIFA EN 1 EMIFA enabled DDR2 EN 1 DDR2 Memory Controller enabled AEA 19 16 BOOTMODE 3 0 0001 HPI Boot AEA 15 S
123. 007 REVISED JANUARY 2008 Table 7 100 PCI Back End Configuration Registers continued 3 TEXAS INSTRUMENTS www ti com DSP ACCESS HEX ADDRESS RANGE ACRONYM DSP ACCESS REGISTER NAME 02C0 0308 PCIMCFGCMD PCI Master Configuration IO Access Command Register 02 0 030C 02 0 030F Reserved 02C0 0310 PCIMSTCFG PCI Master Configuration Register Table 7 101 DSP to_PCI Address Translation Registers HEX ADDRESS PANDE ACRONYM DSP ACCESS REGISTER NAME 02C0 0314 PCIADDSUBO PCI Address Substitute 0 Register 02C0 0318 PCIADDSUB1 PCI Address Substitute 1 Register 02C0 031G PCIADDSUB2 PCI Address Substitute 2 Register 02C0 0320 PCIADDSUB3 Address Substitute Register 02C0 0324 PCIADDSUB4 PCI Address Substitute 4 Register 02C0 0328 PCIADDSUB5 _ PCI Address Substitute 5 Register 02C0 032C PCIADDSUB6 PCI Address Substitute 6 Register 02C0 0330 PCIADDSUB7 Address Substitute 7 Register 02C0 0334 PCIADDSUBS8 PCI Address Substitute 8 Register 02C0 0338 PCIADDSUB9 Address Substitute 9 Register 02C0 033C PCIADDSUB10 PCI Address Substitute 10 Register 02C0 0340 PCIADDSUB11 PCI Address Substitute 11 Register 02C0 0344 PCIADDSUB12 PCI Address Substitute 12 Register 02C0 0348 PCIADDSUB13 PCI Address Substitute 13 Register 02C0 034C PCIADDSUB14 PCI Address Substitute
124. 010 111b 0 LSB LSB This bit is read as a 1 for C6455 Submit Documentation Feedback Device Configuration 77 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 3 7 3 8 78 www ti com Pullup Pulldown Resistors Proper board design should ensure that input pins to the C6455 device always be at a valid logic level and not floating This may be achieved via pullup pulldown resistors The C6455 device features internal pullup IPU and internal pulldown IPD resistors on most pins to eliminate the need unless otherwise noted for external pullup pulldown resistors An external pullup pulldown resistor needs to be used in the following situations e Device Configuration Pins If the pin is both routed out and 3 stated not driven an external pullup pulldown resistor must be used even if the IPU IPD matches the desired value state Other Input Pins If the IPU IPD does not match the desired value state use an external pullup pulldown resistor to pull the signal to the opposite rail For the device configuration pins listed in Table 3 1 if they are both routed out and 3 stated not driven it is strongly recommended that an external pullup pulldown resistor be implemented Although internal pullup pulldown resistors exist on these pins and they may match the desired configuration value providing external connectivity can help ensur
125. 02A0 04C8 Q3E2 Event Queue 3 Entry Register 2 02A0 04CC Q3E3 Event Queue 3 Entry Register 3 02A0 04D0 Q3E4 Event Queue 3 Entry Register 4 02A0 04D4 Q3E5 Event Queue 3 Entry Register 5 02A0 04D8 Q3E6 Event Queue 3 Entry Register 6 02A0 04DC Q3E7 Event Queue 3 Entry Register 7 02A0 04E0 Q3E8 Event Queue 3 Entry Register 8 02A0 04E4 Q3E9 Event Queue 3 Entry Register 9 02A0 04E8 Q3E10 Event Queue 3 Entry Register 10 02A0 04EC Q3E11 Event Queue 3 Entry Register 11 02A0 04F0 Q3E12 Event Queue 3 Entry Register 12 02A0 04F4 Q3E13 Event Queue 3 Entry Register 13 02A0 04F8 Q3E14 Event Queue 3 Entry Register 14 02A0 04FC Q3E15 Event Queue 3 Entry Register 15 02A0 0500 02A0 051C Reserved 02A0 0520 02A0 05FC Reserved 02A0 0600 QSTATO Queue Status Register 0 02A0 0604 QSTAT1 Queue Status Register 1 02A0 0608 QSTAT2 Queue Status Register 2 02A0 060C QSTAT3 Queue Status Register 3 02A0 0610 02A0 061C Reserved 02A0 0620 QWMTHRA Queue Watermark Threshold A Register 02A0 0624 02A0 063C Reserved 02A0 0640 CCSTAT Status Register 02A0 0644 02A0 06 Reserved 02A0 0700 02 0 7 Reserved 02A0 0800 MPFAR Memory Protection Fault Address Register 02A0 0804 MPFSR Memory Protection Fault Status Register 02A0 0808 MPFCR Memory Protection Fault Command Register 02 0 080 Memory Protection Page Attribute Register 0 02A0 0810 MPPA1 Memory Protection Page Attribute Register 1 02A0 0814 MPPA2 Memory Protection Page Attribute
126. 08 HAS X XI Ww N o 4 13 h 16 lt 16 15 4 5 15 37 4 37 r 14 gt HSTROBE A w J 3 3 lt 1 01 i 1 gt 2 Ese 2 wa a 38 4 4 9 9 7 Ie 6 4 HRDY B HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 44 16 Read Timing HAS Not Used Tied High 182 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 HAS N N 4 12 4 1 e 11 X XXX k gt 12 12 e 11 e 11 GW wwwWasi kH 12 12 4 1 11 4 k 10 je 10 9 4 9 37 13 lt 13 697 0 4 14 gt HSTROBE A _ 54 EN 1 0 1 3 4 2 3
127. 124 This system event is generated from within the C64x megamodule C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 10 C6455 System Event Mapping continued EVENT NUMBER INTERRUPT EVENT DESCRIPTION 41 XINTO McBSPO transmit interrupt 42 RINT1 receive interrupt 43 XINT1 McBSP1 transmit interrupt 44 50 Reserved Reserved Do not use 51 GPINTO GPIO interrupt 52 GPINT1 GPIO interrupt 53 GPINT2 GPIO interrupt 54 GPINT3 GPIO interrupt 55 GPINT4 GPIO interrupt 56 GPINT5 GPIO interrupt 57 GPINT6 GPIO interrupt 58 GPINT7 GPIO interrupt 59 GPINT8 GPIO interrupt 60 GPINT9 GPIO interrupt 61 GPINT10 GPIO interrupt 62 GPINT11 GPIO interrupt 63 GPINT12 GPIO interrupt 64 GPINT13 GPIO interrupt 65 GPINT14 GPIO interrupt 66 GPINT15 GPIO interrupt 67 TINTLOO Timer O lower counter interrupt 68 TINTHIO Timer 0 higher counter interrupt 69 TINTLO1 Timer 1 lower counter interrupt 70 TINTHI1 Timer 1 higher counter interrupt 71 EDMA3CC_INTO completion interrupt Mask0 72 EDMA3CC_INT1 completion interrupt Mask1 73 EDMASCO INT2 EDMASCC completion interrupt Mask2 74 EDMA3CC_INT3 completion
128. 14 Register 02C0 0350 PCIADDSUB15 PCI Address Substitute 15 Register 02C0 0354 PCIADDSUB16 PCI Address Substitute 16 Register 02C0 0358 PCIADDSUB17 PCI Address Substitute 17 Register 02C0 035C PCIADDSUB18 PCI Address Substitute 18 Register 02C0 0360 PCIADDSUB19 PCI Address Substitute 19 Register 02C0 0364 PCIADDSUB2O PCI Address Substitute 20 Register 02C0 0368 PCIADDSUB 21 PCI Address Substitute 21 Register 02C0 036C PCIADDSUB22 PCI Address Substitute 22 Register 02C0 0370 PCIADDSUB23 PCI Address Substitute 23 Register 02C0 0374 PCIADDSUB24 PCI Address Substitute 24 Register 02C0 0378 PCIADDSUB25 PCI Address Substitute 25 Register 02 0 037C PCIADDSUB26 PCI Address Substitute 26 Register 02 0 0380 PCIADDSUB27 PCI Address Substitute 27 Register 02C0 0384 PCIADDSUB28 PCI Address Substitute 28 Register 02C0 0388 PCIADDSUB29 PCI Address Substitute 29 Register 02C0 038C PCIADDSUB30 PCI Address Substitute 30 Register 02C0 0390 PCIADDSUB31 PCI Address Substitute 31 Register 226 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 102 PCI Hook Configuration Registers DSP ACCESS HEX ADDRESS RANGE ACRONYM DSP ACCESS REGISTER NAME 0
129. 184 0182 O1FF Reserved 94 C64x4 Megamodule Submit Documentation Feedback SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR 4 6 INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 5 8 Megamodule Cache Configuration Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 0000 L2CFG L2 Cache Configuration Register 0184 0004 0184 001F Reserved 0184 0020 L1PCFG L1P Configuration Register 0184 0024 L1PCC L1P Cache Control Register 0184 0028 0184 003F Reserved 0184 0040 L1DCFG L1D Configuration Register 0184 0044 L1DCG L1D Cache Control Register 0184 0048 0184 0FFF Reserved 0184 1000 0184 104F See Table 5 10 CPU Megamodule Bandwidth Management Registers 0184 1050 0184 3FFF z Reserved 0184 4000 L2WBAR L2 Writeback Base Address Register for Block Writebacks 0184 4004 L2WWC L2 Writeback Word Count Register 0184 4008 0184 400C Reserved 0184 4010 L2WIBAR L2 Writeback and Invalidate Base Address Register for Block Writebacks 0184 4014 L2WIWC L2 Writeback and Invalidate word count register 0184 4018 L2IBAR L2 Invalidate Base Address Register 0184 401C L2IWC L2 Invalidate Word Count Register 0184 4020 L1PIBAR L1P Invalidate Base Address Register 0184 4024 L1PIWC L1P Invalidate Word Count Register 0184 4030 L1DWIBAR L1D Writeback and
130. 1B8 RIO SP3 ERR STAT Port 3 Error and Status CSR 0200 11BC RIO SP3 CTL Port 3 Control CSR 02D0 11 0 0200 1FFC Reserved RapidlO Extended Feature Error Management Registers 02D0 2000 RIO ERR RPT BH Error Reporting Block Header 02D0 2004 Reserved 02D0 2008 RIO ERR DET Logical Transport Layer Error Detect CSR 02D0 200C RIO ERR EN Logical Transport Layer Error Enable CSR 02D0 2010 RIO H ADDR CAPT Logical Transport Layer High Address Capture CSR 02D0 2014 RIO ADDR CAPT Logical Transport Layer Address Capture CSR 02D0 2018 RIO ID CAPT Logical Transport Layer Device ID Capture CSR 242 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 112 RapidIO Control Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 201C RIO CTRL Logical Transport Layer Control Capture CSR 02D0 2020 02D0 2024 Reserved 02D0 2028 RIO PW TGT ID Port Write Target Device ID CSR 0200 202C 0200 203C Reserved 02D0 2040 RIO_SP0_ERR_DET Port 0 Error Detect CSR 02D0 2044 RIO_SP0_RATE_EN Port 0 Error Enable CSR 02D0 2048 RIO_SPO_ERR_ATTR_CAPT_DBGO Port 0 Attributes Error Ca
131. 1FF Reserved 029C 0200 029C FFFF Reserved 7 8 3 PLL2 Controller Register Descriptions This section provides a description of the PLL2 controller registers For details on the operation of the PLL controller module see the TMS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide literature number SPRUE56 NOTE The PLL2 controller registers can only be accessed using the CPU or the emulator Not all of the registers documented in the TMS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide literature number SPRUE56 are supported on the C6455 Only those registers documented in this section are supported Furthermore only the bits within the registers described here are supported You should not write to any reserved memory location or change the value of reserved bits Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 153 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 8 3 4 PLL Controller Divider 1 Register The PLL controller divider 1 register PLLDIV1 is shown in Figure 7 24 and described in Table 7 33 31 16 Reserved R 0 15 14 5 4 0 D1EN Reserved RATIO R W 1 R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Figure 7 24 PLL Controller Divider 1 Register PLLDIV1 Hex Addr
132. 2 PGBE3 P5 Volz 52 I or PCI command byte enable UXADDR1 PIDSEL R3 4 2 PCI initialization device UXADDROPTRDY 102 a w ikha iha HD31 AD31 AA3 HD30 AD30 AA5 HD29 AD29 AC4 HD28 AD28 AA4 HD27 AD27 5 HD26 AD26 Y1 HD25 AD25 AD2 HD24 AD24 W1 Voz Host port data 31 16 pin 1 0 2 default or PCI data address bus 31 16 HD23 AD23 0 2 HD22 AD22 HD21 AD21 AD1 HD20 AD20 W2 HD19 AD19 AC1 HD18 AD18 Y2 HD17 AD17 AB1 HD16 AD16 Y3 HD15 AD15 AB2 HD14 AD14 W4 HD13 AD13 AC2 HD12 AD12 V4 HD11 AD11 AF3 HD10 AD10 HD9 AD9 AB3 HD8 AD8 W5 VO Z Host port data 15 0 pin I O Z default or PCI data address bus 15 0 0 2 HD7 AD7 AB4 HD6 AD6 Y4 HD5 AD5 AD3 HD4 AD4 Y5 HD3 AD3 AD4 HD2 AD2 W6 HD1 AD1 5 HD0 AD0 AE2 32 Device Overview Submit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR B SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE iPD IPU O DESCRIPTION NAME NO EMIFA 64 BIT CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ABA1 EMIFA EN V25 O Z IPD EMIFA bank address control ABA 1 0 e Active low bank selects for the 64 bit EMIFA When interfacing to 16 bit Asynchronous devices ABA1 carries bit 1 of the byte address For an 8 bit Asynchronous interface ABA 1 0 are used to ca
133. 28 Mailbox to Queue Mapping Register H28 02D0 08bE8 RIO RXU MAP L29 Mailbox to Queue Mapping Register L29 02D0 08EC RIO RXU MAP H29 Mailbox to Queue Mapping Register H29 0200 08F0 RIO RXU MAP L30 Mailbox to Queue Mapping Register L30 02D0 08F4 RIO RXU MAP H30 Mailbox to Queue Mapping Register H30 02D0 08F8 RIO RXU MAP L31 Mailbox to Queue Mapping Register L31 02D0 08FC RIO RXU MAP H31 Mailbox to Queue Mapping Register H31 02D0 0900 RIO FLOW CNTLO Flow Control Table Entry Register 0 02D0 0904 RIO FLOW ONTL1 Flow Control Table Entry Register 1 0200 0908 RIO FLOW CNTL2 Flow Control Table Entry Register 2 02D0 090C RIO FLOW CNTL3 Flow Control Table Entry Register 3 0200 0910 RIO FLOW CNTL4 Flow Control Table Entry Register 4 02D0 0914 RIO FLOW CNTL5 Flow Control Table Entry Register 5 02D0 0918 RIO FLOW CNTL6 Flow Control Table Entry Register 6 0200 091C RIO FLOW CNTL7 Flow Control Table Entry Register 7 02D0 0920 RIO FLOW CNTL8 Flow Control Table Entry Register 8 02D0 0924 RIO FLOW CNTL9 Flow Control Table Entry Register 9 02D0 0928 RIO FLOW ONTL10 Flow Control Table Entry Register 10 0200 092C RIO FLOW ONTL11 Flow Control Table Entry Register 11 02D0 0930 RIO FLOW OCNTL12 Flow Control Table Entry Register 12 02D0 0934 RIO FLOW OCNTL13 Flow Control Table Entry Register 13 02D0 0938 RIO FLOW ONTL14 Flow Control Table Entry Register 14 02D0 093C RIO FLOW OCNTL15 Flow Control Table Entry Register 15 0200 0940 0200 09FC Reserved RapidlO Periphe
134. 2C0 0394 PCIVENDEVPRG PCI Vendor ID and Device ID Program Register 02C0 0398 PCICMDSTATPRG PCI Command and Status Program Register 02C0 039C PCICLREVPRG PCI Class Code and Revision ID Program Register 02C0 03A0 PCISUBIDPRG PCI Subsystem Vendor ID and Subsystem ID Program Register 02 0 03A4 PCIMAXLGPRG PCI Max Latency and Min Grant Program Register 02C0 03A8 PCILRSTREG PCI LRESET Register 02 0 PCICFGDONE _ PCI Configuration Done Register 02 0 03B0 PCIBAROMPRG PCI Base Address Mask Register 0 Program Register 02C0 03B4 PCIBAR1MPRG Base Address Mask Register 1 Program Register 02C0 03B8 PCIBAR2MPRG _ PCI Base Address Mask Register 2 Program Register 02C0 03BG PCIBARSMPRG PCI Base Address Mask Register Program Register 02 0 03CO PCIBARAMPRG Base Address Mask Register 4 Program Register 02C0 03C4 PCIBARSMPRG _ PCI Base Address Mask Register 5 Program Register 02 0 03C8 PCIBAROPRG PCI Base Address Register 0 Program Register 02C0 03CC PCIBAR1PRG PCI Base Address Register 1 Program Register 02C0 0300 PCIBAR2PRG PCI Base Address Register 2 Program Register 02C0 03D4 PCIBAR3PRG PCI Base Address Register 3 Program Register 02C0 03D8 PCIBAR4PRG PCI Base Address Register 4 Program Register 02C0 03DG PCIBAR5PRG PCI Base Address Register 5 Program Register 02C0 03E0 PCIBAROTRLPRG PCI Base Address Translation Register 0 Program Register 02C0 03E4 PCIBAR1TRLPRG PCI Base Address Translation Register 1 Pro
135. 320C6455 Design Guide and Comparisons to TMS320TC6416T literature number SPRAA89 7 20 2 Serial RapidlO Peripheral Register Description s Table 7 112 RapidlO Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 0000 RIO PID Peripheral Identification Register 02D0 0004 RIO PCR Peripheral Control Register 02D0 0008 02DO 001C Reserved 02D0 0020 RIO PER SET CNTL Peripheral Settings Control Register 0200 0024 0200 002C Reserved 02D0 0030 RIO GBL EN Peripheral Global Enable Register 02D0 0034 RIO GBL EN STAT Peripheral Global Enable Status 0200 0038 RIO BLKO EN Block Enable 0 02D0 003C RIO BLKO EN STAT Block Enable Status 0 02D0 0040 RIO BLK1 EN Block Enable 1 02D0 0044 RIO BLK1 EN STAT Block Enable Status 1 234 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 112 RapidIO Control Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 0048 RIO BLK2 EN Block Enable 2 02D0 004C RIO BLK2 EN STAT Block Enable Status 2 02D0 0050 RIO BLK3 EN Block Enable 3 0200 0054 RIO EN STAT Block Enable Status 3 0200 0058 RIO BLK4
136. 4 4 RIOCLK 4 RIORX 3 0 gt RIORX 3 0 Receive RAPID IO A This pin functions as GP 1 by default For more details see the Device Configuration section of this document B These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins For more details see the Device Configuration section of this document C These UTOPIA and PCI peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins For more details see the Device Configuration section of this document Figure 2 7 Timers GPIO RapidlO Peripheral Signals Submit Documentation Feedback Device Overview 25 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 AED 63 0 ACE5 A 2 AEA 19 0 ABA 1 0 DED 31 0 DEA 13 0 DSDDQM3 DSDDQM2 DSDDQM1 DSDDQMO Memory Map Space Select External Memory I F a Byte Enables Memory Map Space Select Bus Arbitration EMIFA 64 bit Data Bus External n Memory I F C m Byte Enables DDR2 Memoty Controller 32 bit Data Bus Bank Address A EMIFA ACEO and are not functionally supported on the C6455 device 26 Device Overview 6 INSTRUMENTS www ti com
137. 4 TBD SNPB Level 4 220C 72 HR V62 07649 01XA ACTIVE FCBGA GTZ 697 44 TBD SNPB Level 4 220C 72 HR V62 07649 02XA ACTIVE FCBGA GTZ 697 44 TBD SNPB Level 4 220C 72 HR The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS Tis terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip ch
138. 455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com 7 2 7 3 7 3 1 power supplies SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Recommended Control Signal Transition Behavior All clocks and control signals must transition between Vj and Vi or between Vi and Vip in a monotonic manner Power Supplies Power Supply Sequencing TI recommends the power supply sequence shown in Figure 7 5 After the DVppss supply is stable the remaining power supplies can be powered up at the same time as CVpp as long as their supply voltage never exceeds the CVpp voltage during powerup Some TI power supply devices include features that facilitate power sequencing for example Auto Track or Slow Start Enable features For more information visit www ti com dsppower CVpp12 E All other Figure 7 5 Power Supply Sequence Table 7 2 Timing Requirements for Power Supply Sequence NO 720 850 A 1000 1000 UNIT 1200 MIN MAX 1 2 Setup time DVppas supply stable before CVpp12 supply stable 0 5 200 ms 2 lsucVDD12 ALLsUP Setup time CVpp12 supply stable before all other supplies stable 0 200 ms 7 3 2 Power Supply Decoupling To properly decouple the supply planes from system noise place as many capacitors caps as possible close to the DSP These caps need to be close to the DSP no more than 1 25 cm maximum distance to be effective
139. 45x device and other devices compliant with Philips Semiconductors Inter IC bus I2C bus specification version 2 1 and connected by way of an I2C bus This document assumes the reader is familiar with the I2C bus specification TMS320C645x DSP Peripheral Component Interconnect PCI User s Guide This document describes the peripheral component interconnect PCI port in C645x devices See the PCI Specification revision 2 3 for details on the PCI interface TMS320C645x DSP Serial Rapid User s Guide This document describes the Serial Rapid IO SRIO on the C645x devices TMS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide This document describes the operation of the software programmable phase locked loop PLL controller in the C645x digital signal processors DSPs The PLL controller offers flexibility and convenience by way of software configurable multipliers and dividers to modify the input signal internally The resulting clock outputs are passed to the C645x DSP core peripherals and other modules inside the C645x DSP 5320 645 DSP 64 Bit Timer User s Guide This document provides an overview of the 64 bit timer in the C645x DSP The timer can be configured as a general purpose 64 bit timer dual general purpose 32 bit timers or a watchdog timer When configured as a dual 32 bit timers each half can operate in conjunction chain mode or independently unchained mode of each other TM
140. 5 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 6 Reset Controller The reset controller detects the different type of resets supported on the C6455 device and manages the distribution of those resets throughout the device The C6455 device has several types of resets power on reset warm reset max reset system reset and CPU reset Table 7 12 explains further the types of reset the reset initiator and the effects of each reset on the chip For more information on the effects of each reset on the PLL controllers and their clocks see Section 7 6 8 Reset Electrical Data Timing Table 7 12 Reset Types TYPE INITIATOR EFFECT s Power on Reset POR pin Resets the entire chip including the test and emulation logic RESET pi Resets everything except for the test and emulation logic and PLL2 Vest eset RESET Emulator stays alive during Warm Reset Max Reset RapidlO through INTDST5 Same as Warm Reset A system reset maintains memory contents and does not reset the System Reset Emulator test and emulation circuitry The device configuration pins are also not re latched and the state of the peripherals is also not affected 2 CPU Local Reset CPU local reset 1 INTDST5 is used generate MAX reset only It is not connected to the device interrupt controller For more detailed information on the INTDST5 see the 7
141. A 1000 1000 UNIT 1200 MIN MAX 3 twcknx Pulse duration CLKR X high or CLKR X low CLKR X int C 10 C 10 ns ta CKRH FRV Delay time CLKR high to internal FSR valid CLKR int 24 3 3 ns CLKX int 1 7 3 9 ta CKXH FXV Delay time CLKX high to internal FSX valid CLKX exi 17 9 ns 12 bey Disable time DX high impedance following CLKX int 3 9 4 iso D ANZ last data bit from CLKX high CLKX ext 21 9 i Delas tia CLKX int 3 9 D1 4 p20 MIR up CLKX ext 21 019 9 p28 7 Delay time FSX high to DX valid FSX int 234D19 5 6 0209 14 la FXH DXV ONLY applies when data ng 9 9 delay 0 XDATDLY 00b mode FSX ext he 9 D2 7 C HorL S sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period H CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even H CLKGDV 1 2 S if CLKGDV is odd L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit see 4 above 8 Extra delay from CLKX high to DX valid applies only to the first data bit of a device if and only if DXENA 1 in SPCR if DXENA 0 then D1 D2 0 if DXENA 1 then D1 6P D2 12P 9 Extra delay from FSX high to DX valid applies only to the first data bit of a
142. A SDLL bus devices 0 0 0 9 us Pulse duration SDA high between STOP and 8 tw SDAH START 4 7 1 3 us conditions 9 Rise time SDA 1000 20 0 1049 300 ns 10 tsen Rise time SCL 1000 20 0 10 300 ns 11 Fall time SDA 300 20 0 109 300 ns 12 Fall time SCL 300 20 0 109 300 ns Setup time SCL high before SDA high for 18 tsu scLH SDAH STOP condition 9 gh 4 0 6 us 14 tw SP Pulse duration spike must be suppressed 0 50 ns 15 C Capacitive load for each bus line 400 400 1 2 pins SDA SCL do not feature fail safe I O buffers These pins could potentially draw current when the device is powered down 2 Fast mode I C bus device can be used in a Standard mode I C bus system but the requirement tsu SDA SCLH 2250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line t max tsuspa scLH 1000 250 1250 ns according to the Standard mode I C Bus Specification before the SCL line is released 3 device must internally provide a hold time of at least 300 ns for the SDA signal referred to the Viymin of the SCL signal to bridge the undefined region of the falling edge of SCL The maximum trgpa scLL has only to be met if the device does not stretch th
143. Accelerated Stress Test HAST or biased 85 85 temperature cycle autoclave or unbiased HAST electromigration bond intermetallic life and mold compound life Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Parameters Endianess Little Endian Big Endian 64 Bit External Memory Interface EMIFA Glueless Interface to Asynchronous Memories SRAM Flash and EEPROM and Synchronous Memories SBSRAM ZBT SRAM Supports Interface to Standard Sync Devices and Custom Logic FPGA CPLD ASICs etc 32M Byte Total Addressable External Memory Space Four 1x Serial RapidlOG Links or One 4x v1 2 Compliant 1 25 2 5 3 125 Gbps Link Rates Message Passing DirectlO Support Error Management Extensions and Congestion Control IEEE 1149 6 Compliant I Os DDR2 Memory Controller Interfaces to DDR2 533 SDRAM 32 Bit 16 Bit 533 MHz data rate Bus 512M Byte Total Addressable External Memory Space Controller 64 Independent Channels 32 16 Bit Host Port Interface HPI 32 Bit 33 66 MHz 3 3 V Peripheral Component Interconnect PCI Master Slave Interface Conforms to PCI Local Bus Specification version 2 3 One Inter Integrated Circuit Bus Two McBSPs 10 100 1000 Mb s E
144. BER 2007 REVISED JANUARY 2008 Odd Even register register file A men A1 0 2 A5 A31 ARAS D STib 4 5 1 4 Data path LD1b LD1a Even Odd register register file B file B BO B2 B1 B3 4 30 B5 B31 LD2b Data path B ST2a lt ST2b 4 uni 051215 32 MSB B On M unit 051115 32 LSB C64x CPU M unit src2 is 32 bits C64x CPU M unit src2 is 64 bits D On Land S units odd dst connects to odd register files and even dst connects to even register files Figure 2 1 C64x CPU DSP Core Data Paths 14 Device Overview Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 23 Memory Map Summary SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 2 shows the memory map address ranges of the C6455 device The external memory configuration register address ranges in the C6455 device begin at the hex address location 0x7000 0000 for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller Table 2 2 C6455 Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE BYTES HEX ADDRESS RANGE Reserved 1024K 0000 0000 000F FFFF Internal ROM 32K 0010 0000 0010 7FFF
145. C Reserved 02A3 0380 DFOPT2 Destination FIFO Options Register 2 02A3 0384 DFSRC2 Destination FIFO Source Address Register 2 02A3 0388 DFCNT2 Destination FIFO Count Register 2 02A3 038C DFDST2 Destination FIFO Destination Address Register 2 02A3 0390 DFBIDX2 Destination FIFO BIDX Register 2 02A3 0394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 02A3 0398 02A3 03BC Reserved 02A3 03C0 DFOPT3 Destination FIFO Options Register 3 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 121 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 7 8 EDMA3 Transfer Controller 2 Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 03C4 DFSRC3 Destination FIFO Source Address Register 3 02A3 03C8 DFCNT3 Destination FIFO Count Register 3 02A3 03CC DFDST3 Destination FIFO Destination Address Register 3 02A3 03D0 DFBIDX3 Destination FIFO BIDX Register 3 02A3 03D4 DFMPPRXY3 _ Destination FIFO Memory Protection Proxy Register 3 02A3 03D8 02A3 7FFF Reserved Table 7 9 EDMA3 Transfer Controller 3 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 8000 PID Peripheral Identification Register 02A3 8004 TCCFG
146. C RMII Input Receive for 100 Mbps see Figure 7 67 720 850 NO A 1000 1000 UNIT 1200 MIN MAX Setup time receive selected signals valid before MREFCLK at DSP 1 su MRXD MREFCLK p 4 0 ns high low 2 h MREFCLK MRXD Hold time receive selected signals valid after MREFCLK at DSP high low 2 0 ns 1 For RMII receive selected signals include MRXD 1 0 MRXER and MCRSDV pe k Input u k 2 et je 5 212 MRXD1 MRXD0 MCRSDV O AO SK MRXER Inputs Figure 7 67 EMAC Receive Interface Timing RMII Operation 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 49 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 14 3 3 EMAC RGMII Electrical Data Timing An extra clock signal RGREFCLK running at 125 MHz is included as a convenience to the user Note that this reference clock is not a free running clock This should only be used by an external device if it does not expect a valid clock during device reset Table 7 84 Switching Characteristics Over Recommended Operating Conditions for EMAC RGREFCLK RGMII Operation see Figure 7 68 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 1 Ic RGFCLK Cycle time RGREFCLK 8 0 8 8 0 8 ns 2 tw R
147. C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 7 103 PCI External Memory Space continued HEX ADDRESS OFFSET ACRONYM REGISTER NAME 4800 0000 487F FFFF PCI Master Window 16 4880 0000 48FF FFFF PCI Master Window 17 4900 0000 497F FFFF PCI Master Window 18 4980 0000 49FF FFFF PCI Master Window 19 4A00 0000 4A7F FFFF PCI Master Window 20 4 80 0000 4AFF FFFF PCI Master Window 21 4B00 0000 4B7F FFFF PCI Master Window 22 4B80 0000 4BFF FFFF PCI Master Window 23 4 00 0000 4C7F FFFF PCI Master Window 24 4 80 0000 4CFF FFFF PCI Master Window 25 4D00 0000 4D7F FFFF PCI Master Window 26 4D80 0000 4DFF FFFF PCI Master Window 27 4E00 0000 4E7F FFFF PCI Master Window 28 4E80 0000 4EFF FFFF PCI Master Window 29 4 00 0000 4F7F FFFF PCI Master Window 30 4 80 0000 4FFF FFFF PCI Master Window 31 228 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback R Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 18 3 PCI Electrical Data Timing Texas Instruments has performed the simulation and system characterization to ensure that the PCI peripheral mee
148. C8 0500 MACADDRLO matching 02 8 0504 MACADDRHI s ae High Bytes Register used in receive address 02C8 0508 MACINDEX MAC Index Register 02C8 050 02C8 05 Reserved 02C8 0600 TXOHDP Transmit Channel 0 DMA Head Descriptor Pointer Register 02C8 0604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register 02C8 0608 TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register 02C8 060C TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register 02C8 0610 TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register 02C8 0614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register 02C8 0618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register 02C8 061C TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register 02C8 0620 RXOHDP Receive Channel 0 DMA Head Descriptor Pointer Register 02C8 0624 RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register 02C8 0628 RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register 02C8 062C RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register 02C8 0630 RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register 02C8 0634 RX5HDP Receive Channel 5 DMA Head Descriptor Pointer Register 02C8 0638 RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register 02C8 063C RX7HDP Receive Channel 7 DMA Head Descriptor Pointer Register 02C8 0640 TXOCP RU Channel 0 Completion Pointer Interrupt Acknowledge 02C8 0644 TX1CP end Channel 1 Completion Pointer Interrupt Acknowledge
149. CESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 EDMA3 Channel Controller Events SLAVE MASTER Data SCR 128 SYSCLK2 64 SYSCLK2 128 SYSCLK2 5 2 128 SYSCLK2 128 EDMA3 Z SYSCLK2 64 SYSCLK2 ss 128 SYSCLK2 s 128 SYSCLK2 32 SYSCLK2 CFG 5 SCR 128 bit SYSCLK2 32 SYSCLK3 128 32 32 SYSCLK3 EMAC M SY SYSCLK3 SYSCLK3 S McBSPs 32 SYSCLK3 J a 32 SYSCLK3 e PPS HPI M Z 128 SYSCLK2 gt 5 ML _ 32 SYSCLK3 32 SYSCLK3 128 64 SYSCLK2 SYSCLK2 DDR2 Memory 32 32 Controller Serial RapidlO SYSCLK3 SYSCLK 128 64 Descriptor A Bridge j Z SYSCLK2 SYSCLK2 Serial RapidlO Perec 128 SYSCLK2 5 Megamodule Data 128 SYSCLK2 Megamodule M gt Configuration Bus Data Bus Figure 4 1 Switched Central Resource Block Diagram Submit Documentation Feedback System Interconnect 83 SM320C6455 EP 9 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 4 1 SCR Connection Matrix DDR2 MEMORY lt I m gt 1 PY Y Y EN uo j 5 1 Y Y Y Y 0
150. CPIC8 TCP2 Input Configuration Register 8 5000 0024 TCPIC9 TCP2 Input Configuration Register 9 5000 0028 TCPIC10 TCP2 Input Configuration Register 10 5000 002 TCPIC11 TCP2 Input Configuration Register 11 5000 0030 TCPIC12 TCP2 Input Configuration Register 12 5000 0034 TCPIC13 TCP2 Input Configuration Register 13 5000 0038 TCPIC14 TCP2 Input Configuration Register 14 5000 003C TCPIC15 TCP2 Input Configuration Register 15 5000 0040 TCPOUTO TCP2 Output Parameters Register 0 5000 0044 TCPOUT1 TCP2 Output Parameters Register 1 5000 0048 TCPOUTP2 TCP2 Output Parameters Register 2 5001 0000 N A X0 TCP2 Data Sys and Parity Memory 5003 0000 N A WO TCP2 Extrinsic Mem 0 5004 0000 N A wi TCP2 Extrinsic Mem 1 5005 0000 N A 10 2 Interleaver Memory 5006 0000 00 2 Output Decision Memory 5007 0000 N A S0 TCP2 Scratch Pad Memory 5008 0000 N A TO TCP2 Beta State Memory 5009 0000 N A co TCP2 CRC Memory 500A 0000 N A BO TCP2 Beta Prolog Memory 500B 0000 N A AO TCP2 Alpha Prolog Memory 02BA 0000 TCPPID TCP2 Peripheral Identification Register N A 02BA 004C TCPEXE TCP2 Execute Register N A 02BA 0050 TCPEND TCP2 Endianness Register N A 02BA 0060 TCPERR TCP2 Error Register N A 02BA 0068 TCPSTAT TCP2 Status Register N A 02BA 0070 TCPEMU TCP2 Emulation Register N A 02BA 005C 02BB FFFF Reserved 222 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas SM320C6455 EP INST
151. Clock Valid Clock Valid B SYSREFCLK of the PLL2 controller runs at CLKIN2 x10 SYSCLK1 of PLL2 controller runs at SYSREFCLK 2 default Power supplies CLKIN1 CLKIN2 if used and PCLK if used must be stable before the start of typor Do not tie the RESET and POR pins together The RESET pin can be brought high after the POR pin has been brought high In this case the RESET pin must be held low for a minimum of tymgsgr after the POR pin has been brought high moog Ww gt Figure 7 8 Power Up Timing 134 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 JVA JNAVAJNAVNMA AOAA NAVNVNAAV AVNA JANA JAAA JAVNA AAMVA AAN erkin NVAJNVJAVAJA NA JA A A JAVAVAVA VAVVAVAVNA AA AAA A VAAVA AVAA N k n r P H t nn s N n r L 6 RESET A B eee 9 RESETSTAT EE 7 8 Boot and m rrrp r Device Configuration Pins A RESET should only be used after device has been powered up For more details on the use of the RESET pin see Section 7 6 Reset Controller reset signal is generated internally during a Warm Reset This internal reset signal has the same effect as the RESET pin during a Warm Reset Boot and De
152. Configuration Register 02A3 8008 02A3 80FC Reserved 02A3 8100 TCSTAT Channel Status Register 02A3 8104 02A3 811C Reserved 02A3 8120 ERRSTAT Error Register 02A3 8124 ERREN Error Enable Register 02A3 8128 ERRCLR Error Clear Register 02A3 812C ERRDET Error Details Register 02A3 8130 ERRCMD Error Interrupt Command Register 02 8134 02A3 813C Reserved 02A3 8140 RDRATE Read Rate Register 02A3 8144 02A3 823C Reserved 02A3 8240 SAOPT Source Active Options Register 02A3 8244 SASRC Source Active Source Address Register 02A3 8248 SACNT Source Active Count Register 02A3 824C SADST Source Active Destination Address Register 02A3 8250 SABIDX Source Active Source B Index Register 02A3 8254 SAMPPRXY Source Active Memory Protection Proxy Register 02A3 8258 SACNTRLD Source Active Count Reload Register 02A3 825C SASRCBREF _ Source Active Source Address B Reference Register 02A3 8260 SADSTBREF Source Active Destination Address B Reference Register 02A3 8264 02A3 827C Reserved 02A3 8280 DFCNTRLD Destination FIFO Set Count Reload 02A3 8284 DFSRCBREF _ Destination FIFO Set Destination Address B Reference Register 02A3 8288 DFDSTBREF Destination FIFO Set Destination Address B Reference Register 02A3 828C 02A3 82FC Reserved 02A3 8300 DFOPTO Destination FIFO Options Register 0 02A3 8304 DFSRCO Destination FIFO Source Address Register 0 02A3 8308 DFCNTO Destination FIFO Count Register 0 02A3 830C DFDSTO Destination FIFO Destinat
153. DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 2 VCP2 GPIO McBSPs UTOPIA n lt r A e n n n lt lt lt n e n r f f A A A e r A amp amp amp amp amp amp amp n n n n n n n n e e e me n lt o r A n lt o r A e C 2 Oo Timers P EMAC MDIO U Controllers A Device Configuration s 32 SYSCLK2 32 32 SYSCLK2 Sy s 32 eoa 32 32 SYSCLK2 Sy YSCLK2 K2 S EDMA3 TC2 Registers Serial RapidlO SYSCLK2 5 EDMA3 EDMAS TCO Figure 4 2 C64x Megamodule SCR Connection Submit Documentation Feedback System Interconnect 85 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 uk 4 4 Bus Priorities On the C6455 device bus priority is programmable for each master The register bit fields and default priority levels for C6455 bus masters are shown in Table 4 2 The priority levels should be tuned to obtain the best system performance for a particular application Lower values indicate higher priorities For some masters the priority values are programmed at the system level by configuring the PRI ALLOC register Details on the PRI ALLOC register are shown in Figure 4 3 The C64x megamodu
154. DS2 AED 63 0 AECLKIN AARDY AHOLD AEA 22 3 ACE 3 0 ABE 7 0 AECLKOUT ASDCKE AHOLDA ABUSREQ GP 15 12 2 1 ASADS ASRE AAOE ASOE AAWE ASWE ED 31 0 DEA 21 2 DCE 1 0 DBE 3 0 DDRCLK DDRCLK DSDCKE DDQS DDQS DSDCAS DSDRAS DSDWE CLKIN1 PLLV1 PLL1 PLL2 and PLL1 and PLL2 CLKIN2 PLLV2 SYSCLK4 Controller Controller McBSP1 TINP1L TOUTIL CLKRO FSRO DRO CLKSO TINPO FSX0 CLKXO TIMERO TOUTO MRXD 7 0 MRXER MRXDV MCOL MCRS MTCLK MRCLK RIOCLK RIOCLK RIOTX 3 0 RIOTX 3 0 RIORX 3 0 RIORX 3 0 RapidlO SCL SDA MTXD 7 0 MTXEN MDIO MDCLK Shading denotes a peripheral module not available for this configuration DEVSTAT Register 0x0061 8161 PCI EN 0 PCI disabled default 1 EMIFA EN 1 EMIFA enabled ABA0 DDR2 EN 1 DDR2 Memory Controller enabled AEA 19 16 BOOTMODE 3 0 0001 HPI Boot AEA 8 PCI EEAI 0 PCI I2C EEPROM Auto Init disabled default AEA 15 AECLKIN SEL 0 AECLKIN default AEA 7 0 do not oppose IPD AEA 14 HPl WIDTH 1 HPI 32 bit Operation AEA 6 PCI66 0 PCI 33 MHz default don t care AEA 13 LENDIAN 7 IPU Little Endian Mode default AEA 5 MCBSP1 EN 0 McBSP1 disabled default AEA 12 UTOPIA EN 0 UTOPIA disabled default AEA 4 SYSCLKOUT EN 1 SYSCLKA pin function AEA 11 1 must oppose IPD AEA 3 1 must oppose IPD AEA 10 9 MACSEL 1 0 0
155. DV PCI EN Y ss DD33 RSV43 RSV42 RSV44 ASGE W DVppi2 Vss DVpp12 Vss DVpp33 Vss ARW ACE3 ACE2 RSV41 ABE7 W ABA1 ABA0 V DV V DV ACES ACE4 AECLKOUT V ss DDRM ss DD ss DD33 EMIFA EN DDR2 EN AEAS AEAO AEA1 AEA6 U DV V V DV V Rsv20 U DDRM ss DD ss DD33 ss CFGGP0 CFGGP1 PCI66 S 2 T Vss CVpp Vss CVpp Vss AEA11 AEA3 sYySCLKOUT T CFGGP2 _EN AEA14 ASADS AEA13 AEA12 R cv V V DV V _ pace AHOLD R 95 99 8s Win ASRE LENDIAN UTOPIA EN 16 17 18 19 20 21 22 23 24 25 26 272 29 0 29 MM MM Figure 2 3 C6455 Pin Map Bottom View Quadrant B Submit Documentation Feedback Device Overview 21 SM320C6455 EP 79 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 16 17 18 19 20 21 22 ee 8 amp __26 _ _ 27 28 29 AEA16 AEA15 P AEA8 P Vss CVpp Vss CVop RSV30 RSV31 BOOT AECLKIN DVpps3 Vss MODEO _SEL AEA19 N CVpp Vss CVpp Vss Vss DVpp33 BOOT AHOLDA AEA7 CLKIN1 AECLKIN N MODE3 AEA10 AEA9 M V cv V M SS CVpp Vss DD DVpp33 55 MACSEL1 Vss MACSELO DVpp33 Vss AEA17 AEA18 L CVpp Vss CVpp Vss Vss DVppss BOOT BOOT ABUSREQ ABE4 ABES L MODE1 MODE2 i DVpp33 Vss AED33 ABE6 AED32 AED34 AARDY K J Vss
156. ED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 www ti com Table 2 3 Terminal Functions continued SIGNAL TYPE IPD APU DESCRIPTION NAME NO DSDDQS3 E23 VO Z DSDDQS2 E20 VO Z DDR2 Memory Controller data strobe 3 0 positive DSDDQS1 E8 VO Z DSDDQSO E11 VO Z DSDDQS3 D23 VO Z DDR2 data strobe 3 0 negative DSDDQS2 Hen unc Note These pins are used to meet AC timings For more detailed information DSDDQS1 D8 VO Z see the Implementing DDR2 PCB Layout on the TMS320C6455 application DSDD 0 D11 VO Z report literature number PRAAA 7 DDR2 MEMORY CONTROLLER 32 BIT ADDRESS DEA13 B15 DEA12 A15 DEA11 A16 DEA10 B16 DEA9 C16 DEA8 D16 DEA7 B17 O Z DDR2 Memory Controller external address DEA6 C17 DEA5 D17 DEA4 E17 DEA3 A18 DEA2 B18 DEA1 C18 DEA0 D18 38 Device Overview Submit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE iPD IPU 2 DESCRIPTION NAME NO DDR2 MEMORY CONTROLLER 32 BIT DATA DED31 B25 DED30 A25 DED29 B24 DED28 A24 DED27 D22 DED26 C22 DED25 B22 DED24 A22 DED23 D21 DED22 C21 DED21
157. EL 0 AECLKIN default AEA 14 WIDTH 1 HPI 32 bit Operation AEA 13 LENDIAN IPU Little Endian Mode default AEA 12 UTOPIA EN 0 UTOPIA disabled default AEA 11 1 must oppose IPD AEA 10 9 MACSEL 1 0 00 10 100 MII Mode Figure 3 13 Configuration Example B 2 McBSPs 2 I2C EMIFA DDR2 Memory Controller TIMERS RapidlO EMAC GMII MDIO AEA 8 PCI EEAI 0 PCI I2C EEPROM Auto Init disabled default AEA 7 0 do not oppose IPD AEA 6 PCI66 0 PCI 33 MHz default don t care AEA 5 MCBSP1 EN 1 McBSP1 enabled AEA 4 SYSCLKOUT EN 1 SYSCLKA pin function AEA 3 1 must oppose IPD AEA 2 0 CFGGP 2 0 000 default 80 Device Configuration Submit Documentation Feedback Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR 4 1 www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 System Interconnect On the C6455 device the C64x Megamodule the EDMAS transfer controllers and the system peripherals are interconnected through two switch fabrics The switch fabrics allow for low latency concurrent data transfers between master peripherals and slave peripherals Through a switch fabric the CPU can send data to the Viterbi co processor VCP2 without affecting a data transfer between the PCI and the DDR2 memory controller The switch fabrics also allow for seamless arbitration between the system masters when accessi
158. EMIFA pins when RESETSTAT is low NOTE If a configuration pin must be routed out from the device and 3 stated not driven the internal pullup pulldown IPU IPD resistor should not be relied upon TI recommends the use of an external pullup pulldown resistor For more detailed information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see Section 3 7 Pullup Pulldown Resistors Table 3 1 C6455 Device Configuration Pins AEA 19 0 ABA 1 0 and PCI EN CONFIGURATION IPD PIN NO Ipu FUNCTIONAL DESCRIPTION Boot Mode Selections BOOTMODE 3 0 These pins select the boot mode for the device 0000 No boot default mode 0001 Host boot HPI 0010 Reserved 0011 Reserved N25 0100 EMIFA 8 bit ROM boot AEA 19 16 IPD 0101 Master 12C boot P26 0110 Slave 2 boot 0111 Host boot PCI 1000 thru Serial Rapid I O boot configurations 1111 If selected for boot the corresponding peripheral is automatically enabled after device reset For more detailed information on boot modes see Section 2 4 Boot Sequence CFGGP 2 0 pins must be set to 000b during reset for proper operation of the PCI boot mode EMIFA input clock source select AECLKIN SEL 0 AECLKIN default mode 15 Par IPD 1 SYSCLK4 CPU x Clock Rate The SYSCLK4 clock rate is software selectable via the Software PLL1 Controller By default SYSCLK4 is selected as CPU 8 clock rate 1 IPD
159. EN Block Enable 4 02D0 005C RIO BLK4 EN STAT Block Enable Status 4 02D0 0060 RIO BLK5 EN Block Enable 5 02D0 0064 RIO BLK5 EN STAT Block Enable Status 5 0200 0068 RIO BLK6 EN Block Enable 6 0200 006C RIO BLK6 EN STAT Block Enable Status 6 02D0 0070 RIO BLK7 EN Block Enable 7 02D0 0074 RIO BLK7 EN STAT Block Enable Status 7 02D0 0078 RIO BLK8 EN Block Enable 8 0200 007C RIO BLK8 EN STAT Block Enable Status 8 02D0 0080 RIO DEVICEID REG RapidlO DEVICEID1 Register 02D0 0084 RIO DEVICEID REG2 RapidlO DEVICEID2 Register 0200 0088 0200 008C Reserved 02D0 0090 RIO PF 16B CNTLO Packet Forwarding Register 0 for 16 bit Device IDs 0200 0094 RIO PF 8B CNTLO Packet Forwarding Register 0 for 8 bit Device IDs 02D0 0098 RIO PF 16B CNTL1 Packet Forwarding Register 1 for 16 bit Device IDs 02D0 009C RIO PF 8B CNTL1 Packet Forwarding Register 1 for 8 bit Device IDs 0200 00A0 RIO PF 16B ONTL2 Packet Forwarding Register 2 for 16 bit Device IDs 02D0 00A4 RIO PF 8B CNTL2 Packet Forwarding Register 2 for 8 bit Device IDs 02D0 00A8 RIO PF 16B CNTL3 Packet Forwarding Register 3 for 16 bit Device IDs 02D0 00AC RIO PF 8B Packet Forwarding Register 3 for 8 bit Device IDs 0200 00B0 0200 00FC Reserved 02D0 0100 RIO SERDES CFGRX0 CNTL SERDES Receive Channel Configuration Register 0 02D0 0104 RIO SERDES CFGRX1 CNTL SERDES Receive Channel Configuration Register 1 02D0 0108 RIO SERDES CFGRX2 CNTL SERDES Receive Channel Configuration Register 2 0200 010C RIO SERDES CFG
160. F in Figure 7 23 PLL2 Block Diagram Revision History Submit Documentation Feedback 39 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 8 Mechanical Data 8 1 Thermal Data Table 8 1 shows the thermal resistance characteristics for the PBGA ZTZ GTZ mechanical package Table 8 1 Thermal Resistance Characteristics S PBGA Package ZTZ GTZ NO C W 1 Junction to case 1 45 N A 2 Junction to board 8 34 N A 3 16 1 0 00 4 13 0 1 0 ROJA Junction to free air 19 20 6 10 7 3 0 0 37 0 00 7 Junction to package top ae 1 01 1 5 1 17 3 00 7 6 0 00 6 7 1 0 8 Junction to board 6 4 1 5 5 8 3 00 1 m s meters per second 8 2 Packaging Information The following packaging information reflects the most current released data available for the designated device s This data is subject to change without notice and without revision of this document Submit Documentation Feedback Mechanical Data 251 TEXAS PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 22 Jan 2008 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty SM320C6455BGTZEP ACTIVE FCBGA GTZ 697 44 TBD SNPB Level 4 220C 72 HR SM320C6455BGTZSEP ACTIVE FCBGA GTZ 697 4
161. FFF 0184 833C MAR207 Controls EMIFA CE4 Range CF00 0000 CFFF FFFF 0184 8340 MAR208 Controls EMIFA CE5 Range D000 0000 D0FF FFFF 0184 8344 MAR209 Controls EMIFA CE5 Range D100 0000 D1FF FFFF 0184 8348 MAR210 Controls EMIFA CE5 Range D200 0000 D2FF FFFF 0184 834 MAR211 Controls EMIFA CE5 Range D300 0000 D3FF FFFF 0184 8350 MAR212 Controls EMIFA CE5 Range D400 0000 D4FF FFFF 96 C64x Megamodule Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 5 8 Megamodule Cache Configuration Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 8354 MAR213 Controls EMIFA CES Range 0500 0000 D5FF FFFF 0184 8358 MAR214 Controls EMIFA CES Range D600 0000 D6FF FFFF 0184 835C MAR215 Controls EMIFA CES Range 0700 0000 D7FF FFFF 0184 8360 MAR216 Controls EMIFA CES Range 0800 0000 D8FF FFFF 0184 8364 MAR217 Controls EMIFA CES Range 0900 0000 D9FF FFFF 0184 8368 MAR218 Controls EMIFA CES Range DA00 0000 DAFF FFFF 0184 836C MAR219 Controls EMIFA CES Range 0000 DBFF FFFF 0184 8370 MAR220 Controls EMIFA CES Range 0000 DCFF FFFF 0184 8374 MAR221 Controls EMIFA 5 Range DD00 0000 DDFF FFFF 0184 8378 MAR222 Controls EMIFA CES Range DE00 0000 DEFF FFFF 0184 837C MAR223
162. GFCLKH Pulse duration RGREFCLK high 3 2 4 8 ns 3 tw RGFCLKL Pulse duration RGREFCLK low 3 2 4 8 ns 4 tRGFCLK Transition time RGREFCLK 0 75 ns 1 4 Output k 3 4 3 le Figure 7 68 RGREFCLK Timing Table 7 85 Timing Requirements for RXC RGMII Operation see Figure 7 69 720 850 NO A 1000 1000 UNIT 1200 MIN MAX 10 Mbps 360 440 1 te RXC Cycle time RXC 100 Mbps 36 44 ns 1000 Mbps 7 2 8 8 10 Mbps 0 40 tyRxc 0 60 te RxC 2 tw RXCH Pulse duration RXC high 100 Mbps 0 40 tyRxc 0 60 ns 1000 Mbps O 45 tenxc 0 55 lt 10 Mbps 0 40 tyRxc 0 60 3 tw RXCL Pulse duration RXC low 100 Mbps 0 40 tyRxc 0 60 ns 1000 Mbps 0 45 tyrxc 0 55 lt 10 Mbps 0 75 4 Transition time 100 Mbps 0 75 ns 1000 Mbps 0 75 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 213 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 86 Timing Requirements for EMAC RGMII Input Receive for 10 100 1000 Mbps see Figure 7 69 720 850 NO A 1000 1000 UNIT 1200 MIN MAX tsu RXD RXCH Setup time receive selected signals valid before RXC at DSP high low 1 0 ns th RXCH RXD Hold time receive selected signals valid after RXC at DSP high low 1 0 ns 1 For RGMII receive selected sig
163. GTXD2 c3 RGMII transmit data 3 0 O This pin is available only when RGMII mode is RGTXD1 B3 selected MACSEL 1 0 11 RGTXDO A3 RGMII transmit enable O This pin is available only when RGMII mode is RGTXOTL D3 0 2 selected MACSEL 1 0 11 RGMII receive clock I This pin is available only when RGMII mode is selected RGRXO s MACSELI1 0 11 RGRXD3 C1 RGRXD2 E4 RGMII receive data 3 0 I This pin is available only when RGMII mode is RGRXD1 E2 selected MACSEL 1 0 11 RGRXDO E1 l RGMII receive control I This pin is available only when RGMII mode is RGRXCTL Ge selected MACSELI1 0 11 RESERVED FOR TEST RSV02 V5 RSV03 W3 Reserved These pins must be connected directly to core supply CVpp for RSV04 N11 proper device operation RSV05 P11 RSV07 G4 Reserved These pins must be connected directly to 1 5 1 8 V I O supply DVpp45 for proper device operation RSV09 D26 NOTE If the EMAC RGMII is not used these pins be connected directly to ground Vss Reserved This pin must be connected to ground Vss via a 200 Q resistor for proper device operation NOTE If the DDR2 Memory Controller is not used the Vrersst_ RSV11 and RSV11 D24 RSV12 pins can be connected directly to ground Vss to save power However connecting these pins directly to ground will prevent boundary scan from functioning on the DDR2 Memory Controller pins To preserve boundary scan functionality on the DDR2 Memory Controller pins
164. Gbytes sec The DDR2 bus is designed to sustain a maximum throughput of up to 2 1 Gbytes sec at a 533 MHz data rate 267 MHz clock rate as long as data requests are pending in the DDR2 Memory Controller DDR2 Memory Controller Device Specific Information The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces such as EMIF HPI and McBSP For these other interfaces the device timing was specified in terms of data manual specifications and buffer information specification IBIS models For the C6455 DDR2 memory bus the approach is to specify compatible DDR2 devices and provide the printed circuit board PCB solution and guidelines directly to the user Texas Instruments has performed the simulation and system characterization to ensure all DDR2 interface timings in this solution are met The complete DDR2 system solution is documented in the mplementing DDR2 PCB Layout on the TMS320C6455 application report literature number SPRAAA7 only supports designs that follow the board design guidelines outlined in the SPRAAA7 application report The DDR2 Memory Controller pins must be enabled by setting the DDR2 EN configuration pin ABAO high during device reset For more details see Section 3 1 Device Configuration at Device Reset The ODT 1 0 pins of the memory controller must be left unconnected The ODT pins on the DDR2 memory device s must be connected to ground The DD
165. I Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Clocks and Timers www ti com clocks Digital Control www ti com digitalcontrol Interface
166. I mode RGMDIO I O ETHERNET MAC EMAC MII RMII GMII If the Ethernet EMAC and MDIO are enabled AEA12 driven low UTOPIA_EN 0 there are two additional configuration pins the MAC_SEL 1 0 AEA 10 9 pins that select one of the four interface modes MII RMII or RGMII for the EMAC MDIO interface For more detailed information on the EMAC configuration pins see Section 3 Device Configuration UTOPIA receive clock URCLK driven by Master ATM Controller I or when the UTOPIA peripheral is disabled UTOPIA_EN AEA12 pin 0 this pin is URGLK MRELK i EMAC receive clock MRCLK for MII default or GMI MACSEL 1 0 dependent UTOPIA receive cell available status output signal from UTOPIA Slave O or URCLAV MCRS J4 VO Z when the UTOPIA peripheral is disabled UTOPIA EN AEA12 pin 0 this RMCRSDV pin is EMAC carrier sense MCRS I for MII default or GMII or EMAC carrier sense receive data valid RMCRSDV I for RMII MACSEL 1 0 dependent UTOPIA receive Start of Cell signal I or when the UTOPIA peripheral is 0 H4 disabled UTOPIA_EN AEA12 pin 0 this pin is EMAC receive error MRXIR 1 for MII default RMII or GMII MACSEL 1 0 dependent UTOPIA receive interface enable input signal 1 Asserted by the Master Controller to indicate to the UTOPIA Slave to sample the Receive Data Bus URDATA 7 0 and URSOC signal in the next clock cycle or therea
167. IO_QUEUE4_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 4 02D0 0514 RIO_QUEUE5_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 5 02D0 0518 RIO_QUEUE6_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 6 02D0 051C RIO_QUEUE7_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 7 02D0 0520 RIO_QUEUE8_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 8 02D0 0524 RIO_QUEUE9_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 9 02D0 0528 RIO_QUEUE10_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 10 02D0 052C RIO QUEUE11 TXDMA HDP Queue Transmit DMA Head Descriptor Pointer Register 11 02D0 0530 RIO QUEUE12 TXDMA HDP Queue Transmit DMA Head Descriptor Pointer Register 12 02D0 0534 RIO QUEUE13 TXDMA HDP Queue Transmit DMA Head Descriptor Pointer Register 13 02D0 0538 RIO QUEUE14 TXDMA HDP Queue Transmit DMA Head Descriptor Pointer Register 14 02D0 053C RIO QUEUE15 TXDMA HDP Queue Transmit DMA Head Descriptor Pointer Register 15 02D0 0540 0200 057C Reserved 02D0 0580 RIO QUEUEO TXDMA CP Queue Transmit DMA Completion Pointer Register 0 02D0 0584 RIO QUEUE1 TXDMA CP Queue Transmit DMA Completion Pointer Register 1 02D0 0588 RIO QUEUE2 TXDMA CP Queue Transmit DMA Completion Pointer Register 2 02D0 058C RIO QUEUES8 TXDMA CP Queue Transmit DMA Completion Pointer Register 3 02D0 0590 RIO QUEUE4 TXDMA CP Queue Transmit DMA Completion Pointer Register 4 02D0 0594 RIO QUEUE5 TXDMA CP Qu
168. IVIDER D3 A 6 SYSCLK3 DIVIDER D4 12 14 SYSCLK4 16 Internal Clock Input PLLDIV4 15 ENA DIVIDER D5 6 H gt SYSCLK 2 18 5 D5EN PLLDIV5 15 ENA Emulation and Trace Lllcl l lILlllllll lI LI IIl N AECLKIN External EMIF Clock Input 12 CLKDIV CTRL 18 16D N 1 AECLKINSELN 1_0 sySCLKOUT_EN AEA 15 pin 4 pin EMIF Input Clock EMIFA gt AECLKOUT GP1 SYSCLK4 A DIVIDER D2 and DIVIDER D3 are always enabled B CLKIN1 is a 3 3 V signal Figure 7 10 PLL1 and PLL1 Controller 7 7 1 PLL1 Controller Device Specific Information 7 7 1 1 Internal Clocks and Maximum Operating Frequencies As shown in Figure 7 10 the PLL1 controller generates several internal clocks including the system reference clock SYSREFCLK and the system clocks SYSCLK2 3 4 5 The high frequency clock signal SYSREFCLK is directly used to clock the C64x megamodule including the CPU and also serves as a reference clock for the rest of the DSP system Dividers D2 D3 D4 and D5 divide the high frequency clock SYSREFCLK to generate SYSCLK2 SYSCLK3 SYSCLK4 and SYSCLKS5 respectively The system clocks are used to clock different portions of the DSP e SYSCLK is used to clock the switched central resources SCRs VCP2 TCP2 and RapidlO as well as the data bus interfaces of the EMIFA and DDR2 Memory C
169. Invalidate Base Address Register 0184 4034 L1DWIWC L1D Writeback and Invalidate Word Count Register 0184 4038 Reserved 0184 4040 L1DWBAR L1D Writeback Base Address Register for Block Writebacks 0184 4044 L1DWWC L1D Writeback Word Count Register 0184 4048 L1DIBAR L1D Invalidate Base Address Register 0184 404C L1DIWC L1D Invalidate Word Count Register 0184 4050 0184 4FFF Reserved 0184 5000 L2WB L2 Global Writeback Register 0184 5004 L2WBINV L2 Global Writeback and Invalidate Register 0184 5008 L2INV L2 Global Invalidate Register 0184 500C 0184 5024 Reserved 0184 5028 L1PINV L1P Global Invalidate Register 0184 502C 0184 503C Reserved 0184 5040 L1DWB L1D Global Writeback Register 0184 5044 L1DWBINV L1D Global Writeback and Invalidate Register 0184 5048 L1DINV L1D Global Invalidate Register 0184 8000 0184 81FC MARIO Reserved 0184 8200 0184 823C 12810 Reserved 0184 8240 0184 827C Reserved 0184 8280 MAR160 Controls EMIFA CE2 Range A000 0000 A0FF FFFF 0184 8284 MAR161 Controls EMIFA CE2 Range A100 0000 A1FF FFFF 0184 8288 MAR162 Controls EMIFA CE2 Range A200 0000 A2FF FFFF 0184 828 MAR163 Controls EMIFA CE2 Range A300 0000 A3FF FFFF 0184 8290 MAR164 Controls EMIFA CE2 Range A400 0000 A4FF FFFF 0184 8294 MAR165 Controls EMIFA CE2 Range A500 0000 A5FF FFFF Submit Documentation Feedback C64x Megamodule 95 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com S
170. LKOUT low 1 8 ns 1 EMIF input clock AECLKIN or SYSCLKA period in ns for EMIFA 2 The reference points for the rise and fall transitions are measured at Vo and Vor MIN 3 EHis the high period of E EMIF input clock period in ns and EL is the low period of E EMIF input clock period in ns for EMIFA X f NX NL o NM 1 gt 1 1 6 3 5 5 2 4 5 4 4 AECLKOUT1 Figure 7 32 AECLKOUT Timing for the EMIFA Module 7 10 3 1 Asynchronous Memory Timing Table 7 44 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module 1 0 see Figure 7 33 and Figure 7 34 720 850 NO A 1000 1000 UNIT 1200 MIN MAX 3 tsu EDV AOEH Setup time AEDx valid before AAOE high 6 5 ns 4 th AOEH EDV Hold time AEDx valid after AAOE high 0 ns 5 tsu ARDY EKOH Setup time AARDY valid before AECLKOUT low 1 ns 6 th EKOH ARDY Hold time AARDY valid after AECLKOUT low 2 ns 7 tw ARDY Pulse width AARDY assertion and deassertion 2E 5 ns 8 t Delay time from AARDY sampled deasserted on AECLKOUT falling to 4E hs d ARDY HOLD beginning of programmed hold period 9 Setup time before end of programmed strobe period by which AARDY 2E Su ARDY HOLD should be asserted in order to insert extended strobe wait states 1 AECLKOUT period in ns for EMIFA 2 To ensure data setup time sim
171. LOW MASKS3 Transmit CPPI Supported Flow Mask Register 3 02D0 0714 RIO TX CPPI FLOW MASKS4 Transmit CPPI Supported Flow Mask Register 4 02D0 0718 RIO TX CPPI FLOW MASKS5 Transmit CPPI Supported Flow Mask Register 5 02D0 071C RIO TX CPPI FLOW MASKS6 Transmit CPPI Supported Flow Mask Register 6 02D0 0720 RIO TX CPPI FLOW MASKS7 Transmit CPPI Supported Flow Mask Register 7 02D0 0724 02DO 073C Reserved 02D0 0740 RIO RX QUEUE TEAR DOWN Receive Queue Teardown Register 02D0 0744 RIO RX CPPI CNTL Receive CPPI Control Register 0200 0748 0200 07DC Reserved 02D0 07EO RIO TX QUEUE CNTLO Transmit CPPI Weighted Round Robin Control Register 0 02D0 07E4 RIO TX QUEUE ONTL1 Transmit CPPI Weighted Round Robin Control Register 1 02D0 07E8 RIO TX QUEUE CNTL2 Transmit CPPI Weighted Round Robin Control Register 2 02D0 07EC RIO TX QUEUE CNTL3 Transmit CPPI Weighted Round Robin Control Register 3 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 239 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 112 RapidIO Control Registers continued 6 INSTRUMENTS www ti com HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 07F0 02D0 07FC Reserved 02D0 0800 RIO_RXU_MAP_LO Mailbox to Queue Mapping Register LO 02D0 0804 RIO RXU MAP HO Mailbox to Queue Mapping Register HO 02D0 0808 RIO RXU MAP L1 Mail
172. M register defines the input reference clock frequency multiplier in conjunction with the PLL divider ratio bits RATIO in the PLL controller pre divider register PREDIV 31 16 Reserved R 0 15 5 4 0 Reserved PLLM R 0 R W 0h LEGEND R W Read Write R Read only n value after reset Figure 7 12 PLL Multiplier Control Register PLLM Hex Address 029A 0110 Table 7 20 PLL Multiplier Control Register PLLM Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 PLLM PLL multiplier bits Defines the frequency multiplier of the input reference clock in conjunction with the PLL divider ratio bits RATIO in PREDIV Oh x1 multiplier rate Eh x15 multiplier rate 13h x20 multiplier rate 18h x25 multiplier rate 1Dh x30 multiplier rate 1Fh x32 multiplier rate Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 141 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 7 3 3 PLL Pre Divider Control Register 31 The PLL pre divider control register PREDIV is shown in Figure 7 13 and described in Table 7 21 16 R 0 15 14 5 i 2 R W 1 R 0 RIW 2h LEGEND R W Read Write R Read only n value after reset Figure 7 13
173. MS320C645x DSP Serial Rapid I O User s Guide literature number SPRU976 2 On the C6455 device peripherals can be in one of several states These states are listed in Table 3 4 7 6 1 Power on Reset POR Pin Power on Reset is initiated by the POR pin and is used to reset the entire chip including the test and emulation logic Power on Reset is also referred to as a cold reset since the device usually goes through a power up cycle During power up the POR pin must be asserted driven low until the power supplies have reached their normal operating conditions Note that a device power up cycle is not required to initiate a Power on Reset The following sequence must be followed during a Power on Reset 1 Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted driven low While POR is asserted all pins are set to high impedance After the POR pin is deasserted driven high all Z group pins low group pins and high group pins are set to their reset state and remain at their reset state until the otherwise configured by their respective peripheral All peripherals except those selected for boot purposes are disabled after a Power on Reset and must be enabled through the Device State Control registers for more details see Section 3 3 Peripheral Selection After Device Reset 2 Once all the power supplies are within valid operating conditions the POR pin must remain asserted low for a min
174. O Set Destination Address B Reference Register 02A2 828C 02A2 82FC Reserved 02A2 8300 DFOPTO Destination FIFO Options Register 0 02A2 8304 DFSRCO Destination FIFO Source Address Register 0 02A2 8308 DFCNTO Destination FIFO Count Register 0 02A2 830C DFDSTO Destination FIFO Destination Address Register 0 02A2 8310 DFBIDXO Destination FIFO BIDX Register 0 02A2 8314 DFMPPRXYO Destination FIFO Memory Protection Proxy Register 0 02A2 8318 02A2 833C Reserved 02A2 8340 DFOPT1 Destination FIFO Options Register 1 02A2 8344 DFSRC1 Destination FIFO Source Address Register 1 02A2 8348 DFCNT1 Destination FIFO Count Register 1 02A2 834C DFDST1 Destination FIFO Destination Address Register 1 02A2 8350 DFBIDX1 Destination FIFO BIDX Register 1 02A2 8354 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1 02A2 8358 02A2 837C Reserved 02A2 8380 DFOPT2 Destination FIFO Options Register 2 02A2 8384 DFSRC2 Destination FIFO Source Address Register 2 02A2 8388 DFCNT2 Destination FIFO Count Register 2 02A2 838C DFDST2 Destination FIFO Destination Address Register 2 02A2 8390 DFBIDX2 Destination FIFO BIDX Register 2 02A2 8394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 02A2 8398 02A2 83BC Reserved 02A2 83C0 DFOPT3 Destination FIFO Options Register 3 02 2 83 4 DFSRC3 Destination FIFO Source Address Register 3 02A2 83C8 DFCNT3 Destination FIFO Count Register 3 02A2 83CC DFDST3 Destination FIFO Destination Address
175. OINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 64 Timing Requirements for McBSP as SPI Master or Slave CLKSTP 11b CLKXP 00 see Figure 7 55 720 850 A 1000 1000 NO 1200 UNIT MASTER SLAVE MIN MAX MIN MAX tsu DRV CKXH Setup time DR valid before CLKX high 12 2 18 ns th CKXH DRV Hold time DR valid after CLKX high 4 5 36P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 Table 7 65 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave CLKSTP 11b CLKXP 0 see Figure 7 55 720 850 A 1000 1000 NO PARAMETER 1200 UNIT MASTER SLAVE MIN MAX MIN MAX 1 thiCKXL FXL Hold time FSX low after CLKX low 4 L 2 L 3 ns 2 td EXL CKXH Delay time FSX low to CLKX high T 2 T 3 ns 3 la CKXL DXV Delay time CLKX low to DX valid 2 4 18P 2 8 17 ns Disable time DX high impedance following E 6 as CKXLDXHZ last data bit from CLKX low 2 1 7 la FXL DXV Delay time FSX low to DX valid H 2 H 4 12P 2 24P 17 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 For all SPI Slave modes CLKG is programmed as 1 6 of the C
176. OPIA Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02B4 0000 UCR UTOPIA Control Register 02B4 0004 Reserved 02B4 0008 Reserved 02B4 000C Reserved 02B4 0010 5 Reserved 02 4 0014 CDR Clock Detect Register 02B4 0018 EIER Error Interrupt Enable Register 02B4 001G EIPR Error Interrupt Pending Register 02B4 0020 02B4 01FF Reserved 02B4 0200 02B7 FFFF Reserved Table 7 105 UTOPIA Data Queues Receive and Transmit Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 3C00 0000 3C00 03FF URQ UTOPIA Receive Rx Data Queue 3C00 0400 3C00 07FF UXQ UTOPIA Transmit Tx Data Queue 230 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 19 3 UTOPIA Electrical Data Timing Table 7 106 Timing Requirements for UXCLK see Figure 7 74 720 850 NO A 1000 1000 UNIT 1200 MIN MAX 1 te uxck Cycle time UXCLK 20 2 tw UXCKH Pulse duration UXCLK high O 4tctuxck 0 ns 3 wUXCKL Pulse duration UXCLK low O 4tc Uxck 0 6tyuxck 4 tyuxck Transition time UXCLK 2 n amp 1 The reference points for the rise and fall transitions are measured at Vi MAX and Vi MIN w pe x i ke 3 u 4 gt le Figure 7 74 UXCLK
177. PIA peripheral its state also affects the operation of the UTOPIA Table 3 3 describes the effect of the UTOPIA EN PCI EN and MACSEL 1 0 configuration pins Table 3 3 UTOPIA EN and MAC SEL 1 0 Peripheral Selection UTOPIA and EMAC CONFIGURATION PIN SETTING PERIPHERAL FUNCTION SELECTED MAC SEL 1 0 UTOPIA EN PCI EN PIN T A AEA 10 9 PINS EMAC MDIO UTOPIA AEA12 PIN R28 Y29 M25 M27 10 100 EMAC MDIO with MII Interface 0 x 00b default Disabled 10 100 EMAC MDIO with RMII 0 x 01b Interface Disabled 10 100 1000 EMAC MDIO with GMII 0 x 10b I terface Disabled 10 100 1000 EMAC MDIO with RGMII 0 x 11b Interface Disabled 1 0 00b 01b or 10b Disabled UTOPIA Slave with Full Functionality 10 100 1000 EMAC MDIO with RGMII 2 1 0 11b Interface UTOPIA Slave with Full Functionality 1 1 00b 01b or 10b Disabled il Slave with Single PHY Mode 1 1 11b 10 100 1000 EMAC MDIO with RGMII UTOPIA Slave with Single PHY Mode Interface Only 1 RGMII interface requires 1 5 1 8 V I O supply 62 Device Configuration Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 3 3 Peripheral Selection After Device Reset On the C6455 device peripherals can be in one of several states These states are listed in Table 3 4 Table 3 4 Peripheral States SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUAR
178. PIA peripheral is disabled UTOPIA_EN AEA12 pin 0 these UXDATA1 MTXD1 14 pins function as EMAC transmit data pins MTXD x 0 O for RMII or RMTXD1 MACSEL 1 0 dependent UXDATAO MTXDO M1 RMTXDO Submit Documentation Feedback Device Overview 43 SM320C6455 EP R3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE iPD IPU 2 DESCRIPTION NAME NO ETHERNET MAC EMAC RGMII If the Ethernet MAC EMAC and MDIO are enabled AEA12 driven low UTOPIA EN 0 there are two additional configuration pins the MAC SEL 1 0 AEA 10 9 pins that select one of the four interface modes MII RMII GMII or RGMII for the EMAC MDIO interface For more detailed information on the EMAC configuration pins see Section 3 Device Configuration RGMII reference clock O This 125 MHz reference clock is provided as a convenience It can be used as a clock source to a PHY so that the PHY may RGREFCLK C4 O Z generate RXC clock to communicate with the EMAC This clock is stopped while the device is in reset This is available only when RGMII mode is selected MACSEL 1 0 211 RGMII transmit clock O This pin is available only when RGMII mode is RGTXC D4 Oz selected MACSEL 1 0 11 RGTXD3 A2 R
179. PRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 5 8 Megamodule Cache Configuration Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 8298 MAR166 Controls EMIFA CE2 Range A600 0000 A6FF FFFF 0184 829C MAR167 Controls EMIFA CE2 Range A700 0000 A7FF FFFF 0184 82A0 MAR168 Controls EMIFA CE2 Range A800 0000 ABFF FFFF 0184 82A4 MAR169 Controls EMIFA CE2 Range A900 0000 A9FF FFFF 0184 82A8 MAR170 Controls EMIFA 2 Range AA00 0000 AAFF FFFF 0184 82AC MAR171 Controls EMIFA 2 Range AB00 0000 ABFF FFFF 0184 82B0 MAR172 Controls EMIFA 2 Range AC00 0000 ACFF FFFF 0184 82B4 MAR173 Controls EMIFA 2 Range AD00 0000 ADFF FFFF 0184 82B8 MAR174 Controls EMIFA CE2 Range AE00 0000 AEFF FFFF 0184 82BC MAR175 Controls EMIFA CE2 Range AF00 0000 AFFF FFFF 0184 82 0 MAR176 Controls Range 000 0000 BOFF FFFF 0184 82C4 MAR177 Controls EMIFA CE3 Range B100 0000 B1FF FFFF 0184 82C8 MAR178 Controls EMIFA CE3 Range B200 0000 B2FF FFFF 0184 82CC MAR179 Controls EMIFA CE3 Range B300 0000 B3FF FFFF 0184 82D0 MAR180 Controls EMIFA CE3 Range B400 0000 B4FF FFFF 0184 82D4 MAR181 Controls EMIFA CE3 Range B500 0000 B5FF FFFF 0184 82D8 MAR182 Controls EMIFA CE3 Range B600 0000 B6FF FFFF 0184 82DC MAR183 Controls EMIFA CE3 Range B700 0000 B7FF FFFF
180. PU clock by setting CLKSM CLKGDV 1 3 S Sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P clks if CLKSM 0 P clks period T CLKX period 1 CLKGDV S H CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even H CLKGDV 1 2 S if CLKGDV is odd L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd 4 FSRP FSXP 1 As SPI Master FSX is inverted to provide active low slave enable output As a Slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master McBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP 5 FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock CLKX CLKX j LS VS 1 le 2 FSX J 4 4 5 5 DR Bit X 2 X GEE X mQ X1 Figure 7 55 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 0 v Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 197 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 66 Timing Requirements for McBSP SPI Master or Slave CLKSTP 10b CLKXP 10 see Figure 7 56
181. P_L21 Mailbox to Queue Mapping Register L21 02D0 08AC RIO_RXU_MAP_H21 Mailbox to Queue Mapping Register H21 02D0 08 0 RIO_RXU_MAP_L22 Mailbox to Queue Mapping Register L22 02D0 08B4 RIO_RXU_MAP_H22 Mailbox to Queue Mapping Register H22 240 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 112 RapidIO Control Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 08B8 RIO_RXU_MAP_L23 Mailbox to Queue Mapping Register L23 02D0 08BG RIO_RXU_MAP_H23 Mailbox to Queue Mapping Register H23 02D0 08C0 RIO_RXU_MAP_L24 Mailbox to Queue Mapping Register L24 02D0 08C4 RIO_RXU_MAP_H24 Mailbox to Queue Mapping Register H24 02D0 08C8 RIO_RXU_MAP_L25 Mailbox to Queue Mapping Register L25 02D0 08CC RIO_RXU_MAP_H25 Mailbox to Queue Mapping Register H25 0200 0800 RIO RXU 126 Mailbox to Queue Mapping Register L26 02D0 08D4 RIO RXU H26 Mailbox to Queue Mapping Register H26 02D0 08D8 RIO RXU MAP L27 Mailbox to Queue Mapping Register L27 0200 08DC RIO RXU MAP H27 Mailbox to Queue Mapping Register H27 02D0 08E0 RIO_RXU_MAP_L28 Mailbox to Queue Mapping Register L28 02D0 08E4 RIO RXU H
182. Queue Mapping Register L11 02D0 085C RIO_RXU_MAP_H11 Mailbox to Queue Mapping Register H11 02D0 0860 RIO_RXU_MAP_L12 Mailbox to Queue Mapping Register L12 02D0 0864 RIO_RXU_MAP_H12 Mailbox to Queue Mapping Register H12 02D0 0868 RIO_RXU_MAP_L13 Mailbox to Queue Mapping Register L13 02D0 086C RIO_RXU_MAP_H13 Mailbox to Queue Mapping Register H13 02D0 0870 RIO_RXU_MAP_L14 Mailbox to Queue Mapping Register L14 02D0 0874 RIO_RXU_MAP_H14 Mailbox to Queue Mapping Register H14 02D0 0878 RIO_RXU_MAP_L15 Mailbox to Queue Mapping Register L15 02D0 087C RIO RXU MAP H15 Mailbox to Queue Mapping Register H15 02D0 0880 RIO RXU MAP L16 Mailbox to Queue Mapping Register L16 02D0 0884 RIO RXU MAP H16 Mailbox to Queue Mapping Register H16 02D0 0888 RIO RXU MAP L17 Mailbox to Queue Mapping Register L17 02D0 088C RIO RXU MAP H17 Mailbox to Queue Mapping Register H17 02D0 0890 RIO_RXU_MAP_L18 Mailbox to Queue Mapping Register L18 02D0 0894 RIO_RXU_MAP_H18 Mailbox to Queue Mapping Register H18 02D0 0898 RIO_RXU_MAP_L19 Mailbox to Queue Mapping Register L19 02D0 089C RIO_RXU_MAP_H19 Mailbox to Queue Mapping Register H19 02D0 08A0 RIO_RXU_MAP_L20 Mailbox to Queue Mapping Register L20 02D0 08A4 RIO_RXU_MAP_H20 Mailbox to Queue Mapping Register H20 02D0 08A8 RIO_RXU_MA
183. R L2 memory protection fault command register 0184 A00C 0184 A0FF Reserved 0184 A100 L2MPLKO L2 memory protection lock key bits 31 0 0184 A104 L2MPLK1 L2 memory protection lock key bits 63 32 0184 A108 L2MPLK2 L2 memory protection lock key bits 95 64 0184 A10C L2MPLK3 L2 memory protection lock key bits 127 96 0184 A110 L2MPLKCMD 12 memory protection lock key command register 0184 A114 L2MPLKSTAT 12 memory protection lock key status register 0184 A118 0184 A1FF Reserved 0184 A200 L2MPPAO L2 memory protection page attribute register 0 0184 A204 L2MPPA1 L2 memory protection page attribute register 1 0184 A208 L2MPPA2 L2 memory protection page attribute register 2 0184 A20C L2MPPAS3 L2 memory protection page attribute register 3 Submit Documentation Feedback C64x4 Megamodule 97 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 5 9 Megamodule L1 L2 Memory Protection Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 A210 L2MPPA4 L2 memory protection page attribute register 4 0184 A214 L2MPPA5 L2 memory protection page attribute register 5 0184 A218 L2MPPA6 L2 memory protection page attribute register 6 0184 A21C L2MPPA7 L2 memory protection page attribute register
184. R2 memory controller on the C6455 device supports the following memory topologies e A 32 bit wide configuration interfacing to two 16 bit wide DDR2 SDRAM devices A 16 bit wide configuration interfacing to a single 16 bit wide DDR2 SDRAM device A race condition may exist when certain masters write data to the DDR2 memory controller For example if master A passes a software message via a buffer in external memory and does not wait for indication that the write completes when master B attempts to read the software message then the master B read may bypass the master A write and thus master B may read stale data and therefore receive an incorrect message Some master peripherals e g EDMAS transfer controllers will always wait for the write to complete before signaling an interrupt to the system thus avoiding this race condition For masters that do not have hardware guarantee of write read ordering it may be necessary to guarantee data ordering via software If master A does not wait for indication that a write is complete it must perform the following workaround 1 Perform the required write 2 Perform a dummy write to the DDR2 memory controller module ID and revision register 3 Perform a dummy read to the DDR2 memory controller module ID and revision register 4 Indicate to master B that the data is ready to be read after completion of the read in step 3 The completion of the read in step 3 ensures that the previous write
185. RAES QDMA Region Access Enable Register for Region 3 02A0 0390 02A0 039C Reserved 02 0 0400 QOEO Event Queue 0 Entry Register 0 02A0 0404 QOE1 Event Queue 0 Entry Register 1 02A0 0408 QOE2 Event Queue 0 Entry Register 2 02A0 040C QOES3 Event Queue 0 Entry Register 3 02A0 0410 QOE4 Event Queue 0 Entry Register 4 02A0 0414 QOE5 Event Queue 0 Entry Register 5 02 0 0418 QOE6 Event Queue 0 Entry Register 6 02A0 041C QOE7 Event Queue 0 Entry Register 7 02 0 0420 QOE8 Event Queue 0 Entry Register 8 02 0 0424 Q0E9 Event Queue 0 Entry Register 9 02A0 0428 Q0E10 Event Queue 0 Entry Register 10 02 0 042 Q0E11 Event Queue 0 Entry Register 11 02A0 0430 Q0E12 Event Queue 0 Entry Register 12 02A0 0434 Q0E13 Event Queue 0 Entry Register 13 02A0 0438 Q0E14 Event Queue 0 Entry Register 14 02A0 043 Q0E15 Event Queue 0 Entry Register 15 02A0 0440 Q1E0 Event Queue 1 Entry Register 0 02A0 0444 Q1E1 Event Queue 1 Entry Register 1 02A0 0448 Q1E2 Event Queue 1 Entry Register 2 02A0 044 Q1E3 Event Queue 1 Entry Register 3 02A0 0450 Q1E4 Event Queue 1 Entry Register 4 02A0 0454 Q1E5 Event Queue 1 Entry Register 5 02A0 0458 Q1E6 Event Queue 1 Entry Register 6 02A0 045G Q1E7 Event Queue 1 Entry Register 7 02A0 0460 Q1E8 Event Queue 1 Entry Register 8 02A0 0464 Q1E9 Event Queue 1 Entry Register 9 02A0 0468 Q1E10 Event Queue 1 Entry Register 10 02 0 046 Q1E11 Event Queue 1 Entry Register 11 02A0 0470 Q1E12 Event Queue 1 Entry Register 12 02A0 0474 Q1E13 Eve
186. RESS RANGE ACRONYM REGISTER NAME COMMENTS 0298 0000 Reserved 0298 0004 EMUMGT_CLKSPD1 Timer 1 Emulation Management Clock Speed Register 0298 0008 i Reserved 0298 000 5 Reserved 0298 0010 CNTLO1 Timer 1 Counter Register Low 0298 0014 CNTHI1 Timer 1 Counter Register High 0298 0018 PRDLO1 Timer 1 Period Register Low 0298 001 PRDHI1 Timer 1 Period Register High 0298 0020 TCR1 Timer 1 Control Register 0298 0024 TGCR1 Timer 1 Global Control Register 0298 0028 WDTCR1 Timer 1 Watchdog Timer Control Register 0298 002 Reserved 0298 0030 i Reserved 0298 0034 0299 FFFF Reserved 218 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 15 3 Timers Electrical Data Timing Table 7 94 Timing Requirements for Timer Inputs see Figure 7 73 720 850 NO A 1000 1000 UNIT 1200 MIN MAX lw TINPH Pulse duration TINPLx high 12P ns 2 lw TINPL Pulse duration TINPLx low 12P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use 1 ns Table 7 95 Switching Characteristics Over Recommended Operating Conditions for Timer Outputs see Figure 7 73 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 3 tw TOUTH Pulse duration TOUTLx high 12P 3
187. RIO_SP2_ERR_CAPT_DBG2 Port 2 Packet Control Symbol Error Capture CSR 2 02D0 20D4 RIO_SP2_ERR_CAPT_DBG3 Port 2 Packet Control Symbol Error Capture CSR 3 02D0 20D8 RIO_SP2_ERR_CAPT_DBG4 Port 2 Packet Control Symbol Error Capture CSR 4 02D0 20DC 02D0 20E4 Reserved 02D0 20E8 RIO_SP2_ERR_RATE Port 2 Error Rate CSR 02D0 20EC RIO_SP2_ERR_THRESH Port 2 Error Rate Threshold CSR 02D0 20F0 02D0 20FC Reserved 02D0 2100 RIO_SP3_ERR_DET Port 3 Error Detect CSR 02D0 2104 RIO_SP3_RATE_EN Port 3 Error Enable CSR 02D0 2108 RIO_SP3_ERR_ATTR_CAPT_DBGO Port Attributes Error Capture CSR 0 02D0 210C RIO SP3 ERR CAPT DBG1 Port 3 Packet Control Symbol Error Capture CSR 1 02D0 2110 RIO SP3 ERR CAPT DBG2 Port 3 Packet Control Symbol Error Capture CSR 2 02D0 2114 RIO SP3 ERR CAPT DBG3 Port 3 Packet Control Symbol Error Capture CSR 3 0200 2118 RIO SP3 ERR CAPT DBG4 Port 3 Packet Control Symbol Error Capture CSR 4 02D0 211C 02D0 2124 Reserved 02D0 2128 RIO SP3 ERR RATE Port 3 Error Rate CSR 02D0 212C RIO SP3 ERR THRESH Port 3 Error Rate Threshold CSR Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 243 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 7 112 RapidlO Control Registers continued
188. RIPTION NAME NO EMIFA 64 BIT DATA AED63 F25 AED62 A27 AED61 C27 AED60 C28 AED59 E27 AED58 D28 AED57 D27 AED56 F27 AED55 G25 AED54 G26 AED53 A28 AED52 F28 AED51 B28 50 G27 AED49 B27 AED48 G28 AED47 H25 AED46 J26 AED45 H26 AED44 J27 AED43 H27 VO Z IPU EMIFA external data AED42 J28 AED41 29 AED40 J29 AED39 D29 AED38 J25 AED37 F29 AED36 F26 AED35 G29 AED34 K28 AED33 K25 AED32 K27 AED31 AA27 AED30 AG29 AED29 AB29 AED28 AC27 AED27 AB28 AED26 AC26 AED25 AB27 AED24 25 AED23 AB26 AED22 AD28 36 Device Overview Submit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE iPD IPU O DESCRIPTION NAME NO AED21 AD29 AED20 AJ28 AED19 AF29 AED18 AH28 AED17 AE29 AED16 AG28 AED15 AF28 AED14 AH26 AED13 AE28 AED12 AE26 AED11 AD26 AED10 AF27 VO Z IPU EMIFA external data 9 AG27 AED8 AD27 AED7 AE25 AED6 AJ27 AED5 AJ26 AED4 27 AED3 AG25 AED2 AH27 AED1 AF25 AEDO AD25 DDR2 MEMORY C ONTROLLER 32 BIT CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY DDR2 Memory Controller memory space enable When the DDR2 Memory DCE0 Fla 0 2 Controller is enabled it always keeps this
189. ROM provided the PCI peripheral pins are enabled PCI EN 1 Note If the PCI pin function is disabled PCI EN pin 0 this pin must not be pulled up AEA7 N27 IPD For proper C6455 device operation do not oppose the IPD on this pin PCI Frequency Selection PCI66 Selects the operating frequency of the PCI either 33 MHz or 66 MHz AEA6 U27 IPD 0 PCI operates at 33 MHz default 1 PCI operates at 66 MHz Note If the PCI pin function is disabled pin 0 this pin must not be pulled up McBSP1 pin function enable bit MCBSP1 EN Selects which function is enabled on the McBSP1 GPIO multiplexed pins 0 GPIO pin function enabled default HER IB This means all multiplexed McBSP1 GPIO pins function as GPIO pins 1 McBSP1 pin function enabled This means all multiplexed McBSP1 GPIO pins function as McBSP1 pins 60 Device Configuration Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 3 1 C6455 Device Configuration Pins AEA 19 0 ABA 1 0 and continued eR gage FUNCTIONAL DESCRIPTION SYSCLKOUT Enable bit SYSCLKOUT_EN Selects which function is enabled on the SYSCLK4 GP 1 muxed pin PE 0 GP 1 pin function is enabled default 1 SYSCLKA pin function is enabled For proper C6455 device operation the AEA3 pin must be pulled up at dev
190. RUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 18 Peripheral Component Interconnect PCI The C6455 DSP supports connections to a PCI backplane via the integrated PCI master slave bus interface The PCI port interfaces to DSP internal resources via the data switched central resource The data switched central resource is described in more detail in Section 4 For more detailed information on the PCI port peripheral module see the TMS320C645x DSP Peripheral Component Interconnect PCI User s Guide literature number SPRUE60 7 18 1 PCI Device Specific Information The PCI peripheral on the C6455 DSP conforms to the PCI Local Bus Specification version 2 3 The PCI peripheral can act both as a PCI bus master and as a target It supports PCI bus operation of speeds up to 66 MHz and uses a 32 bit data address bus On the C6455 device the pins of the PCI peripheral are multiplexed with the pins of the HPI UTOPIA and GPIO peripherals PCI functionality for these pins is controlled enabled disabled by the PCI_EN pin 29 The maximum speed of the PCI 33 MHz or 66 MHz is controlled through the PCI66 027 For more detailed information on the peripheral control see Section 3 Device Configuration The C6455 device provides an initialization mechanism through which the default values for some of the PCI configuration registers can be read from an 2 EEPROM Table 7 98 shows
191. RX3 CNTL SERDES Receive Channel Configuration Register 3 02D0 0110 RIO SERDES CFGTXO CNTL SERDES Transmit Channel Configuration Register 0 02D0 0114 RIO SERDES CFGTX1 CNTL SERDES Transmit Channel Configuration Register 1 0200 0118 RIO SERDES CFGTX2 CNTL SERDES Transmit Channel Configuration Register 2 02D0 011C RIO SERDES CFGTX3 CNTL SERDES Transmit Channel Configuration Register 3 02D0 0120 RIO SERDES CFGO CNTL SERDES Macro Configuration Register 0 02D0 0124 RIO SERDES CFG1 CNTL SERDES Macro Configuration Register 1 02D0 0128 RIO SERDES CFG2 CNTL SERDES Macro Configuration Register 2 02D0 012C RIO SERDES CFG3 CNTL SERDES Macro Configuration Register 3 0200 0130 0200 01FC Reserved 02D0 0200 RIO_DOORBELLO_ICSR DOORBELL Interrupt Condition Status Register 0 02D0 0204 Reserved 02D0 0208 RIO_DOORBELLO_ICCR DOORBELL Interrupt Condition Clear Register 0 02D0 020C Reserved 02D0 0210 RIO_DOORBELL1_ICSR DOORBELL Interrupt Condition Status Register 1 02D0 0214 Reserved 02D0 0218 RIO_DOORBELL1_ICCR DOORBELL Interrupt Condition Clear Register 1 02D0 021C Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 235 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 7 112 RapidlO Control Registers continued
192. RapidIO Control Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 0610 RIO _QUEUE4_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 4 02D0 0614 RIO_QUEUE5 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 5 02D0 0618 RIO QUEUE6 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 6 02D0 061C RIO QUEUE7 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 7 0200 0620 RIO QUEUE8 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 8 02D0 0624 RIO QUEUE9 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 9 02D0 0628 RIO QUEUE10 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 10 02D0 062C RIO QUEUE11 RXDMA Queue Receive DMA Head Descriptor Pointer Register 11 02D0 0630 RIO QUEUE12 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 12 02D0 0634 RIO QUEUE13 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 13 02D0 0638 RIO QUEUE14 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 14 02D0 063C RIO QUEUE15 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 15 02D0 0640 0200 067C Reserved 0200 0680 RIO QUEUEO RXDMA CP Queue Receive DMA Completion Pointer Register 0 02D0 0684 RIO QUEUE1 RXDMA CP Queue Receive DMA Completion Pointe
193. Register 2 02A0 0818 Memory Protection Page Attribute Register 3 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 115 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 7 4 EDMA3 Channel Controller Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 081C MPPA4 Memory Protection Page Attribute Register 4 02A0 0820 MPPA5 Memory Protection Page Attribute Register 5 02A0 0824 MPPA6 Memory Protection Page Attribute Register 6 02A0 0828 MPPA7 Memory Protection Page Attribute Register 7 02A0 082C 02A0 OFFC Reserved 02A0 1000 ER Event Register 02A0 1004 ERH Event Register High 02A0 1008 ECR Event Clear Register 02A0 100C ECRH Event Clear Register High 02A0 1010 ESR Event Set Register 02A0 1014 ESRH Event Set Register High 02A0 1018 CER Chained Event Register 02A0 101C CERH Chained Event Register High 02A0 1020 EER Event Enable Register 02A0 1024 EERH Event Enable Register High 02A0 1028 EECR Event Enable Clear Register 02A0 102C EECRH Event Enable Clear Register High 02A0 1030 EESR Event Enable Set Register 02A0 1034 EESRH Event Enable Set Register High 02A0 1038 SER Secondary Event Register 02A0 103C SERH Secondary Ev
194. Register 3 0180 0090 0180 009C 5 Reserved 0180 00A0 MEVTFLAGO Masked Event Flag Status Register 0 Events 31 0 0180 00A4 MEVTFLAG1 Masked Event Flag Status Register 1 0180 00A8 MEVTFLAG2 Masked Event Flag Status Register 2 0180 00AG MEVTFLAG3 Masked Event Flag Status Register 0180 00B0 0180 00BC Reserved 0180 00C0 EXPMASKO Exception Mask Register 0 Events 31 0 0180 00C4 EXPMASK1 Exception Mask Register 1 0180 00C8 EXPMASK2 Exception Mask Register 2 0180 00CC EXPMASK3 Exception Mask Register 3 0180 00D0 0180 00DC Reserved 0180 00E0 MEXPFLAGO Masked Exception Flag Register 0 0180 00E4 MEXPFLAG1 Masked Exception Flag Register 1 0180 00 8 MEXPFLAG2 Masked Exception Flag Register 2 0180 00 MEXPFLAGS Masked Exception Flag Register 0180 00F0 0180 00FG Reserved 0180 0100 z Reserved 0180 0104 INTMUX1 Interrupt Multiplexor Register 1 0180 0108 INTMUX2 Interrupt Multiplexor Register 2 0180 010C INTMUX3 Interrupt Multiplexor Register 3 0180 0110 0180 013C Reserved 0180 0140 AEGMUXO Advanced Event Generator Mux Register 0 0180 0144 AEGMUX1 Advanced Event Generator Mux Register 1 0180 0148 0180 017C Reserved 0180 0180 INTXSTAT Interrupt Exception Status Register 0180 0184 INTXCLR Interrupt Exception Clear Register Submit Documentation Feedback C64x Megamodule 93 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMEN
195. S320C645x DSP Turbo Decoder Coprocessor TCP User s Guide Channel decoding of high bit rate data channels found in third generation 3G cellular standards requires decoding of turbo encoded data The turbo decoder coprocessor TCP in some of the digital Submit Documentation Feedback Device Overview 57 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 58 SPRUE48 SPRU972 Device Overview 3 TEXAS www ti com signal processor DSPs of the C6000 DSP family has been designed to perform this operation for IS2000 and 3GPP wireless standards This document describes the operation and programming of the TCP TMS320C645x DSP Universal Test amp Operations PHY Interface for ATM 2 UTOPIA2 User s Guide This document describes the universal test and operations PHY interface for asynchronous transfer mode ATM 2 UTOPIA2 in the C645x digital signal processors DSPs of the C6000 DSP family TMS320C645x DSP Viterbi Decoder Coprocessor VCP User s Guide Channel decoding of voice and low bit rate data channels found in third generation 3G cellular standards requires decoding of convolutional encoded data The Viterbi decoder coprocessor 2 VCP2 provided in C645x devices has been designed to perform Viterbi Decoding for 152000 and 3GPP wireless standards The VCP2 coprocessor has been designed to perform forward error correction for 2G and 3G wireless systems The
196. SEPTEMBER 2007 REVISED JANUARY 2008 Static Powerdown Enable In Progress Disabled Enabled Figure 3 1 Peripheral Transitions Between States Figure 3 2 shows the flow needed to change the state of a given peripheral on the C6455 device Unlock the PERCFGO register by using the PERLOCK register Write to the PERCFGO register within 16 SYSCLK3 clock cycles to change the state of the peripherals Poll the PERSTAT registers to verify state change Figure 3 2 Peripheral State Change Flow A 32 bit key value 0x0F0A 0B00 must be written to the Peripheral Lock register PERLOCK in order to allow access to the PERCFGO register Writes to the PERCFG1 register can be done directly without going through the PERLOCK register NOTE The instructions that write to the PERLOCK and PERCFGO registers must be in the same fetch packet if code is being executed from external memory If the instructions are in different fetch packets fetching the second instruction from external memory may stall the instruction long enough such that PERCFGO register will be locked before the instruction is executed 64 Device Configuration Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 3 4 Device State Control Registers The C6455 device has a set of registers that are used to control the status of its peripher
197. SOE and AAWE ASWE 3 All pending EMIF transactions are allowed to complete before HOLDA is asserted If no bus transactions are occurring then the minimum delay time can be achieved External Requestor Owns Bus DSP Owns Bus le 3 DSP Owns Bus e 1 PC EMIF Bus D A Bus consists of ACE 5 2 ABE 7 0 AED 63 0 AEA 19 0 ABA 1 0 ARAV ASADS ASRE AAOE ASOE and AAWE ASWE Figure 7 39 HOLD HOLDA Timing for EMIFA Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 171 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 10 5 BUSREQ Timing 6 INSTRUMENTS www ti com Table 7 50 Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module see Figure 7 40 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 1 td AEKOH ABUSRV Delay time AECLKOUT high to ABUSREQ valid 1 5 5 ns AECLKOUTx fF S 4 oe ABUSREQ Y Figure 7 40 BUSREQ Timing for EMIFA 172 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 11 12C Peripheral The inter integrated circuit
198. SSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 only supports designs that follow the board design guidelines outlined in the SPRAAA8 application report Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 245 SM320C6455 EP 79 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 21 General Purpose Input Output GPIO 7 21 1 GPIO Device Specific Information On the C6455 the GPIO peripheral pins GP 15 8 and GP 3 0 are muxed with the UTOPIA PCI and McBSP1 peripheral pins and the SYSCLKA signal For more detailed information on device peripheral configuration and the C6455 device pin muxing see Section 3 Device Configuration 7 21 2 GPIO Peripheral Register Description s Table 7 113 GPIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02B0 0008 BINTEN GPIO interrupt per bank enable register 02B0 000C Reserved 02B0 0010 DIR GPIO Direction Register 02B0 0014 OUT DATA GPIO Output Data register 02B0 0018 SET DATA GPIO Set Data register 02 0 001C CLR DATA GPIO Clear Data Register 02B0 0020 IN DATA GPIO Input Data Register 02B0 0024 SET RIS TRIG GPIO Set Rising Edge Interrupt Register 02B0 0028 CLR RIS TRIG GPIO Clear Rising Edge Interrupt Register 02B0 002C SET FAL TRIG GPIO Set Falling Edge Interrupt Register 02B0 0030 CLR FAL TRIG GPIO Clear Falling Edge Inter
199. STROBE low 5 ns 17 tsu HDV HSTBH Setup time host data valid before HSTROBE high 5 ns 18 th HSTBH HDV Hold time host data valid after HSTROBE high 1 ns 37 tsu HCSL HSTBL Setup time HCS low before HSTROBE low 0 ns Hold time HSTROBE low after HRDY low HSTROBE should not be 38 th HRDYL HSTBL inactivated until HRDY is active low otherwise HPI writes will not 1 1 ns complete properly 1 HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS 2 M SYSCLK3 period 6 CPU clock frequency in ns For example when running parts at 1000 MHz use M 6 ns 3 Select signals include 1 0 and HR W For 16 mode only select signals also include HHWIL 180 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 56 Switching Characteristics for Host Port Interface Cycles see Table 7 56 through Figure 7 51 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX Case 1 HPIC or HPIA read 5 15 Case 2 HPID read with no 9 M 20 auto increment Delay time HSTROBE low to Case 3 HPID read with auto increment i 1 DSP data valid and read FIFO initially empty ote S Case 4 HPID read with auto increment an
200. SYSREFCLK by 10 such that SYSCLK4 and hence the EMIF internal clock runs at 100 MHz All hosts HPI PCI etc must hold off accesses to the DSP while the frequency of its internal clocks is changing A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed Note that there is a minimum and maximum operating frequency for PLLREF PLLOUT SYSCLK4 and SYSCLK5 The PLL1 Controller must not be configured to exceed any of these constraints certain combinations of external clock input internal dividers and PLL multiply ratios might not be supported For the PLL clocks input and output frequency ranges see Table 7 16 Table 7 16 PLL1 Clock Frequency Ranges CLOCK SIGNAL MIN MAX UNIT CLKIN1 66 6 MHz PLLREF PLLEN 1 33 3 66 6 MHz PLLOUT 400 1200 MHz SYSCLK4 25 166 MHz SYSCLK5 333 MHz 1 Only applies when the PLL1 Controller is set to PLL mode PLLEN 1 in the PLLCTL register 7 7 1 2 PLL1 Controller Operating Modes The PLL1 controller has two modes of operation bypass mode and PLL mode The mode of operation is determined by the PLLEN bit of the PLL control register PLLCTL In PLL mode SYSREFCLK is generated from the device input clock CLKIN1 using the divider PREDIV and the PLL multiplier PLLM In bypass mode CLKIN1 is fed directly to SYSREFCLK All hosts HPI PCI etc must hold off accesses to the DSP while the frequency of its internal
201. Serial Port Maintenance Block Header 0200 1104 02DO 1118 02D0 1120 RIO SP LT CTL Port Link Time Out Control CSR 0200 1124 RIO SP RT CTL Port Response Time Out Control CSR 02D0 1128 0200 1138 Reserved 02D0 113C RIO SP GEN CTL Port General Control CSR 0200 1140 RIO SPO LM REQ Port 0 Link Maintenance Request CSR 02DO 1144 RIO SPO LM RERIO SP Port 0 Link Maintenance Response CSR 02D0 1148 RIO SPO ACKID STAT Port 0 Local Acknowledge ID Status CSR 02D0 114C 0200 1154 Reserved 02D0 1158 RIO SPO ERR STAT Port 0 Error and Status CSR 02D0 115C RIO SPO CTL Port 0 Control CSR 0200 1160 RIO SP1 LM REQ Port 1 Link Maintenance Request CSR 02D0 1164 RIO SP1 LM RERIO SP Port 1 Link Maintenance Response CSR 02D0 1168 RIO SP1 ACKID STAT Port 1 Local Acknowledge ID Status CSR 02D0 116C 02DO 1174 Reserved 0200 1178 RIO SP1 ERR STAT Port 1 Error and Status CSR 02D0 117C RIO SP1 CTL Port 1 Control CSR 02D0 1180 RIO SP2 LM REQ Port 2 Link Maintenance Request CSR 02D0 1184 RIO SP2 LM RERIO SP Port 2 Link Maintenance Response CSR 02D0 1188 RIO SP2 ACKID STAT Port 2 Local Acknowledge ID Status CSR 0200 118C 0200 1194 Reserved 02D0 1198 RIO SP2 ERR STAT Port 2 Error and Status CSR 02D0 119C RIO SP2 CTL Port 2 Control CSR 02DO 11A0 RIO SP3 LM REQ Port 3 Link Maintenance Request CSR 02D0 11A4 RIO SP3 LM RERIO SP Port 3 Link Maintenance Response CSR 02D0 11A8 RIO SP3 ACKID STAT Port 3 Local Acknowledge ID Status CSR 02D0 11AC 0200 11B4 Reserved 02D0 1
202. TA7 MTXD7 URDATA6 MRXD6 UXDATA6 MTXD6 URDATA5 MRXD5 NNNM UXDATA5 MTXD5 URDATA4 MRXD4 EN 2 as UXDATA4 MTXD4 URDATAS MRXD3 Receive Transmit UXDATA3 MTXD3 URDATA2 MRXD2 H4 UXDATA2 MTXD2 URDATA1 MRXD1 RMRXD1 mw NEN UXDATA1 MTXD1 RMTXD1 URDATAO MRXDO RMRXDO i UXDATAO MTXDO RMTXDO URENB MRXDV UXENB MTXEN RMTXEN URADDR4 PCLK GP 2 UXADDR4 GMDCLK URADDR3 PREQ GP 15 BE O UXADDR3 GMDIO URADDR2IPINTATGP 14 Control Status Control Status 5 UXADDR2 PCBES URADDR1 PRST GP 13 EN UXADDR1 PIDSEL URADDRO PGNT GP 12 UXADDRO PTRDY URCLAV MCRS RMCRSDV UXCLAV GMTCLK URSOC MRXER RMRXER B N UXSOC MCOL TCLKRISE URCLK MRCLK UXCLK MTCLK REFCLK A These UTOPIA pins are muxed with the PCI or EMAC or GPIO peripherals By default these signals function as GPIO or EMAC peripheral pins or have no function For more details on these muxed pins see the Device Configuration section of this data sheet Figure 2 11 UTOPIA Peripheral Signals HD 15 0 AD 15 0 HD 31 16 AD 31 16 HHWIL PCLK Data Address UXADDR1 PIDSEL HCNTL1 PDEVSEL UXADDR2 PCBE3 HINT PFRAME HR W PCBE2 Command URADDR2 PINTA GP 14 Enable Control 1 UXADDR4 PCBE0 GP 2 HRDY PIRDY HCNTLO PSTOP UXADDRO PTRDY SRADDROPGNT GPI Arbitration HDS1 PSERR URADDR3 PREQ GP 15 HCS PPERR PCI Interface A A These PCI pins are mu
203. TAQ test port data in TCK AJ9 IPU JTAQ test port clock TRST 1 PD U compatibilty statement portion of the document S EMUO AF7 VO Z IPU Emulation pin 0 EMU1 9 AE11 VO Z IPU Emulation pin 1 EMU2 AG9 VO Z IPU Emulation pin 2 EMU3 AF10 VO Z IPU Emulation pin 3 EMU4 AF9 VO Z IPU Emulation pin 4 EMU5 AE12 VO Z IPU Emulation pin 5 EMU6 AG8 VO Z IPU Emulation pin 6 EMU7 AF12 VO Z IPU Emulation pin 7 EMU8 AF11 VO Z IPU Emulation pin 8 EMU9 AH13 VO Z IPU Emulation pin 9 EMU10 AD10 VO Z IPU Emulation pin 10 EMU11 AD12 VO Z IPU Emulation pin 11 EMU12 AE10 VO Z IPU Emulation pin 12 EMU13 AD8 VO Z IPU Emulation pin 13 EMU14 AF13 VO Z IPU Emulation pin 14 EMU15 9 VO Z IPU Emulation pin 15 EMU16 AH12 VO Z IPU Emulation pin 16 EMU17 AH10 VO Z IPU Emulation pin 17 EMU18 AE13 VO Z IPU Emulation pin 18 1 I Input Output Z High impedance S Supply voltage GND Ground A Analog signal 2 IPD Internal pulldown IPU Internal pullup For most systems a 1 kQ resistor can be used to oppose the IPU IPD For more detailed information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see Section 3 7 Pullup Pulldown Resistors These pins are multiplexed pins For more details see Section 3 Device Configuration 4 C6455 DSP does not require external pulldown resistors on the EMUO and EMU1 pins for normal or boundary scan operation 30 Device Overview S
204. TOPIA EN 12 pin 1 URADDR3 PREQ e 5 bit Slave receive address input pins driven by the Master ATM Controller GP 15 P2 to identify select of the Slave devices to 31 possible the URADDR2 PINTA ATM System GP 14 P3 l When the UTOPIA peripheral is disabled UTOPIA EN AEA12 pin 0 these pins are PCI if PCI EN 1 or GPIO if PCI EN 0 pins URADDR1 PRST GP 15 12 2 GP 13 s As PCI peripheral pins PCI command byte enable 0 PCBEO I O Z RADDRO PGNT PCI bus request PREQ O Z GP i R4 PCI interrupt A PINTA O Z PCI reset PRST I and PCI bus grant PGNT I O Z URDATA7 MRXD7 M2 UTOPIA 8 bit R Data Bus I O Z default or EMAC data b it Receive Data Bus efault or receive data bus URDATAS MRXDS L2 MII default 0 2 or GMII VO Z or RMII 1 0 2 URDATA4 MRXD4 L1 Using the Receive Data Bus the UTOPIA Slave on the rising edge of the URDATA3 MRXD3 J8 ion URCLK can receive the 8 bit ATM cell data from the Master ATM Controller When the UTOPIA peripheral is disabled UTOPIA EN AEA12 pin 0 these RDATA2 MRXD2 1 i pins function as EMAC pins and controlled by the MACSEL 1 0 AEA 10 9 URDATA1 MRXD1 pins to select the RMII GMII or RGMII EMAC interface For more details H3 RMRXD1 see Section 3 Device Configuration URDATAO MRXDO J2 RMRXDO 1 These pins function as open drain outputs when confi
205. TS www ti com Table 5 4 Megamodule Interrupt Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0188 INTDMASK Dropped Interrupt Mask Register 0180 0188 0180 01BC Reserved 0180 01 0 EVTASRT Event Asserting Register 0180 01C4 0180 FFFF Reserved Table 5 5 Megamodule Powerdown Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0181 0000 PDCCMD Power down controller command register 0181 0004 0181 1FFF Reserved Table 5 6 Megamodule Revision Register HEX ADDRESS RANGE ACRONYM REGISTER NAME 0181 2000 MM_REVID Megamodule Revision ID Register 0181 2004 0181 2FFF Reserved Table 5 7 Megamodule IDMA Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0182 0000 IDMAOSTAT IDMA Channel 0 Status Register 0182 0004 IDMAOMASK IDMA Channel 0 Mask Register 0182 0008 IMDAOSRC IDMA Channel 0 Source Address Register 0182 000C IDMAODST IDMA Channel 0 Destination Address Register 0182 0010 IDMAOCNT IDMA Channel 0 Count Register 0182 0014 0182 O0FC Reserved 0182 0100 IDMA1STAT IDMA Channel 1 Status Register 0182 0104 Reserved 0182 0108 IMDA1SRC IDMA Channel 1 Source Address Register 0182 010C IDMA1DST IDMA Channel 1 Destination Address Register 0182 0110 IDMA1CNT IDMA Channel 1 Count Register 0182 0114 0182 017C Reserved 0182 0180 Reserved 0182 0
206. Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 96 VCP2 Registers continued HEX ADDRESS RANGE HEX ALORE S RANE ACRONYM REGISTERNAME 5800 1000 BM Branch Metrics 5800 2000 SM State Metric 5800 3000 TBHD Traceback Hard Decision 5800 6000 TBSD Traceback Soft Decision 5800 F000 IO Decoded Bits 7 17 Enhanced Turbo Decoder Coprocessor TCP2 7 17 1 2 Device Specific Information The C6455 device has a high performance embedded coprocessor Turbo Decoder Coprocessor TCP2 that significantly speeds up channel decoding operations on chip With the CPU operating at 1 GHz the TCP2 can decode up to forty 384 Kbps or eight 2 Mbps turbo encoded channels assuming 8 iterations The TCP2 implements the max log map algorithm and is designed to support all polynomials and rates required by Third Generation Partnership Projects 3GPP and 3GPP2 with fully programmable frame length and turbo interleaver Decoding parameters such as the number of iterations and stopping criteria are also programmable Communications between the TCP2 and the CPU are carried out through the EDMAS controller The TCP2 supports e Parallel concatenated convolutional turbo decoding using the MAP algorithm e All turbo code rates greater than or equal to 1 5 3GPP and CDMA2000 turbo encoder trellis 3GPP and CDMA2000 block sizes in sta
207. Timing Table 7 107 Timing Requirements for URCLK see Figure 7 75 720 850 NO A 1000 1000 UNIT 1200 MIN MAX 1 tc URCK Cycle time URCLK 20 2 tw URCKH Pulse duration URCLK high O 4tc URCK 0 6t uRCK ns 3 twURCKL Pulse duration URCLK low 0 4tc URCK 0 ns 4 lURCK Transition time URCLK 2 fis 1 The reference points for the rise and fall transitions are measured at Vy MAX and MIN X 1 E m k 3 l 1 4 3 le Figure 7 75 URCLK Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 231 SM320C6455 EP 79 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 108 Timing Requirements for UTOPIA Slave Transmit see Figure 7 76 720 850 NO A 1000 1000 UNIT 1200 MIN MAX tsu UXAV UXCH Setup time UXADDR valid before UXCLK high ns th UXCH UXAV Hold time UXADDR valid after UXCLK high ns tsu UXENBL UXCH Setup time UXENB low before UXCLK high ns th UXCH UXENBL Hold time UXENB low after UXCLK high CO OO Q n l al ia ns Table 7 109 Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave Transmit Cycles see Figure 7 76 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 1 ta UXCH UXDV Delay
208. Vppigmon pin is not used it should be connected directly to the 1 8 V I O supply DVpp g SUPPLY VOLTAGE PINS VREFSSTL C14 DVpp18 2 V reference for SSTL buffer DDR2 Memory Controller This input voltage can be generated directly from DVppig using two 1 kQ resistors to form a resistor divider circuit NOTE The DDR2 Memory Controller is not used the Vrersst_ RSV11 and RSV12 pins can be connected directly to ground Vss to save power However connecting these pins directly to ground prevents boundary scan from functioning on the DDR2 Memory Controller pins To preserve boundary scan functionality on the DDR2 Memory Controller pins see Section 7 3 4 VREFHSTL B2 DVpp15 2 V reference for HSTL buffer EMAC RGMII can be generated directly from DVpp15 using two 1 kQ resistors to form a resistor divider circuit NOTE If the RGMII mode of the EMAC is not used the DVppis VREFHSTL RSV13 and RSV14 pins can be connected to directly ground Vss to save power However connecting these pins directly to ground prevents boundary scan from functioning on the RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins see Section 7 3 4 DVppn AD20 1 8 V I O supply voltage SRIO regulator supply NOTE If Rapid I O is not used this pin be connected directly to Vss AVppA AC15 AC17 AD16 SRIO analog supply 1 25 V I O supply voltage 1000
209. Y 2008 STATE DESCRIPTION PERIPHERALS THAT CAN BE IN THIS STATE Static powerdown Peripheral pin function has been completely disabled through the device configuration pins Peripheral is held in reset and clock is turned off HPI PCI McBSP1 UTOPIA EMAC MDIO EMIFA DDR2 Memory Controller Disabled Peripheral is held in reset and clock is turned off Default state for all peripherals not in static powerdown mode TCP VCP 2 0 1 GPIO EMAC MDIO McBSP0 McBSP1 HPI PCI UTOPIA Enabled Clock to the peripheral is turned on and the peripheral is taken out of reset TCP VCP 2 0 1 GPIO MDIO EMAC MDIO McBSP0 McBSP1 HPI PCI UTOPIA EMIFA DDR2 Memory Controller Enable in progress Not a user programmable state This is an intermediate state when transitioning from an disabled state to an enabled state All peripherals that can be in an enabled state Following device reset all peripherals that are not in the static powerdown state are in the disabled state by default Peripherals used for boot such as HPI and PCI are enabled automatically following a device reset Peripherals are allowed only certain transitions between states see Figure 3 1 Submit Documentation Feedback Device Configuration 63 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B
210. Z default DX1 GP 9 AG5 VO Z IPD McBSP1 transmit clock 1 0 2 or GP 3 1 0 2 default CLKX1 GP 3 AF5 VO Z IPD GP 1 pin I O Z SYSCLK4 is the clock output at 1 8 of the device speed 0 2 his pi P 1 pin 1 0 2 fault URADDRA PCBEU or this pin can be programmed as a GP 1 pin 1 0 2 default P1 VO Z GP 2 SYSCLK4 GP 1 AJ13 O Z IPD CLKR1 GP 0 AF4 VO Z IPD HOST PORT INTERFACE HPI or PERIPHERAL COMPONENT INTERCONNECT PCI PCI enable pin This pin controls the selection enable disable of the HPI and PCI EN Y29 IPD GP 15 8 or PCI peripherals This pin works in conjunction with the MCBSP1 EN AEAS pin to enable disable other peripherals for more details see Section 3 Device Configuration HINT PFRAME U3 VO Z Host interrupt from DSP to host 0 2 or PCI frame 1 2 Host control selects between control address or data registers default or HCNTL1 PDEVSEL U4 VO Z PCI device select 1 0 2 Host control selects between control address or data registers 1 default or HCNTLO PSTOP U5 VO Z PCI stop l O Z Host half word select first or second half word not necessarily high or low HHWIL PCLK V3 VO Z order For HPI16 bus width selection only I default or PCI clock I HR W PCBE2 T5 VO Z Host read or write select I default or PCI command byte enable 2 2 HAS PPAR T3 VO Z Host address strobe I default or PCI parity 1 0 2 HCS PPERR U6 VO Z Host chip select I defau
211. a configuration bus 3400 0010 DXR1 McBSP1 Data Transmit Register via EDMA bus 0290 0008 SPCR1 McBSP1 serial port control register 0290 000C RCR1 McBSP1 Receive Control Register 0290 0010 XCR1 McBSP1 Transmit Control Register 0290 0014 SRGR1 McBSP1 sample rate generator register 0290 0018 MCR1 McBSP1 multichannel control register McBSP1 Enhanced Receive Channel Enable 0290 001C RCEREO Register 0 Partition A B McBSP1 Enhanced Transmit Channel Enable 0290 0020 ACEREO Register 0 Partition A B 0290 0024 PCR1 McBSP1 Pin Control Register McBSP1 Enhanced Receive Channel Enable 0290 0028 RCEREI1 Register 1 Partition C D McBSP1 Enhanced Transmit Channel Enable 0290 002 Register 1 Partition C D McBSP1 Enhanced Receive Channel Enable 0290 0030 RCERE21 Register 2 Partition E F McBSP1 Enhanced Transmit Channel Enable 0290 0034 XCERE21 Register 2 Partition E F McBSP1 Enhanced Receive Channel Enable 0290 0038 Register 3 Partition 0290 003C XCERE31 McBSP1 Enhanced Transmit Channel Enable Register 3 Partition G H 0290 0040 0293 FFFF Reserved 192 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 13 2 McBSP Electrical Data Timing 7 13 2 1 Multichannel Buffered Serial Port McBSP Timing Table 7 59 Timing Requirem
212. ace accesses Figure 7 36 Programmable Synchronous Interface Read Timing for EMIFA With Read Latency 2 AECLKOUT NV _ N AEN 1 gt 1 1 MEE k 2 e 3 ABE ZTO BE X BE X BE X BE X A 14 5 5 AEA 19 0 ABA 1 0 ERE C ER E _ a L 19 11 AED 63 0 G C 8 8 ASADS ASRE eee AAOE ASOE 12 AAWE ASWE M A The following parameters are programmable via the EMIFA Chip Select n Configuration Register CESECn Read latency LTNCY 1 2 or 3 cycle read latency Write latency W_LTNCY 0 1 2 or 3 cycle write latency ACEx assertion length END For standard SBSRAM or ZBT SRAM interface ACEx goes inactive after the final command has been issued EXT 0 For synchronous FIFO interface ACEx is active when ASOE is active CE EXT 1 Function of ASADS ASRE ENABLE For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles ENABLE 0 For FIFO interface ASADS ASRE acts as SRE with NO deselect cycles R ENABLE 1 In this figure W LTNCY 0 CE EXT 0 R ENABLE 0 and SSEL 1 B AAOE ASOE and AAWE ASWE operate as ASOE and ASWE respectively during programmable synchronous interface accesses Figure 7 37 Programmable Synchronous Interface Write Timing for EMIFA
213. ache or all SRAM The on chip Bootloader changes the reset configuration for L1P and L1D For more information see the TMS320C645x Bootloader User s Guide literature number SPRUEC6 Figure 5 2 and Figure 5 3 show the available SRAM cache configurations for L1P and L1D respectively L1P mode bits 000 001 010 011 100 L1P memory 16 bytes 3 4 7 8 SRAM All SRAM direct SRAM mapped cache 8K bytes direct direct cache 4K bytes mapped bytes Figure 5 2 C6455 L1P Memory Configurations L1D mode bits 000 001 010 011 100 L1D memory eben 16K bytes 3 4 7 8 SRAM All SRAM 2 wa y SRAM cache 8K bytes 2 way cache 4K bytes 2 way cache 2 4K bytes 88 C64x Figure 5 3 C6455 L1D Memory Configurations Block base address 00E0 0000h 00 0 4000h 00E0 6000h 00E0 7000h 00E0 8000h Block base address OOFO 0000h OOFO 4000h 00 0 6000h OOFO 7000h 00 0 8000h Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 The L2 memory configuration for the C6455 device is as follows e Port 0 configuration Memory size is 2096KB Starting address is 0080 0000h 2 cycle latency 4 128 bit bank configuration e Port 1 configuration Memory size i
214. age I2C pins 0 7DVpps3 V RGMII pins VREFHSTL 0 10 DVpp15 0 30 V DDR2 memory controller pins VREFSSTL 0 125 DVppi8 0 3 V DC 3 3 V pins except PCI capable and 0 08 V I2C pins E 0 5 0 3DVppss V Vit Low level input voltage I2C pins 0 03DVppas V RGMII pins 0 3 VREFHSTL 0 1 V DDR2 memory controller pins 0 3 VrersstL 0 125 V DC Maximum voltage during overshoot undershoot Vos PCI capable pins 2 3 5 74 V default temperature i 99 Te Operating case temperature A temperature 40 105 C S temperature 55 105 1 These rated numbers are from the PCI Local Bus Specification version 2 3 The DC specifications and AC specifications are defined in Table 4 3 and Table 4 4 respectively of the PCI Local Bus Specification 2 PCI capable pins can withstand a maximum overshoot undershoot for up to 11 ns as required by the PCI Local Bus Specification version 2 3 102 Device Operating Conditions Submit Documentation Feedback SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 ki TEXAS INSTRUMENTS www ti com 6 3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Unless Otherwise Noted PARAMETER TEST CONDITIONS MIN MAX UNIT 3 3 V pins except PCl capable and I2C D Vboss 7 MIN 0 8DVppas pins OH High
215. agement and the memory and cache SPRU965 TMS320C6455 Technical Reference An introduction to the C6455 DSP and discusses the application areas that are enhanced SPRAA84 TMS320C64x to TMS320C64x CPU Migration Guide Describes migrating from the Texas Instruments C64x digital signal processor DSP to the C64x DSP The objective of this document is to indicate differences between the two cores Functionality in the devices that is identical is not included SPRU889 High Speed DSP Systems Design Reference Guide Provides recommendations for meeting the many challenges of high speed DSP system design These recommendations include information about DSP audio video and communications systems for the C5000 and Device Overview Submit Documentation Feedback 4 6 INSTRUMENTS www ti com SPRU970 SPRU966 SPRU975 SPRU971 SPRU724 SPRU969 SPRU974 SPRUE60 SPRU976 SPRUE56 SPRU968 SPRU973 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 C6000 DSP platforms TMS320C645x DSP DDR2 Memory Controller User s Guide This document describes the DDR2 memory controller in the C645x digital signal processors DSPs TMS320C645x DSP Enhanced DMA EDMA3 Controller User s Guide This document describes the Enhanced DMA EDMA3 Controller on the C645x device TMS320C645x DSP EMAC MDIO Module User s Guide This document provides a functional description of the Eth
216. als These registers are shown in Table 3 5 and described in the next sections NOTE The device state control registers can only be accessed using the CPU or the emulator Table 3 5 Device State Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02AC 0000 Reserved 02 0004 PERLOCK Peripheral Lock Register 02AC 0008 PERCFG0 Peripheral Configuration Register 0 02AC 000G Reserved 02 0010 Reserved 02 0014 PERSTATO Peripheral Status Register 0 02AC 0018 PERSTAT1 Peripheral Status Register 1 02AC 001C 02AC 001F Reserved 02AC 0020 EMACCFG EMAC Configuration Register 02 0024 02 002 Reserved 02AC 002G PERCFG1 Peripheral Configuration Register 1 02AC 0030 02AC 0053 Reserved 02 0054 EMUBUFPD Emulator Buffer Powerdown Register 02AC 0058 Reserved Submit Documentation Feedback Device Configuration 65 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 3 4 1 Peripheral Lock Register Description When written with correct 32 bit key 0x0F0A0B00 the Peripheral Lock Register PERLOCK allows one write to the PERCFGO register within 16 SYSCLK3 cycles NOTE The instructions that write to the PERLOCK and PERCFGO registers must be in the same fetch packet if code is being executed from external memory If the instructions are in different fetch packets
217. always be set to a value of 1 or greater The McBSP Data Receive Register DRR and Data Transmit Register DXR can be accessed through two separate busses a configuration bus and a data bus Both paths can be used by the CPU and the EDMA The data bus should be used to service the McBSP as this path provides better performance However since the data path shares a bridge with the PCI and UTOPIA peripherals see Figure 4 1 the configuration path should be used in cases where these peripherals are being used to avoid any performance degradation Note that the PCI peripheral consists of an independent master and slave Performance degradation is only a concern when this peripheral is used to initiate transactions on the external bus 7 13 1 1 McBSP Peripheral Register Description s Table 7 57 McBSP 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS The CPU and EDMA3 7 controller can only read 028C 0000 DRRO McBSPO Data Receive Register via Configuration Bus this register they cannot write to it 3000 0000 DRRO McBSPO Data Receive Register via EDMA3 Bus 028C 0004 DXRO McBSPO Data Transmit Register via Configuration Bus 3000 0010 DXRO McBSPO Data Transmit Register via EDMA Bus 028C 0008 SPCRO McBSPO Serial Port Control Register 028C 000C RCRO McBSPO Receive Control Register 028C 0010 XCRO McBSPO0 Transmit Control Register 028C 0014 SRGRO McBSPO0 Sample Rate Generat
218. and 1200 devices 1 2 V I O supply voltage 850 and 720 devices Do not use core supply NOTE If Rapid I O is not used these pins can be connected directly to Vas AVDpLL1 A13 AVpLL2 E18 1 8 V I O supply voltage 46 Device Overview Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE iPD IPU 2 DESCRIPTION NAME NO U16 SRIO interface supply V15 1 25 V core supply voltage 1000 and 1200 devices DVppru s 1 2 V core supply voltage 850 and 720 devices V17 The source for this supply voltage must be the same as that of CVpp NOTE If RapidIO is not used these pins can be connected directly to Vss W16 Main SRIO supply 1 25 V I O supply voltage 1000 and 1200 devices DVpp12 s 1 2 V I O supply voltage 850 and 720 devices W18 Do notuse core supply NOTE If RapidIO is not used these pins can be connected directly to Vss AE17 AE19 AE23 SRIO termination supply 1 25 V I O supply voltage 1000 and 1200 devices AVppr AF20 A 1 2 V I O supply voltage 850 and 720 devices 20 Do notuse core supply NOTE If RapidIO is not used these pins can be connected directly to Vss AJ17
219. application For more detailed information on the boot modes see Section 2 4 Boot Sequence Submit Documentation Feedback C64x4 Megamodule 89 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 5 2 www ti com Memory Protection Memory protection allows an operating system to define who or what is authorized to access L1D L1P and L2 memory To accomplish this the L1D L1P and L2 memories are divided into pages There are 16 pages of L1P 2KB each 16 pages of L1D 2KB each and 32 pages of L2 64KB each L1D L1P and L2 memory controllers in the C64x Megamodule are equipped with a set of registers that specify the permissions for each memory page Each page may be assigned with fully orthogonal user and supervisor read write and execute permissions Additionally a page may be marked as either or both locally or globally accessible A local access is a direct CPU access to L1D L1P and L2 while a global access is initiated by a DMA either IDMA or the or by other system masters Note that EDMA or IDMA transfers programmed by the CPU count as global accesses The CPU and the system masters on the C6455 device are all assigned a privilege ID of 0 Therefore it is only possible to specify whether memory pages are locally or globally accessible The AID0 and LOCAL bits of the memory protection page attribute registers specify the memory pag
220. arameter Set 9 02A0 47 0 02 0 47FF Parameter Set 63 02A0 4800 02 0 481F Parameter Set 64 02A0 4820 02 0 483F Parameter Set 65 02A0 5FCO 02A0 5FDF Parameter Set 254 02A0 5FEO 02 0 5FFF Parameter Set 255 1 The C6455 device has 256 EDMAS parameter sets total Each parameter set can be used as a DMA entry a QDMA entry or a link entry Table 7 6 EDMAS Transfer Controller 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 0000 PID Peripheral Identification Register 02A2 0004 TCCFG Configuration Register 02A2 0008 02 2 00 Reserved 02A2 0100 TCSTAT Channel Status Register 02A2 0104 02A2 011G Reserved 02A2 0120 ERRSTAT Error Register 02A2 0124 ERREN Error Enable Register 02A2 0128 ERRCLR Error Clear Register 02A2 012 ERRDET Error Details Register 02A2 0130 ERRCMD Error Interrupt Command Register 02A2 0134 02A2 013G Reserved 02A2 0140 RDRATE Read Rate Register 02A2 0144 02A2 023G Reserved 02A2 0240 SAOPT Source Active Options Register 02A2 0244 SASRC Source Active Source Address Register 02A2 0248 SACNT Source Active Count Register 02 2 024 SADST Source Active Destination Address Register 02A2 0250 SABIDX Source Active Source B Index Register 02A2 0254 SAMPPRXY Source Active Memory Protection Proxy Register 02A2 0258 SACNTRLD Source Act
221. ared by software before triggering transfers on DMA channel 0 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 223 SM320C6455 EP 43 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 18 2 PCI Peripheral Register Description s Table 7 99 PCI Configuration Registers bie pares OFT ET ACRONYM PCI HOST ACCESS REGISTER NAME 0x00 PCIVENDEV Vendor ID Device ID 0x04 PCICSR Command Status 0x08 PCICLREV Class Code Revision ID 0x0C PCICLINE BIST Header Type Latency Timer Cacheline Size 0x10 PCIBARO Base Address 0 0x14 PCIBAR1 Base Address 1 0x18 PCIBAR2 Base Address 2 0x1C Base Address 3 0x20 PCIBAR4 Base Address 4 0x24 PCIBAR5 Base Address 5 0x28 0x2B Reserved 0x2G PCISUBID Subsystem Vendor ID Subsystem ID 0x30 5 Reserved 0x34 PCICPBPTR Capabilities Pointer 0x38 Ox3B Reserved 0x3C PCILGINT Max Latency Min Grant Interrupt Pin Interrupt Line 0x40 Ox7F Reserved 224 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 100 PCI Back End C
222. ata sheet to make it an SPRS276H revision Scope Applicable updates to the C64x device family specifically relating to the SM320C6455 EP device have been incorporated C6455 Revision History SEE ADDITIONS MODIFICATIONS DELETIONS Global Section 1 Section 2 1 Section 2 8 2 Section 6 3 Section 7 Section 7 7 1 Section 7 8 Added 1 2 GHz device information Features Added 0 83 ns instruction cycle time Added 1 2 GHz clock rate Device Characteristics Table 2 1 Characteristics of the C6455 Processor Added 1200 1 2 GHz Frequency Added 0 83 ns C6455 1200 1 2 GHz CPU Cycle Time Added 1200 device to 1 25 V Core Voltage Device Support Added Device Speed Range 2 1 2 GHz to Figure 2 13 C64x DSP Device Nomenclature including the SM320C6455 EP DSP Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Added a row to Pcpp Core supply power for CPU frequency 1200 MHz with a TYP value of 1 79 W Added a row to Pppp I O supply power for CPU frequency 1200 MHz with a TYP value of 0 54 W C64x Peripheral Information and Electrical Specifications Added 1200 to all timing and switching characteristics tables PLL1 Controller Device Specific Information Changed third paragraph to PLLOUT is set to 1200 MHz Changed PLLOUT MAX value to 1200 MHz in Table 7 16 PLL1 Clock Frequency Ranges PLL2 and PLL2 Controller Changed C162 value to 0 1 u
223. ation Boot Modes Supported The C6455 has six boot modes e No boot BOOTMODE 3 0 0000b With no boot the CPU executes directly from the internal L2 SRAM located at address 0x80 0000 Note device operations are undefined if invalid code is located at address 0x80 0000 This boot mode is a hardware boot mode e Host boot BOOTMODE 3 0 0001b and BOOTMODE 3 0 0111b If host boot is selected after reset the CPU is internally stalled while the remainder of the device is released During this period an external host can initialize the CPU s memory space as necessary through Host Port Interface HPI or the Peripheral Component Interconnect PCI interface Internal configuration registers such as those that control the EMIF also can be initialized by the host with two exceptions Device State Control registers Section 3 4 PLL1 and PLL2 Controller registers Section 7 7 and Section 7 8 cannot be accessed through any host interface including HPI and PCI Once the host is finished with all necessary initialization it must generate a DSP interrupt DSPINT to complete the boot process This transition causes boot configuration logic to bring the CPU out of the stalled state The CPU then begins execution from the internal L2 SRAM located at 0x80 0000 Note that the DSP interrupt is registered in bit 0 channel 0 of the EDMA Event Register ER This event must be cleared by software before triggering transfers on DMA channel 0
224. auto incrementing HPIA or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 C The timing tw HSTBH HSTROBE high pulse duration must be met between consecutive HPI accesses 2 mode Figure 7 50 2 Write Timing HAS Not Used Tied High 188 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com HAS input HCNTL 1 0 input HR W input HSTROBE A input HCS input m SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 1 yy 4 17 HD 31 0 input dt 4 35 55 lt 38 6 9 5 HRDY B output Y N HSTROBE refers to the following logical operation on 5 HDS1 and HDS2 NOT HDST HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 C The timing twHstBH HSTROBE high pulse durati
225. be programmed to 2 mode default when using the Gigabit Media Independent Interface GMII mode and to 5 mode when using the Reduce Gigabit Media Independent Interface RGMII Divider D1 is software programmable and if necessary must be programmed after device reset to 5 when the RGMII mode of the EMAC is used Note that internally the data bus interface of the EMAC is clocked by SYSCLK3 of the PLL2 controller Note that there is a minimum and maximum operating frequency for PLLREF PLLOUT and SYSCLK1 The clock generator must not be configured to exceed any of these constraints For the PLL clocks input and output frequency ranges see Table 7 31 Also when EMAC is enabled with RGMII or GMII CLKIN2 must be 25 MHz Table 7 31 PLL2 Clock Frequency Ranges CLOCK SIGNAL MIN MAX UNIT PLLREF PLLEN 1 12 5 26 7 MHz PLLOUT 250 533 MHz SYscLk1 50 125 MHz 1 SYSCLK1 restriction applies only when the EMAC is enabled and the RGMII GMII modes used SYSCLK1 must be programmed to 125 MHz when the GMII mode is used and to 50 MHz when the RGMII mode is used 7 8 1 2 PLL2 Controller Operating Modes 152 Unlike the PLL1 controller which can operate in bypass and a PLL mode the PLL2 controller only operates in PLL mode In this mode SYSREFCLK is generated outside the PLL2 controller by dividing the output of PLL2 by two The PLL2 controller is affected by power on reset warm reset and max res
226. best performance TI recommends that all the PLL external components be on a single side of the board without jumpers switches or components other than the ones shown For reduced PLL jitter maximize the spacing between switching signals and the PLL external components C1 C2 and the EMI Filter The minimum CLKIN1 rise and fall times should also be observed For the input clock timing requirements see Section 7 7 4 PLL1 Controller Input and Output Clock Electrical Data Timing CAUTION The PLL controller module as described in the TMS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide literature number SPRUE56 includes a superset of features some of which not supported on the C6455 DSP The following sections describe the features that are supported it should be assumed that any feature not included in these sections is not supported by the C6455 DSP 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 LEUTE TMS320C6455 DSP PLLV1 X PLL1 Controller PLLEN PLLCTL 0 DIVIDER PREDIV SYSREFCLK IVA C64x MegaModule LX 12 13 PLLM I xt X15 DIVIDER 02 20 25 30 32 B SYSCLK2 _ PREDEN PREDIV 15 D
227. ble Set Register 02A0 2090 QSER QDMA Secondary Event Register 02A0 2094 QSECR QDMA Secondary Event Clear Register 02A0 2098 02A0 23FF Reserved 02A0 2400 02A0 2497 Shadow Region 2 Channel Registers 02A0 2498 02A0 25FF Reserved 02A0 2600 02A0 2697 Shadow Region 3 Channel Registers 02A0 2698 02A0 27FF Reserved 02A0 2800 02A0 2897 Shadow Region 4 Channel Registers 02A0 2898 02A0 29FF Reserved 02A0 2A00 02A0 2A97 Shadow Region 5 Channel Registers 02A0 2A98 02A0 2BFF Reserved 02A0 2C00 02A0 2C97 Shadow Region 6 Channel Registers 02A0 2C98 02A0 2DFF Reserved 02A0 2E00 02A0 2E97 Shadow Region 7 Channel Registers 02A0 2E98 02A0 2FFF Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 117 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Wy TEXAS www ti com Table 7 5 EDMA3 Parameter RAM HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 4000 02 0 401F Parameter Set 0 02A0 4020 02 0 403F Parameter Set 1 02A0 4040 02A0 405F Parameter Set 2 02A0 4060 02A0 407F Parameter Set 3 02A0 4080 02A0 409F Parameter Set 4 02A0 40A0 02A0 40BF Parameter Set 5 02A0 40 0 02 0 40DF Parameter Set 6 02A0 40E0 02 0 40FF Parameter Set 7 02A0 4100 02A0 411F Parameter Set 8 02A0 4120 02A0 413F P
228. box to Queue Mapping Register L1 02D0 080C RIO RXU MAP H1 Mailbox to Queue Mapping Register H1 02D0 0810 RIO RXU MAP L2 Mailbox to Queue Mapping Register L2 02D0 0814 RIO RXU MAP H2 Mailbox to Queue Mapping Register H2 02D0 0818 RIO RXU MAP L3 Mailbox to Queue Mapping Register L3 02D0 081C RIO MAP Mailbox to Queue Mapping Register H3 02D0 0820 RIO RXU MAP L4 Mailbox to Queue Mapping Register L4 02D0 0824 RIO RXU MAP H4 Mailbox to Queue Mapping Register H4 02D0 0828 RIO RXU MAP L5 Mailbox to Queue Mapping Register L5 02D0 082C RIO MAP H5 Mailbox to Queue Mapping Register H5 02D0 0830 RIO RXU MAP L6 Mailbox to Queue Mapping Register L6 02D0 0834 RIO RXU MAP H6 Mailbox to Queue Mapping Register H6 02D0 0838 RIO RXU MAP L7 Mailbox to Queue Mapping Register L7 02D0 083C RIO RXU MAP H7 Mailbox to Queue Mapping Register H7 02D0 0840 RIO_RXU_MAP_L8 Mailbox to Queue Mapping Register L8 02D0 0844 RIO_RXU_MAP_H8 Mailbox to Queue Mapping Register H8 02D0 0848 RIO_RXU_MAP_L9 Mailbox to Queue Mapping Register L9 02D0 084C RIO_RXU_MAP_H9 Mailbox to Queue Mapping Register H9 02D0 0850 RIO_RXU_MAP_L10 Mailbox to Queue Mapping Register L10 02D0 0854 RIO_RXU_MAP_H10 Mailbox to Queue Mapping Register H10 02D0 0858 RIO_RXU_MAP_L11 Mailbox to
229. c and PLL2 are not reset The following sequence must be followed during a Warm Reset 1 Hold the RESET pin low for a minimum of 24 CLKIN1 cycles Within the minimum 24 CLKIN1 cycles Within the low period of the RESET pin the following happens The Z group pins low group pins and the high group pins are set to their reset state with one exception The PCI pins are not affected by warm reset if the PCI module was enabled before RESET went low In this case PCI pins stay at whatever their value was before RESET went low The reset signals flow to the entire chip excluding the test and emulation logic resetting modules that use reset asynchronously The PLL1 controller is reset thereby switching back to bypass mode and resetting all its registers to their default values PLL1 is placed in reset and loses lock The PLL1 controller clocks start running at the frequency of the system reference clock The clocks are propagated throughout the chip to reset modules that use reset synchronously The PLL2 controller is reset thereby resetting all its registers to their default values The PLL2 controller clocks start running at the frequency of the system reference clock PLL2 is not reset therefore it remains locked The RESETSTAT pin becomes active low indicating the device is in reset 2 The RESET pin may now be released driven inactive high When the RESET pin is released the configuration pin values are latched and
230. ce Note that some peripherals can be accessed through the data SCR and also through the configuration SCR Submit Documentation Feedback System Interconnect 81 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 4 2 82 www ti com Data Switch Fabric Connections Figure 4 1 shows the connection between slaves and masters through the data switched central resource SCR Masters are shown on the right and slaves on the left The data SCR connects masters to slaves via 128 bit data buses running at a SYSCLK2 frequency SYSCLK is supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency divided by 3 Some peripherals like PCI and the C64x Megamodule have both slave and master ports Note that each EDMAS transfer controller has an independent connection to the data SCR The Serial RapidlO SRIO peripheral has two connections to the data SCR The first connection is used when descriptors are being fetched from system memory The other connection is used for all other data transfers Note that masters can access the configuration SCR through the data SCR The configuration SCR is described in Section 4 3 Not all masters on the C6455 DSP may connect to all slaves Allowed connections are summarized in Table 4 1 System Interconnect Submit Documentation Feedback Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PRO
231. ce and reduces system cost for applications that include multiple DSPs on a board such as video and telecom infrastructures and medical imaging The C6455 DSP integrates a large amount of on chip memory organized as a two level memory system The level 1 L1 program and data memories on the C6455 device are 32KB each This memory can be configured as mapped RAM cache or some combination of the two When configured as cache L1 program L1P is a direct mapped cache where L1 data L1D is a two way set associative cache level 2 L2 memory is shared between program and data space and is 2096KB in size L2 memory also can be configured as mapped RAM cache or some combination of the two The C64x Megamodule also has a 32 bit peripheral configuration CFG port an internal DMA IDMA controller a system component with reset boot control interrupt exception control a power down control and a free running 32 bit timer for time stamp The peripheral set includes inter integrated circuit bus module 2 two multichannel buffered serial ports McBSPs an 8 bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode ATM Slave UTOPIA Slave port two 64 bit general purpose timers also configurable as four 32 bit timers user configurable 16 bit or 32 bit host port interface 16 2 a peripheral component interconnect PCI a 16 pin general purpose input output port GPIO with programmable i
232. ck 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR i SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 2 8 Development 2 8 1 Development Support In case the customer would like to develop their own features and software on the C6455 device TI offers an extensive line of development tools for the C6000 DSP platform including tools to evaluate the performance of the processors generate code develop algorithm implementations and fully integrate and debug software and hardware modules The tool s support documentation is electronically available within the Code Composer Studio Integrated Development Environment IDE The following products support development of C6000 DSP based applications Software Development Tools Code Composer Studio Integrated Development Environment IDE including Editor C C Assembly Code Generation and Debug plus additional development tools Scalable Real Time Foundation Software DSP BIOS which provides the basic run time target software needed to support any DSP application Hardware Development Tools Extended Development System XDS Emulator Supports C6000 DSP multiprocessor system debug EVM Evaluation Module 2 8 2 Device Support 2 8 2 1 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle TI assigns prefixes to the part numbers of all DSP devices and support tools Each DSP commercial family memb
233. cle time GMTCLK 8 2 twGMTCLKH Pulse duration GMTCLK high 28 ns 3 tw GMTCLKL Pulse duration GMTCLK low 28 B 4 lGMTCLK Transition time GMTCLK 1 us w m gt 4 h amu Z N y Output Figure 7 61 GMTCLK Timing EMAC Transmit GMII Operation Table 7 78 Timing Requirements for EMAC MII and GMII Receive 10 100 1000 Mbit s see Figure 7 62 720 850 A 1000 1000 NO 1200 UNIT 1000 Mbps 100 10 Mbps MIN MAX MIN MAX Setup time receive selected signals valid before 1 tsu MRXD MRCLKH MECUK high 9 2 8 ns 2 Hold time receive selected signals valid after th MRCLKH MRXD MRCLK high 0 8 ns 1 For Receive selected signals include MRXD 3 0 MRXDV and MRXER For Receive selected signals include MRXD 7 0 MRXDV and MRXER MRCLK Input qu NEM x NENNEN MRXD7 MRXD4A GMII only V V V Y Y V Y NY Y Y Y Y NY X V V Y X Y YA KZ RRR MRXDV MRXER Inputs Figure 7 62 EMAC Receive Interface Timing MII and GMII Operation Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 209 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 79 Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII Transmit 10 100 Mbit s see Figure 7 63
234. clocks is changing A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed 7 7 1 3 PLL1 Stabilization Lock and Reset Times 138 The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device powerup The PLL should not be operated until this stabilization time has expired The PLL reset time is the amount of wait time needed when resetting the PLL writing PLLRST 1 in order for the PLL to properly reset before bringing the PLL out of reset writing PLLRST 0 For the PLL1 reset time value see Table 7 17 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 The PLL lock time is the amount of time needed from when the PLL is taken out of reset PLLRST 1 with PLLEN 0 to when to when the PLL controller can be switched to PLL mode PLLEN 1 The PLL1 lock time is given in Table 7 17 Table 7 17 PLL1 Stabilization Lock and Reset Times MIN TYP MAX UNIT PLL stabilization time 150 us PLL lock time 2000 C ns PLL reset time 128 ns 1 cycle time in ns For example when CLKIN1 frequency is 50 MHz use C 20 ns 7 7 2 PLL1 Controller Memory The memory map of the
235. ct to Vss 6 2 Recommended Operating Conditions MIN NOM MAX UNIT A 1000 1000 1 2125 1 25 1 2875 V CV Supply voltage Core pp ien 1 1640 1 20 1 2360 V 720 1000 1000 1 2125 1 25 1 2875 V DV Supply voltage Core DDRM required only for RapidIO EA 1 1640 1 20 1 2360 V A 1000 1000 1 1875 1 25 1 3125 V 4 Supply voltage VO BED required only for RapidIO 7720 1 14 1 20 1 26 V DVpp33 Supply voltage I O 3 14 3 3 3 46 V DVppi8 Supply voltage I O 1 71 1 8 1 89 V Supply voltage I O 1 71 1 8 1 89 V AVpLL2 Supply voltage I O 1 71 1 8 189 V VREFSSTL Reference voltage 0 49DVppi8 0 50DVppi8 0 51 DVppi8 V DVppis Supply voltage 1 8 V operation 1 71 1 8 189 V required only for EMAC RGMII 1 5 V operation 1 43 1 5 157 V 1 8 V operation 0 855 0 9 0 945 V VrerHst Reference voltage 1 5 V operation 0 713 0 75 0 787 V PIEVI Supply voltage PLL 1 71 1 8 189 V Submit Documentation Feedback Device Operating Conditions 101 SM320C6455 EP Wy TEXAS FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Recommended Operating Conditions continued MIN NOM MAX UNIT Vss Supply ground 0 0 0 V 3 3 V pins except PCI capable and 2 V 2 pins PCI capable 0 5DVppss DVppss 0 5 V Vin High level input volt
236. d Frames Register 206 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 72 EMAC Statistics Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 020810230 RAOGTETS E Ei d in good frames 0208 0234 TXGOODFBAMES 02 8 0238 TXBCASTFRAMES Broadcast Transmit Frames Register 02C8 023G TXMCASTFRAMES Multicast Transmit Frames Register 02C8 0240 TXPAUSEFRAMES Pause Transmit Frames Register 02C8 0244 TXDEFERRED Deferred Transmit Frames Register 02C8 0248 TXCOLLISION Transmit Collision Frames Register 02C8 024G TXSINGLECOLL Transmit Single Collision Frames Register 02C8 0250 TXMULTICOLL Transmit Multiple Collision Frames Register 02C8 0254 TXEXCESSIVECOLL Transmit Excessive Collision Frames Register 02C8 0258 TXLATECOLL Transmit Late Collision Frames Register 02C8 025G TXUNDERRUN Transmit Underrun Error Register 02C8 0260 TXCARRIERSENSE Transmit Carrier Sense Errors Register 02C8 0264 TXOCTETS Transmit Octet Frames Register 02C8 0268 FRAME64 Transmit and Receive 64 Octet Frames Register 02C8 026G FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register 02C8 0270 FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register 02C8 0274 FRAME256T51 1 T
237. d data previously prefetched into the 5 15 read FIFO 2 ldis HSTBH HDV Disable time HD high impedance from HSTROBE high 1 4 ns 3 len HSTBL HD Enable time HD driven from HSTROBE low 3 15 ns 4 ta HSTBL HRDYH Delay time HSTROBE low to HRDY high 12 ns 5 ta HSTBH HRDYH Delay time HSTROBE high to HRDY high 12 ns Case 1 HPID read with no 10 20 TET Delay time HSTROBE low to auto increment kie eee ene HRDY low Case 2 HPID read with auto increment 10 M 20 and read FIFO initially empty 9 7 ta HDV HRDYL Delay time HD valid to HRDY low 0 ns wn asco Case 1 HPIA write 9 5 M 20 4 Delay time HSTROBE high to 3 td DSH HRDYL HRDY low Case 2 HPID write with no 5 M 20 ns auto increment 9 Delay time HSTROBE low to HRDY low for HPIA write and FIFO not 35 td HSTBL HRDYL pice 40 20 ns 36 ty HASL HRDYH Delay time HAS low to HRDY high 12 ns 1 M SYSCLKS period 6 CPU clock frequency in ns For example when running parts at 1000 MHz use M 6 ns 2 HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS 3 Assumes the HPI is accessing L2 L1 memory and no other master is accessing the same memory location Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 181 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 20
238. de of the EMAC conforms to the RMII Specification revision 1 2 as written by the RMII Consortium As the name implies the Reduced Media Independent Interface RMII mode is a reduced pin count version of the MII mode Interface Mode Select The EMAC uses the same pins for the MII GMII and RMII modes Standalone pins are included for the RGMII mode due to specific voltage requirements Only one mode can be used at a time The mode used is selected at device reset based on the MACSEL 1 0 configuration pins for more detailed information see Section 3 Device Configuration Table 7 70 shows which multiplexed pins are used in the MII GMII and RMII modes on the EMAC For a detailed description of these pin functions see Table 2 3 Terminal Functions Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 201 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 70 EMAC MDIO Multiplexed Pins MII RMII and GMII Modes 202 TExAS INSTRUMENTS www ti com BALL NUMBER DEVICE PIN NAME MII RMII GMII MAC SEL MAC SEL MAC SEL 00b 01b 10b J2 URDATAO MRXDO RMRXDO MRXDO RMRXDO MRXDO H3 URDATA1 MRXD1 RMRXD1 MRXD1 RMRXD1 MRXD1 J1 URDATA2 MRXD2 MRXD2 MRXD2 J8 URDATA3 MRXD3 MRXD3 MRXD3 L1 URDATA4 MRXD4 MRXD4 L2 URDATA5 MRXD5 MRXD5
239. e Table 7 60 Switching Characteristics Over Recommended Operating Conditions for McBSP 2 see Figure 7 52 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX Delay time CLKS high to CLKR X high for internal CLKR X generated from CLKS input 9 1 4 10 ms 2 te CKRX Cycle time CLKR X CLKR X int or 10 9 9 6 ns 1 CLKRP CLKXP FSRP FSXP 0 If polarity of any of the signals is inverted then the timing references of that signal are also inverted Minimum delay times also represent minimum output hold times 3 The CLKS signal is shared by both McBSPO and McBSP1 on this device Minimum CLKR X cycle times must be met even when CLKR X is generated by an internal clock source Minimum CLKR X cycle times are based on internal logic speed the maximum usable speed may be lower due to EDMA limitations and AC timing requirements 5 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns Use whichever value is greater Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 193 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 60 Switching Characteristics Over Recommended Operating Conditions for McBSP see Figure 7 52 continued 720 850 NO PARAMETER
240. e imaging medical and wireless infrastructure WI The C64x devices are upward code compatible from previous devices that are part of the C6000 DSP platform Based on 90 nm process technology and with performance of up to 9600 million instructions per second MIPS or 9600 16 bit MMACs per cycle at a 1 2 GHz clock rate the C6455 device offers cost effective solutions to high performance DSP programming challenges The C6455 DSP possesses the operational flexibility of high speed controllers and the numerical capability of array processors Features Submit Documentation Feedback Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 The C64x DSP core employs eight functional units two register files and two data paths Like the earlier C6000 devices two of these eight functional units are multipliers or M units Each C64x M unit doubles the multiply throughput versus the C64x core by performing four 16 bit x 16 bit multiply accumulates MACs every clock cycle Thus eight 16 bit x 16 bit MACs can be executed every cycle on the C64x core At a 1 2 GHz clock rate this means 9600 16 bit MMACs can occur every second Moreover each multiplier on the C64x core can compute one 32 bit x 32 bit MAC or four 8 bit x 8 bit MACs every clock cycle The C6455 device includes Serial RapidlO This high bandwidth peripheral dramatically improves system performan
241. e 7 90 Timing Requirements for MDIO Input R G MII see Figure 7 71 720 850 NO A 1000 1000 UNIT 1200 MIN MAX 1 te MDCLK Cycle time MDCLK 400 ns 2a tw MDCLK Pulse duration MDCLK high 180 ns 2b tw MDCLK Pulse duration MDCLK low 180 ns 3 tt MDCLK Transition time MDCLK 5 ns 4 tsu MDIO MDCLKH Setup time MDIO data input valid before MDCLK high 10 ns th MDCLKH MDIO Hold time MDIO data input valid after MDCLK high 10 ns 1 MDCLK fF fF 4 27 4 MDIO XXXXXX xX XX input KKK RR RY SSE EEE Figure 7 71 MDIO Input Timing Table 7 91 Switching Characteristics Over Recommended Operating Conditions for MDIO Output see Figure 7 72 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 7 ta MDCLKL MDIO Delay time MDCLK low to MDIO data output valid 100 ns 1 MDCLK uu nx i MEN 4 1 MDIO YY XXX XK XK N N N N N N YY YY XXX XK X KX XXY X V Y Y YY V Y Y Y re EE MAN Figure 7 72 MDIO Output Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 217 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 uk 7 15 Timers The timers can be used to t
242. e EMIFA For example if master A passes a software message via a buffer in external memory and does not wait for indication that the write completes when master B attempts to read the software message then the master B read may bypass the master A write and thus master B may read stale data and therefore receive an incorrect message Some master peripherals e g transfer controllers always wait for the write to complete before signaling an interrupt to the system thus avoiding this race condition For masters that do not have hardware guarantee of write read ordering it may be necessary to guarantee data ordering via software If master A does not wait for indication that a write is complete it must perform the following workaround 1 Perform the required write 2 Perform a dummy write to the EMIFA module ID and revision register 3 Perform a dummy read to the EMIFA module ID and revision register 4 Indicate to master B that the data is ready to be read after completion of the read in step 3 The completion of the read in step 3 ensures that the previous write was done 162 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 10 2 Peripheral Register Description s Table 7 41 EMIFA Registers
243. e Maximum Ratings Over Operating Case Temperature Range Unless Otherwise Noted Supply voltage range CVpp 0 5 V to 1 5 V DVppss 2 0 5 V to 4 2 V DVppRn 2 2 0 5 V to 2 5 V DVpp s 2 0 5 V to 2 5 V DVpp12 AVppa 2 0 5 V to 1 5 V PLLV1 PLLV2 0 5 V to 2 5 V Input voltage Vi range 3 3 V pins except PCI capable pins 0 5 V to DVppsas 0 5 V PCI capable pins 0 5 V to DVppss 0 5 V RGMII pins 0 5 V to 2 5 V DDR2 memory controller pins 0 5 V to 2 5 V Output voltage Vo range 3 3 V pins except PCI capable pins 0 5 V to DVpp33 0 5 V PCI capable pins 0 5 V to DVppsas 0 5 V RGMII pins 0 5 V to 2 5 V DDR2 memory controller pins 0 5V 10 2 5 V Operating case temperature range Tc default temperature 0 C to 90 C A temperature 40 C to 105 C 5 temperature 55 to 105 C Storage temperature range Tstg 65 C to 150 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 All voltage values are with respe
244. e last reset to occur Warm Reset was the last reset to occur 0 POR Power on reset 0 Power on Reset was not the last reset to occur Power on Reset was the last reset to occur 132 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 6 8 Reset Electrical Data Timing Table 7 14 Timing Requirements for Reset Osee Figure 7 8 and Figure 7 9 720 850 NO A 1000 1000 UNIT 1200 MIN MAX twiPoR Pulse duration POR low 256D 4 ns tw RESET Pulse duration RESET low 24C ns 7 t Setup time boot mode and configuration pins valid before POR high or 6P su bool RESET high 9 d 8 t Hold time boot mode and configuration pins valid after POR high or 6P h bool RESET high 9 ng 1 C 1 CLKIN1 clock frequency in ns D 1 CLKIN2 clock frequency in ns 3 P 1 CPU clock frequency in nanoseconds ns Note that after power on reset warm reset and max reset the CPU frequency is equal to the CLKIN1 frequency divided by three due to the PLL1 controller being reset see Section 7 6 Reset Controller If CLKIN2 is not used typog must be measured in terms of CLKIN1 cycles otherwise use CLKIN2 cycles 5 AEA 19 0 ABA 1 0 and are the boot configuration pins during device rese
245. e low period tw scLL of the SCL signal 5 total capacitance of one bus line in pF If mixed with HS mode devices faster fall times are allowed 176 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 e n 90 k L1 1 LX XT NC N MT LaL kH 8 6 14 M 1 8 le 5 lt c le 1 k 12 e7 NEM Stop Start Repeated Stop Start Figure 7 42 2 Receive Timings Table 7 53 Switching Characteristics for I2C Timings see Figure 7 43 720 850 A 1000 1000 NO PARAMETER 1200 UNIT STANDARD MODE FAST MODE MIN MAX MIN MAX 16 le scL Cycle time SCL 10 2 5 us Delay time SCL high to SDA low for a 17 iatSoLH SDAL repeated START condition d 0 6 us Delay time SDA low to SCL low for a START 18 la SpAL sSCLL and a repeated START condition i 0 6 us 19 tw SCLL Pulse duration SCL low 4 7 1 3 us 20 tw SCLH Pulse duration SCL high 4 0 6 us 21 la SDAV SDLH Delay time SDA valid to SCL high 250 100 ns Valid time SDA valid after SCL low For 2 22 L SDLL SDAV bus devices 0 0 0 9 ps Pulse duration SDA high between STOP and 23 lw sDAH
246. e protection scheme see Table 5 1 Table 5 1 Available Memory Page Protection Schemes AIDO Bit LOCAL Bit Description 0 0 No access to memory page is permitted 0 1 Only direct access by CPU is permitted 1 0 Only accesses by system masters and IDMA are permitted includes EDMA and IDMA accesses initiated by the CPU 1 1 All accesses permitted 5 3 90 For more information on memory protection for L1D L1P and L2 see the TMS320C64x Megamodule Reference Guide literature number SPRU871 Bandwidth Management When multiple requestors contend for a single C64x Megamodule resource the conflict is solved by granting access to the highest priority requestor The following four resources are managed by the Bandwidth Management control hardware e Level 1 Program L1P SRAM Cache e Level 1 Data L1D SRAM Cache Level 2 L2 SRAM Cache Memory mapped registers configuration bus The priority level for operations initiated within the C64x Megamodule e g CPU initiated transfers user programmed cache coherency operations and IDMA initiated transfers are declared through registers in the C64x Megamodule The priority level for operations initiated outside the C64x Megamodule by system peripherals is declared through the Priority Allocation Register PRI ALLOC see Section 4 4 System peripherals with no fields in PRI ALLOC have their own registers to program their priorities More inf
247. e sections is not supported by the C6455 DSP TMS320C6455 DSP SYSCLK3 From PLL1 Controller SYSCLK2 From PLL1 Controller DDR2 Memory Controller 2 90 DIVIDER D1 1 SYSREFCLK ee A must be programmed to 2 for default and to 5 for RGMII B If EMAC is enabled with RGMII or CLKIN2 frequency must be 25 MHz 2 is a 3 3 V signal Figure 7 23 PLL2 Block Diagram Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 151 SM320C6455 EP R3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 www ti com 7 8 1 PLL2 Controller Device Specific Information 7 8 1 1 Internal Clocks and Maximum Operating Frequencies As shown in Figure 7 23 the output of PLL2 PLLOUT is divided by 2 and directly fed to the DDR2 memory controller This clock is used by the DDR2 memory controller to generate DDR2CLKOUT and DDR2CLKOUT Note that internally the data bus interface of the DDR2 memory controller is clocked by SYSCLK of the PLL1 controller The PLLOUT 2 clock is also fed back into the PLL2 controller where it becomes SYSREFCLK Divider D1 of the PLL2 controller generates SYSCLK1 for the Ethernet media access controller EMAC The EMAC uses SYSCLK1 to generate the necessary clock for each of its interfaces Divider D1 should
248. e that valid logic levels are latched on these device configuration pins In addition applying external pullup pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes Tips for choosing an external pullup pulldown resistor Consider the total amount of current that may pass through the pullup or pulldown resistor Make sure to include the leakage currents of all the devices connected to the net as well as any internal pullup or pulldown resistors e Decide a target value for the net For a pulldown resistor this should be below the lowest Vi level of all inputs connected to the net For a pullup resistor this should be above the highest Vj level of all inputs on the net A reasonable choice would be to target the Vo or Vor levels for the logic family of the limiting device which by definition have margin to the Vi and Vj levels e Select a pullup pulldown resistor with the largest possible value but which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor The current to be considered includes leakage current plus any other internal and external pullup pulldown resistors on the net e For bidirectional nets there is an additional consideration that sets a lower limit on the resistance value of the external resistor Verify that the resistance is small enough
249. e two 32 bit HPIA registers HPIAR for read operations and HPIAW for write operations The HPI can be configured such that HPIAR and HPIAW act as a single 32 bit HPIA single HPIA mode or as two separate 32 bit HPIAs dual HPIA mode from the perspective of the host The CPU can access HPIAW and HPIAR independently For details about the HPIA registers and their modes see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 179 SM320C6455 EP 49 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 12 3 HPI Electrical Data Timing Table 7 55 Timing Requirements for Host Port Interface Cycles see Table 7 56 through Figure 7 51 720 850 NO A 1000 1000 UNIT 1200 MIN MAX 9 tsu HASL HSTBL Setup time HAS low before HSTROBE low 5 ns 10 th HSTBL HASL Hold time HAS low after HSTROBE low 2 ns 11 su SELV HASL Setup time select signals valid before HAS low 5 ns 12 in HASL SELV Hold time select signals valid after HAS low 5 ns 13 tw HSTBL Pulse duration HSTROBE low 15 ns 14 tw HSTBH Pulse duration HSTROBE high between consecutive accesses 2M ns 15 Isu SELV HSTBL Setup time select signals valid before HSTROBE low 5 ns 16 in HSTBL SELV Hold time select signals valid after H
250. ed UTOPIA_EN AEA12 pin 0 this pin is EMAC MII default or receive clock MACSEL 1 0 dependent Receive cell available status output signal from UTOPIA Slave 0 indicates NO space is available to receive a cell from Master ATM Controller URCLAV MCRS J4 VO Z 1 indicates space is available to receive a cell from Master ATM Controller RMCRSDV When the UTOPIA peripheral is disabled UTOPIA EN AEA12 pin 0 this pin is EMAC MII carrier sense default or RMII carrier sense data valid or GMII carrier sense MACSEL 1 0 dependent MACSEL 1 0 dependent UTOPIA receive interface enable input signal Asserted by the Master ATM Controller to indicate to the UTOPIA Slave to sample the Receive Data Bus URENB MRXDV H5 VO Z URDATA 7 0 and URSOC signal in the next clock cycle or thereafter When the UTOPIA peripheral is disabled UTOPIA_EN AEA12 pin 0 this pin is EMAC MII default or receive data valid MACSEL 1 0 dependent Receive Start of Cell signal This signal is output by the Master ATM Controller to indicate to the UTOPIA Slave that the first valid byte of the cell is available to URSOC MRXER H4 VO Z sample on the 8 bit Receive Data Bus URDATA 7 0 RMRXER When the UTOPIA peripheral is disabled UTOPIA EN AEA12 pin 0 this pin is EMAC MII default or RMII or GMII receive error MACSEL 1 0 dependent URADDR4 PCBE0 P1 UTOPIA receive address pins URADDR 4 0 1 GP 2 As UTOPIA receive address pins U
251. ed as dictated by the DEVSTAT register The DDR2 Memory Controller and EMIFA registers retain their previous values Only the DDR2 Memory Controller and EMIFA state machines are reset by the System Reset The PLL controllers are operating in the mode prior to System Reset System clocks unaffected The boot sequence is started after the system clocks are restarted Since the configuration pins including the BOOTMODE 3 0 pins are not latched with a System Reset the previous values as shown in the DEVSTAT register are used to select the boot mode 7 6 5 CPU Reset A CPU Reset is initiated by the HPI or PCI peripheral This reset only affects the CPU During a PCl initiated CPU Reset the PCI pins are set to their reset state With the exception of the HRDY PIRDY pin the PCI pins have a reset state of high impedance the HRDY PIRDY pin goes high during reset 130 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 6 6 Reset Priority If any of the above reset sources occur simultaneously the PLLCTRL only processes the highest priority reset request The rest request priorities are as follows high to low e Power on Reset e Maximum Reset e Warm Reset e System Reset e CPU Reset Submit Documentation Feedback C64x Peripheral Information and Elec
252. ed before the instruction is executed 31 30 29 24 SRIOCTL Reserved R W 0 R W 0 23 22 21 20 19 18 17 16 Reserved UTOPIACTL Reserved PCICTL Reserved HPICTL Reserved McBSP1CTL R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 Reserved McBSPOCTL Reserved I2CCTL Reserved GPIOCTL Reserved TIMER1CTL R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 Reserved TIMEROCTL Reserved EMACCTL Reserved VCPCTL Reserved TCPCTL R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write only n value after reset Figure 3 4 Peripheral Configuration Register 0 PERCFGO 0 02 0008 Table 3 7 Peripheral Configuration Register 0 PERCFGO Field Descriptions Bit Field Value Description 31 30 SRIOCTL Mode control for SRIO SRIO does not have a corresponding status bit in the Peripheral Status Registers Once SRIOCTL is set to 11b the SRIO peripheral can be used within 16 SYSCLK3 cycles 00b Set SRIO to disabled mode 11b Set SRIO to enabled mode 29 23 Reserved Reserved 22 UTOPIACTL Mode control for UTOPIA 0 Set UTOPIA to disabled mode 1 Set UTOPIA to enabled mode 21 Reserved Reserved 20 PCICTL Mode control for PCI This bit defaults to 1 when Host boot is used BOOTMODE 3 0 0111b 0 Set PCI to disabled mode 1 Set PCI to enabled mode 19 Reserved Reserved 18 HPICTL Mode control for HPI This bit defaults to 1 when Host boot is used BOOTMODE 3 0 0001
253. ed end use failure rate still is undefined Only qualified production devices are to be used Submit Documentation Feedback Device Overview 55 SM320C6455 EP 9 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 www ti com TI device nomenclature also includes a suffix with the device family name This suffix indicates the package type for example ZTZ the temperature range for example blank is the default commercial temperature range and the device speed range megahertz for example blank is 1000 MHz 1 GHz Figure 2 13 provides a legend for reading the complete device name for any C64x DSP generation member For device part numbers and further ordering information for SM320C6455 EP in the ZTZ GTZ package type see the TI website www ti com or contact your TI sales representative TMS 320 C6455 B 272 2 EP PREFIX L MILITARY ENHANCED PRODUCT TMX Experimental device SM Qualified device DEVICE SPEED RANGE 7 720 MHz 8 850 MHz DEVICE FAMILY Blank 1 GHz 320 TMS320 DSP family 2 1 2 GHz SM HiRel non 38535 TEMPERATURE RANGE Blank 0 C to 90 C default commercial temperature DEVICE A 40 C to 105 C extended temperature C64x DSP 5 55 C to 105 C extended temperature C6455 PACKAGE TYPE ZTZ 697 pin plastic BGA with Pb Free solder balls GTZ 697 pin plastic BGA with Pb ed solder balls SILICON REVISION B
254. edback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 5 9 Megamodule L1 L2 Memory Protection Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 A648 18 L1P memory protection page attribute register 18 0184 A64C L1PMPPA19 L1P memory protection page attribute register 19 0184 A650 L1PMPPA20 L1P memory protection page attribute register 20 0184 A654 21 L1P memory protection page attribute register 21 0184 A658 L1PMPPA22 L1P memory protection page attribute register 22 0184 A65C L1PMPPA23 L1P memory protection page attribute register 23 0184 A660 L1PMPPA24 L1P memory protection page attribute register 24 0184 A664 L1PMPPA25 L1P memory protection page attribute register 25 0184 A668 L1PMPPA26 L1P memory protection page attribute register 26 0184 A66C L1PMPPA27 L1P memory protection page attribute register 27 0184 A670 L1PMPPA28 L1P memory protection page attribute register 28 0184 A674 L1PMPPA29 L1P memory protection page attribute register 29 0184 A678 L1PMPPA30 L1P memory protection page attribute register 30 0184 A67C L1PMPPA31 L1P memory protection page attribute register 31 0184 A680 0184 ABFF Reserved 0184 ACOO L1DMPFAR L1 data L1D memory protection fault address regist
255. eference Guide literature number SPRU871 And for more detailed information on device resets see Section 7 6 Reset Controller Submit Documentation Feedback C64x4 Megamodule 91 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 5 6 Megamodule Revision The version and revision of the C64x Megamodule can be read from the Megamodule Revision ID Register MM REVID located at address 0181 2000h The MM REVID register is shown in Figure 5 5 and described in Table 5 3 The C64x Megamodule revision is dependant on the silicon revision being used For more information see the TMS320C6455 Digital Signal Processor Silicon Errata literature number SPRZ234 31 16 15 0 VERSION REVISION R 1h R n LEGEND R Read only n value after reset A The C64x Megamodule revision is dependant on the silicon revision being used For more information see the TMS320C6455 Digital Signal Processor Silicon Errata literature number SPRZ234 Figure 5 5 Megamodule Revision ID Register MM REVID Hex Address 0181 2000h Table 5 3 Megamodule Revision ID Register MM REVID Field Descriptions Bit Field Value Description 31 16 VERSION th Version of the C64x Megamodule implemented on the device This field is always read as 1h 15 00 REVISION Revision of the C64x Megamodule version implemented on
256. eld Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 1 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 GOSET GO operation command for SYSCLK rate change and phase alignment Before setting this bit to 1 to initiate a GO operation check the GOSTAT bit in the PLLSTAT register to ensure all previous GO operations have completed 0 No effect Write of 0 clears bit to 0 Initiates GO operation Write of 1 initiates GO operation Once set GOSET remains set but further writes of 1 can initiate the GO operation Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 145 SM320C6455 EP 9 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 7 3 7 PLL Controller Status Register The PLL controller status register PLLSTAT shows the PLL controller status PLLSTAT is shown in Figure 7 17 and described in Table 7 25 31 16 R 0 15 1 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Figure 7 17 PLL Controller Status Register PLLSTAT Hex Address 029A 013C Table 7 25 PLL Controller Status Register PLLSTAT Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit
257. ent Register High 02A0 1040 SECR Secondary Event Clear Register 02A0 1044 SECRH Secondary Event Clear Register High 02A0 1048 02A0 104C Reserved 02A0 1050 IER Interrupt Enable Register 02A0 1054 IERH Interrupt Enable High Register 02A0 1058 IECR Interrupt Enable Clear Register 02A0 105C IECRH Interrupt Enable Clear High Register 02A0 1060 IESR Interrupt Enable Set Register 02A0 1064 IESRH Interrupt Enable Set High Register 02A0 1068 IPR Interrupt Pending Register 02A0 106C IPRH Interrupt Pending High Register 02A0 1070 ICR Interrupt Clear Register 02A0 1074 ICRH Interrupt Clear High Register 02A0 1078 IEVAL Interrupt Evaluate Register 02A0 107C Reserved 02A0 1080 QER QDMA Event Register 02A0 1084 QEER QDMA Event Enable Register 02A0 1088 QEECR QDMA Event Enable Clear Register 02A0 108C QEESR QDMA Event Enable Set Register 02A0 1090 QSER QDMA Secondary Event Register 02A0 1094 QSECR QDMA Secondary Event Clear Register 02A0 1098 02A0 1FFF Reserved Shadow Region 0 Channel Registers 02A0 2000 ER Event Register 02A0 2004 ERH Event Register High 02A0 2008 ECR Event Clear Register 116 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007
258. ents for McBSP 1 see Figure 7 52 720 850 NO A 1000 1000 UNIT 1200 MIN MAX 2 Cycle time CLKR X CLKR X ext or 100 9 ns tw CKRX Pulse duration CLKR X high or CLKR X low CLKR X ext O 5tcckmx 71 9 ns CLKR int 9 5 tsu FRH CKRL Setup time external FSR high before CLKR low CLKR ext is ns CLKR int 6 th CKRL FRH Hold time external FSR high after CLKR low CLKR ext 3 ns 7 Setup time DR valid before CLKR low ns CLKR ext 0 9 f CLKR int 3 8 th CKRL DRV Hold time DR valid after CLKR low ext 34 ns 10 tsu FXH CKXL Setup time external FSX high before CLKX low 2 ns CLKX ext 1 3 11 th CKXL FXH Hold time external FSX high after CLKX low B ns CLKX ext 3 1 CLKRP CLKXP FSRP FSXP 0 If polarity of any of the signals is inverted then the timing references of that signal are also inverted P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use 1 ns 3 Use whichever value is greater Minimum CLKR X cycle times must be met even when CLKR X is generated by an internal clock source The minimum CLKR X cycle times are based on internal logic speed the maximum usable speed may be lower due to EDMA limitations and AC timing requirements 4 This parameter applies to the maximum McBSP frequency Operate serial clocks CLKR X in the reasonable range of 40 60 duty cycl
259. er 0184 AC04 L1DMPFSR L1D memory protection fault status register 0184 ACO8 L1DMPFCR L1D memory protection fault command register 0184 ACOC 0184 ACFF Reserved 0184 ADOO L1DMPLKO L1D memory protection lock key bits 31 0 0184 AD04 L1DMPLK1 L1D memory protection lock key bits 63 32 0184 ADO8 L1DMPLK2 L1D memory protection lock key bits 95 64 0184 ADOC L1DMPLK3 L1D memory protection lock key bits 127 96 0184 AD10 L1DMPLKCMD L1D memory protection lock key command register 0184 AD14 L1DMPLKSTAT L1D memory protection lock key status register 0184 AD18 0184 ADFF Reserved 0184 AE00 0184 AE3C 9 Reserved 0184 AE40 L1DMPPA16 L1D memory protection page attribute register 16 0184 AE44 L1DMPPA17 L1D memory protection page attribute register 17 0184 AE48 L1DMPPA18 L1D memory protection page attribute register 18 0184 AE4C L1DMPPA19 L1D memory protection page attribute register 19 0184 AE50 L1DMPPA20 L1D memory protection page attribute register 20 0184 AE54 L1DMPPA21 L1D memory protection page attribute register 21 0184 AE58 L1DMPPA22 L1D memory protection page attribute register 22 0184 5 L1DMPPA23 L1D memory protection page attribute register 23 0184 AE60 L1DMPPA24 L1D memory protection page attribute register 24 0184 AE64 L1DMPPA25 L1D memory protection page attribute register 25 0184 AE68 L1DMPPA26 L1D memory protection page attribute register 26 0184 AE6C L1DMPPA27 L1D memory protection page attribute register 27 0184 AE70 L1DMPPA28
260. er has one of three prefixes TMX TMP or TMS e g TMS320C6455ZTZ Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS Device development evolutionary flow TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped with against the following disclaimer Developmental product is intended for internal evaluation purposes TMS devices and TMDS development support tools have been characterized fully and the quality and reliability of the device have been demonstrated fully Tl s standard warranty applies Predictions show that prototype devices TMX or TMP have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expect
261. ernet Media Access Controller EMAC and Physical layer PHY device Management Data Input Output MDIO module integrated with the devices of the C645x family TMS320C645x DSP External Memory Interface EMIF User s Guide This document describes the operation of the external memory interface EMIF in the digital signal processors DSPs of the C645x DSP family TMS320C645x DSP General Purpose Input Output GPIO User s Guide This document describes the general purpose input output GPIO peripheral in the digital signal processors DSPs of the C645x DSP family The GPIO peripheral provides dedicated general purpose pins that can be configured as either inputs or outputs When configured as an input you can detect the state of the input by reading the state of an internal register When configured as an output you can write to an internal register to control the state driven on the output pin TMS320C645x DSP Host Port Interface HPI User s Guide This guide describes the host port interface HPI on the C645x digital signal processors DSPs The HPI enables an external host processor host to directly access DSP resources including internal and external memory using a 16 bit 16 or 32 bit HPI32 interface TMS320C645x DSP Inter Integrated Circuit I2C Module User s Guide This document describes the inter integrated circuit I2C module in the C645x Digital Signal Processor DSP The 2 provides an interface between the C6
262. erview 23 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 2 6 Signal Groups Description Clock PLL1 RM PLL Ce n T sasaw NM ontroller Interrupts POR CLKIN2 5 Clock PLL2 RSV02 TMS RSV03 TDO RSV04 TDI RSV05 TCK RSV07 TRST RSV09 Reserved IEEE Standard EMU0 1149 1 EMU1 JTAG RSV42 Emulation RSV43 RSV44 e EMU14 EMU15 EMU16 EMUI Enable Disable EMU18 Control Status A This pin functions as GP 1 by default For more details see the Device Configuration section of this document Figure 2 6 CPU and Peripheral Signals 24 Device Overview Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 TOUTLO TINPLI Timer 1 Timero TOUTL1 lt TINPL0 Timers 64 Bit URADDR3 PREQ GP 15 4 gt lt 7 URADDR2 PINTA GP 14 O 4 lt gt 6 URADDR1 PRST GP 13 4 lt GP 5 URADDRO PGNT GP 12YO 4 gt lt GP 4 FSX1 GP 11 8 4 gt lt gt FSR1 GP 10 4 gt lt gt URADDR4 PCBEU GP 2 O DX1 GP 9 B 4 lt gt SYSCLK4 GP 1 4 DR1 GP 8 4 gt 4 gt CLKR1 GP OJB General Purpose Input Output 0 GPIO Port 4 RIOTX 3 0 lt 5 4 RIOCLK RIOTX 3 0
263. ess 029C 0118 Table 7 33 PLL Controller Divider 1 Register PLLDIV1 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 D1EN Divider D1 enable bit 0 Divider D1 is disabled No clock output 1 Divider D1 is enabled 14 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 RATIO O 1Fh Divider ratio bits th 2 Divide frequency by 2 4h 5 Divide frequency by 5 Others Reserved 154 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 8 3 2 PLL Controller Command Register The PLL controller command register PLLCMD contains the command bit for GO operation PLLCMD is shown in Figure 7 25 and described in Table 7 34 31 16 Reserved R 0 15 2 1 0 Reserved Rsvd GOSET R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 7 25 PLL Controller Command Register PLLCMD Hex Address 029C 0138 Table 7 34 PLL Controller Command Register PLLCMD Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved The reserved bit location is alway
264. ess location See Section 5 6 Megamodule Revision Revision ID 0181 2000h See Section 3 6 JTAG ID JTAGID Register JTAG BSDL_ID register address location 0x02A80008 Description Frequency MHz 720 850 1000 1 GHz and 1200 1 2 GHz 1 39 ns C6455 720 1 17 ns C6455 850 Cycle Time ns 1 ns C6455 A 1000 1000 1 GHz CPU 0 83 ns C6455 1200 1 2 GHz CPU 1 25 V A 1000 1000 1200 Core V 1 2 V 850 720 Voltage 1 25 1 2 RapidlO V 1 5 1 8 EMAC RGMII and 1 8 and 3 3 V I O Supply Voltage PLL1 and PLL1 Controller Options CLKIN1 frequency multiplier Bypass x1 x15 x20 x25 x30 x32 PLL2 CLKIN2 frequency multiplier DDR2 Memory Controller and EMAC support only x20 BGA Package 24 x 24 mm 697 Pin Flip Chip Plastic BGA ZTZ 697 Pin Flip Chip Plastic BGA GTZ 1 The extended temperature device s A 1000 electrical characteristics and ac timings are the same as those for the corresponding commercial temperature devices 1000 Submit Documentation Feedback Device Overview 11 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 www ti com Table 2 1 Characteristics of the C6455 Processor continued HARDWARE FEATURES C6455 Process Technology um 0 09 um 2 Product Preview PP Advance Information Al Product Status or Pr
265. et During these resets the PLL2 controller registers get reset to their default values The internal clocks of the PLL2 controller are also affected as described in Section 7 6 Reset Controller PLL2 is only unlocked during the power up sequence see Section 7 6 Reset Controller and is locked by the time the RESETSTAT pin goes high It does not lose lock during any of the other resets 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 8 2 PLL2 Controller Memory Map The memory map of the PLL2 controller is shown in Table 7 32 Note that only registers documented here are accessible on the C6455 Other addresses in the PLL2 controller memory map should not be modified Table 7 32 PLL2 Controller Registers HEX ADDRESS RANGE ACRONYM DESCRIPTION 029C 0000 029C 0114 Reserved 029C 0118 PLLDIV1 PLL Controller Divider 1 Register 029 011C 029 0134 Reserved 029C 0138 PLLCMD PLL Controller Command Register 029C 013G PLLSTAT PLL Controller Status Register 029C 0140 ALNCTL PLL Controller Clock Align Control Register 029C 0144 DCHANGE PLLDIV Ratio Change Status Register 029C 0148 Reserved 029C 014G Reserved 029C 0150 SYSTAT SYSCLK Status Register 029 0154 029 0190 Reserved 029 0194 029 0
266. eue Transmit DMA Completion Pointer Register 5 02D0 0598 RIO QUEUE6 TXDMA CP Queue Transmit DMA Completion Pointer Register 6 0200 059C RIO QUEUE7 TXDMA CP Queue Transmit DMA Completion Pointer Register 7 02D0 05A0 RIO QUEUE8 TXDMA CP Queue Transmit DMA Completion Pointer Register 8 02D0 05A4 RIO QUEUE9 TXDMA CP Queue Transmit DMA Completion Pointer Register 9 02D0 05A8 RIO QUEUE10 TXDMA CP Queue Transmit DMA Completion Pointer Register 10 0200 05AC RIO QUEUE11 TXDMA CP Queue Transmit DMA Completion Pointer Register 11 0200 05BO RIO QUEUE12 TXDMA CP Queue Transmit DMA Completion Pointer Register 12 02D0 05B4 RIO QUEUE13 TXDMA CP Queue Transmit DMA Completion Pointer Register 13 0200 05B8 RIO QUEUE14 TXDMA CP Queue Transmit DMA Completion Pointer Register 14 02D0 05BC RIO QUEUE15 TXDMA CP Queue Transmit DMA Completion Pointer Register 15 0200 05DO 0200 05FC Reserved 0200 0600 RIO QUEUEO RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 0 02D0 0604 RIO QUEUE1 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 1 0200 0608 RIO QUEUE2 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 2 02D0 060C RIO QUEUE3 RXDMA HDP Queue Receive DMA Head Descriptor Pointer Register 3 238 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 112
267. ew instructions such as 32 bit multiplications complex multiplications packing sorting bit manipulation and 32 bit Galois field multiplication Exception Handling Intended to aid the programmer in isolating bugs The C64x CPU is able to detect and respond to exceptions both from internally detected sources such as illegal op codes and from system events such as a watchdog time expiration e Privilege Defines user and supervisor modes of operation allowing the operating system to give a basic level of protection to sensitive resources Local memory is divided into multiple pages each with read write and execute permissions Time Stamp Counter Primarily targeted for Real Time Operating System RTOS robustness a free running time stamp counter is implemented in the CPU which is not sensitive to system stalls For more details on the C64x CPU and its enhancements over the C64x architecture see the following documents TMS320C64x C64x DSP CPU and Instruction Set Reference Guide literature number SPRU732 TMS320C64x DSP Cache User s Guide literature number SPRU862 TMS320C64x Megamodule Reference Guide literature number SPRU871 TMS320C6455 Technical Reference literature number SPRU965 TMS320C64x to TMS320C64x CPU Migration Guide literature number SPRAA84 Submit Documentation Feedback Device Overview 13 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEM
268. from memory to the register file and store results from the register file into memory The C64x CPU extends the performance of the C64x core through enhancements and new features Each C64x M unit can perform one of the following each clock cycle one 32 x 32 bit multiply two 16 x 16 bit multiplies two 16 x 32 bit multiplies four 8 x 8 bit multiplies four 8 x 8 bit multiplies with add operations and four 16 x 16 multiplies with add subtract capabilities including a complex multiply There is also support for Galois field multiplication for 8 bit and 32 bit data Many communications algorithms such as FFTs and modems require complex multiplication The complex multiply CMPY instruction takes for 16 bit inputs and produces a 32 bit real and a 32 bit imaginary output There are also complex multiplies with rounding capability that produces one 32 bit packed output that contain 16 bit real and 16 bit imaginary values The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high precision algorithms on a variety of signed and unsigned 32 bit data types The L or Arithmetic Logic Unit now incorporates the ability to do parallel add subtract operations on a pair of common inputs Versions of this instruction exist to work on 32 bit data or on pairs of 16 bit data performing dual 16 bit add and subtracts in parallel There are also saturated forms of these instructions The C64x core enhances the S uni
269. fter URENB MRXDV H5 When the UTOPIA peripheral is disabled UTOPIA EN AEA12 pin 0 this pin is EMAC MII default or receive data valid MRXDV MACSEL 1 0 dependent 42 Device Overview Submit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE iPD IPU 2 DESCRIPTION NAME NO URDATA7 MRXD7 M2 URDATA6 MRXD6 H2 URDATA5 MRXD5 L2 UTOPIA 8 bit Receive Data Bus I default or EMAC receive data bus for MII default RMII or GMII URDATA4 MRXD4 L1 Using the Receive Data Bus the UTOPIA Slave on the rising edge of the URDATA3 MRXD3 J3 URCLK can receive the 8 bit ATM cell data from the Master ATM Controller URDATA2 MRXD2 J1 When the UTOPIA peripheral is disabled UTOPIA_EN AEA12 pin 0 these URDATA1 MRXD1 pins function as EMAC receive data pins for MII default or GMII BMRXD1 H3 MRXD x 0 I MACSEL 1 0 dependent URDATAO MRXDO J2 RMRXD0 Transmit cell available status output signal from UTOPIA slave O e 0 indicates a complete cell is NOT available for transmit UXCLAV GMTCLK K5 O Z e 1 indicates a complete cell is available for transmit When the UTOPIA peripheral is disabled UTOPIA EN AEA12 pin 0 this pin is EMAC GMII transmit clock GMTCLK O MACSEL 1 0 dependent UTOPIA transmit
270. gram Register 02 0 03E8 PCIBAR2TRLPRG PCI Base Address Translation Register 2 Program Register 02C0 03EC PCIBARSTRLPRG PCI Base Address Translation Register 3 Program Register 02 0 03F0 PCIBAR4TRLPRG PCI Base Address Translation Register 4 Program Register 02 0 03F4 PCIBAR5TRLPRG PCI Base Address Translation Register 5 Program Register 02C0 03F8 PCIBASENPRG PCI Base En Prog Register 02 0 03FC 02 0 O3FF Reserved Table 7 103 PCI External Memory Space HEX ADDRESS OFFSET ACRONYM REGISTER NAME 4000 0000 407F FFFF PCI Master Window 0 4080 0000 40FF FFFF PCI Master Window 1 4100 0000 417F FFFF PCI Master Window 2 4180 0000 41FF FFFF PCI Master Window 3 4200 0000 427F FFFF PCI Master Window 4 4280 0000 42FF FFFF PCI Master Window 5 4300 0000 437F FFFF PCI Master Window 6 4380 0000 43FF FFFF PCI Master Window 7 4400 0000 447F FFFF PCI Master Window 8 4480 0000 44FF FFFF PCI Master Window 9 4500 0000 457F FFFF PCI Master Window 10 4580 0000 45FF FFFF PCI Master Window 11 4600 0000 467F FFFF PCI Master Window 12 4680 0000 46FF FFFF PCI Master Window 13 4700 0000 477F FFFF PCI Master Window 14 4780 0000 47FF FFFF PCI Master Window 15 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 227 SM320
271. gured as PCI pins Submit Documentation Feedback Device Overview 41 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL TYPE iPD IPU DESCRIPTION NAME NO RAPIDIO SERIAL PORT RIOCLK AF15 RapidlO serial port source reference clock RIOCLK AG15 Negative RapidlO serial port source reference clock RIOTX3 AF17 RIOTX2 AG18 O Z RapidlO transmit data bus bits 3 0 differential RIOTX1 AG22 RIOTXO AF23 RIOTX3 AF18 RIOTX2 AG19 O Z RapidlO negative transmit data bus bits 3 0 differential RIOTX1 AG21 RIOTXO AF22 RIORX3 AH18 RIORX2 AJ18 7 RapidlO receive data bus bits 3 0 differential RIORX1 AJ22 RIORXO AH22 RIORX3 AH17 RIORX2 AJ19 RapidlO negative receive data bus bits 3 0 differential RIORX1 AJ21 RIORXO AH23 MANAGEMENT DATA INPUT OUTPUT MDIO FOR MII RMII GMII UTOPIA transmit address pin UXADDR4 1 4 or MDIO serial clock MDCLK UXADDR4 MDCLK M5 VO Z IPD for MII RMII RGMII mode O UTOPIA transmit address pin UXADDR3 I or MDIO serial data MDIO for UXADDRS MDIO N3 VO Z IPU MII RMII RGMII mode I O MANAGEMENT DATA INPUT OUTPUT MDIO FOR RGMII RGMDCLK B4 O Z MDIO serial clock RGMII mode RGMDCLK O RGMDIO A4 VO Z MDIO serial data RGMI
272. h auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 46 HPI16 Write Timing HAS Not Used Tied High 184 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 12 1 12 1 XX OX e 12 eF 12 1L 11 11 HR vFA 12 e 12 g 1 114 994 37 gt lt 14 18 18 7 1 4 _ M 34 ET gt 5 4 34 5 e A HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 47 16 Write Timing HAS Used Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 185 SM320C6455 EP 49
273. he PCI66 PCI EEAI and HPI WIDTH control other functions of the PCI and HPI peripherals Table 3 2 describes the effect of the PCI EN PCI66 PCI EEAI and HPI WIDTH configuration pins Submit Documentation Feedback Device Configuration 61 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 3 2 66 and HPI WIDTH Peripheral Selection HPI and PCI CONFIGURATION PIN 5 4 PERIPHERAL FUNCTION SELECTED ERN PM HPI DATA HPI DATA 32 BIT PCI PCI Y29 U27 P25 R25 LOWER UPPER 66 33 MHz AUTO INIT 0 0 0 0 Enabled Hi Z Disabled N A 0 0 0 1 Enabled Enabled Disabled N A Enabled 1 1 1 X Disabled Enabled via External 2 66 MHz EEPROM 1 1 0 X Disabled Disabled Disabled 1 0 x Disabled default values Enabled 33 MHz Enabled 1 0 1 X Disabled via External 2 EEPROM 1 PCI_EEAI is latched at reset as a configuration input If PCI EEAI is set as one then default values are loaded from an external 2 EEPROM The UTOPIA and EMAC MDIO pins are also multiplexed on the C6455 device The UTOPIA EN function AEA12 pin controls the function of these multiplexed pins The MAC SEL 1 0 configuration pins AEA 10 9 control which interface is used by the EMAC MDIO Note that since the PCI shares some pins with the UTO
274. he package type with pin count SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 1 Characteristics of the C6455 Processor HARDWARE FEATURES C6455 Peripherals Not all peripherals pins are available at the same time For more detail see the Device Configuration section EMIFA 64 bit bus width clock source AECLKIN or SYSCLK4 DDR2 Memory Controller 32 bit bus width 1 8 V I O clock source CLKIN2 1 64 independent channels CPU 3 clock rate 1 High speed 1 4 Serial Rapid IO Port 1 2 1 HPI 32 16 bit user selectable 1 16 or 2 PCI 32 bit 66 MHz or 33 MHz 1 PCI66 or PCI33 McBSPs internal CPU 6 or external clock source up to 100 Mbps 2 UTOPIA 8 bit mode 50 MHz Slave only 1 10 100 1000 Ethernet MAC EMAC 1 Management Data Input Output MDIO 1 64 Bit Timers Configurable internal clock source CPU 6 clock frequency 2 64 bit or 4 32 bit Organization General Purpose Input Output Port GPIO 16 VCP2 clock source CPU 3 clock frequency 1 Decoder Coprocessors TCP2 clock source CPU 3 clock frequency 1 Size Bytes 2192K 32K Byte 32KB L1 Program Memory Controller On Chip Memory SRAM Cache 32KB Data Memory Controller SRAM Cache 2096KB L2 Unified Memory Cache 32KB L2 ROM C64x Megamodule Megamodule Revision ID Register addr
275. hen it is configured for RMII operation The RMREFCLK frequency should be 50 MHz 50 PPM with a duty cycle between 35 and 65 inclusive Table 7 81 Timing Requirements for RMREFCLK RMII Operation see Figure 7 65 720 850 NO PARAMETER UNIT MIN MAX tw RMREFCLKH Pulse duration RMREFCLK high 7 13 ns tw RMREFCLKL Pulse duration RMREFCLK low 7 13 ns 3 I RMREFCLK Transition time RMREFCLK 2 ns Input unicum 3 gt l le Figure 7 65 RMREFCLK Timing Table 7 82 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10 100 Mbit s see Figure 7 66 720 850 A 1000 1000 NO PARAMETER 1200 UNIT 1000 Mbps MIN MAX 1 ta RMREFCLKH MTXD Delay time RMREFCLK high to transmit selected signals valid 3 10 ns 1 For RMII transmit selected signals include MTXD 1 0 and MTXEN m RMREFCLK Input Z MeL N MTX D 1 nA MTX D 0 7 MTXEN Outputs RY RRRS Figure 7 66 EMAC Transmit Interface Timing RMII Operation Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 211 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 www ti com Table 7 83 Timing Requirements for EMA
276. heral Signals Submit Documentation Feedback Device Overview 27 SM320C6455 EP 9 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Ethernet MAC EMAC Transmit MII UXDATA 7 2 MTXD 7 2 UXDATA 1 0 MTXD 1 0 RMTXD 1 0 RMII GMII RGTXD 3 0 A 3 0 Input Output MII Receive RMII UXADDR3 MDIO MII URDATA 7 2 MRXD 7 2 GMII URDATA 1 0 MRXD 1 0 RMRXD 1 0 RMII RGMII A RGMDIO GMII RGRXD 3 0 RGMIIA Error Detect andicontrol UXADDR4 MDCLK URSOC MRXER RMRXER MII URENB MRXDV URCLAV MCRS RMCRSDV RMII UXSOC MCOL UXENB MTXEN RMTXEN RGTXCTL RGRXCTL RGM UXCLK MTCLK RMREFCLK URCLK MRCLK UXCLAV GMTCLK RGTXC RGRXC RGREFCLK Ethernet EMAC and MDIO A ROGMII signals are mutually exclusive to all other EMAC signals B These EMAC pins are muxed with the UTOPIA peripheral By default these signals function as EMAC For more details on these muxed pins see the Device Configuration section of this document Figure 2 10 EMAC MDIO MII RMII GMII RGMII Peripheral Signals 28 Device Overview Submit Documentation Feedback Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 UTOPIA SLAVE A URDATA7 MRXD7 UXDA
277. high throughput interconnect mainly used to move data across the system for more information see Section 4 2 The data SCR connects masters to slaves via 128 bit data buses running at a SYSCLK2 frequency SYSCLK2 is generated from PLL1 controller Peripherals that have a 128 bit data bus interface running at this speed can connect directly to the data SCR other peripherals require a bridge The configuration switch fabric also known as the configuration switch central resource SCR is mainly used by the C64x Megamodule to access peripheral registers for more information see Section 4 3 The configuration SCR connects C64x Megamodule to slaves via 32 bit configuration buses running at a SYSCLK2 frequency SYSCLK2 is generated from PLL1 controller As with the data SCR some peripherals require the use of a bridge to interface to the configuration SCR Note that the data SCR also connects to the configuration SCR Bridges perform a variety of functions e Conversion between configuration bus and data bus e Width conversion between peripheral bus width and SCR bus width e Frequency conversion between peripheral bus frequency and SCR bus frequency For example the EMIFA and DDR2 memory controller require a bridge to convert their 64 bit data bus interface into a 128 bit interface so that they can connect to the data SCR In the case of the TCP2 and VCP2 a bridge is required to connect the data SCR to the 64 bit configuration bus interfa
278. ice reset using a AEA3 T27 IPD 1 kQ resistor if power is applied to the SRIO supply pins If the SRIO peripheral is not used and the SRIO supply pins are connected to Vgs the AEA3 pin must be pulled down to Vss using a 1 resistor T26 Configuration General Purpose Inputs CFGGP 2 0 AEA 2 0 U26 IPD The value of these pins is latched to the Device Status Register following device reset and is 025 used by the bootloader for some boot modes For information the boot modes see Section 2 4 Boot Sequence PCI pin function enable bit PCI_EN Selects which function is enabled on the and the PCI UTOPIA multiplexed pins 0 HPI and UTOPIA pin function enabled default PCI_EN Y29 IPD This means all multiplexed HPI PCI and PCI UTOPIA pins function as HPI and UTOPIA pins respectively 1 PCI pin function enabled This means all multiplexed HPI PCI and PCI UTOPIA pins function as PCI pins DDR2 Memory Controller enable DDR2_EN ABAO V26 IPD 0 DDR2 Memory Controller peripheral pins are disabled default 1 DDR2 Memory Controller peripheral pins are enabled EMIFA enable ABA1 V25 IPD 0 EMIFA peripheral pins are disabled default 1 EMIFA peripheral pins are enabled 3 2 Peripheral Configuration at Device Reset Some C6455 peripherals share the same pins internally multiplexed and are mutually exclusive Therefore not all peripherals may be used
279. igh When the POR pin is deasserted the configuration pin values are latched and the PLL controllers change their system clocks to their default divide down values PLL2 is taken out of reset and automatically starts its locking sequence Other device initialization is also started 4 After device initialization is complete the RESETSTAT pin is deasserted driven high By this time PLL2 has already completed its locking sequence and is outputting a valid clock The system clocks of both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks After the pause the system clocks are restarted at their default divide by settings 5 The device is now out of reset device execution begins as dictated by the selected boot mode see Section 2 4 Boot Sequence NOTE To most of the device reset is de asserted only when the POR and RESET pins are both de asserted driven high Therefore in the sequence described above if the RESET pin is held low past the low period of the POR pin most of the device will remain in reset The only exception being that PLL2 is taken out of reset as soon as POR is de asserted driven high regardless of the state of the RESET pin The RESET pin should not be tied together with the POR pin 7 6 2 Warm Reset RESET Pin A Warm Reset has the same effects as a Power on Reset except that in this case the test and emulation logi
280. ime events count events generate pulses interrupt the CPU and send synchronization events to the EDMAS channel controller 7 15 1 Timers Device Specific Information The C6455 device has two general purpose timers 0 and Timer1 each of which be configured as a general purpose timer or a watchdog timer When configured as a general purpose timer each timer can be programmed as a 64 bit timer or as two separate 32 bit timers Each timer is made up of two 32 bit counters a high counter and a low counter The timer pins TINPLx and TOUTLx are connected to the low counter The high counter does not have any external device pins 7 15 2 Timers Peripheral Register Description s Table 7 92 Timer 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0294 0000 Reserved 0294 0004 EMUMGT CLKSPDO Re e en Management Clock Speed 0294 0008 Reserved 0294 000C Reserved 0294 0010 CNTLOO Timer 0 Counter Register Low 0294 0014 CNTHIO Timer 0 Counter Register High 0294 0018 PRDLOO Timer 0 Period Register Low 0294 001C PRDHIO Timer 0 Period Register High 0294 0020 TCRO Timer 0 Control Register 0294 0024 TGCRO Timer 0 Global Control Register 0294 0028 WDTCRO Timer 0 Watchdog Timer Control Register 0294 002C Reserved 0294 0030 i Reserved 0294 0034 0297 FFFF Reserved Table 7 93 Timer 1 Registers HEX ADD
281. imum of 256 CLKIN2 cycles The PLL1 controller input clock CLKIN1 and the PCI input clock PCLK must also be valid during this time PCLK is only needed if the PCI module is being used If the DDR2 memory controller and the EMAC peripheral are not needed CLKIN2 can be tied low and in this case the POR pin must remain asserted low for a minimum of 256 CLKIN1 cycles after all power supplies have reached valid operating conditions Within the low period of the POR pin the following happens The reset signals flow to the entire chip including the test and emulation logic resetting modules that use reset asynchronously The PLL1 controller clocks are started at the frequency of the system reference clock The clocks are propagated throughout the chip to reset modules that use reset synchronously By default PLL1 is in reset and unlocked The PLL2 controller clocks are started at the frequency of the system reference clock PLL2 is held in reset Since the PLL2 controller always operates in PLL mode the system reference clock and 128 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 all the system clocks are invalid at this point The RESETSTAT pin stays asserted low indicating the device is reset 3 The POR pin may now be deasserted driven h
282. ing memory contents are maintained during a System Reset DDR2 Memory Controller The DDR2 Memory Controller registers are not reset In addition the DDR2 SDRAM memory content is retained if the user places the DDR2 SDRAM in self refresh mode before invoking the System Reset The contents of the memory connected to the EMIFA are retained The EMIFA registers are not reset Test emulation and clock logic are unaffected The device configuration pins are also not re latched and the state of the peripherals see Table 3 4 is not affected During a System Reset the following happens 1 The System Reset is initiated by the emulator During this time the following happens The reset signals flow to the entire chip resetting all the modules on chip except the test and emulation logic The PLL controllers are not reset Internal system clocks are unaffected If PLL1 PLL2 were locked before the System Reset they remain locked The RESETSTAT pin goes low to indicate an internal reset is being generated 2 After device initialization is complete the RESETSTAT pin is deasserted driven high In addition the PLL controllers pause their system clocks for about 10 cycles At this point The state of the peripherals before the System Reset is not changed For example if McBSPO was in the enabled state before System Reset it will remain in the enabled state after System Reset The I O pins are controll
283. interface ti com Medical www ti com medical Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Telephony www ti com telephony ZigBee Solutions www ti com Iprf Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2008 Texas Instruments Incorporated
284. interrupt Mask3 75 EDMA3CC_INT4 completion interrupt Mask4 76 EDMA3CC_INT5 completion interrupt Mask5 77 EDMA3CC_INT6 completion interrupt Mask6 78 EDMA3CC_INT7 EDMASCC completion interrupt Mask7 79 EDMA3CC_ERRINT EDMASCC error interrupt 80 Reserved This system event is not connected therefore not 81 EDMA3TCO_ERRINT error interrupt 82 EDMA3TC1_ERRINT EDMASTC1 error interrupt 83 EDMA3TC2_ERRINT 2 error interrupt 84 EDMA3TC3_ERRINT error interrupt 85 95 Reserved 2 These system events not connected therefore 96 INTERR Interrupt Controller dropped CPU interrupt event 97 IDMAERR EMC invalid IDMA parameters 98 99 Reserved ie id These system events are not connected and therefore 1000 EFIINTA EFI interrupt from side A 1010 EFIINTB EFI interrupt from side B Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 125 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 7 10 C6455 System Event Mapping continued EVENT NUMBER INTERRUPT EVENT DESCRIPTION 102 112 Blesarvad 2 These system events not connected therefore 1130 L1P ED1 L1P single bit error detected during DMA read 114 115
285. ion Address Register 0 02A3 8310 DFBIDXO Destination FIFO BIDX Register 0 02A3 8314 DFMPPRXYO Destination FIFO Memory Protection Proxy Register 0 02A3 8318 02A3 833C Reserved 02A3 8340 DFOPT1 Destination FIFO Options Register 1 02A3 8344 DFSRC1 Destination FIFO Source Address Register 1 02A3 8348 DFCNT1 Destination FIFO Count Register 1 02A3 834C DFDST1 Destination FIFO Destination Address Register 1 122 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 9 EDMA3 Transfer Controller 3 Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 8350 DFBIDX1 Destination FIFO BIDX Register 1 02A3 8354 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1 02A3 8358 02A3 837 Reserved 02A3 8380 DFOPT2 Destination FIFO Options Register 2 02A3 8384 DFSRC2 Destination FIFO Source Address Register 2 02A3 8388 DFCNT2 Destination FIFO Count Register 2 02A3 838G DFDST2 Destination FIFO Destination Address Register 2 02A3 8390 DFBIDX2 Destination FIFO BIDX Register 2 02A3 8394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 02A3 8398 02A3 83BG Reserved 02A3 83C0 DFOPT3 Destination FIFO Options Register 3 02A3 83C4 DFSRC3 Destination FIFO Source Address Regis
286. ion Feedback 4 TEXAS 5 320 6455 INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 C64x Peripheral Information and Electrical Specifications 71 Parameter Information Tester Pin Electronics Data Sheet Timing Reference Point 429 3 5 nH Output Under T 70 500 see Note Device Pin 4 0 1 85 pF see Note NOTE This data sheet provides timing at the device pin For output timing analysis the tester pin electronics and its transmission line effects must be taken into account A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect The transmission line is intended as a load only It is not necessary to add or subtract the transmission line delay 2 ns from the data sheet timings Input requirements in this data sheet are tested with an input slew rate of lt 4 Volts per nanosecond 4 V ns at the device pin Figure 7 1 Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals This load capacitance value does not indicate the maximum load the device is capable of driving 7 1 1 3 3 V Signal Transition Levels All input and output timing parameters are referenced to 1 5 V for both 0 and 1 logic levels Vret 1 5 V Figure 7 2 Input and Output Voltage Reference Levels for AC Timing Measu
287. ion Feedback Device Configuration 73 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 3 4 6 Emulator Buffer Powerdown Register EMUBUFPD Description The Emulator Buffer Powerdown Register EMUBUFPD is used to control the state of the pin buffers of emulator pins EMU 18 2 These buffers can be powered down if the device trace feature is not needed 31 8 Reserved R 0 7 1 0 Reserved EMUCTL R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 3 9 Emulator Buffer Powerdown Register EMUBUFPD 0x02AC 0054 Table 3 12 Emulator Buffer Powerdown Register EMUBUFPD Field Descriptions Bit Field Value Description 31 1 Reserved Reserved 0 EMUCTL Buffer powerdown for EMU 18 2 pins 0 Power up buffers 1 Power down buffers 74 Device Configuration Submit Documentation Feedback Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 3 5 Device Status Register Description The device status register depicts the device configuration selected upon device reset Once set these bits will remain set until a device reset For the actual register bit names and their associated bit field descriptions see Figure 3 10 and Table 3 13 Note that enabling or disabling peripherals through the Peripheral Configurati
288. ion software or driver controls the divide down amount 7 14 4 2 NDIO Peripheral Register Description s Table 7 89 MDIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 1800 VERSION MDIO Version Register 02C8 1804 CONTROL MDIO Control Register 02C8 1808 ALIVE MDIO PHY Alive Status Register 02C8 180C LINK MDIO PHY Link Status Register 02C8 1810 LINKINTRAW MDIO Link Status Change Interrupt Unmasked Register 02C8 1814 LINKINTMASKED MDIO Link Status Change Interrupt Masked Register 02C8 1818 02C8 181C Reserved 02C8 1820 USERINTRAW MDIO User Command Complete Interrupt Unmasked Register 02C8 1824 USERINTMASKED MDIO User Command Complete Interrupt Masked Register 02C8 1828 USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register 02C8 182C USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register 02C8 1830 02C8 187C Reserved 02C8 1880 USERACCESSO MDIO User Access Register 0 02C8 1884 USERPHYSELO MDIO User PHY Select Register 0 02C8 1888 USERACCESS1 MDIO User Access Register 1 02C8 188C USERPHYSEL1 MDIO User PHY Select Register 1 02C8 1890 02C8 1FFF Reserved 216 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 14 4 3 Electrical Data Timing Tabl
289. ip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 9 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by to Customer on an annual bas
290. is Addendum Page 1 MECHANICAL DATA GTZ 5 697 PLASTIC BALL GRID ARRAY 22 40 TYP OOOOOOOOOO DOOOOOOOOOO OOOOOOOOO0O0000000000000 A1 Corner 2 HEAT SLUG 11 13 15 17 19 21 252 10 12 14 16 18 2022 24 Bottom View 3 10 MAX dl x Lam 4206099 2 D 02 07 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Thermally enhanced plastic package with heat slug HSL D Flip chip application only E This is leaded solder ball design 3 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such informatio
291. ister 02A0 01B8 DCHMAP46 DMA Channel 46 Mapping Register 02A0 01BC DCHMAP47 DMA Channel 47 Mapping Register 02A0 01 0 DCHMAP48 DMA Channel 48 Mapping Register 02A0 0104 DCHMAP49 DMA Channel 49 Mapping Register 02A0 01C8 DCHMAP50 DMA Channel 50 Mapping Register 02A0 01CC DCHMAP51 DMA Channel 51 Mapping Register 02 0 0100 DCHMAP52 DMA Channel 52 Mapping Register 02A0 01D4 DCHMAP53 DMA Channel 53 Mapping Register 02A0 01D8 DCHMAP54 DMA Channel 54 Mapping Register 112 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 4 EDMA3 Channel Controller Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02 0 01DC DCHMAP55 DMA Channel 55 Mapping Register 02A0 01 0 DCHMAP56 DMA Channel 56 Mapping Register 02A0 01E4 DCHMAP57 DMA Channel 57 Mapping Register 02A0 01E8 DCHMAP58 DMA Channel 58 Mapping Register 02A0 01EC DCHMAP59 DMA Channel 59 Mapping Register 02A0 01 0 DCHMAP60 DMA Channel 60 Mapping Register 02A0 01F4 DCHMAP61 DMA Channel 61 Mapping Register 02A0 01F8 DCHMAP62 DMA Channel 62 Mapping Register 02A0 01FC DCHMAP63 DMA Channel 63 Mapping Register 02A0 0200 QCHMAPO QDMA Channel 0 Mappi
292. istics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Unless Otherwise Noted 103 7 C64x Peripheral Information and Electrical Specifications 105 7 1 Parameter nfOrfrialiOli i252 2eseaes sa ronne VO a T YR wa TUER PERR DEREN denies 105 7 1 1 3 3 V Signal Transition levels nat en area oa aa oa soar enge rara spar 105 74 2 9 9 V Signal Transition Rates noch uen nmn aka usui Re sra pe a dox De asawa 105 7 1 8 Timing Parameters and Board Routing Analysis 106 7 2 Recommended Clock and Control Signal Transition Behavior 107 7 3 Power SUpDIISS met 107 7 3 1 Power Supply Sequencilig s uuu I wasis Mamie NE 107 7 3 2 Power Supply Decoupling 107 7 3 3 Power Dowti OperalloLi usu EE MEUN RES MENS 107 7 3 4 Preserving Boundary Scan Functionality on RGMII and DDR2 Memory 108 7 4 Enhanced Direct Memory Access mne 109 7 4 1
293. ive Count Register 02A3 024 SADST Source Active Destination Address Register 02A3 0250 SABIDX Source Active Source B Index Register 02A3 0254 SAMPPRXY Source Active Memory Protection Proxy Register 02A3 0258 SACNTRLD Source Active Count Reload Register 02A3 025 SASRCBREF _ Source Active Source Address B Reference Register 02A3 0260 SADSTBREF _ Source Active Destination Address B Reference Register 02A3 0264 02A3 027C Reserved 02A3 0280 DFCNTRLD Destination FIFO Set Count Reload 02A3 0284 DFSRCBREF _ Destination FIFO Set Destination Address B Reference Register 02A3 0288 DFDSTBREF _ Destination FIFO Set Destination Address B Reference Register 02A3 028C 02A3 02FC Reserved 02A3 0300 DFOPTO Destination FIFO Options Register 0 02A3 0304 DFSRCO Destination FIFO Source Address Register 0 02A3 0308 DFCNTO Destination FIFO Count Register 0 02A3 030C DFDSTO Destination FIFO Destination Address Register 0 02A3 0310 DFBIDXO Destination FIFO BIDX Register 0 02A3 0314 DFMPPRXYO Destination FIFO Memory Protection Proxy Register 0 02A3 0318 02A3 033C Reserved 02A3 0340 DFOPT1 Destination FIFO Options Register 1 02A3 0344 DFSRC1 Destination FIFO Source Address Register 1 02A3 0348 DFCNT1 Destination FIFO Count Register 1 02A3 034C DFDST1 Destination FIFO Destination Address Register 1 02A3 0350 DFBIDX1 Destination FIFO BIDX Register 1 02A3 0354 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1 02A3 0358 02A3 037
294. ive Count Reload Register 02 2 025 SASRCBREF Source Active Source Address B Reference Register 02A2 0260 SADSTBREF Source Active Destination Address B Reference Register 02A2 0264 02A2 027G Reserved 02A2 0280 DFCNTRLD Destination FIFO Set Count Reload 118 C64x Peripheral Information and Electrical Specifications INSTRUMENTS Submit Documentation Feedback SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR ki TEXAS INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 6 EDMA3 Transfer Controller 0 Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 0284 DFSRCBREF _ Destination FIFO Set Destination Address B Reference Register 02A2 0288 DFDSTBREF Destination FIFO Set Destination Address B Reference Register 02A2 028C 02A2 02FC Reserved 02A2 0300 DFOPTO Destination FIFO Options Register 0 02A2 0304 DFSRCO Destination FIFO Source Address Register 0 02A2 0308 DFCNTO Destination FIFO Count Register 0 02A2 030C DFDSTO Destination FIFO Destination Address Register 0 02A2 0310 DFBIDXO Destination FIFO BIDX Register 0 02A2 0314 DFMPPRXYO Destination FIFO Memory Protection Proxy Register 0 02A2 0318 02A2 033C Reserved 02A2 0340 DFOPT1 Destination FIFO Options Register 1 02A2 0344 DFSRC1 Destination FIFO Source Address Register 1 02A2 0348 DFCNT1 Destination FIFO Count Regis
295. ive frame sync I O Z or GP 10 I O Z default DR1 GP 8 AH5 VO Z IPD McBSP1 receive data 1 or GP 8 1 0 2 default DX1 GP 9 AG5 VO Z IPD McBSP1 transmit data 0 2 or GP 9 0 2 default FSX1 GP 11 AG4 VO Z IPD McBSP1 transmit frame sync 1 0 2 or GP 11 I O Z default CLKX1 GP 3 AF5 VO Z IPD McBSP1 transmit clock 1 0 2 or GP 3 1 0 2 default MULTICHANNEL BUFFERED SERIAL PORT 0 McBSPO CLKRO AG1 VO Z IPU McBSPO receive clock I O Z FSRO AH3 VO Z IPD McBSPO receive frame sync 2 DRO AJ5 IPD McBSPO receive data I AF6 VO Z IPD McBSPO transmit data O Z FSX0 AJ3 VO Z IPD McBSPO transmit frame sync 0 2 CLKXO AG6 VO Z IPU McBSPO transmit clock 0 2 UNIVERSAL TEST AND OPERATIONS PHY INTERFACE for ASYNCHRONOUS TRANSFER MODE ATM UTOPIA SLAVE UTOPIA SLAVE ATM CONTROLLER TRANSMIT INTERFACE Source clock for UTOPIA transmit driven by Master ATM Controller UXCLK MTCLK When the UTOPIA peripheral is disabled UTOPIA_EN AEA12 pin 0 this RMREFCLK N4 VO Z pin is either EMAC MII transmit clock MTCLK or the EMAC RMII reference clock The EMAC function is controlled by the MACSEL 1 0 AEA 10 9 pins For more detailed information see Section 3 Device Configuration Transmit cell available status output signal from UTOPIA Slave 0 indicates a complete cell is NOT available for transmit UXCLAV GMTCLK K5 VO Z 1 indicates a complete cell is available for transmit When
296. ively during programmable synchronous interface accesses Figure 7 38 Programmable Synchronous Interface Write Timing for EMIFA With Write Latency 1 170 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 10 4 HOLD HOLDA Timing Table 7 48 Timing Requirements for the HOLD HOLDA Cycles for EMIFA Module see Figure 7 39 720 850 1200 MAX NO A 1000 1000 UNIT 3 th HOLDAL HOLDL Hold time HOLD low after HOLDA low E ns 1 EMIF input clock period in ns for EMIFA Table 7 49 Switching Characteristics Over Recommended Operating Conditions for the HOLD HOLDA Cycles for EMIFA Module see Figure 7 39 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 1 td HOLDL EMHZ Delay time HOLD low to EMIFA Bus high impedance 2 3 ns 2 la EMHZ HOLDAL Delay time EMIF Bus high impedance to HOLDA low 0 2E ns 4 ta HOLDH EMLZ Delay time HOLD high to EMIF Bus low impedance 2E 7E ns 5 la EMLZ HOLDAH Delay time EMIFA Bus low impedance to HOLDA high 0 2E ns 1 E the EMIF input clock period in ns for EMIFA 2 EMIFA Bus consists of ACE 5 2 ABE 7 0 AED 63 0 AEA 19 0 ABA 1 0 ARW ASADS ASRE AAOE A
297. l Time Bugs application report literature number SPRA753 Using Advanced Event Triggering to Debug Real Time Problems in High Speed Embedded Microprocessor Systems application report literature number SPRA387 7 22 2 Trace 248 The C6455 device supports Trace Trace is a debug technology that provides a detailed historical account of application code execution timing and data accesses Trace collects compresses and exports debug information for analysis Trace works in real time and does not impact the execution of the system For more information on board design guidelines for Trace Advanced Emulation see the 60 Pin Emulation Header Technical Reference literature number SPRUG55 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 22 3 IEEE 1149 1 JTAG 7 22 3 1 JTAG Device Specific Information 7 22 3 1 1 IEEE 1149 1 JTAG Compatibility Statement For maximum reliability the C6455 DSP includes an internal pulldown IPD on the TRST pin to ensure that IRST will always be asserted upon power up and the DSP s internal emulation logic will always be properly initialized when this pin is not routed out JTAG controllers from Texas Instruments actively drive TRST high However some third party JTAG controllers may not drive TRST high but expect the use of an exter
298. lank Initial Silicon 1 1 B Silicon 2 0 A The extended temperature A version devices may have different operating conditions than the commercial temperature devices For more details see the Recommended Operating Conditions section of this document B BGA Ball Grid Array Figure 2 13 C64x DSP Device Nomenclature including the SM320C6455 EP DSP 2 8 2 2 Documentation Support 56 The following documents describe the C6455 Copies of these documents are available on the Internet at www ti com Tip Enter the literature number in the search box provided at www ti com The current documentation that describes the C6455 related peripherals and other technical collateral is available in the C6000 DSP product folder at www ti com c6000 SPRU732 TMSS320C64x C64x DSP CPU and Instruction Set Reference Guide Describes the CPU architecture pipeline instruction set and interrupts for the C64x and C64x digital signal processors DSPs of the C6000 DSP family The C64x C64x DSP generation comprises fixed point devices in the C6000 DSP platform The C64x DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set SPRU871 7 5320 64 DSP Megamodule Reference Guide Describes the C64x digital signal processor DSP megamodule Included is a discussion on the internal direct memory access IDMA controller the interrupt controller the power down controller memory protection bandwidth man
299. le SRIO and EDMA masters contain registers that control their own priority values The priority is enforced when several masters in the system are vying for the same endpoint Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will be enforced when multiple masters try to access the configuration SCR Priority is also enforced on the configuration SCR side when a master through the data SCR tries to access the same endpoint as the C64x megamodule In the PRI ALLOC register the HOST field applies to the priority of the HPI and PCI peripherals The EMAC field specifies the priority of the EMAC peripheral The SRIO field is used to specify the priority of the Serial RapidlO when accessing descriptors from system memory The priority for Serial RapidlO data accesses is set in the peripheral itself Table 4 2 C6455 Default Bus Master Priorities DEFAULT BUS MASTER PRIORITY LEVEL PRIORITY CONTROL EDMA3TCO 0 QUEPRI PRIQO EDMAS register EDMASTC1 0 QUEPRI PRIQ1 EDMA3 register EDMA3TC2 0 QUEPRI PRIQ2 EDMAS register EDMA3TC3 0 QUEPRI PRIQ3 EDMA3 register SRIO Data Access 0 PER_SET_CNTL CBA_TRANS_ PRI SRIO register SRIO Descriptor Access 0 PRI_ALLOC SRIO EMAC 1 PRI_ALLOC EMAC PCI 2 PRI_ALLOC HOST HPI 2 PRI ALLOC HOST C64x Megamodule MDMA port 7 MDMAARBE PRI C64x Megamodule Register 31 16 Reser
300. led on the UTOPIA EMAC and UTOPIA MDIO multiplexed pins EMAC and MDIO pin functions are enabled default UTOPIA pin functions are enabled LENDIAN Device Endian mode LENDIAN Shows the status of whether the system is operating in Big Endian mode or Little Endian mode default System is operating in Big Endian mode System is operating in Little Endian mode default HPI WIDTH HPI bus width control bit Shows the status of whether the HPI bus operates in 32 bit mode or in 16 bit mode default HPI operates in 16 bit mode default HPI operates in 32 bit mode AECLKINSEL EMIFA input clock select Shows the status of what clock mode is enabled or disabled for EMIFA AECLKIN default mode SYSCLKA CPU x Clock Rate The SYSCLK4 clock rate is software selectable via the PLL1 Controller By default SYSCLKA is selected as CPU 8 clock rate 76 Device Configuration Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 3 13 Device Status Register DEVSTAT Field Descriptions continued Bit Field Value Description 3 0 BOOTMODE 3 0 Boot mode configuration bits Shows the status of what device boot mode configuration is operational BOOTMODE 3 0 Note if selected for boot the corresponding peripheral is automatically enabled after device reset 0000 No boot defa
301. level ins 2 0 5 mA Vou uols PCI capable pins DVppas 3 3 V 0 9DVpp33 V RGMII pins DVpp15 0 4 V DDR2 memory 14 V controller pins 3 3 V pins except E PCl capable and I2C P Vppas MIN 0 22DVpp33 V pins oL lo 1 5 PCI capable pins OUT d 0 1DVpp33 V Vo Low level output DVppss 3 3 V voltage Pulled up to 3 3 V 3 mA sink I2C pins currant 0 4 V RGMII pins 0 4 V DDR2 memory 0 4 V controller pins VI Vss to DVppas pins without internal pullup or 1 1 3 3 V pins except pulldown resistor PCl capable and I2C Vi Vss to DVpp33 pins with pins internal pullup resistor 30 100 Ue Hs UR SE V Vss to DVppss pins with DC 7 Vss DD33 i DC internal pulldown resistor aoe 109 50 2 pins 0 1DVpp33 lt VI 0 9DVpp33 10 10 PCI capable pins 1000 1000 pA RGMII pins 0 4 V AECLKOUT CLKR1 GP O0 CLKX1 GP 3 SYSCLKA GP 1 8 mA EMU 18 0 CLKR0 CLKX0 EMIF pins except AECLKOUT NMI TOUTOL TINPOL TOUT1L TINP1L PCI EN High level roe EMAC capable pins loH Del current except RGMII pins 4 mA RESETSTAT McBSP capable pins except CLKR1 GP 0 CLKX1 GP 3 CLKRO CLKXO GP 7 4 and TDO PCI capable pins 0 5 mA RGMII pins 8 mA DDR2 memory 4 mA controller pins 1 For test conditions shown as MIN MAX or NOM use the appropriate value specified in the recommended operating conditions table 2 These rated nu
302. lt or PCI parity error 0 2 HDS1 PSERR U2 I O Z Host data strobe 1 I default or PCI system error I O Z HDS2 PCBE1 U1 VO Z Host data strobe 2 I default or PCI command byte enable 1 0 2 HRDY PIRDY T4 VO Z Host ready from DSP to host 0 2 default or PCI initiator ready 0 2 URADDR3 PREQ P2 VO Z UTOPIA received address pin URADDR3 I or PCI bus request 0 2 or GP 15 GP 15 1 0 2 default 5 Submit Documentation Feedback These pins function as open drain outputs when configured as PCI pins Device Overview 31 SM320C6455 EP 3 TEXAS FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 www ti com Table 2 3 Terminal Functions continued SIGNAL TYPE iPD IPU 2 DESCRIPTION NAME NO URADDR2 PINTA P3 Volz UTOPIA received address 2 URADDR2 1 or PCI interrupt A 2 or GP 14 GP 14 2 default URADDR1 PRST R5 VO Z UTOPIA received address 1 URADDR1 1 or PCI reset 1 GP 13 GP 13 1 0 2 default URADDRO PGNT R4 Volz UTOPIA received address 0 URADDRO I or PCI bus grant I GP 12 GP 12 I O Z default URADDR4 PCBEO B iia UTOPIA received address pin 4 URADDR4A I or PCI command byte enable 0 2 ue 2 24 default UXADDR
303. mation and Electrical Specifications 139 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR 6 INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 7 3 PLL1 Controller Register Descriptions This section provides a description of the PLL1 controller registers For details on the operation of the PLL controller module see the TMS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide literature number SPRUE56 NOTE The PLL1 controller registers can only be accessed using the CPU or the emulator Not all of the registers documented in the TMS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide literature number SPRUE56 are supported on the C6455 Only those registers documented in this section are supported Furthermore only the bits within the registers described here are supported You should not write to any reserved memory location or change the value of reserved bits 7 7 3 4 PLL1 Control Register The PLL control register PLLCTL is shown in Figure 7 11 and described in Table 7 19 31 16 15 R 0 R 0 8 7 6 5 4 3 2 1 0 Reserved Rsvd Revd Reserved PLLRST Revd PLL PLLEN PWRDN 1 RO R W 0 R R W 0 R W 1 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 7 11 PLL1 Control Register PLLCTL Hex Address 029A 0100 Table 7 19 PLL1 Control Register PLLCTL Field Descriptions
304. mbers are from the PCI Local Bus Specification version 2 3 The DC specification and AC specifications are defined in Table 4 3 and Table 4 4 respectively of the PCI Local Bus Specification 3 l applies to input only pins and bi directional pins For input only pins indicates the input leakage current For bi directional pins includes input leakage current and off state hi Z output leakage current 4 PCI input leakage currents include Hi Z output leakage for all bidirectional buffers with 3 state outputs Submit Documentation Feedback Device Operating Conditions 103 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Unless Otherwise Noted continued PARAMETER TEST CONDITIONS MIN MAX UNIT AECLKOUT CLKR1 GP O0 CLKX1 GP 3 SYSCLKA GP 1 B MA EMU 18 0 CLKRO CLKXO EMIF pins except AECLKOUT NMI TOUTOL TINPOL TOUTP1L TINP1L PCI EN Low level output EMAC capable pins ot current DC except RGMII pins 4 mA RESETSTAT McBSP capable pins except CLKR1 GP 0 CLKX1 GP 3 CLKRO GP 7 4 and TDO PCI capable pins 15 mA RGMII pins 8 mA DDR2 memory 4 mA controller pins 5 Off state output Vin 4 loz current DC 3 3 V pins Vo
305. memory controller and exception o primary lI switch fabric 128 Cache control lt Master DMA Bandwidth management Memory protection L1D cache SRAM A When accessing the internal ROM of the DSP the CPU frequency must be less than 750 MHz Figure 5 1 64x Megamodule Block Diagram For more detailed information on the C64x Megamodule on the C6455 device see the TMS320C64x Megamodule Reference Guide literature number SPRU871 5 1 Memory Architecture The C6455 device contains a 2096KB level 2 memory L2 a 32KB level 1 program memory L1P and a 32KB level 1 data memory L1D The L1P memory configuration for the C6455 device is as follows Region 0 size is OK bytes disabled e Region 1 size is 32K bytes with no wait states The L1D memory configuration for the C6455 device is as follows e Region 0 size is OK bytes disabled Submit Documentation Feedback C64x Megamodule 87 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Region 1 size is 32K bytes with no wait states L1D is a two way set associative cache while L1P is a direct mapped cache 6 INSTRUMENTS www ti com The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register L1PMODE and the L1DMODE field of the L1D Configuration Register L1DCFG of the C64x Megamodule After device reset L1P and L1D cache are configured as all c
306. mentation Feedback ki TEXAS INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION DVppss AD5 AD7 AD14 AD18 AD22 AD24 AE6 AE8 AE15 AF 1 AF16 AF24 AG12 AG17 AG23 AH14 AH16 AH24 AJ7 AJ15 AJ25 AJ29 3 3 V I O supply voltage CVpp L12 L14 L16 L18 M11 M13 M15 M17 M19 N12 N14 N16 N18 P13 P15 P17 P19 R12 R14 R16 1 25 V core supply voltage 1000 and 1200 devices 1 2 V core supply voltage 850 and 720 devices Submit Documentation Feedback Device Overview 49 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION CVpp R18 11 13 15 17 T19 012 014 U18 V11 V13 V19 W12 W14 1 25 V core supply voltage 1000 and 1200 devices 1 2 V core supply voltage 850 and 720 devices GROUND PINS
307. n Feedback ki TEXAS INSTRUMENTS www ti com 1 Features e Controlled Baseline One Assembly Site Test Site One Fabrication Site Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product Change Notification e Qualification Pedigree High Performance Fixed Point DSP C6455 1 39 ns 1 17 ns 1 ns and 0 83 ns Instruction Cycle Time 1 GHz Clock Rate Eight 32 Bit Instructions Cycle 9600 MIPS MMACS 16 Bits Commercial Temperature 0 C to 90 C Extended Temperature 40 C to 105 C S Temp 55 C to 105 C e C64x DSP Core Dedicated SPLOOP Instruction Compact Instructions 16 Bit Instruction Set Enhancements Exception Handling e C64x Megamodule L1 L2 Memory Architecture 256K Bit 32K Byte L1P Program Cache Direct Mapped 256K Bit 32K Byte L1D Data Cache 2 Way Set Associative 16M Bit 2096K Byte L2 Unified Mapped RAM Cache Flexible Allocation e 256K Bit 32K Byte L2 ROM Time Stamp Counter 4 Enhanced VCP2 Supports Over 694 7 95 Kbps AMR Programmable Code Parameters Enhanced Turbo Decoder Coprocessor TCP2 Supports up to Eight 2 Mbps 3GPP 6 Iterations Programmable Turbo Code and Decoding Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range This includes but is not limited to Highly
308. n is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual propert
309. nabled disabled EMIFA peripheral pins are disabled default EMIFA peripheral pins are enabled 21 DDR2 EN DDR2 Memory Controller Enable DDR2 EN status bit Shows the status of whether the DDR2 Memory Controller peripheral pins are enabled disabled DDR2 Memory Controller peripheral pins are disabled default DDR2 Memory Controller peripheral pins are enabled 20 PCI EN PCI Enable PCI EN status bit Shows the status of which function is enabled on the HPI PCI and PCI UTOPIA multiplexed pins HPI and UTOPIA pin functions are enabled default PCI pin functions are enabled 19 17 CFGGP 2 0 Used as General Purpose inputs for configuration purposes These pins are latched at reset These values can be used by S W routines for boot operations 16 Reserved Reserved Read only writes have no effect Submit Documentation Feedback Device Configuration 75 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR 6 INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 3 13 Device Status Register DEVSTAT Field Descriptions continued Bit Field Value Description 15 SYSCLKOUT_EN SYSCLKOUT Enable SYSCLKOUT_EN status bit Shows the status of which function is enabled on the SYSCLK4 GP 1 muxed pin GP 1 pin function of the SYSCLK4 GP 1 pin enabled default SYSCLKA pin function of the SYSCLKA GP 1 pin enabled 14
310. nal memory in the C6455 DSP Note that increment mode is supported by all C6455 peripherals including VCP2 and TCP2 For more information on these two addressing modes see the 7MSS20C645x DSP Enhanced DMA EDMA3 Controller User s Guide literature number SPRU966 A DSP interrupt must be generated at the end of an HPI or PCI boot operation to begin execution of the loaded application Since the DSP interrupt generated by the HPI and PCI is mapped to the EDMA event DSP EVT DMA channel 0 it will get recorded in bit 0 of the EDMA Event Register ER This event must be cleared by software before triggering transfers on DMA channel 0 The EDMA3 on the C6455 DSP supports active memory protection but it does not support proxied memory protection 7 42 EDMAS Channel Synchronization Events The EDMAS supports up to 64 DMA channels that can be used to service system peripherals and to move data between system memories DMA channels can be triggered by synchronization events generated by system peripherals Table 7 3 lists the source of the synchronization event associated with each of the DMA channels On the C6455 the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed For more detailed information on the EDMA3 module and how events are enabled captured processed prioritized linked chained and cleared etc see the TMS320C645x DSP Enhanced DMA EDMA3 Controller User s Guide literature numbe
311. nal pullup resistor on TRST When using this type of JTAG controller assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations 7 22 4 JTAG Peripheral Register Description s 7 22 5 JTAG Electrical Data Timing Table 7 116 Timing Requirements for JTAG Test Port see Figure 7 79 720 850 NO A 1000 1000 UNIT 1200 MIN MAX 1 Cycle time 35 ns 3 tsu TDIV TCKH Setup time TDI TMS TRST valid before TCK high 10 ns 4 th TCKH TDIV Hold time TDI TMS TRST valid after TCK high 9 ns Table 7 117 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port see Figure 7 79 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 2 la TCKL TDOV Delay time TCK low to TDO valid 3 18 ns 4 1 gt 2 2 roo gt gt 4 Figure 7 79 JTAG Test Port Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 249 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 250 Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version This data sheet revision history highlights the technical changes made to the SPRS276G device specific d
312. nals include RXD 3 0 and RXCTL W L 4 5 4 4 RXC at DSP B c 5 1st Half byte 2nd Half byte A Data and control information is received using both edges of the clocks RXD 3 0 carries data bits 3 0 on the rising edge of RXC and data bits 7 4 on the falling edge of RXC Similarly RXCTL carries RXDV on rising edge of RXC and RXERR on falling edge B RXC must be externally delayed relative to the data and control pins Figure 7 69 EMAC Receive Interface Timing RGMII Operation Table 7 87 Switching Characteristics Over Recommended Operating Conditions for TXC RGMII Operation for 10 100 1000 Mbit s see Figure 7 70 720 850 NO A 1000 1000 UNIT 1200 MIN MAX 10 Mbps 360 440 1 tc TXC Cycle time TXC 100 Mbps 36 44 ns 1000 Mbps 7 2 8 8 10 Mbps O 40 t xc 0 60 2 tw TXCH Pulse duration TXC high 100 Mbps 0 40 lt 0 60 ns 1000 Mbps 0 45 terxo _0 55 tecrxe 10 Mbps 0 40 lt _0 60 totxc 3 tw TXcL Pulse duration TXC low 100 Mbps 0 40 tetxc 0 60 tc rxc ns 1000 Mbps 0 45 tarxc 0 55 le rxc 10 Mbps 0 75 4 Transition time TXC 100 Mbps 0 75 ns 1000 Mbps 0 75 214 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www
313. ndalone mode e Larger block sizes in shared processing mode e Both max log MAP and log MAP decoding Sliding windows algorithm with variable reliability and prolog lengths e The prolog reduction algorithm e Execution of a minimum and maximum number of iterations e The SNR stopping criteria algorithm e The CRC stopping criteria algorithm For more detailed information on the TCP2 see the TMS320C645x DSP Turbo Decoder Coprocessor 2 TCP2 Reference Guide literature number SPRU973 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 221 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 17 2 2 Peripheral Register Description s 6 INSTRUMENTS www ti com Table 7 97 TCP2 Registers B XCADDRESS RANGE HEX ADDRESS RANGE ACRONYM REGISTER NAME 5000 0000 TCPICO TCP2 Input Configuration Register 0 5000 0004 TCPIC1 TCP2 Input Configuration Register 1 5000 0008 2 TCP2 Input Configuration Register 2 5000 000C TCPIC3 TCP2 Input Configuration Register 3 5000 0010 TCPIC4 TCP2 Input Configuration Register 4 5000 0014 5 2 Input Configuration Register 5 5000 0018 TCPIC6 TCP2 Input Configuration Register 6 5000 001 TCPIC7 TCP2 Input Configuration Register 7 5000 0020 T
314. ng Register 02A0 0204 1 QDMA Channel 1 Mapping Register 02A0 0208 QCHMAP2 QDMA Channel 2 Mapping Register 02A0 020G QCHMAP3 QDMA Channel 3 Mapping Register 02A0 0210 02A0 021C Reserved 02A0 0220 02A0 023C Reserved 02A0 0240 DMAQNUMO DMA Queue Number Register 0 02A0 0244 DMAQNUM1 DMA Queue Number Register 1 02A0 0248 DMAQNUM2 DMA Queue Number Register 2 02A0 024C DMAQNUM3 DMA Queue Number Register 3 02A0 0250 DMAQNUM4 DMA Queue Number Register 4 02A0 0254 DMAQNUMS5 DMA Queue Number Register 5 02A0 0258 DMAQNUM6 DMA Queue Number Register 6 02A0 025C DMAQNUM7 DMA Queue Number Register 7 02A0 0260 QDMAQNUM QDMA Queue Number Register 02A0 0264 02A0 0280 Reserved 02A0 0284 QUEPRI Queue Priority Register 02A0 0288 02A0 02FC Reserved 02A0 0300 EMR Event Missed Register 02A0 0304 EMRH Event Missed Register High 02A0 0308 EMCR Event Missed Clear Register 02A0 030C EMCRH Event Missed Clear Register High 02A0 0310 QEMR QDMA Event Missed Register 02A0 0314 QEMCR QDMA Event Missed Clear Register 02A0 0318 CCERR EDMASCC Error Register 02A0 031C CCERRCLR EDMASCC Error Clear Register 02A0 0320 EEVAL Error Evaluate Register 02A0 0324 02A0 033C Reserved 02A0 0340 DRAEO DMA Region Access Enable Register for Region 0 02A0 0344 DRAEHO DMA Region Access Enable Register High for Region 0 02A0 0348 DRAE1 DMA Region Access Enable Register for Region 1 02A0 034C DRAEH1 DMA Region Access Enable Register High for Region 1 02A0 0350 DRAE2 DMA
315. ng system slaves Internal Buses Bridges and Switch Fabrics Two types of buses exist in the C6455 device data buses and configuration buses Some C6455 peripherals have both a data bus and a configuration bus interface while others only have one type of interface Furthermore the bus interface width and speed varies from peripheral to peripheral Configuration buses are mainly used to access the register space of a peripheral and the data buses are used mainly for data transfers However in some cases the configuration bus is also used to transfer data For example data is transferred to the VCP2 and TCP2 configuration bus Similarly the data bus can also be used to access the register space of a peripheral For example the EMIFA and DDR2 memory controller registers are accessed through their data bus interface C64x Megamodule the EDMAS traffic controllers and the various system peripherals can be classified into two categories masters and slaves Masters are capable of initiating read and write transfers in the system and do not rely on the EDMAS3 for their data transfers Slaves on the other hand rely the EDMAS to perform transfers to and from them Masters include the EDMAS traffic controllers SRIO and PCI Slaves include the McBSP UTOPIA and 12 The C6455 device contains two switch fabrics through which masters and slaves communicate The data switch fabric known as the data switched central resource SCR is a
316. nma RR wii 133 7 7 PLEAD and PEET Gontroller u usa e nca DER RERO 136 7 7 1 PLL1 Controller Device Specific Information 137 7 7 1 1 Internal Clocks and Maximum Operating Frequencies 137 7 7 1 2 PLL1 Controller Operating Modes 1 138 7 7 1 3 PLL1 Stabilization Lock and Reset Times 138 7 7 2 PLL1 Controller Memory Map sseeen III HH III I II I I hne rrr 139 7 7 8 PLL1 Controller Register Descriptions U 140 2 7 34 PEL TGontrol Register a a mne linteis an 140 7 7 3 2 PLL Multiplier Control 141 7 7 3 3 PLL Pre Divider Control Register 142 7 7 3 4 PLL Controller Divider 4 Register 143 7 7 3 5 PLL Controller Divider 5 HH 144 7 7 8 6 PLL Controller Command Register 2 22 1 2 2 145 7 7 3 7 PLL Controller Status Register 146 7
317. ns 25 MHz 55 qe js 1 4 I k 3 4 gt le Figure 7 30 CLKIN2 Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 159 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 9 7 9 1 160 www ti com DDR2 Memory Controller The 32 bit 533 2 data rate DDR2 Memory Controller bus of the C6455 is used to interface to JESD79D 2A standard compliant DDR2 SDRAM devices The DDR2 external bus only interfaces to DDR2 SDRAM devices up to 512 MB it does not share the bus with any other types of peripherals The decoupling of DDR2 memories from other devices both simplifies board design and provides I O concurrency from a second external memory interface EMIFA The internal data bus clock frequency and DDR2 bus clock frequency directly affect the maximum throughput of the DDR2 bus The clock frequency of the DDR2 bus is equal to the CLKIN2 frequency multiplied by 10 The internal data bus clock frequency of the DDR2 Memory Controller is fixed at a divide by three ratio of the CPU frequency The maximum DDR2 throughput is determined by the smaller of the two bus frequencies For example if the internal data bus frequency is 333 MHz CPU frequency is 1 GHz and the DDR2 bus frequency is 267 MHz CLKIN2 frequency is 26 7 MHz the maximum data rate achievable by the DDR2 memory controller is 2 1
318. ns tw TOUTL Pulse duration TOUTLx low 12P 3 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use 1 ns k 2 i TINPLx 4 F i ms TOUTLx N Figure 7 73 Timer Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 219 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 16 Enhanced Viterbi Decoder Coprocessor VCP2 7 16 1 VCP2 Device Specific Information 6 INSTRUMENTS www ti com The C6455 device has a high performance embedded coprocessor Viterbi Decoder Coprocessor VCP2 that significantly soeeds up channel decoding operations on chip The VCP2 operating at CPU clock divided by 4 can decode over 694 7 95 Kbps adaptive multi rate AMR K 9 R 1 3 voice channels The VCP2 supports constraint lengths K 5 6 7 8 and 9 rates R 3 4 1 2 1 3 1 4 and 1 5 and flexible polynomials while generating hard decisions or soft decisions Communications between the VCP2 and the CPU are carried out through the EDMA3 controller The VCP2 supports Unlimited frame sizes Code rates 3 4 1 2 1 3 1 4 and 1 5 Constraint lengths 5 6 7 8 and 9 Programmable encoder polynomials Programmable reliability and convergence lengths Hard and soft decoded decisions e Tail and convergent modes Yamamoto logic e Tail biting logic e Various input and output
319. nt Queue 1 Entry Register 13 02A0 0478 Q1E14 Event Queue 1 Entry Register 14 02A0 047C Q1E15 Event Queue 1 Entry Register 15 02A0 0480 Q2E0 Event Queue 2 Entry Register 0 02A0 0484 Q2E1 Event Queue 2 Entry Register 1 02A0 0488 Q2E2 Event Queue 2 Entry Register 2 02A0 048 Q2E3 Event Queue 2 Entry Register 3 114 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 4 EDMA3 Channel Controller Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0490 Q2E4 Event Queue 2 Entry Register 4 02A0 0494 Q2E5 Event Queue 2 Entry Register 5 02A0 0498 Q2E6 Event Queue 2 Entry Register 6 02A0 049G Q2E7 Event Queue 2 Entry Register 7 02A0 04A0 Q2E8 Event Queue 2 Entry Register 8 02A0 04A4 Q2E9 Event Queue 2 Entry Register 9 02A0 04A8 Q2E10 Event Queue 2 Entry Register 10 02A0 04AG Q2E11 Event Queue 2 Entry Register 11 02A0 04B0 Q2E12 Event Queue 2 Entry Register 12 02A0 04B4 Q2E13 Event Queue 2 Entry Register 13 02A0 04B8 Q2E14 Event Queue 2 Entry Register 14 02A0 04 Q2E15 Event Queue 2 Entry Register 15 02A0 04C0 Q3E0 Event Queue 3 Entry Register 0 02A0 04C4 Q3E1 Event Queue 3 Entry Register 1
320. nterrupt event generation modes an 10 100 1000 Ethernet media access controller EMAC which provides an efficient interface between the C6455 DSP core processor and the network a management data input output MDIO module also part of the EMAC that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system a glueless external memory interface 64 bit EMIFA which is capable of interfacing to synchronous and asynchronous peripherals and a 32 bit DDR2 SDRAM interface The 2 ports on the C6455 allow the DSP to easily control peripheral devices and communicate with a host processor In addition the standard multichannel buffered serial port McBSP may be used to communicate with serial peripheral interface SPI mode peripheral devices The C6455 device has two high performance embedded coprocessors enhanced Viterbi Decoder Coprocessor VCP2 and enhanced Turbo Decoder Coprocessor TCP2 that significantly speed up channel decoding operations on chip The VCP2 operating at CPU clock divided by 3 can decode over 694 7 95 Kbps adaptive multi rate AMR K 9 R 1 3 voice channels The VCP2 supports constraint lengths K 5 6 7 8 and 9 rates R 3 4 1 2 1 3 1 4 and 1 5 and flexible polynomials while generating hard decisions or soft decisions The TCP2 operating at CPU clock divided by 3 can decode up to fifty 384 Kbps or eight 2 Mbps turbo encoded channels assuming 6 iterations The TCP2 impleme
321. ntrol Modules For more detailed information on the EMAC MDIO see the TMS320C645x DSP EMAC MDIO Module Reference Guide literature number SPRU975 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 14 1 EMAC Device Specific Information Interface Modes The EMAC module on the C6455 supports four interface modes Media Independent Interface MIl Reduced Media Independent Interface RMII Gigabit Media Independent Interface GMII and Reduced Gigabit Media Independent Interface RGMII The MII and GMII interface modes are defined in the IEEE 802 3 2002 standard The RGMII mode of the EMAC conforms to the Reduced Gigabit Media Independent Interface RGMII Specification version 2 0 The RGMII mode implements the same functionality as the GMII mode but with a reduced number of pins Data and control information is transmitted and received using both edges of the transmit and receive clocks TXC and RXC Note The internally delays the transmit clock TXC with respect to the transmit data and control pins Therefore the EMAC conforms to the RGMII ID operation of the RGMII specification However the EMAC does not delay the receive clock this signal must be delayed with respect to the receive data and control pins outside of the DSP The RMII mo
322. ntroller Status Register 156 7 8 3 4 PLL Controller Clock Align Control Register 156 7 8 3 5 PLLDIV Ratio Change Status Register 357 7 8 8 6 SYSGLK Status Registeel esinaine anaa aa 158 7 84 12 Controller Input Clock Electrical Data Timing 159 DDR2 Memory Controller serierne o aE 160 7 9 1 DDR2 Memory Controller Device Specific Information 160 7 9 2 DDR2 Memory Controller Peripheral Register Description s 161 7 9 8 DDR2 Memory Controller Electrical Data Timing 161 External Memory Interface A 162 7 10 1 EMIFA Device Specific 6 162 7 10 2 EMIFA Peripheral Register Description s 163 7 10 3 EMIFA Electrical Data Timing 164 7 10 3 1 Asynchronous Memory Timing
323. nts the max log map algorithm and is designed to support all polynomials and rates required by Third Generation Partnership Projects and SGPP2 with fully programmable frame length and turbo interleaver Decoding parameters such as the number of iterations and stopping criteria are also programmable Communications between the VCP2 TCP2 and the CPU are carried out through the EDMAS controller The C6455 has a complete set of development tools which includes a new C compiler an assembly optimizer to simplify programming and scheduling and a Windows debugger interface for visibility into source code execution Submit Documentation Feedback Features 9 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 1 3 Functional Block Diagram Figure 1 2 shows the functional block diagram of the C6455 device DDR2 SDRAM DDR2 Mem Ctlr BSRAM SBS PLL2 and ZBT SRAM PLL2 Controller D L1P Cache Direct Mapped 32K Bytes ROM FLASH mt 16 32 bit L2 Instruction Dispatch SPLOOP Buffer Cache Memory 2096K Bytes A McBSPO C64x DSP Core Instruction Fetch Control Registers McBSP1 A Serial Rapid Vo HPI 32 16 8 66 10 100 1000 MII RMII GMII RMGII D MDIO Instruction Decode Data Path A Data Path B In Circuit Emulation Memory Protect Power Control Band
324. o other SYSCLKSs selected in ALNCTL when the GOSET bit in PLLCMD is set The SYSCLKn ratio is set to the ratio programmed in the RATIO bit in PLLDIVn 2 0 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 147 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 7 3 9 PLLDIV Ratio Change Status Register Whenever a different ratio is written to the PLLDIVn registers the PLLCTRL flags the change in the PLLDIV ratio change status registers DCHANGE During the GO operation the PLL controller will only change the divide ratio of the SYSCLKs with the bit set in DCHANGE Note that changed clocks will be automatically aligned to other clocks The PLLDIV divider ratio change status register is shown in Figure 7 19 and described in Table 7 27 31 16 Reserved R 0 15 5 4 3 2 0 Reserved SYS5 SYS4 Reserved R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Figure 7 19 PLLDIV Divider Ratio Change Status Register DCHANGE Hex Address 029A 0144 Table 7 27 PLLDIV Divider Ratio Change Status Register DCHANGE Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved The reserved bit location is always read as
325. oduction Data PD PD TMS320C6455ZTZ7 Device Part Numbers For more details on the C64x DSP part TMS320C6455ZTZ8 numbering see Figure 2 13 TMS320C6455ZTZ 2 2 2 12 PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters CPU DSP Core Description The C64x Central Processing Unit CPU consists of eight functional units two register files and two data paths as shown in Figure 2 1 The two general purpose register files A and B each contain thirty two 32 bit registers for a total of 64 registers The general purpose registers can be used for data or can be data address pointers The data types supported include packed 8 bit data packed 16 bit data 32 bit data 40 bit data and 64 bit data Values larger than 32 bits such as 40 bit long or 64 bit long values are stored in register pairs with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register which is always an odd numbered register The eight functional units M1 L1 D1 S1 M2 L2 D2 and S2 are each capable of executing one instruction every clock cycle The M functional units perform all multiply operations The S and L units perform a general set of arithmetic logical and branch functions The D units primarily load data
326. om Boundary Scan Compatible 697 Pin Ball Grid Array BGA Package ZTZ or GTZ Suffix 0 8 mm Ball Pitch 0 09 um 7 Level Cu Metal Process CMOS 3 3 1 8 1 5 1 25 1 2 V I Os 1 25 1 2 V Internal 1 1 ZTZ GTZ BGA Package Bottom View Figure 1 1 shows the SM320C6455 EP device 697 pin ball grid array package bottom view ZTZ GTZ 697 PIN BALL GRID ARRAY BGA PACKAGE BOTTOM VIEW AJ AH AG AF AE AD AC arn Y w OOOOOOOOO V OOOOOOOOO U OOOOOOOOO T OOOOOOOOO R OOOOOOOOO P OOOOOOOOO L K J H G OOOOOOOOOOOO F E OOOOOOOOOOOO D OOOOOOOOOOOOOOOOOOOOOOOOOOOOO B OOOOOOOOOOOOOOOOOOOOOOOOOOOOO A OOOOOOOOOOOOOOOOOOOOOOOOOOOOO 1 35 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 NOTE The ZTZ mechanical package designator represents the version of the GTZ package with lead free balls For more detailed information 1 2 see the Mechanical Data section of this document Figure 1 1 ZTZ GTZ BGA Package Bottom View Description The C64x DSPs including the SM320C6455 EP device are the highest performance fixed point DSP generation in the C6000 DSP platform The C6455 device is based on the third generation high performance advanced VelociTI M very long instruction word VLIW architecture developed by Texas Instruments making these DSPs an excellent choice for applications including video and telecom infrastructur
327. on AECLKIN low 2 7 ns 4 tekn Transition time AECLKIN 2 ns 5 Period Jitter AECLKIN 0 02E 1 reference points for the rise and fall transitions are measured at Vi MAX and Vi MIN E the EMIF input clock AECLKIN or SYSCLK4 period in ns for EMIFA Minimum AECLKIN cycle times must be met even when AECLKIN is generated by an internal clock source Minimum AECLKIN times are based on internal logic speed the maximum useable speed of the EMIF may be lower due to AC timing requirements 4 This timing only applies when AECLKIN is used for EMIFA 5 je 1 aon s a x E 4ol le Figure 7 31 AECLKIN Timing for EMIFA 164 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 43 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the EMIFA Module 72 9 see Figure 7 32 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 1 to EKO Cycle time AECLKOUT E 0 7 0 7 ns 2 tw EKOH Pulse duration AECLKOUT high EH 0 7 EH 0 7 ns 3 tw EKOL Pulse duration AECLKOUT low EL 0 7 EL 0 7 ns 4 Transition time AECLKOUT 1 ns 5 la EKIH EKOH Delay time AECLKIN high to AECLKOUT high 1 8 ns 6 la EKIL EKOL Delay time AECLKIN low to AEC
328. on must be met between consecutive HPI accesses in 2 mode Submit Documentation Feedback Figure 7 51 HPI32 Write Timing HAS Used C64x Peripheral Information and Electrical Specifications 189 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 13 Multichannel Buffered Serial Port McBSP The McBSP provides these functions e Full duplex communication e Double buffered data registers which allow a continuous data stream Independent framing and clocking for receive and transmit e Direct interface to industry standard codecs analog interface chips AICs and other serially connected analog to digital A D and digital to analog D A devices e External shift clock or an internal programmable frequency shift clock for data transfer For more detailed information on the McBSP peripheral see the TMS320C6000 DSP Multichannel Buffered Serial Port McBSP Reference Guide literature number SPRU580 rev E or later 190 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 7 13 1 McBSP Device Specific Information SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 The CLKS signal is shared by both McBSPO and McBSP1 on this device Also the CLKGDV field of the Sample Rate Generator Register SRGR must
329. on Registers PERCFGO and PERCFG 1 does not affect the DEVSTAT register To determine the status of peripherals following writes to the PERCFGO and PERCFG registers read the Peripherals Status Registers PERSTATO and PERSTAT1 31 24 Reserved R 0000 0000 23 22 21 20 19 18 17 16 Reserved DDR2 EN PCI EN CFGGP2 CFGGP1 CFGGPO Reserved R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 15 14 13 12 11 10 9 8 SYSCLKOUT MCBSP1_EN PCI66 Reserved PCI EEAI MAC SEL MAC SELO Reserved R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 7 6 5 4 3 2 1 0 UTOPIA EN LENDIAN HPI WIDTH AECLKINSEL BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODEO R 0 R 1 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only x value after reset Note The default values of the fields in the DEVSTAT register are latched from device configuration pins as described in Section 3 1 Device Configuration at Device Reset The default values shown here correspond to the setting dictated by the internal pullup or pulldown resistor Figure 3 10 Device Status Register DEVSTAT 0x02A8 0000 Table 3 13 Device Status Register DEVSTAT Field Descriptions Bit Field Value Description 31 23 Reserved Reserved Read only writes have no effect 22 EMIFA_EN EMIFA Enable EMIFA_EN status bit Shows the status of whether the EMIFA peripheral pins are e
330. on as their respective power supply has reached normal operating conditions Pins remain high until configured otherwise by their respective peripheral The ABUSREQ pin remains high until the EMIFA is enabled through the PERCFG1 register Once the EMIFA is enabled the ABUSREQ pin is driven to its inactive state driven low All peripherals must be enable through software following a Power on Reset for more details see Section 7 6 1 Power on Reset For power supply sequence requirements see Section 7 3 1 Power Supply Sequencing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 133 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Power Supplies Ramping Power Supplies Stable PCLK UU U UU UU UU UU UU UU U8 k 5 RESETSTAT 2 im 0 SYSREFCLK PLL1C I Tm Win LU SYSCLK4 t ninn I AECLKOUT Internal 7 Boot and Device Configuration Pins _ 8 Z Group p M _ Low Group Undefined Low High Group Undefined n CLKIN2 Internal Reset PLL2C Undefined ee SYSREFCLK PLL2C Undefined i X t PLL2 Unlocked X PLL2 Locked A SYSCLK1 PLL2C Undefined X i PLL2 Unlocked X
331. onfiguration Registers Hey ann NE ACRONYM DSP ACCESS REGISTER NAME 02C0 0000 02C0 000F Reserved 02C0 0010 PCISTATSET PCI Status Set Register 02C0 0014 PCISTATCLR Status Clear Register 02C0 0018 02C0 001F Reserved 02C0 0020 PCIHINTSET PCI Host Interrupt Enable Set Register 02C0 0024 PCIHINTCLR PCI Host Interrupt Enable Clear Register 02 0 0028 02 0 002F Reserved 02C0 0030 PCIBINTSET PCI Back End Application Interrupt Enable Set Register 02C0 0034 PCIBINTCLR PCI Back End Application Interrupt Enable Clear Register 02C0 0038 PCIBCLKMGT PCI Back End Application Clock Management Register 02 0 003C 02 0 00FF Reserved 02C0 0100 PCIVENDEVMIR PCI Vendor ID Device ID Mirror Register 02 0 0104 PCICSRMIR PCI Command Status Mirror Register 02 0 0108 PCICLREVMIR PCI Class Code Revision ID Mirror Register 02 0 010C PCICLINEMIR PCI BIST Header Type Latency Timer Cacheline Size Mirror Register 02 0 0110 PCIBAROMSK PCI Base Address Mask Register 0 02C0 0114 PCIBAR1MSK PCI Base Address Mask Register 1 02C0 0118 PCIBAR2MSK PCI Base Address Mask Register 2 02C0 011C PCIBAR3MSK PCI Base Address Mask Register 3 02C0 0120 PCIBARAMSK PCI Base Address Mask Register 4 02C0 0124 PCIBAR5MSK PCI Base Address Mask Register 5 02 0 0128 02C0 012 Reserved 02C0 012C PCISUBIDMIR PCI Subsystem Vendor ID Subsystem ID Mirror Register 02C0 0130 Reserved 02C0 0134 PCICPBPTRMIR PCI Capabilities Pointer Mirror Register 02 0 0138
332. ontroller e SYSCLK3 clocks the PCI HPI UTOPIA McBSP GPIO TIMER and 2 peripherals as well as the configuration bus of the PLL2 Controller Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 137 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 www ti com e SYSCLK4 is used as the internal clock for the EMIFA It is also used to clock other logic within the DSP e SYSCLKS5 clocks the emulation and trace logic of the DSP The divider ratio bits of dividers D2 and D3 are fixed at 3 and 6 respectively The divider ratio bits of dividers D4 and 54 are programmable through the PLL controller divider registers PLLDIV4 and PLLDIV5 respectively The PLL multiplier controller PLLM and the dividers D4 and D5 must be programmed after reset There is no hardware CLKMODE selection on the C6455 device Since the divider ratio bits for dividers D2 and 03 are fixed the frequency of SYSCLK2 and SYSCLK3 is tied to the frequency of SYSREFCLK However the frequency of SYSCLK4 and SYSCLK5 depends the configuration of dividers D4 and D5 For example with PLLM in the PLL1 multiply control register set 10011b x20 mode and a 50 MHz CLKIN1 input the PLL output PLLOUT is set to 1200 MHz SYSCLK2 and SYSCLK3 run at 333 MHz and 166 MHz respectively Divider D4 can be programmed through the PLLDIV4 register to divide
333. or register 028C 0018 MCRO McBSPO0 Multichannel Control Register McBSPO0 Enhanced Receive Channel Enable 0280 0016 RCERE00 Register 0 Partition A B McBSP0 Enhanced Transmit Channel Enable 028 D020 XCERE00 Register 0 Partition A B 028C 0024 PCR0 McBSPO Pin Control Register McBSPO0 Enhanced Receive Channel Enable 028 0028 RCERE10 Register 1 Partition C D McBSP0 Enhanced Transmit Channel Enable 072G 002 XCERE10 Register 1 Partition C D McBSP0 Enhanced Receive Channel Enable 0286 0030 RCERE20 Register 2 Partition E F McBSP0 Enhanced Transmit Channel Enable 0280 0034 XCERE20 Register 2 Partition E F McBSP0 Enhanced Receive Channel Enable 0280039 Register 3 Partition G H 028C 003C XCERE30 McBSP0 Enhanced Transmit Channel Enable Register 3 Partition G H 028C 0040 028F FFFF Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 191 SM320C6455 EP 3 TEXAS FIXED POINT DIGITAL SIGNAL PROCESSOR INSTR MENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 58 McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS The CPU and EDMA controller can only read 0290 0000 DRR1 McBSP1 Data Receive Register via Configuration Bus this register they cannot write to it 3400 0000 DRR1 McBSP1 Data Receive Register via EDMA bus 0290 0004 DXR1 McBSP1 Data Transmit Register vi
334. ormation on the bandwidth management features of the C64x Megamodule can be found in the TMS320C64x Megamodule Reference Guide literature number SPRU871 C64x4 Megamodule Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 5 4 Power Down Control The C64x Megamodule supports the ability to power down various parts of the C64x Megamodule The power down controller PDC of the C64x Megamodule can be used to power down L1P the cache control hardware the CPU and the entire C64x Megamodule These power down features can be used to design systems for lower overall system power requirements NOTE The C6455 does not support power down modes for the L2 memory at this time More information on the power down features of the C64x Megamodule can be found in the TMS320C64x Megamodule Reference Guide literature number SPRU871 5 5 Megamodule Resets Table 5 2 shows the reset types supported on the C6455 device and they affect the resetting of the Megamodule either both globally or just locally Table 5 2 Megamodule Reset Global or Local GLOBAL LOCAL RESET TYPE MEGAMODULE MEGAMODULE RESET RESET Power On Reset Y Y Warm Reset Y Y Max Reset Y Y System Reset Y Y CPU Reset N Y For more detailed information on the global and local Megamodule resets see the TMS320C64x Megamodule R
335. ough maintenance packets The application software is sent from the host controller to DSP memory The DSP CPU is awakened by interrupt such as a RapidlO DOORBELL packet The application software is executed and normal operation follows For Serial RapidlO boot BOOTMODE2 126 pin is used in conjunction with CFGGP 2 0 T26 026 and 025 pins respectively to determine the device address within the RapidlO network BOOTMODE2 is the MSB of the address while CFGGP 2 0 are used as the three LSBs giving the user the opportunity to have up to 16 unique device IDs BOOTMODE 1 0 L25 and P26 respectively denote the configuration of the RapidlO peripheral i e 006 refers to RapidlO Configuration 0 For exact device RapidlO Configurations see the 5320 645 Bootloader User s Guide literature number SPRUEC6 18 Device Overview Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 The SRIO boot is a software boot mode 2 4 2 2nd Level Bootloaders Any of the boot modes can be used to download a 2nd level bootloader A 2nd level bootloader allows for any level of customization to current boot methods as well as definition of a completely customized boot offers a few second level bootloaders such as EMAC bootloader and a UTOPIA bootloader which can be loaded using the Master I2C boot Submit Documentation Feedback
336. parisons to TMS320TC6416T application report literature number SPRAAS9 If the pin is not used it should be connected directly to the 3 3 V I O supply DVpps3 DVpp15MoN F3 Die side 1 5 1 8 V I O supply DVpp15 voltage monitor pin The monitor pins indicate the voltage on the die and therefore provide the best probe point for voltage monitoring purposes For more information regarding the use of this and other voltage monitoring pins see the TMS320C6455 Design Guide and Comparisons to TMS320TC6416T application report literature number SPRAAS9 If the DVpp4syow pin is not used it should be connected directly to the 1 5 1 8 V I O supply DVppis NOTE If the RGMII mode of the EMAC is not used the DVpp15 DVpp15woN RSV13 and RSV14 pins be connected directly to ground Vss to save power However connecting these pins directly to ground prevents boundary scan from functioning on the RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins see Section 7 3 4 DVpp1sMON A26 Die side 1 8 V I O supply DVppig voltage monitor pin The monitor pins indicate the voltage on the die and therefore provide the best probe point for voltage monitoring purposes For more information regarding the use of this and other voltage monitoring pins see the TMS320C6455 Design Guide and Comparisons to TMS320TC6416T application report literature number SPRAAS9 If the D
337. ply program the strobe width wide enough 3 AARDY is internally synchronized To use AARDY as an asynchronous input the pulse width of the AARDY signal should be at least 2E to ensure setup and hold time is met Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 165 SM320C6455 EP 29 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 7 45 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module 9 9 see Figure 7 33 and Figure 7 34 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 1 losu SELV AOEL Output setup time select signals valid to AAOE low RS E 1 5 ns 2 toh AOEH SELIV Output hold time AAOE high to select signals invalid RS E 1 9 ns 10 la EKOH AOEV Delay time AECLKOUT high to AAOE valid 1 7 ns 11 tosu SELV AWEL Output setup time select signals valid to AAWE low WS E 17 ns 12 tonAwEH sELIV Output hold time AAWE high to select signals invalid WH E 1 8 ns 13 la EKOH AWEV Delay time AECLKOUT high to AAWE valid 1 3 74 ns 1 E AECLKOUT period in ns for EMIFA 2 RS Read setup RST Read strobe RH Read hold WS Write setup WST Write strobe WH Write hold These parameters are programmed via the EMIFA CE Configuration registers CEnCFG 3 Select signals for EMIFA include ACEx ABE 7 0 AEA 19
338. ppismon connect these pins to the 1 8 V I O supply DVpp g e VrerHsti connect to a voltage of DVppi9 2 The DVpp 19 2 voltage can be generated directly from the DVpp4a supply using two 1 resistors to form a resistor divider circuit e RSV13 connect this pin to ground Vss via 200 0 resistor e RSV14 connect this pin to the 1 8 V I O supply DVppig via a 200 0 resistor Similarly when the DDR2 Memory Controller is not used the RSV11 and RSV12 pins can be connected directly to ground Vss to save power However this will prevent boundary scan from functioning on the DDR2 Memory Controller pins To preserve boundary scan functionality on the DDR2 Memory Controller pins RSV11 and RSV12 should be connected as follows e Vprersst_ connect to a voltage of DVppj9 2 The DVppis 2 voltage can be generated directly from the DVpp4a supply using two 1 resistors to form a resistor divider circuit e RSV11 connect this pin to ground Vss via a 200 0 resistor e RSV12 connect this pin to the 1 8 V I O supply DVpp a via a 200 0 resistor C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 44 Enhanced Direct Memory Access EDMA3 Controller The primary purpose of the EDMA3 is to service user programmed data t
339. pture CSR 0 02D0 204C RIO SPO ERR CAPT DBG1 Port 0 Packet Control Symbol Error Capture CSR 1 02D0 2050 RIO SPO ERR DBG2 Port 0 Packet Control Symbol Error Capture CSR 2 02D0 2054 RIO SPO ERR DBG3 Port 0 Packet Control Symbol Error Capture CSR 3 02D0 2058 RIO SPO ERR DBG4 Port 0 Packet Control Symbol Error Capture CSR 4 02D0 205C 0200 2064 Reserved 02D0 2068 RIO SPO ERR RATE Port 0 Error Rate CSR 0 02D0 206C RIO SPO ERR THRESH Port 0 Error Rate Threshold CSR 02D0 2070 02DO 207C Reserved 02D0 2080 RIO SP1 ERR DET Port 1 Error Detect CSR 02D0 2084 RIO SP1 RATE EN Port 1 Error Enable CSR 0200 2088 RIO SP1 ERR ATTR DBGO Port 1 Attributes Error Capture CSR 0 02D0 208C RIO SP1 ERR CAPT DBG1 Port 1 Packet Control Symbol Error Capture CSR 1 02D0 2090 RIO SP1 ERR CAPT DBG2 Port 1 Packet Control Symbol Error Capture CSR 2 02D0 2094 RIO SP1 ERR CAPT DBG3 Port 1 Packet Control Symbol Error Capture CSR 3 02D0 2098 RIO SP1 ERR CAPT DBG4 Port 1 Packet Control Symbol Error Capture CSR 4 02D0 209C 02D0 20A4 Reserved 02D0 20A8 RIO SP1 ERR RATE Port 1 Error Rate CSR 0200 20AC RIO SP1 ERR THRESH Port 1 Error Rate Threshold CSR 0200 20 0 0200 20BC Reserved 02D0 20C0 RIO_SP2_ERR_DET Port 2 Error Detect CSR 02D0 20C4 RIO_SP2_RATE_EN Port 2 Error Enable CSR 02D0 20C8 RIO SP2 ERR ATTR CAPT DBGO Port 2 Attributes Error Capture CSR 0 02D0 20CC RIO SP2 ERR CAPT DBG1 Port 2 Packet Control Symbol Error Capture CSR 1 0200 2000
340. quency in ns For example when running parts at 1000 MHz use P 1 ns 2 For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 3 S Sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period T CLKX period 1 CLKGDV S H CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even H CLKGDV 1 2 S if CLKGDV is odd L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd 4 FSRP FSXP 1 As a SPI Master FSX is inverted to provide active low slave enable output As a Slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master McBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP 5 FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock CLKX CLKX 62 XJ V V V FSX 196 7 le gt 3 DX Bio C Bitn 2 X n3 X na X 4 5 DR BitO __ 1 n2 X m3 X 4 X Figure 7 54 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 0 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas SM320C6455 EP INSTRUMENTS FIXED P
341. r Register 1 02D0 0688 RIO QUEUE2 RXDMA CP Queue Receive DMA Completion Pointer Register 2 02D0 068C RIO QUEUE3 RXDMA CP Queue Receive DMA Completion Pointer Register 3 02D0 0690 RIO QUEUEA RXDMA CP Queue Receive DMA Completion Pointer Register 4 02D0 0694 RIO QUEUE5 RXDMA CP Queue Receive DMA Completion Pointer Register 5 02D0 0698 RIO QUEUE6 RXDMA CP Queue Receive DMA Completion Pointer Register 6 0200 069C RIO QUEUE7 RXDMA CP Queue Receive DMA Completion Pointer Register 7 02D0 06A0 RIO QUEUE8 RXDMA CP Queue Receive DMA Completion Pointer Register 8 02D0 06A4 RIO QUEUE9 RXDMA CP Queue Receive DMA Completion Pointer Register 9 02D0 06A8 RIO QUEUE10 RXDMA CP Queue Receive DMA Completion Pointer Register 10 02D0 06AC RIO QUEUE11 RXDMA CP Queue Receive DMA Completion Pointer Register 11 02D0 06 0 RIO QUEUE12 RXDMA CP Queue Receive DMA Completion Pointer Register 12 02D0 06 4 RIO QUEUE13 RXDMA CP Queue Receive DMA Completion Pointer Register 13 02D0 06B8 RIO QUEUE14 RXDMA CP Queue Receive DMA Completion Pointer Register 14 02D0 06BC RIO QUEUE15 RXDMA CP Queue Receive DMA Completion Pointer Register 15 02D0 06 0 0200 006FC Reserved 02D0 0700 RIO TX QUEUE TEAR DOWN Transmit Queue Teardown Register 02D0 0704 RIO TX CPPI FLOW MASKSO Transmit CPPI Supported Flow Mask Register 0 02D0 0708 RIO TX CPPI FLOW MASKS1 Transmit CPPI Supported Flow Mask Register 1 0200 070C RIO TX CPPI FLOW MASKS2 Transmit CPPI Supported Flow Mask Register 2 02D0 0710 RIO TX CPPI F
342. r SPRU966 Table 7 3 C6455 EDMA3 Channel Synchronization Events CHANNEL BINARY EVENT NAME EVENT DESCRIPTION 0 000 0000 DSP_EVT HPI PCI to DSP event 1 000 0001 TEVTLO0 Timer 0 lower counter event 2 000 0010 TEVTHIO Timer 0 high counter event 3 000 0011 None 4 000 0100 None 5 000 0101 None 6 000 0110 None 7 000 0111 None 8 000 1000 None 9 000 1001 None 10 000 1010 None 11 000 1011 None 12 000 1100 XEVTO McBSPO transmit event 13 000 1101 REVTO McBSPO receive event 14 000 1110 XEVT1 McBSP1 transmit event 15 000 1111 REVT1 McBSP1 receive event 16 001 0000 TEVTLO1 Timer 1 lower counter event 17 001 0001 TEVTHI1 Timer 1 high counter event 1 2 110 In addition to the events shown in this table each of the 64 channels also can be synchronized with the transfer completion or alternate transfer completion events For more detailed information on EDMA event transfer chaining see the TMS320C645x DSP Enhanced DMA EDMA3 Controller User s Guide literature number SPRU966 HPI boot and PCI boot are terminated using a DSP interrupt The DSP interrupt is registered in bit 0 channel 0 of the EDMA Event Register ER This event must be cleared by software before triggering transfers on DMA channel 0 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS SM320C6455 EP
343. r device operation NOTE If the RGMII mode of the EMAC is not used the 15 VREFHSTL RSV14 F1 RSV13 and RSV14 pins can be connected to directly ground Vss to save power However connecting these pins directly to ground prevents boundary scan from functioning on the RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins see Section 7 3 4 Reserved This pin must be connected via 39 Q resistor directly to ground RSV15 T1 Vss for proper device operation The resistor used should have a minimal rating of 1 10 W Reserved This pin must be connected via a 20 Q resistor directly to 3 3 V I O RSV16 T2 Supply DVpp33 for proper device operation The resistor used should have a minimal rating of 1 10 W RSV17 AE21 A RSV18 E13 A RSV19 F18 A RSV20 U29 A RSV21 A6 A RSV22 B26 RSV23 C26 RSV24 B6 RSV25 C6 RSV26 AJ11 A Reserved Leave unconnected do not connect to power or ground RSV27 AH11 A RSV36 AD11 VO Z IPU RSV37 AD9 VO Z IPU RSV38 AG10 VO Z IPU RSV39 AG11 VO Z IPU RSV40 AJ12 VO Z IPU RSV41 W28 O Z IPU RSV42 Y26 O Z IPU RSV43 Y25 O Z IPU RSV44 Y27 O Z RSV28 N7 A RSV29 N6 A Reserved These pins must be connected directly to Vss for proper device RSV30 P23 A operation RSV31 P24 A RSV32 D25 Reserved This pin must be connected to the 1 8 V I O supply DVppig via a 1 resistor for proper device operation Reserved This pin must be connected directly to g
344. r the 4x RapidlO port or approximately 9 Gbps data throughput rate 7 20 1 Serial RapidlO Device Specific Information The approach to specifying interface timing for the SRIO Port is different than on other interfaces such as EMIF HPI and McBSP For these other interfaces the device timing was specified in terms of data manual specifications and I O buffer information specification IBIS models For the C6455 SRIO Port Texas Instruments provides a printed circuit board PCB solution showing two DSPs connected via a 4x SRIO link directly to the user has performed the simulation and system characterization to ensure all SRIO interface timings in this solution are met The complete SRIO system solution is documented in the Implementing Serial Rapid I O PCB Layout on a TMS320C6455 Hardware Design application report literature number SPRAAAS only supports designs that follow the board design guidelines outlined in the SPRAAA8 application report The Serial RapidlO peripheral is a master peripheral in the C6455 DSP It conforms to the RapidlO Interconnect Specification Part VI Physical Layer 1x 4x LP Serial Specification Revision 1 2 If the SRIO peripheral is not used the SRIO reference clock inputs and SRIO link pins can be left unconnected If the SRIO peripheral is enabled but not all links are used the pins of the unused links can be left unconnected and no terminations are needed For more information see the TMS
345. ral Specific Registers 0200 1000 RIO DEV ID Device Identity CAR 02D0 1004 RIO DEV INFO Device Information CAR 02D0 1008 RIO ASBLY ID Assembly Identity CAR 0200 100C RIO ASBLY INFO Assembly Information CAR 0200 1010 RIO PE FEAT Processing Element Features CAR 0200 1014 Reserved 0200 1018 RIO SRC OP Source Operations CAR 02D0 101C RIO DEST OP Destination Operations CAR 02D0 1020 02DO 1048 Reserved 02D0 104C RIO PE LL CTL Processing Element Logical Layer Control CSR 0200 1050 0200 1054 Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 241 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 6 INSTRUMENTS www ti com Table 7 112 RapidlO Control Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02D0 1058 RIO_LCL_CFG_HBAR Local Configuration Space Base Address 0 CSR 02D0 105C RIO_LCL_CFG_BAR Local Configuration Space Base Address 1 CSR 02D0 1060 RIO BASE ID Base Device ID CSR 02D0 1064 Reserved 02D0 1068 RIO HOST BASE ID LOCK Host Base Device ID Lock CSR 02D0 106C RIO COMP TAG Component Tag CSR 02D0 1070 02DO 10FC Reserved RapidlO Extended Features LP Serial Registers 0200 1100 RIO SP MB HEAD 1x 4x LP
346. ransfers between two memory mapped slave endpoints on the device The EDMAS services software driven paging transfers e g data movement between external memory and internal memory performs sorting or subframe extraction of various data structures services event driven peripherals such as a McBSP or the UTOPIA port and offloads data transfers from the device CPU The EDMA3 includes the following features Fully orthogonal transfer description Three transfer dimensions array multiple bytes frame multiple arrays and block multiple frames Single event can trigger transfer of array frame or entire block Independent indexes on source and destination Flexible transfer definition Increment or FIFO transfer addressing modes Linking mechanism allows for ping pong buffering circular buffering and repetitive continuous transfers all with no CPU intervention Chaining allows multiple transfers to execute with one event 256 PaRAM entries Used to define transfer context for channels Each PaRAM entry can be used as a DMA entry QDMA entry or link entry 64 DMA channels Manually triggered CPU writes to channel controller register external event triggered and chain triggered completion of one transfer triggers another Four Quick DMA QDMA channels Used for software driven transfers Triggered upon writing to a single PaRAM set entry Four transfer controllers event queues with p
347. ransmit and Receive 256 to 511 Octet Frames Register 02C8 0278 FRAM E512T1023 Transmit and Receive 512 to 1023 Octet Frames Register 02C8 027C FRAME1024TUP Transmit and Receive 1024 to 1518 Octet Frames Register 02C8 0280 NETOCTETS Network Octet Frames Register 02C8 0284 RXSOFOVERRUNS Receive FIFO or DMA Start of Frame Overruns Register 02C8 0288 RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register 02C8 028C RXDMAOVERRUNS Receive DMA Start of Frame and Middle of Frame Overruns Register 02C8 0290 02C8 02FC Reserved Table 7 73 EMAC Control Module Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 1000 Reserved 02C8 1004 EWCTL EMAC Control Module Interrupt Control Register 02C8 1008 EWINTTCNT EMAC Control Module Interrupt Timer Count Register 02 8 100C 02C8 17FF Reserved Table 7 74 EMAC Descriptor Memory HEX ADDRESS RANGE ACRONYM DESCRIPTION 02C8 2000 02C8 3FFF EMAC Descriptor Memory Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 207 SM320C6455 EP 9 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 14 3 Electrical Data Timing 7 14 3 1 EMAC GMII Electrical Data Timing www ti com Table 7 75 Timing Requirements for MRCLK MII and GMII Operation see Figure 7 59
348. rements All rise and fall transition timing parameters are referenced to Vi MAX and Vi MIN for input clocks MAX and Voy MIN for output clocks Vret Vin MIN or MIN Vref Vip MAX or MAX Figure 7 3 Rise and Fall Transition Time Voltage Reference Levels 7 1 2 3 3 V Signal Transition Rates All timings are tested with an input edge rate of 4 volts per nanosecond 4 V ns Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 105 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 www ti com 7 1 3 Timing Parameters and Board Routing Analysis 106 The timing parameter values specified in this data sheet do not include delays by board routings As a good board design practice such delays must be taken into account Timing values may be adjusted by increasing decreasing such delays recommends utilizing the available I O buffer information specification IBIS models to analyze the timing characteristics correctly To properly use IBIS models to attain accurate timing analysis for a given system see the Using IBIS Models for Timing Analysis application report literature number SPRA839 If needed external logic hardware such as buffers may be used to compensate any timing differences For inputs timing is most impacted by the round trip propagation delay from the DSP to the external device
349. rogrammable system level priority Interrupt generation for transfer completion and error conditions Memory protection support Active memory protection for accesses to PaRAM and registers Debug visibility Queue watermarking threshold allows detection of maximum usage of event queues Error and status recording to facilitate debug Each of the transfer controllers has a direct connection to the switched central resource SCR NOTE Although the transfer controllers are directly connected to the SCR they can access only certain device resources For example only transfer controller 1 TC1 can access the McBSPs Table 4 1 lists the device resources that can be accessed by each of the transfer controllers Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 109 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 4 1 EDMA3 Device Specific Information www ti com The EDMA supports two addressing modes constant addressing and increment addressing mode Constant addressing mode is applicable to a very limited set of use cases for most applications increment mode can be used On the C6455 DSP the EDMA can use constant addressing mode only with the Enhanced Viterbi Decoder Coprocessor VCP2 and the Enhanced Turbo Decoder Coprocessor 2 Constant addressing mode is not supported by any other peripheral or inter
350. rogrammed with predetermined values The boot sequence is started automatically after each power on reset warm reset max reset and system reset For more details on the initiators of these resets see Section 7 6 Reset Controller There are several methods by which the memory and register initialization can take place Each of these methods is referred to as a boot mode The boot mode to be used is selected at reset through the BOOTMODE 3 0 pins Each boot mode can be classified as a hardware boot mode or as a software boot mode Software boot modes require the use of the on chip bootloader The bootloader is DSP code that transfers application code from an external source into internal or external program memory after the DSP is taken out of reset The bootloader is permanently stored in the internal ROM of the DSP starting at byte address 0010 0000h Hardware boot modes are carried out by the boot configuration logic The boot configuration logic is actual hardware that does not require the execution of DSP code Section 2 4 1 Boot Modes Supported describes each boot mode in more detail When accessing the internal ROM of the DSP the CPU frequency must always be less than 750 MHz Therefore when using a software boot mode care must be taken such that the CPU frequency does not exceed 750 MHz at any point during the boot sequence After the boot sequence has completed the CPU frequency can be programmed to the frequency required by the applic
351. round for proper device RSV33 C25 operation RSV34 E6 Reserved This pin must be connected to the 1 8 V I O supply DVppig via a 1 resistor for proper device operation RSV35 D6 Reserved This pin must be connected directly to ground for proper device operation Submit Documentation Feedback Device Overview 45 SM320C6455 EP 3 TEXAS FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 www ti com Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION SUPPLY VOLTAGE MONITOR PINS 1 Die side 1 2 V supply CVpp voltage monitor The monitor pins indicate the voltage on the die and therefore provide the best probe point for voltage monitoring purposes For more information regarding the use of this and other voltage monitoring pins see the TMS320C6455 Design Guide and Comparisons to TMS320TC6416T application report literature number SPRAA89 If the pin is not used it should be connected directly to the 1 2 V core supply CVpp DVppasMoN L6 Die side 3 3 V I O supply DVpp33 voltage monitor pin The monitor pins indicate the voltage on the die and therefore provide the best probe point for voltage monitoring purposes For more information regarding the use of this and other voltage monitoring pins see the TMS320C6455 Design Guide and Com
352. rry bits 1 and 0 of the byte address ABAO DDR2 EN V26 O Z IPD DDR2 Memory Controller enable DDR2 EN ABAO 0 DDR2 Memory Controller peripheral pins are disabled default 1 DDR2 Memory Controller peripheral pins are enabled EMIFA enable EMIFA_EN ABA1 0 EMIFA peripheral pins are disabled default 1 EMIFA peripheral pins are enabled ACES v27 0 2 memory space enables ACE4 V28 O Z IPU Enabled by bits 28 through 31 of the word address ACE3 W26 O Z IPU Only one pin is asserted during any external data access ACE W27 O Z IPU Note The C6455 device does not have ACEO and pins W29 O Z IPU ABE6 K26 O Z IPU ABES L29 0 2 byte enable control ABE4 L28 O Z IPU Decoded from the low order address bits The number of address bits or ABE3 AA29 O Z IPU byte enables used depends on the width of external memory 28 0 2 IPU e Byte write enables for most types of memory ABE1 AA25 O Z IPU ABEO AA26 O Z IPU EMIFA 64 BIT BUS ARBITRATION AHOLDA N26 IPU EMIFA hold request acknowledge to the host AHOLD R29 IPU EMIFA hold request from the host ABUSREQ L27 IPU EMIFA bus request output EMIFA 64 ASYNCHRONOUS SYNCHRONOUS MEMORY CONTROL EMIFA external input clock The EMIFA input clock AECLKIN or SYSCLK4 AECLKIN N29 IPD clock is selected at reset via the pullup pulldown resistor on the AEA 15 pin Note AECLKIN is the default for the EMIFA input clock AECLKOUT V29 O
353. rupt Register 02B0 008C Reserved 02B0 0090 02 0 00FF Reserved 02B0 0100 02B0 3FFF Reserved 246 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 21 3 GPIO Electrical Data Timing Table 7 114 Timing Requirements for GPIO Inputs see Figure 7 78 720 850 NO A 1000 1000 UNIT 1200 MIN MAX tw GPIH Pulse duration high 12P ns 2 lw GPIL Pulse duration GPIx low 12P ns 1 1 CPU clock frequency in ns For example when running parts at 1000 MHz use 1 ns 2 The pulse width given is sufficient to generate a CPU interrupt or an EDMA event However if a user wants to have the DSP recognize the GPIx changes through software polling of the GPIO register the GPIx duration must be extended to at least 24P to allow the DSP enough time to access the GPIO register through the CFGBUS Table 7 115 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs see Figure 7 78 720 850 NO PARAMETER 000 UNIT MIN MAX 3 tw GPOH Pulse duration GPOx high 36 32 ns tw GPOL Pulse duration GPOx low 36P 8 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 This parameter value should not
354. s 32K bytes this corresponds to the internal ROM Starting address is 0010 0000h 1 cycle latency 1 x 256 bit bank configuration L2 memory can be configured as all SRAM or as part 4 way set associative cache The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register L2CFG of the C64x Megamodule Figure 5 4 shows the available SRAM cache configurations for L2 By default L2 is configured as all SRAM after device reset L2 mode bits Block base 000 001 010 011 111 L2 memory address 0080 0000h 7 8 SRAM 1840K bytes 15 16 SRAM All 63 64 31 32 SRAM SRAM SRAM 009C 0000h 4 way 128K bytes cache 009E 0000h 4 way 64K bytes rm cache 32K bytes 009F 0000h 4 009 8000h seh bytes 00 0 0000h Figure 5 4 C6455 L2 Memory Configurations For more information on the operation L1 and L2 caches see the TMS320C64x DSP Cache User s Guide literature number SPRU862 All memory on the C6455 has a unique location in the memory map see Table 2 2 C6455 Memory Map Summary When accessing the internal ROM of the DSP the CPU frequency must be less than 750 MHz Therefore when using a software boot mode care must be taken such that the CPU frequency does not exceed 750 MHz at any point during the boot sequence After the boot sequence has completed the CPU frequency can be programmed to the frequency required by the
355. s AAOE identified under select signals and AAWE respectively during asynchronous memory accesses Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register AWCC Figure 7 34 Asynchronous Memory Write Timing for EMIFA f Strobe 7 f 34 Strobe 2 k Extended Strobe 4 I Hold 2 9 AECLKOUT T y X A Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register AWCC Figure 7 35 AARDY Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 167 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 TExAS INSTRUMENTS www ti com 7 10 3 2 Programmable Synchronous Interface Timing Table 7 46 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module see Figure 7 36 720 850 NO A 1000 1000 UNIT 1200 MAX tsu EDV EKOH Setup time read AEDx valid before AECLKOUT high 2 ns th EKOH EDV Hold time read AEDx valid after AECLKOUT high 1 5 ns Table 7 47 Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for EMIFA Module see Figure 7 36 Figure 7
356. s read as 0 A value written to this field has no effect 1 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 GOSET GO operation command for SYSCLK rate change and phase alignment Before setting this bit to 1 to initiate a GO operation check the GOSTAT bit in the PLLSTAT register to ensure all previous GO operations have completed 0 No effect Write of 0 clears bit to 0 Initiates GO operation Write of 1 initiates GO operation Once set GOSET remains set but further writes of 1 can initiate the GO operation Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 155 SM320C6455 EP 9 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 8 3 3 PLL Controller Status Register The PLL controller status register PLLSTAT shows the PLL controller status PLLSTAT is shown in Figure 7 26 and described in Table 7 35 31 16 R 0 15 1 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Figure 7 26 PLL Controller Status Register PLLSTAT Hex Address 029C 013C Table 7 35 PLL Controller Status Register PLLSTAT Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 GOSTAT GO operation status
357. sing the default settings in the EMIFA registers This boot mode is a hardware boot mode e Master I2C boot BOOTMODE 3 0 0101b After reset the DSP can act as a master to the 2 bus and copy data from an 2 EEPROM or a device acting as an 2 slave to the DSP using a predefined boot table format The destination address and length are contained within the boot table This boot mode is a software boot mode e Slave I2C boot BOOTMODE 3 0 0110b A Slave 2 boot is also implemented which programs the DSP as 12C Slave and simply waits for a Master to send data using a standard boot table format Using the Slave I2C boot a single DSP or a device acting as an 2 Master can simultaneously boot multiple slave DSPs connected to the same 2 bus Note that the Master DSP may require booting via an 2 EEPROM before acting as a Master and booting other DSPs The Slave 2 boot is a software boot mode e Serial RapidlO boot BOOTMODE 3 0 1000b through 1111b After reset the following sequence of events occur The on chip bootloader configures device registers including SerDes and EDMA3 The on chip bootloader resets the peripheral s state machines and registers RapidlO ports send idle control symbols to initialize SerDes ports The host explores the system with RapidlO maintenance packets The host identifies enumerates and initializes the RapidlO device The host controller configures DSP peripherals thr
358. source clock UXCLK driven by Master ATM Controller I or when the UTOPIA peripheral is disabled UTOPIA_EN AEA12 pin 0 this UXCLK MTCLK N4 pin is either EMAC MII default GMII transmit clock MTCLK I or the RMREFCLK EMAC RMII reference clock RMREFCLK I The EMAC function is controlled by the MACSEL 1 0 AEA 10 9 pins For more detailed information see Section 3 Device Configuration UTOPIA transmit Start of Cell signal O This signal is output by the UTOPIA Slave on the rising edge of the UXCLK indicating that the first valid byte of the cell is available on the 8 bit Transmit Data Bus UXDATA 7 0 UXSOC MCOL K3 VO Z When the UTOPIA peripheral is disabled UTOPIA_EN AEA12 pin 0 this is the EMAC collision sense MCDL I for MII default or MACSEL 1 0 dependent UTOPIA transmit interface enable input signal default I or when the UTOPIA UXENB MTXEN J5 VO Z peripheral is disabled UTOPIA EN AEA12 0 this pin is either the RMTXEN EMAC transmit enable MTXEN O for MII default RMII or GMII MACSEL 1 0 dependent UXDATA7 MTXD7 N5 UXDATA6 MTXD6 M3 UXDATAS MTXD5 L5 UTOPIA 8 bit transmit data bus O default or EMAC transmit data bus for MII default RMII or GMII UXDATA4 MTXD4 L3 2 Using the Transmit Data Bus the UTOPIA Slave on the rising edge of the UXDATAS MTXD3 K4 O Z UXCLK transmits the 8 bit ATM cells to the Master ATM Controller UADATAZAMTXD2 When the UTO
359. t Note If a configuration pin must be routed out from the device and 3 stated not driven the internal pullup pulldown IPU IPD resistor should not be relied upon TI recommends the use of an external pullup pulldown resistor For more detailed information on pullup pulldown resistors and situations where external p ullup pulldown resistors are required see Section 3 7 Pullup Pulldown Resistors Table 7 15 Switching Characteristics Over Recommended Operating Conditions During Reset see Figure 7 9 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 9 typorH RsTaTH Delay time POR high AND RESET high to RESETSTAT high 15000C ns 1 C 1 CLKIN1 clock frequency in ns For Figure 7 8 note the following e Z group consists of all 1 0 4 O Z pins except for Low and High group pins Pins become high impedance as soon as their respective power supply has reached normal operating conditions Pins remain in high impedance until configured otherwise by their respective peripheral Low group consists of UXDATAO MTXDO RMTXDO UXDATA1 MTXD1 RMTXD1 UXDATA2 MTXD2 RMTXD2 UXDATA3 MTXD3 RMTXD3 UXDATA4 MTXD4 RMTXD4 and UXENB MTXEN RMTXEN Pins become low as soon as their respective power supply has reache d normal operating conditions Pins remain low until configured otherwise by their respective peripheral e High group consists of AHOLD ABUSREQ and HRDY PIRDY Pins become high as so
360. t in several ways In the C64x core dual 16 bit MIN2 and MAX2 comparisons were available only on the L units On the C64x core they also are available on the S unit which increases the performance of algorithms that do searching and sorting Finally to increase data packing and unpacking throughput the S unit allows sustained high performance for the quad 8 bit 16 bit and dual 16 bit instructions Unpack instructions prepare 8 bit data for parallel 16 bit operations Pack instructions return parallel results to output precision including saturation support Device Overview Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Other new features include SPLOOP A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel SPLOOP buffer reduces the code size associated with software pipelining Furthermore loops in the SPLOOP buffer are fully interruptible Compact Instructions The native instruction size for the C6000 devices is 32 bits Many common instructions such as MPY AND OR ADD and SUB can be expressed as 16 bits if the C64x compiler can restrict the code to use certain registers in the register file This compression is performed by the code generation tools Instruction Set Enhancements As noted above there are n
361. ter Clock Prescale Y Bit Clock Generator 6 INSTRUMENTS www ti com Peripheral Clock CPU 6 Control Own 2 Address Slave IPCSAR Address I2CMDR Mode Transmit 12C Data X Noise Filter Transmit Shift Transmit Buffer Data I2CCNT Count Extended Mode I2ZCEMDR Interrupt DMA Receive I2CDRR Shading denotes control status reg Receive Buffer Receive Shift Interrupt I2CIMR Mask Status Interrupt 2 5 Status Interrupt I2CIVR Vector isters Figure 7 41 2 Module Block Diagram C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 11 2 12 Peripheral Register Description s Table 7 51 I2C Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02B0 4000 ICOAR I2C own address register 02B0 4004 ICIMR I2C interrupt mask status register 02B0 4008 ICSTR 2 interrupt status register 02 0 400 ICCLKL 2 clock low time divider register 02B0 4010 2 clock high time divider register 02B0 4014 ICCNT 12 data count register 02B0 4018 ICDRR I2C data receive register 02B0 401C ICSAR I2C slave address
362. ter 1 02A2 034C DFDST1 Destination FIFO Destination Address Register 1 02A2 0350 DFBIDX1 Destination FIFO BIDX Register 1 02A2 0354 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1 02A2 0358 02A2 037C Reserved 02A2 0380 DFOPT2 Destination FIFO Options Register 2 02A2 0384 DFSRC2 Destination FIFO Source Address Register 2 02A2 0388 DFCNT2 Destination FIFO Count Register 2 02A2 038C DFDST2 Destination FIFO Destination Address Register 2 02A2 0390 DFBIDX2 Destination FIFO BIDX Register 2 02A2 0394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 02A2 0398 02A2 03BC Reserved 02A2 03C0 DFOPT3 Destination FIFO Options Register 3 02 2 03 4 DFSRC3 Destination FIFO Source Address Register 3 02A2 03C8 DFCNT3 Destination FIFO Count Register 3 02A2 03CC DFDST3 Destination FIFO Destination Address Register 3 02A2 03D0 DFBIDX3 Destination FIFO BIDX Register 3 02A2 03D4 DFMPPRXY3 _ Destination FIFO Memory Protection Proxy Register 3 02 2 0308 02 2 7FFF Reserved Ta ble 7 7 EDMAS Transfer Controller 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 8000 PID Peripheral Identification Register 02A2 8004 TCCFG Configuration Register 02A2 8008 02A2 80FC Reserved 02A2 8100 TCSTAT Channel Status Register 02A2 8104 02A2 811C Reserved 02A2 8120 ERRSTAT Error Register 02A2 8124 ERREN Error Enable Register
363. ter 3 02A3 83C8 DFCNT3 Destination FIFO Count Register 3 02 83CC DFDST3 Destination FIFO Destination Address Register 3 02A3 83D0 DFBIDX3 Destination FIFO BIDX Register 3 02A3 83D4 DFMPPRXY3 _ Destination FIFO Memory Protection Proxy Register 3 02A3 83D8 02A3 FFFF Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 123 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 5 Interrupts 6 INSTRUMENTS www ti com 7 5 1 Interrupt Sources and Interrupt Controller The CPU interrupts on the C6455 device are configured through the C64x Megamodule Interrupt Controller The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs CPUINT4 CPUINT15 the CPU exception input EXCEP or the advanced emulation logic The 128 system events consist of both internally generated events within the megamodule and chip level events Table 7 10 shows the mapping of system events For more information on the Interrupt Controller see the TMS320C64x Megamodule Reference Guide literature number SPRU871 Table 7 10 C6455 System Event Mapping EVENT NUMBER INTERRUPT EVENT DESCRIPTION 04 EVTO Output of event combiner 0 in interrupt controller for events 1 31 10
364. th URCH URAV Hold time URADDR valid after URCLK high 9 lsuURENBL URcH Setup time URENB low before URCLK high t t t ns ns ns OO N ns ns 10 h URCH URENBL Hold time URENB low after URCLK high 11 su URSH URCH Setup time URSOC high before URCLK high 12 h URCH URSH Hold time URSOC high after URCLK high ns ns EMEN x SN ns Table 7 111 Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave Receive Cycles see Figure 7 77 720 850 NO PARAMETER A 1000 1000 UNIT 1200 MIN MAX 5 Ia URCH URCLAV Delay time URCLK high to URCLAV driven active value 3 12 ns 6 ta URCH URCLAVL Delay time URCLK high to URCLAV driven inactive low 3 12 ns 7 td URCH URCLAVHZ Delay time URCLK high to URCLAV going Hi Z 9 18 5 ns 8 tw URCLAVL URCLAVHZ Pulse duration low URCLAV low to URCLAV Hi Z 3 ns URCLK Z A ZZ N N _ _ gt le 2 ee URDATA T X P48 C Hn X H X H gt 4 m URADDRI4 0 N X oF j Na X OF ma lt gt 8 45 gt 6 URCLAV N N42 T 10 M 9 URENB _ T le 11 pje 12 URSOC F Y A The UTOPIA Slave module has signals that are middle level signals indicating a high impedance state i e the URCLAV and URSCC signals Figure 7 77 UTOPIA Slave Receive Timing
365. the PLL controllers immediately change their system clocks to their default divide down values Other device initialization is also started 3 After device initialization is complete the RESETSTAT pin goes inactive high All system clocks are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks After the pause the system clocks are restarted at their default divide by settings 4 The device is now out of reset device execution begins as dictated by the selected boot mode see Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 129 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Section 2 4 Boot Sequence NOTE The POR pin should be held inactive high throughout the Warm Reset sequence Otherwise if POR is activated brought low the minimum POR pulse width must be met The RESET pin should not be tied together with the POR pin 7 6 3 Max Reset A Max Reset is initiated by the RapidlO peripheral and has the same affect as a Warm Reset 7 6 4 System Reset The emulator initiates a System Reset via the ICEPick module This ICEPick initiated reset is non maskable To invoke the maximum reset via the ICEPick module the user can perform the following from the Code Composer Studio IM menu Debug Advanced Resets System Reset The follow
366. the UTOPIA peripheral is disabled UTOPIA_EN AEA12 pin 0 this pin is EMAC GMII transmit clock MACSEL 1 0 dependent UTOPIA transmit interface enable input signal Asserted by the Master ATM Controller to indicate that the UTOPIA Slave should put out on the Transmit UXENB MTXEN 2 Bus the first byte of valid data and the UXSOC signal the next clock When the UTOPIA peripheral is disabled UTOPIA_EN AEA12 pin 0 this pin is either the EMAC MII transmit enable default or EMAC RMII transmit enable or EMAC GMII transmit enable MACSEL 1 0 dependent Transmit Start of Cell signal This signal is output by the UTOPIA Slave on the rising edge of the UXCLK indicating that the first valid byte of the cell is available on the 8 bit Transmit Data Bus UXDATA 7 0 UXSOC MCOL K3 Voz When the UTOPIA peripheral is disabled UTOPIA EN AEA12 pin 0 this pin is either the EMAC MII collision sense or EMAC GMII collision sense MACSEL 1 0 dependent UXADDR4 MDCLK M5 UTOPIA transmit address pins UXADDR 4 0 I UXADDR3 MDIO N3 As UTOPIA transmit address pins UTOPIA_EN AEA12 pin 1 e 5 bit Slave transmit address input pins driven by the Master ATM Controller UXADDR2 PCBES PS to identify and select one of the Slave devices up to 31 possible in the UXADDR1 PIDSEL R3 l ATM System When the UTOPIA peripheral is disabled UTOPIA_EN AEA12 pin 0 and if the pin 1 these pins are PCI peripheral pins
367. thernet MAC EMAC IEEE 802 3 Compliant Supports Multiple Media Independent Interfaces MII GMII RMII RGMII Eight Independent Transmit TX and Eight Independent Receive RX Channels Two 64 Bit General Purpose Timers Configurable as Four 32 Bit Timers UTOPIA UTOPIA Level 2 Slave ATM Controller 8 Bit Transmit and Receive Operations up to 50 MHz per Direction User Defined Cell Format up to 64 Bytes 16 General Purpose I O GPIO Pins 5 Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document C64x JTAG C64x VelociTl C6000 Code Composer Studio DSP BIOS XDS are trademarks of Texas Instruments PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 2007 2008 Texas Instruments Incorporated SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 e System PLL and PLL Controller e Secondary PLL and PLL Controller Dedicated to EMAC and DDR2 Memory Controller Advanced Event Triggering AET Compatible e Trace Enabled Device e EEE 1149 1 JTAG 6 INSTRUMENTS www ti c
368. trical Specifications 131 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 6 7 Reset Controller Register The reset type status RSTYPE register 029A OOE4 is the only register for the reset controller This register falls in the same memory range as the PLL1 controller registers 029A 0000 029A 01FF see Table 7 18 7 6 7 1 Reset Type Status Register Description The rest type status RSTYPE register latches the cause of the last reset If multiple reset sources occur simultaneously this register latches the highest priority reset source The reset type status register is shown in Figure 7 7 and described in Table 7 13 31 16 Reserved R 0 15 4 3 2 1 0 Reserved SRST MRST WRST POR R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Figure 7 7 Reset Type Status Register RSTYPE Hex Address 029A 00E4 Table 7 13 Reset Type Status Register RSTYPE Field Descriptions Bit Field Value Description 31 4 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 3 SRST System reset 0 System Reset was not the last reset to occur System Reset was the last reset to occur 2 MRST Max reset 0 Max Reset was not the last reset to occur Max Reset was the last reset to occur 1 WRST Warm reset 0 Warm Reset was not th
369. ts all AC timing specifications as required by the PC Local Bus Specification version 2 3 The AC timing specifications are not reproduced here For more information on the timing specifications see section 4 2 3 Timing Specification 33 MHz timing and section 7 6 4 Timing Specification 66 MHz timing of the PCI Local Bus Specification version 2 3 Note that the C6455 PCI peripheral only supports 3 3 V signaling Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 229 5 320 6455 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 19 UTOPIA 7 19 1 UTOPIA Device Specific Information 6 INSTRUMENTS www ti com The Universal Test and Operations PHY Interface for ATM UTOPIA peripheral is a 50 MHz 8 Bit Slave only interface The UTOPIA is more simplistic than the Ethernet MAC in that the UTOPIA is serviced directly by the controller The UTOPIA peripheral contains two two cell FIFOs one for transmit and one for receive with which to buffer up data sent received across the pins There is a transmit and a receive event to the EDMA3 channel controller to enable servicing For more detailed information on the UTOPIA peripheral see the TMS320C645x DSP Universal Test and Operations PHY Interface for ATM 2 UTOPIA2 User s Guide literature number SPRUE48 7 19 2 UTOPIA Peripheral Register Description s Table 7 104 UT
370. ubmit Documentation Feedback 4 TEXAS SM320C6455 EP INSTRUMENT S FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE iPD IPU DESCRIPTION NAME NO RESETS INTERRUPTS AND GENERAL PURPOSE INPUT OUTPUTS RESET AG14 Device reset Nonmaskable interrupt edge driven rising edge NMI AH4 IPD Any noise on the NMI pin may trigger an NMI interrupt therefore if the NMI pin is not used it is recommended that the NMI pin be grounded versus relying on the IPD RESETSTAT AE14 Reset Status pin The RESETSTAT indicates when the device is reset POR AF14 Power on reset GP 7 AG2 VO Z IPD GP 6 AG3 VO Z IPD General purpose input output GPIO pins I O Z GP 5 AJ2 VO Z IPD GP 4 AH2 VO Z IPD URADDR3 PREQ GP 15 P2 VO Z URADDR2 PINTA9 GP 14 P3 VO Z UTOPIA received address pins or PCI peripheral pins or General purpose RADDR1 PRST S R5 I O Z input output GPIO 15 12 2 pins I O Z default URADDRO PGNT PCI bus request 0 2 or GP 15 l O Z default GP 12 R4 VO Z PCI interrupt 0 2 or GP 14 0 2 default 5 PCI reset I or GP 13 1 0 2 default FSXt GP 11 AG4 VO Z IPD PCI bus grant or GP 12 l O Z default FSR1 GP 10 AE5 VO Z IPD PCI command byte enable 0 0 2 or GP 2 I O
371. ult mode 0001 Host boot HPI 0010 Reserved 0011 Reserved 0100 EMIFA 8 bit ROM boot 0101 Master 2 boot 0110 Slave 2 boot 0111 Host boot PCI 1000 Serial Rapid I O boot For more detailed information on the boot modes see Section 2 4 Boot thru Sequence of this document 1111 3 6 JTAG ID JTAGID Register Description The JTAG ID register is a read only register that identifies to the customer the JTAG Device ID For the C6455 device the JTAG ID register resides at address location 0 02 8 0008 For the actual register bit names and their associated bit field descriptions see Figure 3 11 and Table 3 14 31 28 27 12 11 1 O VARIANT PART NUMBER MANUFACTURER 4 bit 16 bit 11 bit R n R 0000 0000 1000 1010b 0000 0010 111b R 1 LEGEND R Read only n value after reset Figure 3 11 JTAG ID JTAGID Register 0x02A8 0008 Table 3 14 JTAG ID JTAGID Register Field Descriptions Bit Field Value Description 31 28 VARIANT Variant 4 Bit value The value of this field depends on the silicon revision being used For more information see the TMS320C6455 Digital Signal Processor Silicon Errata literature number SPRZ234 Note the VARIANT field may be invalid if no CLKIN1 signal is applied 27 12 PART NUMBER Part Number 16 Bit value C6455 value 0000 0000 1000 1010b 11 1 MANUFACTURER Manufacturer 11 Bit value C6455 value 0000 0
372. ved 02D0 0290 RIO DOORBELL1 ICRR DOORBELL1 Interrupt Condition Routing Register 02D0 0294 RIO_DOORBELL1_ICRR2 DOORBELL 1 Interrupt Condition Routing Register 2 02D0 0298 02D0 029C Reserved 02D0 02A0 RIO_DOORBELL2_ICRR DOORBELL2 Interrupt Condition Routing Register 02D0 02A4 RIO_DOORBELL2_ICRR2 DOORBELL 2 Interrupt Condition Routing Register 2 02D0 02A8 02D0 02AC Reserved 02D0 02B0 RIO_DOORBELL3_ICRR DOORBELL3 Interrupt Condition Routing Register 02D0 02B4 RIO_DOORBELL3_ICRR2 DOORBELL 3 Interrupt Condition Routing Register 2 02D0 02B8 02D0 02BC Reserved 02D0 02C0 RIO_RX_CPPI_ICRR Receive CPPI Interrupt Condition Routing Register 0200 0204 RIO_RX_CPPI_ICRR2 Receive CPPI Interrupt Condition Routing Register 2 02D0 02C8 02D0 02CC Reserved 02D0 02D0 RIO_TX_CPPI_ICRR Transmit CPPI Interrupt Condition Routing Register 02D0 02D4 RIO_TX_CPPI_ICRR2 Transmit CPPI Interrupt Condition Routing Register 2 02D0 02D8 02D0 02DC Reserved 02D0 02E0 RIO_LSU_ICRRO LSU Interrupt Condition Routing Register 0 02D0 02E4 RIO LSU ICRR1 LSU Interrupt Condition Routing Register 1 02D0 02bE8 RIO LSU ICRR2 LSU Interrupt Condition Routing Register 2 0200 02 RIO LSU ICRR3 LSU Interrupt Condition Routing Register 3 236 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR ki TEXAS INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED
373. ved R 0000 0000 0000 0000 15 12 11 9 8 6 5 3 2 0 Reserved SRIO Reserved HOST EMAC R 000 0 R W 001 R 100 R W 010 R W 001 LEGEND R W Read Write R Read only n value at reset 86 Figure 4 3 Priority Allocation Register PRI ALLOC System Interconnect Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 5 64 Megamodule The C64x Megamodule consists of several components the C64x CPU the L1 program and data memory controllers the L2 memory controller the internal DMA IDMA the interrupt controller power down controller and external memory controller The C64x Megamodule also provides support for memory protection for L1P L1D and L2 memories and bandwidth management for resources local to the C64x Megamodule Figure 5 1 shows a block diagram of the C64x Megamodule L1P cache SRAM L1 program memory controller L2 L2 memory Gane control Advanced event Peat controller Bandwidth management triggering Memory protection AET SRAM Cache control Bandwidth C64x CPU Internal management SPLOOP buffer protection 16 32 bit instruction dispatch Data path 1 Data path 2 External memory controller To Chip 32 Configuration registers Registers 128 Interrupt cs 45 Slave L1 data
374. vice Configurations Inputs during reset include AEA 19 0 ABA 1 0 and Figure 7 9 Warm Reset and Max Reset Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 135 SM320C6455 EP Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 7 136 www ti com PLL1 and PLL1 Controller The primary PLL controller generates the input clock to the C64x megamodule including the CPU as well as most of the system peripherals such as the multichannel buffered serial ports McBSPs and the external memory interface EMIF As shown in Figure 7 10 the PLL1 controller features a software programmable PLL multiplier controller PLLM and five dividers PREDIV D2 D3 D4 and D5 The PLL1 controller uses the device input clock to generate a system reference clock SYSREFCLK and four system clocks SYSCLK2 SYSCLK3 SYSCLK4 and SYSCLK5 PLL1 power is supplied externally via the PLL1 power supply pin PLLV1 An external EMI filter circuit must be added to PLLV1 as shown in Figure 7 10 The 1 8 V supply of the EMI filter must be from the same 1 8 V power plane supplying the I O power supply pin DVppig requires EMI filter manufacturer Murata part number NFM18CC222R1C3 or NFM18CC223R1C3 All PLL external components C1 C2 and the EMI Filter must be placed as close to the C64x DSP device as possible For the
375. was done C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 9 2 DDR2 Memory Controller Peripheral Register Description s Table 7 40 DDR2 Memory Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 7800 0000 MIDR DDR2 Memory Controller Module and Revision Register 7800 0004 DMCSTAT DDR2 Memory Controller Status Register 7800 0008 SDCFG DDR2 Memory Controller SDRAM Configuration Register 7800 000C SDRFC DDR2 Memory Controller SDRAM Refresh Control Register 7800 0010 SDTIM1 DDR2 Memory Controller SDRAM Timing 1 Register 7800 0014 SDTIM2 DDR2 Memory Controller SDRAM Timing 2 Register 7800 0018 Reserved 7800 0020 BPRIO DDR2 Memory Controller Burst Priority Register 7800 0024 7800 004C Reserved 7800 0050 7800 0078 z Reserved 7800 007C 7800 00BC Reserved 7800 00 0 7800 00 0 Reserved 7800 00E4 DMCCTL DDR2 Memory Controller Control Register 7800 00E8 7800 00FC Reserved 7800 0100 7FFF FFFF Reserved 7 9 3 DDR2 Memory Controller Electrical Data Timing The mplementing DDR2 PCB Layout on the TMS320C6455 application report literature number SPRAAA7 specifies a complete DDR2 interface solution for the C6455 as well as a list of compatible DDR2 devices TI has performed the
376. width M A Register File B Register File A31 A16 B31 B16 0 Interrupt and Exception Controller Systems Primary Switched Central Resource L1D Cache 2 Way PLL1 and Device PLL1 Configuration GPIO16 Set Associative 32K Bytes Total 2 Secondary Controller Logic LO Switched Central LO Resource u Boot Configuration A McBSPs Framing Chips 100 MVIP SCSA T1 E1 97 Devices SPI Devices Codecs B The PCI peripheral pins are muxed with some of the HPI peripheral pins and the UTOPIA address pins For more detailed information see the Device Configurationsection of this document C Each of the TIMER peripherals TIMER1 and TIMERO is configurable as either two 64 bit general purpose timers or two 32 bit general purpose timers or a watchdog timer D The PLL2 controller also generates clocks for the EMAC E When accessing the internal ROM of the DSP the CPU frequency must always be less than 750 MHz Figure 1 2 Functional Block Diagram 10 Features Submit Documentation Feedback 4 6 INSTRUMENTS www ti com SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR 2 Device Overview 2 4 Device Characteristics Table 2 1 provides an overview of the C6455 DSP The tables show significant features of the C6455 device including the capacity of on chip RAM the peripherals the CPU frequency and t
377. wn in Figure 7 29 and described in Table 7 38 31 16 R 0 15 1 0 1 LEGEND R W Read Write R Read only value after reset Figure 7 29 SYSCLK Status Register Hex Address 029C 0150 Table 7 38 SYSCLK Status Register Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 SYS1ON SYSCLK1 on status 0 SYSCLK1 is gated 1 SYSCLK1 is on 158 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas SM320C6455 EP INSTRUMENTS FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 8 4 PLL2 Controller Input Clock Electrical Data Timing Table 7 39 Timing Requirements for CLKIN2 see Figure 7 30 720 850 NO A 1000 1000 UNIT 1200 MIN MAX 1 te CLKIN2 Cycle time CLKIN2 37 5 80 ns 2 tw CLKIN2H Pulse duration CLKIN2 high 0 4 ns 3 tw CLKIN2L Pulse duration CLKIN2 low 0 4 ns 4 Transition time 2 1 2 ns 5 ty CLKIN2 Period jitter peak to peak CLKIN2 100 ps 1 The reference points for the rise and fall transitions are measured at 3 3 V Vy MAX and MIN 2 C CLKIN cycle time in ns For example when CLKIN2 frequency is 25 MHz use C 40 ns 3 If EMAC is enabled with RGMII or GMII CLKIN2 cycle time must be 40
378. xed with the HPI or UTOPIA or GPIO peripherals By default these signals function as HPI or GPIO or EMAC For more details on these muxed pins see the Device Configuration section of this document Figure 2 12 PCI Peripheral Signals Submit Documentation Feedback Device Overview 29 SM320C6455 EP X3 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 2 7 Terminal Functions The terminal functions table Table 2 3 identifies the external signal names the associated pin ball numbers along with the mechanical package designator the pin type l O Z or 1 2 whether the pin has any internal pullup pulldown resistors and a functional pin description For more detailed information on device configuration peripheral selection multiplexed shared pins and pullup pulldown resistors see Section 3 Device Configuration Table 2 3 Terminal Functions SIGNAL TYPE iPD IPUO DESCRIPTION NAME NO CLOCK PLL CONFIGURATIONS 28 IPD Clock Input for PLL1 CLKIN2 G3 IPD Clock Input for PLL2 PLLV1 T29 A 1 8 V I O supply voltage for PLL1 PLLV2 A5 A 1 8 V I O supply voltage for PLL2 SYSCLK4 GP 1 AJ13 Volz IPD 21 speed 0 2 or this pin can be JTAG EMULATION TMS AJ10 IPU JTAQ test port mode select TDO AH8 O Z IPU JTAG test port data out TDI 9 IPU J
379. y n value after reset Figure 7 14 PLL Controller Divider 4 Register PLLDIV4 Hex Address 029A 0160 Table 7 22 PLL Controller Divider 4 Register PLLDIV4 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 D4EN Divider 4 enable bit 0 Divider 4 is disabled No clock output 1 Divider 4 is enabled 14 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 RATIO O 1Fh Divider ratio bits 0 2 Divide frequency by 2 th 4 Divide frequency by 4 2h 6 Divide frequency by 6 3h 8 Divide frequency by 8 4h 7h 10 to 16 Divide frequency by 10 to divide frequency by 16 8h 1Fh Reserved do not use Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 143 SM320C6455 EP 79 Texas FIXED POINT DIGITAL SIGNAL PROCESSOR INSTRUMENTS www ti com SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 7 7 3 5 PLL Controller Divider 5 Register The PLL controller divider 5 register PLLDIV5 is shown in Figure 7 15 and described in Table 7 23 31 16 Reserved R 0 15 14 5 D5EN Reserved RATIO R W 1 R 0 R W 3 LEGEND R W Read Write R Read only n value after reset Figure 7 15 PLL Controller Divider 5 Register PLLDIV5 Hex Address 029A 0164
380. y of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by T

Texas Instruments SM320C6455-EP User's Manual

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