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Texas Instruments MSP50C614 User's Manual

1. char info MAXIDENTIFIER 1 character string containing some information on the error y struct error_struct error_list MAX_ERRORS PE a i ASM MAIN source file amp w amp passl error error list include list Where Source file is the assembly source file name J wisthe number of warnings returned by the assembler J passi error is the number of errors returned in pass 1 of the assembler error list is a structure containing information about the errors detected by the assembler include lististhe list of directories to search first for include files separated by semicolons iisthe total number of errors returned by the assembler Code Development Tools 5 33 Assembler 5 7 2 Assembler Directives Assembler directives are texts which have special meaning to the assembler Some of these directives are extremely helpful during conditional compiling debugging adding additional features to existing codes multiple hardware development code release etc Other directives are an essential part of the assembler to initialize variable with values assigning symbols to memory location assigning origin of a program etc The assembler directives that start with a hash sign cannot have spaces before the directive The following assembler directives are recognized by the assembler Some of these assembler directives uses expression and symbol These are explained below expression can b
2. 0 cece eee recent o 1 4 1 4 Functional Description coa xr xe 1 5 1 5 G605and 6604 oa a lo EE 1 6 1 6 Terminal Assignments and Signal Descriptions 1 10 Features of the C614 1 1 Features of the C614 O U DU U U U U O O o D O Advanced integrated speech synthesizer for high quality sound Operates up to 8 MHz performs up to 8 MIPS Very low power operation ideal for hand held devices Low voltage operation sustainable by three batteries Reduced power stand by modes less than 10 uA in deep sleep mode Supports high quality synthesis algorithms such as MELP CELP LPC and ADPCM Contains 32K words onboard ROM 2K words reserved 640 words RAM 40 general purpose bit configurable I O 8 inputs with programmable pullup resistors and a dedicated interrupt key scan 16 dedicated output pins Direct speaker driver 32 Q PDM One bit comparator with edge detection interrupt service IMPORTANT Not currently supported Resistor trimmed oscillator or 32 kHz crystal reference oscillator Serial scan port for in circuit emulation and diagnostics The MSP50C614 is sold in die form an emulator device for the MSP50C614 is sold in a ceramic package for development 1 2 Applications Applications Due to its low cost low power needs and high programmability the C614 is suitable for a wide variety of applications incorporating I O control and high quality speech Lj Talking Toys T
3. M7 1 Note The value programmed to the PLLM register is not exactly the multiplicative factor between the 32 kHz reference and the master clock Refer to Section 2 9 3 Clock Speed Control Register for more information on the relationship between the PLLM and the resulting MC rate LLLLLLLL The column in these tables output sampling rate reports the true audio sampling rate achievable by the C614 using the 32 768 kHz CRO The values reported are not always exact multiples of the 8 kHz and 10 kHz options however they are the closest obtainable using the PLLM multiplier under the given set of constraints Peripheral Functions 3 11 Digital to Analog Converter DAC 8 kHz Nominal Synthesis Rate 32 768 kHz Oscillator Reference ClkSpdCtrl Number of Number of PLLM Master CPU Output Instructs Instructs IntGenCtrl Over Register Clock PDM Clock Sampling Between Between DAC PDMCD Sampling Value Rate Rate Rate Rate DAC 8 kHz Precision Bit Factor hex MHz MHz MHz kHz Interrupts Interrupts 8 bits 1 1x Ox OF 2 10 2 10 1 05 8 19 128 128 2x Ox 1E 4 06 4 06 2 03 15 87 128 256 4x Ox 3E 8 26 8 26 4 18 32 26 128 512 8x 0x 7C 16 38 16 38 8 19 64 00 128 1024 0 1x Ox 1E 4 06 2 03 2 03 7 94 256 256 2x Ox 3E 8 26 4 13 4 13 16 13 256 512 4x 0x 7C 16 38 8 19 8 19 32 00 256 1024 9 bits 1 1x Ox 1E 4 06 4 06 2 03 7 94 256 256 2x Ox 3E
4. Ed dma16 for direct or offset16 long relative see section 4 13 MOV A nnet nexa 1 1 1 o o neta an jojojtjojoj1 0 f a ES imm16 L nR MOV MRimmi LnexA 3 1 fo Jo nexa J an rjtysjojojrjojo x ooo mR mov An An nexta 3 o o netA An oo P i Jo a f mov An PHLnextA t s o o netA An o P 1 1 o Po fa A mov sv annaa 3 s tio o netA An 1 ols o ojo a o mov PH anidh neta t1 11 o o nexta An tho lols bo A o MOV Ad L An LnextA 1 1 1 joo netA An ooo 1o Po Ja A mov MR An pnexA t 1 sa an 1fo 1 ofoJa o MOV adrs Rx SEE dma16 for direct or offset16 long relative see section 4 13 MOV Rx ad EER EBIG Lm a A Bal mms imm16 Assembly Language Instructions 4 115 Individual Instruction Descriptions SISTR EE S EE TS TI Ii II MOV SV adis da AKATA CA CA E E dma16 for direct or offset16 ive see section 4 13 MOV PH adrs I 3 Fe s o e lol adrs Mov mem L dma16 for direct or offset16 see section 4 13 MOV MR adrs ln lalu ln 1 o ool adrs mov mem d dma16 for direct or offset16 ive see section 4 13 MOV APn adrs li 1rfof1 1 loji apn adrs MOY Aeneas p dma16 for direct or offset16 see section 4 13 MOV STAT adrs EN iot fi o 1 1 adrs pos dma16 for direct or offset16 see section 4 13 MOV TOS adrs fi Ji fofi 1 fo o 1 o adrs nesa
5. e ees 3 2 3 1 2 Dedicated Input PortF 0 00 eee ees 3 4 3 1 8 Dedicated Output Port G rpad iaa uiaei tiea ieai a ees 3 5 3 1 4 Branch on D Port is asses iz d te dace Fame R aee denm m dade 3 6 3 1 5 Internal and External Interrupts oooocccoccccccnnoncrn ees 3 6 3 2 Digital to Analog Converter DAC 000 cece eee eens 3 8 3 2 1 Pulse Density Modulation Rate 00 cece eee 3 8 3 2 2 DAC Control and Data Registers 20 c cee ees 3 8 3 2 3 PDM Clock Divider sssssssssssse III 3 10 9 9 Comparalot sek oor ee dira ro ria iaa aa 3 14 3 4 Interrupt General Control Register 0 06 c cece e eee eee ees 3 17 3 5 Hardware Initialization States 0 0 teenies 3 19 Assembly Language Instructions ss s x x x x x e e e e e x x x x eee eee 4 1 4 1 Introduction iiie dt a A A a de 4 2 4 2 System Registers bocanada den x ado ERR AERE 4 2 4 2 1 Multiplier Register MBI eI 4 2 4 2 2 Shift Value Register SV ees 4 2 4 2 8 Data Pointer Register DP 2 cece ees 4 2 4 2 4 Program Counter PC n 4 2 42 5 TOp Of Stack TOS soscesusee Ehe va A E de TREO 4 3 4 2 6 Product High Register PH 00 cece cece eee ees 4 4 4 2 7 Product Low Register BLU 4 4 4 2 8 Accumulators ACO AC31 0 ccc eee ees 4 4 4 2 9 Accumulator Pointers APO AP3 0 000 ccc eects 4 5 4 2 10 Indirect Register RO R7 arg RRR
6. eek ok Word w With RPT ck crass MOVT adrs TFn Table 4 46 Table 4 46 Execution dest src PC PC W Flags Affected None Opcode Instructions Pie 5 14 13 12 11 o o e 7 e sajoja Jo MOVE ac TE ple bis e 7 dma16 for direct or offset16 long relative see section 4 13 Description Move TFn from STAT register to memory tag All addressing modes are available See Also MOVU MOV MOVT MOVB MOVBS MOVS Example 4 14 32 1 MOVT R3 TF2 Copy the TF2 flag bit to the 17th bit of the word pointed by R3 Increment R3 by 2 Assembly Language Instructions 4 129 Individual Instruction Descriptions 4 14 37 MOVU Move Data Unsigned Syntax label name dest src mod Clock clk With RPT clk ova mr Arlt nex A wow we peor as ee Execution premodify AP if mod specified dest src PC PC L W Flags Affected src is adrs TAG bit is set accordingly UM is set to 1 Opcode francis 0500000001010 0150 T4 E TS mw pi pop po p mea a HS DE D ES T TS MOVU MR adis A dma16 for direct or offset16 long relative see section 4 13 Description Copy value of src to dest Premodification of accumulator pointers is allowed with some operand types MOVU MR Ar next A Move An to MR register in unsigned multiplier mode MOVU MR aars Move data memory word to MR reset multiplier signed mode See Also MOV MOVB MOVT MOVBS MOVS Example 4 14
7. 4 4 4 Class 4 Instructions Address Register and Memory Reference Class 4 instructions operate on the indirect register Rx that exists in the ad dress unit ADU Even though the last three registers R5 R7 are special INDEX PAGE and STACK class 4 instructions uniformly apply to all regis ters Subclass 4a provides transfers to and from memory In indirect mode any one auxiliary register can serve as the address for loading and storing the con tents of another Subclass 4b instructions provide some basic arithmetic operations between referenced auxiliary register and short 8 bit constants from program memory These instructions are included to provide efficient single cycle instructions for loop control and for software addressing routines Subclass 4c provide basic arithmetic operations between the referenced auxil iary register and 16 bit constants from program memory These instruction re quire 2 instruction cycles to execute Also a compare to R5 INDEX is provided for efficient loop control where the final loop counter value is not chosen to be zero Table 4 21 Class 4a Instruction Encoding pa se ae e 3 Dore e e e por ses pos preste peser pue em er M meet fof e jeperpepererer a le eee PPP OESTE E E Pb Pt tele t ble 4 34 Instruction Classification Table 4 22 Class 4a Instruction Description me menie Dei 00 MOV aars Rx Store Rx register to data memory referred by addressing mode a
8. Low 1 1 1 1 o om 1 1 Class 9c Class 9d ENDLOOP Wen of this bit depends on E class 3 instruction is aka 4 4 1 Class 1 Instructions Memory and Accumulator Reference This class of instructions controls execution between data memory and the accumulator block In addition to the explicit opcode field that specifies an arithmetic operation an eight bit data memory addressing mode reference field am Rx pmi e adrs field controls the addressing of one input operand and a 4 bit field An and next A in class 1a or 2 bit field An in class 1b selects an accumulator location as the other input operand The results are written to the addressed accumulator location or to the offset accumulator in class 1a if A bit 1 In addition each instruction can be treated as a single word length operation or as a string depending on the string control encoded in the op code s 1 in class 1b and An 11 binary in class 1a Assembly Language Instructions 4 25 Instruction Classification Class 1a provides the four basic instructions of load store add and subtract between accumulator and data memory Either the accumulator or the offset accumulator A bit dependent can be stored in memory with the MOV instruction The MOV instruction can load the accumulator or its offset depending on the A bit The ADD or SUB instructions add or subtract memory from an accumulator register and save the results in the accumulator reg
9. INT trigger event IF INT6 Flag is CLEAR AND INT Flag is SET OR TIMER1 Enable is SET THEN TIMER 1 starts counting With regards to the transition events the rising edge in the comparator is a trigger for INT6 This happens independently of any activity associated with TIMER1 TIMER1 on the other hand comes to a stop anytime the following conditional is true IF INT6 Flag is SET OR INT7 Flag is CLEAR AND TIMER1 Enable is CLEAR THEN TIMER stops counting INT6 flag refers to bit 6 within the interrupt flag register IFR peripheral port 0x39 This bit is automatically SET anytime that an INT6 event occurs The Comparator bit is automatically CLEARed again if an INT6 event occurs at the same time thatthe associated mask bit is SET IntGenCtrl address 0x38 bit 6 The latter indicates thatthe program vectoring associated with INT6 is enabled The flag bit is SET when the INT event occurs Only if the mask bit is set does the interrupt service occur vectoring takes place and the flag bit is once again cleared Refer to Section 2 7 Interrupt Logic for more details The INT6 Flag may also be SET or CLEARed deliberately at any time in software Use the OUT instruction with the associated l O port address IFR address 0x39 INT7 flag refers to bit 7 within the interrupt flag register This bitis automatically SET anytime that an INT7 event occurs The bit is automatically CLEARed again if an INT7 event o
10. Interrupt ae 7FF3h PortD2 Risingedge 4th Port D2 goes high titled Comparator for details Note Interrupts may be lost if interrupts occur during power up or wake up from deep sleep mode The interrupts are generated as a divided signal from the master clock The frequency of the several timer interrupts will therefore vary depending upon the operating master clock frequency a MSP50C604 Preliminary Data B 7 Packaging B 4 Packaging The MSP50C604 is sold in die form A 64 pin plastic package is also available Table B 1 MSP50C604 64 Pin PJM Plastic Package Pinout Description Description Pin Description Pin Description Pin Description Pin NC 17 PC6 33 VCC 1 GND 49 VCC3 2 NG 50 PD3 3 NC 51 PD2 4 NC 52 PD1 5 NC 53 PDO 6 NC 54 TEST 7 NC 55 SCAN OUT 8 NC 56 SYNC 9 NC 57 SCAN CLK 10 NC 58 SCAN IN 11 NC 59 RESET 12 NC 60 X2 13 NC 61 X1 14 NC 62 PLL 15 NC 63 GND 16 GND 64 Packaging Figure B 3 MSP50C604 Slave Mode Signals 4 Host write sequence Host read sequence ub SS INRDY OUTRDY 1 BER R WZ STROBE PCg PC New Data valid Data Data latched to Port A Figure B 4 MSP50C604 64 Pin PJM Package 48 33 MSP50C604 Preliminary Data B 9 Packaging Appendix C MSP50C605 Data Sheet This appendix contains the data sheet for the MSP50C605 mixed signal pro cessor
11. e eese 5 30 5 6 8 Known Differences Incompatibilities Restrictions 5 32 bi JASSeImblet 322 eec ela aed Gy eset ceca vla vd Neg 5 33 b 4 Assembler DWE voca rr RIPE TE E REDP EE ER EUER PE 5 33 5 7 2 Assembler Directives rra 5 34 5 8 BI T ii A A a one 5 38 5 9 C Compiler iio iii a A dd A td vac 5 39 D9 FOO WOl ico siii a 5 40 5 9 2 Varable Types osuere donee yeaa ba 5 41 5 9 3 External References o oocccccccococccncc n 5 41 5 9 4 C Directives 0 cece tenet eens 5 42 b 9 5 IMCS 1 nota a dla 5 44 5 9 6 Function Prototypes and Declarations cece eee eee eee 5 45 5 9 7 lnitializations ice cien e WANE ea Ade EET Bec 5 45 99 0 RAMIUSage anta Aa 5 45 5 9 9 Variable Types X 9 5 soos R X 9 ieran ir E RA A 5 45 Contents ix Contents 5 9 10 String FUNC ONS cesis sehr e a ee A 5 45 5 9 11 Constant Functions 000 cece n 5 47 5 10 Implementation Details gg gr RN a 0 0 N 0 K N N 0 R NR ee A 5 48 5 10 1 Comparisons 2 62 00 R 9 ine T deme DRE baa a dd ed dece 5 48 5 10 2 DIVISION isse pere ex c esee c mds aud RA OR RE PURA RR RUNS 5 50 5 10 3 Eunction Calls iet A utt Ee RP 5 50 5 10 4 Programming Example 0 000 cece eect a eee eee 5 51 5 10 5 Programming Example C With Assembly Routines 5 53 5 11 Beware of Stack Corruption 0 0 0 ccc nee eees 5 67 5 12 Reported Bugs With Code Development Too
12. euonoeurpiq eed v uod 81X0 YXO Assembly Language Instructions OLXxO 90X0 80X0 vOXO 00X0 ssoippy 4 204 Instruction Set Summay 0000X0 0000X0 ZH 9ES S9 x L enje TI 49019 ndo ZH Z0 LEL X L 9NJ2A TI OW Sud INTI oo REDUCE oo o joj rij uyj s3 aj Bey 1dnuejur epe Busu zad sy WI 1015 1594 Bey 1dnuejur z OWL Bei 1dnuejui abpa Sulje dd Dey 1dnuejur OWL Bey 1dn419 u1 aBpa uisu pad Bey 1dnuejur jeu OVG pabueyoun yal jqeu ejgesip 0 ejqeue grau ajqeue ieu idnuejui epe Hulle Sad 1dnuejui epe Busu Yad 1dnuejur e8pe Pulje uod 4 1dnujejur epe Hulle ead 1dnuejui epe uisu zad 1dnuejur Z Jeuut 1dnuuejul 13W 99Jnos zJeuil 1dnuejur JowlL OVG 90JNOS paw OW L ON K ejgesip o e qeue sq ejgeue 1dnueiu uonoun J aw Bey 1dnuejur epe Bule sad ON MY A9019 INO d elqeua 9jgesip o Jojeyeduio5 jq wuy dn Hina uod 4 0000 0 aT aT ST o Tro ws T Tos 7 9 sua OL 0 Sid 6 L L ovd eiqeu3 L 11q 8 0 0 ovd e1qesid 0 Ova eis xg Ova elis xe L 0 si ova Y ta vms a eromema wa oo rafia 3 mo aa a ove ai uondioseg uod OI pL 9d0SdSW HLIDOSASIN Jo3u05 Jeisibou pejy 1dnueiju ouo IZENEI 1dnueiu 9L ouo OVG T 4 205 Assembly Language Instructions 90c v suononujsu ebenbue7 Ajquassy ICAA Source TT Fredy commen Ln poses twers IE IN LLL wr pose
13. 4 42 Instruction Classification Table 4 35 Class 9a Instruction Encoding Ee IER p E MECA ADE ES CO S ON ECON RE KC EO ECR S901919 GHL Table 4 36 Class 9a Instruction Description Ge uenis nei FIRK An Rx Finite impulse response tap execution When used with repeat counter will execute a 16 bit x16 bit multiplication between an indirect addressed data memory buffer and program memory coefficients 32 bit accumulation Circular buffering Each tap executes in 2 cycles Rx automatically increments by 2 per tap 1 FIR An Rx Finite impulse response tap execution When used with the repeat counter it will execute a 16 bit x16 bit multiplication between two indirect addressed data memory buffers into a 32 bit accumulator Circular buffer operation Executes in 2 instruction cycles Rx and R x 1 automatically increments by 2 per tap 1 CORK An Rx Correlation function When used with repeat will execute 16x16 multiplication between data memory and program memory 48 bit accumulation and a circular buffer operation Each tap takes 3 instruction cycles Rx automatically increments by 2 per tap 1 1 COR An Rx Correlation function When used with repeat will execute 16x16 multiplication between two indirectly addressed data memory buffers 48 bit accumulation anda circular buffer operation Each tap takes 3 instruction cycles Rx and R x 1 automatically increments by 2 per tap EA 4 37 Class 9b Instruction Descrip
14. Example 4 3 25 AND TF1 0x20 AND the test flag 1 bit TF1 in status register with the 17th bit of the data memory location 0x20 and store the result in the TF1 bit of the STAT Example 4 3 26 OR TF2 R6 0x02 OR the test flag 2 bit TF2 in status register with the 17th bit of the data memory location R6 0x02 and store the result in the TF2 bit in of the status register So if R6 0x0100 then relative flag address is 0x0102 Example 4 3 27 XOR TF1 R6 0x20 XOR the test flag 1 bit TF1 in status register with the 17th bit of the data memory location R6 0x20 and store the result in TF1 bit of the status register So if R6 0x0100 then relative flag address is 0x0120 Assembly Language Instructions 4 19 Instruction Syntax and Addressing Modes 4 3 8 Tag Flag Bits 4 20 The words TAG and flag may be used interchangeably in this manual The TAG bit is the 17th bit of a word of data memory There are 640 words of RAM each 17 bits wide on the C614 Therefore there are 640 TAG bits onthe C614 When an instruction of the format MOV accumulator RAM is performed the STAT register is affected by various properties of this trans fer The TAG bit of the RAM location is copied into the TAG bit of the STAT reg ister during such transfers The TAG bit can be modified using several instructions STAG RTAG SFLAG RFLAG There are subtle differences between these instructions that the user must understand before using them
15. Memory tag Holds the 17th bit whenever a memory value is read Assembly Language Instructions 4 7 Instruction Syntax and Addressing Modes 4 3 Instruction Syntax and Addressing Modes MSP50P614 MSP50C614 instructions can perform multiple operations per instruction Many instructions may have multiple source arguments They can premodify register values and can have only one destination The addressing mode is part of the source and destination arguments In the following subsec tion a detail of the MSP50P614 MSP50C614 instruction syntax is explained followed by the subsection which describes addressing modes 4 3 1 MSP50P614 MSP50C614 Instruction Syntax All MSP50P614 MSP50C614 instructions with multiple arguments have the following syntax name dest src src1 mod where the symbols are described as follows name dest src Src mod name of the instruction Instruction names are shown in bold letters If the instruction name is followed by a B the arguments are all byte types If name is followed by an S all arguments are word string strings of words types If name is followed by BS all arguments are byte string types destination of data to be stored after the execution of an instruction Op tional or not used for some instructions Destination is also used as both a Source and a destination for some instructions If a destination is specified it must always be the first argument Destinations can
16. UNLIST The lines following this directive are NOT included in the listing file extension Ist created by the assembler The MSP50P614 MSP50C614 linker is implemented as a Windows dynamic linked library DLL The current name of the DLL file is 1ink6xx d11 ltcan be invoked from any Windows program provided that the user included the file called 1ink6xx lib in the Windows project C Compiler The syntax of the call is extern int FAR PASCAL LINK_MAIN LPSTR source_file LPSTR exe file ierr LINK MAIN source file exe file Where source file is the project file name which contains the names of the files to be linked exe fileis the name of the linked executable file ierristhe total number of errors returned by the linker If errors occur during link the error information is placed in a file with extension rer With the same name as the executable file 5 9 C Compiler The syntax of the call is The MSP50P614 MSP50C614 C compiler is implemented as a Windows dynamic linked library DLL The current name of the DLL file is cmm6xx d11 It can be invoked from any Windows program provided that the user included the file called cmm6xx 1ib in the Windows project extern int FAR PASCAL CMM MAIN LPSTR source file short warn struct cmm input struct error struct 75 nm define MAX LEN 256 LPSTR source file short w i struct error struct short pass short type short error m
17. next A Multiply MR register by accumulator A 1 or offset MULTPLS An An A720 transfer lower 16 bits of product to accumulator 7 A20 or offset accumulator A 1 Latch upper 16 bits of Product to PH register ALU status is modified SHLSPL Ar An next A Barrel shift the accumulator A 1 or offset accumulator SHLSPLS An An A720 value n bits left SV reg Store the upper 16 bits to PH Subtract the lower 16 bits of value from offset A 1 or accumulator A 0 and store in accumulator A 0 or offset accumulator A 1 ALU status is modified SHLAPL An An next A Barrel shift the accumulator A 1 or offset accumulator SHLAPLS An An A 0 value n bits left SV reg Store the upper 16 bits to PH Add the lower 16 bits of value to offset accumulator A721 or accumulator A 0 and store in accumulator A 0 or offset accumulator A 1 ALU status is modified Assembly Language Instructions 4 33 Instruction Classification Table 4 20 Class 3 Instruction Description Continued Temen pe n O MUL An next A Multiply MR register by accumulator A 1 or offset MULS An accumulator A 0 and latch the rounded upper 16 bits of the resulting product into the PH register SHL An next A Barrel shift the accumulator A 1 or offset accumulator SHLS An A720 value n bits left n stored in SV register Store the upper 16 bits of the 32 bit shift result to PH
18. on antx U HU HH U HH CHH U DH me Jifri Description When used with repeat will execute 16 16 multiplication between data memory and program memory 48 bit accumulation and a circular buffer operation Each tap takes 3 instruction cycles Selected register Rx must be even This instruction also uses R x 1 This instruction must be used with RPT instruction See section 4 11 for more detail on the setup of coefficents and sample data During CORK execution interrupt is queued See Also RPT COR FIR FIRK Example 4 14 13 1 RPT 0 CORK AO RO Computes the calculation for 2 tap correlation filter with 48 bit accumulation See section 4 11 for more detail on the setup of coefficents and sample data Assembly Language Instructions 4 95 Individual Instruction Descriptions 4 14 15 ENDLOOP End Loop Syntax Ea AE LA NES Execution If R4 2 0 decrement R4 by n 1 or 2 PC e first address after BEGLOOP else NOP PC PC 1 Flags Affected None Opcode ULL AEN EET ES ER EGRE ES EGER ET E ES ER ER E38 wona o ep pog pergens o pope po psp oy Description This instruction marks the end of a loop defined by BEGLOOP If register R4 is not negative R4 is decremented by n and the loop is executed again beginning with the first instruction after the BEGLOOP If R4 is negative a NOP instruction is executed and program exits the loop Interrupts queued by BEGLOOP are processed according to their priority This instruction r
19. An adrs accumulator An and store the results in the same accumulator An if A 0 or offset accumulator An A 1 ALU status is modified MOV Anr adrs next A Load accumulator An A 0 or offset accumulator An A 1 from data MOVS An adrs memory location referred to adrs ALU status is modified MOV aars An next A Store accumulator A 0 or offset accumulator A 1 to data memory MOVS aars An location referred to by addressing mode adrs Transfer status is modified 4 26 Instruction Classification Table 4 15 Class 1b Instruction Description m eme emm OR An adrs ORS An adrs AND An adrs ANDS An adrs XOR An adrs XORS An adrs MOVB An adrs g MOVBS An aarsjg MOVB adrs g An MOVBS adrsjg An CMP An adrs CMPS An adrs MOV aars An MOVS adrs An MULTPL An aars MULTPLS An aars MOVSPH An MR aars MOVSPHS An MR adrs MOVAPH An MR adrs MOVAPHS An MR adrs Logical OR the contents of the data memory location in adrs and the selected accumulator Result s stored in accumulator s ALU status is modified Logical AND the contents of the data memory location in adrs and the accumulator Result s stored in accumulator s ALU status is modified Exclusive OR the contents of the data memory location in adrs and the accumulator Result s stored in accumulator s ALU status is modified Load the cont
20. Digital to Analog Converter DAC DAC Control register Address 0x34 4 bit wide location 03 02 01 00 Set DAC resolution to 8 bits Set DAC resolution to 9 bits Set DAC resolution to 10 bits DM Drive Mode selection 0 C3x style 1 C5x style E pulse density modulation Enable overall DAC enable 0x0 default state of register after RESET low Bit 2 in the DAC control register is used to enable disable the pulse density modulation This bit must be set in order to enable the overall functionality of the DAC After RESET is held low the default state of bit 2 is clear In this state the output at the DAC pins is guaranteed to be zero no PDM pulsing During DAC activity the PDM enable bit may also be toggled at any time to achieve the zero state In other words toggling the PDM enable bit from high to low to high brings the DAC output to the known state of zero A Note PDM Enable Bit By default the PDM enable bit is cleared DAC function is off Data values are output to the DAC by writing to the DAC data register address 0x30 The highest priority interrupt INTO is generated at the sampling rate governed by the ClkSpdCtrl and the DAC control register The program in software is responsible for writing a correctly scaled DAC value to the DAC data register in response to each INTO interrupt The register at 0x30
21. MSP50C614 is also available in 100 pin plastic QFP package The pinout is shown in Figure 1 4 and Table 1 2 Table 1 2 MSP50C614 100 Pin PJM Plastic Package Pinout Description NIN o c o llO Co co CO CO CO Oo STN N oy RR o o oy AJON oO oo Pin 6 ae NN ESA MECA E MECHA 18 17 18 19 ao at 22 29 ME 25 Yan m copo mni PGg 00 Introduction to the MSP50C614 1 11 Terminal Assignments and Signal Descriptions Figure 1 4 MSP50C614 100 Pin PJM PLastic Package Pinout Preliminary Information PJM PACKAGE TOP VIEW GND3 DA Y 1 NC NC Y 2 NC NC 13 NC NC Y 4 NC DACM D 5 PBO Vcc3 DA Y 6 PB1 DACP 17 PB2 Vcc U 9 PB3 PF7 09 PB4 PF6 PB5 PF5 PB6 PF4 PB7 PF3 Veci PF2 GND1 PF1 PAO PFO PA1 NC PA2 PG15 PA3 PG14 PA4 PG13 PA5 PG12 PAG PG11 PA7 PG10 PLL PG9 x1 PG8 X2 GND4 NC Verd NC NC NC NC GND PC PEO 10 t CO QI O L I OO Y Z IL I Q0 10 x 00 QN fhoeoseeousozmoooooon 2 az SE S 3 Nd op Terminal Assignments and Signal Descriptions For software development and prototyping a wndowed ceramic 120 pin grid array packaged P614 is available The P614 s PGA package is shown in Figure 1 5 and Table 1 3 Figure 1 5 120 Pin Grid Array Package for the Development Device P614 MSP50P614 0000000000000 0000000000000 0000000000000 OOO 000 OOO OOO OOO GO O O 000 OOO ooo extra pin o
22. The first instruction performs a multiply accumulate with MR and AO and stores PL in AO The second instruction adds PH to the second word of memory string AO and puts the result in accumulator string AO The MULAPL ADDS sequence is a special sequence If A0 is ACO 0xFFFF and MR OxFF after execution ACO 0xFF01 AC1 0x00FE If you replace ADDS AO AO PH with ADDS A1 A1 PH and A1 points to a different accumulator the result is still the same This is because the state generated by MULAPL and other similar instructions described above is used by ADDS instruction If another ADDS AQ AO PH instruction follows the previous one AC2 0x00FE since the ADDS instruction auto increments an internal register not APn The same reason applies for SUBS An An PH instruction IMPORTANT Interrupts may occur between these sequences and the result can be incorrect if the in terrupt service changes the state of the processor To prevent interrupts from happening use the INTD instruction before the execution of the sequence and an INTE afterwards Lookup Instructions 4 9 Lookup Instructions Table lookup instructions transfer data from program memory ROM to data memory or accumulators These instructions are useful for reading permanent ROM data into the user program for manipulation For example lookup tables can store initial filter coefficients characters for an LCD display which can be read for display in the LCD screen etc There a
23. The lookup address is post incremented in the DP register ALU status is modified based on the lookup value ZAC An next A Zero accumulator A 0 or 1 ALU status is modified ZACS An SUB Ar An An next A Subtract offset accumulator from accumulator A 0 or SUB An An An next A subtract accumulator from offset accumulator A 1 SUBS An gt An An Store the result in accumulator A 0 or 1 ALU status is SUBS An An An modified 1 1 ADD An An An next A Add accumulator to offset accumulator and store result to ADDS An An An accumulator A 0 or 1 ALU status is modified 111 SHLAC An An next A Shift accumulator left 1 bit and store the result into SHLACS An An accumulator A 0 or offset accumulator A 1 The LSB is set to zero and the MSB is stored in a carryout status bit ALU status is modified 1 1 1 MOV An An next A Copy accumulator A 0 or 1 to accumulator A 0 or 1 MOVS An An ALU status is modified t These instructions have a special 1 word string operations when string mode is selected The instructions ignore the string count executing only once but maintain the carry and comparison to zero operation of the previous arithmetic operation as if the sequence of the previous string instruction and this instruction execution was a part of a larger string operation Assembly Language Instructions 4 81 Instruction Classification T
24. Therefore to access accumulators use AO A1 A2 and A3 This should not be confused with APn where AP is an accumulator pointer not an accumulator An Indicates the offset of the accumulator pointed to by accumulator pointer An This is also an ac cumulator not an accumulator pointer Apn Accumulator pointer APn where n 0 1 2 or 3 The difference between An and APn is that Anis the accumulator pointed to by APn In both cases n ranges from 0 to 3 cc Condition code bits used with conditional branch calls and test flag bit instructions clk Clock cycles to execute the instruction dmaln n bit data memory address For example dma8 means 8 bit location data memory address If n is not specified defaults to dma16 flagadrs Flag addressing bits as shown in Table 4 7 flg Test flag bit g r Global relative flag bit for flag addressing imm n n bit immediate value kO kn Constant field bits 4 22 Instruction Classification Table 4 11 Symbols and Explanation Continued Symbol Explanation next A Accumulator control bits as described in Table 4 6 next A The preincrement A or predecrement A operation on accumulator pointers An or An Not NOT condition on conditional jumps conditional calls or test flag instructions Value in the repeat counter loaded by repeat instruction Value in string register STR offset n n bit offset from a reference register pma n n bit program memory add
25. and the STACK register R7 The DMAU generates a RAM address as output The DMAU functions completely in parallel with the computational unit which helps the C614 maintain a high computational throughput MSP50C614 Architecture 2 11 Data Memory Address Unit Figure 2 6 Data Memory Address Unit Arithmetic Block RAM Address R7 STACK Register Addressing Mode Internal Databus Internal Program Bus 2 3 1 RAM Configuration The data memory block RAM is physically organized into 17 bit parallel words Within each word the extra bit bit 16 is used as a flag bit or tag for op codes in the instruction set Specifically the flag bit directs complex branch conditions associated with certain instructions The flag bit is also used by the computational unit for signed or unsigned arithmetic operations see Section 2 2 1 Multiplier The size of the C614 RAM block is 640 17 bitlocations Each address provided by the DMAU causes 17 bits of data to be addressed These 17 bits are operated on in different ways depending on the instructions being executed For most instructions the data is interpreted as 16 bit word format This means that bits O through 15 are used and bit 16 is either ignored or designated as a flag or status bit Data Memory Address Unit There are two byte instructions for example MOVB which cause the proces sor to read or write data in a byte 8 bit format The B appearing at the end o
26. 12 HD ro o Js v e fs a EH 52 1 fo SHLSPLS An adis eppbpiebbieil as x dma16 for direct or offset16 long relative see section 4 13 SHLSPLS Ant An s foto f 1 an Je s r ojo o A A EUNTEM Shift accumulator string or data memory string pointed by ads to left nsy bits as specified by the SV register This result is zero filled on the right and either zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the PH register The lower 16 bits of the result PL are subtracted from the destination accumulator or its offset This instruction propagates the shifted bit to the next accumulator See Also SHLSPL SHLTPL SHLTPLS SHLAPL SHLAPLS Example 4 14 72 1 SHLSPLS A0 R4 R5 Shift the string pointed by the byte address stored in R4 by ngy bits to the left subtract the shifted value PL from the value in the accumulator string in AO and store the result in accumulator string AO Add R5 to R4 and store result in R4 After execution of the instruction PH is copied to the next to the last accumulator of the string Example 4 14 72 2 SHLSPLS A2 R1 Shift the string pointed by the byte address stored in R1 by nsy bits to the left subtract the shifted value PL from the value in the accumulator string in A2 and store the result in accumulator string A2 Increment R1 by 2 After execution of the instru
27. 4 14 4 AND Bitwise AND Syntax label name dest src src1 mod Clock clk With RPT clk tL AND An aars Table 4 46 Table 4 46 Ao aer A mio nes mo etie Abre mes 8 D S LR pmo meer es Execution premodify AP if mod specified dest dest AND src for two operands dest src AND src for three operands PC amp PC w Flags Affected destis An OF SF ZF CF are set accordingly destis TFn TFn bits in STAT register are set accordingly src is adrs TAG bit is set accordingly src is flagadrs TAG bit is set accordingly Opcode nee 00000000000 00000101 eo oe n dma16 for direct or offset16 long relative see section 4 13 e rada Pies A DO A 00 00003 mome GD HH epe ee 399 moraa GD eee e I Is Description AND dest src arc mod Bitwise AND src and src and store result in dest Premodification of accumulator pointers are allowed with some operand types AND dest src Bitwise AND dest and src and store result in dest AND TFn flagaars AND TF bit with 17th bit of data memory address referred by addressing mode flagadrs store result in TFn bit in STAT register n is either 1 or 2 AND TFn cc Rx AND test condition cc with TFn bit in STAT register Rx must be provided if cc is one of RZP RNZP RLZP RNLZP to check if the selected Rxis zero or negative Rx should not be provided for other conditionals n is 1 or 2 4 80 Individual Instructi
28. 5 reserved Reserved for future use 6 XZF Transfer equal to zero status bit 7 XSF Transfer sign status bit 8 RCF Auxiliary register carry out status bit 9 RZF Auxiliary register equal to zero status bit 10 Same state as Accumulator overflow status bit 11 before RESET Accumulator sign status bit extended 17th bit 12 Accumulator equal to zero status bit 16 bits 13 Accumulator carry out status bit 16th ALU bit 14 Test flag 1 15 TF2 Test flag 2 16 TAG Memory tag Peripheral Functions 3 21 3 22 Chapter 4 Assembly Language Instructions This chapter describes in detail about MSP50P614 MSP50C614 assembly language Instruction classes addressing modes instruction encoding and explanation of each instruction is described Topic Page il nic UHM coonaopoonecosacoscoonanaconacocoonacanacponanaase 4 2 4 2 System Registers a 4 2 4 3 Instruction Syntax and Addressing Modes 4 8 4 4 Instruction Classification eee 4 22 4 5 Bit Byte Word and String Addressing 4 44 4 6 MSP50P614 MSP50C614 Computational Modes 4 49 4 7 Hardware Loop Instructions e x x x x eee 4 53 A Cam Sming INSthUCTIONS eere e II 4 55 GRI RSS AHG TU CON e 4 57 410 Input OUtputinstructiOns E TTT 4 59 4 11 Special Filter Instr ctions ri 4 59 4 12 Conditionals 7 0 es 4 69 ale Icrnmelaoonooocuncnoocagaocunnooonacoconanandondgonunondonn
29. 512 1024 512 1024 1024 3 13 Comparator 3 3 Comparator The C614 provides a simple comparator that is enabled by a control register option The inputs of the comparator are shared with pins PD4 and PDs PDs is the noninverting input to the comparator and PD is the inverting input When the comparator is enabled the conditional operation COND2 normally associated with PD4 becomes associated with the comparator result In addi tion the interrupts associated with PD4 and PDs namely INT6 and INT7 be come interrupts based on a transition in the comparator result Finally the start stop function of TIMER1 may be controlled indirectly by a comparator transition When enabled therefore the comparator controls the following four events 1 Steady State Comparator TRUE Vpps5 gt Vpp4 COND TRUE CIN2 has its conditional call taken JIN2 has its conditional jump taken CNIN2 has its conditional call ignored JNIN2 has its conditional jump ignored 2 Steady State Comparator FALSE Vpps5 lt Vpp4 COND2 FALSE CIN2 has its conditional call ignored JIN2 has its conditional jump ignored CNIN2 has its conditional call taken JNIN2 has its conditional jump taken 3 Comparator transition FALSE to TRUE Vpps rises above Vpp4 INT6 trigger event IF INT6 Flag is SET OR INT7 Flag is CLEAR AND TIMER1 Enable is CLEAR THEN TIMER stops counting 4 Comparator transition TRUE to FALSE Vpps falls below Vpp4
30. After multiplication the byte address is 0x0008 This instruction will load the value 0x1122 to the accumulator 4 46 Figure 4 4 Data Memory Example Absolute Word Memory Location 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 Data Memory Location even 2 Bit Byte Word and String Addressing Data Memory Absolute word memory location MS Byte LS Byte Location odd 0x0000 0x12 0x34 0x0001 0x0002 0x56 0x78 0x0003 0x0004 0x9a Oxbc 0x0005 0x0006 Oxde OxfO 0x0007 0x0008 0x11 0x22 0x0009 0x000a 0x33 0x44 0x000b Example 4 5 4 MOV STR 4 2 MOV APO 2 MOVBS AO 0x0003 Refer to Figure 4 4 for this example The byte string length is 4 It is loaded to the string register STR in the first instruction APO is 2 and it points to AC2 Third instruction loads the value of the string at byte address 0x0003 and subsequently stores its contents into four consecutive accumulators starting from AC2 The result is AC2 0x0078 AC3 0x009A ACA 0x00BC AC5 Ox00DE Example 4 5 5 MOV STR MOV APO MOVS AO Refer to Figure 4 4 for this example 4 2 2 0x0003 The byte string length is 4 APO is loaded with 2 and points to AC2 The third instruction loads the value of the string at address 0x0002 LSB bit is assumed 0 and stored into four consecutive accumulators starting from AC2 The result is AC2 0x5678 AC3 Ox9ABC ACA OxDEFO AC5 0x1122 Same result can be obtained by replacing the third inst
31. All port F Any falling edge eth Any F port pin goes from all high to low PD4 Rising edge 7th Port D4 goes high PDs Falling edge Lowest Port Ds goes low T INT6 and INT7 may be associated instead with the Comparator function if the Comparator Enable bit has been set qq q ooo ooo co oS 2 SS SS SS AAA ASS Note Interrupts in Reduced Power Mode An interrupt may be lost if its event occurs during power up or wake up from areduced power mode Also note that interrupts are generated as a divided signal from the master clock The frequency of the various timer interrupts will therefore vary depending upon the operating master clock frequency a no KK Peripheral Functions 3 7 Digital to Analog Converter DAC 3 2 Digital to Analog Converter DAC 3 2 1 The C614 incorporates a two pin pulse density modulated DAC which is capable of driving a 32 Q loudspeaker directly To drive loud speakers other than 32 Q an external impedance matching circuit is required Pulse Density Modulation Rate The rate of the master clock MC determines the pulse density modulation PDM rate and this governs the output sampling rate and the achievable DAC resolution In particular the sampling rate is determined by dividing the PDM rate by the required resolution Output sampling rate PDM Rate 2 DAC resolution bits PDM Rate DAC resolution bits Set in ClkSpdCtrl register Set in DAC control register Address Ox3D Address 0x34 For examp
32. Customer Information 7 3 Mechanical Information Figure 7 1 100 Pin PJM Mechanical Information 18 85 TYP 20 20 19 80 23 45 22 95 0 16 NOM 4 Gage Plane y 0 25 MIN y Seating Plane 70 10 3 40 MAX 4040022 B 03 95 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 022 Mechanical Information The C614 is sold in die form for its volume production For software develop ment and prototyping a wndowed ceramic 120 pin grid array packaged P614 is available The P614 s PGA package is shown in Figure 7 2 Figure 7 2 120 Pin Grid Array Package for the Development Device P614 N Nlooo Oo 00 M Mlooo ooo L Llooo Oo 00 K Klooo 000 J Jlooo 000 H H lo oo O00 G Glooo ooo F Flo oo extra pin OuOXO E Elooo Oo OO D Dloooo ooo C Clooooooo ooo 3 B Blooooooo Oo 00 A Alooooooo Oo 00 1312111098 765432 1 1234567289101112 13 TOP VIEW BOTTOM VIEW p 1 Note The PGA package is only available in limited quantities for development purposes LLLLLLLL LLL T Customer Information 7 5 Mechanical Information The pin assignments for the 120 pin PGA are outlined in the following table Refer to Section 1
33. Data Memory Address Unit xx a r 0 a R 0 R N R RR N RRR N R RRR R RRR RR N A 2 12 C614 Memory Map not drawn to scale cr 2 16 Interrupt Initialization Sequence e ee 2 25 PEL Performance 25s heel IRE ir 2 30 Instruction Execution and Timing I 2 34 PDM Glock DIVIdOr 2o diexies 2IRSI IR 3X G8 T6 RA A IEEE N RAE TREN TS 3 10 Relationship Between Comparator Interrupt Activity and the TIMER1 Control 3 15 Top of Stack TOS Register Operation 0 cece eee es 4 3 Relative Flag Addressing 00 eee e eens 4 19 Data Memory Organization and Addressing 00 cece eect eee e eens 4 45 Data Memory Example A Ara R cece eee enn nnn 4 47 FIR Filter SUUGIUIO s o giiia noa iaiia a E a a PSY Perd bs iP essen 4 59 Setup and Execution of MSP50P614 MSP50C614 Filter Instructions N 1 Taps 4 67 Filter Instruction and Circular Buffering for N 1 Tap Filter ananasa aeaa 4 68 Valid Moves Transfer in MSP50P614 MSP50C614 Instruction Set 4 131 Level Translator Circuit 2 2 2 0 00 sadda aai arai a eee eens 5 3 Hardware Installation epp E a Demetr RAE Pneu an de 5 5 10 Pin IDC Connector x e hs 5 6 InstallShield Window 4 bk nr RR a Re Reb ad a eee 5 6 Setup WIDnQOW us aie cse dusk dete ded a e rna od RUE d o gos ERR eR nua Eo d ig 5 7 Exit Setup Dialog ws 4 ts an las reed Ner ld eR repa otis 5 8 User Information Dialog issssssssssssse RII n 5 8 Cho
34. Individual Instruction Descriptions 4 14 41 MULAPLS Multiply String and Accumulate Result Syntax labe name dest src mod Clock clk With RPT clk C maes aneas tebeo rasos Uo wurarcs ant v Execution PH PL MR src dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions Pro a5 fra fis 2 HD to o o v e fs fats 2 1 fo MULAPLS An adi eppliebbbieil as x dma16 for direct or offset16 long relative see section 4 13 wuLAPLS ani ari netaa 1o o 2 Ao Jif fofof fofa a Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the ng 3 x 16 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register added to dest string MULAPLS adrsj Multiply MR by RAM string add PL to An MULAPLS Ar An next A Multiply MR by An string add PL to An See Also MULAPL MULSPL MULSPLS MULTPL MULTPLS Example 4 14 41 1 MULAPLS A0 R3 Multiply MR with the content of data memory word string store at byte location pointed by R3 add accumulator string AO to PL and store result in accumulator AO string Increment R3 by 2 Example 4 14 41 2 MULAPLS A2 A2 A Multiply MR register to accumulator A2 add accumulator string A2 to PL and store result to accumula
35. Next the TOS is loaded with the value pointed to by R7 Finally the stack register R7 is decremented Figure 4 1 Top of Stack TOS Register Operation Program counter PC Top of stack register TOS Read before incrementing R7 store TOS value Data memory stack area Stack register R7 2 Preincrement during write 2 Postdecrement Increment R7 then guring read 2 The MSP50P614 MSP50C614 development tools use the TOS register for parameter passing The TOS register must be used with caution inside user programs If the TOS register and stack register R7 are not restored to their previous values after using the TOS register in an application the program can hang the processor or cause the program to behave in an unpredictable way Assembly Language Instructions 4 3 System Registers It is recommended to avoid using the TOS register altogether in applications and leave its operation to development tools only 4 2 6 Product High Register PH This register holds the upper 16 bits of the 32 bit result of a multiplication multiply accumulate or shift operation The lower 16 bits of the result are stored in the PL register The PH register can be loaded directly by MOV instructions Special move accumulate instructions MOVAPH MOVAPHS MOVSPH MOVSPHS also use the PH register 4 2 7 Product Low Register PL This register holds the lower 16 bits of the 32 bit result of a multipli
36. Note that the addressing of the Rx registers is byte addressing Example 4 3 11 ADD A3 A3 R6 R5 A Refer to the initial processor state in Table 4 8 before execution of this instruction Predecrement AP3 After predecrement A3 is AC28 and A3 is AC12 The contents of the data memory location stored in R6 are added to AC28 The result is stored in accumulator AC12 R6 is then incremented by R5 Final result AP3 28 AC12 AC28 R6 2 0x11A2 0x12AC Ox244E R6 R6 R5 OxSE6 Note that the Rx registers use byte addresses Assembly Language Instructions 4 15 Instruction Syntax and Addressing Modes Example 4 3 12 MOV R5 R5 A0 A Refer to the initial processor state in Table 4 8 before execution of this instruction Preincrement APO After preincrement AO is AC3 and AO is AC19 The contents of AC19 are stored in the data memory location in R5 R5 is then incremented by R5 Final result APO 3 R5 0x0004 0x0002 OxFEED Example 4 3 13 MOV A2 RO Refer to the initial processor state in Table 4 8 before execution of this instruc tion The contents of the data memory address in RO are loaded into A2 AC11 Final result AC11 2 0x0400 Note the addressing is byte addressing Thus RO 0x0454 indicates the word memory location 0x454 2 0x022A Example 4 3 14 IN R4 0x00 The contents of the I O port location 0x00 port PPA are stored in the location pointed to by R4 R4 is incremented by 2 after this operati
37. The allocation for asm ram irx begins where the allocation ended for inter ram irx More irx files can be chained on in this manner and all of the allocation is kept organized When C is added to a project it is important to make sure that the C variables are not allocated in locations already used by assembly variables This is accomplished with a dummy array bogus located in the file ram irx It is simply an integer array that is included in the C program so that it is the first variable allocated By making its size equivalent to the amount of memory used for assembly variables the C variables that the user defines are allocated in unused memory It can be set by building the project and finding the location of the last assembly variable This can then be converted from hexadecimal to decimal and divided by two because a C int is 16 bits to Code Development Tools 5 53 Implementation Details 5 54 find the correct size for bogus Bogus can be made larger for extra safety as long as enough memory is left over for the C variables and the stack If space allows it is a good idea to add a few extra words to bogus in case assembly variables are added to the project without modifying bogus It is also important not to alter the contents of registers R5 and R7 R7 is the stack pointer and R5 is a frame pointer used in C to C function calls Parameters are passed on the stack and the return value is always int
38. adrs wwmms HEEE eee e mr II moves pibe Us mr Tolo mosva Jpppbbblbiiillil MOV SV ad Cp bebbiliil X dma16 for direct or offset16 long relative see section 4 13 t Signed multiplier mode resets UM bit 1 in status register to O Assembly Language Instructions 4 189 Instruction Set Encoding Instructions MOV PH aars ERER UREE UL CER aCeee d MOV MR adrs dma16 for direct or offset16 long relative MOV APn adrs dma16 for direct or offset16 long relative MOV STAT adrs dma16 for direct or offset16 long relative MOV TOS adrs dma16 for direct or offset16 long relative MOV adrs PH dma16 for direct or offset16 long relative MOV adrs MR dma16 for direct or offset16 long relative MOV adrs STAT dma16 for direct or offset16 long relative MOV adrs STR dma16 for direct or offset16 long relative MOV adrs DP dma16 for direct or offset16 long relative MOV adrs SV dma16 for direct or offset16 long relative MOV adrs APn dma16 for direct or offset16 long relative MOV adrs TOS dma16 for direct or offset16 long relative MOV STR aars x dma16 for direct or offset16 long relative moves s o po i D epeo TS p tm 3 mov wen aaa apo rfi fo olo o o aaas Qe Tolo MOV TFn opt Rd 1 oo 1 o fg lua mov stR ima ft ft a a fits lala ln MOVB An adr
39. and a wait routine A C program which calls the assembly routines is also provided RORG 0x0 GLOBAL wait GLOBAL _asminit GLOBAL _Ooport GLOBAL _iport GLOBAL _Ccport GLOBAL IMER1_ISR DAC_ISR GLOBAL IMER2_ISR PORTD2_ISR GLOBAL PORTD4_ISR PORTD5_ISR GLOBAL PORTD3 ISR PORTF ISR GLOBAL reset DUMMY ISR EXTERNAL _main0 include ramNram irx include controlNcontrol irx include controlNio ports irx include controlNcontrol asm PR RRR RRR RRR KEK KER KR KKK KKK KKK KKK KK kc kc ke ek koc ke kk ke kk ke kk ke ek ke ke ck ke ke ke e ke ke e ek x Reset Begin at init614 in INIT ASM This sets the 614 to run at 8 MHz 10 bit DAC at 8 kHz reset HAA A k RRA kc koc kk KKK KK RK hock KK KER koc kk RRR kc ke kk ke ek kc ke kc koc KER koc ke ke kc ke ck ke kk ee KKK reset include control init asm AERERARERERREREKAR AREA RRE RARE RARA ACORN ook eee eoe _MAINASM The start of the assembly code which is called from main routine in main cmm j Wh E RAM ERR LEK SERRE A ERR AERA ER RR AERA ERA REAR Se RA oe coe e ok see nee _asminit nop pause for breath nop nop out IFR a0 clear all interrupt flags PRR RRR RRR KKK KKK KKK KK RK KEK KK KKK KKK KKK KKK KKK KEK KKK KK ERK KKK ke ke ke ke e e Main program RRB RE TRATE RIE IRON LD FE BR E RRE BER AE BR IA ERIN ROA BE I ARA IR de Be HME ege mainbegin mov r4 1000 2 pause for a secon
40. include tables coeffs dat Special Filter Instructions Figure 4 6 Setup and Execution of MSP50P614 MSP50C614 Filter Instructions N 1 Taps DP Rx 1 R1 AS BRA coeff array address RXeven RO R2 R4 R6 coeff_array address sample_buf address Circular buffer operation only R5 Accumulators Pointer Point to accumulator ACr An ACn Accumulators Circular buffer length 2N TAG 1 for 2N0 to last sample for Circular buffer operation FIRK CORK only Program memory FIRK CORK FIR COR only sample buf coeff array Coefficients h k k 0 N Data memory FIR COR H Multiplier OO y y For COR CORK For FIR FIRK t The value of y is stored in ACrand ACr 1 for FIR instruction 32 bit accumulation COR instruction uses 48 bit accumulation and includes accumulator ACr 2 Assembly Language Instructions 4 67 Special Filter Instructions Figure 4 7 Filter Instruction and Circular Buffering for N 1 Tap Filter Rxeven H if TAG 1 G 4H R5 2 N 1 16 Bits CORK FIRK only COR FIR only 17th Bit STAT 16 Bits 171 Bit X K N 1 is replaced by x k 1 sample buf coeff array is stored in program or data memory based on filter instruction program memory FIRK CORK data memory FIR COR li y Ek 0 N him x xfk m f MM NN 48 bit accumulation for CO
41. lo 1 ojo 1 1 o an CC t Flagadrs is 64 locations global or relative to R6 4 190 adrs Ee fis s fis 12 11 iol o e 7 e 8 4 a 2 0 Ll GNI see section 4 13 Eqr ojgsis ose arn as see section 4 13 X Lg eee ee as see section 4 13 X see section 4 13 X 1prfofrfofofofof f _ ____ ems see section 4 13 1pfrfof fofrfofofol _ as see section 4 13 X tte ee see section 4 13 X ajtjeji jele jolh as see section 4 13 afilofjijojijolijo as see section 4 13 X Eqolojsjojoro o o ads see section 4 13 X 1pifof fofofif an eds see section 4 13 X afilojifolijojili as see section 4 13 X Ejrfo e efo o e e as see section 4 13 imma Pimms ojo p an fofofo _ mms lo ads adrs move caga Tofio Tito Toto Tas as SS Instruction Set Encoding COI 0000000 00000100000 MOVB adrs An dma16 for direct or offset16 long relative see section 4 13 wove ania Pppp m mowwems HHDH DH HH a om i CCC 00 Lads MOVBS An aarsj adrs ESEREN REN a or offset16 long relative see section 4 13 mus BEIDIPBIDDeI dma16 for direct or offset16 long relative see section 4 13 MOVE Al adi DO mw dma16 for direct or offset16 long relative see section 4 13 O IO EC CR I e dma16 for direct or offset16 long relative see section 4 13 mee
42. mod Clock clk With RPT clk C maer an fads tebeo tanos 0 maca As Avin Execution premodify AP if mod specified PH PL MR src dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions 16 fas HI 13 12 11 to o jo 7 e S a a pa n fo MULAPL An adis opplebbiliebae l me x dma16 for direct or offset16 long relative see section 4 13 MuLAPL AL Art next 1 T Jo o nwa an tjs fo Jo Jo a a Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register added to dest Certain restriction applies to the use of this instruction when interrupts are occuring in the background See Section 4 8 for more detail MULAPL aars Multiply MR by RAM word add PL to An MULAPL Ar An next A Multiply MR by An word add PL to An See Also MULAPLS MULSPL MULSPLS MULTPL MULTPLS Example 4 14 40 1 MULAPL AO R3 Multiply MR with the content of data memory word stored at byte location pointed by R3 add PL to accumulator AO and store result in accumulator AO Increment R3 by 2 Example 4 14 40 2 MULAPL A2 A2 A Multiply MR register to accumulator A2 add PL to accumulator A2 and store result to accumulator A2 4 134
43. register is 00010X11XXXXXXXX X means don t care bold numbers are re sistor trim bits then the resistor trim value is equal to five o The default value of the ClkSpdCtrl is 0x0000 which means that neither option is enabled by default Immediately after a RESET LOW to HIGH and regardless of whether a resistor or a crystal is installed across OSCiy OSCourT the C614 does not have a reference oscillator running In the absence of a reference however the PLL still oscillates it bottoms out at a minimum frequency The master clock in turn runs at a very slow frequency less than 100 kHz in the absence of a reference oscillator Under this condition program execution is supported at a slow rate until one of the two references RTO or CRO is enabled in software Refer to Chapter 8 MSP50C614 Electrical Specifications for a more precise characterization of the master clock rate under these conditions Once a reference oscillator has been enabled the speed of the master clock MC can be set and adjusted as desired Bits 7 through 0 in the ClkSpdCtrl constitute the PLL multiplier PLLM The value written to the PLLM controls the effective scaling of the MC relative to the 131 07 kHz base frequency A 0 value in PLLM yields the minimum multiplication of 1 and a 255 value in PLLM yields the maximum multiplication of 256 The resulting MC frequency therefore is controlled as follows MC Master clock frequency kHz PLLM register
44. sampled ns 2 times The first sample is stored in the lowest order accumula tor of the string and the last sample is stored in the highest order accumulator of the string See Also IN OUT OUTS Example 4 14 22 1 INS A2 0 Input string starting from port O to accumulator string Assembly Language Instructions 4 105 Individual Instruction Descriptions 4 14 23 INTD Interrupt Disable Syntax Taba same Seek ck wars WP ok ee we a L5 l1 a Execution STATIM 0 IM is STAT bit 4 PC PC 1 Flags Affected None Opcode qae se e te re epe pe ps e De o m wee pops E ER pope psv poses per Description Disables interrupts Resets bit 4 the IM interrupt mask bit of status register STAT to 0 See Also INTE IRET Example 4 14 23 1 INTD Disable interrupts INTD must be always be immediately followed by a NOP Any maskable interrupt occurring after the INTD NOP sequence will not be serviced 4 106 Individual Instruction Descriptions 4 14 24 INTE Interrupt Enable Syntax A A AAA A Execution STAT IM 1 IM is STAT bit 4 PC e PC 1 Flags Affected None Opcode LL NR EAE EE E ERE ERE E E EP ET ERES we U HU UU HUD U HHH HHDH Description Enables interrupts Sets bit 4 the IM interrupt mask bit of status register STAT to 1 See Also INTD IRET Example 4 1 INTE Enables interrupts Any maskable interrupts occurring after this instruction is serviced Assembly
45. that the emulator tries to autodetect the scanport Code Development Tools 5 29 Software Emulator Figure 5 30 Windows Menu Options E MSP50C xx Code Development Tool EMU SHL RPJ stopped Pale E3 File Options Project Debug Wit Help GUI zh Ir 43 Cascade Tile Horizontal 0010 0010 001 Tile Vertical 0000 0000 0000 OOC OOFF OOFF OOF Save Default Setup OO F OO7F OO 7F 00 Load Default Setup OOOF OOOF DOC OOFF OOFF oorr oor RAM Winiow Word Address Byte Address 0000 0010 o o rx LE W Gr UL LJ Lj o t UU CO UU O CO CO UU o o o 1030 0000 0000 0000 coc GPUWindow 0000 00D8 FFFF FFF program Window Watch Window Project Window 1 0 Ports Window Stop Internal or Emulation _ Inspect Window 5 6 7 Emulator Online Help System The emulator has an online help which is launched when the He p menu option is left clicked with a mouse The help window Figure 5 30 is context sensitive and graphical in nature Any topic selected by pointing the mouse to the topic and clicking the left mouse button If a help is available on the topic the cursor becomes a hand cursor Some help topics launches more context sensitive help windows Learning to use the emulator is extremely fast using this graphical help system with minimal text to read 5 30 Software Emulator Figure 5 31 Context Sensitive Help System o gil help cn iy of the dr ridere FAM CPU Pra poa ated Propel pu
46. 1 3 mea Ta T Certain restriction applies to the use of this instruction when interrupts are occuring on the background See Section 4 8 for more detail Execution dest src PC PC W Flags Affected destis An OF SF ZF CF are set accordingly dest is adrs XSF XZF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions ft 15 14 13 12 11 o o Je v e sajofa Jo MOVS Ar adis o fo fofa T T ar ads dma16 for direct or offset16 long relative see section 4 13 CC amaror drec or otsera long lave see sectors MOVE adi A TSTST leia as El dma16 for direct or offset16 long relative see section 4 13 MOVE ad An o eE Pola as El dma16 for direct or offset16 long relative see section 4 13 Fusce 2 espere opa mos Peat E ope Pp pp HD9 mov swan ppp ppp par qp p p pe T T mos em ppp ppp b v qp pp In mos aw pp pp 00 p 0101000 D e OVS MR Ar FE 0 TSTS T wow ww Db I Ie o TED E To To To Do To To fala Assembly Language Instructions 4 125 Individual Instruction Descriptions Description Copy value of src string to deststring Premodification of accumulator pointers is allowed with some operand types Move An string to An string MOVS Anr PH Move product high reg to An string mode This instruction ignores the string count executing only once but maintains the CF and ZF status of the previous m
47. 100 oport B 0x00 wait 100 oport B OxFF wait 100 else If the correct inputs were given oport B 0x00 Light all LED s wait 5000 Keep lit for 5 seconds unlock the door end for return 5 66 Beware of Stack Corruption 5 11 Beware of Stack Corruption MSP50C614 MSP50P614 stack pointed by R7 register can easily get cor rupted if care is not taken Notice the following table read code SUBB R7 4 OV AO R7 ADD A0 address OV AO AO ADD AO R7 OV AO AO RET This code will work perfectly well if no interrupts happen before SUBB and MOV instruction If interrupts do happen between SUBB and MOV instruc tions the parameter in the stack is corrupted by the return address pushed by the hardware This problem may not be easily observed in the system level But once it happens it is very difficult to debug Use the following method to modify stack pointer instead OV AO R7 2 2 ADD AO address OV AO AO ADD AO R7 2 1 OV AO AO RET This method will not have the stack corruption problem since the MOV instruc tion performs the entire operation either before or after an interrupt 5 12 Reported Bugs With Code Development Tool The following are the reported bugs for code development tool version 2 14 Breakpoint Hardware breakpoint within two instruction cycles after the IDLE instruction causes the program to hang Avoid pu
48. 33 1 MOVU MR AO A Preincrement accumulator pointer APO Copy the content of accumulator AO to MR register Example 4 14 33 2 MOVU MR R3 Copy the value pointed by R3 to MR 4 130 Individual Instruction Descriptions Figure 4 8 Valid Moves Transfer in MSP50P614 MSP50C614 Instruction Set Immediate NOTE B Byte move possible S String move possible R5 can be moved to Rx An to An Assembly Language Instructions 4 131 Individual Instruction Descriptions 4 14 38 MUL Multiply Rounded Syntax as name sre mod TRR ok wora w With RPT ok Class Pf ut art ne teary H es Execution premodify AP if mod specified PH PL MR src PC PC W Flags Affected srcis An OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode jinstructions fi 5 sa is r2 fio o Ja 7 o fs ja a 2 1 mul A Le Tt Tt i oo neta an 1 fofofa po Tm ENEN E ER CHER CU MIA SRM dma16 for direct or offset16 long relative see section 4 13 Description Multiply MR and src The 16 MSBs of the 32 bit product are stored in the the PH register The contents of the accumulator are not changed The upper 16 bits of the result are rounded for MUL An but not for MUL adrs Pre modify the accumulator pointer if specified MUL Anr next A Multiply MR by An word store result in An t MUL aars Multiply MR by data memory wordt T R
49. 8 26 8 26 4 13 16 13 256 512 4x 0x 7C 16 38 16 38 8 19 32 00 256 1024 0 1x Ox 3E 8 26 4 13 4 18 8 06 512 512 2x 0x 7C 16 38 8 19 8 19 16 00 512 1024 10 bits 1 1x Ox 3E 8 26 8 26 4 13 8 06 512 512 2x 0x 7C 16 38 16 38 8 19 16 00 512 1024 0 1x 0x 7C 16 38 8 19 8 19 8 00 1024 1024 3 12 DAC Precision 8 bits 9 bits 10 bits IntGenCtrl PDMCD Bit 1 4 T Over Sampling Factor 1x 2x 4x 8x 1x 2x 4x 1x 2x 4x 1x 2x 1x 2x 1x 10 kHz Nominal Synthesis Rate 32 768 kHz Oscillator Reference ClkSpdCirl PLLM Register Value hex 0x 13 Ox 26 Ox 4D 0x 9B Ox 26 0x 4D 0x 9B Ox 26 0x 4D 0x 9B Ox 4D Ox 9B 0x 4D Ox 9B 0x 9B Master Clock Rate MHz 2 62 5 11 10 22 20 45 5 11 10 22 20 45 5 11 10 22 20 45 10 22 20 45 10 22 20 45 20 45 PDM RATE MHZ 2 62 5 11 10 22 20 45 2 56 5 11 10 22 5 11 10 22 20 45 5 11 10 22 10 22 20 45 10 22 Digital to Analog Converter DAC CPU Output Clock Sampling Rate Rate MHz kHz 1 31 10 24 2 56 19 97 5 11 39 94 10 22 79 87 2 56 9 98 5 11 19 97 10 22 39 94 2 56 9 98 5 11 19 97 10 22 39 94 5 11 9 98 10 22 19 97 5 11 9 98 10 22 19 97 10 22 9 98 Peripheral Functions Number of Instructs Between DAC Interrupts 128 128 128 128 256 256 256 256 256 256 512 512 512 512 1024 Number of Instructs Between 10 kHz Interrupts 128 256 512 1024 256 512 1024 256 512 1024
50. Addressing Modes 4 3 6 3 Long Relative 4 18 Example 4 3 20 MOV A3 R6 0x10 Refer to the initial processor state in Table 4 8 before execution of this instruc tion Load A3 AC29 with the contents of byte address R6 0x10 The value of R6 is unchanged Final result AC29 0x0112 Example 4 3 21 ADD A0 A0 R6 0x10 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Preincrement APO After preincrement AO is AC3 and AO is AC19 Add AC3tothe contents of byte address R6 0x10 and store the resultin AC19 The value in R6 is unchanged Final result AC19 AC3 R6 0x10 OXFEED 0x01FA OxFEED 0x0112 OxFFFF Long relative addressing selects one of the 8 address registers Rx as a base value and adds the value of the second word operand The base address reg ister is not modified Syntax name dest src Rx offset16 next A name Rx offset16 src next A Rx x 0 7 Memory Operand Example 4 3 22 MOV AO R1 0x0254 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Preincrement AO After preincrement AO is AC3 and AO is AC19 Load the contents of the data memory byte location R1 0x0254 into AC19 R1 re mains unchanged Final result APO 3 AC19 R1 0x0254 0x022A 0x0400 Example 4 3 23 MOV R7 0x0442 MR Refer to the initial processor state in Table 4 8 before execution of this instruc tio
51. CNIN2 pma16 label CXZ pma16 label CXNZ pmal6 label CXS pma16 label CXNS pma16 label CXG pma16 label CXNG pma16 label CRA pma16 label CRNA pma16 Execution IF cc true R7 TOS TOS PC 2 PC pma16 R7 R7 2 ELSE NOP PC PC 2 Flags Affected none Opcode pe eee evel es eee GG KHER Sos pra ENCHCRERER ER C E fete to pma16 4 86 Individual Instruction Descriptions Table 4 48 Names for cc SEE True condition Or rd condition ccname name MERERI a a S piper s ee L ON Pipinus ser oer L 2 0 BEGUN INE MEL LLLA E misser MA L A OA E E EA IN SOY RCA eee DU UMUR Mo TA re ou eit ele ne E AA GOO a eee NN IEEE ne i ANE AE EAS 000 00 1 pI lon lnl Re RNZP Conditional on value of Rx 0 Not available on Calls Not condition Rx 0 fofififofo RzP RNzP Conditional on MSB of Rx 1 Not available on Calls Notcondition MSB of Rx 0 erre E JAP ULL NNI pug peek 0 11 AA UID NENNEN A OS MOR EL A Y OIEA AE I E NE aa RO A EA OO I WIN NN 0 0 o pelea ae ue far M NI MORO O AN L O EXER ES A E EE ce eee Eu se ARA gt g OOD e As ir 00000 0 00 AAA ARE ELA LLLI NN A za IE EA IN ea S ORO U A AA E EN E EA B OS U O Reeve o Assembly Language Instructions 4 87 Individual Instruction Descriptions Description If cc condition in Table 4 48 is true PC 2 is pushed onto the stack and the second word operand is loaded into the PC If the condition is false e
52. Circuits Itis of particular importance to provide a separate decoupling capacitor forthe Vpp Vss pair which services the DAC These pins are pad numbers 21 and 19 respectively The relatively high current demands of the digital to analog circuitry make this a requirement An alternate circuit for better clock precision and better battery life includes a crystal oscillator Minimum Circuit Configuration for the C614 P614 Using Crystal Referenced Oscillator To pin 1 of Scan Port Connectort optional To pin 2 of Scan Port Connectort optional 1N914 MSP50P614 only 22 pF 100 kQ RESET 1 kat 32kHq 1 1 uF E Reset o Switch OSCouT 20 22 pF MSP50C614 MSP50P614 3300 pF 5 t The diode across Vpp and Vpp may be omitted shorted if the application does not require use of the Scan Port Interface The same applies for the 1 kO resistor which appears at the RESET pin the resistor may be shorted if not using the Scan Port However the footprintfor the resistor is strongly recommended for any C614 production board Refer to the mportant Note regarding Scan Port Bond Out appearing in Chapter 7 Applications 6 3 MSP50C614 MSP50P614 Initialization Codes In any C614 application it is important for certain components to be located as close as possible to the C614 die or package These include any of the decoupling capacitors at Vpp 0 1 uF It also includes all of the components in th
53. EE E EC a dma16 for direct or offset16 long relative see section 4 13 wwxusw O H H 00010100 000100158353 Movs PH Pa Pipi fofoji 1 an too oa jo mera perras ame mp ey Movs aq PH t t s ojo st an ot a fojo fa f a noa rr Lomo pepe uen Movs mR A t t s ojo st an fijofiji fojo fafo paa pas s par we pope pw ee MOVT acts TFn EE ws E dma16 for direct or offset16 long relative see section 4 13 mon mm Ayes MEER Ee ME wem pe dma16 for direct or REN long relative see section 4 13 as 7 BDIDIILel dma16 for direct or offset16 long relative see section 4 13 SN CC dma16 for direct or offset16 long relative see section 4 13 memes bli e dma16 for direct or offset16 long relative see section 4 13 BUDH oto An gt gt gt as dma16 for direct or offset16 long relative see section 4 13 mut anneta tt Lt Jt foto nexta an 1 1 s t o o JA 0 MOVSPHS An MR aars Assembly Language Instructions 4 191 Instruction Set Encoding Instructions fis fas fia fis liz Hn io 9 Je 7 fo s a a 2 t o MUL adrs MULR aars MULS An MULAPL An aars MULAPL Anrj An next A MULAPLS An adrs MULAPLS Ar An MULSPL An adrs MULSPL Ar An next A MULSPLS An aars MULSPLS Ar An MULTPL Ar adrs MULTPL An An next A MUL TPLS An adrs MULTPLS An Ar NEGAC An An next A N
54. G dedicated output 2 Bytes Pins PD4 and PDS may be dedicated to the comparator function if the comparator enable bit is set Refer to Section 3 3 Comparator for details Currently not supported SCANIN SCANOUT SCANCLK SYNC TEST PGMPULSE 54 50 53 52 51 l O l l l The scan port pins must be bonded out on any C614 production board Consult the Important Note regarding Scan Port Bond Out Section 7 1 1 Scan Port Bond Out OSCIN OSCOUT PLL DACp DAC RESET Vss VDD 65 66 67 22 20 55 9 19t 40 64 76 10 21T 23 41 77 l O O DAC Sound Output O O Initialization l Power Signals Scan Port Control Signals Scan port data input Scan port data output Scan port clock Scan port synchronization C614 test modes P614 programming pulse Oscillator Reference Signals Resistor crystal reference in Resistor crystal reference out Phase lock loop filter Digital to analog output 1 Digital to analog output 2 Initialization Ground Processor power T Pads Vss 19 and Vpp 21 service the DAC circuitry Their pins tend to sustain a higher current draw A dedicated decoupling capacitor across these pins is therefore required Refer to Section 6 1 Application Circuits for details 1 10 Terminal Assignments and Signal Descriptions The C614 is sold in die form for its volume production Contact you local TI sales office for mount and bond information
55. Internal This menu option halts execution of an internal program It provides an internal picture of the chip at the time the internal program execution was halted Note that due to the asynchronous nature of this halt one erroneous instruction may be executed before the chip actually stops For the MSP50P614 MSP50C614 chip it restarts the emulation mode and reads the CPU and RAM values Execution can then proceed either in emulation mode or in internal mode to the hardware breakpoint NOTE A hardware breakpoint must be set using SHIFT RIGHT mouse click to the line of interest Synchronize Project Chip This menu option compares the currently opened project object code with that in the program memory of the chip The number of location not matched is displayed 5 6 5 Initializing Chip When the Chip is RESET the hardware initializes the chip s I O registers to a know state But the data memory accumulators accumulator pointers indirect registers and other system registers are at a random state Register initializations are done by the Init menu There are five initialization options Figure 5 26 each of which is described below Figure 5 27 Init Menu Option Em MSP50C6xx Code Development Tool EMU SHL RPJ ES File Options Project nenug TY window Hein gu l E 1989 o8 Ki rans wani im I O Ports Window Init RAM Gir booo 0010 0010 ooio MmitRegisters Dib 908 0000 0000 0000 mitAccumulators Gtri A 910 DOF
56. Language Instructions 4 107 Individual Instruction Descriptions 4 14 25 IRET Return From Interrupt Syntax Taba same EEE mr HH H OTI Execution PC TOS R7 R7 2 TOS R7 Flags Affected None Opcode EL tee eset pepper pepe ape pe To mer EH HDH UHD UH RHH DR HU fs tft Jo See Also RET CALL Ccc INTE INTD Description Return from interrupt Pop top of stack to program counter Example 4 1 IRET Return from interrupt service routine If used in a called subroutine return from subroutine 4 108 Individual Instruction Descriptions 4 14 26 Jcc Conditional Jumps Syntax label name pmat6 Rmod Clock clk With RPT cik vec pmat6 Rmod If true If Not true label JZ pma16 Rmod label JNZ pma16 Rmod label JS pma16 Rmod label JNS pma16 Rmod label JC pma16 Rmod label JC pma16 Rmod label JG pma16 Rmod label JNG pma16 Rmod label JE pma16 Rmod label JNE pma16 Rmod label JA pma16 Rmod label JNA pma16 Rmod label JB pma16 Rmoa label JNB pma16 Rmod label JO pma16 Rmod label JNO pma16 Rmod label JRC pma16 Rmod label JRNC pma16 Rmod label JRE pma16 Rmod label JRNE pma16 Rmod label JL pma16 Rmod label JNL pma16 Rmod label JTF1 pma16 Rmod label JNTF1 pma16 Rmod label JTF2 pma16 Rmod label JNTF2 pma16 Rmod label JTAG pma16 Rmod label JN
57. Long relative to Rx The effective address is indirect register Rx 16 bit positive offset When string instructions are executed the operation of the addressing mode used is modified For all addressing modes except indirect with post modifica tion a temporary copy of the memory address is used to fetch the least signifi cant data word of the string Over the next n instruction cycles the temporary copy of the address is auto incremented to fetch the next n words ofthe string Since the modification of the address is temporary all Rx registers are un changed and still have reference to the least significant data word in memory String data fetches using the indirect with post modification addressing mode and writes the modified address back to the indirect register at each cycle of the string This will leave the address in the Rx register pointing to the data word whose address is one beyond the most significant word of the string All addressing modes except immediate addressing are encoded in bits 0 to 7 ofthe instruction s op code Table 4 2 through Table 4 6 show the encoding of various addressing modes Addressing mode bits except immediate and flag addressing come with an am Rx and pm field These are combined into a single field called adrs The appropriate decoding and syntax for each ad dressing mode with the adrs field is described in Table 4 4 The pmfield only applies to indirect addressing For other addressing modes i
58. Mode Syntax iaa name os ok wora w win Rer ok ass Arm NR 9d Execution STAT FM 0 PC PC 1 Flags Affected None Opcode Instructions Pro 15 fra Jia 12 1 to o e v e 8 a js 2 1 eM ER EH ER ER ER ER fo ER KB EH ERE TB EREE Description Resets fractional mode Clears bit 3 in status register STAT Disable multiplier shift mode for unsigned fractional or integer arithmetic See Also SFM Example 4 14 58 1 REM Resets the fractional mode Clears FM bit of STAT Assembly Language Instructions 4 153 Individual Instruction Descriptions 4 14 59 ROVM Reset Overflow Mode Syntax abel name Tos ok wora w wit RPT ci ass swm L3 l ws ls Execution STAT OM 0 PC PC 1 Flags Affected None Opcode Instructions Pro fis 14 fia i2 to o 8 7 e 8 a J2 1 fo Rem ER EH EHS KR EH EH Ts Fo ER ERE ERT CB ER Description Resets overflow mode in status register bit 2 the OM bit Disable ALU saturation output normal mode See Also SOVM Example 4 14 59 1 ROVM Resets the overflow mode to zero 4 154 Individual Instruction Descriptions 4 14 60 RPT Repeat Next Instruction Syntax ime TA o m je Execution IF RPT aarsjg load src to repeat counter ELSE load imm8 to repeat counter mask interrupt repeat next instruction repeat counter value 2 times PC PC w next instruction
59. Output String to Port Syntax iae ame sess Clock ok wora w With RPT ok crass lows ponsa me we l89 Execution port6 src PC PC 1 Flags Affected XSF XZF are set accordingly Opcode Instructions Pro fis 14 fia 12 to o a v e S a js J2 t Jo outs pore An Lt tt tt tots sie an poo t TA Description Output to I O port Word in the accumulator string can be output to one of 64 port addresses String operation writes several consecutive ports starting from port6 specified in the instruction See Also OUT IN INS Example 4 14 55 1 OUTS 0x04 A3 Put the content of acccumulator string A3 to I O port string address 0x04 PADIR port Note that based on string length other consecutive ports may also be written 4 150 Individual Instruction Descriptions 4 14 56 RET Return From Subroutine CALL Ccc Syntax iaa rame os wora w wit RPT oh Grass RET N R Execution PC TOS R7 R7 2 TOS R7 Flags Affected None Opcode Instructions Pro 15 1a H3 12 HD to o e v e 8 a js 2 1 o eer P fifol fif ififofofof f f f f fo Description Return from call or vectored call Pop stack to program counter continue execution Returns from subroutine calls CALL Ccc instructions and interrupts are different because of the way each process is handled In order to prevent execution pipeline problems the interrupt return IRET instruction uses two
60. Ox3F TIM2 2 6 2 Peripheral Communications Ports 2 16 Peripheral functions in the C614 are controlled using one or more of the I O address mapped communications ports Table 2 2 describes the ports The width of each mapped location shown in width of location is independent of the address spacing In other words some registers are smaller in width than the spacing between neighboring addresses The few unused bits appear to the rightof the LSB values within the DAC Data register address 0x30 refer to Section 3 2 2 DAC Control and Data Registers Memory Organization RAM and ROM When writing to any of the locations in the I O address map therefore the bit masking need only extend as far as width of location Within a 16 bit accumulator the desired bits width of location should be right justified The write operation is accomplished using the OUT instruction with the address of the I O port as an argument A read from these locations is accomplished using the IN instruction with the address of the I O port as an argument When reading from the I O port to a 16 bit accumulator the IN instruction automatically clears any extra bits in excess of width of location The desired bits in the result will be right justified within the accumulator Allowable access indicates whether the port is bidirectional read only or write only The last column of the table points to the section in this manual where the functions of each bit h
61. PDs become the comparator inputs At any time during which bit 15 is set PD4 and PDs MUST be set to INPUT I O Port D Control address 0x1C bits 4 and 5 CLEARed Failure to do so may result in a bus contention The function of pins PD4 and PDs and the behavior of events COND2 INT6 INT7 and TIMER1 are very different depending on whether the comparator has been enabled or disabled A summary of the various states appears in the following table SET bit 15 in the IntGenCtrl address 0x38 PDA functions as comparator negative input port D Control Ox1C bit 4 MUST be 0 PDs functions as comparator positive input port D Control Ox1C bit 5 MUST be 0 COND2 maps to the INTG is triggered by a rising edge at PDs INT7 is triggered by a falling edge at PD5 TIMER1 may be started by a falling edge at PDs TIMER will be stopped by a rising edge at PDs state of the comparator PDs relative to PD4 relative to PD4 assuming TIMER1 Enable is 0 Comparator DISABLED CLEAR bit 15 in the IntGenCtrl address 0x38 PDA functions as a general I O pin port D Control Ox1C bit 4 0 or 1 PDs functions as a general I O pin port D Control Ox1C bit 520 or 1 COND2 maps to the state of the I O pin PD 0 or 1 logical INT6 is triggered by INT7 is triggered by a rising edge at PD4 0 to 1 logical a falling edge at PDs 1 to 0 logical TIMER 1 is started stopped in software by setting clearing TIMER1 enable IntGenCtrl Inte
62. Purchase Order Management Contact Phone Technical Contact Phone Customer Code Version and Revision of format vv rr vv version rr revision numberic values only KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KK SECTION 2A ASSIGNMENT OF TI PRODUCTION PART NUMBER This section is to be completed by TI TI Part Number CSM614xxxy KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KK KKK KKK KKK KK KKK KK SECTION 3 AUTHORIZATION TO GENERATE MASKS PROTOTYPES AND RISK UNITS This section is to be completed by the customer and sent to TI after the following criteria have been met 1 The customer has verified that the TI generated data matches the original data I hereby certify that the TI generated verification data has been checked and found to be correct and I authorize TI to generate masks prototypes and risk units in accordance with the purchase order in Section 1 above In addition By Title Date KKK KKK KKK KKK KKK KKK KKK KK KK KKK KKK KKK KKK KEK KKK KKK KKK KKK ck ck ck KKK KKK KKK KKK KKK KKK SECTION 4 APPROVAL OF PROTOTYPES AND AUTHORIZATION TO START PRODUCTION This section is to be completed by the customer after prototype devices have been received and tested I hereby certify that the prototype devices have been received and tested and
63. R RR R aR RRR sirai e 4 5 4 2 14 String Register STR a aan RR R R R irda R TR ses 4 6 4 2 12 Status Register STAT 2 0 cece ene 4 6 4 3 Instruction Syntax and Addressing Modes eee e eee e eee eee aee 4 8 4 3 1 MSP50P614 MSP50C614 Instruction Syntax 00 cece 4 8 4 3 2 Addressing Modes 0 cece tte e N EEA 4 9 4 3 3 Immediate Addressing 0 x x x eee ete m 4 13 4 3 4 Direct Addressing occcccccccccccc e 4 14 4 3 5 Indirect Addressing 0ooooooocroonnnrn R eee 4 15 4 3 6 Relative Addressing 00 c cece teen eens 4 16 4 3 Flag Addressing siii a dogs eee pede ens 4 19 4 9 8 Tag Flag BUS 22 obe ct og erue tot da ii 4 20 4 4 Instruction Classification ses a gs rd a 00 a iiei 00 R R danii R R RRR RRR 4 22 4 4 2 Class 2 Instructions Accumulator and Constant Reference 4 28 4 4 8 Class 3 Instruction Accumulator Reference omo 4 30 4 4 4 Class 4 Instructions Address Register and Memory Reference 4 34 4 4 5 Class 5 Instructions Memory Reference eanan ra aa 4 36 4 4 6 Class 6 Instructions Port and Memory Reference 4 38 4 4 7 Class 7 Instructions Program Control 00 cece eee ee 4 39 Contents 4 48 Class 8 Instructions Logic and BL 0 cece eee 4 41 4 4 9 Class 9 Instructions Miscellaneous 0c cece eee eee 4 42 4 5 Bit Byte Word and String Addressing 0c cece eect eee eee ee 4 44 4 6
64. RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used TTS publication of information regarding any third party s products or services does not constitute TTS approval warranty or endorsement thereof Copyright O 2000 Texas Instruments Incorporated Preface Read This First About This Manual This user s guide gives information for the MSP50C61 mixed signal proces sor This information includes a functional overview a detailed architectural description device peripheral functional description assembly language instruction listing code development tools applications customer informa tion and electrical characteristics in data sheet This document also contains information for the MSP50C604 and MSP50C605 which are in the Product Preview stage of development How to Use This Manual This document contains the following chapters Chapter 1 Introduction to the MSP50C614 Chapter 2 MSP50C614 Architectur
65. SF 1 N N wo eemper o ES DN ET ws CE we EI CN CTI RNC H Pua Tana R NC E E 5 E Ere NM a RS INIM Z S C A G E R R R C NC A NA D EN EA EA EN G ERES CI odani odada poodi punua Buduri Ona OOO OA a SES EXER EE EXE ER C3 C AO E3 ES EREE ES ER EJ EXER ER EIER KNEES ES aa agaon Hacda paadi maada Instruction Classification Table 4 31 Class 7 Instruction Encoding and Description Continuea cenames names ccnames Description CC cc name Not cc name Not cc name name A E E LL CCC P Er EISE hee 36 HOD o CEA Free LOS LO esee tror e e H K CA K E E KE E E A EL CET KE KE E E TEE CEC KA KA EST Isi ETHER sese S EN EU EZERE EE ER ES EX E 4 4 8 Class 8 Instructions Logic and Bit This class of instructions provides a flexible and efficient means to make complex logical decisions Instead of making a sequence of single bit decisions and constructing a logical statement through a branch decision tree the program can sequentially combine several status conditions to directly construct a final logic value TF1 or TF2 which can be used to control a subsequent branch or call This class includes two subclasses Class 8a instructions update one ofthe test flags TF1 or TF2 with alogical combination of the old test flag value and an addressed memory flag value Sub
66. SV t Control Register CTRL T d Interrupt Processor TEXTE Multiplier Serial Interface Registert Serial Interface Oscillator Registert Product High PH t Timer Period PRD1 and PRD2 t vco Timer Register TIM1 and TIM2 T Frequency AEN es Instruction I APO AP3T Decoder Accumulator Pointer l 32 Accumulators ACO AC31 t 1 Column Exchange Incrementor e Top Of Stack TOS T P Stack R7 Program Counter PC T YA C Page R um Protection Register PR I ruens 4 LLL a Loop R4 e Data Pointer DP t te m te gt a gt a a a AY mi tem fje MUX V MUX 7 String Registert 4 Test Code 7 2k x 17 bit arithmetic Unit Program Memory Repeat Countert 30k x 17 bit Status Register STAT t Macro Calls RTS Data Memory 640 x 17 bit t Indicates internal programmable registers Flag Registert MSP50C614 Architecture Figure 2 2 Computational Unit Block Diagram The shaded boxes represent internal programmable registers Shift Value SV 16 Multiplier Register MR 17 bit x 17 bit Multiplexer 16 MSB Product High PH 16 Product Low PL 16 LSB 16 Read Write ACO Accumulators aco ace ACB Internal Databus 16 bit Computation Unit 2 2 Computation Unit 2 2 1 Multiplier The computational unit CU is comprised of a 17 bit by 17 bit Booth s algorithm m
67. Speak asm dsp var irx speak irx Applications 6 9 Texas Instruments C614 Synthesis Code spk_ram irx general init asm sleep asm io ports irx dac isr asm timl isr asm tim2 isr asm mai mai mai mel lkbps qfm 24kbps qfm n asm n irx n ram irx pl rpj File Description Util obj Dsputil asm Getbits asm Speak asm Dsp var irx Speak irx Spk ram irx Melp obj Melp irx 605 asm 605 irx Init asm Sleep asm Io ports irx Dac isr asm iml isr asm Tim2 isr asm Ram irx lkbps qfm 24kbps qfm rey qfm rey bin Main asm Main irx Main ram irx Flags irx Melpl rpj Texas Instruments C614 Synthesis Code Maths functions and tables used by the vocoders Oversampling and miscellaneous functions Routine to get data from ROM Routines to speak a phrase or sentenc Various vocoder constants Speech header constants RAM map of variables common to all vocoders MELP object code MELP include file Routines to read data from external ROM Port usage constants for address and data bus Initialization code to set the clock speed etc Edit at your peril Routines to enter and wake up from the light mid and deep sleep Control register and bitmask definitions DAC interrupt service routine Pimer 1 interrupt service routine keyscan imer 2 interrupt service routine LED flash RAM overlay for t
68. T9 E D DT as ansans Antea papi o o roa an o T Eo To T do T on enga folol i opel R onenean lolol lole I 1 71 Description Bitwise logical XOR of src and dest Result is stored in dest If three operands are specified then logical XOR src and src1 store the result in dest Pre modification of accumulator pointers is allowed with some operand types XOR An adrs XOR RAM word to An XOR Ar An imm16 next A XOR immediate word to An store result in An XOR An An An next A XOR An word to An word store result in An XOR TF flagadrs XOR TFn either TF1 or TF2 with memory tag store result in TFn bit in STAT XOR TFn cc Rx XOR test condition with TFn either TF1 or TF2 bit in STAT register Rx must be provided if cc is one of RZP RNZP RLZP RNLZP to check if the selected Rx is zero or negative Rx should not be provided for other conditionals Assembly Language Instructions 4 181 Individual Instruction Descriptions See Also XORB XORS AND ANDS OR ORS ORB NOTAC NOTACS Example 4 14 84 1 XOR Al Al Ox13FF XOR immediate value 0x13FF to A1 and store result in A1 Example 4 14 84 2 XOR AO AO 2 A Pre increment pointer APO then XOR immediate value 2 to new AO and store result in AO Example 4 14 84 3 XOR Al Al Al XOR accumulator A1 to accumulator A1 put result in accumulator A1 Example 4 14 84 4 XOR A3 R4 XOR word at addre
69. The beginning of the loop is marked with the BEGLOOP instruction which pushes the next sequential address to a temporary register A second instruction ENDLOOP marks the end of the loop When executed ENDLOOP loads the temporary register to the program counter if R4 is positive and then post decrements R4 If R4 is negative the program counter executes a NOP instruction and exits the loop Since interrupts are queued during the execution of the loop no provision for saving the contents of the temporary register is made Interrupts if enabled before the execution of BEGLOOP will automatically be re enabled after exiting the loop Enabling interrupts inside the loop have no effect Queued interrupts are processed according to their priority after the loop exits provided the corresponding interrupt is enabled The loop overhead is 1 instruction cycle per loop cycle ideal for repeating high priority repeated blocks in DSP routines Table 4 42 Hardware Loops in MSP50P614 MSP50C614 Syntax RPT mm8 adrs g repeatable instruction STR ns string instruction R4 NL oop BEGLOOP body of loop ENDLOOP 4 54 Operation Limitations repeatable instruction is executed nR 2 times where np is the value in repeat counter If the instruction following RPT isa string instructions then string length used will be np not the value in the STR register All interrupts are queued during loop execution Queued interrupts ar
70. The string length is defined in STR register Bitwise logical AND the string An or its offset An with the program memory string at location pma16 and store the result in the accumulator string An or its offset An The string length is defined in STR register Compare the accumulator string An or its offset An with the program memory string at location pma16 and store the result in accumulator string An or its offset An The string length is defined in STR register Subtract accumulator string An or its offset An with program memory string at location pma 16 and store the result in accumulator string An or its offset An The string length is defined in STR register Bitwise Logical XOR the accumulator string An or its offset An with program memory string at location pma16 and store the result to accumulator string An or its offset An The string length is defined in STR register Assembly Language Instructions 4 57 Lookup Instructions 4 58 Lookup instructions make use of the data pointer DP internally The DP stores the address of the program memory location loads the value to the destination and increments it automatically after every load Thus the value of the DP is always the last used program memory address plus one The content of DP changes after the execution of lookup instructions If filter instructions FIRK and CORK are used it is required to context save DP in the interrupt service routine Since these filt
71. This is the mode DSP algorithms should use 4 172 Individual Instruction Descriptions 4 14 78 STAG Set Tag Syntax abel rame dest Go ok Word w win RPT ok cress STAG Table 4 46 Table 4 46 Execution memory tag bit at address adrs 1 PC PC W Flags Affected None Opcode Ez jejsjajsja o efe STAG adis ES ifol fof f fofol ____ as dma16 for direct or offset16 long relative see section 4 13 Description Sets the tag bit at the addressed memory location All addressing modes are available Note that this instruction accesses only the 17th bit of the RAM location The argument adrs is interpreted as bytes For odd RAM byte addresses the least significant bit is ignored See Also RTAG RFLAG SFLAG Example 4 14 78 1 STAG R2 R5 Set TAG bit of the word in RAM byte address R2 R5 R2 and R5 remain unchanged Example 4 14 78 2 STAG 0x200 2 Set TAG bit of RAM word 0x200 RAM byte address 0x400 Example 4 14 78 3 STAG 0x401 Set TAG bit of RAM word 0x200 RAM byte address 0x400 Assembly Language Instructions 4 173 Individual Instruction Descriptions 4 14 79 SUB Subtract Syntax abel name dest se ser renal Gies ok Word w With RPT ok ass sus Ani An adis next A su Jane anh mis nena 2 2 NR a sus az Ani ener ma 3 sue Taan a ea 1 mea a sus arctan ant nena 3 ma a su anime a e m Ce su cs A HE Executi
72. VpP SCANIN Scan Interface A port UO EP ROM 32kx 16 1 bit Data 2x00 SCAN Break Point EP XH s 00 Control 0x04 OUT Emulation Test Area 0x0000 to SCANCLK OTP Program reserved 0x07FF m B port VO Data 0x08 ne Ox7FEF Control 0x0C TEST C614 only INT vectors Ox7FFO to PGMPULSE P614 only Ox7FFF Rio ZEE Data 0x10 DAC DAC 0x30 Control 0x14 F Instr Decoder o DACM 32 Ohm PDM i Comparator 1 bit PD5 vs PD4 RESET Initialization TIMER1 PRD1 TIM1 Dpotl O 0x3A OSC Reference TIMER2 PRD2 Resistor Ox3E Trimmed 32 kHz nominal 0x3B Data TIM2 Control Ox3F E port I O Data Control OSCIN Interrupt Processor FLAG MASK OSCouT 0x39 0x38 F port INPUT Data 0x28 Crystal Referenced 2 768 kHz RAM 640 x 17 bit G port OUTPUT PG data 0x000 to 015 PLL PLL Filter 0x027F Data 0x2C Introduction to the MSP50C614 1 7 C605 and C604 Preliminary Information Figure 1 2 Oscillator and PLL Connection a Crystal Oscillator Operation Connections MSP50P614 MSP50C614 OSCIN OSCOUT PLL 10 MOT 32 768 kHzt e L 10 MOT 22 pFt A 22 pF 7T C PLL 3300 pFt T Keep these components as close as possible to the OSCin OSCQuUT and PLL pins b Resistor Trim Operation Connections MSP50C614 MSP50P614 OSCIN OSCOUT PLL R RTO 470 KQ 1 t J C PLL 3300 pFt T Keep
73. __ a _ _ ii Note Instructions with References Care must be taken when employing instructions that have either long string constant references or look up table references These instructions will execute properly only if the address of the instruction and the address of the data reference are within the same block ype MSP50C614 Architecture 2 19 Memory Organization RAM and ROM The protection modes are implemented on the C614 as follows Within the ROM is a dedicated storage for the block protection word address Ox7FFE The block protection word is divided into two 6 bit fields and two single bit fields The remainder of the 17 bit word is broken into three single bit fields which are reserved for future use ROM Block Protection Word address Ox7FFE 17 bit wide location WRITE only 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 R R IM TM TM TM TM TM GP BP R FM FM FM FM FM FM 05 04 03 02 01 00 05 04 03 02 01 00 True Protection Marker Ny GP Global Protection 0 value protects False Protection Marker Nep BP Block Protection 0 value protects Reserved for future use must be 1 1 Default value of cells on erasure The two 6 bit fields are designated as the true protection marker TM5 through TMO and the false protection marker FM5 through FMO When setting up a partition for partial ROM protection the address of the partition must be spe cif
74. a a Description Perform two s complement negation of src accumulator string and store result in dest accumulator string See Also NEGAC SUB SUBB SUBS ADD ADDB ADDS NOTAC NOTACS Example 4 14 47 1 NEGACS A3 A3 Negate accumulator string A3 and store result in accumulator string A3 Assembly Language Instructions 4 141 Individual Instruction Descriptions 4 14 48 NOP No Operation Syntax abel name Tos Wore w wit RPT ok Grass H A l3 lows ls Execution PC PC 1 No operation Flags Affected None Opcode Instructions Pro fis 14 fia 12 to o e v e 8 a EH 2 1 fo Np ER E EE A E KH ER ERER E EEN Description This instruction performs no operation lt consumes 1 clock of execution time and 1 word of program memory See Also RPT Example 4 14 48 1 NOP Consumes 1 clock cycle 4 142 Individual Instruction Descriptions 4 14 49 NOTAC One s Complement Negation of Accumulator Syntax labe name dest src mod Clock clk With RPT clk Notac TA AL next A Execution premodify AP if mod specified dest NOT src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode instructions Pro 15 1a HS 12 fro o fe v e 8 a js 2 1 o NOTAC Art Art 1b nextAl_ 111 1 fo o neta An fofoJofof JoJa A Description Premodify accumulator pointer if specified Perform one s complement of src accumulator and store resul
75. acc OVS A0 RO RO POINTS TO VALUE IN MEMORY EXTSGN A1 not string version as above Alternatively the following code can do the same thing but requires more code MOV APO O POINT TO LSW OF ACCUM STRING MOV AP1 3 Point to loc corresponding to extended word in acc ZAC A1 INITIALIZE EXTENDED SIGN VALUE as positive MOVS AO RO RO POINTS TO VALUE IN MEMORY JNS POSITIVE branch around negative extension accepting default pos extension NOT A1 INVERT EXTENDED SIGN WORD FOR NEG CASE POSITIVE See Also EXTSGN Example 4 14 17 1 EXTSGNS AO Sign extend accumulator string AO See the above IMPORTANT note on the bug in this instruction at the present time Assembly Language Instructions 4 99 Individual Instruction Descriptions 4 14 18 FIR FIR Filter Function Coefficients in RAM Syntax Tato ame aes se Sook ek Word w Win RPT ok onse pm jm Aa T Execution With RPT N 2 mask interrupts RPT counter N 2 MR h 0 first filter coefficient x sample data pointed at by RXeven h 1 second filter coefficient pointed at RXeyen 1 y result stored in three consecutive accumulators 32 bit pointed by An between every accumulation IF TAG 1 RXeven RXeven R5 for circular buffering ELSE RXeven if Rx is specified in the instruction ENDIF PC PC 1 final result Y Pron UN ANA Execu
76. an indirect reference The indirect reference includes a direct reference to one of 16 and an offset optional which increments the reference by 16 AC N 16 For example ACO has its offset register located at AC16 AC1 has an offset register located at AC17 and so on The block is circular address 31 when incremented results in address 0 The offsets of AC16 through AC31 therefore are ACO through AC15 respectively See Figure 2 5 Indirect referencing by the AP pointers is supported by most of the C614 s accumulator referenced instructions MSP50C614 Architecture 2 9 Computation Unit When writing an accumulator referenced instruction therefore the working accumulator address is stored in one of APO to AP3 The C614 instruction set provides a two bit field for all accumulator referenced instructions The two bit field serves as a reference to the accumulator pointer which in turn stores the address of the actual 16 bit accumulator Some MOV instructions store the contents of the APn directly to memory or load from memory to the APn register Other instructions can add or load 5 bit constants to the current APn register contents A full description of the C614 instruction set is given in Chapter 4 Instructions Figure 2 5 Overview of the Arithmetic Logic Unit Accumulator Block 32 16 bit registers AC 0 AC 31 Accumulator Block Pointers 4 5 bit registers AP 0 AP 3 The accumulator block pointers may assum
77. at shriek4 and then do a Run Internal yellow lightning black centipede icon Step over press F8 and the accumulator 00 will be 0004 after the movb instruction Step over once more and the accumulator 00 will be 0018 after calling the do shriek function Understanding the RAM Map In the above code the value of 4 is stored in the variable shriekvar The list file MAIN LST shows the location of this variable to be 0x448 which is an offset of 0x448 bytes from the beginning of the RAM at 0x000 Since the RAM window displays words of RAM the shriekvar variable is shown at 0x448 2 which is 0x224 To verify this step overthe do shriekfunction and watch RAM location 0x224 change from 0000 blue to 0018 red Modifying Files and Projects The 614 code contains certain files which may be edited some files which should only be edited with good reason and a few files which should never be edited In general These files may be edited MAIN ASM MAIN IRX MAIN RAM IRX and FLAGS IRX Texas Instruments C614 Synthesis Code These files may be edited for special purpose code INIT ASM and SPEAK ASM These files should never be edited SLEEP ASM RAM IRX and SPK RAM IRX A good rule of thumb to follow is that files under the DSP directory should be left alone and all custom code should be added either to MAIN ASM or to a new directory under MODULES e g MODULES CUSTCODE Creating a New Project The easiest way to cr
78. bits i e 1 835 008 bits of slow data ROM The program ROM space is divided into three areas 1 The initial 2K words of ROM 0x0000 0x07FF is reserved for built in self test BIST that is provided by Texas Instruments during mass production 2 Customer can use the program ROM from address extending from 0x0800 to Ox7FFF Restrictions on using certain program ROM location is shown in Figure A 2 The Data ROMis a slower ROM dedicated only to hold data Data ROM cannot execute program instructions The Data ROM locations start from 0x00000 and ends at 0x37FFF The lower 16 bits of the address to be read is provided into IO port DRA register 0x2C the upper 2 bits goes into IO port DRP regis ter 0x08 After 1 5 instruction cycle delay the 8 bit data appears at lO port DRD 0x00 Discharging time is always 3 processor cycle and data is latched to port DRD during this time There is 3 5 page in MSP50C605 pages 0 1 and 2 are full page 3 is half Using 1Kbps MELP algorithm this ROM can provide over 30 minutes of uninterrupted speech Port 10 Name Description Address Function DRA Data ROM Address 0x2C write into this port to access 16 bit of the data ROM address DRP Data ROM Page 0x08 write into this port to select ROM page DRD Data ROM Data 0x00 read this port to get data at specified ROM page and address The MSP50C605 has 32 input output pins 24 of the pins are software confi gurable as either input or output port
79. clear accum pointer 2 mov ap3 0 clear accum pointer 3 mov r0 0 Clear register 0 mov r1 0 Clear register 1 mov r2 0 clear register 2 mov r3 0 clear register 3 mov r4 0 Clear register 4 mov 5 0 clear register 5 mov r6 0 Clear register 6 mov r7 0 clear register 7 mov sv 0 clear shift value register mov TOS 0x000 clear top of stack register mov PH 0x000 clear product high register mov MR 0x000 clear multiplier register PR RRR RRR KKK KKK RRR KKK KK RK KR KK KKK KER KER KKK ko ke RK KE RK KKK KKK KEK KKK KKK KK Choose the source for the reference oscillator Set the PLLM vegister accordingly in this case for a CPU clock of 8 MHz and then set TIMER 2 to a 200 ms period Go to sleep do an IDLE and wake up when the clock has veached full speed and is stable fRRRR ERR EERE EERE EWR KR KON EE ERE EEK REE RRE RE RR EEK EE BRE EEK EE BRK EEK KE if CRO_FLAG mov a0 CROENABLE enable crystal oscillator else if C614 FLAG in a0 RTRIM for C614 read trim value from register else mov a0 RESISTORTRIM for P614 the user supplies the trim value endif and a0 0x3f only want lower 6 bits mov a0 a0 save a copy for later mov sv 10 need to shift left by 10 shltpl a0 a0 bit 1 is now bit 11 bit 0 now bit 10 or a0 RTOENABLE enable resistor trimmed oscillator and a0 IDLEBIT clear bit 10 6 bit trim resides in bits 15 11 and bit 9 LSB of
80. clears another status namely the respective bit in the IFR This action automatically communicates to the IFR that the current pending interrupt is now being serviced Once cleared the IFR bit is ready to receive another SET whenever the next trigger event occurs for that interrupt o a a Note Interrupt Service Branch If the interrupt service branch is not enabled by the respective bit in the mask register then neither the global interrupt enable nor the respective flag bit is cleared No program vectoring occurs A Interrupt Logic Figure 2 8 provides an overview of the interrupt control sequence INTO is the highest priority interrupt and INT7 is the lowest priority interrupt Figure 2 8 Interrupt Initialization Sequence INTD instruction Global Interrupt Enable Interrupt Trigger Event Internal Timer Underflow INTE CLEAR instruction External Input Falling Edge External Input Rising Edge e Software Write Instructiont SET BIT v INT Flag bits IFR Associated With the Interrupt Trigger Event Interrupt Flag Register 0x39 INT Mask bits IMR Specific Enable for Interrupt Service Interrupt General Control Register 0x38 t Interrupt Interrupt Service Branch Service Routine Highest Priority INT is Selected From 1 of 8 Among Those Flagged and Enabled Program Branches to Location Stored in Interrupt Vector Interrupt Vector Storage Ox7FFO Ox
81. combination There are three combinations however which are primarily useful The three modes light mid and deep sleep are executed through the independent control of two bits 1 the idle state clock control and 2 the reference oscillator enable The other pertinent controls simply enhance the performance of the modes dictated by these two Table 2 3 gives a listing of all of the controls which should be maintained by the programmer before engaging the IDLE instruction In some cases it will be impossible to wake from sleep unless certain controls are set appropriately before going to sleep In those cases only the hardware RESET low to high will bring the device back into its normal operating state The top row in Table 2 3 lists the first of the two primary controls namely the idle state clock control The idle state clock control determines the status of the master clock MC during sleep Setting the idle state control causes the CPU clock the PLL clock circuitry and the MC to stop after the next IDLE instruction Clearing the idle state control causes only the CPU clock to stop after IDLE The PLL clock circuitry governs the MC and determines its rate Whenever the PLL circuitry is suspended therefore the MC stops The idle state clock control is accessed at bit 10 in the CIkSpdCtrl register Refer to Section 2 9 3 Clock Speed Control Register for more information The reference oscillator enable is the other control which s
82. completes Section 2A Customer verifies the of NPRF and sends verifi devices work properly and cation code in QBN for completes Section 4 of the mat with BIST included amp NPRF NPRF form to customer TI produces the chip Customer verifies in production quantities code is correct Customer signs Section 3 of the NPRF and sends it to TI TI generates prototype parts for Customer verification Texas Instruments recommends that prototype devices not be used in produc tion systems The expected end use failure rate of these devices is undefined however it is predicted to be greater than that of the standard qualified produc tion Customer Information 7 9 Ordering Information 7 5 Ordering Information Because the MSP50C614 is a custom device it receives a distinct identifica tion as follows CSM 614 XXX X X Gate Code Family ROM Revision Package or Die CSM Custom Member Code Letter PJM Loopin QFP Synthesizer Preliminary With Memory Y Die 7 6 New Product Release Forms The new product release form is used to track and document all the steps in volved in implementing a new speech code onto one of the parent speech de vices This section is to be completed by the customer and sent to TI along with the code 7 10 New Product Release Forms NEW PRODUCT RELEASE FORM FOR MSP50C614 DIE ONLY SECTION 1 ORDER INFORMATION Division Company Project Name
83. cursor over it Assembly files extension asm and C files extension cmm can be put in a project as well as object files created by the emulator extension obj In particular do not forget to include the cmm6xx asm or cmm6xx obj once it has been assembled file in any project containing C files Once all necessary files have been inserted in a project it is a good idea to save the project Menu Project Save The user can then build from scratch or make only files that have to be assembled compiled linked the project If errors are detected the emulator will automatically bring up an editor Code Development Tools 5 15 Software Emulator pfe32 exe and an error dialog The user can modify the source code and save the changes before restarting the building action 5 6 3 Description of Windows Once a new project is created or an old project is opened the following seven windows pops open Figure 5 16 Figure 5 16 MSP50P614 MSP50C614 Code Development Windows im MSP50C xx Code development Tool EMU PCM RPJ topped File Options Project _ m Window Help a sme E sls 12 E d Se I x 20 ay Ez RAM Window W T EIE Ez CPU Windg Ez eem Window a ES 0000h 0000 0000 OC Accumulato 0000 Z disabi 0008h 0010h 0000 OC 0001 mov APO 0 Z ualde 0010h 0020hj 0000 OC 2 0000 0002 mov AP3 0 O 0000 0002 mov APi 0 0018h O0030h OOOO OC Clear all Accumulators 1 0
84. eee eee B 1 Bal J4ntrOdUcliOFi ceis sat daha race eb eti bcn n d ad aen ddr aed B 2 B2 ECAlUTOS scuba baba MA LR E Mae mate B 2 B jO ArchitectUte icol A EO Rt RCM RU RR Ge RA Rer eds B 2 B 3 1 RAM acristalada ebd Pads aset ia B 3 Ee OO I B 3 B339 Le X LEE B 3 B 3 4 Slave Mode Operation 0 00 eee eee eee B 5 Contents B 3 5 Host Write Sequence ssssssssseses seen B 5 B 3 6 Host Read Sequence 00 ccc eee sns B 5 B 3 7 7 Interrupts oi ie b dre I d eate lua B 7 Bia Packaging cid A edo etii dis B 8 C MSP50C605 Data Sheet oooocococcccccn nnn nnn nnn C 1 C 1 MSP50C605 Data Sheet sssssssesssssesssese n C 2 Contents xi Figures dd ck Ld ot ot Ld god g AON Qn E GM l K OON OOO l o DN T L d I RO Na aa a a a C1 GO Y O Ci Functional Block Diagram for the C614 sees 1 7 Oscillator and PLL Connection sess 9 809 980 2 aR 09 ninien ia 0 a n 1 8 RESET Circuit e a A AA AAA A A 1 9 MSP50C614 100 Pin PUM PLastic Package Pinout cece eee eee 1 12 120 Pin Grid Array Package for the Development Device P614 1 13 MSP50C614 Core Processor Block Diagram 2 3 Computational Unit Block Diagram n 2 4 Overview of the Multiplier Unit Operation e eee eee 2 7 Overview of the Arithmetic Logic Un no 2 9 Overview of the Arithmetic Logic Un e o 2 10
85. example sup pose that startOfBuf f points to the first RAM location of the circular buffer Assembly Language Instructions 4 61 Special Filter Instructions 4 62 After the FIR or COR instruction executes the new startOfBuf f will be the last location in the circular buffer After another FIR COR instruction the new startOfBuff will be the second to last location in the circular buffer and so on The second detail is the STAT register The STAT register must be saved im mediately after every FIR or COR instruction Consequently this saved value must be loaded before every FIR or COR instruction If the tag bit in the STAT register is set before an FIR or COR instruction this tells the processor two things First it knows that it must wrap around to the first RAM location of the circular buffer Second it knows that the startOfBuff and RO currently points to the last location in the circular buffer Thus RO will increment by R5 after the first multiply This will become more clear after examining the next ex ample code The third detail is that the filter coefficients take up only N RAM locations but the circular buffer takes up N 1 RAM locations Below is an example of the FIR or COR execution inside a DAC interrupt ser vice routine FIR Filtering routine N 3 rovm reset overflow mode mov R55 2 N circular buffer length 3 words mov R1 coef s R1 points to first of N filter coefficients mov MR R
86. executing only once but maintains the CF and ZF status of the previous multiply or shift operation as if the sequence was a single string IMPORTANT At this stage of documentation a bug in this instruction causes the processor to stall when an attempt is made to sign extend a string that has all zeros in it Also the same interrupt problem on the accumulator pointers exists if the instruction just before is not a string instruction For customers who need the EXTSGNS function now as it was originally intended for string data there is a workaround Unfortunately it involves the use of two accumulator pointers the second pointing to the position in the accumulator register file that would correspond to the extended word location For example if a string exists in memory with the value Ox943500000000 3 word string and the value was to be moved to a accumulator as a 64 bit sign extended value the following code would have been without bugs OV APO 0 OVS A0 RO RO POINTS TO VALUE IN MEMORY EXTSGNS AO EXTENDS THE SIGN OF ABOVE ADD IN ACC 3 Since the bug causes the above function to fail the status of the 2 least signifi cant words is equal to zero However the same case will be correctly executed with the desired result with the existing bug MOV APO O0 POINT TO LSW OF ACCUM STRING 4 98 Individual Instruction Descriptions OV AP1 3 Point to loc corresponding to extended word in
87. filtering N 3 First clear circular buffer and set tag of second to last 3 sample zac a0 mov r0 circBuff point to circular buffer rpt N 2 repeat N times mov r0 a0 clear RAM locations in circular buffer mov r0 a0 N 1 sample in buffer mov 552 now step back one word and set tag sub r0 r5 point r0 back to 2nd to last sample in buffer stag r0 set tag Second initialize filter coeffs to proper values n nere NOTE In this code N must be less than 33 since p EPS there are only 32 accumulator registers mov STR N 2 set string length to N zacs aU zero out N accumulators mov a0 FIR COEFFS point to filter coeffs movs a0 a0 get N filter coeffs mov r0 coeffs point to RAM locs for filter coeffs movs r0 a0 put filter coeffs into RAM locs mov a0 circBuff set up pointer to start of circular buffer mov startOfBuff a0 Initialize filterSTAT tag THIS IS IMPORTANT rovm This line is MANDATORY sxm Sample values are signed mov filterSTAT tag STAT Three more details in the above example merit an explanation The first detail is the pointer to the start of the circular buffer startOfBuff This keeps track of the location of the newest or current sample in the circular buffer It moves backwards by one location in the buffer each time the FIR or COR instruction is executed so that the oldest sample in the buffer is overwritten with the next sample This backwards movementis also circular For
88. for PLL to stabilize J Zeros out system registers Finally jumps to the label main WARNING If P614 parts are used for development then the user MUST CHANGE the resistor trim initialization to read from port 0x2F when switching to the C6xx part MSP50C614 MSP50P614 Initialization Codes 6 2 1 File init asm PRR RR RRR RRR KKK RAK KEK KKK KK RK KEK KKK RR RRE EK koc ke kk ke ck koc kk koc ke RR RAR kc ke ke e KK INIT ASM Copyright 1998 Texas Instruments Inc All rights reserved This Initialization Routine has the following Dependent Files These should be included once within the MAIN program ASM file IMPORTANT H Texas Instruments reserves the right to change this routine at any time without notice This Initialization Routine performs the following Functions r 1 Disable interrupt 2 Zeros all accumulators 3 Clears memory 4 Starts PLL with clock frequency defined by PLLMBITS Appropriately sets the RTO trim bits for C614 only Switch to idle mode for 200ms A for PLL to stabilize 5 If DAC interrupt is replaced by Timer 1 interrupt the period of E timer 1 is stored in TIM1 register 6 Zeros all system registers except R7 STACK Turn off TIMER 2 rather than leave it running Modified to cope with 6 bit trim value Top 5 bits go to bits 15 11 in ClkSpdCtrl LSB of trim goes to bit 9 in ClkSpdCtrl A fairly basic but compact
89. found to be acceptable and I authorize TI to start normal production in accor dance with purchase order By Title Date ck Ck ck ck ck ck Ck ck ck Ck ck ck Ck Sk ck ck Sk KK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK ck kk KKK KK KKK KKK KKK KK KKK KK Return to Texas Instruments Incorporated Attn Code Release Team P O Box 660199 M S 8718 Dallas TX 75266 0199 OR Fax to 972 480 7301 Attn Code Release Team Have Questions CALL Code Release Team 972 480 4444 OR E MAIL code rel msp sc ti com Customer Information 7 11 7 12 Appendix A MSP50C605 Preliminary Data This Appendix contains preliminary data for the MSP50C605 device Note MSP50C605 MSP50C605 is in the Product Preview stage of development For more in formation contact your local TI sales office Topic Page A Tw9Introductioni a a tetra E T A 2 NC A O O O HEU ODIO A 2 A Architecture a ey erexerunt eu e simis siepe Eras A 2 A 1 Introduction A 1 Introduction MSP50C605 is a spin off of the core processor MSP50C614 It uses three IO ports of MSP50C614 and maps a 1 835 Mbits of internal ROM Using a 1 kbps MELP algorithm the C605 can provide over 30 minutes of uninterrupted speech There is no Port A and Port B control register in MSP50C605 Port DRD is read only and Port DRP and DRA are write only Apart from the addi tional ROM and corresponding IO port changes all other functionality of the proc
90. going through the initialization security check This forces all look up tables and long constant references to originate from an external program source when in emulation mode It is possible to switch from trace mode to emulation mode by lowering Vpp but this transition by design does not jeopardize code security 2 6 5 Macro Call Vectors Macro call vectors are similar to CALL instructions except they take an 8 bit address The upper 8 bits is always 7Fh See Section 4 14 83 VCALL for more information on the VCALL instruction 2 7 Interrupt Logic 2 22 An eight level interrupt system is included as part of the C614 s core processor The initialization and control of these interrupts is governed by the following components the global interrupt enable the interrupt flag register the interrupt mask register and the interrupt service branch Each of these is described below Interrupts must be globally enabled using the INTE instruction and they are globally disabled using the INTD instruction INTE sets the global interrupt enable bit and INTD clears the global interrupt enable bit The state of this bit specifically determines whether any interrupt service branches will be taken The global interrupt enable appears as bit 4 within the status register STAT Each interrupt level waits for the conditions of its trigger event refer to Figure 2 8 At the time that a trigger event occurs the respective bit is automatically S
91. imm8 4 202 Instruction Set Summary CN EEE TO woes E oues pos eue H ewe MZ m kws wririmar H 3 wR per me eme AU INC Dn mes a 3 cc names Description echamg True Condition Not true condition Zz Ww Conditional on ZF 1 Not condition ZF 0 s N Conditional on SF 1 Not condition SF 0 Conditional on CF 1 Not condition CF 0 Conditional on ZF 0 and CF 0 Not condition ZF 0 or CF 0 Conditional on ZF 0 and CF 1 Not condition ZF 0 or CFz1 Conditional on SF 0 and ZF 0 Not condition SF 0 or ZF 0 Conditional if ZF 1 and OF 0 Not condition ZFz1 or OF 0 Conditional if OF 1 Not condition OF 0 Conditional on RCF 1 Not condition RCF 0 Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCFz1 Conditional on RZF 1 Not condition RZF ll l ll ll o E HOM MUA Ene HEM E RZP Conditional on value of Rx 0 Not condition Rxx0 Not available on Calls RNLZP Conditional on MSB of Rx 1 Not condition MSB of Rx 0 Not available on Calls Conditional on ZF 0 and SF 1 Not condition ZF 0 or SFz1 NTF1 Conditional on TF1 1 Not condition TF1 0 NTF2 NTAG Conditional on TF2 1 Not condition TF2 0 Conditional on TAG 1 Not condition TAG 0 d ANOS NT ES C T I E 2 e Conditional on IN1 1 status Not condition IN1 0 Conditional on IN2 1 status Not condition IN2 0 Conditional on XZF 1 Not condition XZF 0 Conditional on XSF 1 Not condition XSF 0 Conditional on XS
92. in accumulator string AO Example 4 14 86 2 XORS A3 A3 R1 R5 XOR data memory string beginning at address in R1 to accumulator string A3 put result in accumulator string A3 Add value in R5 to the value in R1 and store result in R1 Example 4 14 86 3 XORS Al Al 0x100 2 XOR program memory string beginning at word address 0x0100 to accumulator string A1 put result in accumulator string A1 Example 4 14 86 4 XORS A2 A2 A2 XOR accumulator string A2 with accumulator string A2 string put result in accumulator string A2 4 184 Individual Instruction Descriptions 4 14 87 ZAC Zero Accumulator Syntax labe rame aesti moa Taa ok Word w With RPT ok crass zac TAL next A Execution premodify AP if mod specified dest 0 PC PC 1 Flags Affected ZF 1 Instructions Pi 15 Pra i i2 fio o fa v Je js a a 2 t o zac Aru next t s tjo o nea An Jo ojops ryo o a Description Zero the specified accumulator Preincrement or predecrement accumulator pointer AP if specified See Also ZACS Example 4 14 87 1 ZAC A2 Reset the content of accumulator AO to zero Example 4 14 87 2 ZAC Al A Preincrement AP1 by 1 Reset the content of new accumulator A1 to zero Assembly Language Instructions 4 185 Individual Instruction Descriptions 4 14 88 ZACS Zero Accumulator String Syntax Ciao name ss Geek ok wora w With RPT ok crass p ome jam
93. initialization routine for the 614 This sets the 614 to run at 8 MHz 10 bit DAC at 8 kHz PRR RR RRR RK RK RK KEK koc RARE ko ke EK ke RAR kk KEK koc kk koc KEK KEK KKK KKK ko ke kk koc KKK ke e KK C614FLAG EQU 0 EQU 1 if MSP50C614 part RESISTORTRIM EQU 0x20 Resistor trim value for MSP50P614 ONLY CRO FLAG EQU 0 EQU O for resistor trimmed osc RTO EQU 1 for external crystal ref CRO PLLMBITS EQU 0x7C For CPU clock of 8MHz PRR R RRR RRR KKK RRR ke KEK AAA ER RE KK KEK ke kc ko koc kc kk ke kk KER KEK KKK KK Start off by clearing all the RAM and tags and then zero every register The status register STAT must be cleared immediately upon power up ARREERERAIERE RARE RERE RARE RARE RARE ERE RARE eae se i RARE ERE RARE RARE RARA init614 zac aU clear a0 mov 0x000 a0 clear first RAM location mov STAT 0x000 clear status register mov STR 32 2 set string register to loop 32 times zacs a0 clear all accumulators out IFR a0 clear pending interrupts Applications 6 5 MSP50C614 MSP50P614 Initialization Codes out IntGenCtrl a0 clear all interrupt mask bits disable timers mov r0 0x000 point to beginning of RAM mov r4 RAM_SIZE 2 do a loop RAM_SIZE times BEGLOOP rtag r reset tag mov r0 a0 clear the RAM ENDLOOP mov STR 0 clear string register mov apo 0 clear accum pointer 0 mov ap1 0 clear accum pointer 1 mov ap2 0
94. is executed Instruction sc pma amoa cw WewimpongF i INC pmai6 Rmo ConditonaljumponGF 0 JE prar mod _ Conditonaljumponequal INE pma16 1 Amo CedWondjumponnoremd UN omar Amoa CondWondjumonporDpimPOp i LM pma Amod Conditional jump on port D pin PDg 0 nz prar Amoa Conanonai ump onpon D pn Po ININ2 pmar61 Amo Condiional ump on pon D pin PDO sO pmarer mod _ ConditonaljumponOF 1 SSS INO pmai6 mod _ ConditonaljumponOF 0 SCS JRA pmai6 Amoa Conditional ump on Rabove unsigned IRC omaro Amoa CoWondiumponXCF 1 HmNCpmarRmod ConWondjumponXtF 0 Conditional jump on XZF 1 equal t RNBEpma l mod Conditional jump on Rxnot below or equal unsigned JRLZP pmaf6 Rmod CondiionaljmponRx lt 0afterpostmod_ Assembly Language Instructions 4 111 Individual Instruction Descriptions Instruction JANLZP pmai6 Amod OondiionaljumponRx 0 ar postmod JANZP pmai6 Rmo Conditionat jump on Rxz 0 after postmod JS pmat6 Amod owdWommponSF T INS pmai6 Amod ___ GondltionaljumponSF 0 CS GwsWoniimpoTG i O JTAG pma16 Rmod JNTAG pma16 Rmod Conditional jump on TAG 0 JTF1 pma16 Rmod Conditional jump on TF1 1 JNTF1 pma16 Rmod Conditional jump on TF1 0 STE2 pmar6l Amod CendWondjumponTF2 1 INTE2 parol Amod ConWondjump
95. its new hexadecimal value over the existing value Values of read only registers cannot be modified Figure 5 23 I O Ports Window im MSP50C xx Code Development Tool EMU SHL RPJ Mie ES 20000 0010 0010 0010 0010 0000 0000 0000 0000 1008 0000 0000 0000 0000 0000 0000 0000 0000 10 OOFF OOFF OOFF OOFF 0000 0000 0000 0000 18 OO F OO07F 007F 007F 0000 0000 0000 0000 20 ODOF OOOF OOOF OOOF 0000 0000 0000 0000 28 DOFF OOFF OOFF OOFF OOFF 0000 0000 0000 30 0000 0000 0000 0000 0000 0000 0000 0000 38 0000 OODS FFFF FFFF 0000 0000 FFFF FFFF OOOOOO 1 s Find String CTRL F11 Project Window All source files making up the project are displayed in this window Only assembly language files asm and C source files cmm should be inserted in a project To insert a file activate the project window by positioning the mouse over it and hit the INS key A file dialog will appear It is also possible to use the File Insert Menu option in the main window To remove a file from a project double click the left mouse button on the filename only top level files can be removed The file becomes highlighted in yellow Hit the DEL key to remove it from the project The indentations in the display reflect the depth of inclusion of dependent files 5 6 4 Debugging a Program 5 22 The software emulator allows various types of debugging The Debug menu Figure 5 23 options are explained in detail as follo
96. location value ad dressed by R7 STACK to program counter T The entire 17 bit is encoded See Table 4 26 Assembly Language Instructions 4 37 Instruction Classification Table 4 27 Class 5 Instruction Description Continued Mnemonic Description RPT aarsjg Load repeat counter with lower 8 bits of data memory location referred by addressing mode adrs Interrupts are queued during execution MOV STAT adrs Load status STAT register with effective data memory location referred by addressing mode adrs 17 bits with TAG 4 4 6 Class 6 Instructions Port and Memory Reference These instructions provide the basic expansion port of the MSP50P614 MSP50C614 processor IN instructions transfer 16 bit data from one of 16 expansion ports OUT instructions transfer 16 bit data to one of the 16 expansion ports In a typical system the expansion ports are divided into those that serve internal peripheral functions and those that serve external pins For subclass 6b IN and OUT provide bidirectional transfers between the same port address 16 and accumulator In addition IN and OUT instructions in class 6b can communicate with an extra 48 ports a total of 64 including the shared ports Class 6b instructions also have reference to the string bit for checking the arithmetic status of a string transfer Table 4 28 Class 6a Instruction Encoding sppe E deee EA E E E Table
97. ma D o3 To ms l3 Execution dest 0 PC amp PC 1 Flags Affected ZF 1 Instructions Pie fas HI 18 12 11 to o jo v e 8 a Pa 12 o zacs aj Tt tt foto fits an ojo ojs tjo o J Aj Description Zero the specified accumulator string See Also ZAC Example 4 14 88 1 ZACS Al Reset the content of offset accumulator string A1 to zero Example 4 14 88 2 MOV STR 32 2 ZACS AO Reset the content of all accumulators to zero It does not matter which accumulator APO is pointing at since all the accumulators are zeroed 4 186 Instruction Set Encoding 4 15 Instruction Set Encoding as fefe jeepee e e T TSTS TSTS TT aDD ari an taa nera RH EH RH o fa mena a ade 7 ADD a Art mei noa 3 1 o To Do rea an 9 To To Do To T1 IT X imm16 CAES ADD ari an Antena 3 1 1 o o ron an o o lo To fa LUE cma X imm16 monss h EEEE E ee h ee e Tolo ADD APA mms faja fa apo fr aro oft fol mms anos arms apo fr fofofofo ar imme n mm paan 1 010 1 Jo 010105 01200 e 210 ADDS Ar An adrs fo of o fo al1 1 an X dma16 for direct or offset16 long relative see section 4 13 ADDS X Ar pma16 ilijojoji ji ar ojojojojo t fa a E fmt adrs pma16 X ADDS Arf An An ER ERER 3 UE EH an fofo ts fofi o fa E anaa AT PR E A E AND An ad TSTS TSTS Ta as dma16 for direct or offset16 long relative see section 4 13 x ree lee eee REB CHEN X imm16 man
98. of R3 with MR register and store PL in accumulator string AO Increment R3 by 2 Example 4 14 45 2 MULTPLS A2 A2 Multiply MR register to accumulator string A2 and store PL to accumulator string A2 Assembly Language Instructions 4 139 Individual Instruction Descriptions 4 14 46 NEGAC Two s Complement Negation of Accumulator Syntax label name dest src mod Clock clk With RPT clk NEGAC Ani AL next A Execution premodify AP if mod specified dest src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pro 15 14 fia 112 t fio fo Je v e 8 a EH 2 1 fo NEGAC An An p nexa 1 1 o o neta An fo foo foo o a A Description Perform two s complement negation of srcaccumulator and store result in dest accumulator See Also NEGACS SUB SUBB SUBS ADD ADDB ADDS NOTAC NOTACS Example 4 14 46 1 NEGAC A3 A3 A Predecrement accumulator pointer AP3 Negate accumulator A3 and store result in accumulator A3 4 140 Individual Instruction Descriptions 4 14 47 NEGACS Two s Complement Negation of Accumulator String Syntax labe rame aese Ta ok Word w With RPT ck crass NEGACS TAT Ani Execution dest src PC e PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pro 15 pafis 12 fn to o e v e 8 a js 2 1 wursPLSAn An 15s trjo o js t an Jo ojJopo opo
99. of accumulator pointers is allowed with some operand types MOV An Arr L next A MOV MR Ar next A Move An to MR register in signed multiplier mode Move data memory word lower 6 bits to APn register Move product high PH register to data memory Move string register STR byte to data memory Move data pointer DP to data memory Move data memory byte to string register STR Move top of stack TOS to data memory word Load logic value of test condition to TEn bit in STAT register MOV SV imm4 Move immediate value to shift value SV register MOV MR aars Move data memory word to MR set multiplier signed mode x MOV aarsj MR Move Multiplier register MR to data memory DP Assembly Language Instructions 4 117 Individual Instruction Descriptions MOV STR imm8 Move immediate byte to String Register STR MOV APn imm5 Move immediate 5 bit value to APn register T Accumulator condition flags are modified to reflect the value loaded into either An or An t Signed multiplier mode resets UM bit 1 in status register to O T Load the logic value of the test condition to the TFn bit in the status register STAT If the condition is true TFn 1 else TFn 0 See Also MOVU MOVT MOVB MOVBS MOVS Example 4 14 28 1 MOV A0 0x0200 2 A Preincrement accumulator pointer APO Copy content of word memory location 0x0200 to accumulator AO Example 4 14 28 2 MOV 0x0200 2 AO A Preincrement accumu
100. or offset16 long relative see section 4 13 pma16 S E EH EH ER C E KH EH ECOL ES ER ERR ER ER ERES apps anti an Po 1 i s foto a ofi rfo fo a fa Description Add value of src string to the value of src1 string and store resulting string in dest String length minus two should be stored in STR before execution See Also ADD ADDB SUB SUBB SUBS Example 4 14 3 1 ADDS AO AO R2 Add data memory string beginning at address in R2 to accumulator string AO put result in accumulator string AO Example 4 14 3 2 ADDS AO A0 0x1400 Add program memory string beginning at address 0x1400 to accumulator string AO put result in accumulator string AO 4 78 Individual Instruction Descriptions Example 4 14 3 3 ADDS Al Al Al Add accumulator string A1 to accumulator string A1 put result in accumulator string A1 Example 4 14 3 4 MULAPL AO A0 ADDS AO A0 PH The first instruction multiplies MR and AO adds PL to AO and stores the result in AO The second instruction adds PH to the second word of memory string AO and puts the result in accumulator string AO Note that MULAPL and ADDS constitute a special sequence When this sequence occurs interrupts are NOT disabled so interrupts should be disabled for correct operation In extended sign mode if AO is ACO 0x0000 A0 is AC1620xFFFF and MR OxFF after execution ACO 0xFF01 AC1 0xFFFF Assembly Language Instructions 4 79 Individual Instruction Descriptions
101. program a context save and restore must be performed on the DP register for each FIRK CORK instruction See the chapter 4 section called Lookup Instructions During FIRK CORK execution the MR register is loaded with the contents of the DP register the DP register increments pointing to the next filter coefficient and the multiply accumulate is performed The remaining FIRK CORK code is almost the same as the FIR COR code mov RO startOfBuff RO points to start of circular buffer mov APO 0 set up room for the mov STR 0 32 bit output sample ACO and AC1 zacs AO STR should be 1 for COR CORK instructions Assembly Language Instructions 4 65 Special Filter Instructions 4 66 mov STAT filterSTAT tag load STAT with last filter tag status rpt N 2 firk AO RO Do one sample gt 32 bit result mov filterSTAT tag STAT save STAT with last filter tag status RO now points to the last sample movs ySampleOut AO0 FIR outputs bits 0 15 in ACO 16 32 in AC1 mov A0 nextSample Replace last sample with newest sample and update mov RO AO0 the start of the mov startOfBuft RO Circular buffer to here RO The setup for the FIRK CORK instruction is the same as the set up for the FIR COR instruction with the exception that the filter coefficients do not need to be loaded into RAM locations Rather they can be included just before speech data or elsewhere in the program code as follows FIRK COEFFS
102. required CPU clock frequency for the C614 is 8 MHz over the entire Vpp range This rate applies to the speed of the core processor Higher CPU clock frequencies may be achieved but these are not qualified over the complete range of supply voltages in the guaranteed specification Figure 2 9 PLL Performance Oscillator Reference 32 kHz Resistor crystal Trimmed 2r referenced TIMER2 Selection Made in ClkSpdCtrl TMER2 TIMER2 Timer Source Option Selected in IntGenCtrl PLL Phase Locked Loop circuit Multiplier Adjusted in ClkSpdCtrl X1 x 256 Master Clock Runs Periphery 131 07 kHz 33 554 MHz CPU Clock Core Processor Speed 65 536 kHz FMAX FMAX 8 MHz 2 9 3 Clock Speed Control Register The ClkSpdCtrl is a 16 bit memory mapped register located at address Ox3D The reference oscillator RTO or CRO is selected by setting one of the two control bits located at bits 8 and 9 Setting bit 8 configures the C614 forthe RTO reference option and simultaneously starts that oscillator Setting bit 9 configures the C614 for the CRO reference option and simultaneously pulses the crystal which starts that oscillator 2 30 Clock Control Note ClkSpdCirl Bits 8 and 9 When bit 8 is set in the ClkSpdCtrl register the crystal oscillator bit bit 9 be comes the least significant bit ofthe 6 bit resistor trim value Thus bits 15 11 and 9 make up the 6 bit resistor trim value For example if the ClkSpdCtrl
103. result in destination accumulator string or its offset Each accumulator is shifted individually The shifted bit is propagated through consecutive accumulators in the string Example 4 14 67 1 SHLACS Al A1 Shift accumulator string A1 one bit to the left store the result in accumulator string A1 Note that this instruction alters the content of all accumulators in the string 4 162 Individual Instruction Descriptions 4 14 68 SHLAPL Shift Left with Accumulate Syntax label name T dest src mod Clock clk With RPT clk emar ne weee Tegas 1b SHLAPL TAL An next A Execution premodify AP if mod specified PH PL src lt lt SV dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode meme 10 11110110 0100 314 14 I8 T4 T 52 EL MN oo UE Co HET e ma dma16 for direct or offset16 long relative see section 4 13 ES SHLAPL AL An p neta 53 t1 o o nexta An s s tpojryo A a bonus ar the accumulator pointer if specified Shift accumulator word or data memory word pointed by ads to left nsy bits as specified by the SV register into a 32 bit result This result is zero filled on the right and either zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the product high PH re
104. result int strl int str2 int lg cmm func mul string int result int strl int mult int lgl int lgr cmm func umul string int result int strl unsigned int mult int lgl int lgr cmm func or string int result int strl int str2 int 19g cmm func and string int result int strl int str2 int 19g cmm func xor string int result int strl int str2 int 19g cmm func not string int result int strl int 19g cmm func neg string int result int strl int 19g cmm func copy string int output int input int 19g cmm func rshift string int output int input int rshift int lg ifdef CMM cmm func strcpy char outstring char instring cmm func strlen char instring cmm func calloc int nitems int size cmm func malloc int size cmm func free int ptr endif cmm func test string int stringl int string2 int lg int oper cmm func xfer const int out int cst addr int 19g cmm func xfer single int out int cst addr ROKK IK KK Sk kc kk kk AA Note the requirement that C function declarations including main of course be preceded by the keyword cmm func Also note the conditional assembly portion used for compatibility with Borland C RRR A ke ke ke e ke e e e x e x e x Macros for C ck Cckckockockckckc ck ck kck kc kk define STR_LENGTH i i 2 CRRA ERE ESE Major Differences between C and C Although we have tried to keep the differences b
105. resulting product product low is multiplexed to the ALU Product low is either loaded to or arithmetically combined with an accumulator register These steps are performed within the same instruction cycle Refer to Figure 2 3 Atthe end ofthe current execution cycle the upper word MSB of the product is latched into the product high register PH MSP50C614 Architecture 2 5 Computation Unit 2 6 The multiplicand source can be either data memory an accumulator or an accumulator offset The multiplier source can be either the 16 bit multiplier register MR or the 4 bit shift value SV register For all multiply operations the MR register stores the multiplier operand For barrel shift instructions the multiplier operand is a 4 to 16 bit value that is decoded from the 4 bit shift value register SV Refer to Figure 2 4 As an example of a barrel shift operation a coded value of 0x7 in the SV register results in a multiplier operand of 0000000010000000 1 at bit 7 This causes a left shift 7 times on the 16 bit multiplicand The output result is 32 bit On the other hand if the status bit FM multiplier shift mode is SET then the multiplier operand 0000000010000000 is left shifted once to form a 17 significant bit operand 00000000100000000 This mode is included to avoid a divide by 2 of the product when interpreting the input operands as signed binary fractions The multiplier shift mode status bit is located in the status r
106. source for TIMER2 Setting bit 9 selects the reference oscillator as the source for TIM ER2 The default value after a RESET LOW is zero select 1 2 MC as the source Each of the TIMERs counts from the value stored in its period register to 0x0000 These maximum and minimum counts each receive a full clock cycle from the TIMER source This means that the true period of the TIMER from one underflow event to the next is the value stored in the period register plus one Time duration btwn underflows value in PRD 1 frequency of Timer Source TIMER1 and TIMER2 must be enabled for use This is done at the IntGenCtrl register Bit 10 of the IntGenCtrl is the enable bit for TIMER1 and bit 11 is the enable bit for TIMER2 Setting the enable bit enables the TIMER i e starts count down running Clearing the enable bit disables the TIMER i e stops the count down The default setting after a RESET LOW is zero both TIMERs disabled Refer to Section 3 4 Interrupt General Control Register for sum mary information regarding the IntGenCtrl The TIMER enable bits may be used to start and stop the TIMERs repeatedly in software Switching the enable bit from 1 to O stops the TIMER but the current value in the count down register is retained When the enable bit is subsequently switched from 0 to 1 count down then resumes from the held value The following procedure outlines one of many possible ways to start the TIMERs TIMER2 is given a
107. status is modified adrs Transfer status is modified modification of status modified in adrs The upper 10 bits are zero filled Transfer status is modified MOV aars MR Store the contents of the multiplier MR register in adrs Transfer status is modified o 4 36 Reserved 0111011 MOV aadrs DP Store the data pointer DP register contents to the location referred by adrs Transfer status is modified Instruction Classification Table 4 27 Class 5 Instruction Description Continued e ed MOV aars TOS Store the contents of the top of stack TOS register to the data memory location referred by addressing mode adrs Transfer status is modified 1 STAG aars Store 1 to the 17th bit of data memory location referred by adrs Set the tag bit 1 0 RTAG aars Store 0 to the 17th bit of data memory location referred by adrs Clear the tag bit MOVT aars TFn Store TF1 bit if n 1 TF2 bit if n 0 status bit to 17th bit of data memory location referred by addressing mode adrs 1 MOV SV adrs 4 Load shift value SV register with contents of the location referred by ad dressing mode aars Transfer status is modified 0 MOV PH aars Load Product High PH register with content of data memory location value referred by addressing mode adrs Transfer is status modified MOV TOS adrs Load top of stack TOS register with content of data memory location refe
108. the multiplier multiplicand to the 17 bit This causes signed multiplication of two signed numbers STAT XM 0 suppresses sign extension Unsigned none none STAT UM 1 causes unsigned multiplication where the mul tiplier assumes its arguments as unsigned value MOVU instruction can be used to enable this mode STAT UM 0 disables unsigned multiplication SOVM ROVM STAT OM 1 initiates overflow mode Overflows cause the accumulator to acquired the most positive or most negative value In the case of string values only the MSB 16 bits are modified The remaining bits in the string are unchanged overflow operation and the accumulator content is unchanged if any overflow occurs Affects OF bit of STAT in case of overflow SFM RFM STAT FM 1 enables fractional multiplication shift mode The multiplier is shifted left 1 bitto produce a 17 bit operand This mode is used on signed binary fractions and does not require the user to left shift as it would have been required if the FM bit was not set STAT FM 1 turns off fractional mode Overflow Fractional 4 50 MSP50P614 MSP50C614 Computational Modes Setting Resetting Function Instruction Instruction STAT OM 0 normal Sign Extension Mode Sign extension mode can be enabled disabled by setting resetting the XM bit of STAT When in sign extension mode a multiply operation will copy the 16th bit of the multiplier multiplicand to the 17th bit When multiplied this will
109. this port address by 4 Product high register 16 bits Product low register 16 bits cannot be read written directly Rx register treated as a general purpose register This bit is not related to any addressing mode Register carry flag Indirect register x where x 0 7 Register zero flag Represents string mode if 1 otherwise normal mode Sign flag Status register 17 bits String register 8 bits Shift value register 4 bits Memory tag Test flag 1 Test flag 2 Top of stack register 16 bits Unsigned mode Word s taken by instruction Don t care Extended sign mode Transfer TX sign flag Transfer TX zero flag Zero flag Legend Table 4 45 Auto Increment and Decrement Operation No modification 0 0 Auto increment A 0 1 Auto Decrement A 1 0 Stringt Relative Repeat locks Words Addressing E Operation Modes clk W Clocks Be o e pem O O ACA Short relative EHE R6 offset7 E offset7 oe E 0 O E Long relative Long relative om ng Rx Rx offsett Rx offsett Indirect ng 2 EL t Replace ng with ng for string operation Note dma16 and offset16 is the second word Table 4 47 Flag Addressing Syntax and Bits flagadrs flag addressing mode encoding flagadrs Flag Repeat alli Ent Litt Addressing Clocks ords Operation Syntax Modes Go AO O foe fe T np is RPT instruction argument clk flag address bits Ass
110. used in various addressing modes or as general purpose registers RO R1 R2 and R3 can be usedsolely as general purpose registers These registers can also be used as indirect registers with relative addressing The R4 or LOOP register is used with instructions BEGLOOP and ENDLOOP to define a hardware controlled loop If R4 is loaded with a value n Ox n lt 32767 the BEGLOOP and ENDLOOP block will be executed n 2times The loop stops when R4 becomes negative The R5 or INDEX register is used with indirect addressing and relative addres sing modes of certain instructions The R6 or PAGE register is used with page relative addressing and relative flag addressing The R7 or STACK register holds the pointer to the stack It can be used as a general purpose register as long as no CALL RET instructions are used before restoring it with its old value However this register can only be used as ageneral purpose register when maskable interrupts are disabled The old Assembly Language Instructions 4 5 System Registers value of the STACK register should be stored before use and restored after use This register must point to the beginning of the stack in the RESET initialization routine before any CALL instruction or maskable interrupts can be used CALL instructions increment R7 by 2 RET instructions decrement R7 by 2 The stack in MSP50P614 MSP50C614 is positively incremented 4 2 11 String Register STR The string register STR h
111. utive addresses o _ _ gt gt _ _o V i iG G B NOTE Data Memory Access Data memory access RAM is always accessed with byte addresses Pro gram memory ROM is accessed with 17 bit words Rx registers autoincre ment or autodecrement by 1 for byte addressing by 2 for word addressing or by the length of the string in bytes if Rx or Rx is used Word and Word string addresses One data memory word is composed of two consecutive bytes A word address is always an even byte address and the least significant bit of the byte address is assumed to be zero Instructions that operate on words have internal hardware which increments the byte ad dress appropriately to load the two consecutive bytes in one clock cycle To use an absolute word address the address should be multiplied by 2 A word string is a string of consecutive words Like a byte string word strings use the STR register to define the string length Word strings always start at an even byte address When string instructions are used words are fetched from the first word string memory location to consecutive addresses The word address is the data memory address in bytes This is obtained by multiplying the byte address by two Figure 4 3 Data Memory Organization and Addressing Global flags Relative flags Data memory 1 Word Data memory Flag address even address odd address
112. value 1 x 131 07 kHz CPU Clock frequency kHz PLLM register value 1 x 65 536 kHz The configuration of bits in the clock speed control register appears below CIkSpdCtrl register address Ox3D 16 bit wide location WRITE only 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 T5 T4 T3 T2 Ti ICO0oTOR M M M M M M M M T RTO oscillator Trim adjust R enable Resistor trimmed oscillator Idle State clock Control M PLLM multiplier bits for MC C enable Crystal oscillator 0x0000 default state after RESET LOW or TO if R is set MSP50C614 Architecture 2 31 Clock Control Bit 10 in the ClkSpdCirl is idle state clock control The level of deep sleep generated by the IDLE instruction is partially controlled by this bit When this bit is cleared default setting the CPU Clock is stopped during the sleep but the MC remains running When the idle state clock control bit is set both the CPU clock and the MC are stopped during sleep Refer to section 2 12 for more information regarding the C614 s reduced power modes p BB B B B B B mw iii si A Note Reference Oscillator Stopped by Programmed Disable If the reference oscillator is stopped by a programmed disable then on re enable the oscillator requires some time to restart and resume its correct fre quency This time imposes a delay on the core processor resuming full speed operation The time delay required for the CRO to start is GREATER than the time delay requi
113. w is pushed onto the top of stack TOS and the second word operand or accumulator value is loaded into the PC Call instructions cannot immedi ately followed by RET instructions No restrictions apply if IRET is used instead of RET CALL pma16 Unconditional call to specified program memory address pma16 CALL An Call to address referenced by An See Also Ccc VCALL RET IRET Example 4 14 8 1 CALL 0x2010 Call unconditionally program memory address 0x2010 Example 4 14 8 2 CALL A0 Call unconditionally program memory address stored in accumulator AO Assembly Language Instructions 4 85 Individual Instruction Descriptions 4 14 9 Ccc Conditional Subroutine Call Syntax Taba rame ases Gic c Word win x ene jest jos j e l2 lw l1 t Cannot immediately follow a CALL instruction with a return instruction If true If Not true label CZ pma16 label CNZ pma16 label CS pma16 label CNS pma16 label CC pma16 label CNC pma16 label CG pma16 label CNG pma16 label CE pma16 label CNE pma16 label CA pma16 label CNA pma16 label CB pma16 label CNB pma16 label CO pma16 label CNO pma16 label CRC pma16 label CRNC pma16 label CRE pma16 label CRNE pma16 label CL pma16 label CNL pma16 label CTF1 pma16 label CNTF1 pma16 label CTF2 pma16 label CNTF2 pma16 label CTAG pma16 label CNTAG pma16 label CIN1 pma16 label CNIN1 pma16 label CIN2 pma16 label
114. when both are used Exceptions to the rule are the instructions NEGAC S NOTAC S MULSPL S MULAPL S MULTPL S SHLSPL S SHLTPL S and SHLAPL S which use the reverse A control A 1 for accumulator A 0 for offset accumulator The A bit in the instruction word controls the destination of the result to be the accumulator A 0 or the offset accumulator A 1 In addition to basic accumulator arithmetic functions this class also includes an accumulator lookup instruction and several register transfer instructions Instruction Classification between the accumulator and the MR SV or PH register As with all accumula tor referenced instructions string operations are possible as well as premodi fication of one of 4 indirectly referenced accumulator pointer registers AP Table 4 19 Class 3 Instruction Encoding R CHENENENERERR aL Table 4 20 Class 3 Instruction Description INN CN CN NEGAC An An next A Store the 2 s complement of the source accumulator NEGACS An An A 0 or 1 to the destination accumulator A 0 or 1 ALU status is modified NOTAC An An next A Place the 1 s complement of the source accumulator NOTACS An An A 0 or 1 into the destination accumulator A 0 or 1 ALU status is modified MOV Arf An next A Look up a value in program memory addressed by MOVS Ap An accumulator A 0 or 1 Place the lookup value into the accumulator A 0 or 1
115. will trigger the INT5 event If any F port pin is continuously held low and another is toggled high to low no interrupt is detected at the toggling pin After all F port pins have been brought high again then it is possible for a new INT5 trigger to occur INTOisaninternal interrupt highest priority which is triggered by an underflow condition on the DAC Timer see Section 3 2 2 DAC Control and Data VO Registers INT1 and INT2 are high priority internal interrupts triggered by the underflow conditions on TIMER1 and TIMER2 respectively Please refer to Section 2 8 Timer Registers for a full description of the TIMER controls and their underflow conditions When properly enabled any of these interrupts may be used to wake the de vice up from a reduced power state In a deep sleep state they can also be used to wake the device when used in conjunction with the ARM bit Please refer to Section 2 11 Reduced Power Modes for information regarding the C614 s reduced power modes A summary of the interrupts is given in Table 3 1 Table 3 1 Interrupts Interrupt INTO INT1 INT2 INT3 INT4 INT5 INT6t INT7T Vector Ox7FFO Ox7FF1 Ox7FF2 Ox7FF3 Ox7FF4 Ox7FF5 Ox7FF6 Ox7FF7 Source Trigger Event Priority Comment DAC Timer Timer underflow Highest Used to synch speech data TIMER1 Timer underflow 2nd TIMER2 Timer underflow 3rd PDo Rising edge 4th Port D goes high PD3 Falling edge 5th Port D3 goes low
116. with limited addressability such as memory transfers can still access these registers Note Reading the Data Register Whether configured as input or as output reading the data register reads the actual state of the pin LLLLLS S S OMM 3A The programmable lO are initialized to a known state by cycling the RESET pin low to high The state of the control registers during and after RESET low VO is 0x00 all inputs The state of the data registers after RESET low is unknown input state provided by external hardware The 8 bit width is the true size of the mapped location This is independent of the address spacing which is greater than 8 bits When writing to any of the locations in the I O address map therefore the bit masking need only extend across 8 bits Within a 16 bit accumulator the desired bits should be right justified When reading from these locations to a 16 bit accumulator the IN instruction automatically clears the extra bits in excess of 8 The desired bits in the result will be right justified within the accumulator The following table shows the bit locations of the I O port mapping 8 bit wide location 07 06 05 04 03 02 01 00 A port control register address 0x04 Cc cec GC C C B port data register address 0x08 B7 Be B5 B4 B3 B2 Bi BO B port control register address 0x0C C GC CG CGC C C C C C port data re
117. wu CPU Window Accumulators Registers i00 0000 10 0000 RO 0000 o000 xN 0 A i01 0000 1i 0000 Ri 0000 0000 UM O i02 0000 12 0000 R2 0000 OOOOJOM O i03 0000 13 0000 R3 0000 onn O i04 0000 14 0000 R4 0000 0000 IM O i05 0000 15 0000 RS 0000 0000 XzF O 06 0000 16 0000 R6 0000 QQQQ ZSF O i07 0000 17 0000 R7 0000 0000 RCF O i08 0000 18 0000 PC 0000 RZF 0 E 0000 19 0000 STAT 0000 oF 0 OA OOOO 12 0000 SY 0000 SF 0 OB 0000 iB 0000 MR 0000 ZF 0 ioc 0000 ic 0000 PH 0000 CF 0 OD 0000 1D 0000 m DP 0003 TF1 0 DE 0000 1E 0000 STR 0000 TF2 0 OF 0000 1F 0000 Tos 0000 AG O APO O0 P1 00 aP200 AP300 CLK 000000000 STK O CUR Stop Internal or Emulation CPU Window Displays values in all MSP50P614 MSP50C614 system registers and some additional information Editing a register value is similar to editing a data memory value in RAM Window The first two columns have registers labeled 00h to 1Fh the 16 bit accumulators RO to R7 indicates indirect register values Values in parenthesis indicates the values pointed by the register using indirect addressing This value is displayed only when valid data memory address in present in the register The fourth columnis all status register STAT bits APO to AP3 are accumulator pointers 5 bits of which is active CLK field is the clocks taken The emulator keeps track of the number of cycles used This counter can be reset by using the Init All or I
118. 000 0003 mov AP2 0 LII d AAA LAN EBSCO 0005 mov STR 32 2 string siz 0000 0010006 zacs A0 ACO AC31 0008 DOC 0007 mov 0 a0 7 0 0 0010 OOF if RAM CLEAR fig 7 zero xL 018 OOF zero entire RAM data t tl a gt gt Ez Inspect Window gl x Ez Project Window lol xl C XC615DEUXPCHXPCH RP J C XC615DEUXPCHNINIT ASH C XC615DEUXPCHXCONTROL IRX C XC615DEUXPCHXIO PORTS IRX LI gt 4 XX OF AER Moe AKA Anka Find Next Software Breakpoint 5 16 Software Emulator Figure 5 17 RAM Window Ex MSP50C6xx Code Development Tool EMU PCM RPJ stopped ME E3 File Options Project Debug Init Window Help 4 Yellow background TAG 1 uu Ki QE le r 2300 EE MEI ee 7 EMS I tra EVE RAM Window Word Address Byte Address LAh 34h PIE asterisk value in Watch h 0000h 0000 0000 6800 0000 0000 1 uu hj 1232 1230 0000 0000 DEDO hj 0000 0000 0000 pong 0000 hj 0000 0000 ADCZ 0000 0000 45EF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1 0000 0000 0000 0000 0000 0000 0000 00 o000 0000 0000 DUDO 0000 0080 ih h ih h IN KA Loc O 0 O 0 O 0 O 0 O 0 O OOO OOO O OOO O L c OOOO OOO OOOO n bh ob CO CO E OO1Ah 0034h ADC2 0O21h 0042h 45EF _ K d o format hex address byte address Build Project RAM Window Displays 16 bit data memory hex
119. 0C614 Computational Modes Example 4 5 10 MOV STR O SFLAG 0x00032 MOVS AO 0x0031 2 RFLAG 0x00032 MOVS AO 0x0031 2 Refer to Figure 4 4 for this example This example is to illustrate the effect of the tag flag bit when used with a string instruction The string register STR is loaded with 0 string length of 2 The second instruction sets the flag bit to 1 at flag address 0x0032 The next instruction reads the word string at word memory location 0x0031 into AO and also sets the TAG bit of STAT to 1 corre sponding to the last memory location of the string which is word address 0x0032 in this case The next two instructions verify this by setting the flag to zero and reading the memory string again 4 6 MSP50P614 MSP50C614 Computational Modes MSP50P614 MSP50C614 has the following computational modes which are the first 4 bits of the status register Y Sign extension mode bit O or XM bit of STAT Unsigned mode bit 1 or UM bit of STAT I Overflow mode bit 2 or OM bit of STAT Fractional mode bit 3 or FM bit of STAT These modes can be set by setting the appropriate status register bits or by special instructions Class 9 as shown in Table 4 41 Assembly Language Instructions 4 49 MSP50P614 MSP50C614 Computational Modes Table 441 Computational Mode Sign extension SXM RXM STAT XM 1 produces sign extension on data as it is passed into accumulators This mode copies the 16th bit of the data in
120. 1 must increment R1 mov RO startOfBuff RO points to start of circular buffer mov APO 0 set up room for the mov STR O 32 bit output sample ACO and AC1 Zacs AO STR should be 1 for COR CORK instructions mov STAT filterSTAT_tag load STAT with last filter tag status rpt N 2 fir AO RO Do one sample gt 32 bit result mov filterSTAT tag STAT save STAT with last filter tag status RO now points to the last oldest sample movs ySampleOut AO0 FIR outputs bits 0 15 in ACO 16 32 in AC1 Special Filter Instructions mov A0 nextSample Replace last sample with newest sample mov R0 A0 and update the start of the mov startOfBuff RO0 circular buffer to here RO First the overflow mode must be reset Next R5 must be loaded with the wrap around value of the circular buffer Wrap around happens automatically This tells the processor how many words to step back when the end of the circular buffer is reached This value must be negative and equal to N words even though the buffer is N 1 words long For example suppose a four word circular buffer starts at RAM location 0x0100 and ends at 0x0106 N 3 In order to wrap around from location 0x0106 back to location 0x0100 the value 0x006 must be subtracted from 0x0106 giving 0x0100 TAGGED LOCATION Go back N words to wrap around RO must point to the current starting point of the circular buffer R1 must point to the filter coefficients The MR registe
121. 1 Flags Affected None Opcode msme ons Pro Pis fra H3 12 HD tro o fs v e 8 fats 2 1 fo RPT facrstg Lt Tt fod tt Poe ts fof ems gt aer imm tt tt Tt tt ts st fofotoy mms Description Loads src value to repeat counter Execute nextinstruction srcvalue 2 times Interrupts are queued during RPT instruction Queued interrupts are serviced after execution completes RPT aadrs g Load data memory byte to repeat counter repeat next instruction RPT imm8 Load immediate byte to repeat counter repeat next instruction See Also BEGLOOP ENDLOOP Example 4 14 60 1 RPT 0x0100 2 MOV R1 AO A Loads the repeat counter with value stored in word data memory location 0x0100 Only 8 bits of data from this location are used The next instruction stores content of AO to data memory address pointed by R1 Since R1 postincrements and AO preincrements in this instruction the overall effect of executing this instruction with RPT is to store accumulator contents to consecutive data memory locations See MOV instruction for detail of various syntax of MOV instruction Example 4 14 60 2 RPT 200 NOP Repeat the NOP instruction 202 times provided the next instruction is repeatable This causes 203 instruction cycle delay including 1 cycle for the RPT instruction Assembly Language Instructions 4 155 Individual Instruction Descriptions 4 14 61 RTAG Reset Tag Syntax iae rame ss Geek ok wora w W
122. 14 pma16 x 32767 for MSP50P614 MSP50C614 Invert the bit of the source Used with flag addressing only Accumulator selector where n 0 3 Anis the accumulator pointed by APn Offset accumulator selector where n 0 3 Anis the accumulator pointed by APn 16 APn wraps after 31 CC cc CF clk ama n DP flagadrs flg flagadrs FM g r IM imm n k0 kn MR next A Not N R Legend Meaning Select offset accumulator as the source if this bit is 1 Used in opcode encoding only Select offset accumulator as the destination accumulator if this bit is 1 Used in opcode encod ing only Select offset accumulator as the source if this bit is O Used in opcode encoding only Can be either A or A based on opcode or instruction Used in Opcode encoding only Can be either An or An where n 0 3 Accumulator Pointer register where n 0 3 Low order 5 bits select one of 32 accumulators Addressing mode bits am Rx pm See Table 4 46 Addressing mode which must be provided It should be of the format shown in Table 4 46 The curly braces are not included in the actual instruction The subscript n represents the data size in bits the instruction will use For example adrs g means that the instruction will use 8 bit data from the addressed memory and the upper bits may not be used If n is not provided data width is 16 bits Condition code bits used with conditional branch calls and test flag bit in
123. 16 bit value OXFF20 and the result is stored in AC1 Final result APO 1 AC1 OXFF20 AND AC17 OxFF20 AND 0x0112 0x0100 Assembly Language Instructions 4 13 Instruction Syntax and Addressing Modes 4 3 4 Direct Addressing 4 14 Direct addressing always requires two instruction words The second word operand is used directly as the memory address The memory operand may be a label or an expression Syntax name dest src dma16 2 next A name dma16 2 src next A Note the multiplication by 2 with the data memory address This only needs to be done for word addresses i e the address that points to 16 bit words This is not required for byte addresses This is explained in detail in section 4 5 Example 4 3 5 MOV A2 0x022A 2 Refer to the initial processor state in Table 4 8 before execution of this instruc tion Loads the contents of data memory location 0x022A 20x0400 to A2 or AC11 The MSP50P614 MSP50C614 always accesses data memory as byte addresses To read a word address multiply the address by 2 Final result A2 AC11 0x0400 Example 4 3 6 MOV Al 0xO1F2 2 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Preincrement AP1 After preincrement A1 is AC22 and A1 is AC6 The content of data memory location 0x01F2 0x12AC is then loaded to accumu lator AC22 offset of AC6 Final result AP1 22 AC6 0x12AC Example 4 3 7 SUB A
124. 2048 x 17 bit 640 x 17 bit 0x 027F reserved 0x07FF 0x0800 User ROM 30704 x 17 bit C604 read only P614 EPROM Ox7F00 Macro Call Vectors 255 x 17 bit overlaps interrupt vector locations EXPO Usable Interrupt Vectors Ox7FF7 8 x 17 bit Ox7FF8 Unusable Interrupt Vectors reserved Ox7FFE Ox7FFF RESET vector B 6 Peripheral Ports Ox 10 PC data Ox 14 PCo 7 ctrl Ox 18 PD data Ox 1C PD ctrl 0x 2C Ox 2F RTRIM Ox 30 DAC data Ox 34 DAC ctrl Ox 38 IntGenCtrl Ox 39 0x 3A 0x 3B TIM1 Ox 3D ClkSpdCirl Ox 3E Ox 3F TIM2 Architecture B 3 7 Interrupts Interrupts for MSP50C604 are the same as MSP50C614 in host mode except INT5 port F interrupt is not available But in slave mode INT3 and INT4 are external interrupts triggered by write sequence and read sequence as ex plained before A summary of the interrupts is given below Vector Condition Priority Host Mode 7FFOh DAC Timer Timer underflow Highest DAC interrupt 7FFih TIMER1 Timerundertow 2nd Timer1 underflow 7FF2h TIMER2 Timer undertow 3rd Timer 2 underflow 7FF4h Port D3 Falling edge 5th Port D3 goes low 7FF5h Port F Falling edge 6th Reserved not used 7FF6h PortD4 Risingedge 7th Port D4 goes hight 7FF7h l pont DR Fallingedge Lowest Port D5 goes lowt T INT6 and INT7 may be associated with the comparator function if the comparator enable bit has been set See the section en
125. 3 R5 Load the contents of the byte address created by adding R3 and R5 to the MR register At the same time add accumulator AO to the PH register and store the result in AO 4 120 Individual Instruction Descriptions 4 14 30 MOVAPHS Move With Adding PH Syntax MOVAPHS An MR aars Table 4 46 Table 4 46 Execution An amp An PH MR lt contents of adrs PC lt lt PC W Flags Affected TAG OF SF ZF CF are set accordingly Opcode Instructions re rs rera 12 11 o o jo v e sajoja Jo UN ae NN dma16 for direct or offset16 long relative see section 4 13 Description Move RAM word to MR add PH to second word in Anstring Certain restriction applies to the use of this instruction when interrupts are occuring on the background See section 4 8 for more details See Also MOVAPH MOVTPH MOVTPHS MOVSPH MOVSPHS Example 4 14 35 1 MOVAPHS A0 MR R3 R5 Load the content of byte address created by adding R3 and R5 to MR register At the same time add second word in accumulator string AO to PH register store result in AO string Assembly Language Instructions 4 121 Individual Instruction Descriptions 4 14 31 MOVB Move Byte From Source to Destination Syntax Jabot name dest T ok With RPT ok MOVB An aars Table 4 46 Table 4 46 MOVB aars An Table 4 46 Table 4 46 L JA JO a a move Jm mme o a move fanme HH HHH Ta Execution dest src PC PC W Flags Affect
126. 4 29 Class 6a Instruction Description C6a Mnemonic Description 0 IN adrs port4 Transfer a 16 bit value of addressed port to data memory location referred by addressing mode adrs Refer to port address map Transfer status is modified 1 OUT port4 adrs Transfer a 16 bit value in the data memory location referred by addressing mode aars to addressed port Refer to Port address map Transfer is sta tus modified 4 38 Instruction Classification Table 4 30 Class 6b Instruction Description C6b Mnemonic Description 0 IN An port6 Transfer the port s 16 bit value to an accumulator Port addresses 0 63 INS An port6 are valid ALU status is modified 1 OUT port6 An Transfer a 16 bit accumulator value to the addressed port Port address OUTS port6 An es 0 63 are valid Transfer status is modified 4 4 7 Class 7 Instructions Program Control This class of instructions provides the logical program control of conditional branches jumps and calls subroutines Both branch and call instructions require a 32 bit instruction word The first word contains the opcode and condition fields and the second word contains the destination address The condition field can specify the true Not 0 or false Not 1 condition of 22 different status conditions The status bits that es tablish the conditions are latched and remain unchanged until another instruc tion that affects them is executed In addition to call a macro ca
127. 4a Instruction Description 0 III 4 35 Class 4b Instruction Description e ee III 4 35 Class 4c Instruction Description se ssaa raam iaia mi KARR 0 9 a eee eee 4 35 4 25 4 26 4 27 4 28 4 29 4 30 4 31 4 32 4 33 4 34 4 35 4 36 4 37 4 38 4 39 4 40 4 41 4 42 4 43 4 44 4 45 4 46 4 47 4 48 5 1 7 1 B 1 Tables Class 4d Instruction Description annii nrn R RCR 9 0 6 R II 4 35 Class 5 Instruction Encoding oooccccococccccnc eh 4 36 Class 5 Instruction Description 0 00 c cece TR a N a R eai a eens 4 36 Class 6a Instruction Encoding or 4 38 Class 6a Instruction Description 00 c arer an Tek eet eens 4 38 Class 6b Instruction Description 0 00 neunana nanenane 4 39 Class 7 Instruction Encoding and Description cece eee eee eee eee 4 40 Class 8a Instruction Encoding 0000 c cece eet teen eee 4 41 Class 8a Instruction Description 0 00 ina X T nE K N 0 eee teens 4 42 Class 8b Instruction Description 0 0000 ec cece eee eens 4 42 Class 9a Instruction Encoding 0000 RR TE E KR RR T ANR R teen eee 4 43 Class 9a Instruction Description III 4 43 Class 9b Instruction Description ve xN nenii ueni N E E SR EK IIIA 4 43 Class 9c Instruction Description 0 000 cr 4 44 Class 9d Instruction Description 0 00 sauna nananana aeaaea 4 44 Data Memory Address and Data Relat
128. 50C604 device Note MSP50C604 MSP50C604 is in the Product Preview stage of development For more in formation contact your local Tl sales office o Topic Page Bslntroductionr od A ro B 2 B 2 Re atu ie aa ere Ee eis B 2 B 3 Architecture caos B 2 BAA Packaging a B 8 B 1 Introduction B 1 Introduction B 2 Features B 3 Architecture B 2 MSP50C604 is a spin off of the core processor MSP50C614 It is targeted as a slave device An external microprocessor is needed to interface with MSP50C604 in slave mode It can also be used a stand alone device if desired U U U U U U U U O O D 30k word ROM customer program memory 8 MHz uDSP core 2 lO pins can be used as a comparator 4 pins for synthesizer syncronization Host read or write interrupts core PLL clock synthesizer Resistor trimmed oscillator or 32 kHz crystal 640 word RAM PDM DAC w direct speaker drive 32 ohm 1 bit comparator with edge detection interrupt service IMPORTANT Not currently supported Serial scan port for in circuit emulation monitor test Host Mode B 14 general purpose l O pins B Can generate interrupts Slave Mode R Works as microprocessor peripheral B STROBE R W lines for host read write control B INPUTREADY OUTPUTREADY for handshake The MSP50C604 will use the 6xx device family core including breakpoint ca pability It has identical instruction sets and uses the same development tool MSP50P614 EPROM device
129. 6 for more information on the signal functions Figure 7 3 provides a cross reference between the C614 die pad numbers and the P614 s PGA package leads Figure 7 3 120 Pin Grid PGA Package Leads P614 CARAS ep Wes o vea o os vo WENN pgmpuls SYNC bottom view RESET deeree e e pepe OSCouT OSCIN 12 T Itis important to provide a separate decoupling capacitor for the Vpp Vss pair which services the DAC These pins are PGA numbers N3 and L4 respectively The relatively high current demands of the digital to analog circuitry make this a requirement Refer to section 6 1 for details roU Om mG rc g r 5 6 7 The following table provides a cross reference between the C614 die pad numbers and the P614 s PGA package leads Customer Information Fields in the ROM 7 2 Customer Information Fields in the ROM In those cases where the customer code is programmed by Texas Instruments some registration of the code release is provided within the ROM This information appears as 7 distinct fields within the ROM test area The ROM testarea extends from address 0x0000 to Ox07FF The code release information is stored in locations 0x0006 through 0x000C Assuming these addresses are not specifically read protected by the ROM security they are read accessible to the programmer The fields appear as follows MSP50C614 EPROM Test Area Customer Information Fields 16 bit wide the 17th bit is ignored Addr
130. 64 flags relative to PAGE may be addressed with this mode Table 4 6 Auto Increment and Auto Decrement Modes Operation No modification Aufto increment Auto decrement String mode Table 4 6 describes the accumulator pointer auto preincrement or predecrement syntax Not all instructions can premodify accumulator pointers The next A field is a two bit field using bits 10 and 11 of only certain classes of instructions Instructions with a next A have either a A or a A in the instruction See Table 4 6 Assembly Language Instructions 4 11 Instruction Syntax and Addressing Modes For any particular addressing mode replace the adrs with the syntax shown in Table 4 4 To encode the instruction replace the am Rx and pm bits with the bits required by the addressing mode Table 4 4 For example the instruction MOV An adrs next A indicates all of the following only partial combinations are shown MOV AQ Oxab12 n 0 aars dma16 Oxab12 MOV A1 R6 0x2f A n 1 adrs R6 0x2f offset7 Ox2f next A A MOV A2 RO R5 A n 2 adrs RO R5 x 0 next A A MOV A3 R1 0x12ef Nn 3 adrs R1 0x12ef x 1 offset16 0x12ef MOV AO R2 n 0 adrs R2 x 22 MOV A1 R3 A n 1 adrs R3 x 3 next A A MOV A2 R4 nz2 aars R4 x 4 MOV AS R7 R5 A n 3 adrs R7 R5 x 7 next A A Flag instructions ap
131. 7FF2 0x7FF4 Ox7FF6 Ox7FF1 Ox7FF3 Ox7FF5 Ox7FF7 t The port addressed write instruction OUT can be used to SET or CLEAR bits in the IFR and IMR MSP50C614 Architecture 2 25 Timer Registers In addition to being individually enabled all interrupts must be GLOBALLY enabled before any one can be serviced Whenever interrupts are globally disabled the interrupt flag register may still receive updates on pending trigger events Those trigger events however are not serviced until the next INTE instruction is encountered After an interrupt service branch it is the responsibility of the programmer to re SET the global interrupt enable using the INTE instruction 2 8 Timer Registers 2 26 The C614 contains two identical timers TIMER1 and TIMER2 Each includes a period register and a count down register The period register PRD1 or PRD2 defines the initial value for the counter and the count down register TIM1 or TIM2 does the counting When the count down register decrements to the value 0x0000 then the value currently stored in the period register is loaded to the count down register The count down register then resumes counting again from that value For each TIMER there is an interrupt trigger event associated with the TIMER s underflow condition the point of reaching 0x0000 and then re setting again When enabled the interrupt INT1 is triggered by the underflow of TIMER1 and the interrupt INT2 is triggered by the underflo
132. C D and E Eight of the pins are dedi cated as input pins with programmable pullout resistors port F These ports are identical to the similar ports in MSP50C614 see Chapter 2 and Chapter 3 for details MSP50C605 Preliminary Data A 3 Architecture Figure A 1 MSP50C605 Architecture SCAN jn Scan Interface SCANOUT Break Point SCANCLK OTP Program SYNC TEST C605 only PGM puLs P614 only DAC p DAC DAC M 32 Ohm PDM RESET Initialization Logic OSC Reference Resistor Trimmed 32 kHz nominal OSC IN OSC OUT Crystal Referenced 32 768 kHz PLL PLL Filter A 4 VSS Power Fo Y y P614 only EPROM 32k x 16 1 bit Test Area reserved User ROM 0x0000 to Ox07FF 0x0800 to Ox7FEF Ox7FFO to Ox7FFF INT vectors Instr Decoder PCU Prog Counter Unit CU Computational Unit RTOTRIM Register 0x2F TIMER1 X PRD1 TIM1 Ox3A OxSB PRD2 TIM2 OxSE OxSF DAC Data Control Control Data 0x34 0x30 Clock Control 0x3D Gen Control 0x38 Interrupt Processor FLAG MASK 0x39 0x38 Data Mem Addr TIMER2 DMAU RAM 640 x 17 bit data 0x0000 to 0x027F gt Data ROM 229 376 x 8 bit Data ROM access DRA DRP DRD C port 1 0 DATA 0x10 Control 0x14 Comparator 1 bit PD5vs PD4 D port 1 0 DATA 0x18 Control 0x1iC E port 1 0 DATA 0x20 Control 0x24 F port INPUT DATA 0x28 Figure A 2 MSP50C605 Memory Organization Program Memory 0
133. CTA ACI AIN AR e kr Mim m ow R m 7 HH HH e mre fe mr a o fs e ee E RUNS CI e menme E 2 H CI e memo Te CI EA e CIC 13 ICI II A Assembly Language Instructions 4 197 Instruction Set Summary dest src src1 mod Clock c k With RPT clk adrs An next A Table 4 46 Table 4 46 Weser eem omnes s or COCA OE Eom B for enm tp om P ur enit S ION o B wr GTI 3 o B Aera 3 p o9 p rca 3 E o T M adrs Rx Table 4 46 mm 3 i 1 MOV MOV MOV OV MOV MOV OV Bum 3 IAN adrs STR Table 4 46 Table 4 46 adrs DP Table 4 46 Table 4 46 t Signed multiplier mode resets UM bit 1 in status register to O MOV MOV MOV MOV OV 4 198 Instruction Set Summary name dest src src1 moa Clock clk With RPT clk adrs SV Table 4 46 Table 4 46 15 adrs APn Table 4 46 Table 4 46 5 E E wo jmessm FCO p sow CC wor pmmeus POC p 3 oS CC mw menm HH 3 H e ww mms 0 3 e E as man o 3 o T os man pos fwd T Flagadrs is 64 locations global or relative to R6 Co wo Assembly Language Instructions 4 199 Instruction Set Summary rome uersus TSS winner ok Sess me oma ICC E e mc paa IEC I pom CI m pa oo 99 o9 p mas em owe H mus e A P Mme LLLI m ewm p ome m9 Th fon LESS AIN p 28 18 COMINO CS CITA 31 T a gt 4 200 Instruction Set Summary pane ssar senmo ESE Words
134. E 18 OO 40 OO SoIGAMEDSTESTAEXAMFLES RPO 48 OO SpA EI OURONGO UNI REL 50 oni Figure 5 14 Project Open Dialog 4 Open File name Folders c userdata d 614dev2 16 Cancel Cy c Ey userdata EJ dev Help y tools E3 Exxtools Eq 614dev2 16 jidi Bi Network List files of type Drives C6xx Project RPJ amp c ejaz 5 14 Software Emulator Figure 5 15 File Menu Options Ez MSP50C6xx Code Development Tool EMU SHL RPJ stopped ES sss Project Genus imit Window Helm insertin project E E Ph Launch Editor Insert files into project Program File Alt F9 Teri CIMA WHR HIS Y Launch PFE text editor Exit Alt F3 Program Chip with a file Verify Chip with Program File Exit this application Build Project 5 6 2 Projects The emulator can only work from project files created within the emulator itself These files have the extension rpj and are not compatible with the rpj files used in the old simulator In other words even to assemble a single as sembly program the user has to create a project and insert the name of the assembly file in the project To create a new project Menu Project New Project then enter a project name Figure 5 14 To insert files in a project Menu File Insert Figure 5 15 or activate the project window by placing the mouse over it and hit the INS key Any window can be activated by placing the mouse
135. EF MS7 x 3 Ox7F MS10 locked 0 cport B OxFF Configure port B as output Port B is the LED s on the code development unit oport B OxFF Turn off all 4 LEDs for i20 i 4 i loop through all required inputs k iport F read port F while k OxFF wait for keypress k iport F read port F oport B k output the value from F wait 100 delay 100ms for key debouncing l iport F read port F while 1 OxFF wait for key release wait 100 delay 100ms for key debouncing l iport F read port F if x i k 4 compare to correct input locked 1 1f incorrect then lock and return return locked end for i20 i 4 i return locked If the program reaches this return then all inputs were correct and the main program can unlock cmm_func main code begins executing here after init614 asm is executed asminit configure everything cport B OxFF configure port B as output for j 0 j 1000 j semi infinite loop if lock get input and see if correct if lock 1 the input was incorrect The LED s are then flashed and the program repeats oport B 0x00 wait 100 oport B OxFF wait 100 oport B 0x00 wait 100 oport B OxFF Code Development Tools 5 65 Implementation Details wait 100 oport B 0x00 wait 100 oport B OxFF wait
136. EGACS Ar An OR An adrs OR An An imm16 next A OR Anr An An next A OR TFn flagadrs Ppbppbbbbbl 9 dma16 for direct or offset16 long relative see section 4 13 YT TS TTT TS TTS 9 x dma16 for direct or offset16 long relative see section 4 13 PPPIPDPLDPL LDbLbLDbLDIITI TD lifer ffl 9 dma16 for direct or offset16 long relative see section 4 13 rs oo roa an JoJo Jo aya HEHE HEH O HT dma16 for direct or offset16 long relative see section 4 13 HHDH YI TS far ads dma16 for direct or offset16 long relative see section 4 13 1 foo nexa an t t ojo o 0 fa a HEHEHE is an adis dma16 for direct or offset16 long relative see section 4 13 ooo i an ejs ojo ojo fa a ojojoj an An An adrs o nexta an a a Jo a a Jo Ja a ofif a alif an qao rro ae A neta An oo o loo o JA A Instruction Set Encoding Instructions ORS Ar gt An pma16 ORS Ar An a OUT port4 adrs Em dma16 for direct or offset16 long relative see section 4 13 is sa is 12 o jo fa 7 Jo 8 a s 2 t Jo ES EN ofofo EN p E arn Sd ORS Sa ORS a a meos aa CS CI CIS SFLAG pagada sw EITS SR nasa SALSPL AAA smuss ELA RFLAG flagadrs flagadrs adrs x dma16 for direct or offset16 long relative see section 4 13 ROVM RTAG adrs SFLAG flagadrs fla
137. ET in the interrupt flag register IFR The IFR is an 8 bit wide port addressed register wherein each interrupt level is represented A set bit in the IFR indicates that the interrupt is pending and waiting to be serviced A clear bit indicates that the interrupt is not currently pending The address of the IFR is 0x39 After a RESET low the IFR is left in the same state it was before Interrupt Logic the RESET low assuming there is no interruption in power For a full description of the interrupt trigger events refer to Section 3 1 5 Internal and External Interrupts 8 bit wide location 07 06 05 04 03 02 01 00 lt INT number IFR Interrupt Flag register D5 D4 PF D3 D2 T2 T1 DA address 0x39 low high priority priority port Ds falling edget PF any port F falling edge port D4 rising edget T2 TIMER2 underflow port Ds falling edge T1 TIMER underflow port Do rising edge DA DAC timer underflow A bit value 1 indicates pending interrupt waiting to be serviced RESET The IFR is left in the same state it was before RESET low assuming no interruption in power T INT6 and INT7 may be associated instead with the Comparator function if the Comparator Enable bit has been set Refer to Section 3 3 Comparator for details Individual interrupts are enabled or disabled for service by setting or clearing the respective bit in the interrupt mask register IMR 8 bits If an interrupt level has its bit cleared
138. Ed EN EE ER E DR aa AND TEN faga fo fo pepe lelel 07 9 AND TEn cd R TSTST ofa v e I ajo ANDE An imn afoje hoh m o o 7 ANDS An ads STTS TSTST TTS Tas x dma16 for direct or offset16 long relative see section 4 13 ANDS An An pma16 ANDS Anr An An CALL pma16 po fo fos vr ce Jofojolo Assembly Language Instructions 4 187 Instruction Set Encoding ass 0 0000000010000 00000 CIP An ads ppbibjbbbeli as SCs dma16 for direct or offset16 long relative see section 4 13 x CMP A immt next A fits fo fo nna an folrfofololr A i CMP An An next A BBPBPBDeLDeLDBIBPBPBIBIBI CMP Arr Ant next A pitta fo fo neta an Ht opo o o jo s Jo CMP Rx immt pitts didi ts fojofo fiji e ojo imm16 1 1 1 1 1 Mel X SI inna Ie RRC a e ee GOE E CHR am dma16 for direct or offset16 long relative see section 4 13 7 gt 3 Q y o gt 5 9 G OJO O lt l lt lt Di pr x 28 Ed E E 3 3 3 3 Go Oo CMPS An pma16 1 ZEE BES SDS gt 3 pma16 CO 00100 0101010 000010 0 0100 emps ar An isis fofo 1 an so fo ofo fo a cor anrs tt a tt fo fofo an afi fot rs fifi cork An Rx tt fa 1fof1fofol an sjoj o m fifi enpoopn tt ft it ft ft a as Jo o fo fo a jo Jo JoJo pre a E 10 E ITA E ESE EEES Jo s fs ole ofifo m fil 0 0 02000 CR ERN ER KHER ES KB EH foto E KE EUL LL dma16 for di
139. F Texas Instruments C614 Synthesis Code To continue click on the Run Internal icon again The LEDs should flash during MELP synthesis Extra extra read all about it and should flash in a different pattern after MELP synthesis Running the Program The MELP1 program can run on either the demo box orthe code development board The latter has only two switches SW1 and SW2 while the former has ten switches SW1 to SW10 four LEDs an LCD an EPROM socket and a flash card socket Upon power up the 614 should say Extra extra etc and the LEDs should flash in alternating pairs When the LED pattern becomes a rolling onethe program is sitting in a loop and scanning SW1 and SW2 Pressing SW1 launches the MELP synthesizer into 11 character phrases Pressing SW2 begins a more complex sequence of events One MELP phrase is synthesized and then the 614 goes into midsleep mode the LEDs will cease flashing This sleep mode can be exited by pressing SW1 after which another character voice will be synthesized Finally if an EPROM is plugged in and it contains MELP speech data at address 0x0000 then this data will be synthesized before the program returns to the tight keyscan loop Atany time during speech you can press one ofthe port F keys SW3 to SW10 to skip to the next phrase This feature is not available when running the code on the demo box Directory Structure melpi MEE common util obj general dsputil asm getbits asm
140. F 0 and XZF 0 Not condition XSF 0 or XZF 0 Assembly Language Instructions 4 203 0000X0 a sindino Q e 00x0 saje s indui eulajxa sayejs indui eula xa saje1s indu eulajxa sayejs 1ndui eula xa saje s indui eulajxa sayejs indu eulajxa 13538 14V Instruction Set Summay vex0 Ol Ul Od Ld ees aJeo JUOp ova HO 8 y Ha ep 0 090 14 6 4q MOJHSAO ova 19 0L S uq ufis S pe ase Oj Y L lt A Auo 1ndino yBiy xog XD Hq oo io zo eo vo so uiu X4q 1ndur L X4 4q fos taf zs es va ss indino se Xgg O q yb 4d L 41 30 0 39 so M yb Xod 1 uq Dee 39 T 97 indino se Xgq 0 10 u amp iu ad 1 g Hq uBiu Ya L Xy ya ov iv ev ev sv sv Aluo 1ndino moj XDd 0 XD 4q mo X4q Ndu 0 X4 109 o Xad 0 7 Xa xq indui se Xgd 0 lt 0 4q mo X3q 0 7 10 91NI si86Bu1 Gd Sqq pue uaru Yad oDpe usu J mo X5g 0 X9 na mol Xgq 0 a na mol Ya 0 Xy uq py Dee le lels o e e e uondiioseg HOd OI Y LIAOSASIN v L920SdSIN erea ovd Auo y L900SdSIAt INIH LOLH Ajuo 1ndino ead 9 Hod Ajuo 1ndur eq 4 uod 031002 Y uod jeuonoeuipig eq 3 uod jo3uoo uonounininui 00002 q uod jeuonoeupiq pod uonounjninui eyeq 0 uod 041002 2 HOJ Jeuonoeurpiq eed 9 uod 041002 Y HOJ euonoeurpiq eyeq a uog O1JUOD Y uod
141. F DOFF OOFF Jio OO07F OO07F OO07F Init RII F2 0 ODOF OOOF OOOF 28 DOFF OOFF OOFF OOFF OOFF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 OODS FFFF FFFF 0000 0000 FFFF FFFF O OOO OOO 1 OOO 2 e oO All except BP This menu option initializes all internal registers and all RAM locations on the chip to zero except PC which is setto start of program It also resets the cycle counter The program counter set at the value indicated by the start vector at address OXFFFF However the breakpoints if any are not reset This is the preferred initialization when a program is being debugged Code Development Tools 5 27 Software Emulator Init RAM Initializes the data memory values to zero including tag bits Init Registers Initializes all the system registers excluding accumulators to zero except PC which is initialized to start vector Init Accumulators Initializes all the accumulators to zero Init All This menu option initializes all internal registers and all RAM location in the chip It also resets the cycle counter The program counter is set at the value indicated by the start vector at address Ox7FFF 5 6 6 Emulator Options 5 28 The Software emulator has some user setup options The first four options are to setup screen fonts for CPU window RAM Window Program Window and Project Window The Verbose C menu selection can be toggled to inhibit the insertion o
142. FFF 0 0 1 YU Signed comparison of a and b a is in AO b is in AO Assembly Test Condition _ amp q a b AEQ _ne al b IAEQ t a lt b ALZ _le a lt b IAGT ge a b LAL Z _gt a gt b AGT 5 48 Implementation Details Unsigned comparison of a and b a is in AO b is in AO Assembly Test Condition ult a b AULT ule a b IAUGT uge a gt b IAULT ugt a gt b AUGT The small number of comparisons was an invitation to use them as vector calls We return a 1 or 0 in AQ as the result of the comparison and also set flag 2 if the comparison is true The flag is not currently used by the compiler It is important to note that functions return their results via AO but there is no guarantee that the absolute value of the AO pointer is not changed by the function To compare integers a and b after loading a in AO and b in AO do a vector call to the appropriate comparison routine Assembly Vector eq 0 _ne 1 It 2 _le 3 _ge 4 gt 5 ult 6 ule 7 uge 8 ugt 9 _Ineg 10 We return the result of the comparison in Flag 2 set for TRUE reset for FALSE and in AO 1 for TRUE O for FALSE We have also implemented vector calls for string comparisons There are a few C callable routines that make use of those calls test_string or_string and_string xor_string neg_string not_string Code Development Tools 5 49 Implementation Details 5 10 2 Division The integer division currently requires the use of several acc
143. HLAPLS A2 R1 Shiftthe string pointed by the byte address stored in R1 by nsy bits to the left add the shifted value PL with accumulator string the accumulator and store the result in accumulator string A2 Increment R1 by 2 PH holds the upper 16 bits of the shift Example 4 14 69 3 SHLAPLS A1 A1 Shift the accumulator string A1 by nsy bits to the left add the shifted value PL to the accumulator and store the result in accumulator string A1 After execution PH contains the upper 16 bits of the 32 bit shift 4 164 Individual Instruction Descriptions 4 14 70 SHLS Shift Left Accumulator String to Product Syntax Taba rame dest Gies ok wora w win RPT ck Grass sms jan nws 1 ms a Execution PH PL src SV PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions re ts 14 13 12 11 o o o v e a a jo 2 1 o sus arg Pi Et Tt Foto att Ao Jifrfifr fifofa ro Description Shift accumulator string value left nsy bits as specified by the SV register into a ns 2 x 16 bit result The result is zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the PH register Accumulator content is not changed The lower 16 bit value is discarded SHLS instruction can be used with RPT instructions but the string length used wi
144. J 2 wr mov s CI Lows Es wov s es 3 tr ps wo PH ads ea Tesis mo rr tar meis mess 5 wo arn aa becas Tesis 5 mov Temas tebeo mesas 5 mov rosea tables mesas 5 mov Taan oenas Tesis 5 wo fa oeae Tess 5 mov Tas star tebeo mess 5 mov Tas sra tebeo Tess 5 mov fea or exse Tess 5 mov Taa becas Tess 5 mov Tas aro eias Tesis 5 Tae Tass eiae Tess 5 Tae Tem sas tebeo mesas 5 wo vases res 3 JA mes LE mov renea 1 3 1 3 ms Tea m n Individual Instruction Descriptions Taba rae TR ok Word E Dio wow sm me 3 3 8 Ls To sima id Lv Ls Tov arr inns are Execution premodify AP if mod specified dest src PC z lt PC W Flags Affected destis An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordingly dest is adrs XSF XZF are set accordingly src is adrs TAG bit is set accordingly src is flagadrs TAG bit is set accordingly Opcode CATA 0 5 0010101000100 01001501 58 02 ao E mc or dma16 for direct or offset16 long relative see section 4 13 El mov aegea ojo olele an ae El dma16 for direct or offset16 long relative see section 4 13 S GER eiee
145. L dma16 for direct or offset16 see section 4 13 MOV aars PH fi ifofi ofo o fo adrs pove O dma16 for direct or offset16 see section 4 13 MOV adrs MR aa Jo la o slo e o adrs E dma16 for direct or offset16 see section 4 13 ES m dm EH MOV aars DP ollo lula lula adrs E dma16 for direct or offset16 long relative see section 4 13 MOV adrs SV io 1 olo oloj o adrs n eaS o dma16 for direct or offset16 long relative see section 4 13 MOV adrs APn fi Ji fofi o fo a an adrs E dma16 for direct or offset16 long relative see section 4 13 wem E T x lt o a o 5 Er lt b x k 3 gt a m o 5 lt x lt S 3 a o 5 lt x lt 3 3 a o 5 lt x lt S 3 a o 5 c lt b x o 3 a o 5 lt adrs AS x lt dma16 for direct or offset16 see section 4 13 er pe e ror por Er adis dma16 for direct or offset16 long relative see section 4 13 A 3 gt a m o 5 lt x x lt x dma16 for direct or offset16 long relative see section 4 13 meme BEIEDDDISUDD dma16 for direct or offset16 long relative see section 4 13 mne TTT Pape fe OO vmm E ol E E CC E a mov ten tear i o s povem pepe 4 116 Individual Instruction Descriptions Description Copy value of srcto dest Premodification
146. MSP50C614 Mixed Signal Processor User s Guide SPSUO14 January 2000 KA Texas Es INSTRUMENTS Se Sees IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products orto discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S
147. MSP50P614 MSP50C614 Computational Modes 0 cece eee eee ee 4 49 4 7 Hardware Loop Instructions 0 0 0 cece eens 4 53 4 8 Stnng InsU cltiohs uen ket Lek teet d tho apa s Ex Rue adler ed deed aede 4 55 4 9 Lookup INStructiOns sie retten eked career d lla end aded 4 57 4 10 Input Output Instruccions L 4 59 4 11 Special Filter Instructions arrsa 000 a 0 0 SR eens 4 59 4 12 Conditionals xotescoterrsrrtarratitartrrrrdata tarros 4 69 443 LOGON cinc id a zi a dina Ve ji 4 70 4 14 Individual Instruction Descriptions ssas I 4 74 4 15 Instruction Set Encoding lt Zs sK T Z d ST dianani KE Z Z 60 nn 4 187 4 16 Instruction Set Summary oocoocccccccco cor 4 196 Code Development Tools ss ss es sss see een nnn 5 1 bi JattogUlctloni os ih A bebe a aeie 5 2 5 2 MSP50C6xx Software Development Tool eese 5 3 5 9 Beqgulremients cia AA A A 5 4 5 4 Hardware installation e e n 5 5 5 5 Software Installation arase saas u ahaa aa araa a hran a aa D ayre a a ay d d eee eee 5 6 5 6 Software Emulator conoces ees ew dead HEU ED ies 5 13 5 6 1 The Open Screen usssssssssslsee seen 5 13 D 0 2 glo PC 5 15 5 6 3 Description of Windows lt aR R e R T R RR R a eh 5 16 5 6 4 Debugging a Program vre Kar 9 aR T N RT teen eee 5 22 5 6 5 Initializing CIP uu cce do A Ret kad s Ru deni 5 27 5 6 6 Emulator Options ue eet bia in ade eld ad eg dd 5 28 5 6 7 Emulator Online Help System
148. Note Writing to the TIM Register Writing to the TIM register causes the same value to be written to the PRD register In this case the TIM register is immediately updated and counting continues immediately from the new value o Each TIMER decrements its count down register at a fixed clock rate The rate is selectable between two existing clock sources the reference oscillator or 1 2 Master Clock The rate of the master clock MC is programmable It is determined by the value loaded to the PLL multiplier Section 2 9 3 Clock Speed Control Register The source to the TIMER is therefore one half the frequency of the programmed master clock 1 2 MC If instead the reference oscillator is selected as the source to the TIMER then the source is either a resistor trimmed oscillator RTO or a crystal oscillator CRO Both reference oscillators are designed to run at a nominal 32 kHz Refer to Section 2 9 Clock Control for more information regarding the oscillator configuration and clock programmability MSP50C614 Architecture 2 27 Timer Registers 2 28 Selection between the timer source options is made using two control bits in the interrupt general control register IntGenCtrl The IntGenCtrl is a 16 bit port addressed register at 0x38 Clearing bit 8 selects 1 2 MC as the source for TIMER1 Setting bit 8 selects the reference oscillator as the source for TIM ER1 Similarly clearing bit 9 of the IntGenCtrl selects 1 2 MC as the
149. O O O O Intel i486 or Pentium class processor Microsoft Windows 3 11 Windows 95M or Windows 98 operating system 16 MB memory 8 MB hard disk space Parallel port interface Development Requirements d d Ll Ll O MSP50C6xx Scanport Interface MSPSI MSP50C6xx software development tool Included with MSPSI Several PGA packaged MSP50P614s EPROM eraser UV light source Application board see the following note Note The user may provide their own application board but Tl has a basic applica tion board that may provide everything needed to start software develop ment This boardis called the speech EVM and was designed to support sev eral Tl speech devices by using different personality cards The user will need to use the appropriate personality card for the device that is being de veloped LLLLLL LLLL OA Hardware Installation 5 4 Hardware Installation The following steps are used to set up the hardware see Figure 5 2 1 Connectthe 18 V power supply to the MSPSI and connect the mains pins to a 120 V 60 Hz ac source 2 Connectone end of the IEEE1284 parallel cable to the MSPSI board and the other end to the PC parallel port The red power LED should be ON The yellow Emul Prog LED comes ON when entering into emulation mode or during programming The green target LED is ON if the MSPSI is connected to
150. OR src for two operands dest src OR src for three operands PC PC W Flags Affected destis An OF SF ZF CF are set accordingly dest is TF n TFn bits in STAT register are set accordingly src is adrs TAG bit is set accordingly src is flagadrs TAG bit is set accordingly Opcode Instructions Pio fas HI 18 92 11 to o jo 7 e s a p 2 9 1 fo TT rpdeljepejel e as 4 dma16 for direct or offset16 long relative see section 4 13 acatar TS o rov an o To 9 To D E lon co Aes Arena a o o loo preci Jo ES D E Ee 18 for eques o o w nalo s fo me fon menara 11 lolol lo na I Jo 7 Description Bitwise OR of src and dest Result is stored in dest If three operands are specified then logical OR src and src1 store result in dest Premodification of accumulator pointers are allowed with some operand types OR TFn flagadrs OR TFn with memory tag store result in TFn bit in STAT OR TFn cc Rx OR test condition with TFn bit in STAT register Rx must be provided if cc is one of RZP RNZP RLZP RNLZP to check if the selected Rx is zero or negative Rx should not be provided for other conditionals Assembly Language Instructions 4 145 Individual Instruction Descriptions See Also ORB ORS AND ANDS XOR XORS NOTAC NOTACS Example 4 14 51 1 OR A0 RO R5 OR accumulator AO with the value in data memory address stored in RO and store result in accumulator AO A
151. ORB NOTAC NOTACS Example 4 14 86 1 XORB A2 0x45 XOR 0x45 to accumulator A2 byte mode Upper 8 bits of A2 is unchanged Assembly Language Instructions 4 183 Individual Instruction Descriptions 4 14 86 XORS Logical XOR String Syntax label name dest src src Clock clk With RPT clk XORS An aars Table 4 46 Table 4 46 xons ani Arti amara ms wi An An Execution deste dest XOR src for two operands dest Src XOR src for three operands PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode instructions Pio fa fra fis 12 11 10 o 8 7 e js jaa ja ti o XORS An adj ploteo loli e 7 ena for arean orofserr tong lave eee secon H CTO 10010101 0 ae 0 01010 010005 EJ XORS A Yos An E t rdofolrit an fo rjo ojo o a a Description Bitwise XOR of src string and deststring Result is stored in deststring If three operands are specified then logical XOR srcstring and src string store result in dest string XORS An aars XOR data memory string to An string XORS An An pma16 XOR program memory string to An string store result in An string XORS An An An XOR An string to An string store result in An string See Also XOR XORB AND ANDS OR ORS ORB NOTAC NOTACS Example 4 14 86 1 XORS AO AO R2 XOR data memory string beginning at address in R2 to accumulator string AQ put result
152. PD5 PD6 PD7 Architecture B 3 4 Slave Mode Operation The MSP50C604 is used as a peripheral device in slave mode A microproces sor microcontroller controls the RANZ STROBE INRDY OUTRDY pins of MSP50C604 to use it as a slave processor No special programming is re quired to switchthe C604 to slave mode Slave mode is exclusively controlled by the four pins mentioned above B 3 5 Host Write Sequence MSP50C604 signals readiness to receive data by taking INRDY low Host takes R WZ low Host puts 8 bit data on port C pins PCg PC7 Host takes STROBE low On rising edge of STROBE data latched into port A INRDY goes high rising edge interrupt INT3 is activated When input latch is read INRDY goes low to restart cycle B 3 6 Host Read Sequence MSP50C604 signals readiness to receive data by taking OUTRDY low Host takes R WZ high Host takes STROBE low Data port C sets as output by MSP50C604 MSP50C604 program has already written 8 bit data into IO port C Host reads data from port pins PCg PC7 Host takes STROBE high On rising edge of STROBE OUTRDY goes high data port goes 3 state and falling edge interrupt INT4 is activated When MSP50C604 writes to the output latch OUTRDY goes low to restart cycle MSP50C604 Preliminary Data B 5 Architecture Figure B 2 MSP50C604 Memory Organization and I O ports Program Memory Data Memory 0x0000 Ox 0000 Internal Test Code RAM
153. R CORK c 32 bit accumulation for FIR FIRK 4 68 Conditionals 4 12 Conditionals STAT register bit settings ZF 1 SF 1 CF 1 ZF 0 amp CF 0 ZF 0 amp CF 1 ZF 1 amp SF 0 ZF 1 amp 0F 0 OF 1 ZF 0 amp SF 1 RCF 1 RZF 0 amp RCF 1 RZF 1 TF1 1 TF2 1 TAG 1 IN1 IN2S XZF 1 XSF 1 XZF 0 amp XSF 0 The condition bits in the status register STAT are used to modify program control through conditional branches and calls Various combinations of bits are available to provide a rich set of conditional operations These condition bits can also be used in Boolean operations to set the test flags TF1 and TF2 in the status register NOT NOTt condition Arithmetic Logic Condition Alternatet condition alternatet Condition mnemonic mnemonic mnemonic mnemonic Zero flag ZF NZF Sign flag SF NSF Carry flag CF NCF Below unsigned B NAE NB AE Above unsigned A NBE NA BE Greater signed G NLE NG LE Equal E NE Overflow flag OF NOF Less signed L NGE NL GE Rx carry flag RCF RNCF Rx above unsigned RA RNBE RNA RBE Rx equal RE RZ RNE RNZ Test flag 1 TF1 NTF1 Test flag 2 TF2 NTF2 Memory tag TAG NTAG Input line 1 IN1 NIN1 Input line 2 IN2 NIN2 Transfer zero flag XZF XNZF Transfer sign flag XSF XNSF Transfer greater signed XG XNLE XNG XLE T Alternate mnemonics are provided to help program readability They generate the same opcodes as the associated condition t Status Register STAT bit
154. R1 OV R7 0x0280 32 2 with the starting value of stack i e 0x0260 OV 0x0200 2 RO word location 0x0200 OV RO R5 OV AP2 R3 mory location stored in R3 to accumulator pointer AP2 OV R6 8 2 DP Copy data pointer DP to data memory word location pointed by R6 offset by 8 location short relative addressing Example 4 14 28 19 Copy the STR register w Example 4 14 28 20 Copy TF2 flag to the flag Example 4 14 28 21 Copy status of ZF flag in Example 4 14 28 22 OV STR 0x0200 2 ith the content of word memory location 0x0200 OV R6 0x20 TF2 bit in relative flag location R6 offset by 0x20 OV TF1 ZF STAT register to TF1 OV SV 4 2 Load SV register with a constant value 2 Example 4 14 28 23 Load accumulator pointe OV AP3 23 16 r AP3 with value 7 Assembly Language Instructions 4 119 Individual Instruction Descriptions 4 14 29 MOVAPH Move With Adding PH Syntax MOVAPH An MR aars Table 4 46 Table 4 46 Execution An amp An PH MR lt contents of adrs PC PC L W Flags Affected TAG OF SF ZF CF are set accordingly Opcode Instructions Pi 5 14 13 12 11 10 o jo v Je sa aja ro NN lo DIETE E RE Rm dma16 for direct or offset16 long relative see section 4 13 Description Move RAM word to MR register add PH to An in parallel See Also MOVAPHS MOVTPH MOVTPHS MOVSPH MOVSPHS Example 4 14 34 1 MOVAPH A0 MR R
155. R3 R5 Refer to the initial processor state in Table 4 8 before execution of this instruc tion AO is accumulator AC2 The contents of the data memory byte location pointed to by R3 R5 is ANDed with AC2 The result is stored in AC2 The val ues in R3 and R5 are unchanged Final result AC2 AC2 AND 0x01F2 0x13F0 AND 0x12AC 0x12A0 Example 4 3 18 MOV R2 R5 A2 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Preincrement AP2 After preincrement A2 is AC12 and A2 is AC28 Store AC28 in the data memory byte location R2 R5 The values in R2 and R5 are unchanged Final result Ox02A1 0x11A2 Example 4 3 19 ADD AO AO R4 R5 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Predecrement APO After predecrement AO is AC1 and AO is AC17 Add AC1 to the contents of byte location R4 R5 and put the result in AC17 The values in R4 and R5 are unchanged Final result AC17 AC1 R4 R5 0x0007 0x0002 0x0007 0x499A 0x49A1 4 3 6 2 Short Relative Short relative also called PAGE Relative addressing selects the Page register R6 as a base value and adds a 7 bit positive offset from the operand The page register is not modified Syntax name dest src R6 offset7 next A name R6 offset7 src next A R6 PAGE register 7 Bit positive offset Assembly Language Instructions 4 17 Instruction Syntax and
156. RERERERLAE REE RL RE RE RE RARE REE RARER EEE RARE EER ERR RE RE EE RRS EEEE movb a0 0x02 choose 10 bit DAC C3x style orb a0 DACON enable DAC out DACCTRL a0 switch DAC on PRR RRR RRR RRR RAR RE kk KKK KK RK KR kc kk ke kk ke kc kk kk koc ke kk ke kc ko koc kc kk ke kk ke ck koc EK KKK KK Initialization complete Now tidy up and branch to the main user code PRERERERERAR Koo oko RENE EERE RE EERE ERE A saos RARE RAR zac a0 tidy up zac a0 jmp _main jump to the main program Applications 6 7 Texas Instruments C614 Synthesis Code 6 3 Texas Instruments C614 Synthesis Code 6 8 Some sample codes are supplied with the development tools These samples are in the Examples subdirectory where the tool is installed In this manual only one example code is explained This description applies to all the code development The following example assumes that you have the MSP scanport interface connected to the parallel port of your PC and Tl speech code development unit connected to the MSP Scanport interface You should have the MSP50C6xx code development tool already installed on the system before attempting to continue with this example Overview This example code demonstrates MELP running at 2400 bps It shows how to use the timer interrupts to scan a keyboard and flash LEDs while speaking Activation of the sleep modes is also illustrated Getting Started Connect the MSP scanport the small grey metal box to the PC and
157. SET then the block protection mode is engaged This means that read and write access is prevented at locations 0x0000 through NTM 1 x 512 1 Read and write access is permitted at locations NTM 1 x 512 through Ox7FFF If GP is CLEAR then the global protection mode is engaged This prevents read and write access to all addresses of the ROM regardless of the value of BP A Note Block Protection Word The remaining bits in the block protection word are reserved for future use but must remain set in order to ensure future compatibility These bits are numbers 6 15 and 16 LLLLA MSP50C614 Architecture 2 21 Interrupt Logic When the device is powered up the hardware initialization circuit reads the value stored in the block protection word The value is then loaded to an inter nal register and the security state of the ROM is identified Until this occurs execution of any instructions is suspended The same initialization sequence is executed before entry into the special test modes available on the P614 and C614 EPROM mode emulation mode and trace mode This insures that the protection scheme is always in force when running the processor in one of these modes A dedicated circuit ensures that a switch between emulation mode and trace mode cannot occur without
158. See Also MULTPLS MULAPL MULAPLS MULSPL MULSPLS Example 4 14 44 1 MULTPL A0 R3 Multiply the contents of R3 with MR register and store PL in accumulator AO Increment R3 by 2 Example 4 14 44 2 MULTPL A2 A2 A Multiply MR register to accumulator A2 and store PL to accumulator A2 4 138 Individual Instruction Descriptions 4 14 45 MULTPLS Multiply String and Transfer PL to Acumulator Syntax abel rame usse Taa ok Word w With RPT ok crass aes aag eas mesas Uo Tweets ant t Execution PH PL MR Y src An lt PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions Pro a5 sa fis 12 HD to o o v e fs a EH 2 fo MULSPLS An adr pplebebbiel1 as x dma16 for direct or offset16 long relative see section 4 13 wursPLSAn An trs tjo o s t Ao ifilo i lo a a Description Perform multiplication of multiply register MR and value of src string The 16 MSBs of the ng 3 x 16 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register stored in An string MULTPLS An adrs Multiply MR by effective data memory string move PL to An MULTPLS Ar An Multiply MR by An string move PL to An See Also MULTPL MULAPL MULAPLS MULSPL MULSPLS Example 4 14 45 1 MULTPLS A0 R3 Multiply the contents
159. TAG pma16 Rmod label JIN1 pma16 Rmod label JNIN1 pma16 Rmod label JIN2 pma16 Rmod label JNIN2 pma16 Rmod label JXZ pma16 Hmod label JXNZ pma16 Rmod label JXS pma16 Rmod label JXNS pma16 Rmod label JXG pma16 Rmod label JXNG pma16 Rmod label JRA pma16 Rmod label JRNA pma16 Rmod label JRZP pma16 Hmod label JRNZP pma16 Rmod label JRLZP pma16 Rmod label JRNLZP pma16 Rmod Rmod Rx Rx Rx R5 Execution IF condition true OR unconditional PC pma16 ELSE NOP PC PC 2 if post modification specified IF Rmod Rx Rx Rx 2 ELSE IF Rmod Rx Rx Rx 2 ELSE IF Rmod Rx R5 Rx Rx R5 Flags Affected RCF and RZF affected by post modification of Rx Assembly Language Instructions 4 109 Individual Instruction Descriptions Opcode instructions pie fas t4 1 12 11 Pto se f7fefsf fa 2 1 o emm ES pma16 ENE S ES pma16 A ERREUR EN pma16 pa ela O FREE S pma16 led co names Description cc cc name Not cc name True condition Not true condition 0 Z NZ Conditional on ZF 1 Not condition ZF 0 nanan S NS Conditional on SF 1 Not condition SF 0 1 0 C NC Conditional on CF 1 Not condition CF 0 anno B NB Conditional on ZF 0 and CF 0 Not condition ZF 0 or CFzO0 1 0 A NA Conditional on ZF 0 and CF 1 Not condition ZF 0 or CFz1 anno G NG Conditional on SF 0 and ZF 0 N
160. The first difference between the xTAG and xFLAG instructions is the addressing STAG 0x0000 sets the TAG bit of RAM word zero RTAG 0x0002 clears the TAG bit of RAM word one STAG 0x0002 2 sets the TAG bit of RAM word two STAG and RTAG use RAM byte addresses to specify which TAG to set or clear This immediately causes confusion since there are 1280 bytes and only 640 TAGs What happens when an odd byte is used to set a tag with STAG STAG 0x0001 sets the TAG bit of RAM word zero STAG 0x0003 sets the TAG bit of RAM word one STAG 0x0005 2 sets the TAG bit of RAM word five All word boundaries in RAM start at even numbers RAMeyen If an odd byte RAMeven 1 is used to set a TAG then the TAG for RAMgyeg is set Thus STAG 0x0000 TAG 0x0001 un are functionally equivalent As a sharp contrast the SFLAG and RFLAG instructions use RAM word ad dresses to specify which TAG to set or clear SFLAG 0x0000 sets the TAG bit of RAM word zero SFLAG 0x0001 sets the TAG bit of RAM word one Another difference between the xTAG and xFLAG instructions is the addres sing modes STAG and RTAG can use adrs addressing modes This in cludes direct short relative relative to R5 long relative and indirect addres sing modes This affects the number of clock cycles it takes to execute xTAG instructions Instruction Syntax and Addressing Modes However xFLAG instructions use flagadrs addressing m
161. The windowed PGA version of the MSP50P614 is required for this debugging mode Functional Description 1 4 Functional Description The device consists of a micro DSP core embedded program and data memory and a self contained clock generation system General purpose pe riphery is comprised of 64 bits of partially configurable I O The core processor is a general purpose 16 bit micro controller with DSP capability The basic core block includes a computational unit CU data address unit program address unit two timers eight level interrupt processor and several system and control registers The core processor gives the P614 and C614 break point capability in emulation The processor is a Harvard type for efficient DSP algorithm execution lt re quires separate program and data memory blocks to permit simultaneous ac cess The ROM has a protection scheme to prevent third party pirating It is configured in 32K 17 bit words The total ROM space is divided into two areas 1 The lower 2K words are re served by Texas Instruments for a built in self test 2 the upper 30K is for user program data The data memory is internal static RAM The RAM is configured in 640 17 bit words Both memories are designed to consume minimum power at a given System clock and algorithm acquisition frequency A flexible clock generation system is included that enables the software to control the clock over a wide frequency range The implementation uses
162. Tools 5 61 Implementation Details iprta in a0 0x10 read from PortC ret _iprtd in a0 0x18 read from PortD ret _iprte in a0 0x20 read from PortE ret iprtf in a0 0x28 read from PortF ret in port access table for table lookup DATA _iprta DATA _iprtb DATA _iprtc DATA _iprtd DATA _iprte DATA _iprtf called from C void cport char Port int Control Writes Control bits for the I O port specified by the letter Port Example F cport B OxFF Configure all bits of Port B as output 7 _cport mov a0 r7 lt 4 port address mov aQ r7 2 data add a0 cont port access A find the location in the table mov a0 a0 get the value of the label in the table jmp a0 jump to the label from the table _cprta out 0x04 a0 write to PortA control ret _cprtb out OxOC a0 write to PortB control ret _cprtc out 0x14 a0 write to PortC control ret _cprtd out Ox1C a0 write to PortD control ret _cprte out 0x24 a0 write to PortE control ret cont port access table for table lookup DATA eprta DATA _cprtb DATA eprte DATA cEprtd 5 62 DATA _cprte called from C void wait int msec waits for the amount of msec passed Calls waitlms 7 _walt mov a0 r7 2 shlac a0 a0 mov tempa a0 mov r4 tempa rep call waitlms wait ims jrnzp _rep r4 decrement counter by 2 ret i g EAK K k k
163. Topic Page C1 IMSP50C605 Data Sheet 2 aa ta a aia alante C 2 C 1 MSP50C605 Data Sheet This appendix contains the data sheet for the MSP50C605 mixed signal pro cessor C 2
164. Transfer accumulator A 0 or offset accumulator A 1 MOVS PH An to PH register Transfer status is modified MOV MR An next A Transfer accumulator A 0 or offset accumulator A 1 MOVS MR An to MR register in the signed multiplier mode UM bit in status register set to 0 Transfer status is modified MOVU MR An next A Transfer accumulator A 0 or 1 to MR register in the unsigned multiplier mode UM bit set to 1 Transfer status is modified MULSPL An An next A Multiply the MR register by accumulator A 1 or offset MULSPLS An An accumulator A720 subtract lower 16 bits of the product from the offset accumulator A 1 or accumulator A 0 Store in the accumulator A 0 or offset accumulator A 1 Latch the upper 16 bits in PH ALU status is modified MULAPL An An next A Multiply MR register by accumulator A 1 or offset MULAPLS An An accumulator A 0 add lower 16 bits of product to offset accumulator A 1 or accumulator A 0 and store to accumulator A 0 or offset accumulator A 1 Latch upper 16 bits in PH ALU status is modified SHLTPL An An next A Barrel shift the accumulator A 1 or 1 value n bits left SHLTPLS An An SV reg Store the upper 16 bits of the 32 bit shift result to PH msbs extended by XM mode bit Transfer the lower 16 bits to accumulator A 0 or offset A 1 ALU status is modified MULTPL An An
165. Unit The hardware loop counter controls the execution of repeated instructions using one of two modes 1 consecutive iterations of a single instruction following the repeat RPT instruction or 2 a single instruction which operates on a string of data values string loops For all types of repeated execution interrupt service branches are automatically disabled temporarily The data pointer DP register is loaded at two instances 1 from the accumulator during lookup table instructions and 2 from the databus during the fetch of long string constants To simplify algorithms which require sequential indices to lookup tables the DP register may be stored in RAM The bit logic unit is a 1 bit unit which operates on flag bit data It is controllable by eleven different instructions which generate the decision flags for conditional program control The results of operations performed by the bit logic unit are sent either to the flag bit of RAM memory or to the TF1 and TF2 bits of the status register STAT Memory Organization RAM and ROM 2 6 Memory Organization RAM and ROM Data memory RAM and program memory ROM are each restricted to internal blocks on the C614 The program memory is read only and limited to 32K 17 bit words The lower 2048 of these words is reserved for an internal test code and is not available to the user The data memory is static RAM and is limited to 640 17 bit words 16 bits of the 17 bit RAM are used
166. V to a 16 bit value For example a value of 7H inthe SV register is decodedto a multiplier operand of 0000000010000000 binary In effect this causes a left shift of 7 bits to in the final 32 bit product In other words a nonzero value say k 0 lt k x 15 in the SV register means padding K number of zeros to the right of the final result 4 2 3 Data Pointer Register DP The data pointer register DP is a 16 bit register that is used to point to a program memory location for various look up table instructions DP is not directly loaded by the user It is loaded during the execution of lookup instructions overwriting the previous content of the DP register Lookup instructions are described in detail in section 4 9 The DP register auto increments the next logical program memory location after the execution of a lookup instruction In addition to lookup instructions the filter instructions FIRK and CORK see Section 4 11 for detail use the DP pointer to look up filter coefficients It may be required to context save and restore the DP in interrupt service routines 4 2 4 Program Counter PC The program counter PC holds the program memory location to be used for the next instruction s execution It increments by 1 for single word instructions 4 2 4 2 5 Top of Stack System Registers or by 2 for double word instructions each execution cycle and points to the next program memory location to fetch During a maskable interrupt
167. a phase locked loop PLL circuit that drives the processor clock at a selectable frequency between the minimum and maximum achievable Selectable frequencies for the processor clock are spaced apart in 65 536 kHz steps The PLL clock reference is also selectable either a resistor trimmed oscillator or a crystal referenced oscillator may be used Internal and peripheral clock sources are controlled separately to provide different levels of power management see Figure 1 2 The peripheral consists of five 8 bit wide general purpose l O ports one 8 bit wide dedicated input port and one 16 bit wide dedicated output port The bidirectional I O can be configured under software control as either high impedance inputs or as totem pole outputs They are controlled via addressable l O registers The input only port has a programmable pullup option 100 kO minimum resistance and a dedicated service interrupt These features make the input port especially useful as a key scan interface A simple one bit comparator is also included in the periphery The comparator is enabled by a control register and its pin access is shared with two pins in one of the general purpose I O ports Rounding out the C614 periphery is a Introduction to the MSP50C614 1 5 C605 and C604 Preliminary Information built in pulse density modulated DAC digital to analog converter with direct speaker drive capability The block diagram appearing in Figure 1 1 gives an overvie
168. a target board that has power applied Figure 5 2 Hardware Installation MSP Scanport IEEE1284 Interface MSPSI San bi MSP50P614 ort table GREEN YELLOW Target development 4 gt LED LED board e e PC Parallel port 18 V DC Target board power LED DESCRIPTION MSPI power Emulation mode programming Emul Prog Target board power Code Development Tools 5 5 Software Installation Figure 5 3 10 Pin IDC Connector top view looking at the boara IDC2X5M Vpp PGMPULSE GND SCANIN SCANOUT PINOUT DETAILS 5 5 Software Installation 10 PIN HEADER 3M PART 2510 60024B efes IDC2X5M RESET OO PAD DIA 0 060 SCANCLK O O SYNC 0 800 O G N C O HOLE DIA 0 038 0 1 VDD O O 0 1 ee LAYOUT DETAILS Install the MSP50P614 MSP50C614 development tool from the supplied floppy disk by running the setup exe Installation should not take much more than one minute Following are the Software Installation steps Step 1 Run the setup exe application from Windows explorer or using the Run menu option by pressing the start button Figure 5 4 InstallShield Window Setup E MSP50C6xx Code Development Tool Setup is preparing the InstallShield R Wizard which will guide you through the rest of the setup process Please wait Software Installation Figure 5 5 Setup Window MAE Bitis Coda Eran Te WSPAO Cv Code Development Tool dij
169. able 4 20 Class 3 Instruction Description Continued Lm pe AA 0 n XOR An An An next A XORS An An An OR An An An next A ORS An An An AND An An An next A ANDS An An An SHRAC An An next A SHRACS An An SUB Ar An PH next A SUBS An An PH T ADD An An PH next A ADDS An An PH MOV An PH next A MOVS An PH T EXTSGN An next A EXTSGNS An T CMP An An next A CMP An An next A CMPS An An CMPS An An Logically exclusive OR accumulator with offset accumulator and store the results in accumulator A 0 or 1 ALU status is modified Logically OR accumulator with offset accumulator and store results into accumulator A 0 or 1 ALU status is modified Logically AND accumulator with offset accumulator and store result s into accumulator A 0 or 1 ALU status is modified Shift accumulator or offset accumulator right 1 bit and store result in accumulator A 0 or 1 MSB will be set to zero or be set equal to the sign bit XSGM dependent ALU status is modified Subtract product high register from accumulator A 0 or from offset accumulator A 1 and store the result into accumulator A 0 or into the offset accumulator A 1 ALU status is modified String bit causes subtract with carry status CF Add product high register to accumulator or to offset accumulato
170. above unsigned t CRNA pma16 CRBE pma16 Conditional call on Rx not above unsigned 4 88 Individual Instruction Descriptions Syntax Alternate Syntax Description CRC pma16 Conditional call on RCF 1 CRNC pma16 Conditional call on RCF 0 CRE pma16 CRZ pma16 Conditional call on RZF 1 equal t CRNE pma16 CRNZ pma16 Conditional call on RZF 0 not equal CXG pma16 CXNLE pma16 Conditional call on transfer greater signed CXNG pma16 CXLE pma16 Conditional call on transfer not greater signed t CXS pma16 Conditional call on XSF 1 CXNS pma16 Conditional call on XSF 0 t Alternate mnemonics are provided as a way of improving source code readability They generate the same opcode as the original mnemonic For example CA call above tests the same conditions as CNBE call not below or equal but may have more meaning in a specific section of code See Also CALL VCALL RET IRET Example 4 14 9 1 CZ 0x2010 Call routine at program memory address 0x2010 if a previous operation has set the ZF 1 flag in STAT Example 4 14 9 2 CTF1 0x2010 Call routine at program memory address 0x2010 if a previous operation has setthe TF1 1 flag in STAT Example 4 14 9 3 CRNBE 0x2010 Call routine at program memory address 0x2010 if a previous operation has set the flags RCF 1 RZF 0 in STAT Assembly Language Instructions 4 89 Individual Instruction Descriptions 4 14 10 CMP Compare Two Words a An adrs Table 4 46 Table 4 46 ou
171. accumulator SHLSPL An adrs Shift data memory word left substract PL from An SHLSPL An An next A Shift An left substract PL to An See Also SHLSPLS SHLTPL SHLTPLS SHLAPL SHLAPLS Example 4 14 71 1 SHLSPL AO R4 R5 Shift the word pointed by the byte address stored in R4 by ngy bits to the left subtract the shifted PL from Accummulator AO and store the result in accumulator AO Add R5 to R4 and store result in R4 PH holds the upper 16 bits of the shift Example 4 14 71 2 SHLSPL A2 R1 Shift the word pointed by the byte address stored in R1 by nay bits to the left subtract the shifted value PL from the accumulator A2 and store the result in accumulator A2 Increment R1 by 2 PH holds the upper 16 bits of the shift Example 4 14 71 3 SHLSPL Al Al A Preincrement accumulator pointer AP1 Shift the accumulator A1 by nsy bits to the left subtract PL from A1 and store result in accululator A1 After execution PH contains the upper 16 bits of the 32 bit shift 4 166 Individual Instruction Descriptions 4 14 72 SHLSPLS Shift Left String With Subtract PL Syntax Taba name dest we cook ok wora w With RPT c crass Tamang An aos tao Table as 1b LT snusecs Wil are Execution PH PL src lt lt SV dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions Pro Pis fra fis
172. ackage for the Development Device P614 o o o 7 5 120 Pin Grid Array PGA Package Leads P614 0 cece cece eee 7 6 Speech Development Cycle 0 0 nent nn 7 8 MSP50C605 Architecture rsrs psani cece eens A 4 MSP50C605 Memory Organization 0 000 cece eens A 5 MSP50C605 100 Pin PUM Package 200 c cece eee teens A 6 MSP50C604 Block Diagram 00 cc tenet eens B 4 MSP50C604 Memory Organization and I O ports 0 00 0 cece eee eens B 6 MSP50C604 Slave Mode Signals cece cece eee teen eens B 9 MSP50C604 64 Pin PUM Package teen n B 9 Contents xiii Tables ak p lod d on o al E N TTT T T aA wN 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 4 19 4 20 4 21 4 22 4 23 4 24 xiv Signal and Pad Descriptions for the C614 sees 1 10 MSP50C614 100 Pin PUM Plastic Package Pinout Description 1 11 Signed and Unsigned Integer Representation liliis o 2 5 Summary of C614 s Peripheral Communications Ports 0 000 cee eens 2 17 Programmable Bits Needed to Control Reduced Power Modes 2 37 Status of Circuitry When in Reduced Power Modes eee eens 2 38 How to Wake Up from Reduced Power Modes 0002ceeeeeee eee eaee 2 39 Destination of Program Counter on Wake Up Under Various Conditions 2 40 Interr ptS sc csedisi
173. age Instructions 4 75 Individual Instruction Descriptions Description ADD FADD dest sre src ADD src with dest and store the result to dest ADD dest src src poo esi oe ADD src with src and store the result to dest Premodify the mod before execution if provided See Also ADDB ADDS SUB SUBB SUBS Example 4 14 1 1 ADD A2 A2 R2 R5 A Decrement accumulator pointer AP2 Add word at address in R2 to A2 put result in A2 Add value in R5 to R2 and store in R2 Example 4 14 1 2 ADD A1 A1 0x1221 Add immediate value of 0x1221 to A1 and store result in A1 Example 4 14 1 3 ADD AO A0 PH Add PH to accumulator AO and store result in accumulator AO Example 4 14 1 4 ADD Al Al Al Add accumulator A1 to accumulator A1 put result in accumulator A1 Example 4 14 1 5 ADD R3 0x1000 Add 0x1000 to register R3 store result in R3 Example 4 14 1 6 ADD R2 R5 Add R2 to R5 store result in R2 Example 4 14 1 7 ADD AP3 0x10 Add immediate 0x10 to accumulator pointer AP3 store result in accumulator pointer AP3 4 76 Individual Instruction Descriptions 4 14 2 ADDB ADD BYTE Syntax Execution dest dest src PC PC 1 Flags Affected dest is An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordingly Opcode LL NNNM ERES ECT EE ERI ER EC LCD papel pp Rm e Te rre TeleleTe eTeTe m Te Te See Also ADD ADDS SUB SUBB SUBS Description Add immediate value of
174. alking Books Electronic Learning Aids Talking Dictionaries J Games QU Warning Systems Talking Clocks Equipment for the Handicapped Introduction to the MSP50C614 1 3 Development Device MSP50P614 1 3 Development Device MSP50P614 The MSP50P614 is an EPROM based version of the MSP50C614 and is available in 120 pin windowed ceramic pin grid array This EPROM based version of the device is only available in limited quantities to support software development Since the MSP50P614 program memory is EPROM each person doing software development should have several of these PGA packaged devices The MSP software development tool supports non real time debugging by scanning the code sequence through the MSP50C614 MSP50P614 scanport without programming the EPROM However the rate of code execution is lim ited by the speed of the PC parallel port Any MSP50C614 MSP50P614 can be used in this debugging mode The MSP50P614 EPROM must be programmed to debug the code in real time The MSP software development tool is used to program the EPROM set a breakpoint and evaluate the internal registers after the breakpoint is reached If a change is made to the code the code will need to be updated and programmed into another device while erasing previous devices This cycle of programming debugging and erasing typically requires 10 15 devices to be in the eraser at any one time so 15 20 devices may be required to operate efficiently
175. anch is initiated The trigger event is marked by a 0 to 1 transition in the IFR bit At that time the core processor searches all interrupt levels which have both 1 pending interrupt flag and 2 interrupt service enabled The highest priority interrupt among these is selected The program then branches to the location which is stored in the associated Interrupt Vector Section 2 6 3 Inter rupt Vectors This location constitutes the start of the interrupt service routine Instructions in the interrupt service routine are executed until the IRET return instruction is encountered Afterwards any other pending interrupts will be similarly serviced in the order of their priority Eventually the program returns to whatever point it was before the first interrupt service branch When an interrupt service branch is taken the global interrupt enable is automatically cleared by the core processor This disables all further interrupt service branches while still in the pending service routine As a result the programmer must re enable the interrupts globally using the INTE instruction If performed as the second to last instruction in the service routine then no nesting of multiple interrupts will occur If on the other hand a nesting of certain interrupts is desired then the INTE instruction may be included as the first instruction or anywhere else within the service routine When an interrupt service branch is taken the processor core also
176. and always located in a0 The stack usage for function calls is as follows C to C function call The stack is shown after the operation on the bottom is performed R7 Param 2 Param 2 R7 Param 1 Param 1 Param 1 Param 1 R7 R5 Stack data R5 Stack data R5 Stack data Before call Parameter 1 Parameter 2 R7 RS Function call R7 R5 ADDB R7 2 MOV R7 R5 R5 R7 Code Development Tools Implementation Details lt This is the SP before the C function call 5 55 Implementation Details 5 56 C to C function return in cmm return R5 R7 SUBB R7 2 R7 R5 MOV A0 R7 MOV 0 A0 MOV R5 0 R7 R5 R7 R5 Implementation Details Code Development Tools 5 57 Implementation Details 5 58 C to ASM function call The stack is shown after the operation on the bottom is performed R7 R5 Before Call R7 R5 Parameter 1 R7 R5 Parameter 2 R7 R5 C to ASM function return R7 R5 Function call R7 R5 Implementation Details Code Development Tools 5 59 Implementation Details To call an assembly routine from C the routine must be defined as GLOBAL in the assembly file and as a CMM FUNC in the C file The following contains C callable assembly routines for accessing the I O ports
177. and delivers the maximum possible current drive to the loudspeaker The overflow bits thus help to ensure that the audible artifacts of wrap around do not occur 3 2 3 PDM Clock Divider The pulse density modulation rate is determined by the master clock The PDM rate may be set equal to the rate of the MC or it may be set at one half the rate of the MC This option is controlled by the PDM clock divider PDMCD in the interrupt general control register IntGenCtrl The PDMCD is located at bit 18 in IntGenCtrl address 0x38 Clearing the PDMCD bit results in a PDM rate equal to 1 2 MC i e the CPU Clock rate Setting the PDMCD bit results in a PDM rate equal to the MC After RESET is held low the default setting for the PDMCD bit is zero PDM rate 1 2 MC Figure 3 1 PDM Clock Divider Master Clock 131 07 kHz 33 554 MHz MC PDMCD PDM Clock Divider Bit 13 in IntGenCtrl EJ PDM Rate Pulse Density Modulation Rate Governs DAC Capacity te adjusted in ClkSpdCtrl EN rate OO did do 65 536 kHz FMAX frequency or 131 07 33 554 MHz CPU Clock Core Processor Speed 65 536 kHz FMAX 8 MHz is max assured see Chapter 9 Digital to Analog Converter DAC For a given sampling rate and DAC resolution the CPU clock rate may be increased if necessary through the use of over sampling In the previous example an original sampling rate of 8 kHz and a PDM rate of 4 MHz was used A 2 times over samplin
178. and sample data 4 102 Individual Instruction Descriptions 4 14 20 IDLE Halt Processor Syntax Taba O ESE Wor w WPT ax ee pe H L5 d Ns CES Execution Stop processor clocks PC PC 1 Flags Affected None Opcode pr Presets e E LEE anno ee ESS Description Halts execution of processor An external interrupt wakes the processor This instruction is the only instruction to enter one of the three low power modes defined in section 2 11 Low power modes depend on the state of ClkSpdCtrl register bit 8 through bit 10 and the ARM bit in IntGenCtrl register Example 4 14 20 1 MOV AO 0 OUT 0x34 AO Turn off DAC MOV AO 0x0400 Turn off clock idle bit 1 OUT Ox3d AO Write in ClkSpdCtrl write only IN AO 0x38 Read IntGenCtrl register value OR AO AO 0x4000 Set ARM 1 OUT 0x38 AO Write to IntGenCtrl IDLE Go to deep sleep mod To understand this routine refer to the Reduced Power Modes table in section 2 11 The bits to be set up to switch to deep sleep mode are as follows set bits 10 of ClkSpdCirl IO address 0x3d register to 1 and reset bits 8 and 9 of CIkSpdCtrl register to O The PLLM bits are reset to zero in this example which is not a necessary operation Note that the ClkSpdCtrl register is write only Set the ARM bit in the IntGenCtrl UO address 0x38 register to 1 program line 2 and 3 above The last line executes the IDLE instruction which switches the processo
179. art program memory location hex If this value is not provided execution starts from current PC value Start Trace At PC 0x0000 Optional PC location where Stop at PC execution should stop If Stop After field is used program stops which ever c 3 occurs first This radio button is Stop After 100000 Cycles checked when trace mode sia Is running Optional number of clock cycles to execute from C Running Trace to File Start location If Stop at PC field is used program stops which ever occurs Stop Quit first an Saves the result of trace to Start tracing a file with the name as Stop tracing Exit Trace Mode project with extension trc Run Internal This menu option launches execution on the program actually programmed on the chip In the case of MSP50P614 MSP50C614 program execution will stop if a hardware breakpoint is encountered Otherwise the user will have to stop execution by hitting the Stop icon for example IMPORTANT The hardware breakpoint has to be located more that one cycle away from the current program counter location For example if the current PC is 0x0800 and the instruction at 0x0800 is a one cycle instruction like NOP then the closest location for a hardware breakpoint is at PC 2 If a breakpoint was set at address PC 1 it would be ignored by the system NOTE The code to execute must be present on the chip 5 26 Software Emulator Stop
180. ave been defined in more detail Table 2 2 Summary of C614 s Peripheral Communications Ports Control Register Address Location Access Name I O port A control I O port B control I O port C control UO port D control I O port E control Interrupt general Ctrl t Input states are provided by the external hardware t A control register value of 0x00 yields a port configuration of all inputs EA State after Section for Abbreviation RESET LOW Reference PAn 7 Data unknownt PCo 7 Data 3 1 1 PCo 7 Ctrl PDo 7 Data PDO 7 Ctrl PEp 7 Data p DAC Data DAC OR e Same state as IFR before RESET MSP50C614 Architecture 2 17 Memory Organization RAM and ROM Table 2 2 Summary of C614 s Peripheral Communications Ports Continuea 1 O Map Width of Allowable Control Register N Abbreviation State after Section for Address Location Access ONTO drei Sera S Tieni RESET LOW Reference 16 bits TIMER1 period PRD1 0x0000 16 bits TIMER1 count down TiM 0x0000 WRITE only T Clock speed control ClkSpdCtri 0x0000 2 6 3 Interrupt Vectors 2 18 When its event has triggered and its service has been enabled an interrupt causes the program counter to branch to a specific location The destination location is stored programmed in the interrupt vector which resides in an up per address of ROM The following table lists the ROM address associated with each interrupt vector ROM address of Interrupt Name Vector Event Sourc
181. avoids the software pipelining effect that post modification would cause Some C614 instructions reference only the accumulator register and cannot use or modify the offset register that is fetched at the same time Other instruc tions provide a selection field in the instruction word A or A op code bit This has the effect of exchanging the column addressing sense and thus the source or order of the two registers Also some instructions can direct the ALU output to be written either to the accumulator register or to the offset accumula tor register Refer to Chapter 4 nstructions for more details The ALU s accumulator block functions as a small workspace which elimi nates the need for many intermediate transfers to and from memory This al leviates the memory thrashing which frequently occurs with single accumula tor designs 2 3 Data Memory Address Unit The data memory address unit DMAU provides addressing for data memory internal RAM The block diagram of the DMAU is shown in Figure 2 6 The unit consists of a dedicated arithmetic block and eight read write registers RO through R7 Each read write register is 16 bits in size The arithmetic block is used to add subtract and compare memory address operands The register set includes four general purpose registers RO to R3 and four special purpose registers The special purpose registers are the LOOP control register R4 the INDEX register R5 the PAGE register R6
182. be system registers or data memory locations referred by addressing modes This is instruc tion specific source of first data Optional or not used for some instruction Source can be a system register a data memory location referred by addressing modes or a program memory location This is instruction specific source of second data Some instructions use a second data source Op tional or not used for some instructions Source 1 can be a system register a data memory location referred by addressing modes or a program memory location This is instruction specific pre or post modification of a register The meaning of mod is instruction specific Square brackets represent optional arguments Some instructions have many combinations of source and destination registers and addressing modes The combination is instruction class specific The possible combinations of sources destinations and modifications are de pendent on the instruction class Instruction classes are discussed in detail in section 4 4 4 8 Instruction Syntax and Addressing Modes 4 3 2 Addressing Modes The addressing modes on the MSP50P614 MSP50C614 are immediate di rect indirect with post modification and three relative modes The relative modes are Y Relative to the INDEX or R5 register The effective address is indirect reg ister INDEX Short relative to the PAGE or R6 register The effective address is PAGE 7 bit positive offset
183. beectefeekRave eu eene RP esr aa 3 7 State of the Status Register 17 bit after RESET Low to High 3 21 Status Register STAT ee n 4 7 Addressing Mode Encoding e 4 9 arssMBIeDe pM EE Mc 4 10 Addressing Mode Bits and adrs Field Description sisse 4 10 MSP50P614 MSP50C614 Addressing Modes Summary 02000eee eens 4 11 Auto Increment and Auto Decrement Modes 4 11 Flag Addressing Field flagadrs for Certain Flag Instructions Class 8a 4 12 Initial Processor State for the Examples Before Execution of Instruction 4 13 Indirect Addressing Syntax een 4 15 Symbols and Explanation vs 2 5 ar KR 0 N 9 ioe a cece sn 4 22 Instruction Classification 00 cece eet eens 4 23 Classes and Opcode Definition 0 4 25 Class 1 Instruction Encoding 00 Z 2 cece a E eee eee 4 26 Class 1a Instruction Description 0 0000 cece eens 4 26 Class 1b Instruction Description iatea N KR a eee 4 27 Class 2 Instruction Encoding 00 ccc eee eee eee eee eee 4 29 Class 2a Instruction Descritpion 0000 eens 4 29 Class 2b Insstruction Description cx K isean daea mi KKR e KK iodi a R d ia aaa ee 4 30 Class 3 Instruction Encoding 9 4 90 0 d 0 d E a ee eect eee eee 4 31 Class 3 Instsruction Description sh 4 31 Class 4a Instruction Encoding aso iaaa md iaat daia N eee a dii a odia ao dai eens 4 34 Class
184. cation multiply accumulate or shift operation The upper 16 bits of the result are stored in the PH register There are no instructions that load or save the PL register directly but multiply accumulate instructions allow the contents of the PL register to be added subtracted or transferred to the accumulator 4 2 8 Accumulators ACO AC31 4 4 There are 32 accumulators on the MSP50P614 MSP50C614 Each is 16 bits wide The first sixteen accumulators ACO AC15 have offset accumulators AC16 AC31 and vice versa At any one time four accumulators can be selected through accumulator pointer registers APO AP3 see section 4 2 9 Some instructions can specify offset accumulators which are the accumulators pointed to by APn 16 or APn 16 whichever is in the range 0 to 31 The offset accumulators are indicated by an offset bit A in some instructions When this bit is 0 An points to the accumulator directly If it is 1 then An points to the offset for some instructions this scheme changes The selected accumulator pointer register should contain the index to the corresponding accumulator For example if APO has a value of 25 then it is pointing to accumulator AC25 If the offset bit is 1 AO then it is pointing to accumulator AC9 25 16 9 Because accumulators can only be addressed through accumulator pointers special symbols are used in MSP50P61 4 MSP50C614 instructions Accumulators are indicated by the symbol An where nrange
185. ccurs at the same time that the associated mask bit is SET IntGenCtrl address 0x38 bit 7 The latter indicates that the service for INT7 is enabled The INT7 Flag may also be SET or CLEARed at any time in software Use the OUT instruction with the associated I O port address IFR address 0x39 The TIMER1 enable bit is set or cleared in software bit 10 of the IntGenCtrl Similarly the falling edge event in the comparator is a trigger for INT7 This happens independently of any activity associated with TIMER1 TIMER1 starts counting anytime the following conditional is true IF INT6 Flag is CLEAR AND INT7 Flag is SET OR TIMER1 Enable is SET THEN TIMER starts counting Figure 3 2 Relationship Between Comparator Interrupt Activity and the TIMER1 Control INT Trigger INT Service port addressed Event Branch write instruction TIMER1 ENABLE Bit 10 IntGenCtrl 0x38 INT Flag bits IFR Associated With the Interrupt Trigger Event Interrupt Flag Register 0x39 Comparator ENABLE be act Genia Bit 15 IntGenCtrl 0x38 Mi Mii Peripheral Functions 3 15 Comparator Comparator ENABLED The comparator along with all of its associated functions is enabled by setting bit 15 of the interrupt general control register IntGenCtrl address 0x38 The default value of the register is zero comparator disabled a a CC Note IntGenCtrl Register Bit 15 At the time that bit 15 in the IntGenCtrl is set PD4 and
186. ck source for TIMER1 0 chooses 1 2 MC DAC timer underflow 1 value enables interrupt service The remaining bits in the IntGenCtrl have various control functions which are not directly related to the interrupt system Four of these are related to the timer functions Bits 8 and 9 are used to select the clock sources which govern the rates of TIMER1 and TIMER2 Clearing bit 8 chooses 1 2 MC as the source for TIMER i e the TIMER runs at one half the frequency of the Master Clock Setting bit 8 chooses the oscillator reference RTO or CRO as the source for TIMER1 The same applies for bit 9 and TIMER2 Bits 10 and 11 in the IntGenCtrl are used to enable TIMER1 and TIMER2 respectively Setting bit 10 starts TIMER1 and clearing bit 10 stops TIMER1 The same applies for bit 11 and TIMER2 Peripheral Functions 3 17 Interrupt General Control Register The upper four bits in the IntGenCtrl have independent functions Bit 12 is the enable bit for the pull up resistors on input port F Setting this bit engages all 8 F port pins with at least 100 kQ pull ups see Section 3 1 2 Dedicated Input Port F Bit 13 is the PDMCD bit for the pulse density modulation clock Clearing this bit yields a PDM clock rate equal to one half the frequency of the master clock i e the CPU clock rate Setting bit 13 yields a PDM rate equal to the rate of the master clock see Section 3 2 3 PDM Clock Divider Bit 14 is the ARM bit The set ARM bit cau
187. class 8b provides a flexible means of logically combining the test flag TF1 or TF2 with a status condition and storing the results back to the test flag Table 4 32 Class 8a Instruction Encoding n ERR CHER ERI CORN A ues pp pj Is I9 masa ts fo D ETT EE EC mh E CC EE ED D LL te Assembly Language Instructions 4 41 Instruction Classification Table 4 33 Class 8a Instruction Description MN CN CI MOV TFn flagadrs Load flag bit 17h bit from data memory referred by flag addressing mode flagadrs to either TF1 or TF2 in status register Load with inverted value if Not 1 OR TFn flagaars Logically OR either TF1 or TF2 with flag bit 17th bit from data memory referred by flag addressing mode flagadrs or inverted value if N21 addressed by the instruction and store back to TF1 or TF2 respectively AND TFn flagadrs Logically AND either TF1 or TF2 with flag bit 17th bit from data memory referred by flag addressing mode flagadrs or inverted value if Not 1 addressed by the instruction and store back to TF1 or TF2 respectively XOR TF flagadrs Logically exclusive OR either TF1 or TF2 with flag bit 17th bit from data memory in flagaars if Not 1 or inverted value if Not 0 addressed by the instruction and store back to TF1 or TF2 respectively MOV flagadrs TEn Store TF1 or TF2 to flag bit 17th bit from data memory referred by flag addressing mode flagadrs Table 4 32 RFLAG fla
188. cond oscillator option CRO for crystal referenced is a real time clock utilizing a 32 768 kHz crystal The crystal is mounted externally across pins OSCin and OSCour 2 9 2 PLL Performance A software controlled PLL multiplies the reference frequency generated from either RTO or CRO by integer multiples This higher frequency drives the master clock which in turn drives the CPU clock The master clock MC drives the circuitry inthe periphery sections ofthe C614 The CPU Clock drives the core processor its rate determines the overall processor speed The multi plier in the PLL circuit therefore allows the master clock and the CPU clock to be adjusted between their minimum and maximum values For either oscillator option the reference frequency 32 768 kHz is multiplied by four before itis accessed bythe PLL circuit The base frequency forthe PLL therefore is 131 07 kHz and the multiplier operates in increments of this base frequency The minimum multiplication of the base frequency is 1 and the maximum multiplication is 256 The resulting master clock frequency there fore can be varied from a minimum of 131 07 kHz to a maximum of 33 554 MHz in 131 07 kHz steps From the master clock to the CPU clock there is a divide by two in frequency The CPU clock therefore can be setto run between 65 536 kHz and the maxi mum achievable see Appendix C in 65 536 kHz steps MSP50C614 Architecture 2 29 Clock Control The maximum
189. copies to bit 11 of register Ox3D 2 32 Execution Timing However the general specification of the adjustment can be useful in certain circumstances For example the adjustment can be used to obtain a program matic increase or decrease in the speed of the RTO reference The default val ue for the adjustment after RESET low is all zeros The zero value generates the slowest programmable rate for the RTO reference The maximum value OxSF generates the fastest programmable rate for the RTO reference The full range from 0x00 to Ox3F effects an approximate 62 change based on the RTO resistor value specification The change is nonlinear and nonlinear it changes from one device to another On the P614 part the above method does not cause in the correct trim value to be loaded in ClkSpdCtrl MSP50P614 is an EPROM device Any preprogrammed value is erased when the chip goes through a UV erase procedure The RTO trim value must therefore be computed separately for each chip RTO trim values differ from one chip to another is identical for the same chip I X 7 Note Register Trim Value A resistor trim value is only needed when the resistor trimmed oscillator RTO is used The MSP50P614 device must determine the trim value sepa rately and use this value in the ClkSpdCtrl register bits 15 11 and 9 but C614 device needs to copy bit 0 of I O location O
190. countered first all lines following it are assembled until a HENDIF directive is found Code Development Tools 5 35 Assembler 5 36 Example HIF expression do something here HELSE do other things here HENDIF HIFDEF symbol Start of a conditional assembly structure If symbol has been defined either with a DEFINE directive or an EQU directive then the lines following this directive are assembled until a ELSE or a ENDIF directive are encountered If symbol has not been defined then all input lines are skipped until a ELSE or a ENDIF directive is encountered If a ELSE directive is encountered first all lines following it are assembled until a ZENDIF directive is found IFNDEF Start of a conditional assembly structure If symbol has NOT been defined then the lines following this directive are assembled until a ELSE or a ENDIF directive are encountered If symbol has been defined either with a DEFINE directive or an EQU directive then all input lines are skipped until a ELSE or a ENDIF directive are encountered If a ELSE directive is encountered first all lines following it are assembled until a ZENDIF directive is found Example IFDEF symbol do something here ELSE do other things here ENDIF IFNDEF symbol do something here ELSE do other things here ENDIF ZSTART FT This directive is created by the C compiler when it outputs assembly code to a file It marks the beginnin
191. ction PH is copied to the next to the last accumulator of the string Example 4 14 72 3 SHLSPLS A1 A1 Shift the accumulator string A1 by nev bits to the left subtract the lower 16 bits of shifted value PL from A1 and store the result in A1 After execution PH contains the upper 16 bits of the 32 bit shift Assembly Language Instructions 4 167 Individual Instruction Descriptions 4 14 73 SHLTPL Shift Left and Transfer PL to Accumulator Syntax label name dest src mod Clock clk With RPT clk sme ants maa Texas tb sure art AE not Execution premodify AP if mod specified PH PL src lt lt SV dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Wende 19 1 10110 De 01 T9 T2 1 Ee 8 T4 8 T2 1 TS a ctun e E can y dma16 for direct or offset16 long relative see section 4 13 ES SHLTPL Art A L nextal_ 1 1 Jo o neta An tjs oj fo Jo A A Description ums the accumulator pointer if specified Shift accumulator or data memory value pointed by adrs to left ngy bits as specified by the SV register into a 32 bit result The result is zero filled on the right and either zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the PH register The lower 16 bits of the result PL are t
192. ction board Furthermore it is recommended that these pins be connected to test points so the development tool can be connected Since the development tool requires Vpp and Vgs test points connected these signals are also needed LLLLLLLL The application circuits appearing in section 6 1 show the minimum recommended configuration for any C614 application board For production purposes the 10 kQ resistor which appears at the RESET pin is optional It is required for use with the Scan Port Interface but they may be shorted otherwise The footprints for this resistor is strongly recommended 7 1 1 Die Bond Out Coordinates 7 2 Die bond out coordinates are available upon request from Texas Instruments Mechanical Information 7 1 2 Package Information The MSP50C614 will be available in the 100 pin PJM package see Figure 7 1 and Table 7 1 Contact your local TI sales office for more informa tion Table 7 1 MSP50C614 100 Pin PJM Plastic Package Pinout Description GND4 Description GND3 DA Zz Ojo EET Zz xe gt Q N co ce 00 N A N aye oO ps co aja o mn ojo o DAOM Vcc3 DA DACp PF qa al PF T AR U z U TU U U O TI wo U 2 T PFo co PG15 PG14 PG13 PG42 PG PG10 Gg PGg copo mM Po Nimninif i afaf of
193. ctions 4 27 Instruction Classification Table 4 15 Class 1b Instruction Description Continuea A OO EO MULAPL An adrs Multiply the MR register by the addressing mode adrs and add MULAPLS An adrs the lower 16 bits of the product to the accumulator Latch the upper 16 bits into the PH register ALU status is modified SHLTPL An adrs Shift left n bits SV reg The 16 bit contents of the data memory SHLTPLS An adrs location in adrs are shifted and placed in accumulator string An Zeros fill from the right and either zeros or ones fill the left depending on the sign assuming XSGM mode is set Transfer the lower 16 bits to the accumulator and latch the upper 16 bits in PH ALU status is modified SHLSPL An adrs Shift left n bits SV reg The contents of the data memory SHLSPLS An adrs location in adrs are placed in a 32 bit result Zeros fill from the right and either zeros or sign extended ones fill the left if XSGM mode is set Subtract the lower 16 bits from the accumulator and latch the upper 16 bits in PH ALU status is modified SHLAPL An adrs Shift left n bits SV reg The contents of the data memory loca SHLAPLS An adrs tion in adrs are placed into a 32 bit result Zeros fill the right and either zeros or sign extended ones fill the left in XSGM mode Add the lower 16 bits to the accumulator and latch the upper 16 bits in PH ALU status is modified MULSPL An aars Multiply the MR
194. cumulator value not modified 1 ORB An imm8 Logical OR 8 bit positive constant with accumulator and store result to accumulator ALU status modified 1 1 ANDB An imm8 T Logical AND 8 bit positive constant with accumulator Store result to accumulator ALU status modified XORB An imm8 Logical XOR 8 bit positive constant with accumulator Store result to accumulator ALU status modified MOVB MR imm Load 8 bit constant to Multiplier register MR Does not change UM mode in status register but will zero fill the top 8 bits in MR register No change in status Assembly Language Instructions 4 29 Instruction Classification Table 4 18 Class 2b Instruction Description C2b Mnemonic Description 0 0 ADD Ar An imm16 next A Add long constant to accumulator or offset accumulator if 1 ADDS An An pma16 A 1 and store result to accumulator A 0 or offset accumulator A 1 ALU status modified 1 MOV An imm16 next A Load long constant to accumulator A 0 or 1 ALU status is MOVS An pma16 modified 0 1 SUB Ar An imm16 next A Subtract a long constant from the accumulator A 0 or 1 SUBS An An pma16 Store the result in accumulator A 0 or offset accumulator A 1 ALU status is modified CMP An imm16 next A Modify ALU status by subtracting a long constant from accu CMPS An pma16 mulator A 0 or from offset accumula
195. cycles and the Return RET instruction cannot immediately follow a CALL i e RET followed by a RET should not be allowed See Also CALL Ccc IRET Example 4 14 56 1 RET Returns from subroutine A CALL or Ccc instruction must have executed before Assembly Language Instructions 4 151 Individual Instruction Descriptions 4 14 57 RFLAG Reset Memory Flag Syntax pue mess TT 1 NR Toa Execution memory flag bit at flagadrs data memory location 0 PC PC 1 Flags Affected None Opcode Instructions Pro fis fia fia 12 to o e v e s a a 2 Jo RFLAG faga tjo ojs ojo o oj t fagars Description Reset flag at addressed memory location to 0 flagadrs includes two groups of memory flag addresses global flags which are the first 64 word locations in RAM and relative flags which are 64 locations relative to the page register R6 Flag address flagadrs only addresses the 17th bit See section 4 3 7 for more information See Also SFLAG STAG RTAG Example 4 14 57 1 RFLAG 0x21 Resets the flag bit at RAM byte location 0x0042 to zero Example 4 14 57 2 RFLAG R6 0x0002 Resets the flag bit at RAM byte location 0x0084 to zero Assume R6 0x0080 The R6 register is represented in bytes but the 0x0002 is represented in words Thus 0x0080 bytes plus 0x0002 words or 0x0004 bytes equals 0x0084 bytes 4 152 Individual Instruction Descriptions 4 14 58 RFM Reset Fractional
196. d call _wait Set TIMER2 to run from the RTO CTO 32 kHz and with a one second period in a0 IntGenCtrl or a0 TIM2REFOSC set bit 9 CTO clock 32 kHz out IntGenCtrl a0 INTE enable all interrupts ret 5 60 Implementation Details called from C void oport char Port int Data Writes Data to the I O port specified by the letter Port Example H oport B OxAA Write OxAA to port B oport mov a0 r7 4 port address mov a0 r7 2 data add a0 out port access A find the location in the table mov a0 a0 get the value of the label in the table jmp a0 jump to the label from the table _prta out 0x00 a0 write to PortA ret _prtb out 0x08 al write to PortB ret price out 0x10 a0 write to PortC ret _prtd out 0x18 a0 write to PortD ret prte out 0x20 a0 write to PortE ret out port access table for table lookup DATA _prta DATA _prtb DATA _prtc DATA _prtd DATA prte called from C int iport char Port Reads data from the I O port specified by the letter Port Example int data iport F Read port F _iport mov a0 r7 2 port address add a0 in port access A find the location in the table mov a0 a0 get the value of the label in the table jmp a0 jump to the label from the table _iprta in a0 0x00 read from PortA ret _iprtb in a0 0x08 read from PortB ret Code Development
197. dd R5 to RO after execution Example 4 14 51 2 OR Al Al OxFOFF A Preincrement pointer AP1 OR immediate OxFOFF to accumulator A1 Store result in accumulator A1 Example 4 14 51 3 OR Al Al Al A Pre decrement accumulator pointer AP1 OR accumulator A1 to accumulator A1 put result in A1 Example 4 14 51 4 OR TF1 R6 0x22 OR TF1 bit in STAT with tag bit 17th bit at relative flag address 0x22 relative to R6 i e R6 0x22 store result in TF1 flag in STAT Example 4 14 51 5 OR TF1 ZF OR ZF flag in STAT register with to TF1 put result in TF1 bit in STAT Example 4 14 51 6 OR TF2 RZP R2 OR TF2 with the condition code RZP Rx 0 flag for R2 and store result in TF2 If the content of R2 is zero then RZP condition becomes true otherwise false TF2 bit in STAT is modified based on this result 4 146 Individual Instruction Descriptions 4 14 52 ORB Bitwise OR Byte Syntax iae name usse Ta ok Word w With RPT ck crass or N R Execution dest dest OR src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode msmetons Pro 15 pafis 12 fn to o e v e s a ja fa 1 Jo Ll immB JORB an imme Lt Tots fot lofo an imm8 Description Bitwise OR byte of src and dest Result is stored in dest Only lower 8 bits of accumulator is affected See Also OR ORS AND ANDS XOR XORS NOTAC NOTACS Example 4 14 52 1 ORB A2 0x45 OR 0x45 immediate to accumulato
198. ddressing Syntax Syntax Operation name dest src Rx R5 next A Premodify accumulator pointer if next A is included Add Rx with R5 name Rx R5 src next A name dest src Rx next A Premodify accumulator pointer if next A is included Use address name Rx src next A pointed by Rx Rx content unchanged name dest src Rx next A Premodify accumulator pointer if next A is included Use address name Rx src next A pointed by Rx post increment Rx after use name dest src Rx next A Premodify accumulator pointer if next A is included Use address name Rx src next A pointed by Rx post decrement Rx after use x 0 7 R5 Note that the Rx registers treats data memory as a series of bytes Therefore when a word is loaded Rx increments by 2 Rx decrements by 2 When loading a word address into Rx the address must be converted into a byte ad dress by multiplying by 2 For example if we want Rxto point to the word ad dress 0x100 Rx should be loaded with 0x100 2 0x200 Example 4 3 10 MOV Al R1 R5 A Refer to the initial processor state in Table 4 8 before execution of this instruction Preincrement AP1 After preincrement A1 is AC22 and A1 is AC6 The contents of the data memory location stored in R1 are loaded into accumulator AC6 R1 is then incremented by R5 Final result AP1 22 AC6 Oxacb R1 R1 R5 0x0202
199. dest src imm next A Where immis the immediate value of a 16 bit number Example 4 3 1 ADD APO Ox1A Assume the initial processor state in Table 4 8 before execution of this instruc tion This instruction adds the immediate value 0x1A to APO Final result APO 0x1A 2 Ox1C Table 4 8 Initial Processor State for the Examples Before Execution of Instruction Registers register value APO 2 AP1 21 0x15 AP2 11 0x0B AP3 29 0x1D RO 0x0454 R1 0x0200 R2 0x0540 R3 0x03E2 R4 0x0000 R5 2 R6 0x03E4 R7 0x0100 AC2 0x13F0 AC1 0x0007 AC17 0x0112 AC20 0x3321 AC3 OXFEED AC28 0x11A2 AC29 0xAB AC19 0x1200 MR 0x1A15 data memory address data word address to convert to byte address multiply by 2 0x022A 0x0400 0x01F2 0x12AC 0x02A1 0x1001 0x012F 0x0000 0x0100 OXOABC 0x0080 0x0000 0x0001 0x499A 0x01FA 0x0112 program memory address data 0x13F0 Ox1B12 Example 4 3 2 MOV R5 OxF000 Loads the immediate value OxFO000 to R5 register Final result R5 OxFOOO Example 4 3 3 MOVB MR OxF2 Loads the immediate byte Oxf2 to MR register Final result MR Oxf2 Example 4 3 4 AND A0 A0 OxFF20 A Assume the initial processor state in Table 4 8 before execution of this instruc tion The source accumulator pointer APO is predecremented After predecre ment AO points to AC1 and AO points to AC17 AC17 is anded with the im mediate
200. diate byte from Rx Example 4 14 80 1 SUBB A2 0x45 Subtract 0x45 from accumulator A2 byte Example 4 14 80 2 SUBB R3 OxF2 Subtract OxF2 from register R3 byte 4 176 Individual Instruction Descriptions 4 14 81 SUBS Subtract Accumulataor String Syntax abel name dest sel Glock ok Word w With RPT ok ass P sues ant An 1203 sues art arch pman sus art Anar sss Ani An Ar susst arts Ari PH t This instruction ignores the string count executing only once but maintains the CF and ZF status of the previous multi ply or shift operation as if the sequence was a single string This instruction should immediately follow one of the fol lowing class 1b instructions MOVAPH MULAPL MULSPL SHLTPL SHLSPL and SHLAPL An interrupt can occur betweenone ofthese instructions andthis instruction An interrupt may cause an incorrect result Also single stepping is not allowed for this instruction An in this instruction should be the same as An in one of the listed class 1b instruc tion Offsets are allowed See Section 4 8 for detail Execution premodify AP if mod specified dest dest src for two operands dest src src for three operands PC PC w Flags Affected destis An OF SF ZF CF are set accordingly src1 is adrs TAG bit is set accordingly Opcode Instructions Pie fis ra 13 12 11 10 o jo v e S a s a n fo sus wages olofoli al a as x dma16 for direc
201. displayed in a different color Instructions are displayed as black text Comments are always displayed as green text Preprocessor text is displayed as comments The current instruction pointed by program counter is displayed as text with yellow background This highlight forwards as you step through the code Lines containing software breakpoints are displayed in red To set a software breakpoint just click the right mouse button over the line you want to break Only program lines that are notin a gray area can contain breakpoints To remove a breakpoint click the right mouse button over the line containing the breakpoint to be removed Texts with cyan Code Development Tools 5 19 Software Emulator background is the line reached by a search command by PC line number or label Search position can also be set by double clicking on itin the program window The line if any contain the hardware breakpointis displayed in green background To set a hardware breakpoint just click the right mouse button over the line you want to break while holding the SHIFT key down Only program lines that are not in a gray area can contain breakpoints To remove a hardware breakpoint click the right mouse button over the line containing the breakpointto be removed while holding the SHIFT key down The 8 most recent hardware breakpoint addresses are kept in memory The user can review them by clicking on the hardware breakpoint icon which pops up the Hardware B
202. dition TAG 0 Conditional on IN1 1 status Not condition IN1 0 Conditional on IN2 1 status Not condition IN2 0 Unconditional Conditional on XZF 1 Not condition XZF 0 Conditional on XSF 1 Not condition XSF 0 Conditional on XSF 0 and XZF 0 Not condition XSFz0 or XZFz0 reserved reserved 1 reserved 0 reserved 1 reserved Assembly Language Instructions 4 195 Instruction Set Summary 4 16 Instruction Set Summary Use the legend in Section 4 13 and the following table to obtain a summary of each instruction and its format For detail about the instruction refer to the detail description of the instruction eme esiste ESE eris warner one hm a me meca meca Du po Ja ariete 2 p 2 we fa oo CSC f Lm ES ECON CEST Lom P 9 we ems H H 1 b em Lo pm nme H LL IS mos mme uerse mers Tees qu pes wrimRimas ws 2 wR ta pes wA HH mse pes wuam HHH om P pw ewm ANTI Teens e mo Jarama 3 2 wm fa CCOO CUSCO 4 ms P 9 bw mmu A 9 A A SERRE pes fuer 1 an fa es T wm anos MEL Ar o2 M o2 NR Table 4 46 Table 4 46 Es EN NI Le Eg LING 4 196 Instruction Set Summary eur CATS ANI CONCISA 7 CONCIENCIA 2 AAA ws mms E tt a EE CN RN NT yb m eu EL A CMPS An An CIO CS IC mrn po CI E em 03 3 998 Emo LL pe m qem H 999 I mw mm E p pomme T ms L L w CI m
203. drs Modify transfer status 1 MOV Rx adrs Load Rx with the value in data memory referred by addressing mode adrs Modify transfer status Table 4 23 Class 4b Instruction Description Cen ueni I DOE OO DOE 1 1 CMPB Rx imm8 Store the status of the subtraction Rx 8 bit positive constant into RZF and RCF bits of the STAT register Rx remains unchanged Table 4 24 Class 4c Instruction Description EIC DO arenis meae me or Sve Reina ban beste corser tren es ms DOE EN 1 1 CMP Rx imm16 Store the status of the subtraction Rx 16 bit positive constant into RZF and RCF bits of the STAT register Rx remains unchanged Table 4 25 Class 4d Instruction Description cw wem ose aug ADD Rx R5 Add R5 to Rx register Modify RX status ag SUB Rx R5 Subtract R5 from Rx register Modify RX status B0 MOV Rx R5 Load Rx with R5 Modify RX status 1 1 CMP Rx R5 Store the status of the subtraction Rx R5 into RZF and RCF bits of the STAT register Rx and R5 remain unchanged Assembly Language Instructions 4 35 Instruction Classification 4 4 5 Class 5 Instructions Memory Reference Class 5 instructions provide transfer to and from data memory and all registers except accumulators and Rx which are included in classes 1 and 4 The registers referenced for both read and write operations are the multiplier register MR the product high register PH the shift value reg
204. e Chapter 3 Peripheral Functions Chapter 4 Assembly Language Instructions Chapter 5 Code Development Tools Chapter 6 Applications Chapter 7 Customer Information Appendix A MSP50C605 Preliminary Data Appendix B MSP50C604 Preliminary Data U U E E U U U D m o Appendix C MSP50C605 Data Sheet Notational Conventions This document uses the following conventions Program listings program examples and interactive displays are shown inaspecial typeface similar to a typewriter s Examples use a bold Notational Conventions version of the special typeface for emphasis interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays such as prompts command output error messages etc Here is a sample program listing 0011 0005 0001 field 1 2 0012 0005 0003 field 3 4 0013 0005 0006 field 6 3 0014 0006 even Here is an example of a system prompt and a command that you might enter C csr a user ti simuboard utilities In syntax descriptions the instruction command or directive is in a bold typeface font and parameters are in an italic typeface Portions of a syntax that are in bold should be entered as shown portions of a syntax that are in italics describe the type of information that should be entered Here is an example of a directive syntax asect section name address asectis the directive This directiv
205. e mmea timerundertow o T INT6 and INT7 may be associated instead with the Comparator function if the Comparator Enable bit has been set Refer to section 3 3 for details 8 kHz Nominal Synthesis Rate 32 768 kHz oscillator reference ClkSpdCtrl Output Number of Number of IntGenCtrl PLLM Master Clock PDM CPUClock Sampling Instructs Instructs DAC PDMCD Over Sampling Register Rate Rate Rate Rate btwn DAC btwn 8 kHz Precision Bit Factor Value Hz Hz Hz Hz Interrupts Interrupts 2 10M 2 10M 1 05 M 8 19k 4 06 M 4 06 M 2 03 M 15 87 k 8 26 M 8 26 M 4 13M 32 26 k 16 38 M 16 38 M 8 19M 64 00 k 4 06 M 2 03 M 8 26 M 4 13M 16 38 M 8 19M 4 06 M 4 06 M 8 26 M 8 26 M 16 38 M 16 38 M 8 26 M 4 13M 4 13M 8 06 k 16 38 M 8 19M 8 19M 16 00 k 8 26 M 8 26 M 4 13M 8 06 k 16 38 M 16 38 M 8 19 M 16 00 k 16 38 M 8 19 M 8 19 M 8 00 k euwuns Jes uogoni su suoijonujsu ebenbue7 Ajquassy L0ec v DAC Precision IntGenCtrl PDMCD Bit 0 Over Sampling PLLM Register Value 0x 13 Ox 26 0x 4D 0x 9B Ox 26 0x 4D 0x 9B Ox 26 0x 4D 0x 9B 0x 4D 0x 9B 0x 4D Ox 9B 0x 9B Master Clock Rate Hz 2 62 M 5 11 M 10 22M 20 45 M 5 11 M 10 22M 20 45 M 5 11 M 10 22M 20 45 M 10 22M 20 45 M 10 22M 20 45 M 20 45 M PDM Rate Hz 2 62 M 5 11 M 10 22M 20 45 M 5 11 M 10 22M 20 45 M 5 11 M 10 22M 10 22M 20 45 M 10 22M 10 kHz Nominal Synthes
206. e Interrupt Priority INTO Ox7FFO DAC Timer Highest INT1 Ox7FF1 TIMER1 2nd INT2 Ox7FF2 TIMER2 3rd INT3 Ox7FF3 port Do 4th INT4 Ox7FF4 port D3 5th INT5 Ox7FF5 all port F eth INT6 Ox7FF6 port D4 7th INT7 Ox7FF7 port Ds Lowest Ox7FFE storage for ROM Protection Word RESET Ox7FFF storage for initialization vector p BB iiM Note ROM Locations that Hold Interrupt Vectors ROM locations that hold interrupt vectors are reserved specifically for this purpose Additional ROM locations Ox7FF8 Ox7FFD are reserved for future expansion Like the interrupt vectors they should not be used for general program storage a The branch to the program location that is specified in the interrupt vector is of course contingent on the occurrence of the trigger event Refer to Section Memory Organization RAM and ROM 3 1 5 Internal and External Interrupts for more information regarding the specific conditions for each interrupt trigger event The branch operation however is also contingent on whether the interrupt service has been enabled This is done individually for each interrupt using the interrupt mask bits within the interrupt general control register Refer to Section 2 7 Interrupt Logic for more details The ROM location Ox7FFF holds the program destination associated with the hardware RESET event branch happens after RESET LOW to HIGH The location Ox7FFE holds the read write block protection word Refer to Sec tion 2 6 4 ROM Code Secu
207. e any numeric value Addition subtraction and multiplication are allowed Examples 128 2 2 220 5 2 0x200 equates to OxAE 0x200 where 0x200 indicates data memory location 2 2 2 5 2 3 2 0x0F amp 0x04 equates to 0x15 Note that bitwise AND 8 operator and OR operator operation is allowed 10 2 5 0x120 expression points to data memory content at 0x120 and multiplies decimal 5 to it and finally adds decimal 20 Note that a space is required between successive asterisks Also note that 0x120 indicates content of memory location at 0x120 hex The grammer for expression and symbol is as follows number number 0 1 2 314151 6 71 81 9 expression number expression expression expression expression expression expression expression expression expression expression expression expression expression expression expression expression expression indicates bitwise complement 5 34 Assembler symbol is any alphanumeric text starting with an alphabetic character a number or an expression Examples SYM1 EQU 12 256 SYM2 EQU SYM1 32 4 SYM3 EQU SYM1 SYM2 0x200 From the above example SYM1 SYM2 and SYM3 are symbols for some ex pression The grammar for Symbol is as follows symbol expression symbol Expression Restrictions It is recommended that a space be inserted between the operator i e 8 and th
208. e crystal reference network between OSCjy and OSCour 22 pF 10 MQ 32 kHz 6 2 MSP50C614 MSP50P614 Initialization Codes 6 4 Before any kind of application code can be written the MSP50C614 MSP50P614 processor state must be initialized The initialization code is in it asm where file extension asm is for an assembly language file The entry point to the initialization routine is INIT DEVICE 614 This entry point must notbe called call INIT DEVICE 614 A jumpto this routine should be used jmp INIT DEVICE 614 After the end of initialization the routine always jumps to the main which is the beginning of MSP50P614 MSP50C614 user code It is recommended that INIT DEVICE 614 is per formed immediately after RESET to ensure that device initialization is always performed at RESET Users modifying the initialization routine is not recom mended The initialization routine does the following Disables all interrupts Y Zeros out all accumulators Zeros out all memory Starts oscillators at frequency 8 192 MHz If CRO_FLAG is 1 then crystal oscillator is started If CRO_FLAG is 0 then the resistor trim oscillator is started If resistor trim oscillator is chosen in P614 part then RESISTOR TRIM must be defined by the user this value is written under the P614 part Ifthe C614 partis used then the resistor trim is read from I O location RTRIM 0x2P Delays execution of the core for 200 ms
209. e has two parameters indicated by sec tion name and address When you use asect the first parameter must be an actual section name enclosed in double quotes the second parameter must be an address Square brackets and identify an optional parameter If you use an optional parameter you specify the information within the brackets you don t enter the brackets themselves Here s an example of an instruction that has an optional parameter LALK 16 bit constant shift The LALK instruction has two parameters The first parameter 16 bit con stant is required The second parameter shift is optional As this syntax shows if you use the optional second parameter you must precede it with a comma Square brackets are also used as part of the pathname specification for VMS pathnames in this case the brackets are actually part of the path name they are not optional Braces and indicate a list The symbol read as or separates items within the list Here s an example of a list pe psp que This provides three choices or Information About Cautions and Warnings Unless the list is enclosed in square brackets you must choose one item from the list Some directives can have a varying number of parameters For example the byte directive can have up to 100 parameters The syntax for this di rective is byte value values This syntax shows that byte must have at least one value pa
210. e processed according to priority after the completion of the RPT loop 0 lt ngx 255 String length for the string instruction is ng 2 All interrupts are queued during loop execution Queued interrupts are processed according to priority after the completion of the string instruction The maximum accumulator string length is 32 i e 0 ng x 29 O lt ng lt 255 NOTE 0 lt ng x 29 for accumulator strings The number of times the body of loop is executed is N oop 2 All interrupts are queued during loop execution Queued interrupts are processed according to priority after the completion of the BEGLOOP ENDLOOP block 0 lt NL oop lt 32767 String Instructions 4 8 String Instructions Class 1 2 3 and 6 instructions can have string modes During the execution of string instruction STR register value plus 2 is assumed as string length An accumulator string is a group of consecutive accumulators spanning from An to the next N consecutive accumulators N is the length ofthe string The STR register should be loaded with N 2 to define a string length N A value of zero in the STR register defines a string length of 2 string length 1 means the instruction is not in string mode Arithmetic string instructions treat the string as an N word arithmetic value The result is also an arithmetic value of the same length Conditionals are set as they would be set without string mode Comparing two strings is equivalen
211. e sign extension mode to normal mode Sets XM bit of STAT to 0 Assembly Language Instructions 4 157 Individual Instruction Descriptions 4 14 63 SFLAG Set Memory Flag Syntax iae rame Joes Geek ok wora w With RPT ok crass sme jme 3 1 3 1 NR L8 Execution memory flag bit at flagadrs data memory location 1 PC PC 1 Flags Affected None Opcode Instructions Pro Pis 14 fia 12 to o e v e s a a 2 1 Jo seLaG pagar tjoojstjis o tyo t tagacrs Description Set flag at addressed memory location flagadrs includes two groups of memory flag adrresses global flags which are the first 64 words in RAM and relative flags which are 64 locations relative to the page register R6 Flag address flagadrs only accesses the 171 bit See Also RFLAG STAG RTAG Example 4 14 63 1 SFLAG R6 0x12 Sets the flag bit of the RAM word addressed by R6 plus 0x0002 Note that R6 contains a byte address and 0x0002 is interpreted as a word offset 4 158 Individual Instruction Descriptions 4 14 64 SFM Set Fractional Mode Syntax a TOA l3 lI ws ls Execution STAT FM lt 1 PC PC 1 Flags Affected None Opcode instructions Pro 15 fra ra 12 HUD to o e v e 8 a js 2 1 pax ER EH ER EH RR ER ER KR foo ER KB EH EHS TH ERER Description Sets bit 3 the FM bit in status register STAT to 1 Enable multiplier shift mode for signed fractio
212. e symbol or numeric expression to perform arithmetic and bitwise operations For example ADD AO AO 1 2 adds a 1 to AO because the argument is read as 1 2 1 but writing the argument as 1 2 may or may not give the correct result Outside parenthesis are not allowed in instruction arguments For example ADD A0 A0 1 2 300 256 causes compile time syntax error But removing the outside parenthesis i e ADD A0 A0 1 2 300 256 Causes no error HELSE see IF and IFDEF ZEND FT This directive is created by the C compiler when it outputs assembly code to a file It marks the end of the function table used to track function calls and C variables in the emulator Users should NEVER use this directive in an assembly language program ENDIF marks the end of a conditional assembly structure started by IF or HIFDEF IF expression Start of a conditional assembly structure expression is an arithmetic expression that can contain symbols Caution since the conditional assembly is resolved during the first pass of the assembler no forward referenced symbols should be used in a conditional assembly expression l an expression is TRUE non zero then the lines following this directive are assembled until a ELSE or a ENDIF directive are encountered If an expression is FALSE equal to zero then all input lines are skipped until a ZELSE or a ENDIF directive are encountered If a ELSE directive is en
213. e transfer is through the internal databus the XSF and XZF flags are affected The SF flag is the sign flag and itis equal to the most significant bit of an accumulator when an accumulator instruction is executed ZF is the zero flag and is set when the instruction causes the accumulator value to become zero CF is the carry flag and is set when the instruction causes a carry A carry is generated by addition subtraction multiplication multiply accumulate compare shifting and some MOV instructions that have accumulation features CF is reset if no carry occurs after execution of an instruction OF is set when a computation causes overflow in the result It is reset if no overflow occurs during an accumulator based instruction Overflow saturation mode is set by the OM bit as explained in section 4 6 System Registers Table 4 1 Status Register STAT Bit 0 10 11 12 13 14 15 16 Name XM UM OM FM IM Reserved XZF XSF RCF RZF OF SF ZF CF TF1 TF2 TAG Function Sign extended mode bit This bit is one if sign extension mode is enabled See MSP50P614 MSP50C614 Computational Modes Section 4 6 Unsigned multiplier mode This bit is one if unsigned multiplier mode is enabled See MSP50P614 MSP50C614 Computational Modes Section 4 6 Overflow mode This bit is one if overflow saturation mode is enabled See MSP50P614 MSP50C614 Computational Modes Section 4 6 Fractional multip
214. e values in one of two forms 1 DIRECT REFERENCE AC Register 2 INDIRECT REFERENCE 0 15 points to 0 15 0 15 OFFSET pointsto 16 31 15 31 OFFSET points to 0 15 AP registers are served by a 5 bit processor for sequencing addresses or repetitive operations Selection between the 4 AP s is made in the 2 bit An field in all accumulator referenced instructions 2 2 2 8 String Operations The AP registers are served by a 5 bit processor that provides efficient sequencing of accumulator addresses The design automates repetitive operations like long data strings or repeated operations on a list of data When operating on a multiword data string the address is copied from the AP register to fetch the least significant word of the string This copy is then consecutively incremented to fetch the next n words of the string At the completion of the consecutive operations the actual address stored in the AP register is left unchanged its value still points to the least significant location The AP register therefore is loaded and ready for the next repeatable operation Data Memory Address Unit For some instructions the 5 bit string processor can also preincrement or predecrement the AP pointer value by 1 or 1 before being used by the accumulator register block This utility can be effectively used to minimize software overhead in manipulating the accumulator address The premodification of the address
215. eate a new project is to copy the entire MELP1 directory into another directory Rename the project file as desired eg NEWPROJ RPJ It is not necessary to change the paths of the files in the project this will be done automatically by the code development tool 6 3 1 Memory Overlay C614 release code uses memory overlay to accommodate multiple synthesis algorithms If the user is interested in using the data memory the starting memory location has to start from the last memory location used by the program 2 The synthesis code has a file named MAIN RAM IRX This file is provided for maintaining overlay New variables are added as follows bytes bytel equ RAMSTART CUSTOMER 1 byte2 equ bytel 1 words wordl equ byte2 2 1 word2 equ wordl 2 1 byte arrays arrayl equ word2 10 word arrays array2 equ arrayl 2 4 End of RAM RAMEND CUSTOMER equ array2 RAMLENGTH CUSTOMER equ RAMEND CUSTOMER RAMSTART CUSTOMER Two byte variables two word variables and two arrays are assigned storage space in realtion to the previous variable The last two rows must be present and the constant RAMEND CUSTOMER should equate to the name of the last used variable in the list Note that the C614 RAM is always accessed as byte therefore 1 word memory location is equal to 2 bytes Hence the multiplication by 2 Applications 6 13 ROM Usage With Respect to Various Synthesis Algorith
216. ed dest is An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordingly dest is aars XSF XZF are set accordingly src is adrs TAG bit is set accordingly Opcode aas 0 0000000100000 01018 02 MOVE An ad HERIT fol a as O eee ee MOVE ad An opele ee 5 05 S m mov anme HH G pro fo Toi a mma 3 move wmm E H H ED E m move Rims Toto lw telelelelel m eo Description Copy value of unsigned src byte to dest byte MOVB An adrs Move data memory byte to Ant MOVB adrs An Move An byte to data memory MOVB An imm8 Move immediate byte to Ant MOVB MR imma Move immediate byte to multiply register MR MOVB Rx imma Move immediate byte to Rx T Zeros loaded to upper 8 bits of An t Status flags are not modified See Also MOVU MOV MOVT MOVBS MOVS Example 4 14 29 1 MOVB AO R2 Copy data memory byte pointed by R2 to accumulator AO 4 122 Individual Instruction Descriptions Example 4 14 29 2 OVB R2 AO Copy lower 8 bits of accumulator AO to the data memory byte pointed by R2 Example 4 14 29 3 OVB AO Oxf2 Load accumulator AO with value of Oxf2 Example 4 14 29 4 OVB MR 34 Load MR register with immidiate value of 34 decimal Example 4 14 29 5 OVB R2 255 Load R2 with immidiate value of 255 decimal Assembly Language Instructions 4 123 Individual Instruction Descriptions 4 14 32 MOVBS Move Byte String from Source to Destination Syntax iae name
217. eger int 32768 32767 2 int i j Character char 0 255 1 char c d Array of integer int Not Applicable Not Applicable int array 12 Array of characters char Not Applicable forced to even char text 20 Pointer to integer int Not Applicable 2 int j Pointer to character char Not Applicable 2 char string Notes 1 Thereis a major difference between an MSP50P614 MSP50C614 integer string and an 5 9 3 External References array of integers an array of integers is an ordered set of n 16 bit integers whereas an integer string of length n represents a single integer with 16 n bits In C MSP50P614 MSP50C614 strings are declared as arrays of integers but must be operated upon using the special purpose string arithmetic functions described below As in regular C the above types can be qualified with the word unsigned There is another important qualifier that is special to C constant We made the mnemonic purposely different from the usual C constqualifier because it is not exactly equivalent It is used to initialize arrays in program ROM A good use of it would be for a sine table for example The syntax is simple for example constant int array 10 2 1 2 3 4 5 6 7 8 9 10 dummy will create a series of DATA statements in the assembly language output file Uninitialized constants like dummy above generate a warning and are initialized to zero Constants are to be handled with care Since they cannot be accessed the same
218. eger strings The same source file with the exception of the first line can be used for C or regular C In the case of regular C ithas to be compiled and linked with cmm func c define CMM must be present for C compiler ONLY ifdef CMM else include stdio h include lt stdlib h gt include string h include lt math h gt include cmm back h endif include cmm func h include cmm macr h Code Development Tools 5 51 Implementation Details constant int M1 4 0x04CB 0x71FB 0x011F 0x0 constant int M2 4 0x85EB 0x8FD9 0x08FB 0x0 cmm func string multiply int p int lgp int ml int lgml int m2 int lgm2 note length of p lgp 2 must be at least lgm1 2 lgm2 2 1 this function string multiplies string ml of length lgml 2 by string m2 of length lgm2 2 and puts the result into string p of length lgpt2 T int sign i J int mml mm2 pp sign 1 mml calloc sizeof int 1gm1 2 mm2 calloc sizeof int 1gm2 2 pp calloc sizeof int lgpt2 if test_string m1 0 1gm1 LTS_N neg string mml ml lgml sign 1 else copy string mml1 ml lgm1l if test string m2 0 1gm2 LTS N neg string mm2 m2 1gm2 sign 1 else copy string mm2 m2 1gm2 for j 0 j lt lgp 2 j p 3170 for i 0 i lt 1gm2 2 1 for j 0 j lgp 2 j pplj1 70 umul string amp pp i mm1 mm2 i lgm1 add string p pp p lgml ti 1
219. egister STAT All three multiplier registers PH SV and MR can be loaded from data memory and stored to data memory In addition data can be transferred from an accumulator register to the PH or vice versa Both long and short constants can be directly loaded to the MR from program memory The multiplicand is latched in a write only register from the internal data bus The value is not accessible by memory or other system registers Computation Unit Figure 2 3 Overview of the Multiplier Unit Operation MULTIPLIER UNIT INPUTS Multiplicand 16 bit latched in a write only register writeable and readable by Data Memory from one of the following sources as one of the following Data Memory MULTIPLYING MR Multiplier Registert 16 bit or e A coun alee SHIFTING SV e Shift Value Register 4 bit Offset Accumulator MULTIPLIER UNIT performs multiplication and barrel shifting MULTIPLIER UNIT INPUTS MSB 16 bit LSB 16 bit PH Product High PL Product Low readable and writeable by Data Memory a simulated register PL is realized in ALU A readable and writeable by ALU A t Also write able by Program Memory 2 2 2 Arithmetic Logic Unit The arithmetic logic unit is the focal point of the computational unit where data can be added subtracted and compared Logical operations can also be performed by the ALU The basic hardware word length of the ALU is 16 bits however most ALU instruct
220. elects between the three reduced power modes listed in Table 2 3 This control may be one of two bits depending on which oscillator reference is implemented in circuitry Refer to Section 2 9 3 Clock Speed Control Register When using the resistor trimmed oscillator RTO the reference oscillator enable appears as bit 8 in the ClkSpdCtrl register When using the crystal referenced oscillator CRO the reference oscillator enable appears as bit 9 in the ClkSpaCtrl register If both bits 8 and 9 are clear then no reference oscillator is enabled If either of bits 8 or 9 are set then the reference oscillator enable is considered set This enables the PLL circuitry to regulate to the reference frequency 32 kHz assuming the idle state clock control is clear Whichever state the reference oscillator is in before idle it remains in that state running or stopped after idle If the reference oscillator is left running during sleep however it comes at a cost to power consumption This may be a necessary cost if in your application elapsed time needs to be monitored during sleep MSP50C614 Architecture 2 35 Reduced Power Modes 2 36 The power consumed during sleep when the RTO oscillator is left running is greaterthan the power consumed during sleep when the CRO oscillator is left running If the idle state clock control is clear then the PLL circuitry active during sleep will attempt to regulate the MC to whatever frequency is program
221. embly Language Instructions 4 73 Individual Instruction Descriptions 4 14 Individual Instruction Descriptions 4 74 In this section individual instructions are discussed in detail Use the conditionals in Section 4 12 and the legend in Section 4 13 to help with individual instruction descriptions Each instruction is discussed in detail and provides the following information Assembler syntax Clock cycles required with or without repeat instructions Words required Limitation and restrictions Execution Affected flags Opcode Description Recommendation to other related instructions See Also field Examples 0 U O O U O U O U LU Individual Instruction Descriptions 4 14 1 ADD Add word Syntax Faber name dost st sertim eo wt Arh mmret net wn eoo Atri jvc PH ne abo aac ar nt nes T Does not affect the status flags Execution premodify AP if mod specified dest dest src for two operands dest src src for three operands PC PC w Flags Affected destis An OF SF ZF CF are set accordingly destis Rx RCF RZF are set accordingly src1 is adrs TAG is set accordingly Opcode DIT REN T ELEC E EIER ER ER TEE EC ERE ER ADD Ar An adrs next A EMPATA ENE EA adrs dma16 for direct or offset16 long relative see section 4 13 sien To I Denn TS ISTE E TET A x imm16 EO e pee a e e e e e aaa ppal EN e CER A ADD OOOO E Ol muc CA 0000000000 CE H HHEH CA E Assembly Langu
222. ents of the data memory location in adrs and to the lower 8 bits of the accumulator Zero fill the upper byte in the accumulator ALU status is modified Store the lower 8 bits of accumulator to the data memory location in adrs The data byte is automatically routed to either the lower byte or upper byte in the 16 bit memory word based on the LSB of the address Transfer status is modified Store the arithmetic status of the contents of adrs subtracted from accumulator into the ALU status bits The accumulator is not modified Look up the value stored in program memory addressed by the accumulator and store in the data memory location in adrs Transfer status is modified Multiply the MR register by the contents of adrs and transfer the lower 16 bits of the result to the accumulator Latch the upper 16 bits into the PH register ALU status is modified Load the MR register in signed mode from the data memory location in adrs In parallel subtract the PH register from the accumulator The string bit will string with the previous ALU status CF ZF but it will not load the string counter executes once ALU status is modified Load the MR register in signed mode from the data memory location in adrs In parallel add the PH register to the accumulator The string bit will string with the previous ALU status CF ZF but it will not load the string counter executes once ALU status is modified Assembly Language Instru
223. er instructions use DP to read coefficient data see section 4 10 any interrupt occurring between loading the first coefficient and the execution of a FIRK CORK will change the last value of DP if the interrupt routine uses a lookup instruction DP can be stored in RAM MOV adrs DP and a restoration is done as follows MOV An adrs SUB An 0x1 MOV An An Context save and restore of instructions are not required if filter instructions are not used Example 4 9 1 MOV AO 0x100 MOV AO AO DP 0x101 after execution gt RPT N 2 FIRK A2 RO Beginning of interrupt service routine context save MOV ctx DP DP ctx DP stores the present DP 0x101 Some lookup instructions i context restore MOV AO ctx DP DP 0x101 SUB AO 0x1 A0 0x100 after execution MOV AO AO DP 0x101 after execution IRET Input Output Instructions 4 10 Input Output Instructions The MSP50P614 MSP50C614 processor communicates with other on chip logic as well as external hardware through a parallel I O interface Up to 40 I O ports are addressable with instructions that provide bidirectional data transfer between the I O ports and the accumulators Data input is performed with the IN instruction Class 6 This instruction uses a memory address and a 4 bit port address It can also use an accumulator or offset accumulator and a 6 bit port address String transfers are allowed between the accumulato
224. erani m ae ES a Ct boone es pi Step 2 After setup runs the InstallShield see Figure 5 4 the setup window pops up see Figure 5 5 Step 3 Press the Next gt button to continue with installation or press Cancel to exit installation Code Development Tools 5 7 Software Installation Figure 5 6 Exit Setup Dialog Bs rase Step 4 Ifyou press Cancel you can return to setup by pressing Hesumebut ton You can exit setup by pressing Exit Setup button Figure 5 6 Figure 5 7 User Information Dialog Texas Instruments Texas Instruments Software Installation Step 5 If you continue with setup you will be brought to User Information dialog Enter your Name and Company Name in the two respective fields To get into this screen you must press yes to the license screen and press next to the Information dialog Step 6 Type any alphanumeric value as Serial number Press Next gt when done Press lt Backto goto the previous dialog Press Cancelto exit Figure 5 8 Choose Destination Location Dialog Choose Destination Location Ed Setup will install EMLICBxx in the following folder To install to this folder click Next Tipus to a different folder click Browse and select another folder You can choose not to install EMUC6xx by clicking Cancel to exit Setup Destination Folder C Program Files TISEMUCBxx Browse Step 7 Selectaninstallation directory by
225. ered as assembly language hence not compiled The insertion continues until a endasm directive is found Note that both asm and endasm must be at the beginning of a line and that all text following them on the same line is ignored Signals the end of assembly language insertion Must be paired with a asm directive Zifdef Zifndef Zif Zelse Zendif Starts conditional assembly if token following it has been defined not been defined by a define directive These directives are terminated by a endif directive and can be coupled with a else directive as in regular C Note that the test can only check if the named token is currently defined or undefined Starts conditional assembly if expression following it evaluates to a non zero value This directive is terminated by a endif directive and can be coupled with a else directive as in regular C See if directive Must be present to terminate a ifdef or ifndef directive Code Development Tools 5 43 C Compiler 5 9 5 Include Files There are currently two include files supplied with C cmm func h which contains function prototypes for the C functions and cmm macr h which contains some predefined macros Both files are listed below 8K KK ck kk ke ck kk ke ko ke ke ke ke e ke e e e ee e e x x f Prototypes for C functions KOK KKK Ck kk k kk AA cmm func add string t result int strl int str2 int lg in cmm func sub string int
226. ess 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C Field Description Device number Mask number assigned by TI Reserved Customer code version number Customer code revision number Year mask generated Data mask generated mm dd Example Value 0x0614 for C614 0x0005 0x0001 0x0005 e g version 1 5 0x1999 0x0816 e g 8 16 1999 Customer Information 7 7 Speech Development Cycle 7 3 Speech Development Cycle Figure 7 4 Speech Development Cycle Speaker Selection Speech Recording Software Writing Prototype Construction Speech Analysis Speech Editing Speech Evaluation Speech Specification Recording Script Software Design Preparation Hardware Design Software Debugging System Evaluation Asample speech development cycle is shown in Figure 7 4 Some of the com ponents such as speech recording speech analysis speech editing and speech evaluation require different hardware and software TI provides a speech development tool called the SDS6000 which allows the user to per form speech analysis using various algorithms speech editing for certain algo rithms andto evaluate synthesis results through playback of encoded speech Design of the software and hardware development of software and prototype construction are all customer dependent aspects of the speech development cycle 7 4 Device Production Sequence 7 8 For the speech development group at Tl
227. essor is similar to MSP50C614 The mapping is as follows Port Name IO Location MSP50C614 MSP50C605 Port A 0x00 General purpose bit configurable IO Data ROM data DRD Port B 0x08 General purpose bit configurable IO Data ROM page DRP Port G 0x2C General purpose 16 bit output Data ROM address DRA A 2 Features A 3 Architecture A 2 O U U U O U U U U U 30k word ROM customer program memory Approximately 1 835 Mbits data ROM 8 MHz uDSP core 32 input or output pins B 24 Pins general purpose bit configurable as input or output B 8 input pins with programmable 100 4 pull up resistors 1 bit comparator with edge detection interrupt service IMPORTANT Not currently supported PLL clock synthesizer Resistor trimmed oscillator or 32 kHz crystal 640 word RAM PDM DAC w direct speaker drive 32 Q Serial scan port for in circuit emulation monitor test The MSP50C605 uses the MSP50C614 core including breakpoint capability It has identical instruction sets and uses the same development tool MSP50P614 EPROM device is used for code development and testing MSP50C605 architecture is shown in Figure A 1 A 3 1 A 3 2 A 3 3 RAM ROM 1 O Pins Architecture The MSP50C605 like MSP50C614 has 640 17 bit words of internal data memory static RAM This RAM occupies a space extending from 0 to 0x27F in the address space The MSP50C605 contains 32K by 17 bit words of internal program ROM and 229 376 bytes by 8
228. est 0000h 0000h 0001h 0001h 0002h 0003h 0002h 0004h 0005h e e nnnn e e e e nnnn MS Byte LS Byte nnnn 1 Note Word address is data memory address or byte address divided by 2 17th Bit t Flag address always accesses the 17th bit of 17 bit wide data word in data memory Assembly Language Instructions 4 45 Bit Byte Word and String Addressing Flag address The flag or TAG address uses linear addressing from 0 to the size of data memory in 17 bit wide words 0 to 639 for MSP50P614 MSP50C614 Only the 17th bit is accessible When a word memory location is read the corresponding flag for that location is always loaded into the TAG bit of the status register STAT The flag address always corresponds to a 17 bit wide word address If string instructions are used then the flag bit of the last memory location of the string is loaded into the TAG bit of the status register Global flag addressing or relative flag addressing is used to address flags Flag bits can be set or reset using flag instructions in addition to various logical op erations The flag address does not have a string mode Rx post modifications Indirect addressing allows post modification of Rx For byte and byte string mode Rxis post modified by 1 for each byte For word and word string mode Rxis post modified by 2 for each word Post modification of Rx is not available for flag addressing Table 4 40 Data Memory Adaress and Data Relations
229. esults in an overhead of one instruction cycle per loop cycle compared to two instruction cycle if branching is used If ENDLOOP is used without any argument it assumes n 1 See Also BEGLOOP INTE Example 4 14 15 1 See Example 4 14 7 1 in BEGLOOP 4 96 Individual Instruction Descriptions 4 14 16 EXTSGN Sign Extend Word Syntax label name dest mod Clock clk With RPT clk MESES CST EZ O 1 1 3 1 99 E Execution premodify AP if mod specified new most significant word of dest STAT SF PC lt PC 1 Flags Affected None Opcode pese ODO masque senes ee Se SOC Pa AE e ar a peor KR s d a Description Copy accumulator sign flag SF to all 16 bits of An See Also EXTSGNS Example 4 14 16 1 EXTSGN A0 A Preincrement accumulator pointer APO Sign extend the accumulator AO Assembly Language Instructions 4 97 Individual Instruction Descriptions 4 14 17 EXTSGNS Sign Extend String Syntax eese CT SII mw 1 H E Execution new most significant word of dest STAT SF PC PC 1 Flags Affected None Opcode pause queer sepe peperere eps exrsensar UH U UDH CHU a fof f f f fofo a Description Extend the sign bit SF of most significant word an additional 16 bits to the left The accumulator address is preincremented internally causing the sign of the addressed accumulator to be extended into the next accumulator address This instruction ignores the string count
230. etween regular C and C to a minimum there are still a few that require some explanations 5 44 C Compiler 5 9 6 Function Prototypes and Declarations 5 9 7 Initializations 5 9 8 RAM Usage As mentioned above C function prototypes and declarations MUST be preceded with the keyword cmm func Also since all functions return through accumulator AO all functions are of type integer so that the function type can be omitted in the function declaration If present it is ignored anyway Trying to typecast a function as returning a pointer will result in a compiler error Note To change a C program back into a regular C program at least from the pointof view of function prototypes and declarations the following line can be inserted at the beginning of the C program define cmm func A library of regular C functions to substitute for the special MSP50P614 MSP50C614 functions is supplied with the C compiler allowing the user to compare the results of regular C programs with those of C programs The library is contained in the C source file cmm unc c It should be linked with the C equivalent of the C program and run in Borland C Due in part to the architecture of the MSP50P614 MSP50C614 processor initialization is only allowed for global variables As a side effect local static variables are not allowed For example a global array can be declared and initialized as f
231. executes 20 000 instructions before it briefly releases control to Windows the response to a stop command may take a few seconds The number of instructions executed ata timein Fast Run mode is a parameter in the EMUC6xx ini file Local Parameters nb fast instruction 220000 Run This menu option key equivalent CTRL F8 allows the user to execute a portion of the program windows until a breakpoint is encountered The windows are refreshed after every instruction animation so that the execution speed is rather slow If no breakpoint is encountered the user can stop the program by hitting the STOP option CTRL F10 in the debug menu Stop This menu option key equivalent CTRL F10 allows the user to stop execution of a program that was running fast or animated Do not use this option to halt a program that is running internally use the stop internal option instead Inspect This menu option is explained in section 5 6 3 under Inspect Window Show Hide Op Codes This menu option can be toggled to show or hide the opcodes in the program window Find Hardware Breakpoint Finds a hardware breakpoint from the list of hardware breakpoint A Hardware Breakpoint dialog box is opened and the presently enabled hardware breakpoint is selected as active This option is useful if you have multiple hardware breakpoint list but like to find which is currently active Find Next Breakpoint Finds the next software breakpoint from pre
232. f MOVB designates it as an instruction which uses byte addressable argu ments The byte addressable mode causes the hardware to read write either the upper or lower 8 bits of the 16 bit word based on the LSB of the address In this case the address is a byte address rather than a word address Bits O through 7 within the word are used so that a single byte is automatically right justified within the databus Bits 8 through 15 may also be accessed as the up per byte at that same address A third data addressing mode is the flag data mode whereby the instruction operates on only the single flag bit bit 16 at a given address All flag mode instructions execute in one instruction cycle The flags can be referenced in one of two addressing modes 1 global address whereby 64 global flags are located at fixed locations in the first 64 RAM addresses and 2 flag relative address whereby a reference is made relative to the current PAGE R6 The relative address supports 64 different flags whose PAGE offset values are stored in the PAGE register The flag mode instructions cannot address memory in the INDEX relative modes See Chapter 4 nstructions for more details 2 3 2 Data Memory Addressing Modes The DMAU provides a powerful set of addressing modes to enhance the per formance and flexibility of the C614 core processor The addressing modes for RAM fall into three categories Direct addressing Indirect addressing with post modi
233. f extraneous comment lines in the assembly code generated by the C compiler The Debugging option is checked the monitor routine output is sent to a dump file The Misc menu option allows the user to set a certain number of options for the emulator When this option is clicked a dialog box appears Figure 5 27 The Chip Select option allows the users to force a choice between the MSP50P60 and MSP50P614 MSP50C614 development systems Note that the development systems are automatically detected when the software is started as long as the development board is connected and powered up Default is MSP50P614 Windows related options are available in the Windows menu as shown in Figure 5 28 Software Emulator Figure 5 28 Options Menu im MSP50C6xx Code Development Tool EMU SHL RPJ Mi ES CPU Font RAM Font PGM Font J0 RPIFont e e G G OG G G G G e KA Verbose C C Denugging Decimal RAM Address oo V IDLEASNOF Figure 5 29 Miscellaneous Dialog List of directories separated by semicolons that the C compiler will search for include files enclosed in angl Include Directories C brackets lt gt before searching current o e c K Heap start address for C compiler Heap Start Hex OxFFFF 4 Beginning of Stack for C compiler Stack Start Hex Parallel port address where the Parallel Port Address Hex Scanport interface is connected Note
234. ferences with long constant fields operating on Rx and others ojojoj T Memory references with long constant fields operating on Rx and others 5 General mMemory reference instructions 6 I O port and memory reference instructions A Port memory reference Port accumulator reference 7 Program control instructions A Macro call instructions Conditional and unconditional jump instructions C Conditional and unconditional call instructions 8 Logical bit instructions Logical flag instructions Test status instructions 9 Miscellaneous instructions Filter instructions Miscellaneous short constant instructions Accumulator address instructions ojojoj T Other instructions 4 24 Instruction Classification Table 4 12 Classes and Opcode Definition Lom po epe o e 5 Te E EI IE wen o fo cm woe an am me om men fo oe sa am me om Down o po joe mm me U Coss ri o 9 waa am om I IS TT al Lows r1 po o ooo T pe Ee e Lows 1 o foal a I Posse por e lw pelelw ele leo Lowe 1 RR RR RR RRR RD e am x x Lose 1 1 CIO CIO CIO CO CO CO EA CO om D Lows ppp 5 om oe om SE 3 5 fo fos none m rx om _ Lowe rp pb po fijate vos le 63 a CO CI a a Comer Pipo o o 9 om ew prp TSTS i o m Liei Oee maaa E EE x UCA 1 9 9 E 1D E E99 E EEE E T Low 1 o o r r pee cm mew ar Low 1 ofo o w vl e a ee e Lows 1 be D p po o om Tole
235. fication QU Relative addressing The relative addressing modes appear in three varieties YU Immediate Short relative to the PAGE R6 register The effective RAM address is R6 a 7 bit direct offset O Relative to the INDEX R5 register The effective RAM address is R5 an indexed offset Long Immediate relative to the register base The effective RAM address is Rx a 16 bit direct offset Refer to Chapter 4 Instructions for a full description of how these modes are used in conjunction with various instructions MSP50C614 Architecture 2 13 Program Counter Unit 2 4 Program Counter Unit 2 5 Bit Logic Unit The program counter unit provides addressing for program memory onboard ROM It includes a 16 bit arithmetic block for incrementing and loading addresses It also consists of the program counter PC the data pointer DP a buffer register a code protection write only register and a hardware loop counter for strings and repeated instruction loops The program counter unit generates a ROM address as output The program counter value PC is automatically saved to the stack on various CALL instructions and interrupt service branches The stack consists of one hardware level register TOS which points to the top of stack The TOS is followed by a software stack The software stack resides in RAM and is addressed using the STACK register R7 in indirect mode see Section 2 3 Data Memory Address
236. for the data value while the extra bit is used as a status flag The C614 does not have the capability to execute instructions directly from external memory However additional program memory external ROM can be accessed using the general purpose I O The interface for external ROM must be configured in the software 2 6 1 Memory Map The memory map for the C614 is shown in Figure 2 7 Refer to Section 2 6 3 Interrupt Vectors for more detailed information regarding the interrupt vectors andto Section 2 7 2 Peripheral Communications Ports for more information on the I O communications ports MSP50C614 Architecture 2 15 Memory Organization RAM and ROM Figure 2 7 C614 Memory Map not drawn to scale Program Memory Data Memory Peripheral Ports 0x0000 Internal Test Code X0000 RAM 0x00 PAg_7 data RSS 640 x 17 bit 0x04 PAg_7ctrl 0x027F 0x08 PBg 7 data Ox07FF reserved 0x0800 0x0C PBo 7 ctrl 0x10 PCo 7 data User ROM 30704 x 17 bit 0x14 PCo 7 ctrl C614 read only 0x18 PDgo 7 data P614 EPROM oxic PDo_7 ctrl Ox7F00 0x20 PEQ 7 data Macro Call Vectors 0x24 PE 7 ctrl 255 x 17 bit overlaps interrupt 0x28 PFo_7 data vector locations 0x2C PGo_15 data Ox7FFO Usable Interrupt 0x2F RTRIM Vesp 0x30 DAC data 8 x 17 bit Ox7FF7 0x34 DAC ctrl Ox7FF8 Unusable Interrupt Vectors 0x38 IntGenCirl lad RESET vector Ox3A PRD1 0x3B TIM1 0x3D ClkSpdCirl Shaded boxes highlight dedicated ROM and conirol registers Ox3E
237. frf f rf fol1 Description Unconditional vectored call Macro call Push next address onto stack load PC with the content of the address obtained by adding vector8 to 0x7F00 The execution of the instruction continues from the new PC location RET instruction is used to return from VCALL RET cannot immediately follow VCALL IRET can be used instead of RET and IRET can immidiately follow VCALL VCALL is used to call frequently used routines and takes 1 word See Also RET IRET CALL Ccc Example 4 14 83 1 VCALL 0x7F02 Loads PC value with the program memory address stored in program memory location 0x7F02 4 180 Individual Instruction Descriptions 4 14 80 XOR Logical XOR Syntax abel name dest sr seri mod Sick cic Word w with RPT cc lass Tas aneas moerse rasos ta xo Jard aril miei next A o Jarl An Anl next or fen tragar HH HHH fea Dom Jen tc bd CE H Des Execution premodify AP if mod specified dest dest XOR src for two operands dest lt Src XOR src for three operands PC PC W Flags Affected destis An OF SF ZF CF are set accordingly dest is TFn TFn bits in STAT register are set accordingly src is adrs TAG bit is set accordingly src is flagadrs TAG bit is set accordingly Opcode Instructions 16 rs Pra Pra fra ri fro Fo e v e S a ya 2 fi fo SORS pf ebpljeielel ams x dma16 for direct or offset16 long relative see section 4 13 rama Japo Dreh D E D
238. g therefore would require the PDM rate to be 8 MHz This can be accomplished in two ways PDM rate 8 MHz Set the master clock to 8 MHz also ClkSpaCtrl Set the PDMCD bit to 1 1x master clock IntGenCtrl CPU clock rate will be 4 MHz PDM rate 8 MHz Setthe master clock to 16 MHz Set the PDMCD bit to 0 1 2 master clock CPU clock rate will be 8 MHz In the case of over sampling the same number of instructions are achievable between each INTO interrupt Not every INTO however requires an independently computed synthesis value hence the advantage in increased instruction capacity A 2 times over sampling means that every 2nd INTO requires a computed update from the synthesis algorithm The other INTO may be satisfied with an interpolating filter computation then a return to the main program As stated previously the maximum ensured CPU clock frequency for the C614 operates over the entire Vpp range This rate applies to the speed of the core processor Operating the processor higher than the listed specification is not recommended by Texas Instruments The following tables illustrate a number of possible combinations with respect to sampling rate PDM rate DAC resolution master clock rate and CPU clock rate The first table applies to the 8 kHz sampling rate and N times 8 kHz over sampling The second applies to the 10 kHz sampling rate and N times 10 kHz over sampling p
239. g multiplier shift mode for unsigned fractional or integer arithmetic Sets XM in status register to 1 enabling sign extension mode Set OM bit in status register to 0 disabling the saturating ALU operation normal mode 4 5 Bit Byte Word and String Addressing The MSP50P614 MSP50C614 has instructions which address bits bytes words and strings in data memory or program memory Data memory is always accessed in bytes by the hardware but is based on the instruction The data memory location is treated as a byte word or flag address There are five different kinds of addresses byte addresses byte string addresses word addresses word string addresses and flag addresses Each type of address is described below Refer to Figure 4 3 and Table 4 40 for reference Byte and byte string address Byte addressing is used to access individual bytes with an instruction in byte mode Such instructions have a suffix B at the end of instruction name for example ADDB MOVB etc A byte string 4 44 Bit Byte Word and String Addressing is a string of bytes The length of the byte string is stored in the string register STR To define the length of a string the STR register should hold the length of the string minus 2 For example if the length of a byte string is 10 then STR should be 8 A byte string address can be even or odd Byte string data is fetched from the lower address starting address one byte at a time to consec
240. g of the function table used to track function calls and C variables in the emulator Users should NEVER use this directive in an assembly language program AORG expression Marks the start of an ABSOLUTE segment code i e a segment that cannot be relocated by the linker expression evaluates to the starting address of the absolute segment in the program memory Assembler BYTE expression expression Introduces one or more data items of BYTE size 8 bits The bytes are placed in the program memory in the order in which they are declared CHIP TYPE chip name This directive is here for compatibility with future chips in the same family It defines some chip parameters like RAM and ROM size for the assembler For now the only defined chip names are MSP50P614 MSP50C614 and MSP50P614 MSP50C614 DATA expression expression Introduces one or more data items of WORD size 16 bits The words are placed in the program memory in the order in which they are declared Even though the program memory is 17 bits wide only 16 bits can be read using assembly instructions like MOV A0 A0 so the DATA directive only stores 16 bits per data expression DB expression expression Equivalent to BYTE directive DEF symbol symbol Equivalent to GLOBAL directive DW expression expression Equivalent to DATA directive END expression Expression defines the start up vector for the current assembly program This directive generates the follow
241. gadrs ANCHE pi ER i UH ERER ECH CCC C o nexA An i 1 a 4 fi Jo fafo po fata an ERER rojo Jato J fede Ae adrs 1 aa oreo fst org la ew oan 15 aa i t elo Io rea o pilla SHAPLS An e CA CECA A TIT E SHLSPL An adrs o i BEER adrs Nasal jo jajaja EH EE SHLAPL An adrs ka EN ER SHL An next A a EN o EN SHLSPL Anj An L nexta 1 SHLSPLS Ar adrs Lo X E o t t amn as dma16 for direct or offset16 long relative see section 4 13 SHLSPLS ATAT Arpa TTS TSTST SHLTPL An ada CIEN O fe ae s NN E amara or are or ofeert long lave see sector aaa sump EE E COCA aa aaa ES SHLTPLS An adr epppilepiae l Ix dma16 for direct or offset16 long relative see section 4 13 Assembly Language Instructions 4 193 Instruction Set Encoding mme METAS AMA az Sa saes anan SHRAG At Ann SHRAGS AA STAG adrs SUB Ar An adrs next A SUB Anr An imm16 next A SUB Anr An PH next A SUB Ar An An next A SUB An An An next A SUB Rx imm16 SUB Rx R5 SUBB An imm8 SUBB Rx imm8 S OR An An SUBS An An adrs SUBS WARE ums AMAN Am sums Anar An sums WAR VCALL vector8 XOR An adrs X imm16 next A XOR An An An next A XOR TFn flagadrs XOR TFn cc Rx XORB An mm XORS An adrs XORS An An p
242. gadrs Reset flag bit 17th bit from data memory referred by flag addressing mode flagadrs to 0 Table 4 32 SFLAG flagadrs Set flag bit 17 bit from data memory referred by flag addressing mode flagadrs to 1 Table 4 34 Class 8b Instruction Description Description cop Wemone MOV TFn cc Rx Load a logic value of the tested condition to one of the test flag bits in status register TF1 or TF2 1 OR TFA cc Rx Logically modify one of the two test flags in status register TF1 or TF2 by ORing it with the status condition specified 1 0 AND TFn cc Rx Logically modify one of the two test flags in status register TF1 or TF2 by ANDing it with the status condition specified 1 1 XOR TFn cc Rx Logically modify one of the two test flags in status register TF1 or TF2 by EXCLUSIVE ORing it with the status condition specified For this instruction the polarity of Not is inverted Not 1 for XOR Not 0 for XNOR 4 4 9 Class 9 Instructions Miscellaneous This instruction class includes all the remaining instructions that do not fit in the previous classes Some instructions have byte wide operand fields and others have no operands One subclass is a set of instructions that provide specific DSP functions FIR filters Another subclass provides some hardware software loop capability Ten instructions provide the means to set or reset five different status mode bits independently
243. gister The lower 16 bits of the result product low PL register is added to the destination accumulator or its offset This instruction propagates the shifted bits to the next accumulator SHLAPL An aars Shift data memory word left add PL to An SHLAPL Ar An next A Shift An left add PL to An See Also SHLAPLS SHLTPL SHLTPLS SHLSPL SHLSPLS Example 4 14 68 1 SHLAPL AO R4 R5 Shift the word pointed by the byte address stored in R4 by nsy bits to the left add the shifted value PL with accumulator AO store the result in accumulator AO Add R5 to R4 and store result in R4 PH holds the upper 16 bits of the shift Example 4 14 68 2 SHLAPL A2 R1 Shift the word pointed by the byte address stored in R1 by nsy bits to the left add the shifted value PL with the accumulator A2 and store the result in accumulator A2 Increment R1 by 2 PH holds the upper 16 bits of the shift Example 4 14 68 3 SHLAPL Al Al A Preincrement accumulator pointer AP1 Shift the accumulator A1 by ngy bits to the left add the shifted value PL to the accumulator and store the result in accumulator A1 After execution PH contains the upper 16 bits of the 32 bit shift Assembly Language Instructions 4 163 Individual Instruction Descriptions 4 14 69 SHLAPLS Shift Left String With Accumulate Syntax labe rame dest se eos ok Word w with Rer c Class snars aneas OO tes teves o starts ar
244. gister address 0x10 C7 C6 C5 C4 C3 C2 C1 CO C port control register address 0x14 C C C C CC C C D port data register address 0x18 D7 D6 D5 D4 D3 D2 Di DO D port control registert address 0x1C Cc CG CG CGC C C C C E port data register address 0x20 E7 E6 E5 E4 E3 E2 Ei EO E port control register address 0x24 Cc GC CG CG C C C C A7 B7 C7 D7 E7 data register C control register 0 IN 1 OUT 0x00 state of control register after RESET low T Ports Da and Ds may be dedicated to the Comparator function if the Comparator Enable bit is set If so then bits 4 and 5 of the D port Control register mustbe CLEAR Please refer to Section 3 3 Comparator for details Port Dg is connected to the branch condition COND1 Port D4 is connected to the branch condition COND2 assuming the comparator is disabled Please refer to Section 3 1 4 Branch on D Port and to Section 3 3 Comparator for more information External interrupts can be caused by transitions on ports Do D3 D4 and Ds The interrupts associated with the D port are supported whether those pins are programmed as inputs or as outputs Peripheral Functions 3 3 y o 3 1 2 Dedicated Input Port F 3 4 Port F is an 8 bit wide input only port The data presented to the input pin can be read by referring to the appropriate bit in the F port data register address 0x28 This is done using the IN instruction with the 0x28 address as an argu
245. give a 17 x 17 bit multiplication producing 34 bit result where the upper two bits 33d and 34th bits are the sign bits and discarded by the processor Sign extension is also applicable in string mode Sign extension mode is the recommended mode to use for signed number multiplication Example 4 6 1 SXM MOV AO 0x8000 MOV MR 0x8000 MULTPL AO AO This example illustrates the sign extension mode during multiplication Here two negative number 0x8000 are multiplied with 0x8000 to obtain a positive number 0x40000000 If the signs were not extended we would have obtained 0xC0000000 a negative number MSP50P614 MSP50C614 Computational Modes Example 4 6 2 SXM MOV STR 2 2 String length 2 MOV MR 0x8000 MOV AO 0x8000 A load MS Byte MOV A0 0x0000 A load LS Byte MULTPLS A0 AO This example illustrates the sign extension mode on a string during multiplication Here two negative numbers 0x80000000 and 0x8000 are multiplied to obtain a positive number 0x400000000000 If the signs were not extended we would have obtained 0xC00000000000 a negative number Unsigned Mode The multiplier unsigned mode may be enabled disabled by setting resetting the UM bit of the STAT When in unsigned mode the 1 7th bit of the multiplier is loaded as zero to indicate an unsigned value When UM is setto zero signed multiplication is enabled and the multiplier copies the MSB of the multiplier 16th bit to the 17th bit of the multiplier Examp
246. he entire program MELP speech at 1000 bps MELP speech at 2400 bps MELP speech at 2400 bps MELP speech binary format for external ROM Main user code User constants User RAM requirements Flags used to configure the 614 and set the resistor trim value Project file for the MELP1 program Applications 6 11 Texas Instruments C614 Synthesis Code 6 12 RAM Usage The file MAIN LST contains the variable RAM assignments Do a search for BEGIN_RAM to find the start of the RAM locations Adding Another Module There are three steps to adding a new module to a project First the project file RP J must be updated to include the ASM file click on File Insertto add files to a project Second the RAM overlay file MATN_RAM IRX should be updated with the RAM required by the new module And finally any functions which are called from MAIN ASM should be declared as external at the top of MAIN ASM Here the self extracting zipfile MELP2 ZIP contains the necessary extra files to implement the N factorial N function normally referred to as N shriek This function is called do shriek and is in SHRIEK ASM under the MODULES SHRIEK directory Under the MELP2 directory the file MAIN ASM should now contain the following two extra lines of code just below the shriek4 label shriek4 movb a0 4 call do shriek To test this code build the MELP2 project and program another P614 Set a breakpoint
247. he machine level instruction set is divided into a number of classes The classes are primarily divided according to field references associated with memory hardware registers and control fields The following descriptions give class encode bit assignments the OP code value within the class and the abbreviated field descriptions Some ofthe following symbols will be used repeatedly throughout this chapter as shown in Table 4 10 for additional information see section 4 13 Table 4 10 Symbols and Explanation Symbol Explanation Invert the bit of the source Used with flag addressing only adrs n The contents of the effective data memory address referred to by the addressing mode syntax If n is specified n bits are involved If unspecified data is 16 bits See Table 4 4 cc Condition code mnemonic used with conditional branch calls and test flag bit instructions Curly braces indicate this field is not optional flagadrs Flag addressing syntax as shown in Table 4 7 A Select offset accumulator as the destination accumulator if this bit is 1 A Can be either A or A based on the opcode or instruction A Select offset accumulator as source if this bit is 1 adrs Addressing mode bits am Rx pm See Table 4 4 An Accumulator pointed to by APn Accumulators cannot be referenced directly For example A22 is not valid since accumulators are only addressible though the accumulator pointers APO AP3
248. he software overhead associated with counting comparing and branching software controlled structures are very inefficient for short loops To ease this burden two basic types of hardware assisted loop structures are included in the MSP50P614 MSP50C614 processor Hardware loop instructions are summarized in Table 4 42 Repeatable instructions Most instructions can be repeated N 2 times with zero software overhead Repeated instructions are functionally identical to coding the same instruction N 2 times in sequence Repeat loops require a RPT instruction to set a count length N This immediately precedes the instruction to be repeated This next instruction is repeated N 2 times The RPT instruction is useful for clearing RAM locations filtering etc If the repeating instruction utilizes auto increments decrements to either Rx or AC registers i e R2 or A then the repeated modification controls will be permanent If the repeatable instruction is a string instruction then the string register STR will be replaced by N During the execution of a RPT instruction interrupts are queued Queued interrupts are serviced after the RPT operation completes according to their priority String instructions String loops are enabled by direct field decodes in classes 1 2b 3 and 6b and have no counter overhead These instructions automatically load the counter using the contents of the STR String instruction loops are different because they ass
249. hip Mode Address Used Data Order Rx Post modify Single byte Absolute 16 bit address 8 bit data 1 Byte string Beginning of string at lower address String length times 8 bit data 1 per byte in string by Incrementing addresses Single word Even address if odd address is used 16 bit data 2 the LSB bit of address is assumed 0 Word string Even address beginning at a lower String length times 16 bit data 2 per word in address if odd address is used the by incrementing addresses string LSB bit of address is assumed 0 Flag Address is considered as holding 17 bit 1 bit data not available data but only 17th bit is accessed Rx post modification is available by various addressing modes see 4 3 Instruction Syntax and Addressing Modes for detail Example 4 5 1 MOVB AO 0x0003 Refer to Figure 4 4 for this example This instruction loads the value 0x78 to the accumulator The upper 8 bits of the accumulator is padded with zeros Example 4 5 2 MOV AO 0x0000 MOV AO 0x0001 Refer to Figure 4 4 for this example Both instructions will load the value 0x1234 to the accumulator In word addressing the LSB bit of the address is assumed to be zero Thus in the second instruction the least significant bit of the address is ignored Example 4 5 3 MOV AO 0x0004 2 Refer to Figure 4 4 for this example The word address 0x0004 is referred Multiplication by 2 is necessary to convertthe word address into the equivalent byte address
250. ied as 2 20 Memory Organization RAM and ROM Nim 1 512 1 highest ROM address within the block to be protected Nim 1 512 lowest ROM address which is left unprotected NTM the value programmed at TM5 TMO true protection marker NFM the binary complement of NTM Nem the value programmed at FM5 FMO false protection marker The purpose of the true and false protection markers is to provide parity An erased P614 EPROM cell defaults to the value 1 Once programmed from 1 to 0 it cannot be programmed back to 1 unless the cell and all other cells along with it are subject to erasure A multi pass programming therefore can only lower the value stored at an EPROM address and never raise it Once a valid block partition address has been properly specified in both TM and FM itis impossible to change TM to another address and still maintain parity with FM mA Note Block Protection Mode When applying the block protection mode bits FM5 through FMO must be programmed as the logical inverse of bits TM5 through TMO respectively o Across the span of the 32k word ROM space there are 64 possible values for NTM including zero Hence the 6 bit wide locations for TM and FM The two single bit fields found within the block protection word are the block protection bit BP and the global protection bit GP If BP and GP are both SET erased then no protection is applied to the ROM If BP is CLEAR and GP is
251. if sign 1 neg string pp p STR LENGTH l1gp 2 7 copy string p pp STR LENGTH 1gp 2 5 free mm1 5 52 free mm2 free pp cmm func main int argc char argv int m1 4 m2 4 product 9 xfer const m1 M1 s xfer const m2 M2 8 R L ENGTH 4 R_LI ENGTH 4 Implementation Details string_multiply product STR_LENGTH 9 m1 STR_LENGTH 4 m2 STR_LENGTH 4 5 10 5 Programming Example C With Assembly Routines There are several important considerations when using the C compiler The ram allocation must be coordinated so that a location is not accidentally used twice In assembly this is usually done with IRX files by making each label equal to the location of the previous one plus whatever storage space is needed All of the IRX files for a project are then combined in a master IRX file so that the space for each sub file can be allocated For example a master IRX file RAM SIZE equ 640 STACK equ 2 RAM SIZE 14 BEGIN RAM equ 0 RESERVED equ BEGIN RAM 2 1 RAMSTART INT equ RESERVED include inter inter_ram irx RAMSTART ASM equ RAMEND INT include Nasm ram irx Here the sub files are inter ram irx and asm ram irx The allocation for inter ram irx begins at memory location 2 This is because the memory location O is reserved for use by the C compiler
252. ilizes the microswitches and LED s on a Speech Code Development Unit Waits for user input on the switches The correct sequence is MS7 MS9 MS7 MS10 If the correct Sequence is detected then all LED s will light for 5 seconds As soon as an incorrect sequence or portion of the sequence is detected the LED s will flash and the procedure will repeat Due to the indication of an incorrect sequence partway through there are only 4 combinations needed to find a sequence of length 4 The difficulty of determining the code could be increased greatly by using multiple key combinations MS7 and MS8 simultaneously for ex ample or by only indicating an incorrect code after the sequence is com plete Revisions Copyright c Copyright 1999 Texas Instruments Inc All Rights Reserved Ck Ck ck ck Ck ck ck kk ce ck ck Ck Sk KKK KKK KKK KKK KK KKK KKK KR KKK KKK KKK KKK KKK KKK KKK ck kk kk ck kk ko kk Sk Sk KKK KKK KKK endif include ramNram h cmm func asminit cmm func wait int x wait function x is ms cmm func oport int x int y output to a port cmm func cport int x int y configure a port 5 64 Implementation Details cmm_func iport int x read a port dnt ty jpk ply various temp and loop variables int x 4 array holding the correct key sequenc int locked 1 variable returned by lock cmm func lock x 0 OxEF MS7 x 1 OxBF MS9 x 2 Ox
253. in Table 2 7 J PLL circuitry master clock CPU clock and TIMERs are stopped Current draw from the Vpp is less than 10 uA in this condition Interrupt flag register IFR at address 0x39 is not automatically cleared Internal RAM is not automatically cleared Peripheral Functions 3 19 Hardware Initialization States 3 20 Fh II OS N A Note Internal RAM State after Reset The RESET low will not change the state ofthe internal RAM assuming there is no interruption in power This applies also to the interrupt flag register The same applies to the states of the accumulators in the computational unit _ _ AAA When RESET is brought back high again many of the programmable controls and registers are left in their default states RESET high just after low No reference oscillator is enabled PLL runs at its minimum achievable rate Master clock runs at a very slow frequency less than 100 kHz PLL multiplier is set to 0x00 renders slowest speed for MC once reference is enabled RTO oscillator trim bits are set to zero renders slowest speed for RTO once enabled Interrupt mask register is 0x00 Global interrupt enable is clear All Interrupts are disabled 1 O Ports A through E and output Port G have the same state as in RESET low All pull up resistors on input Port F are disabled DAC circuitry is disabled no PDM pulsing Both TIMER1 and TIMER are disabled Count down a
254. in port C becomes a data bus controlled by STROBE and R WZ externally Internally the port is used to transfer data between the core and the I O latches External interrupts can be caused by transitions on the PD2 PD3 PD4 and PD5 The interrupts associated with the D port are supported whether those pins are programmed as inputs or as outputs MSP50C604 Preliminary Data B 3 Architecture Figure B 1 MSP50C604 Block Diagram SCANIN Scan Interface SCAN OUT Break Point Emulation SCANCLK OTP Progra SYN TEST C604 only PGM PULSE P614 only DACp DAC 0x30 DACM 32 Ohm PDM RESET Initialization Logic OSC Reference Resistor Trimmed 32 kHz nominal Crystal Referenced 32 768 kHz PLL PLL Filter B 4 Vss VDD Vpp EP ROM 32k x 16 1 bit Test Area 0x0000 to reserved 0x07FF User ROM 0x0800 to Ox7FEF Ox7FFO to Ox7FFF INT vectors Instr Decoder PCU Prog Counter Unit CU Computational Unit RTOTRIM Register Ox2F TIMER1 PRD1 TIM1 Ox3A Ox3B TIMER2 PRD2 TIM2 0x3E Ox3F DAC Data Control ControlData 0x34 0x30 Clock Control 0x3D Gen Control 0x38 Interrupt Processor FLAG MASK 0x39 0x38 DMAU Data Mem Addr RAM 640 x 17 bit data 0x0000 to 0x027F G port 1 0 DATA 0x10 Control 0x14 C port 1 0 DATA 0x10 Control 0x14 Comparator 1 bit PD5vs PD4 D port 1 0 DATA 0x18 Control 0x1C PGO PCQ 7 INRDY PDO OUTRDY PDI STROBE PD2 R WZ PD3 PD4
255. in the IMR then the interrupt service associated with that interrupt is disabled Setting the bit in the IMR allows service to occur pending the trigger event which is registered in the IFR The IMR is accessible as part of another larger register namely the interrupt general control register peripheral port 0x38 After a RESET LOW the default value of each bit in the IMR is zero no interrupt service enabled A full description ofthe bit locations in the interrupt general control register can be found in Section 3 4 Interrupi General Control Register The IMR functions independently of the IFR in the sense that interrupt trigger events can be registered in the IFR even if the respective IMR bit is clear Both the IFR and IMR are readable and writeable as port addressed registers To read the register use the IN instruction in conjunction with the port address 0x38 or 0x39 Use the OUT instruction to write Refer to Section 2 6 2 Peripheral Communications Ports for more information MSP50C614 Architecture 2 23 Interrupt Logic 2 24 Note Setting a Bit in the IFR Using the OUT Instruction Setting a bit within the IFR using the OUT instruction is a valid way of obtain ing a software interrupt An IFR bit may also be cleared using OUT at any time ST aoe Assuming the global interrupt enable is set and the specific bit within the IMR is set then at the time of the interrupt trigger event an interrupt service br
256. incorrect results in FIR COR operations Overflow mode must always be reset The overflow bit of the STAT register may not be set For samples or filter coefficients that are signed the sign extension mode bit must also be set Use the following set up for the filterSTAT tag variable rovm Mandatory Any addition modes can be set hereafter sxm For signed samples coefficients filter output mov filterSTAT tag STAT The FIRK CORK instructions are almost identical to the FIR COR instructions The main difference is that the filter coefficients are placed in ROM instead of RAM In other words the filter coefficients are in a look up table As a result the R1 register is not used Before a FIRK CORK instruction executes the data pointer register DP must be set by the following code rovm reset overflow mode mov R5 2 N circular buffer length 3 words mov AO FIRK COEFFS Loads address of lookup table mov AO AO Loads first coefficient to AO and sets DP mov MR AO Load first coefficient in to MR register In the sequence of code above the DP register points to the first filter coeffi cient in program memory located at FIRK COEFFS This happens during the mov AO AO instruction In addition the DP register automatically incre ments to the next address It should be pointing to the second filter coefficient in program memory If the contents of the DP register are used somewhere else in the
257. increment Post increment R3 by 2 Example 4 14 42 2 MULSPL A2 A2 A Predecrement accumulator pointer AP2 Multiply MR register to accumulator A2 subtract PL from accumulator A2 and store result to accumulator A2 4 136 Individual Instruction Descriptions 4 14 48 MULSPLS Multiply String and Subtract PL From Accumulator Syntax as rame sess Taa ok Word w With RPT ck crass O wusms ates roere mesas Uo LT mute ant tz Execution PH PL MR src dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions Pro 15 sa fis i2 HD to o Js v e 8 a 3 2 fo MULSPLS An adr op GCOCE G s 1 x dma16 for direct or offset16 long relative see section 4 13 wutsPLSAn An tos rjo ojs t an o sjopog opo a a Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the ng 3 x 16 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register subtracted from dest string MULSPLS aars Multiply MR by data memory string subtract PL from An MULSPLS An An Multiply MR by An string subtract PL from An See Also MULSPL MULTPL MULTPLS MULAPL MULAPLS Example 4 14 43 1 MULSPLS A0 R3 Multiply MR with the contents of R3 subtract PL from accumulator string AO and
258. ing assembly code AORG OxFFFF DATA expression which defines the start up vector of the program i e the program address where execution starts following INIT of the chip label EQU expression Associates the value of expression with label EXTERNAL symbol symbol This directive is used to indicate to the assembler that one or more symbols are external references i e symbols that will be resolved by the linker GLOBAL symbol symbol This directive is used to indicate to the assembler that one or more symbols are global references These symbols MUST be defined in the current file and will be used by the linker to resolve external references present in other files GLOBAL should only be used for PROGRAM labels RAM variables are handled with the GLOBAL VAR directive GLOBAL VAR symbol symbol This directive can be used to allow for RAM variables to be referenced in a different file from where they were defined GLOBAL VAR should be used prior to defining a RAM variable with the RESW directive for example The variable to be referenced in another file Code Development Tools 5 37 Linker 5 8 Linker 5 38 should be declared there as EXTERNAL or REP Note thatthis technique can also be used to make constants defined with the EQU statement available to other files INCLUDE filename This directive is used to insert another file in the current assembly file The name of the file to be included must be enclosed in doub
259. ions can also operate on strings of 16 bit words i e a series or array of values The ALU operates in conjunction with a flexible 16 bit accumulator register block The accumulator register block is composed of 32 16 bit registers which further enhances execution and promotes compact code The ALU has two distinct input paths denoted ALU A and ALU B see Figure 2 4 The ALU A input selects between all zeros the internal databus the product high register PH the product low PL or the offset output of the accumulator register block The ALU B input selects between all zeros and the output from the accumulator register block MSP50C614 Architecture 2 7 Computation Unit The all zero values are necessary for data transfers and unitary operations All zeros also serve as default values for the registers which helps to minimize residual power consumption The databus path through ALU A is used to input memory values RAM and constant values program memory to the ALU The PH and PL inputs are useful for supporting multiply accumulate operations refer to Section 2 2 1 Multiplier The operations supported by the ALU include arithmetic logic and comparison The arithmetic operations are addition subtraction and load add to zero The logical operations are AND OR XOR and NOT Comparison includes equal to and not equal to The compare operations may be used with constant memory or string values without destroying any accumu
260. ionship 0000 c cece eee eee 4 46 MSP50P614 MSP50C614 Computational Modes 2000 cece eee eee eee 4 50 Hardware Loops in MSP50P614 MSP50C614 0c cece 4 54 Initial Processor State for String Instructions 00 0 eee eee eee ee 4 55 Lookup Instructions aiii Gary a A add ades dard 4 57 Auto Increment and Decrement K K e K K e K e en 4 73 Addressing Mode Bits and adrs Field Description o 4 73 Flag Addressing Syntax and BIts eee 4 73 Names Tor CO cicatrices 4 87 String FUNCIONS seins ia AA de e 5 46 MSP50C614 100 Pin PJM Plastic Package Pinout Description 7 3 MSP50C605 100 Pin PJM Plastic Package Pinout Description A 7 MSP50C604 64 Pin PJM Plastic Package Pinout Description aaua aeaa B 8 Contents XV Notes Cautions and Warnings MSP50C605 and MSP50C604 3 cede ease a P a er ud E qe ds 1 6 PGA Package tic ed deer eed tre e ole ta ROLE RR ee 1 13 ROM Locations that Hold Interrupt Vectors s ee 2 18 Instructions with References e 000 c cece eet eet eee eee 2 19 Block Protection Mode steria IRR ere ERR Re TERRA eee A a wae aed 2 21 Block Protections Word occiso e RR em A AR A A da 2 21 Setting a Bit in the IFR Using the OUT Instruction one 2 24 Interrupt Service Branch o occcccccccccccc hen 2 24 Writing to the TIM Register vg R N K 0 N 9 0 cece EN N R N N ee IIIA RIA Mn 2 27 ClkSpdCtrl B
261. is 16 bits wide The data is written in sign magnitude format Bit 15 of the register is the sign bit Bits 14 and 13 are the overflow bits Bits 12 through 3 are the data value bits The MSB is bit 12 and the LSB is bit 5 4 or 3 depending on the resolution DAC Data register Address 0x30 16 bit wide location Write Only 15 14 13 12 10 bit DAC resolution S O O M 9 bit DAC resolution S O O M D S 8 bit DAC resolution OO M D S Sign bit M Most significant data value D Data magnitude O Overflow bits L Least significant data value X ignored bits The overflow bits function in different ways depending on the drive mode selected The two DAC drive modes are informally named C3x style and C5x Peripheral Functions 3 9 Digital to Analog Converter DAC style Their selection is made at bit 3 of the DAC control register 0x34 The C3x style is selected by clearing bit 3 and the C5x style is selected by setting bit 3 The default value of the selection is zero which yields the C3x style The overflow bits appear in the DAC data register 14 and 13 to the left of the MSB data bit 12 In the C3x style mode the overflow bits serve as a 2 bit buffer to handle overflow in the value field bits 12 3 Any magnitude written to the value field which is greater than 1023 up to the limit 4095 lands a 1 in the overflow The overflow state when a 1 appears in either bit 13 or 14 yields the maximum PDM saturation
262. is Rate 32 768 kHz oscillator reference ClkSpdCirl CPU Clock Rate Hz 5 11 M 10 22 M 5 11 M 10 22 M 10 22 M Output Number of Number of Sampling Instructs Instructs Rate btwn DAC btwn 10 kHz Hz Interrupts Interrupts 10 24 k 19 97 k 39 94 k 79 87 k 9 98 k 19 97 k 9 98 k 19 97 k 9 98 k euwuns Jes uogoni su Instruction Set Summay 4 208 Assembly Language Instructions Chapter 5 Code Development Tools For code development purposes the programmable MSP50P614 is used The MSP50C6xx code development tool is used to compile link and debug assembly language programs This tool can also be used to program an MSP50P614 A reduced function C compiler called C is also available Topic Page Bal Unies WHOL nonwooneonanannondadomosAnnonsodnenaooonnonAannone 5 2 5 2 MSP Software Development Tool leeeueeeeeee 5 3 Be nequirementsm re TORTE nba oo 5 4 5 4 Hardware Installation aaa 5 5 5 5 Software Installation Rm reU EE 5 6 5 6 Software Emulator RTI 5 13 5 7FASsembler c ere CEPI CERTE TI 5 33 AA Carora ora eem 5 38 ICC nai 5 39 5 10 Implementation Details ooooooonorcconaccocan cos 5 48 5 11 Beware of Stack Corruption x sss x e x x K x x K x x K K K K Kee 5 67 5 12 Reported Bugs With Code Development Tool 5 67 5 1 Introduction 5 1 5 2 Introduction The MSP50C6xx develo
263. is used for code development and testing The architecture block diagram is shown in Figure B 1 B 3 1 B 3 2 B 3 3 RAM ROM 1 O Pins Architecture The MSP50C604 like MSP50C614 has 640 17 bit words of internal data memory static RAM This RAM occupies a space extending from 0 to 0x27F in the address space The MSP50C604 contains 32K by 17 bit words of internal program ROM The program ROM space is divided into two areas 1 The initial 2K words of ROM 0x0000 0x07FF is reserved for built in self test BIST that is provided by Texas Instruments during mass production 2 Customer can use the ROM from address extending from 0x0800 to Ox7FFF Restrictions on using certain program ROM location is shown in Figure B 2 The MSP50C604 has 14 output pins There are two different configurations for these pins host mode and slave mode In host mode 6 of the 14 pins are the same as pins PDO to PD5 on port D of the MSP50C614 The other 8 pins are the same as one of I O port C All of the functions of port D on the MSP50C614 are available on the MSP50C604 in cluding four interrupts the conditional branch control and the comparator In slave mode only PD4 and PD5 are be available for general purpose I O in cluding two interrupts and the comparator PDO PD1 PD2 and PD3 are used to control the slave mode interface internally and becomes INRDY OUTRDY STROBE and R WZ on the I O pinout respectively The other 8 p
264. ister A 0 or its offset A 1 Two of the four codes provided by the next A field will cause a pre increment or a predecrement of the accumulator register pointer AP prior to execution This preincrement is a permanent change to the referenced AP and further expands the use of the accumulator block as an efficient workspace Preincrements and predecrements are not available in string mode One ofthe four codes of the Anfield An 11 binary will cause the instruction to betreated as a multicycle string instruction This will not result in any perma nent modification to the referenced AP Since there is no reference to offset accumulators in Class 1b instructions the execution operates on memory and accumulators All other modes of control string preincrement predecrement AP data memory addressing modes etc are provided for logical byte multiply accumulate and barrel shift instructions Table 4 13 Class 1 Instruction Encoding aerea aja sio o cra rm ar _ as mew e r o gt 3 Table 4 14 Class 1a Instruction See Mnemonic Description O ADD An An adrs next A Add contents of data memory location referred by adrs to accumulator An ADDS An An adrs and store the results in the same accumulator An if A 0 or offset accumulator An A 1 ALU status is modified SUB Ar An adrs next A Subtract contents of data memory location referred by adrs from SUBS An
265. ister SV the status register STAT the top of stack TOS the string register STR and the four accumulator pointer registers APO to AP3 The data pointer register DP is read only since its value is established by lookup table instructions The RPT n repeat instruction is write only since repeated instructions cannot be interrupted IRET and RET instructions are read only operations for popping the stack and are included in this class because the stack is memory mapped Also included in this class are four flag instructions that modify flag memory and two instructions that multiply memory by MR storing the results in the PH register Table 4 26 Class 5 Instruction Encoding e RR ee ee EN NUN EAS ORE ECRIRE adrs lass 5 A A Table 4 27 Class 5 Instruction Description Mnemonic Description MOV adrs SV Store SV in the data memory location referred by addressing mode RM MOV aars PH Store the PH in the data memory location referred by addressing mode 0 1 MOV aadrs STAT Store the status STAT register contents to the data memory location referred by addressing mode adrs 17 bits including TAG No 0 1 1 MOV aars STR Store string STR register contents to data memory location referred by addressing mode adrs zero filled on upper 8 bits Transfer status is MOV aars APn Store the accumulator pointer APn register to the data memory location adrs zero filled on upper 12 bits Transfer
266. ith RPT ok Class mme ids Execution memory tag bit at adrs data memory location 0 PC PC 1 Flags Affected None Opcode RTAG adrs dma16 for direct or offset16 long relative see section 4 13 Description Resets tag bit at addressed memory location All addressing modes are available Note that this instruction accesses only the 17th bit of the RAM location For odd RAM byte addresses the least significant bit is ignored See Also STAG RFLAG SFLAG Example 4 14 61 1 RTAG 0x0200 2 Reset the tag bit of data memory word location to O Note that this operation can also be done with RFLAG by loading the R6 register with 0200 2 Example 4 14 61 2 RTAG R6 0x0002 Reset the tag bit of RAM location 0x0082 Assume R6 0x0080 Unlike the SFLAG and RFLAG instructions the argument of the STAG RTAG instruction is interpreted as bytes Example 4 14 61 3 RTAG R6 0x0003 Reset the tag bit of RAM location 0x0082 Assume R6 0x0080 4 156 Individual Instruction Descriptions 4 14 62 RXM Reset Extended Sign Mode Syntax iaa name o ok wora w win Rer c ass Px NR 9d Execution STAT XM 0 PC lt PC 1 Flags Affected None Opcode instructions U 14 18 r2 m to o 8 7 e s 4 3 2 1 xu i tt it eo Jo Ts fo fis Joo Jo Description Reset extended sign mode status register bit O the XM bit to 0 See Also SXM Example 4 14 62 1 RXM Resets th
267. its 8 and 9 css iiaeiai netted eet teens 2 31 Reference Oscillator Stopped by Programmed Disable 000 cece eee ees 2 32 Register Trimi Value siii ada Bana deta Beara ida Pio 2 33 Idle State Clock Control BIT 2 36 Reading the Data Register 2 2 cece eens 3 2 PON Enable Bi iii c a dut tte cia e b CS idos da ita a id aaa 3 9 IntGenCtrl Register Bit 15 aarre cnc 3 16 Internal RAM State after Reset 0 cette tte e eee e ees 3 20 Stack Pointer Initialization 2200 0 0 m 3 21 Data Memory ACCOSS s bier a a eis a ee ae he 4 45 Scan Port BONA Oul A K R N R L RR id Rcake xe ede Per APERAR PENA ERER RRR ao ene aes 7 2 MSP50G605 TT A 1 MSP50C604 1 ssbockUsbitbeh e E DP REM RE UA HRA neg eu ERa AHE sube elis salit ibid B 1 xvi Chapter 1 Introduction to the MSP50C614 The MSP50C614 C614 is a low cost mixed signal controller that combines a speech synthesizer general purpose I O onboard ROM and direct speaker drive in a single package The computational unit utilizes a powerful new DSP which gives the C614 unprecedented speed and computational flexibility compared with previous devices of its type The C614 supports a variety of speech and audio coding algorithms providing a range of options with respect to speech duration and sound quality Topic Page Features onthe Cona ter terete tein EIE 1 2 Us Jl US soonossovonararacacnoracanson ooo racona sanas nar 1 3 1 3 Development Version P614
268. its to the left and store the result in accumulator string AO Increment R1 by 2 at each execution to get the next memory value Example 4 14 74 3 SHLTPLS A1 A1 Shift the accumulator string A1 by nay bits to the left Assembly Language Instructions 4 169 Individual Instruction Descriptions 4 14 75 SHRAC Shift Accumulator Right Syntax label name dest src mod Clock clk With RPT clk SHRAC TA AL next A Execution premodify AP if mod specified dest src 1 PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions 6 5 14 13 12 11 jo o jo 7 Je a 4 fa 2 1 fo SHRAC Art Anii nextal_ 1 1 fo o nexta An oft jo o la a Description Premodify accumulator pointer if specified Shift source accumulator src or its offset to right one bit and store the result into dest accumulator or its offset MSB of result will be set according to extended sign mode XM bit in the status register Example 4 14 75 1 SHRAC A1 A1 Shift right one bit the accumulator A1 Example 4 14 75 2 SHRAC Al Al A Preincrement by one accumulator pointer AP1 Shift right one bit the newly pointed accumulator A1 and store result to offset accumulator A1 4 170 Individual Instruction Descriptions 4 14 76 SHRACS Shift Accumulator String Right Syntax iae name sess Ta ok Word w With RPT ck crass SHracs TAT Art Execution dest
269. k k k k kk k k ke KKK KKK KK RK KR KK KKK ke kc ko koc KKK KKK KEK KEK koc ke ck k ck koc k k kek KK Pause for lms Input Output Uses Calls wait200us g ACkCkckCROROACK Roe e RC Koo eoe oe deo RARE Koo oe ERE eoe oe KEKE deae seal sie eoe oe RRARERA RR eae waitlms Call wait200us Call wait200us call wait200us call wait200us call wait200us ret PRR RRR RRR ARRE RR RRE kk KKK KK kk RRE RR kc kk kk koc ke RR REA RAR RE EK KKK ke ke Pause for 200us Input Output Uses LRR RER R RR RR EKER NR RER RE RRR RER RR ERE RH KE wait200us rpt 256 2 nop rpt 256 2 nop rpt 256 2 nop rpt 256 2 nop rpt 256 2 nop rpt 256 2 nop rpt 64 2 Code Development Tools Implementation Details 5 63 Implementation Details nop ret SERRE RI ERA EB RIL BR RB ROT RRA BRL RR REERE EE REE RI TERR RR de BRR BR He ee Dummy interrupt routines p RRR RRR kk kk KEK RRR KKK KK RK KEK KKK KK KKK KKK KKK KKK KER KK RK ke kk KEK ke ke ke ke ke e e DAC_ISR IMER2_ISR IMER1_ISR PORTD2_ISR PORTD3_ISR PORTF_ISR PORTD4_ISR PORTD5_ISR DUMMY_ISR nop INTE iret Here is a sample C file that accesses the routines ifdef DOC_FILE Ck Ck ck ck Ck KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK kk ck kk KK KKK KKK KKK KKK File main cmm Version Release 1 00 25 MAY 99 Description Main routine for 614 lock demo Demonstrates use of assembly routines with C Ut
270. l 0 0 eee eee 5 67 6 Applications 2 etr ri rh Raum neues ene einen dee eae 6 1 6 1 JApplication CIICUIIS criar a E SERA RE RoR E NURA a AR 6 2 6 2 MSP50C614 MSP50P614 Initialization Codes 0 0 cece eee 6 4 6 2 1 Fileinit aSm icai eed ee arce duse donor d od ena awe 6 5 6 3 Texas Instruments C614 Synthesis Code cn 6 8 6 31 Memory Overlay hn 6 13 6 4 ROM Usage With Respect to Various Synthesis Algorithms o o 6 14 7 Customer Information 00 0 cece nnn nnn nnn 7 1 7 1 Mechanical Information La E KR EN E KE TATA R EA IH 7 2 7 1 1 Die Bond Out Coordinates sz R N iania R R R sens 7 2 7 1 2 Package Information c saa a 00 A 09 00 NER cece eee eee 7 3 7 2 Customer Information Fields in the ROM eee eee teens 7 7 7 8 Speech Development Cycle 20 0 0 e 7 8 7 4 Device Production Sequence cece nent een eens 7 8 7 5 Ordering Information 0 0 eee ss mh 7 10 7 6 New Product Release Forms e 7 10 A MSP50C605 Preliminary Data ssseeeeeeeeeee RR nnn A 1 AT JnOOdUCHON adria rie de ind D eser aa dq dees A 2 AQ RBeatulesS eiii AA AR A A 2 AS SATCDIOCIUTO siii A add bv dl beaded bees P de ER AA A 2 ASA BAM eet ER a onde tures beer RE Aaa Fire A 3 Ae ROM cata ated a telam LEE c EN AES E ES A 3 AS WO RIOS terse ct atts et ode idilio dd oa I MS MAIN AEN A 3 B MSP50C604 Preliminary Data sseeeeeeeee e
271. l Al 0x02A1 2 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Predecrement AP1 After predecrement A1 is AC20 and A1 is AC4 Sub tract the content of 0x02A1 0x1001 in data memory from AC20 and store resultto AC4 Final result AP1 20 AC4 AC20 0x1001 lt 0x3321 0x1001 0x2320 Example 4 3 8 MOV 0x012F 2 AO Refer to the initial processor state in Table 4 8 before execution of this instruc tion This is a table lookup instruction This instruction reads the program memory address stored in AO or AC2 and stores the data in data memory loca tion 0x012F Final result 0x012F 0x1B12 Example 4 3 9 MULR 0x02A1 2 Refer to the initial processor state in Table 4 8 before execution of this instruc tion Multiply MR with the contents of 0x02A1 The MSB of the result is stored in PH register and rounded The LSB is ignored Final result multiply MR e 0x02A1 0x1A15 e 0x1001 2 0x1A16A15 PH 0x01A1 4 3 5 Instruction Syntax and Addressing Modes Indirect Addressing Indirect addressing uses one of 8 registers RO R7 to point memory addresses The selected register can be post modified Modifications include increments decrements or increments by the value in the index register R5 For post modifications the register increments or decrements itself by 2 for word operands and by 1 for byte operands Syntaxes are shown in Table 4 9 Table 4 9 Indirect A
272. l Al 0x1220 Subtract program memory string at address 0x1220 from accumulator string A1 put result in accumulator string A1 Example 4 14 81 3 SUBS A2 A2 A2 Subtract accumulator string A2 from accumulator string A2 put result in accumulator string A2 Example 4 14 81 4 SUBS A2 A2 A2 Subtract accumulator string A2 from accumulator string A2 put result in accumulator string A2 Example 4 14 81 5 SUBS A3 A3 PH Subtract PH from accumulator string A3 put result in accumulator string A3 This instruction ignores the string count 4 178 Individual Instruction Descriptions 4 14 82 SXM Set Extended Sign Mode Syntax sw l3 l ws ls Execution STAT XM lt 1 PC e PC 1 Flags Affected None Opcode instructions U 14 r2 m to o 8 7 e 5 4 a 2 1 isxm tt apa ffs i Tt Js Jot fo is Joo Jo Jo Description Sets extended sign mode status register STAT bit 0 to 1 See Also RXM Example 4 14 82 1 SXM Set XM bit of STAT to 1 Now all arithematic operation will be in sign extention mode Assembly Language Instructions 4 179 Individual Instruction Descriptions 4 14 83 VCALL Vectored Call Syntax Ciao rame ses Glock ok wora w With RPT ok Class von ess 1l 2 1l 3 Tom l7 Execution Push PC 1 PC 0x7F00 vector8 R7 R7 2 Flags Affected None Opcode Instructions Pro fis 1 8 12 to o e v e S a js J2 Jo veatt vectors P fif
273. l registers after the breakpoint is reached If a change is made to the code the code will need to be updated and programmed into another device while erasing previous devices This cycle of programming debugging and erasing typically requires 10 15 devices to be in the eraser at any one time so 15 20 devices may be required to operate efficiently The windowed PGA version of the MSP50P614 is required for this debugging mode It is necessary to build preproduction application boards with a zero insertion force PGA socket that allows the device to be easily changed during software development Use the PGA package pin assignment shown in Figure 1 7 These preproduction boards also have the following requirements for the development tools to function properly 1 a 10 pin IDC header that connects the MSP50P614 to the MSP Scanport Interface should be provided 2 the VPP pin of the MSP50P614 must be pulled up to 5V with a diode so the development tool can apply 12V to this pin 3 The development tool must be allowed to toggle the reset pin without being loaded by any low impedance reset circuit This can be accomplished by inserting a 1K ohm resister between MSP50C6xx Software Development Tool the reset circuit and the reset pin and connecting the scanport reset signal directly to the reset pin See the recommended reset circuit shown in Figure 1 3 It is also recommended that all production boards be built with the scanport interface con
274. lacement string the given string is deemed defined this can be used in conjunction with the ifdef ifndef directives It is also possible to undefine a macro with the Zundefine directive With Arguments The macro name must be immediately followed by a pair of parenthesis which introduces the arguments This is completely compatible with the usual C definition Example define modulo i i96j Every occurrence of the word modulo followed by an expression in parentheses will be replaced by i j where i is the first argument in the parenthesis and j the second argument modulo a b c will thus be replaced by a b c The string following this directive is removed from the list of macros There is no warning if the string is not found in the macro list 5 9 4 3 5 9 4 4 5 9 4 5 5 9 4 6 5 9 4 7 5 9 4 8 5 9 4 9 include asm endasm C Compiler As in regular C this directive allows for the insertion of a file into the current file If the file name that follows is enclosed in gt the system searches the include directories for the file otherwise if it is enclosed in the current directory is searched Example include file h include lt stdio h gt The include directories are defined on the cmm_input structure passed to the compiler There is no limit to the nesting of include files All text following this directive is inserted as is in the output file and is consid
275. last value of RXeven points to the sample buffer location where the next sample can be stored FIRK CORK instructions FIRK CORK instructions work exactly the same was as FIR COR instructions however the coefficient array is located in program memory ROM Instead of loading RXeyen 1 with the pointer to coefficient array in RAM the data pointer DP is loaded with the value of the coefficient array Circular Buffering The easiest way to understand circular buffering is by example Suppose a filter h n has 3 coefficients Then theoretically to calculate one output sample of the filter the buffer should contain the current sample plus the past 2 samples Since the output y k for a three tap filter is y k h 0 ex k h 1 e X k 1 h 2 x k 2 On the C614 the circular buffer must contain N 1 samples In the above ex ample the buffer must contain 4 locations which is one more location than Special Filter Instructions theory requires The second to last RAM location in the circular buffer is tagged using an STAG instruction Below is an example of how to set up circu lar buffering with FIR or COR When using the FIR or COR instruction with circular buffering RAM needs to be allocated forthe circular buffer and the filter coefficients Therefore the filter coefficient RAM locations must be loaded into RAM and the circular buffer must be cleared before the first FIR or COR instruction is executed Set up for FIR
276. lator pointer APO Copy content of accumulator AO to word memory location 0x0200 Example 4 14 28 3 MOV 0x0200 2 A1 Transfer content of program memory location pointed by A1 to word data memory location 0x0200 Example 4 14 28 4 MOV A2 Oxf200 A Predecrement accumulator pointer AP2 Load accumulator A2 with immediate value Oxf200 Example 4 14 28 5 MOV A0 A0 Copy content of accumulator AO to accumulator AO Example 4 14 28 6 MOV A0 AO Copy content of accumulator AO to accumulator AO Example 4 14 28 7 MOV AO PH Copy content of PH to accumulator AO Example 4 14 28 8 MOV SV A3 A Predecrement accumulator pointer AP3 Copy content of accumulator A3 to SV Example 4 14 28 9 MOV PH A3 Copy content of accumulator A3 to PH Example 4 14 28 10 MOV MR A3 A Predecrement accumulator pointer AP3 Copy content of accumulator A3 to MR Example 4 14 28 11 OV Al A1l Transfer program memory value pointed by accumulator A1 to accumulator A1 This is a table lookup instruction Example 4 14 28 12 MOV 0x0200 2 RO Store content of RO to data memory word location 0x0200 4 118 Example 4 14 28 13 Load immediate word me Example 4 14 28 14 Load R7 stack register Example 4 14 28 15 Store RO to data memory Example 4 14 28 16 Transfer R5 to RO Example 4 14 28 17 Copy content of data me Example 4 14 28 18 Individual Instruction Descriptions OV R1 0x0200 2 mory address 0x0200 to
277. lator values 2 2 2 1 Accumulator Block The output of the ALU is the accumulator block The accumulator block is com posed of 32 16 bit registers These registers are organized into two terminals denoted accumulator and OFFSET accumulator The terminals provide refer ences for all of the data which is to be held in the accumulator block The accu mulator incorporates one half of the 32 accumulator registers ACO AC15 The OFFSET accumulator incorporates the other half AC16 AC31 2 8 Computation Unit Figure 2 4 Overview of the Arithmetic Logic Unit ALU INPUTS ALU A 16 bit ALU B 16 bit selects between selects between all 0 s O all 0 s Offset Accumulator Register Accumulator Register Data Memory Program Memory Product Hight Product Lowt ARITHMETIC LOGIC UNIT performs arithmetic comparison and logic ALU OUTPUTS THE ACCUMULATOR BLOCK Accumulator Register OFFSET Accumulator Register 16 16 bit registers 16 16 bit registers ACO AC1 AC2 AC3 ACA AC5 AC6 AC7 AC8 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 t For multiply accumulate operations 2 2 2 2 Accumulator Pointer Block There are four 5 bit registers which are used to store pointers to members of the accumulator block The accumulator pointers APO AP1 AP2 AP3 are used in two modes 1 as a direct reference to one of 32 or 2 as
278. le a 9 bit PDM DAC at 8 kHz sampling rate requires a PDM rate of 4 096 MHz There are four sampling rates which may be used effectively within the constraints of the C614 and the various software vocoders provided by Texas Instruments These are 7 2 kHz 8 kHz 10 kHz and 11 025 kHz Other sampling rates however may also be possible From the MC to the PDM clock there is an optional divide by two in frequency This option is controlled by the PDM clock divider in the interrupt general control register This means that the PDM rate can be set to run between 131 07 kHz and 33 554 MHz in 131 07 kHz steps the same as the MC Or the PDM rate can be set to run between 65 536 kHz and the maximum achievable CPU frequency see Chapter 8 MSP50C614 Electrical Specifications in 65 536 kHz steps The PDM clock divider determines which of these two ranges apply Within these ranges it is the PLLM which sets the rate CIkSpaCtrl Ox3D Refer to Section 3 2 3 PDM Clock Divider for more information regarding the PDM clock divider and the available combinations of CPU clock rates vs sampling rates Section 2 9 3 Clock Speed Control Register has more details regarding the PLLM 3 2 2 DAC Control and Data Registers 3 8 The resolution of the PDM DAC is selected using the control bits in the DAC control register address 0x34 The available options are 8 9 or 10 bits of res olution Bits O and 1 in the DAC control register control this option
279. le quotes If the file name itself is enclosed in angled brackets lt gt then the assembler will first look for the include file in the include directory list that is passed as an argument during the DLL call LIST The lines following this directive are included in the listing file extension Ist created by the assembler REF symbol symbol Equivalent to EXTERNAL directive label RESB expression This directive is used to reserve the number of bytes indicated by expression starting at the current RAM address Label is given the value of the current RAM address label RESW expression This directive is used to reserve the number of words indicated by expression starting at the current RAM address label is given the value of the current RAM address If the current RAM address is not EVEN the assembler increments it by 1 before allocating the desired amount Note that RAM locations are accessed by their BYTE address in MSP50P61 4 MSP50C614 assembly language i e word 1 is at address 2 etc RORG expression Marks the start of a RELATIVE segment code i e a segment that can be relocated by the linker expression is an arbitrary number but it must be present or an assembly error will occur STRING text string Equivalent to the TEXT directive but the text is terminated by a 0 automatically done by the assembler TEXT text string Equivalent to the BYTE directive but the data are a text string enclosed in double quotes
280. le 4 6 1 MOV A0 0x8000 MOVU MR AO MOV AO 0x80 MULTPL A0 AO In this example we do an unsigned multiplication between 0x8000 and 0x80 The first two lines set up the MR register with value 0x8000 and switch to unsigned multiplication mode Line 3 loads AO with 0x80 and line 4 multiplies the values in unsigned mode The lower 16 bits of the result is stored in AO and the upper 16 bits are stored in PH The final result is 0x400000 where PH holds the value 0x0040 and AO holds the lower 16 bits Notice that if the multiplication is not done in unsigned mode the MR is treated as negative We would have obtained OxFFC00000 PH OxFFCO AO 0000 which is the negative value of the previous result The key to unsigned multiplication is the MOVU instruction in the second line which set the UM bit to 1 in the STAT register and switches the multiplication mode to unsigned Overflow Mode The accumulator s overflow mode may be enabled disabled by setting resetting the OM bit of STAT When the computation is in the overflow mode and an overflow occurs the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator depending upon the direction of the overflow In string mode instead of representing the most positive or most negative value only the 16 bit MSB is set to OX7FFF or 0x8000 depending on direction of overflow The remaining words of the accumulator string are
281. length of 3 Final result A1 string 0x233EFBCA1223 0x9086EE3412AC 0xB3C5E9FE24CF AC5 0x24CF AC6 0xE9FE AC7 0xB3C5 STR 2 unchangea Notice that this instruction has accumulated a carry Special String Sequences There are two string instructions that have a special meaning If any of the following instructions MULAPL MULSPL MULTPL SHLAPL SHLSPL SHLTPL EXTSGNS MOVAPH immediately precedes ADDS An An PH and SUBS An An PH the following things happen 1 Carry generated by the preceding instruction is used in computation 2 Interrupts can occur between these instructions 3 Allinstructions in the sequence execute as a single string operation So An accumulator pointed by the first instruction of the sequence should be used for the remaining instructions in the sequence and changing the value of non one of the above instructions in the sequence has no effect 4 Accumulators used by ADDS and SUBS when used with PH auto incre ment internal registers not APn So subsequent ADDS and SUBS im mediately following instructions write into higher accumulators 5 The sequence ends with ADDS or SUBS used with PH 6 These sequences may not give same result when single step debugging because single stepping changes the internal state They should be used either with a hardware breakpoint or with fast run mode The breakpoint should be set after the sequence ends For example MULAPL AO A0 ADDS AO AO PH
282. les per tap The FIR FIRK instruction takes 2N clock cycles for N taps to execute once inside the RPT loop FIRK is useful for fixed filters and requires the minimum amount of data memory However the DP register may need to be context saved and restored since the filter coefficients are in ROM FIR is useful for adaptive filtering or applications where coefficients are provided from an external source FIR does not require a context save and restore for the DP register since both the buffer and the coefficients are in RAM COR and CORK instructions perform 16 x 16 bit multiplies and 48 bit accumulation in 3 clock cycles per tap Once inside the RPT loop the total number of clock cycles for an N tap filter is 3N The COR and CORK instructions are identical in operation and arguments to FIR and FIRK However an additional 16 bit extended accumulate cycle is added to prevent the arithmetic overflow common in auto correlation filters FIR COR instructions The execution of the filter instructions is shown in Figure 4 6 To use FIR COR instructions some initial setup is required Consecutive Rxpair RXeven RXeyen 1 should be chosen with B x aven pointing to the RAM sample buffer array and RXeyen 1 pointing to the RAM coefficient array The MR register should be loaded with the first coefficient h 0 FIR COR can now execute with a repeat instruction for N taps The value of RXeven is incremented during execution After execution the
283. lication shift mode This bit is set if fractional mode is enabled See MSP50P614 MSP50C614 Computational Modes Section 4 6 Maskable interrupt enable mode If this bit is zero all maskable interrupts are disabled Reserved for future use Transfer x equal to zero status flag bit In transfer instructions this bit is set if the operation cause the destination result to become zero excluding accumulator and Rx registers Transfer x sign status flag bit In transfer instructions the sign bit of the value is copied to this bit if the destination is not accumulator or Rx registers Indirect register carry out status flag bit This bitis setif an addition to the value of Rxregister caused a carry Indirect register equal to zero status flag bit This bitis set ifthe Rxregister content used by the instruction is zero Accumulator overflow status flag bit This bitis set if an overflow occurs during computation in ALU Accumulator sign status flag bit extended 17th bit This bit is set if the 16th bit the sign bit of the destination accumulator is 1 Accumulator equal to zero status flag bit 16 bits This bit is set to 1 if the result of previous instruction cause the destination accumulator to become zero Accumulator carry out status flag bit 16th ALU bit Test Flag 1 Test flags are related with Class 8 instructions discussed later Test Flag 2 Test flags are related with Class 8 instructions discussed later
284. ll be ns 2 See Also SHLS Example 4 14 70 1 SHLS AO Shift accumulator string AO to the left Accumulator content is not changed PH contains the upper 16 bits of the shifted result Assembly Language Instructions 4 165 Individual Instruction Descriptions 4 14 71 SHLSPL Shift Left With Subtract PL Syntax label name dest src mod Clock clk With RPT cik smsm aneao tables Teese ib SHLSPL TATA next A Execution premodify AP if mod specified PH PL src lt lt SV dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode raas 10 1 0101 0 5 8 E 0 510 0101 E 01 e ee x dma16 for direct or offset16 long relative see section 4 13 SHLSPL A A Len AL 1 1 fo o nexra An 1 1 Jo o Jo a A Description Premodify the accumulator pointer if specified Shift accumulator or data memory value pointed by adrs to left ngy bits as specified by the SV register into a 32 bit result This result is zero filled on the right and either zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the product high PH register The lower 16 bits of the result product low PL register is subtracted from the destination accumulator or its offset This instruction propagates the shifted bit to the next
285. ll instruction is included This instruction is similar to an unconditional call instruction When executed it pushes the PC 1 value to the STACK and loads a paged vector 7F loaded in the upper 8 bits of PC and an 8 bit vector number loaded into the lower 8 bits of the PC This makes the macro call a single word instruction that take 2 instruction cycles to execute This instruction is useful for referencing frequently used subroutines A normal RET instruction is used to return to the main program from macro calls Auxiliary register R7 STACK is used as the program stack pointer and is automatically incremented on calls and macro calls It is automatically decremented on returns Interrupts are vectored in the same way as macro calls The stack pointer is incremented when interrupts fire and decremented when an IRET is executed One side effect of the program stack s operation is that it is not permissible to return to a RET instruction Either the compiler inserts a NOP between such occurrences or the programmer must avoid this sequence Assembly Language Instructions 4 39 Instruction Classification Table 4 31 Class 7 Instruction Encoding and Description E NEJGEIEHEXENESHJESESXEAENEAEIEAENERES EP pp ppp e O vector8 doe ifofofopfofofna o m amp an o fo jo P r o x an e poleo eel e a a Erw 1 o Jo fo x a 0 cc names Description CC cc name Not cc name Z Conditional on ZF 1 S Conditional on
286. ma16 XORS An An An 4 194 t a jojo fa 4 Jo o A A A netaj An o fo t 4 pita a of fof 1foja Ja A ro An pt a fo a pee ree e ne us En An imma Low Jojo adrs rt fel fol fo fo fo fo lo Rep ew Lo An adrs Instruction Set Encoding instructions Te pis fra fra fi2 n 00 9 8 7 e 5 4 a 2 1 o zac An Lnext A tt ht t fo fo netA an o o o 1 t o o E ZACS Art E l frfofof an Jo ojo r s opo A cc names Description True condition Not true condition Conditional on ZF 1 Not condition ZF 0 Conditional on SF 1 Not condition SF 0 Conditional on CF 1 Not condition CF 0 Conditional on ZF 0 and CF 0 Not condition ZF 0 or CFzO0 Conditional on ZF 0 and CF 1 Not condition ZF 0 or CFz1 Conditional on SF 0 and ZF 0 Not condition SF 0 or ZFzO Conditional if ZF 1 and OF 0 Not condition ZFz1 or OF 0 Conditional if OF 1 Not condition OF 0 Conditional on RCF 1 Not condition RCF 0 Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCFz1 Conditional on RZF 1 Not condition RZF 0 Conditional on value of Rx 0 Not available on Calls Not condition RxzO Conditional on MSB of Rx 1 Not available on Calls Not condition MSB of Rx 0 Conditional on ZF 0 and SF 1 Not condition ZFz0 or SFz1 reserved reserved Conditional on TF1 1 Not condition TF1 0 Conditional on TF2 1 Not condition TF2 0 Conditional on TAG 1 Not con
287. mal immediate from accumulator A1 put result in accumulator A1 Example 4 14 79 2 SUB AO AO 2 A Pre increment pointer APO subtract 2 from new accumulator AO put result in accumulator AO Example 4 14 79 3 SUB Al Al Al Subtract accumulator A1 from accumulator A1 put result in accumulator A1 Example 4 14 79 4 SUB Al Al Al A Pre decrement AP1 Subtract accumulator A1 from accumulator A1 put result in accumulator A1 Example 4 14 79 5 SUB A3 A3 R4 Subtract word at address in R4 from A3 store result in A3 decrement value in R4 by 2 word mode after the subtraction Example 4 14 79 6 SUB R3 R5 Subtract R5 from R3 put result in R3 Assembly Language Instructions 4 175 Individual Instruction Descriptions 4 14 80 SUBB Subtract Byte Syntax iae ame sess crock ok wora w With RPT ok Class P suse ame WA a a mume l 3 a Execution dest dest imma PC PC 1 Flags Affected dest is An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordingly Opcode ET NN 65 BE su i Pep fee feta me TINI OOOO a Tee m Tere Description Subtract value of src byte from value of destbyte and store result in dest Note that subtraction is performed in 2 s complement and therefore the CF carry flag may get set even when subtracting a smaller value from a larger value SUBB An imm Subtract immediate byte from An SUBB Rx imm8 Subtract imme
288. me wes ann Tt Tt Ts fotos sa fe ol ofo ofo o Ea pem RE H ee X Description Subtract src7 string from src string and only modify the status flags Content of accumulators are not changed See Also CMPB CMP Jcc CCC Example 4 14 12 1 CMPS AO RO Compare string at data memory location pointed by RO to AO and change the STAT flags accordingly Example 4 14 12 2 CMPS Al 0x1400 Compare string at program memory location 0x1400 to A1 and change the STAT flags accordingly Example 4 14 12 3 CMPS A2 A2 Compare accumulator string A2 to accumulator string A2 and change the STAT flags accordingly Assembly Language Instructions 4 93 Individual Instruction Descriptions 4 14 13 COR Tabet reme CC eic c Word wine x ene Syntax Correlation Filter Function cor Awme d 3 dm foa Execution Flags Affected Opcode ma ee ae eo se ie ea ee peas With RPT N 2 mask interrupts RPT counter N 2 MR HO first filter coefficient x sample data pointed by Rxeyen h 1 second filter coefficient pointed by RXeyen 1 y result stored in three consecutive accumulators 48 bit pointed by An between every accumulation IF TAG 1 RXeven RXeven R5 for circular buffering ELSE RXeven if Rx is specified in the instruction ENDIF PC PC 1 final result Y co va MK XIN T R Execution is detailed in section 4 11 none om as mo s s sejrjo o a
289. med in the PLL multiplier see Section 2 9 3 Clock Speed Control Register The MC con tinues to run at this frequency even during sleep provided that the reference oscillator is enabled If the idle state clock control is set then neither the MC CPU clock nor the TIMER clocks run during sleep unless the TIMER source is linked to the reference oscillator Section 2 8 Time Registers These relationships are shown explicitly as a function of the reduced power mode in Table 2 4 Because the DAC circuitry is the single most source of power consumed on the C614 itis important to disable the DAC entirely before engaging any IDLE instruction This is accomplished at the DAC control register address 0x34 Refer to Section 3 2 2 DAC Control and Data Registers The ARM bit is another important control to consider before engaging the reduced power mode It is recommended that the ARM bit be cleared whenever the idle state clock control is clear and set whenever the idle state clock control is set Table 2 3 The set ARM bit causes an asynchronous response to all programmable interrupts when in the sleep state The cleared ARM bit yields the standard synchronous response at all times Affected interrupts include those tied to TIMER1 and TIMER2 as well as those tied to the inputs at Ports F Do D3 D4 and Ds The advantage to having the ARM bit set is that the device may be awakened by one of these interrupts even when the PLL clock circuitr
290. ment The state of the F port data registers after RESET low is unknown input state provided by external hardware Each of the pins at port F has a programmable pull up resistor The resistance of these pullups is at least 100 kQ All eight pullup resistors can be enabled by setting the enable pullup EP in the interrupt general control register Int GenCtrl The address of the IntGenCtrl is 0x38 and the location of the EP bit is 12 Clearing the EP bit disables the eight pullups and setting the EP bit en ables the eight pullups After RESET low the default setting for the EP bit is 0 F port pullups disabled Input Port F Data register address 0x28h Possible input data values Low 0 High 1 Possible output data values N A Value after RESET low Pullup resistors DISABLED When reading from the 8 bit F port data register to a 16 bit accumulator the IN instruction automatically clears the extra bits in excess of 8 The desired bits in the result will be right justified within the accumulator The following table shows the bit locations of the port F address mapping F port Input Data register address 0x28h 8 bit wide location READ only 07 06 05 04 03 02 01 00 F7 F6 F5 F4 F3 F2 F1 FO The external interrupt INT5 is triggered by a falling edge event on any of the eight port F input pins see Section 3 1 5 Internal and External Interrupts Specifically INT5 is triggered if all eight port F pins are held high and
291. mputation Unito 5 9 pe Te Terent eee 2 5 2 3 Data Memory Address Unit a 2 11 2 4 Program Counter Unit e essees ssa ss 2 14 2 See A EAE TT 2 14 2 6 Memory Organization RAM and ROM 2 15 2 70 Ica os ove ko sosopoovaconsanasoncansconabonoonaoDac or aanoa 2 22 7A UIE LSC Ste 2 26 ZINC OCC Eee s 2 29 2 10 Execution Timing se oo ao abans 2 33 2 11 Reduced Power Modes sesa aa em enn ntes sere 2 34 2 1 2 1 Architecture Overview The core processor in the C614 is a medium performance mixed signal pro cessor with enhanced microcontroller features and a limited DSP instruction set In addition to its basic multiply accumulate structure for DSP routines the core provides for a very efficient handling of string and bit manipulation A unique accumulator register file provides additional scratch pad memory and minimizes memory thrashing for many operations Five different addressing modes and many short direct references provide enhanced execution and code efficiency The basic elements of the C614 core are shown in Figure 2 1 In addition to the main computational units the core s auxiliary functions include two timers an eight level interrupt processor a clock generation circuit a serial scan port interface and a general control register Figure 2 1 MSP50C614 Core Processor Block Diagram Interrupt Inputs ll Peripheral Interrupt Flag Register IFR T Interface Multiplier MR t Shift Value
292. ms 6 4 ROM Usage With Respect to Various Synthesis Algorithms The following table lists some possible synthesis options and their ROM requirements The models assume that just enough program space as necessary for storage of the synthesis algorithm is used The remainder ofthe ROM is dedicated entirely to the speech data with the goal of maximizing the synthesis playback time If any two synthesis algorithms are to be used in combination e g MELP and LPC together then a separate allocation must be made for each algorithm within the same fixed pool of ROM The program space must hold two algorithms and the speech data is allocated in proportion to how much speech duration is used for each algorithm The bit rates and program sizes given in this table are only approximations The estimates are applicable at the time of this printing but they are subject and likely to change Also the data rate is sometimes dependent on the properties of the speech C614 Total ROM Storage gt 32 768 words BIST MELP program MELP speech data rate 2 4 k bits per second 2048 words 4 2 k words 26 k words 170 seconds of speech BIST CELP program CELP speech data rate 5 0 k bits per second 2048 words 6 k words 25kwords 79 seconds of speech BIST LPC program D6 LPC speech data rate 2 0 k bits per second 2048 words 1 5 k words 29 k words 230 seconds of speech BIST ADPCM program ADPCM speech data rate 32 0 k bi
293. n Store the value in MR to data memory byte location R7 0x0442 R7 re mains unchanged Final result 0x02A1 0x1A15 Instruction Syntax and Addressing Modes 4 3 7 Flag Addressing This addressing mode addresses only the 17th bit the flag tag bit located in data memory This addressing applies to Class 8a instructions as explained in section 4 4 Using flag addressing the flag bit can be loaded or saved In addition various logical operations can be performed without affecting the re maining 16 bits ofthe selected word Two addressing modes are provided The first addressing mode global flag addressing has bit O set to zero and a six bit field b1 b6 that defines the flag word address The second mode relative flag addressing has bit O set to one and a six bit field b1 b6 that defines the flag address relative to R6 see Figure 4 2 In other words the i e effective address contents of R6 6 bit offset In flag addressing R6 contains the address that points to the 17th bit This should not be confused with byte ad dresses and word addresses Figure 4 2 Relative Flag Addressing R6 PAGE register 6 Bit positive offset Syntax name dest src Global Flag name TFn dma6 name dma6 TFn Relative Flag name TFn R6 offset6 name R6 offset6 TFn Example 4 3 24 MOV 0x02 TF2 Take the test flag 2 bit TF2 in the status register and place it into the 17th bit of the data memory location 0x02
294. nal arithmetic Example 4 14 64 1 SFM Set fractional mode Set FM bit of STAT to 1 Assembly Language Instructions 4 159 Individual Instruction Descriptions 4 14 65 SHL Syntax Shift Left iae ame dest i mod TRR ok Word w With RPT ok crass Ll sh TAL next A Execution Flags Affected Opcode Instructions Pis U 14 13 12 10 o jo v Je s EH EH EHH premodify AP if mod specified PH PL src lt lt SV PC PC 1 OF SF ZF CF are set accordingly sul An pnetA LL i foto nexta An f f3f fofa fo Description See Also Example 4 14 65 1 Premodify the accumulator pointer if specified Shift accumulator word left nsy bits as specified by the SV register into a 32 bit result This resultis zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the PH register Accumulator content is not changed The lower 16 bit value PL is discarded The SHL instruction can be used with a RPT instruction but without much advantage since the instruction does not write back into the accumulator Use SHLAC for this purpose SHLS SHL A0 A Preincrement accumulator pointer APO Shift accumulator word AO to the left by SV bits Accumulator content is not changed PH contains the upper 16 bits of the shifted result 4 160 Individual Instruction Descriptions 4 14 66 SHLAC Shift Lef
295. nd period registers are 0x0000 The status register is partially initialized as specified in Table 3 1 Idle state clock control and ARM bit are both set to zero DO OOO D D D DD When in this state the processor runs albeit slowly It executes the following initialization routine then resumes execution of the program 1 ROM block protection word is read from address Ox7FFE 2 ROM block protection word is loaded to an internal register 3 RESET interrupt vector is read from address Ox7FFF 4 Program counter is loaded with the value read from 3 execution re sumes there Hardware Initialization States L I Note Stack Pointer Initialization The software stack pointer R7 must be initialized by the programmer so that it points to some legitimate address in data memory RAM This must be done prior to any CALL or Ccc instruction If this is not done then the first push pop operation performed on the STACK will render the Program Count er to an unknown state Table 3 2 State of the Status Register 17 bit after RESET Low to High Bits 5 through 16 are left uninitialized Bit Description 0 pm o e Extended sign mode disabled 1 pum o Unsigned multiplier mode disabled allows signed multiplier mode 2 pom poo Overflow mode disabled allows ALU normal mode 3 wl Shift mode for fractional multiplication disabled allows unsigned fractional integer arithmetic 4 pm o Global interrupt enable bit
296. nector footprint connected to the appropriate pins and VPP level translator circuit shown in Figure 5 1 This allows the MSP50C6xx Software Development Tools to facilitate any post production debugging The 10 pin connector transistor zenor diode and resistors can be added as needed The development tool must be allowed to toggle the reset pin without being loaded by any low impedance reset circuit This can be accomplished by inserting a 1 kQ resistor between the reset circuit and the reset pin and connecting the scanport reset signal directly to the reset pin See the recommended reset circuit shown in Figure 1 3 If this is not possible it would be helpful to provide an easy way to connect the MSP50C6xx scanport pins to an external level translator circuit and scanport connector Figure 5 1 Level Translator Circuit VDD 5 1 V Zener 100 kQ E Vpp q 2N2222 To 10 pin IDC header connecting to 10 kQ MSP50C6xx scanport 10 ko S TEST y To MSP50C6xx D Device 5 2 MSP50C6xx Software Development Tool The development tool software is a Microsoft Windows based integrated graphical development environment which includes the following Assembler Linker Make utility Debugger C compiler Application programming interface O O O O O LU Code Development Tools 5 3 Requirements 5 3 Requirements 5 4 The requirements for a complete MSP50C6xx development system are as follows PC Requirements O
297. nit All Except Breakpoints menu options It is provided as a convenience to fime programs Software Emulator being run in emulation mode STK field is the depth of the stack The emulator keeps track of number of calls and returns and changes this variable accordingly CUR field is the current subroutine name In C programs it becomes very handy to display local variables of a subroutine C Figure 5 19 Program Window mz MSP50C6xx Code Development Tool EMU SHL R Mill E3 rorg 0x00 0800 MOV TF1 NZF 0801 mov 0 tfiq 0802 rflag 0 0803 mov tfi 7 0 7 10uDoun 08042 IDLE 4 Yellow background Current Program Counter Black Instructions Red Software Breakpoint Gray background Instructions 0805 d a Program memory that cannot be stepped 7 7 Location 0806 mov sv 24 0807 mov ap0 0 080A mov a0 2 7 a 4 Cyan background Last line reached bv search Green background gt Hardware Find next String CTRL F12 Program Window The program window displays program instructions comments preprocessor text and program memory location The project must be built or made to view the instructions on the program window If the program is not properly built the emulator displays error message and launches the PFE EXE editor to correct the error The programmer should fix the errors save the new file and try to rebuild again The text in program window is
298. ns 2 40 State of Interrupt Controls Assuming Wake Up can occur before IDLE Instruction Destination of Program Counter after Wake Up e Global interrupt enable is SET Program counter goes to the location stored in the interrupt vector Respective IMR bit is SET associated with the waking Interrupt Global interrupt enable is CLEAR Program counter goes to the next instruction immediately following Respective IMR bit is SET the IDLE which initiated sleep e Global interrupt enable is SET Wake up cannot occur from the programmed Interrupt under these Respective IMR bit is CLEAR conditions If RESET low to high occurs then program goes to the location stored in the RESET interrupt vector Chapter 3 Peripheral Functions This chapter describes in detail the MSP50C614 peripheral function i e I O control ports general purpose l O ports interrupt control registers compara tor and digital to analog DAC control mechanisms Topic Page MIMO aaa 3 2 3 2 Digital to Analog Converter DAC eeeeeeeeeeeee 3 8 ICO Mi 3 14 3 4 Interrupt General Control Register x x ee eee 3 17 3 5 Hardware Initialization States eee 3 19 3 1 VO 3 1 3 1 1 1 0 The C614 has 64 input output pins Forty ofthese are software configurable as either inputs or outputs Eight are dedicated inputs and the remaining sixteen are dedicated outputs General Pu
299. nstruction address PC 1 mask interrupts PC PC 1 Flags Affected none Opcode pee e en ae ae to Se eee eee KEL eaor tt tt tt rfofofofofofofofafo Description This instruction saves the next sequential address in a shadow register and masks interrupts Interrupts occurring during execution of this and following instructions are actually queued until the loop is complete see ENDLOOP The loop executes N number of times Thus N 2 should be loaded in R4 in order to loop N times BEGLOOP and ENDLOOP block has following restrictions J No CALL instructions can be used Y All maskable interrupts are queued Y BEGLOOP ENDLOOP block cannot be nested See Also ENDLOOP Example 4 14 7 1 OV R4 count 2 init R4 with loop count BEGLOOP ADD AO AO AO add AO to AO count times ENDLOOP Initialize R4 with the loop count value minus 2 to repeat the loop for count times Execute the ADD AO AO AO instruction until R4 is negative R4 is decremented each time ENDLOOP is encountered When R4 is negative ENDLOOP becomes a NOP and execution continues with the next instruction after ENDLOOP 4 84 Individual Instruction Descriptions 4 14 8 CALL Unconditional Subroutine Call Syntax address Clock clk With RPT c k Execution R7 TOS TOS PC 2 PC pma16 or An R7 R7 2 Flags Affected None Opcode ps epe es m oases pees ERE oa X pma16 EA E EE E ES EE E EOS e EE Description PC
300. o 4 70 4 14 Individual Instruction Descriptions eeeeeee 4 74 A15 instruction Set Encoding eC Ee IT 4 187 4 16 Instruction Set Summary eeeeeeeeeeee 4 196 Introduction 4 1 Introduction In this chapter each MSP50P614 MSP50C614 class of instructions is explained in detail with examples and restrictions Most instructions can individually address bits bytes words or strings of words or bytes Usable program memory is 30K by 17 bit wide and the entire 17 bits are used for instruction set encoding The execution of programs can only be executed from internal program memory Usable program memory starts from location 800h The data memory is 640 by 17 bits of static RAM 16 bits of which are an arithmetic value The 17th bit is used for flags or tags 4 2 System Registers A functional description of each system register is described below 4 2 1 Multiplier Register MR The multiplier uses this 16 bit register to multiply with the multiplicand MOV instructions are used to load the MR register The multiplicand is usually the operand of the multiply instructions All multiply multiply accumulate instructions and filter instructions FIR FIRK COR and CORK use the MR register see Section 4 11 for detail 4 2 2 Shift Value Register SV The shift value register is 4 bits wide For barrel shift instructions the multiplier operand decodes a 4 bit value in the shift value register S
301. odes This includes global dma6 and relative R6 6 bit offset Both take only one clock cycle Possible sources of confusion Consider the following code ram0 equ0x0000 2 RAM word zero raml equ0x0001 2 RAM word one ram2 equ0x0002 2 RAM word two STAG raml MOV AO raml TAG bit is set in STAT register RTAG raml SFLAG raml This sets the TAG bit of ram2 MOV AO raml TAG bit is not set in STAT register MOV TF1 raml TF1 bit in STAT is set Explanation The first three instructions perform as you would expect The TAG bit is set at the RAM variable ram1 The TAG bitis set in the STAT register when the MOV instruction executes Finally ram1 s TAG bit is cleared The next two instructions are problematic When SFLAG sets the tag bit it will set the tag bit for the second word location ram2 This does not set the TAG bit for ram1 What is worse is that the value in ram1 must be less than 64 dma6 since this is global addressing for SFLAG To access TAG bits for high er RAM the R6 PAGE register is needed The last instruction is also confusing Why is TF1 setin the STAT even though ram1 s TAG bit is not set The answer is that this MOV instruction considers the src argument to be a word value instead of the usual byte value Thus this MOV instruction operates on ram2 rather than on ram1 Assembly Language Instructions 4 21 Instruction Classification 4 4 Instruction Classification T
302. oint to the return address after the previous BP is popped The return is performed by a RET instruction The calling routine is then responsible for moving the stack pointer to its previous location before the arguments were put on the stack Because all functions return via AO the only function return type allowed is integer Our implementation of C allows for function prototyping and checks that prototyped functions are called with the correct number of arguments Implementation Details Function declarations or function prototypes are introduced by the mnemonic cmm_func We only allow the new style of function declarations prototypes where the type of the arguments is declared within the function s parentheses For example cmm func bidon int il char i2 is valid but cmm func bidon il i2 int il char i2 is invalid Note The exact implementation of the MSP50P614 MSP50C614 stack is as follows on CALL 1 Increment R7 2 Transfer TOS top of stack register to R7 3 Transfer return address to TOS register on RET 1 next PC TOS 2 transfer R7 to TOS 3 decrement R7 We can freely manipulate R7 before a CALL Ccc and after a RET to load and unload arguments to and from the stack Of course it would be a bad idea to mess with the TOS register in the body of a function 5 10 4 Programming Example The following example implements string multiplication i e the multiplication of 2 int
303. olds the length of the string used by all string instruc tions MOV instructions are used to load this register to define the length of a string The value in this register is not altered after the execution of a string instruction A value of zero in this register defines a string length of 2 Thus a numerical value ng in the STR register defines a string length of ng 2 The maximum string length is 32 Therefore 0 lt ng lt 30 corresponds to actual string lengths from 2 to 32 4 2 12 Status Register STAT 4 6 The status register STAT provides the storage of various single bit mode conditions and condition bits As shown in Table 4 1 mode bits reside in the first 5 LSBs of the status register and can be independently set or reset with specific instructions See section 4 6 for detail about these computational modes Condition bits and flags are used for conditional branches calls and flag instructions Flags and status condition bits are stored in the upper 10 bits of the 17 bit status register MOV instructions provide the means for context saves and restores of the status register The STAT should be initialized to 0000h after the processor resets The XSF and XZF flags are related to data flow to or from the internal data bus If the destination of the transfer is an accumulator then the SF ZF CF and OF flags are affected If the destination of the transfer is Rx the RCF and RZF flags are affected If the destination of th
304. ollows int int_array 5 1 2 3 4 5 Initialization values are store in program memory RAM location 0 is reserved and used intensively by the compiler The choice of location O does not conflict with the usual definition of a NULL pointer 5 9 9 Variable Types As mentioned above there are strong restrictions to the variable types that are recognized by C 5 9 10 String Functions Arithmetic string functions are special functions that perform string arithmetic of all things The functions currently implemented are shown in Table 5 1 Code Development Tools 5 45 C Compiler Table 5 1 String Functions add string int result int strl int str2 int 1g adds strings strl and str2 of length lg 2 and puts the result in string result sub string int result int strl int str2 int 1g subtracts strings str2 from strl of length lg 2 and puts the result in string result mul string int result int strl int mult int lgl int lgr multiplies string strl of length lg1 2 by integer multiple and puts the result in string result of length ler 2 umul string int result int strl int mult int lgl int lgr same as previous one with UNSIGNED multiply or string int result int strl int str2 int 1g ors strings strl and str2 of length lg 2 and puts the result in string result and string int result int strl int str2 int 1g ands strings strl and str2 of length lg 2 and puts the result in st
305. on Example 4 3 15 MOVB R7 A3 Refer to the initial processor state in Table 4 8 before execution of this instruc tion Store the lower 8 bits of A3 AC29 in the data memory byte address pointed to by R7 R7 is then incremented by one Notice that to find the word address divide the address in R7 by 2 Final result R7 0x0101 0x0100 OxAB byte address or 0x80 OxABOO word address Example 4 3 16 OUT 0x08 R1 Refer to the initial processor state in Table 4 8 before execution of this instruc tion The contents of the data memory byte location stored in R1 are placed on port 0x08 port PPB R1 is then decremented by 2 Final result R1 Ox01FE 0x08 OxCB Port PPB is 8 bits wide so the upper 8 bits of R1 0x0A are ignored 4 3 6 Relative Addressing There are three types of relative addressing on the MSP50P614 MSP50C614 short relative long relative and relative to the index register R5 These ad dressing modes are described below 4 3 6 1 Relative to Index Register R5 4 16 This relative addressing mode uses one of the 8 address registers RO R7 as a base value The index register R5 is added to the base address value in Rx The base address register is not modified Thus the effective address is Rx R5 Syntax name dest src Rx R5 next A name Rx R8 src next A Instruction Syntax and Addressing Modes Rx x 0 7 Index Register R5 Example 4 3 17 AND AO
306. on premodify AP if mod specified dest dest src for two operands dest src src1 for three operands PC PC W Flags Affected dest is An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordingly src1 is adrs TAG bit is set accordingly Opcode Instructions te fas fra fra rz m o fo fa HDHH EH EHH RHH alL o o foleLalmerla mee P amar for aro or orar long rato se sexton ii ae nara an 2 3 To E SUB An AL PHL nex 1 1 oo netA An oli fofofofa a SUB AGL AS NU Ln Fifi i foo neta an olo tjo ojo o A SUB Art An AnLnexA o o neta An ofo 1fofofo a sus Ru immo 1 fofolofo m Jofo sus rers tlslrlelehe slolols ol mx Jofo Description Subtract value of src from value of dest and store result in dest If three operands are specified then subtract value of src1 from value of src i e src src1 and store result in dest string Premodification of accumulator pointers is allowed with some operand types Note that subtraction is performed in 2 s complement and therefore the CF carry flag may get set even when subtracting a smaller value from a larger value 4 174 Individual Instruction Descriptions SUB Ani An adis next A Subtract Product High PH register from An store result in An See Also SUBB SUBS ADD ADDB ADDS Example 4 14 79 1 SUB A1 A1 74 Subtract 74 deci
307. on Descriptions See Also ANDS ANDB OR ORB ORS XOR XORB XORS Example 4 14 4 1 AND A3 R4 And word at address in R4 to A3 store result in A3 Decrement value in R4 by 2 word mode after the AND operation Example 4 14 4 2 AND AO AO OxffOf A Predecrement accumulator pointer APO And immediate value OxffOf to register accumulator AO store result in accumulator AO Example 4 14 4 3 AND TF2 0x0020 AND global flag bit at RAM word location 0x0020 to TF2 in the STAT Store result in the TF2 bit in the STAT register Note that flagadrs cannot exceed values greater than Ox003F Example 4 14 4 4 AND TF1 TF2 AND TF1 with TF2 bit in the STAT register and store result in TF1 Assembly Language Instructions 4 81 Individual Instruction Descriptions 4 14 5 ANDB Bitwise AND Byte Syntax as ESE era TRET ss Execution dest dest AND src byte PC e PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode psu ferrer spe np moms h eee me 1 Description Bitwise AND src byte and byte stored in dest register and store result in dest register See Also AND ANDS OR ORB ORS XOR XORB XORS Example 4 14 5 1 ANDB A2 0x45 AND immediate value 0x45 to A2 byte mode Store result in A2 Upper 8 bits of A2 will be ANDed with zeros 4 82 Individual Instruction Descriptions 4 14 6 ANDS Bitwise AND String Syntax Jl name dest src src Clock clk With RPT c k Class ANDS An ad
308. onTF2 0 O XSpmar Rmo CendWondjumponvanderSE 1 IXNS parsi med __ ConditonalumponvansferSF 0 JXZ pma16 Rmo Conditional jump on transfer ZF 1 zero INZ pmai6T Amod Conditionat jump on vanster ZF 0 not equa IZ pma1ol amoa Onion jamp an ZE O INZ pmat6 Rmod CondiionaljumponzF 0 _ T Alternate mnemonics are provided as a way of improving source code readability They generate the same opcode as the original mnemonic For example JA jump above tests the same conditions as JNBE jump not below or equal but may have more meaning in a specific section of code See Also JMP CALL Ccc Example 4 14 27 1 JNZ 0x2010 Jump to program memory location 0x2010 if the result is not zero Example 4 14 27 2 JE 0x2010 R3 R5 Jump to program memory location 0x2010 if flag RZF 1 Increment R3 by R5 Since this jump instruction does not have a P at the end post modification is NOT reflected in the STAT register Thus if R3 becomes zero RZF is not updated Example 4 14 27 3 JIN1 0x2010 R1 Jump to program memory location 0x2010 if I O port address PDg pin has a value of 1 Decrement R1 by 2 Example 4 14 27 4 JTAG 0x2010 R2 Jump to program memory location 0x2010 if TAG bit of STAT is zero Increment R2 by 2 4 112 Individual Instruction Descriptions 4 14 27 JMP Unconditional Jump Syntax dest L mod Clock clk With RPT clk pmai6 Rx E EA ON Execution PC lt de
309. onstants Long constants 16 bits and long string constants differ in that ref erences are made to constants in the second word of the two word instruction word References made to a single 16 bit integer constant are immediate That is the actual constant value follows the first word opcode in memory For string constants the second word reference to the constants is immediate indirect which indicates that the second word is the address of the least significant word of the string constant This definition allows all long string constants to be located in a table and permits the reference in the machine language listing to be consistent with those of shorter constants Table 4 16 Class 2 Instruction Encoding a ae ee ats as aa era aj a CH E EIC fm me HHH OC ea III IS EC E E Table 4 17 Class 2a Instruction Description cm memos msn S ADDB An imm8 Add an 8 bit positive constant to the accumulator and store the result in the accumulator ALU status is modified ESEREN MOVB An imm8 Load an 8 bit Load an 8 bit positive constant into accumulator ALU status is modified constant into accumulator ALU status is Load an 8 bit positive constant into accumulator ALU status is modified SUBB An imm8 Subtract 8 bit positive constant from accumulator and store result accumulator ALU status modified CMPB An imm8 Modify ALU status with the result of 8 bit positive value subtracted from accumulator Original ac
310. oo OOO 000 000 OOO 0000000000000 0000000000000 0000000000000 uoommozircarszaz ooommozrzcarszaz 2 1312 1110987654321 123 45 6 7 8 9 1011 1213 top view bottom view Note PGA Package The PGA package is only available in limited quantities for development pur poses Introduction to the MSP50C614 1 13 Terminal Assignments and Signal Descriptions VDD Vss PCo PC5 PD4 PD7 PC4 PC3 PCG The pin assignments for the 120 pin PGA package P614 device only are out lined in the following table Refer to Section 1 6 for more information on the signal functions e Gra Peo 9 o EN Pos re ares or Exe vos ros Pes Pos ros Pea Poo sama nc p gt D UOUOmMmn nOTICAFS Z 1 2 3 E AM 4 5 6 7 8 9 10 11 12 ttis important to provide a separate decoupling capacitor for the Vpp Vss pair which services the DAC These pins are PGA numbers N3 and L4 respectively The relatively high current demands of the digital to analog circuitry make this a requirement Refer to Section 6 1 TBD for details Chapter 2 MSP50C614 Architecture A detailed description of MSP50C614 architecture is included in this chapter After reading this chapter the reader will have in depth knowledge of internal blocks memory organization interrupt system timers clock control mecha nism and various low power modes Topic Page 2 4 Architecture Overview reete aaa 2 2 2 29 Co
311. or Falling Edge as appropriate wakes device RESET LOW to HIGH always wakes device DAC Timer e Assuming PDM bit is clear as in D No wake up from DAC Timer The external interrupt is the other programmable option for waking the C614 from sleep The associated interrupt trigger event is in some cases a rising edge at the input port in some casesitis a falling edge Refer to Section 3 1 5 Internal and External Interrupts for a full description of these events Consider also the comparator driven interrupts described in Section 3 3 Comparator The input ports which are supported by external interrupt include the entire F Port and when programmed as inputs Ports Do D3 D4 and Ds Refer to Sec tion 3 1 O for a description of the various I O configurations Under normal operation the DAC timer when IMR enabled triggers an interrupt on underflow Before any IDLE instruction however the entire DAC circuitry should be disabled This ensures the effectiveness of the reduced power mode and prevents any wake up from the DAC timer MSP50C614 Architecture 2 39 Reduced Power Modes In orderto wake the device using a programmable interrupt the interrupt mask register must have the respective bit set to enable interrupt service see Sec tion 2 7 Interrupt Logic In some cases the ARM bit must also be set in order for the interrupts to be visible during sleep Table 2 3 After the C614 wakes from sleep the program counte
312. or battery powered operation Refer to Chapter 8 MSP50C614 Electrical Specifications for a full description of the electrical characteristics including the acceptable power supply ranges The reduced power state on the C614 is achieved by a call to the IDLE instruction The idle state is released by some interrupt event Different modes or levels of reduced power are brought about by controlling a number of different core and periphery components on the device These components are independently enabled disabled before engaging the IDLE instruction The number of subsystems left running during sleep directly impacts the overall power consumption during that state The various subsystems that determine or are affected by the depth of sleep include the Processor core which is driven by the CPU clock PLL clock circuitry PLL reference oscillator C614 periphery which is driven by the master clock TIMER1 and TIMER2 PDM pulsing LU U O O U LU Reduced Power Modes The deepest sleep achievable on the C614 for example is a mode where all of the previously listed subsytems are stopped In this state the device draws less than 10 uA of current and obtains the greatest power savings It may be awakened from this state using an external interrupt input port A number of control parameters determine which of the internal components are left running after the IDLE instruction In most cases the states of these controls may be mixed in any
313. ose Destination Location Dialog mI 5 9 ee quer 0 JO Q E GM O Ln Ln Ln Ln Gn Gn Gn C1 Gn A IN dd d d H LLb 1 DA o Figures Select Program Folder Dialog 0 0 eee eens 5 10 CODVINGUFIICS nce at eer A OR DI Poetis a Da 5 11 Setup Complete Dialog ssssseessssssssss RRR R NAR rn 5 12 Open Screen edes ea DRE an ob abl RE jtd das Pate 5 13 aired DP 5 14 Project Open Dialog 0 cece eee aR i Daoa 5 14 File Ment Options 222 pa A ia 5 15 MSP50P614 MSP50C614 Code Development Windows ssesssss 5 16 RAM WINDOW 42e ean ordre ia atada ee 5 17 CPU WindoW 2 aa bos 5 18 Program WIRdOW educere eeu eee ender eee a di 5 19 Hardware Breakpoint Dialog o oocooccccocccconcc III 5 20 Inspect Dialog iios ete sioe rs ram exer Dawe a M operate a M eU new sak 5 21 InSpect WIDngdOW sau ees et mtee edm eter en ng eder e esie edente leben a bud E beg 5 21 l O Ports WindOW scs p due O a ad ed rt 5 22 Debug MENU E IM 5 23 EPROM Programming Dialog teresi ser R 0 cc cece eee 5 25 Trace Mode ico A A A A a 5 26 Tata MENU OPTION sc ac ci de ada a 5 27 Options Men nitate td ia ia ai a Dd deeded ae 5 29 Miscellaneous Dialog arai irmis iada bacs sia dea mata i aaeoa III I 5 29 Windows Menu Options a a a RR iira dia nini a eiaa aeda i i i e a aah ai a aaa iag 5 30 Context Sensitive Help System annaa 5 31 100 Pin PJM Mechanical Information II 7 4 120 Pin Grid Array P
314. ot condition SF 0 or ZF 0 jojo 1 1 o E NE Conditional if ZF 1 and OF 0 Not condition ZFz or OF0 rela lada o NO Conditional if OF 1 Not condition OF 0 1 0 RC RNC Conditional on RCF 1 Not condition RCF 0 BHG RA RNA Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCFz1 1 1 0 RE RNE Conditional on RZF 1 Not condition RZF 0 anno RZP RNZP Conditional on value of Rx 0 Not condition Rx 0 1 1 0 RLZP RNLZP Conditional on MSB of Rx 1 Not condition MSB of Rx 0 anno L NL Conditional on ZF 0 and SF 1 Not condition ZF 0 or SFz1 1 1 110 reserved anna reserved 1 010 0 0 TFI NTF1 Conditional on TF1 1 Not condition TF1 0 11 fofolo 1 _ TF2 NTF2 Conditional on TF2 1 Not condition TF2 0 11 f ofo fifo TAG NTAG Conditional on TAG 1 Not condition TAG 0 11010 1 1 IN NIN1 Conditional on IN1 1 status Not condition IN1 0 1 1 0 IN2 NIN2 Conditional on IN2 1 status Not condition IN2 0 0000 Unconditional 1 1 110 reserved BHHBH reserved 1 1 0 XZ XNZ Conditional on XZF 1 Not condition XZF 0 HHRHH XS XNS Conditional on XSF 1 Not condition XSF 0 1 o 1 o xa XNG Conditonalon XSF 0 and XZF 0 Not condition XSFz0 or XZFz0 1 ERFSEEER reserved Individual Instruction Descriptions cc names Description eeiam Notwenania True condition Not true condition apa esa E eee Cp E ewe LL Description PC is replaced with second word operand if condition is true or unconditional If test condition is false a NOP
315. ound upper 16 bits t No status change See Also MULR MULAPL MULSPL MULSPLS MULTPL MULTPLS MULAPL Example 4 14 38 1 MUL AO A Predecrement accumulator pointer APO Multiply MR with accumulator AO and store upper 16 bits of the result rounded PH Accumulator AO is left unchanged Example 4 14 38 2 MUL R3 Multiply MR with the value pointed at by R3 and store the upper 16 bits of the result rounded into PH Decrement R3 by 2 4 132 Individual Instruction Descriptions 4 14 39 MULS Multiply String With No Data Transfer Syntax mus janig nws 1 ms 93 Execution PH PL MR src string PC PC 1 Flags Affected None Opcode Instructions Pie 15 14 J 13 12 11 o o o v e a a js 2 0 mues ar THEHR TH st Ao ifs fits foto fa o Description Multiply MR and the value in src The 16 MSBs of the ng 3 x 16 bit product are stored in the PH register The value in src is unchanged and the value in PL is ignored This instruction rounds the upper 16 bits Note that Anis a string of length ng 2 where ng is the value in STR register See Also MUL MULR MULAPL MULSPL MULSPLS MULTPL MULTPLS MULAPL Example 4 14 39 1 MULS AO Multiply MR with AO and store the upper 16 bits with rounding to PH register Assembly Language Instructions 4 133 Individual Instruction Descriptions 4 14 40 MULAPL Multiply and Accumulate Result Syntax label name dest src
316. ply to certain classes of instructions Class 8a They ad dress only the flag bit by either a 6 bit global address or a 6 bit relative address from the indirect register R6 If bit O of these instructions is O then bits 1 to 6 ofthe opcode are taken as the bit address starting from data memory location 0000h If bit O is 1 then bits 1 to 6 are used as an offset from the page register R6 to compute the relative address Bits 0 to 6 of flag instructions are written as flagadrs throughout this manual When this symbol appears it should be replaced by the syntax and bits shown in Table 4 7 For example AND TFn flagadrs can be written as follows not all possible combinations are shown AND TF1 0x21 global flag addressing flag address is 0x21 absolute AND TF2 R6 0x21 relative flag addressing flag address is R6 0x21 absolute Table 4 7 Flag Addressing Field flagadrs for Certain Flag Instructions Class 8a B flagadrs flag addressing mode encoding flagadrs Flag mn Addressing Clocks _ ge Mets oret Sm s Ts e efe po Modes clk flag address bits g r z EC E A AB E tnp is RPT argument 4 12 Instruction Syntax and Addressing Modes 4 3 3 Immediate Addressing The address of the memory location is encoded in the instruction word or the word following the opcode is the immediate value Single word instructions take one clock cycle and double word instructions take two clock cycles Syntax name
317. pment tools gain access to the core controller via a serial scan interface called the Scanport The basic elements needed to do de velopment with the MSP50C6xx devices are listed below in Section 5 3 The MSP50C6xx software development tool is included with the MSP scanport in terface TI part MSPSCANPORTI F or MSPSI The mask programmed MSP50C6xx devices are available in die form to sup port large volume production quantities The MSP50C614 605 devices are available in a 100 pin 14x20 mm quad flat pack QFP and the MSP50C604 is available in a 64 pin 10x10 QFP for medium volume application The MSP50P614 is an EPROM based version of the MSP50C614 andis available in a 120 pin windowed ceramic pin grid array package This EPROM based version of the device is only available in limited quantities to support software development Since the MSP50P614 program memory is EPROM each per son doing software development should have several of these PGA packaged devices The MSP50C6xx software development tool supports non real time debugging by scanning the code sequence through the MSP50C6xx scanport without programming the EPROM However the rate of code execution is limited by the speed of the PC parallel port Any MSP50C6xx device can be used in this debugging mode The MSP50P614 EPROM must be programmed to debug the code in real time The MSP50C6xx software development tool is used to program the EPROM set a breakpoint and evaluate the interna
318. pressing the Browse button if the default directory is not desired Setup automatically created the installation directories Step 8 Press Next to continue with installation Code Development Tools 5 9 Software Installation Figure 5 9 Select Program Folder Dialog Select Program Folder x Setup will add program icons to the Program Folder listed below You may type a new folder name or select one from the existing Folders list Click Next to continue Program Folders MSP50C6xx Code Development T ool Existing Folders 3Com NIC Utilities Accessories Adobe Acrobat T430 Beyondh ail Borland C 4 52 Borland C 5 02 Borland C Builder Borland C Builder 4 Y lt Back Cancel Step 9 Enter a new folder name in Select Program Folder dialog Step 10 Press Next to continue with installation 5 10 Software Installation Figure 5 10 Copying Files M biis Grobe be gier Te WSPAOCvx Code Development Tool Step 11 The program starts installation When the installation is complete an icon is also created on the desktop Code Development Tools 5 11 Software Installation Figure 5 11 Setup Complete Dialog 5 12 Step 12 The Setup Complete dialog message is displayed when setup is completed Press the Finish button to complete the installation Software Emulator 5 6 Software Emulator Run the EMUC6xx exe program which will be in the installation direc
319. pt trigger event will not be capable of waking the device from sleep Note also the state of the idle state clock control bit and the ARM bit if you expect to wake up using either type of interrupt internal or external In most cases the state of these bits should coincide Table 2 3 Reduced Power Modes The interrupt trigger event associated with each of the two internal TIMERs is the underflow condition of the TIMER In order for a TIMER underflow to occur during sleep the TIMER must be left running before going to sleep In certain cases however the act of going to sleep can bring a TIMER to stop thereby preventing a TIMER induced wake up The bottom row of Table 2 4 illustrates the various conditions under which the TIMER will continue to run after the IDLE instruction Notthat the reduced power mode DEEP leaves both TIMERs stopped after IDLE This mode cannot therefore be used for a timed wake up sequence Table 2 5 How to Wake Up from Reduced Power Modes Refer to Table 2 3 and Table 2 4 deeper sleep relatively less power gt Determined by Controls LIGHT MID DEEP Timer interrupts TIMER1 and TIMER2 No wake up e Assuming respective IMR bit is set A B C e Assuming ARM bit is set as in C External interrupts Port F and Do 3 4 5 if input e Assuming respective IMR bit is set e Assuming ARM bit is set as in C RESET If TIMER is running then Underflow wakes device from TIMER Rising Edge
320. pulsing D stopped stopped stopped TIMER1 or TIMER2 status e Assuming TIMER is enabled 1 running 1 stopped 1 stopped 1 TIMER source 1 2 MC 2 running 2 running 2 stopped 2 TIMER source RTO or CRO If the reference oscillator is stopped by a programmed disable or by an IDLE instruction then on re enable or wake up the oscillator requires some time to restart and resume its correct frequency This time imposes a delay on the core processor resuming full speed operation The time delay required for the CRO to start is greater than the time delay required for the RTO to start There are a number of ways to wake the C614 from the IDLE induced sleep state The various options are summarized as a function of the reduced power mode in Table 2 5 Naturally the RESET event happens after the RESET pin has gone low to high causes an immediate escape from sleep whereby the program counter assumes the location stored in the RESET interrupt vector The RESET escape from sleep is always enabled regardless of the depth of sleep or the state of programmable controls The more functional methods available for waking the device are 1 the Internal TIMER interrupt and 2 the external input port interrupt For either of these options to work the respective bit in the interrupt mask register address 0x38 must be set to enable the associated interrupt service If the appropriate IMR bit is not set before the IDLE instruction then the interru
321. r ad himniotrewa 2 2 NR a ar An An next A CMP An An next A we mmwe 3 jmemm a o Tome Je t Does not modify An status Execution premodify AP if mod specified STAT flags set by src src operation PC PC W Flags Affected srcis An OF SF ZF CF are set accordingly src is Rx RCF RZF are set accordingly src is adrs TAG bit is set accordingly Opcode mee 00000000000 0000010 OS CO dma16 for direct or offset16 long relative see section 4 13 ER pr HHH A EJ imm16 CMP An An next A ESESERETERE NEN EA ER EXER EXERCI KB CMP An Anl nex A OOO MEE 01101103 CS CHES ER OMP Rx immt6 EREE EH 90 E E E E E RC C2 C3 x imm16 ve RRS fa fa tt tft fofof f a foto Description Subtract value of src1 from src i e src src1 and only modify the status flag Premodification of accumulator pointer is allowed with some operand types See Also CMPB CMPS Jcc Ccc Example 4 14 10 1 CMP AO RO Compare value at accumulator AO and the content of data memory location pointed by RO and change the STAT flags accordingly Example 4 14 10 2 CMP AO 0x1400 A Predecrement accumulator pointer APO Compare value at accumulator AO to immediate value at 0x1400 and change the STAT flags accordingly 4 90 Individual Instruction Descriptions Example 4 14 10 3 CMP R2 Oxfe20 Compare value at R2 to immediate value Oxfe20 and change the STAT flags acco
322. r A2 lower 8 bits Assembly Language Instructions 4 147 Individual Instruction Descriptions 4 14 53 ORS Bitwise OR String Syntax label name dest src src Clock clk With RPT clk ors an aars Table 4 46 Table 4 46 oss jaimiomas nta 2 NR 2 ons ai An An Execution dest dest OR src fortwo operands dest Src OR src for three operands C PC w Flags Affected destis An OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode instructions Pro fis sa fis 12 HD to 9 Js v e 8 a ja i2 1 Jo ORS An adis oplo lol m ams x dma16 for direct or offset16 long relative see section 4 13 ORS An Ani omato ijififojofijif an fofo lo o 1 fa A ors apanman 1 f fofoJ an ojs jojo t o A A Description Bitwise OR of src and dest Result is stored in dest If three operands are specified then logical OR src and src store result in dest ORS An adrs OR RAM string to An string ORS An An pma16 OR ROM string to An string store result in An string ORS Ar An An OR An string to An string store result in An string See Also OR ORB AND ANDS XOR XORS NOTAC NOTACS Example 4 14 53 1 ORS A0 R2 OR data memory string beginning at address in R2 to accumulator string AO Result stored in accumulator string AO Example 4 14 53 2 ORS AO AO Ox13F0 OR program memory string beginning at address in 0x13F0
323. r after a power fluctuation The application circuits shown in Section 6 1 Application Circuits illustrate one implementation of a reset on power up circuit The circuit consists of an RC network 100 kO 1 uF When powering Vpp from 0 V to 4 5 V the circuit provides some delay on the RESET pin s low to high transition This delay helps to ensure that the C614 initialization occurs after the power supply has had time to stabilize between Vpp MIN and Vpp MAX Vpp MIN and Vpp MAX are the minimum and maximum supply voltages as rated for the device The circuit shown however may not shield the RESET pin from every kind of rapid fluctuation in the power supply At any time that the power supply falls below Vpp MIN even momentarily then the RESET pin must be held low and then high once again either by the user of the device or by some other external cir cuitry Refer to Chapter 8 MSP50C614 Electrical Specifications for a charac terization of the values Vpp MIN Vpp MAX Vj and VoL Vjj and Vo are the low level and high level input voltages respectively which dictate the precise levels of transition for RESET When the RESET pin is held low the C614 is considered reset and has the following internal states RESET low VO ports are be placed in a high impedance Input condition Ports A B C D and E Y All outputs on Port G is are set to low 0x0000 Device is placed in a deep sleep state refer to reduced power mode IV
324. r and store the result into accumulator A 0 or 1 ALU status is modified The string bit causes an add with carry status CF Transfer product high register to accumulator A 0 or offset accumulator A 1 ALU status is modified String bit will cause stringing with current ZF status bit Copy SF bit in status register to all 16 bits of the accumulator or offset accumulator On strings the accumulator address is preincremented causing the sign of the addressed accumulator to be extended into the next accumulator address Subtract offset accumulator from accumulator A 0 or subtract accumulator from offset accumulator A 1 and store the status of the result into ALU status Accumulator or offset accumulator original value remains unchanged 1 o o o 1 reserved NS goode A c o o T reme a T These instructions have a special 1 word string operations when string mode is selected The instructions ignore the string count executing only once but maintain the carry and comparison to zero operation of the previous arithmetic operation as if the sequence of the previous string instruction and current instruction were part of a larger string operation 4 32 Instruction Classification Table 4 20 Class 3 Instruction Description Continuea c quem IRE 1 1 MOV SV An next A Transfer accumulator A 0 or offset accumulator A 1 MOVS SV An to SV register Transfer status is modified MOV PH An next A
325. r assumes a specific location resuming normal operation of the device Normally the destination of the program on wake up is the interrupt service routine associated with the interrupt which initiated the wake up The start of the interrupt service routine is defined by the program location stored in the respective interrupt vector see Section 2 6 3 Interrupt Vectors This wake up response requires that the global interrupt enable is set before going to sleep use the INTE instruction If the global interrupt enable is CLEAR before going to sleep then the programmed interrupt can still wake the device provided that the respective IMR and ARM bits are set as in Table 2 5 Instead of waking to the interrupt service routine however the program counter assumes the location immediately following the IDLE instruction which initiated the sleep This type of wake up response may be useful for putting the C614 into a hold sleep whereby any number of programmable interrupts can wake the device yet they all return the program to the very same location In order to accomplish this each of the necessary interrupts should be enabled in the IMR The global interrupt enable however is cleared using the INTD instruction Table 2 6 lists the various possible destinations of the program counter on wake up provided that the wake up is bound to occur under the given conditions Table 2 6 Destination of Program Counter on Wake Up Under Various Conditio
326. r js rjo me ijt Description See Also Example 4 14 13 1 When used with repeat will execute 16 x 16 multiplication between two indirectly addressed data memory buffers 48 bit accumulation and a circular buffer operation Each tap takes 3 instruction cycles The selected register Rx must be even This instruction also uses R x 1 This instruction must be used with RPT instruction See section 4 11 for more detail on the setup of coefficents and sample data During COR execution interrupts are queued RPT CORK FIR FIRK RPT 0 COR AO RO Computes the calculation for 2 tap correlation filter with 48 bit accumulation See section 4 11 for more detail on the setup of coefficents and sample data 4 94 Individual Instruction Descriptions 4 14 14 CORK Correlation Filter Function Syntax Tabor ame CE EE Word w wih RP ok cies Poor ante 1 3 it ref oe Execution With RPT N 2 mask interrupts RPT counter N 2 MR h 0 first filter coefficient x sample data pointed at by RXeyen h 1 second filter coefficient pointed by DP y result stored in three consecutive accumulators 48 bit pointed by An between every accumulation IF TAG 1 RXeven RXeven R5 for circular buffering ELSE RXeven if Rx is specified in the instruction ENDIF PC PC 1 final result p yee RII RNC Execution is detailed in section 4 11 Flags Affected None Opcode pase 0 0 epe were telefe
327. r must contain the first filter coefficient h 0 RO and R1 must be used this way The filtering operation will not work if the Rx registers are reversed The following are the only allowable register combinations RO points to circular buffer and R1 points to filter coefficients R2 points to circular buffer and R3 points to filter coefficients Assembly Language Instructions 4 63 Special Filter Instructions Any combination of registers different from the above will yield incorrect results with the FIR COR instruction 0x0106 0x010 Use R5 to wrap around RO 0x0100 9 After FIR COR execution The STAT register is saved in the filerSTAT tag location The output of the fil tering operation in the example is located in ACO lower word and AC1 high word This 32 bit result is stored in the SampleOut RAM location RO should be pointing to the oldest sample The oldest sample x k 3 is overwritten by the next sample to be filtered x k 1 RO is saved in the startOfBuff pointer for the next FIR COR instruction Notice that RO points backwards by one location from its starting point each time an FIR COR instruction is executed In the above figure RO would end up at successive locations in a clockwise manner 4 64 Special Filter Instructions Important note about setting the STAT register It is very important to consider the initial value of the filterSTAT_tag variable Failure to set up the filerSTAT tag variable can cause
328. r to deep sleep mode Assembly Language Instructions 4 103 Individual Instruction Descriptions 4 14 21 IN Input From Port Into Word Syntax Liner meme asas Sook oe Word w E Um esse ms rena es wea 5 H T L9 Execution dest content of port6 or port4 PC PC W Flags Affected dest is An OF SF ZF CF are set accordingly dest is adrs XZF XSF are set accordingly Opcode rr CO mB cae ee Wisi pond HH HD HT 1 39 7 dma16 for direct or offset16 long relative see section 4 13 wxums Pe fol ome ES Description Input from I O port Words can be input to memory from one of 16 port addresses or one of 48 port addresses The port4 address is multiplied by 4 to get the actual port address See Also INS OUT OUTS Example 4 14 21 1 IN RO 0x0c Input data from port address OxOc 4 0x30 to data memory location pointed by RO Example 4 14 21 2 IN A2 0x3d Input data from port address Ox3d to accumulator A2 4 104 Individual Instruction Descriptions 4 14 22 INS Input From Port Into String Syntax Ts sr o9 fe Execution dest content of port6 PC e PC 1 Flags Affected destis An OF SF ZF CF are set accordingly Opcode LIIS NR ETE EE EE EI ELE ELE ER ERE EE CR manes eo fm me I Description Input string from same port port6 to accumulator string Strings can be input to accumulators from one of 64 port addresses In this instruction port6 is
329. rameter but you have the option of supplying additional value parameters separated by commas Information About Cautions and Warnings This book may contain cautions and warnings This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A warning statement describes a situation that could potentially cause harm to you The information in a caution or a warning is provided for your protection Please read each caution and warning carefully Trademarks Intel i486 and Pentium are trademarks of Intel Corporation Microsoft Windows Windows 95 and Windows 98 are registered trademarks of Microsoft Corporation Read This First V vi Contents Introduction to the MSP50C614 cccccccccccccc n nnn n nnn 1 1 1 1 Features of the C614 e 1 2 1 2 Applications ccc sesso aa Eae eee eee RR I E 1 3 1 3 Development Device MSP50P614 oococcccccocccocccn eres 1 4 1 4 Functional Description 00 ccc RI n 1 5 1 5 C605 and C604 Preliminary Information 0c cece eee eee eee eee 1 6 1 6 Terminal Assignments and Signal Descriptions ooo 1 10 MSP50C614 Architecture vee 99 see eee n e eA p Ere wx rana Eee zu Rae 2 1 2 1 Architecture Overview 0 0 c cee hh 2 2 2 2 Computation Unit 0 tenet eens 2 5 2 2 1 M lllpliGE 2 us dee acres E Oe RR rei REOR
330. ransferred to the destination accumulator or its offset This instruction propagates the shifted bit into PH SHLTPL An adrs Shift data memory word left transfer PL to An SHLTPL Ar An next A Premodify APn if next A specified Shift An left transfer PL to An See Also SHLTPLS SHLAPL SHLAPLS SHLSPL SHLSPLS Example 4 14 73 1 SHLTPL A0 R4 R5 Shift the word pointed by the byte address stored in R4 by ngy bits to the left and store the result in accumulator AO Add R5 to R4 and store result in R4 at each execution to get the next memory value After execution PH contains the upper 16 bits of the 32 bit shift Example 4 14 73 2 SHLTPL A2 R1 Shift the value pointed by the byte address stored in R1 by ngy bits to the left and store the result in accumulator AO Increment R1 by 2 at each execution to get the next memory value After execution PH contains the upper 16 bits of the 32 bit shift Example 4 14 73 3 SHLTPL Al Al A Preincrement accumulator pointer AP1 Shift the accumulator A1 by nev bits to the left After execution PH contains the upper 16 bits of the 32 bit shift 4 168 Individual Instruction Descriptions 4 14 74 SHLTPLS Shift Left String and Transfer PL to Accumulator Syntax SHLTPLS An adrs Table 4 46 Table 4 4 1b SHLTPLS TAT AT Execution PH PL src SV dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is
331. rates an assembly language file of the same name with extension opt It also generates a file with extension y1b where global variable initialization is taken care of if the routine main was encountered in the current file A file with extension ext is also generated to take care of global and external declarations that will be used by the assembler These two files are included in the opt file generated by the C compiler Note that all symbols defined in C source code are changed before being written to assembly language an underscore character is put in front of the first character of each symbol Also note that local labels created by the C compiler are built using the current source file name followed by an ordinal number Consequently to avoid problems at link time due to symbols bearing the same name it is a good idea to never use symbol names starting with an underscore in assembly language files and it is imperativeto use file names that are different for C files extension cmm and assembly language files extension asm C is a high level language to be used with the MSP50P614 MSP50C614 microprocessor and its spin offs Although it looks a lot like C it has some limitations restrictions which will be highlighted throughout this document This language is compiled into MSP50P614 MSP50C614 assembly language 5 9 2 Variable Types C Compiler Type Name Mnemonic Range Size in Bytes Example Int
332. rdingly Example 4 14 10 4 CMP RO R5 Compare value at RO to R5 and change the STAT flags accordingly Assembly Language Instructions 4 91 Individual Instruction Descriptions 4 14 11 CMPB Compare Two Bytes Syntax as ESE Word w AE jwe mms a tL NR fa Yours Reime L 3 e Execution status flags set by src src byte PC PC 1 Flags Affected src is An OF SF ZF CF are set accordingly src is Rx RCF RZF are set accordingly Opcode Qe FF A Eee omm HDH CA CA EE E IEA or mme HDH HH 10 CO CO s ee Description Subtract value of src1 zero filled in upper 8 bits from src i e src src1 and only modify the status flags Contents of src not changed See Also CMP CMPS Jcc CCC Example 4 14 11 1 CMPB AO Oxf3 Compare immediate value Oxf3 to accumulator AO Example 4 14 11 2 CMPB R3 0x21 Compare immediate value 0x21 to R3 4 92 Individual Instruction Descriptions 4 14 12 CMPS Compare Two Strings Syntax CMPS An aars Table 4 46 Table 4 46 C MPS Ar pma16 ng 4 N R 2b CMPS Anl pmat6 mew NR gt CMPS An An Ng 3 1 ng 3 3 CMPS An An Execution status flags set by src src1 string PC PC W Flags Affected srcis An OF SF ZF CF are set accordingly src1 is adrs TAG bit is set accordingly Opcode CO 000000000000 000010 eem E ers X dma16 for direct or offset16 long relative see section 4 13 pma16 Ea LIT NU OO EO EE CR C ERES
333. re four lookup instructions as shown in Table 4 44 Lookup instructions always read the program memory address from the second argument which is accumulator or its offset An asterisk always precedes this accumulator to indicate that this is an address Table 4 44 Lookup Instructions Instructions MOV aars An MOV An An next A MOVS adrs An MOVS An An Description Data Transfer The program memory address is stored in accumulator An Store the contents of this address in data memory location referred by addressing mode adrs The program memory address is stored in accumulator An or its offset An Store the contents of this address in accumulator An or An The program memory string address is stored in accumulator An Store the contents of this address to the data memory string referred by the addressing mode aars The string length is defined in STR register The program memory string address is stored in accumulator An or its offset An Store the contents of this address to the accumulator string An or its offset An The string length is defined in STR register Data Manipulation on Strings ADDS An An pma16 ANDS An An pma16 CMPS An pma16 SUBS An An pma16 XORS An An pma16 ADD the accumulator string An or its offset An with the program memory string at location pma16 and store the result to the accumulator string An or its offset An
334. reakpoint dialog box as shown in Figure 5 20 Hardware Breakpoint dialog allows a name to be associated with a hardware breakpoint corresponding to the breakpoint address Only one hardware breakpoint can be made active at any time Figure 5 20 Hardware Breakpoint Dialog 5 20 Hardware Breakpoints LX Active Address Label x0814 x0841 CE O aS AS lE SE SS 3 D o H Inspect Window This is the window where C variables can be examined Variables are inserted in the Inspect window by hitting the INSERT key while this window is active i e when the mouse cursor is in it A dialog appears Figure 5 20 and the user should just type the name of the C variable The Software Emulator variable value and its address in RAM are then displayed Figure 5 21 Variables appearing on a gray background either are not defined or are not active atthis time The user can also use the Inspect option inthe Debug menu to insert a variable in the Inspect window Figure 5 21 Inspect Dialog Inspect Dialog LX Expression Radix gt Dec lt Hex Display as lt Int gt Char MII Tats j tint 5 addr Us 00021 i fint 3 addr QOx g011 I O Ports Window The 64 I O Port values are displayed in this window Figure 5 22 They can be modified the same way most values can be Code Development Tools 5 21 Software Emulator modified i e by double clicking on a value and typing
335. rect or offset16 long relative see section 4 13 o r r o An ros o al riot U an pons fo al EE EE EEN E E E E EEE SS I E ais fel w o Retire eiit me EP PEPE Eee plo pfma s O pma16 4 188 Instruction Set Encoding instructions UR 14 fia 2 1 10 o 8 v e 5 sa fa 2 fo Lem ies EH st x Lens ens s X pma16 TSTS TSTST TSTS TSTS TSTST a fo fo fofofo Ie E x JMP pma16 Rx JMP pma16 Rx R5 Jcc pma 6 Jcc pmat6 Rx Jcc pma16 Rx Jcc pma16 Rx R5 MOV adrs An next A MOV An adrs next A MOV aadrs An MOV An imm16 next A MOV MR imm16 next A MOV An An next A MOV An PH next A MOV SV An next A MOV PH An next A MOV Ar gt An next A x ofo p Ti eaa e ofo TSTS ena La gt lojs orsye e jo a as dma16 for direct or offset16 long relative see section 4 13 Pt a a fo fo nea Ao o o1 o o 1 o A HUMD fo rea Ao t 1 jo o 1 o o fo fo newa Ao oo 9 9 1 jo fa a LTR TS rea Ao ols 1 1 o jo fa A t o o newa Ao 50 1 0 o o a o HUMD fo neta an 15010 10 A o o fo newa an o ojo 1 o o fa a mov mR arpoa 1 1 1 oo neta an lols 1fojofa o Xx MOV adrs Rx MOV Rx adrs hhh t pepo x Phot e D ae dma16 for direct or offset16 long relative see section 4 13
336. red for the RTO to start o 2 9 4 RTO Oscillator Trim Adjustment Bits 15 through 11 and bit 9 6 bits total in the ClkSpdCtrl effect a software control for the RTO oscillator frequency The purpose of this control is to trim the RTO to its rated 32 kHz specification The correct trim value varies from device to device The user must program bits 15 through 11 and 9 in order to achieve the 32 kHz specification within the rated tolerances Texas Instruments provides the trim value to the programmer of the P614 part with a sticker on the body of the chip For the C614 part the correct trim value is located at I O location Ox2Fh RTRIM Register Read Only Applies to MSP50C614 Device Only UO Address 0x2Fh 17 bit wide location 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 R RH R R R R R R R R R T5 T4 T3 T2 Ti TO T RTO oscillator trim storage device specific R reserved for Texas Instruments use ClkSpdCirl Value Copied Shaded Bep ER Ee E port E eq E A vr Me vo M4 vo m2 wt mo When selecting and enabling the RTO oscillator therefore the bits at positions 05 through 01 should be read from I O location 0x2F MSP50C614 device only then copied to the ClkSpaCtrl trim adjust bits 15 through 11 of control register OX3D and bitO of Ox2F I O port should be copied to bit 9 of ClkSpdCtrl register The bit ordering is the same bit 04 of I O Ox2F copies to bit 15 of register OX3D Likewise bit 00 of I O Ox2F
337. register by the contents of adrs and subtract MULSPLS An adrs the lower 16 bits of the product from the accumulator Latch the upper 16 bits into the PH register ALU status is modified 4 4 2 Class 2 Instructions Accumulator and Constant Reference 4 28 These instructions provide the capability to reference short 8 bits or long 16 bits or ng 2 16 bit string constants stored in program memory and to execute arithmetic and logical operations between accumulator contents and these constants Since the MSP50P614 MSP50C614 is a Harvard type pro cessor these instructions are necessary and distinct from the general class of memory reference instructions Subclass 2a listed belows include refer ences between accumulator and short 8 bit constants This class has the ad vantage of requiring only 1 instruction word to code and 1 instruction cycle to execute Thus is particularly useful for control variables such as loop counts indexes etc The short constants also provide full capability for byte opera tions in a single instruction word Subclass 2b references accumulator and long constants from program memory 16 bits for non string constants and ng 2 16 bits for string constants Class 2b instructions take 2 instruction words to code The execu tion of these instructions is 2 instruction cycles when the long constant is a single word The execution is ng 2 execution cycles for ng word string Instruction Classification c
338. ress For example pma8 means 8 bit program memory address If n is not specified defaults to pma16 port n n bit I O port address Rx registers are treated as general purpose registers These bits are not related to any addres sing modes Indirect register bits as described in Table 4 3 S Represents string mode if 1 otherwise normal mode x Don t care Instructions on the MSP50P614 MSP50C614 are classified based on the op erations the instruction group performs see Table 4 11 Each instruction group is referred to as a class There are 9 instruction classes Classes are subdivided into subclasses Classes and opcode definitions are shown in Table 4 11 Table 4 11 Instruction Classification Class Sub Description Class 1 Accumulator and memory reference instructions A Accumulator and memory references with or without string operations and accumulator preincrementing B Accumulator and memory references with or without string operations 2 Accumulator constant reference A Short constant to accumulator Long constant to accumulator 3 Accumulator reference instructions with no addressing modes Assembly Language Instructions 4 23 Instruction Classification Table 4 11 Instruction Classification Continued Class Sub Description Class 4 Register and memory reference Memory references that use Rx all addressing modes available Memory references with short constant fields operating on Rx Memory re
339. ring result xor string int result int strl int str2 int 1g exclusive ors strings strl and str2 of length lg 2 and puts the result in string result not string int result int strl int 1g takes the l s complement of string str of length lg 2 and puts the result in strings result neg string int result int strl int 1g takes the 2 s complement of string str of length lg 2 and puts the result in strings result test string int stringl int string2 int lg int oper performs a logical test operation on strings stringl and string2 of length lg 2 The logical value is returned in AO If string2 is NULL the logical test is performed between string string and a zero string operator can take the following values predefined constants EOS N NES_N LTS N lt LES N lt GES N gt GTS N gt 7 ULTS N lt unsigned ULES N lt unsigned UGES N gt unsigned UGTS N gt unsigned A major feature of the MSP50P614 MSP50C614 is that the string length present in the string register is the actual length of the string minus two To avoid confusion a macro is supplied that automatically translates the real length of the string to the MSP50P614 MSP50C614 length of the string It is included in the cmm macr h file and is called STR LENGTH lstr For example STR LENGTH 98 is 8 2 6 5 46 C Compiler Also note that the user has to supply the length of the inp
340. rity for an explanation of the ROM security scheme 2 6 4 ROM Code Security The C614 provides a mechanism for protecting its internal ROM code from third party pirating The protection scheme is composed of two levels both of which prevent the ROM contents from being read Protection may be applied to the entire program memory or it can be applied to a block of memory beginning at address 0x0000 and ending at an arbitrary address The two levels of ROM protection are designated as follows Y Direct read and write protection via the ROM scan circuit Indirect read protection which prohibits the execution of memory lookup instructions Forthe purposes of direct security the ROMis divided into two blocks The first block begins at location 0x0000 and ends inclusively at location m x 512 1 where m is some integer Each address specifies a 17 bit word location The second block begins at location m x 512 and ends inclusively at Ox7FFF the end of the ROM The first block is protected from reads and writes by programming a block protection bit and the second block is protected from reads and writes by programming a global protection bit The two block system is designed in such a way that a secondary developer is prevented from changing the partition address between blocks Once the block protection has been engaged then the only security option available to the secondary developer is engaging the global protection
341. rpose l O Ports The forty configurable input output pins are organized in 5 ports A B C D and E Each port is one byte wide The pins within these ports can be individually programmed as input or output in any combination The selection is made by clearing or setting the appropriate bitin the associated control register Control A B C D or E Clearing the bit in the control register renders the pin as a high impedance input Setting the control bit renders the pin as a totem pole output When configured as an input the data presented to the input pin can be read by referring to the appropriate bit in the associated data register Data A B C D or E This is done using the IN instruction with the address of the data register as an argument When configured as an output the data driven by the output pin can be controlled by setting or clearing the appropriate bit in the associated data register This is done using the OUT instruction with the address of the data register as an argument Port A Port B Port C Port D Port E Control register address OxO4hf OxOCh 0x14h 0x1Ch 0x24h Possible control values 0 High Z INPUT 1 TOTEM POLE OUTPUT Value after RESET low 0 High Z INPUT Data register address 0x20h Possible input data values Low 0 High 1 don t care on write Possible output data values 0 lt LOW 1 High t Each of these I O ports is only 8 bits wide The reason for the 4 byte address spacing is so that instructions
342. rred by addressing mode aars MOV STR adrsjg Load String STR register with content of data memory location referred by addressing mode adrs Only the lower 8 bits are loaded Transfer status modified MOV APn adrs Load lower 5 bits with content of data memory location referred by addressing mode adrs to accumulator pointer AP register n Transfer status is modified 16 bit value MOV MR aars Load Multiplier MR register with content of data memory location referred by addressing mode adrs and set the multiplier signed mode UM 0 in STAT register Transfer status is modified MOVU MR adrs Load Multiplier MR register with content of data memory location referred by addressing mode aars and setthe multiplier unsigned mode UM 1 in STAT register Transfer status is modified MULR aars Multiply MR register by content of data memory location referred by addressing mode adrs add 0x00008000 to the 32 bit product to produce a rounding on the upper 16 bits Store the upper rounded 16 bits to the PH register No status change MUL aars Multiply MR register by content of data memory location referred by addressing mode adrs and store the most significant 16 bits of product into the PH register No status change 1 1 1 0 O RETf Return from subroutine Load data memory location value addressed by R7 STACK to program counter 1l1l1fo 1 IRETT Return from interrupt routine Load data memory
343. rrupi General Control Register 3 4 Interrupt General Control Register IntGenCirl register address 0x38 Theinterrupt general control IntGenCtrl is a 16 bit wide port mapped register located at address 0x38 The primary component in the IntGenCtrl is the 8 bit interrupt mask register IMR The service branch enable status for each of the eight interrupts is registered in the IMR A SET bit in the IMR enables that interrupt to assume the service branch at the time that the associated trigger event occurs A CLEAR bit disables the service branch for that interrupt The IMR is located at bits 0 through 7 in the IntGenCtrl Bit O is associated with INTO which is the highest priority interrupt Bit 7 is associated with INT7 Refer to Section 2 7 Interrupt Logic for more information regarding the interrupt system logic and initialization sequence 16 bit wide location 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 CE AR PD EP E2 El S2 Si D5 D4 PF D3 D2 T2 Ti DA low high priority priority 0x0000 State after RESET low Interrupt mask register Comparator enable port Ds falling edge ARM bit port D4 rising edge Pulse density clock PDMCD port Dg falling edge Enable pullup resistors on port F port Do rising edge Enable TIMER2 1 value starts timer any port F falling edge Enable TIMER 1 1 value starts timer TIMER2 underflow Clock source for TIMER2 0 chooses 1 2 MC TIMER1 underflow Clo
344. rs Table 4 46 Table 4 4 1 A 6 ANOS Ac Ar Execution dest string deststring AND src string for two operands dest string src string AND src string for three operands PC PC W Flags Affected destis An OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode eee 000000000000 000010 mmc she a a dma16 for direct or offset16 long relative see section 4 13 pr LAA Ed X pma16 ANOS An Am An 1 1 fofoJ 1 an oft fo of A Description ANDS dest src Bitwise AND of src string and dest string and store result in dest string ANDS dest src src1 Bitwise AND src7 string src string and store result in dest string See Also AND ANDB OR ORB ORS XOR XORB XORS Example 4 14 6 1 ANDS A0 R2 AND data memory string beginning at address in R2 to AO put result in AO Example 4 14 6 2 ANDS A0 AO 0x1400 AND program memory string beginning at address in 0x1400 to AO put result in AO Example 4 14 6 3 ANDS AO A0 AO AND accumulator string AO to accumulator string AO put result in accumulator string AO Example 4 14 6 4 ANDS AO AO R2 AND memory string beginning at address in R2 to AO put result in AO Assembly Language Instructions 4 83 Individual Instruction Descriptions 4 14 7 BEGLOOP Begin Loop Syntax mer CS EI Word v Twin x ose mmo 1 3 Lo lw l t Loop must end with ENDLOOP Execution Save next i
345. rs and the input port Data output is performed with the OUT instruction Class 6 The OUT instruction can specify a memory address and a 4 bit port address It can also use an accumulator or offset accumulator and a 6 bit port address String transfers are allowed between the accumulators and the output port 4 11 Special Filter Instructions The MSP50P614 MSP50C614 processor can perform some DSP functions Fundamental to many filtering algorithms is the FIR structure which requires several parallel operations to execute for each tap of the filter as shown in Figure 4 5 Each tap has 1 multiply and 1 accumulation to obtain the output y for N 1 taps Figure 4 5 FIR Filter Structure N 1 Tap FIR filter Newest sample Oldest sample x k Xii x k 2 KN T O oe x x k 3 A k 2 k 2 x k 2 x k 2 TA x k 1 x k 1 f Mi 32 or 48 KA YIK Emo him tkm y k h 0 x k h 1 x 1 h 2 x k 2 ALN x x k N Assembly Language Instructions 4 59 Special Filter Instructions 4 60 N tap filters ideally require 2N multiply accumulates Four instructions are provided to compute this equation FIR FIRK COR and CORK All filter instructions require overflow modes to be reset since these instructions have built in overflow hardware In addition these instructions must be used with a RPT instruction FIR and FIRK instructions perform 16 x 16 bit multiplies and 32 bit accumulation in 2 clock cyc
346. ruction by MOVS AO 0x0001 2 which uses the absolute word memory address Example 4 5 6 MOV STR OV APO MOV RO MOVBS AO 4 2 2 0x0005 RO Refer to Figure 4 4 for this example The byte string length is 4 APO points to AC2 RO is loaded with 0x0005 The fourth instruction loads the value of the byte string at the address in RO i e 0x0005 in byte mode RO auto incre ments by 1 after every fetch and stores the RAM contents into four consecutive accumulators starting from AC2 The result is AC2 0x00BC AC3 OxOODE ACA 0x00F0 AC5 0x0011 There were four byte fetches and the new value of RO 0x0009 Assembly Language Instructions 4 47 Bit Byte Word and String Addressing 4 48 Example 4 5 7 MOV STR 4 2 MOV APO 2 MOV RO 0x0001 2 MOVBS AO RO Refer to Figure 4 4 for this example The word string length is 4 APO points to AC2 accumulator RO is loaded with 0x0002 The fourth instruction loads the value of the word string atthe RAM address in RO 0x0002 RO autoincrements by 2 after each fetch and stores them into four consecutive accumulators starting from AC2 The result is AC2 0x5678 AC3 Ox9ABC AC4 OxDEFO AC5 0x1122 There were 4 word fetches and the new value of RO 0x000A Example 4 5 8 SFLAG 0x0003 MOV AO 0x0003 2 RFLAG 0x0003 MOV AO 0x0003 2 Refer to Figure 4 4 for this example This example illustrates the use of the TAG and flag bits Notice
347. s an example 1 Select the TIMER2 clock source 1 2 MC or RTO CRO bit 9 of the Int GenCtrl address 0x38 2 Clear the TIMER2 enable bit 11 in the IntGenCtrl 3 Loadthe count down register TIM2 with the desired period value ahead of time This prepares TIM2 for counting and also loads the period regis ter PRD2 with its value 4 Besurethe TIMER2 interrupt INT2 has been enabled for service set bit 2 of IntGenCtrl 5 Flipthe TIMER2 enable bit from 0 to 1 at the precise time you want count ing to begin Clock Control 2 9 Clock Control 2 9 1 Oscillator Options The C614 has two oscillator options available Either option may be enabled using the appropriate control bits in the clock speed control register ClkSpdCtrl The ClkSpdCtrl is described in Section 2 9 3 Clock Speed Con trol Register The first oscillator option called the resistor trimmed oscillator RTO is useful in low cost applications where accuracy is less critical This option utilizes a single external resistor to reference and stabilize the frequency of an internal oscillator The oscillator is designed to run nominally at 32 kHz It has alow Vpp coefficient and a low temperature coefficient refer to Appendix C The reference resistor is mounted externally across pins OSC n and OSCour The RTO oscillator is insensitive to variations in the lead capacitance at these pins The required value of the reference resistor is 470 kQ 1 The se
348. s from 0 to 3 The symbol indicates that the accumulator pointed to by APnis the referring accumulator If APn has a value of k it is pointing to accumulator ACk Similarly An points to the offset accumulator pointed by APn For example if AP3 22 then A3 is accumulator AC22 and A3 is accumulator AC6 System Registers During accumulator read operations both An and offset An are fetched Depending on the instruction either or both registers may be used In addition some write operations allow either register to be selected The accumulator block can also be used in string operations The selected accumulator An or An is the least significant word LSW of the string and is restored at the end of the operation String instructions are described in detail in section 4 8 4 2 9 Accumulator Pointers APO AP3 The accumulator pointer AP registers are 5 bit registers which point to one of the 32 available accumulators The APs contain the index of accumulators Many instructions allow preincrement or predecrement accumulator pointers Such instructions have a suffix of A for preincrement or A for predecrement Accumulator pointers can be stored or loaded from memory using various addressing modes Limited arithmetic operations can be performed on accumulator pointers CN ECO E O E APO AP3 Not used Points to An n val b0 b4 4 2 10 Indirect Register RO R7 Indirect registers RO R7 are 16 bit registers that are
349. s typ CTRL Leben Dai edo ban lag focis Ta ecr Um ferus dp a parlicalar adrot just plage Ibe miga cuesar over if mh b 100551 Ung L 0060 Miata owe r2 wa jure gm OMe F ran Onn 0000 jars LE E 0006 0030 ig EF 5 Qu te 0000 1090981 X ome r7 BoM 108911 di im mE c pig 040 OdAD 0249 0040 Of J 0601 000 0000 OMG TAT DOPO HAT DI4F 044 024P 0000 0001 DOZ dag i ik gwe EY 0000 DIFF GOFF GOFF OFF f d Vic iB dat i 0000 MEF GOFF GOFF GOFF 000 0004 000 0000 aC ic 0006 rH mpa DID 0000 0701 0000 060 0007 000 0005 ib be de EH 0007 0007 0307 0307 00609 ODOT DOS DUE E OMe s 000 3004 3004 4904 4204 4004 4004 4004 dona Y N s i IP J TOE ARS d sacada mr Estoy Den ALTE UD KTZ 8D Ecri D 2 CUR FIR PERES p RUNE GH tb Lal 20 rrr EPET E n bs EL IAE O DURS RIE Y D ADUEDHCHACHM HALE H Jal Code Development Tools 5 31 Software Emulator 5 6 8 Known Differences Incompatibilities Restrictions 5 32 O O Include statements in assembly language files must enclose the file name in double quotes REF DEF statements in assembly language files should be replaced with EXTERNAL GLOBAL statements but the old REF DEF are still supported There is no default type for variables in the C compiler The user should always use int or char Typedef is not supported in C To use external functions in C put a function prototype in the file that calls the external function To use e
350. sent search position cyan highlighted text If no software breakpoint is found it gives an error Error No more software breakpoint There is no limit on software breakpoints This operation does not change the program counter value EPROM Program This menu option launches the EPROM Programming Dialog Figure 5 24 that allows the user to program a project on a chip Software Emulator Figure 5 25 EPROM Programming Dialog Number of words hex to be programmed Starting hex address Endinghex address Dumps entire content of Program Memory to a file same as project name with bmp extension Ramz 2 0x00800 If this box 1s checked default Program verification is performed for each programmed location If error occurs itis reported Performs Blank Check of EPROM value OxlFFFF Reports unerased locations if successful or OK otherwise Programs the current program into EPROM Asks for confirmation before proceeding Performs blank check before programming the EPROM Asks for confirmation before proceeding Code Development Tools 5 25 Software Emulator Trace Mode This menu option launches the Trace Mode Dialog Figure 5 25 that allows that user to run the chip in trace mode i e running an internal program on the chip while monitoring its execution on the scanport Figure 5 26 Trace Mode Trace Mode ES Optional Trace Mode st
351. ses an asynchronous response to the internal and external interrupts during the sleep state If the master clock has been suspended during sleep then the ARM bit must be set before the IDLE instruction in order to allow a programmable interrupt to wake the C614 Refer to Section 2 11 Reduced Power Modes for more information Finally the top most bit in the IntGenCtrl is the comparator enable bit Setting bit 15 enables the comparator and all of its associated functions Some of the C614 s conditions interrupts and timers behave differently depending on whether the comparator is enabled or disabled by this bit Refer to Section 3 3 Comparator for a full description Hardware Initialization States 3 5 Hardware Initialization States The RESET pin is configured at all times as an external interrupt It provides for a hardware initialization of the C614 When the RESET pin is held low the device assumes a deep sleep state and various control registers are initialized After the RESET pin is taken high once again the Program Counter is loaded with the value stored in the RESET Interrupt Vector p A Note Internal Power Reset Function There is no power on reset function internal to the C614 After the initial pow er up or after an interruption in power the RESET pin must be cycled low to high The application circuitry must therefore provide a mechanism for ac complishing this during a power up transition o
352. set accordingly Opcode instructions Pro fis fra fis 2 HD to o o v e S a EH 2 fo SHLTPLS An adi Ceppbliedlebleli as dma16 for direct or offset16 long relative see section 4 13 smrPLS An An 1 1 1 foto 51 a fo ofofa A Description Shift left accumulator string or data memory string pointed at by adrs by nsy bits as specified by the SV register The result is zero filled on the right and either zero filled or sign extended on the left based on the setting of the Extended Sign Mode XM bit in the status register The upper 16 bits are latched into the PH register The result is transferred to the destination accumulator or its offset This instruction propagates the shifted bits to the next accumulator including one accumulator past the string length which receives the same data as PH SHLTPLS An adrs Shift data memory string left transfer result to An SHLTPLS Ar An Shift An string left transfer result to An See Also SHLTPL SHLAPL SHLAPLS SHLSPL SHLSPLS Example 4 14 74 1 SHLTPLS A0 R4 R5 Shift the string pointed by the byte address stored in R4 by nsv bits to the left and store the result in accumulator string AO Add R5 to R4 and store result in R4 After execution of the instruction PH is copied to the next to the last accumulator of the string Example 4 14 74 2 SHLTPLS A2 R1 Shift the string pointed by the byte address stored in R1 by ngy b
353. settings are inverted for NOT conditions Hardware lines used for I O expansion design These lines are PAO and PA1 Assembly Language Instructions 4 69 Legend 4 13 Legend name dest src srci mod Symbol An An 4 70 All instructions of the MSP50P614 MSP50C614 use the following syntax name dest src src1 mod Name of the instruction Instruction names are shown in bold letter through out the text Destination ofthe data to be stored afterthe execution ofthe instruction Optional for some instructions or not used Destination is also used as both source and destination for some instructions Source of the first data Optional for some instructions or not used Source of the second data Some instructions use a second data source Optional for some instructions or not used Post modification of a register This can be either next A or Rmod and will be specified in the instruction Meaning The following table describes the meanings of the symbols used in the instruction set descriptions Bold type means it must be typed exactly as shown italics type means it is a variable square brackets enclose optional arguments Operands 0 x dma6 x 63 0 dmat16 x 65535 0 x imm5 x 31 0 lt imm16 lt 65535 0 lt offset6 x 63 0 x offset7 x 127 0 lt offset16 x 65535 0 lt pma8 lt 255 0 lt pmat16 x 65535 0 lt port4 x 15 0 x port6 x 63 dma16 x 639 for MSP50P614 MSP50C6
354. sg pass where error was detected type of error error warning error message number short file number file number in object file table long line number line number in file where error occurred char info MAXIDENTIFIER 1 character string containing some y struct cmm_input short heap_st short stack_st information on the error start of heap start of stack Code Development Tools 5 39 C Compiler u a u Q y hort ram_size hort verbose hort c code hort optimize har dir list ram size for the chip refers to assembly code output if non zero c code is included as assembly language comments should always be non zero string of include directories searched for C include directive har directory MAX LEN name of data directory i e directory where tools where installed struct error struct error list MAX ERRORS TBE eh i CMM MAIN EL Where 5 9 1 5 40 U U U U source file amp w amp input error list source file is the source file name w is the number of warnings generated by the compiler input is a structure that is used to pass some parameters to the compiler error list contains the errors generated by the compiler upon return similar as the one used in the assembler Foreword The C compiler gene
355. src gt gt 1 PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pro 15 1a ra 12 fn to o e v e s a js 2 1 suracs Ah An 11 toto EHH an Jjo sjops ryo A a Description Shift accumulator string right one bit and store the result into An string MSB of each accumulator in the result will be set according to extended sign mode XM bit in the status register This instruction shifts each accumulator individually 1 bit to the right so shifts from one accumulator are not propagated to the next consecutive accumulator in the string See Also SHRAC SHL SHLS SHLAPL SHLAPLS SHLSPL SHLSPLS SHLTPL SHLTPLS Example 4 14 76 1 SHRACS AO AO Shift accumulator string AO 1 bit right individually Example 4 14 76 2 SHRACS Al Al Shift accumulator string A1 individually put result in accumulator string A1 Assembly Language Instructions 4 171 Individual Instruction Descriptions 4 14 77 SOVM Set Overflow Mode Syntax ime mame Glock ok wora w With RPT ok Class o som NR o Execution STAT OM lt 1 PC PC 1 Flags Affected None Opcode Instructions Pro Pis 14 fia 12 to o 8 v fo 8 a a J2 t o iow rjeloisdeoisde ero eis ojs ojo o o Description Sets overflow mode in status register STAT bit 2 to 1 Enable ALU saturation output DSP mode See Also ROVM Example 4 14 77 1 SOVM Set OM bit of STAT to 1
356. ss in R4 to accumulator A3 decrement value in R4 by 2 word mode after the operation Example 4 14 84 5 XOR A2 A2 R2 R5 A Pre decrement pointer AP2 XOR word at effective address R2 R5 to new accumulator A2 put result in accumulator A2 Value of R2 is not modified Example 4 14 84 6 XOR TF1 0x21 XOR TF1 with the flag at global address 0x21 and store result in TF1 in STAT Example 4 14 84 7 XOR TF2 R6 0x21 XOR TF2 with the flag at effective address R6 0x21 and store result in TF2 Example 4 14 84 8 XOR TF1 CF XOR TF1 with the condition code CF Carry Flag and store result in TF1 Example 4 14 84 9 XOR TF1 RZP R3 XOR TF1 with the condition code RZP Rx 0 flag for R3 and store result in TF1 If the content of R3 is zero then RZP condition becomes true otherwise false 4 182 Individual Instruction Descriptions 4 14 85 XORB Logical XOR Byte Syntax iae rame sess Ta ok Word w win RPT ck crass xor Anime 1 1 Execution An An XOR imma for two operands PC PC 1 Flags Affected dest is An OF SF ZF CF are set accordingly Opcode Instructions re rs 14 13 12 11 o o o 7 Jo s EH EH EH Jo Ll mm8 xorB An imme fo Jo ls fols tito an imm8 Description Bitwise logical XOR lower 8 bits of An and dest byte Result is stored in accumulator An Upper 8 bits of accumulator An is not affected See Also XOR XORS AND ANDS OR ORS
357. st Post modify Rx if specified Flags Affected RCF and RZF affected by post modification of Rx Opcode fe RR E ETE E ae EE E EE ED E ERE M e EH EEE E E EB EEE EO EH LE fee pma16 JMP pmat Res K US EHH E L RESCUE CPI CRM CHER X pma16 JMP pmat6 Ri Ee Ee EZ CHEN ES BINA ER ERI pma16 IMP pmat6 Ress AA E ES ER DICTI EU EB X pma16 ome An Pipo po fo f fofoj A jojojo ojojojojo Description A L ee ee JMP pma16 mod PC is replaced with second word operand Post modification of Rxregister is done if specified JMP An PC is replaced with content of accumulator An See Also Jcc CALL Ccc Example 4 14 26 1 JMP 0x2010 R2 Jump unconditionally to program memory location 0x2010 Decrement R2 by 2 Example 4 14 26 2 JMP A3 Jump unconditionally to program memory location stored in accumulator A3 Assembly Language Instructions 4 113 Individual Instruction Descriptions 4 14 28 MOV Move Data Word From Source to Destination Syntax 4 114 bel name dest sr L Oli wora w With RPT ok Clas P Mov tras aa toas Teese ta mov arts tara neral Tesa Teese ta Tae Tas ar date as Teese o wov wtimmetrsa 2 2 NR wow me inmsineta 2 2 NR a mov An ane I next mov ati Bena Tae Te asn a 3 1 mma a wo p aaaea a Le pa Tae Taa anan 1 1 oe pa wo Jm arte f E oe pa mov rre teves Tesis da C mov asea OO tebeo ases a mov emme J
358. sters as base value and adds the value in the second word operand Does not modify the base address register Selects one of 8 address registers as base value and adds the value in R5 Does not modify the base address register Indirect Short Relative name dest src Rx R5 next A name dest src Rx next A name dest src Rx next A name dest src Rx next A name Rx R5 src next A name Rx src next A name Rx src next A name Rx src next A name dest src R6 offset7 next A name R6 offset7 src next A Selects one of 8 address registers to be used as the ad dress post modifications of increment decrement and INDEX R5 are possible Selects PAGE R6 register as the base address and adds a 7 bit positive address offset from operand field b6 b0 This permits the relative addressing of 128 bytes or 64 words Does not modify the PAGE address register k is shown as constant Global Flag Relative Flag name TFn dma6 name dma6 TFn name TFn R6 offset6 name R6 offset6 TF n For use with flag instructions only Adds lower 7 bits of instruction to a fixed address base reference of zero 64 fixed flags are addressed by this mode beginning at ad dress 0000h For use with flag instructions only Adds lower 7 bits of instruction Isb set to zero to a address base reference stored in the PAGE register R6
359. store result in accumulator string AO Increment R3 by 2 Example 4 14 43 2 MULSPLS A2 A2 Multiply MR register to accumulator string A2 subtract PL from accumulator string A2 and store result to accumulator string A2 Assembly Language Instructions 4 137 Individual Instruction Descriptions 4 14 44 MULTPL Multiply and Transfer PL to Accumulator Syntax label name dest src mod Clock clk With RPT clk P mutter fanta moeras ranas 0 ur wil anti no Execution premodify AP if mod specified PH PL MR src An amp PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions Pro fis sa HS 12 HD to 9 Js v e 8 a EH 32 1 Jo MULTPL An dis epplefefbeibeiel ame x dma16 for direct or offset16 long relative see section 4 13 wutTPL An LAn inextA_ 1 1 Jo o rea an ejs ojs Ta a Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs ofthe product contained in product low PL register are stored in An Certain restrictions apply to the use of this instruction when interrupts are occuring in the background See Section 4 8 for more detail MULTPL aars Multiply MR by data memory word move PL to An MULTPL Ar An next A Multiply MR by An word move PL to An
360. structions Conditional code mnemonic used with conditional branch calls and test flag bit instructions Curly braces indicates this field is not optional Carry flag Total clock cycles per instruction n bit data memory address For example dma8 means 8 bit location data memory address If nis not specified defaults to dma16 Data pointer register 16 bits Flag addressing syntax as shown in Table 4 47 Test flag bit Used in opcode encoding only Flag addressing syntax as shown in Table 4 48 Fractional mode Global relative flag bit for flag addressing Interrupt enable mode n bit immediate value If n is not specified defaults to imm16 Constant field bits Multiply register 16 bits Accumulator pointer premodification See Table 4 45 Not condition on conditional jumps conditional calls or test flag instructions Not repeatable or not recommended Assembly Language Instructions 4 71 Legend Symbol NR Ng OF offsei n OM PC pmaln porin PH PL RCF Rx RZF SF STAT STR SV TAG TF1 TF2 TOS UM XM XSF XZF ZF 4 72 Meaning Value in repeat counter loaded by RPT instructions Value in string register STR Overflow flag n bit offset from a reference register Overflow mode Program counter 16 bits n bit program memory address For example pma8 means 8 bit program memory address If nis not specified defaults to pma16 n bit I O port address Certain instructions multiply
361. t 1 COND TRUE CIN1 has its conditional call taken CNIN1 has its conditional call ignored JIN1 has its conditional jump taken JNIN1 has its conditional jump ignored Dn 0 COND FALSE CIN1 has its conditional call ignored CNIN1 has its conditional call taken JIN1 has its conditional jump ignored JNIN1 nas its conditional jump taken T D 1 COND2 TRUE CIN2 has its conditional call taken CNIN2 has its conditional call ignored JIN2 has its conditional jump taken JNIN2 nas its conditional jump ignored T Dy 0 COND2 FALSE CIN2 has its conditional call ignored CNIN2 has its conditional call taken JIN2 has its conditional jump ignored JNIN2 has its conditional jump taken t COND2 may be associated instead with the comparator function if the comparator Enable bit is set Please refer to Section 3 3 Comparator for details Internal and External Interrupts INT3 INT4 INT6 and INT7 are external interrupts which may be triggered by events on the PD PD3 PD4 and PDs pins These interrupts are supported whether the D port pins are programmed as inputs or outputs When programmed as an output the pin effectively triggers a software interrupt INT5 is an external interrupt triggered by a falling edge event on any of the F port inputs It is triggered if all eight port F pins are held high and then one or more of these pins is taken low Only the transition from OxFFh all high to one or more pins low
362. t or offset16 long relative see section 4 13 sus aran ET I D ECL DP DD DE DE mal sms ap I I T Ev D b p TSTS Ta sms aas e Dr E E D I b p p o E E sus Aum pato o DE Lo T DE Eo To Eo T8 E Description Subtract the value of the src string from value of the dest string and store the result in the dest string If three operands are specified then subtract value of src string from value of src string i e src src1 and store result in deststring Note that substraction is performed in 2 s complement and therefore the CF carry flag may get set even when subtracting a smaller value from a large value Assembly Language Instructions 4 177 Individual Instruction Descriptions SUBS ANI An adis SUBS Adi An An SUBS Ar An An Subtract An string from An string store result in An string SUBS An An PH Subtract product high PH register from An string mode This instruction ig nores the string count executing only once but maintains the CF and ZF status of the previous multiply or shift operation as if the sequence was a single string Word alignment with PH is maintained i e PH is subtracted from the second word of the string Also only the second word is copied to the destination string Example 4 14 81 1 SUBS AO AO R2 Subtract data memory string beginning at address in R2 from accumulator string AO put result in accumulator string AO then increment R2 by 2 Example 4 14 81 2 SUBS A
363. t Accumulator Syntax labe name dest src mod Clock clk With RPT clk SHLAC TA AL next A Execution premodify AP if mod specified dest src lt lt 1 PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions re rs 14 13 12 11 10 o fe v e a js 2 1 SHLAC An LAn p nextAl 1 1 1 Jo o nexta An jojo o o a a Description Premodify accumulator pointer if specified Shift source accumulator src or its offset left by one bit and store the result in the destination accumulator or its offset LSB of result is set to zero Example 4 14 66 1 SHLAC A1 A1 Shift accumulator A1 by one bit to the left Example 4 14 66 2 SHLAC Al Al A Predecrement accumulator pointer AP1 by 1 Shift the newly pointed accumulator A1 by one bit to the left store the result in accumulator A1 Assembly Language Instructions 4 161 Individual Instruction Descriptions 4 14 67 SHLACS Shift Left Accumulator String Individually Syntax iae rame sess Clock ok wora w With RPT ok crass SHLACS Ari An Execution dest src lt lt 1 PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pro 15 14 fia 12 to o 8 e 8 a J2 1 fo suiacs art ar 1 11 1 foto titi an foto fo Jo A A Description Shift the source accumulator string src or its offset left one bit and store the
364. t Ar Execution PH PL src lt lt SV dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode emnes e speIspe Te Ie I 15 T7 I5 T4 T4 T T2 T 02 ins NN a ccoo e o dma16 for direct or offset16 long relative see section 4 13 EN snares A An tjs tjo ojs t an i s i fot Jo A A Description Shift accumulator string or data memory string pointed by adrs to left nsy bits as specified by the SV register The resultis zero filled on the right and either zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the product high PH register The lower 16 bits ofthe result product low PL register are added to the destination accumulator or its offset This instruction propagates the shifted bits to the next accumulators in the string SHLAPLS An adrs Shift data memory string left add PL to An SHLAPLS Ar An Shift An string left addb PL to An See Also SHLAPL SHLTPL SHLTPLS SHLSPL SHLSPLS Example 4 14 69 1 SHLAPLS AO R4 R5 Shift the string pointed by the byte address stored in R4 by ney bits to the left add the shifted value PL with accumulator string and store the result in accumulator string AO Add R5 to R4 and store result in R4 PH holds the upper 16 bits of the shift Example 4 14 69 2 S
365. t filter coefficient x sample data pointed by RXeven h 1 second filter coefficient pointed by DP y result stored in three consecutive accumulators 32 bit pointed by An between every accumulation IF TAG 1 RXeyen RXeven R5 for circular buffering ELSE RXeven if Rx is specified in the instruction ENDIF PC PC 1 final result y 2 co MA ANA Execution is detailed in section 4 11 Flags Affected None Opcode a e e oS eee eee ee rie An Re s Tt tt foi foto Aa ojojo rx fifi Description Finite impluse response FIR filter Execute finite impulse response filter taps using coefficients from program memory and samples from data memory Address reference for data memory is indirect using specified Rx and address reference for program memory is contained in DP register This instruction must be used with RPT instruction When used with the repeat counter it will execute 16 x 16 multiplication between indirect addressed data memory buffer and program memory coef 32 bit accumulation and circular buffer operation Each tap executes in 2 cycles See section 4 11 for more detail on the setup of coefficents and sample data Selected register Rx must be even During FIRK execution interrupts are queued See Also RPT FIR COR CORK Example 4 14 19 1 RPT 0 FIRK AO RO Computes the calculation for 2 tap FIR filter with 32 bit accumulation See section 4 11 for more detail on the setup of coefficients
366. t in dest accumulator See Also NOTACS AND ANDB ANDS OR ORB ORS XOR XORB XORS NEGAC NEGACS Example 4 14 49 1 NOTAC A3 A3 A Predecrement accumulator pointer AP3 One s complement invert bits accumulator A3 and put result in accumulator A3 Assembly Language Instructions 4 143 Individual Instruction Descriptions 4 14 50 NOTACS One s Complement Negation of Accumulator String Syntax iae rame ses se Glock ok wora w With RPT ok Class NOTACS Ari An Execution dest NOT src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pro 15 14 fia 12 to o 8 7 e 8 a 3 2 fo noracs Amb an 11 1 foto titi an ojojojo t o A A Description Perform one s complement of src accumulator string and store result in dest accumulator string See Also NOTAC AND ANDB ANDS OR ORB ORS XOR XORB XORS NEGAC NEGACS Example 4 14 50 1 NOTACS A3 A3 Take the one s complement invert bits of the accumulator string A3 and put result in accumulator string A3 4 144 Individual Instruction Descriptions 4 14 51 OR Bitwise Logical OR Syntax abel name aest sei weil mod Glock ok Word w win RPT ci ass p onum H T aves a o ant Artic immi6 next A OR lA An Anf next A or Tntfagads t t NR ea OR rFn cd LRA m Execution premodify AP if mod specified dest dest
367. t to comparing each bit of the string The accumulator status is modified representing the outcome of the entire operation Examine the following examples Table 4 43 Initial Processor State for String Instructions Registers register value APO 22 ACO AC4 AC8 AC12 OXAAAA AC16 AC20 AP1 21 0x15 AP2 11 0x0B AP3 29 0x1D ACi AC2 AC3 AC5 AC6 AC7 AC9 AC10 AC11 OXAAAA AC13 OxAAAA AC14 OXAAAA AC15 OxAAAA AC17 AC18 AC19 AC21 0x1223 AC22 OxFBCA AC23 0x233E data memory address data 0x0200 0x12AC 0x0201 OxEE34 0x0202 0x9086 0x0203 OxCDE5 program memory adaress data 0x1400 0x0123 0x1404 OXFEDC 0x1401 0x4567 0x1402 0x89AB 0x1403 OXCDEF 0x1405 0xBA98 0x1404 0x7654 0x1405 0x3210 Example 4 8 1 MOV STR 4 2 string length 2 MOVS A0 0x1400 Refer to initial the processor state in Table 4 43 AO points to AC2 Consider a program memory location string of length 4 at 0x1400 OxCDEF89AB45670123 STR equal to 4 2 2 defines a string length of 4 Final result AC220x0123 AC3 0x4567 AC4 0x89AB and AC5 0xCDEF Example 4 8 2 MOV STR 3 2 string length 3 ADDS Al Al 0x0200 Refer to the initial processor state in Table 4 43 A1 is AC21 A1 is AC5 the Assembly Language Instructions 4 55 String Instructions 4 56 A1 string is OX233EFBCA1223 and 0x200 0x9086EE3412AC STR 3 2 1 defines a string
368. ten Rate CB E Sek gie nea 2 5 2 22 Arithmetic Logic Unit eeu ie Deu Re bed rede een 2 7 2 3 Data Memory Address Unit 0 e 2 11 2 3 1 RAM Configuration siasa siomi gadaa daa teeta 2 12 2 3 2 Data Memory Addressing Modes esee 2 13 2 4 Program Counter Unit sesse n smrecie meai aiii ai n 2 14 2 5 BID EogiC Ta sos toro riores car duo Bad cR eder 2 14 2 6 Memory Organization RAM and ROM n 2 15 205 Memory Map zccmeecete temere Rr tede e eR BO pen Ste RARE Pacte 2 15 2 6 2 Peripheral Communications Ports cece eee eee ee eee 2 16 2 6 3 Interrupt Vecto s caricia da 2 18 2 6 4 ROM Code Security e e nents 2 19 2 6 5 Macro Call Vectis sssi os cekbsce Ree ddata i i paa A dena PC D A A a Ro ER 2 22 24 Interruptor Adora 2 22 2 8 Timer RegisSterS ssussssssssssses Rhen 2 26 2 9 Clock Control 1 ui oet tad dde td a a A ee ed iud 2 29 2 9 1 Oscillator Options ssssssssssssssee ete eens 2 29 2 9 2 PLL Performance ooc occccconnccnnccc n nnn 2 29 2 9 3 Clock Speed Control Register ccc eect eee eee 2 30 2 9 4 RTO Oscillator Trim Adjustment 0000 cece eee 2 32 2 10 Execution TIMING 0003 A pare res e inde AAA 2 33 2 11 Reduced Power Modes vegar a naaa Td R RRR R RRR nn 2 34 Peripheral Functions 2 0366 iio a eee eee meses 3 1 Slt 6 arte crriao baste rap Sharh ease eda nods bes cn aia 3 2 vii Contents viii 3 1 1 General Purpose I O Porte
369. that SFLAG uses a word address 0x0003 while the MOV instruction uses a byte address 0x0003 2 The first instruction sets the flag tag bit at flag address 0x0003 Flag address 0x0003 represents the 17th bit of the 3 d word or 6th byte of RAM In the second instruction this flag bit is placed in the TAG status bit of the STAT and the value in RAM location 0x0003 2 is placed in AO The third instruction resets the flag tag to O at the same flag address The fourth instruction reads the same word memory loca tion and writes the TAG bit of STAT which is now 0 Note SFLAG 0x0003 could have been replaced by STAG 0x0003 2 and RFLAG 0x0003 could have been replaced by RTAG 0x0003 2 Example 4 5 9 SFLAG 0x0005 MOVB AO 0x000b RFLAG 0x0005 MOVB AO 0x000b Refer to Figure 4 4 for this example The SFLAG instruction sets the 17th bit tag flag of the 5th word of RAM The MOVB instruction gets the lower byte of the 5th word of RAM and puts it in AO In addition the TAG bit of the STAT register is set Ifthe MOVB instruction addressed 0x000A instead of 0x000B the STAT register would still be updated with the same tag flag bit the 17th bit of the 5th word of RAM This means that odd byte locations in RAM RAMogd have the same tag flag as the preceding byte location RAMogg 1 For exam ple the 7th word of RAM is made up of two bytes 0x000E and 0x000F These two byte locations share the same tag flag bit MSP50P614 MSP5
370. the next PC address is stored in the TOS register and is reloaded from TOS after the interrupt encounters an IRET instruction Call and jump instructions also store the next instruction address by adding PC 2 and then storing the result in the TOS register Upon encountering a RET instruction the TOS value is reloaded to the PC Call instructions may not precede RET instructions Similarly a RET instruction may not immediately follow another RET instruction In these conditions pipeline operations breaks down and the PC never recovers its re turn address from the TOS register The processor stalls and the only solution is to reset the device On the other hand RET can be safely replaced by IRET eliminating processor stalls in all conditions However IRET takes one more cycle than RET TOS Thetop of stack TOS register holds the value of the stack pointed by the stack register R7 The MSP50P614 MSP50C614 hardware uses TOS register for very efficient returns from CALL instructions Figure 4 1 shows the operation of the TOS register When call instructions are executed the old TOS register value is pushed into the stack by pre incrementing R7 The current PC value is incremented by 2 to compute the final return address and is then stored in the TOS register Thus the TOS register holds the next PC value pointing to the next instruction When the subroutine reaches the RET instruction the program counter PC is loaded with the TOS register
371. then one or more of these pins is taken low Port F therefore is especially useful as a key scan interface VO 3 1 3 Dedicated Output Port G Port G is a 16 bit wide output only port The output drivers have a Totem Pole configuration The data driven by the output pin can be controlled by setting or clearing the appropriate bit in the G port Data register address 0x2C This is done using the OUT instruction with the 0x2C address as an argument Af ter RESET low the default settings for the G port outputs are O logical low Totem Pole Output Port G Data register address 0x2Ch Possible input data values N A Possible output data values 0 lt LOW 1 High Value after RESET low 0 Low The following table shows the bit locations of the port G address mapping G port Data address OX2C 16 bit wide location read and write 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 GO 0x0000 default state of data register after RESET low Peripheral Functions 3 5 VO 3 1 4 Branch on D Port 3 1 5 Instructions exist to branch conditionally depending upon the state of ports Dg and Dy These conditionals are COND1 and COND2 respectively The condi tionals are supported whether the Do and D4 ports are configured as inputs or as outputs The following table lists the four possible logical states for Dy and D4 along with the software instructions affected by them Do l
372. these components as close as possible to the OSC N OSCour and PLL pins 1 8 Figure 1 3 RESET Circuit C605 and C604 Preliminary Information gt To Pin 1 of Optional Scanport MSP50P614 only Connector Vpp IN914t 5V VDD 100 kQ IN914 RESET kot Inside the RESET MSP50P614 MSP50C614 1pF Reset 20 T O Switch Vss To Pin 2 of optional scan port connectort t Ifitis necessary to use the software development tools to control the MSP50P614 in application board the 1 KQ resistor is need ed to allow the development tool to over drive the RESET circuit on the application board This Diode can be omitted shorted if the application does not require use of the scanport interface See Section 7 1 1 regarding scan port bond out Introduction to the MSP50C614 1 9 Terminal Assignments and Signal Descriptions 1 6 Terminal Assignments and Signal Descriptions Table 1 1 Signal and Pad Descriptions for the C614 SIGNAL PAn PA7 PBo PB7 PC PC7 PDo PD7 PEo DES PFo PF7 PGo PG7 PGg PG15 PAD NUMBER 75 gt 68 85 gt 78 821 185 11 63 5 56 31 gt 24 49 gt 42 39 gt 32 1 0 Input Output Ports 1 0 1 0 1 0 1 0 1 0 l O DESCRIPTION Port A general purpose I O 1 Byte Port B general purpose I O 1 Byte Port C general purpose I O 1 Byte Port D general purpose I O 1 Byte Port E general purpose lO 1 Byte Port F key scan input 1 Byte Port
373. tion Mnemonic Description A EXC imma o P P the repeat counter with an 8 bit constant and execute the instruction that follows imm8 2 times Interrupts are queued during execution o 1 MOV STR imm8 Load the STR register with an 8 bit constant ESEJ MOV SV imm4 Load the SV shift value register with a 4 bit constant Assembly Language Instructions 4 43 Bit Byte Word and String Addressing Table 4 38 Class 9c Instruction Description Lo MOV APn imm6 Load the accumulator pointer AP with a five bit constant ADD APn imm5 Add a five bit constant imm to the referenced accumulator pointer AP Table 4 39 Class 9d Instruction Description Marks the beginning of loop Queue interrupts and pushes the next PC value onto a temporary stack location If R4 is not negative pops the temporary stack value back on the PC and decrements R4 by n If R4 is negative the instruction is a NOP and execution will exit the loop nis either 1 or 2 1 IDLE Stops processor clocks Device enters low power mode waiting on an interrupt to restart the clocks and execution INTE Sets IM bit in status register to a 1 thus enabling interrupts 1 INTD Sets IM bit in status register to a 0 thus disabling interrupts Sets XM in status register to 0 disabling sign extension mode Sets FM in status register to 1 enabling multiplier shift mode for signed fractional arithmetic Sets FM in status register to 0 enablin
374. tion is detailed in section 4 11 Flags Affected None Opcode pau re esse spese p pues 00 Ee e wpepep sme ps e Description Finite impulse response FIR filter Execute finite impulse response filter taps using coefficients from data memory and samples from data memory The instruction specifies two registers Rx and R x 1 which sequentially address coefficients and the sample buffer in the two instruction FIR tap sequence This instruction must be used with RPT instruction When used with the repeat counter it will execute a 16 x 16 multiplication between two indirect addressed data memory buffers 32 bit accumulation and circular buffer operation Executes in 2 instruction cycles Selected register Rx must be even This instruction also uses R x 1 See section 4 11 for more detail on the setup of coefficients and sample data During FIR execution interrupt is queued 4 100 Individual Instruction Descriptions See Also RPT FIRK COR CORK Example 4 14 18 1 RPT 0 FIR AO RO Computes the calculation for 2 tap FIR filter with 32 bit accumulation See section 4 11 for more detail on the setup of coefficients and sample data Assembly Language Instructions 4 101 Individual Instruction Descriptions 4 14 19 FIRK FIR Filter Function Coefficients in ROM Syntax TI ER Word wine x ene jrmkj An x 2 ng 9a Execution With RPT N 2 mask interrupts RPT counter N 2 MR 0 firs
375. tiplier fractional mode may be enabled disabled by setting resetting the FM bit of STAT When the multiplier is in fractional mode the multiplier is shifted left 1 bit to form a 17 significant bit operand Fractional mode avoids a divide by 2 of the product when interpreting the input operands as signed binary fractions Q formats Fractional mode works with string mode as well Example 4 6 1 SXM MOV AO Ox7FFF MOV MR Ox7FFF MULTPL A0 AO Ox7FFF Ox7FFF PH Ox3FFF A0 0001 SFM MULTPL A0 A0 PH Ox7FFE AO 0002 This example illustrates the differences between a regular multiply and a frac tional mode multiply The first multiply in the above code is nonfractional The Hardware Loop Instructions high word of the result is stored in the PH register and is 0x3FFF The low word is stored in AO as 0x0001 If the two numbers are considered as Q15 fraction al numbers all bits are to the right of the decimal point then the result will be a Q30 number To translate a Q30 number back to a Q15 number first left shift the number MOV AO PH SHL A0 A0 and then truncate the lower word ig nore A0 When fractional mode is set the left shift is done automatically MOV AO PH Thus the desired Q15 result is already in the PH register 4 7 Hardware Loop Instructions These instructions enhance both execution speed and code space requirements for procedures that use short loop sequences Because of pipeline delays and t
376. tis coded as zero Table 4 2 Addressing Mode Encoding pe pe e lo owe rea am contains addressing mode bits 5 7 See Table 4 4 for details Rx is the register being used See for Table 4 3 for details pm is the post modification flag See Table 4 3 for details next A is the accumulator pointer premodification field See Table 4 5 for details Assembly Language Instructions 4 9 Instruction Syntax and Addressing Modes Table 4 3 Rx Bit Description Operation Table 4 4 Addressing Mode Bits and adrs Field Description H addressing mode encoding adrs Relative epeat Addressing ibis bias Operation aars Izjelsi4 s 2 t o Modes i clk am Rx x 2 0 7 pm Ber pr ze pee pe 0 Lope eem pp oo om Cp qm PET O E E CA e go DUI 111 Rx go Relative to R5 Long relativet T dma16 and offset16 is the second word t np is RPT instruction argument 4 10 Instruction Syntax and Addressing Modes Table 4 5 MSP50P614 MSP50C614 Addressing Modes Summary ADDRESSING Direct Long Relative Relative to R5 INDEX SYNTAX name dest src dma16 2 next A name dma16 2 src next A name dest src Rx offset16 next A name Rx offset16 src next A name dest src Rx R5 next A name Rx R5 src next A OPERATION Second word operand dma16 used directly as memory address Selects one of 8 address regi
377. to accept a custom device program the customer must submit a new product release form NPRF This form describes the custom features of the device e g customer information prototype and production qualities symbolization etc Sections 1 and 2A of the NPRF are completed by TI personnel A copy of the NPRF can be found in section 7 6 TI generates the prototype photomask then processes manufactures and tests 25 prototype devices for shipment to the customer Limited quantities in addition to the 25 prototypes may be purchased for use in customer evaluation Device Production Sequence All prototype devices are shipped with the following disclaimer Itis understood that for expediency purposes the initial 25 prototype devices and any additional prototype devices purchased were assembled on a prototype i e not production qualified manufacturing line whose reliability has not been characterized Therefore the anticipated inherent reliability of these devices cannot be expressly defined The customer verifies the operation and quality of the prototypes and responds with either written customer prototype approval or disapproval A nonrecurring mask charge that includes the 25 prototype devices is incurred by the customer A minimum purchase is required during the first year of production Customer Sends Code in TI sends sample devices QBN or TITAG format and to customer for completes Section 1 of the verification NPRF TI
378. to accumulator string AO put result in accumulator string AO Note that the address 0x13F2 is a program memory address Example 4 14 53 3 ORS AO AO AO OR accumulator string AO to accumulator string AO put result in accumulator string AO 4 148 Individual Instruction Descriptions 4 14 54 OUT Output to Port Syntax labe rame aes sre Taa ok wora w With Rer crass P out Iona teary oere muss n TT out poe my tae ms oa Execution port4 or port6 src PC PC w Flags Affected XSF XZF are set accordingly src is adrs TAG bit is set accordingly Opcode instructions Pro fis fra fis 2 HD fro o o v e S a EH 2 1 fo OUT por adis apto To E e as dma16 for direct or offset16 long relative see section 4 13 jour ports An HH HHRHH HH ts fo an po t al Description Output to 1 O port Words 16 bits in memory can be output to one of 16 port addresses Words 16 bits in the accumulators can be output to these same 16 port addresses or to an additional 48 port addresses Note that port4 address is multipled by 4 to get the actual port address See Also OUTS IN INS Example 4 14 54 1 OUT 3 0x0200 2 Outputs the content of word memory location value stored in 0x0200 to I O port at location 0x0C PBDIR port Note that address 3 converts to 3 4 Oxc Assembly Language Instructions 4 149 Individual Instruction Descriptions 4 14 55 OUTS
379. to the speech development board Ensure that the scanport and the development board are powered on the red LED and the green LED on the MSP Scanport are both illuminated before attempting to start the code development tool Click on Start menu go to Programs EMUC6xx and click on MSP50C6xx development tool menu item To open a project click on Project New Project and select the desired project file e g C 614 PROJECTS MELP1 MELP1 RPu Click on Project Build to assemble and link the constituent files of the project Then click Debug Eprom Programming and select Blank Check Program to burn the code onto a P614 device Alternatively press F3 then ENTER Set the breakpoint at the _main label To do this click on the blue magnifying glass icon at the top of the screen then from the Symbol list choose main Click OK and the Program Window will display the label and the surrounding code The line of code at main MOV R7 STACK is highlighted in cyan Setthe breakpoint by moving the mouse to this line holding the SHIFT key and clicking the right mouse button Click on nit Init Allto reset the P614 All the values in the RAM window should turn blue and should be zero 0000 To run the program click on the yellow lightning black centipede Run Internal icon at the end of the tool bar The program should halt at the _main label All the values in the CPU window should be blue and zero apart from PC STAT DP RZF and Z
380. tor A 1 Neither ac cumulator or offset accumulator is modified 1 0 OR An An imm16 next A Logical OR a long constant with accumulator A 0 or 1 ORS An An pma16 Store the result in accumulator A 0 or offset accumulator A 1 ALU status is modified 1 0 1 AND An An imm16 next A Logical AND a long constant with accumulator A 0 or ANDS An An pma16 1 Store the result to accumulator A 0 or 1 ALU status is modified 1 1 0 XOR An An imm16 next A Logical exclusive OR a long constant with accumulator A 0 XORS An An pma16 or 1 Store the result to accumulator A 0 or 1 ALU status is modified 1 1 1 MOV MR mm16 next A Load a long constant to MR in signed mode No change in status 4 4 3 Class 3 Instruction Accumulator Reference 4 30 These instructions reference the accumulator and in some instances specific registers for transfers Some instructions use a single accumulator operand and others use both the accumulator and the offset accumulator to perform operations between two accumulator values The A bitin the instruction word reverses the sense of the addressed accumulator and the addressed offset accumulator In general if A 1 the instruction uses the offset accumulator as the input operand on single accumulator operand instructions It interchanges the arithmetic order subtract compare multiply accumulate etc of the two operands
381. tor A2 Assembly Language Instructions 4 135 Individual Instruction Descriptions 4 14 42 MULSPL Multiply and Subtract PL From Accumulator Syntax label name dest src mod Clock clk With RPT clk map fanta eese ranas Uo L wucse wil anti no a Execution premodify AP if mod specified PH PL MR src dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions se ss sa fis 12 HD to 9 je v e 8 a ja 92 1 Jo MULSPL A adis ppbbbbLiel s x dma16 for direct or offset16 long relative see section 4 13 wutsPL An LAn next aL ts Jo o rea an tjs ojo o o A A Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register are subtracted from dest Certain restrictions apply to the use of this instruction when interrupts are occuring in the background See Section 4 8 for more details MULSPL adrs Multiply MR by RAM word substract PL to An MULSPL Ar An next A Multiply MR by An word substract PL to An See Also MULSPLS MULTPL MULTPLS MULAPL MULAPLS Example 4 14 42 1 MULSPL AO R3 Multiply MR with the contents of R3 subtract PL from accumulator AO and store result in accumulator AO post
382. tory or on your desktop icon Your scanport interface and the target board must be connected and turned on before the emulator can be successfully used If the opening window comes up without any messages the system is working properly If the WARNING Development board not detected message appears there is a communication problem between the PC and the board Possible reasons are no power supply no chip in socket bad chip bad connection or board not working 5 6 1 The Open Screen The open screen is the initial screen blank screen of the emulator software as shown in Figure 5 12 If this is the first time you are using emulator software or you want to create a new project you should choose the Project menu to create a new project If you already created a project and it appears at the bottom of project menu project list you can open the project just by clicking the appropriate project see Figure 5 13 Figure 5 12 Open Screen ORONS Deny Int Minow Code Development Tools 5 13 Software Emulator Figure 5 13 Project Menu ha MSP58P70 Code Development Tool EMU File Options enpo Mii Window Hel O ject rig D Ir Hey Fant EST ee oc oot Ghose Project 08 OO oS Make current Project i0 oor 18 pnp Build current Project 90 projects ml B ID ED OU ROR COUNT Reo 210 AE MTSPOSPIDAERHIYPDES RETI oou o Ce CO C2 CJ LJ LJ LJ LJ tJ LJ LJ LG LJ 1 O OO O O CI O CI C LI 3 co oO
383. tract PH from An store result in An See Also MOVSPHS MOVAPH MOVAPHS MOVTPH MOVTPHS Example 4 14 36 1 MOVSPH A0 MR R3 R5 Load the content of byte address created by adding R3 and R5 to MR register At the same time subtract PH register from accumulator AO store result in AO Assembly Language Instructions 4 127 Individual Instruction Descriptions 4 14 35 MOVSPHS Move String With Subtract From PH Syntax Tae name est we set T ak With RPT ok __ MOVSPHS An MR aars Table 4 46 Table 4 46 Execution An An second word PH MR lt contents of adrs PC PC w Flags Affected TAG OF SF ZF CF are set accordingly Opcode Instructions Pis U 14 13 12 11 10 o jo v Je sa aja Jo ME lc Ke RE SERE dma16 for direct or offset16 long relative see section 4 13 Description Move data memory word string to MR subtract PH from second word An string Store result in An Certain restrictions apply to the use of this instruction when interrupts are occuring on the background See Section 4 8 for more details See Also MOVSPH MOVAPH MOVAPHS MOVTPH MOVTPHS Example 4 14 37 1 MOVSPHS A0 MR R3 R5 Loadthe content of byte address created by adding R3 and R5to MR register Atthe same time subtract PH register from second word of AO string store result in AO string 4 128 Individual Instruction Descriptions 4 14 36 MOVT Move Tag From Source to Destination Syntax iae rame dest
384. trim value and a0 a0 0x01 look at bit 0 of trim value JZ trimbito0 do nothing if it is zero or a0 0x0200 else set bit 9 trimbitO endi orb a0 PLLMBITS set PLLM for CPU clock of 8 MHz 6 6 MSP50C614 MSP50P614 Initialization Codes mov save clkspdctrl a0 save the ClkSpdCtrl value for later when waking up from mid or deep sleep mov 0 TIM2REFOSC TIM2IMR disable TIMER 2 out IntGenCtrl a0 mov a0 6553 setup a 200 ms period out TIM2 a0 load TIM2 and PRD2 in one fell swoop mov a0 TIM2ENABLE TIM2REFOSC TIM2IMR out IntGenCtrl a0 use 32 kHz crystal as source wake up from TIM2 out ClkSpdCtrl a0 set clock to full speed idle go to sleep nop wake up 200 ms later clock running at full speed nop nop gp ACKCKORGAORK Koh Rok Ko Roco ce eoe oo ale ee eoe eoe e e e eoe oe eese ie eoe dee albe e eoe oe eae beoe eee Upon reset all ports are set to input and port G output is set low 0x0000 Therefore it remains only to enable the pullups On port F FERRE EAE OR ee ap ek ab RR RR ER abesse ap IR sees ab RRR ataca in a0 IntGenCtrl or a0 PFPULLUPS enable port F pullups and a0 TIM2IMR turn off TIMER 2 interrupt and a0 TIM2ENABLE turn off TIMER 2 out IntGenCtrl a0 PRR R RRR RRR RRR RRR RRR KKK KK RK KR KKK KK KER KEK KR KEK KEK KERR KKK KEE KEK KKK KK Set the DAC to 10 bits C3x style For C5x style set bit 3 high PRA
385. ts per second 8 kHz S R 2048 words 0 3 k words 30 k words 15 seconds of speech BIST 8 bit PCM speech data rate 64 0 k bits per second 8 kHz S R 2048 words 30kwords 7 5 seconds of speech 6 14 Chapter 7 Customer Information Customer information regarding package configurations development cycle and ordering forms are included in this chapter Topic Page 7 1 Mechanicalllntormatio n a na eee eee 7 2 7 2 Customer Information Fields in the ROM ooooooooooo 7 7 7 3 Speech Development Cycle Lussseuuuees 7 8 7 4 Device Production Sequence eeeeeeeeeeeee 7 8 7 5 Ordering Information e RII 7 10 7 6 New Product Release Forms sss ss e c c e e s s x x x c e x x K K K eee 7 10 7 1 Mechanical Information 7 1 Mechanical Information The C614 is normally sold in die form but is also available in 100 pin PJM packages The P614 is available in a windowed ceramic package 120 pin PGA F7 1 NOTE Scan Port Bond Out The Scan Port Interface on the MSP50C6xx devices has five dedicated pins and one shared pin that need to be used by the MSP50Cxx development tools The SCANIN SCANOUT SCANCLK SYNC and TEST pins are dedicated to the scan port interface The RESET pin is shared with the application These pins may play an important role in debugging any system problems For this reason these pins MUST be bonded out on any C614 produ
386. tting breakpoint af ter IDLE instruction within two instruction cycle Code Development Tools 5 67 5 68 Chapter 6 Applications This chapter contains application information on application circuits proces sor initialization sequence resistor trim setting synthesis code memory over lays and ROM usage Topic Page Gales ApplicationiGircuitses sc E E 6 2 6 2 MSP50C614 MSP50P614 Initialization Codes 6 4 6 3 Texas Instruments C614 Synthesis Code 6 8 6 4 ROM Usage With Respect to Various Synthesis Algorithms 6 14 6 1 Application Circuits 6 1 Application Circuits Minimum Circuit Configuration for the C614 P614 Using Resistor Trimmed Oscillator To pin 2 of Scan Port Connectort optional MSP50P614 only 1N914 RREFERENCE MSP50C614 MSP50P614 t The diode across Vpp and Vpp may be omitted shorted if the application does not require use of the Scan Port Interface The same applies for the 1 kO resistor which appears at the RESET pin the resistor may be shorted if not using the Scan Port However the footprintfor the resistor is strongly recommended for any C614 production board Refer to the Important Note regarding Scan Port Bond Out appearing in Chapter 7 Note that there are 5 each of the pins Vpp and Vss Each of these should be connected with separate decoupling capacitors 0 1 uF included for each VDD 6 2 Application
387. ultiplier and a 16 bit arithmetic logic unit ALU The block diagram of the CU is shown in Figure 2 2 The multiplier block is served by 4 system registers a 16 bit multiplier register MR a 16 bit write only multiplicand register a 16 bit high word product register PH and a 4 bit shift value register SV The output of the ALU is stored in one 16 bit accumulator from among the 32 which compose the accumulator register block The accumulator register block can supply either one operand to the ALU addressed accumulator register or its offset register or two operands to the ALU both the addressed register and its offset The multiplier executes a 17 bit by 17 bit 2s complement multiply and multiply accumulate in a single instruction cycle The sign bit within each operand is bit 16 and its value extends from bit O LSB to bit 15 MSB The sign bit for either operand multiplier or multiplicand can assume a positive value zero or a value equal to the MSB bit 15 In assuming zero the extra bit supports unsigned multiplication In assuming the value of bit 15 the extra bit supports signed multiplication Table 2 1 shows the greater magnitude achievable when using unsigned multiplication 65535 as opposed to 32767 Table 2 1 Signed and Unsigned Integer Representation Unsigned Signed Decimal Hex Hex 65535 OxFFFF OxFFFF 32768 0x8000 0x8000 32767 Ox7FFF Ox7FFF 0 0x0000 0x0000 During multiplication the lower word LSB of the
388. ultiply or shift operation as if the sequence was a single string MOVS An An Move program memory string at An to An See Also MOVU MOV MOVT MOVB MOVBS Example 4 14 31 1 OVS A2 R6 Load the string pointed by R6 to accumulator string A2 Example 4 14 31 2 MOVS R4 A2 Copy the accumulator string A2 to data memory location pointed by R4 Example 4 14 31 3 OVS 0x0100 2 AO Transfer the program memory word string pointed by content of AO to the data memory word location 0x0100 This is a lookup instruction Example 4 14 31 4 OVS A2 0x1400 Transfer program memory string at 0x1400 to accumulator string A2 Example 4 14 31 5 MOVS Al Al Transfer accumulator string A1 to accumulator string A1 Example 4 14 31 6 MOVS Al A1 Transfer accumulator string A1 to accumulator string A1 Example 4 14 31 7 OVS A2 PH Transfer value in PH to accumulator string A2 PH is copied to the second word of the string 4 126 Individual Instruction Descriptions 4 14 34 MOVSPH Move With Subtract from PH Syntax MOVSPH An MR aars Table 4 46 Table 4 46 Execution An amp An PH MR lt contents of adrs PC PC w Flags Affected TAG OF SF ZF CF are set accordingly Opcode Instructions re rs rera 12 11 o Jo jo v Jef stats jets Jo a CR EH CERCLE RE RE NN dma16 for direct or offset16 long relative see section 4 13 Description Move data memory to MR sub
389. ume the references made to data memory and accumulators are long data strings causing pointers to auto increment Incrementing pointers does not affectthe permanent value stored in Rxor APn registers For arithmetic string operations carries from one word operation will automatically be linked to the carry in of the next word operation Additionally status equal to zero will be detected on the result as a long string These combinations provide efficient and convenient means to operate between lists or stings or between a fixed location and a list or string All string instructions have a suffix S In this text string instructions are written as nameS During Assembly Language Instructions 4 53 Hardware Loop Instructions the execution of a string instruction interrupts are queued Queued interrupts are serviced according to their priority after the string operation is complete In addition to repeat and string instructions the combination of repeated string instructions has a very useful function Since there is only one counter to control the hardware repeat count itis not possible to nest repeats and strings When a repeat instruction is followed by a string instruction the string register count is replaced by the value in the preceding repeat instruction This offers greater utility in some programs and avoids load and store operations on the string register Loop instructions This is a software loop with an explicit reference to R4
390. umulator pointers We divide a 16 bit integer located in AO by a 16 bit integer located in AO We return the quotient in AO and the remainder in AO We make use of A3 and A3 for scratch pads We also set flag 1 if a division by zero is attempted and zero out the quotient and the remainder in this case We also use PH for temporary storage of the divisor 5 10 3 Function Calls 5 50 Every function is associated with a stack frame A regular C program is initially given control by a call to main A C program starts with a jump to the _main symbol which must therefore be present in the C source code The stack frame has the following structure First Argument Low Adaress eee v i i SP MEE High Address BP is the frame pointer base pointer SP the stack pointer We use R7 for stack pointer and yet another register for BP REG BP R5 because of its special arithmetic capabilities Before a function is called the arguments are pushed on the stack first argument first The function call automatically pushes the return address on the stack Immediately upon entering the function body the current BP is pushed on the stack to preserve it so that the stack pointer now points to the next location This location is copied to REG BP which becomes our fixed reference point for the current function Locals are then allocated on the stack from this starting location When the function returns SP is made to p
391. unchanged If the OM status register bit is reset and an overflow occurs the overflowed results are placed in the accumulator without modification Note that logical operations cannot result in overflow Assembly Language Instructions 4 51 MSP50P614 MSP50C614 Computational Modes 4 52 Example 4 6 1 SOVM MOV AO Ox7FFE ADD AO 5 In this example we set the overflow mode OM 1 of STAT Adding 0x7 FFE with 5 causes an overflow OF 1 of STAT Since the expected result is a positive value the accumulator saturates to the largest representable value Ox7FFF If overflow mode was not set before the ADD instruction then the accumulator would overflow Therefore the result 0x8003 would be a negative value Example 4 6 2 SOVM OV STR 2 2 string length 2 OV APO 0 OV AO 0x1234 OV A0 0x1000 OV AO 0x7F00 A OV A0 0x1000 OV APO 0 point to beginning of string ADD AO A0 AO In this example saturation on a string value is illustrated A 2 word string is loaded into the STR register The accumulator string AO is loaded with 0x7F001234 and accumulator string AO is loaded with 0x10001000 When the two values are added together it causes an overflow The OF bit of the STAT is set to 1 the 16 bit MSBs of the string become Ox7FFF and the lower bits of the string become 0x2234 The final result is Ox7FFF2234 Note that if overflow mode was not set the result would have been 0x8F002234 Fractional Mode Mul
392. unsigned src byte to value stored in dest register and store result in the same dest register Example 4 14 2 1 ADDB A2 0x45 Add immediate 0x45 to A2 Example 4 14 2 2 ADDB R5 Oxf2 Add immediate Oxf2 to R5 Assembly Language Instructions 4 77 Individual Instruction Descriptions 4 14 3 ADDS Add String Syntax ADDS A J An adrs Table 4 46 Table 4 46 Table 4 46 t This instruction ignores the string count executing only once but maintains the CF and ZF status of the previous multi ply or shift operation as if the sequence was a single string This instruction should immediately follow one of the fol lowing class 1b instructions MOVAPH MULAPL MULSPL SHLTPL SHLSPL and SHLAPL An interrupt should not occur between one of these instructions and ADDS An interrupt may cause incorrect results Interrupts must be explicitly disabled at least one instruction before the class 1b instruction This special sequence is protected inside a BEGLOOP ENDLOOP construct In addition single stepping is not allowed for this instruction An in this instruc tion should be the same as Anin one of the listed class 1b instruction Offsets are allowed See Section 4 8 for more LN d p m detail Execution dest string src string src7 string PC PC W Flags Affected dest is An OF SF ZF CF are set accordingly src1 is adrs TAG is set accordingly Opcode amas 0 01010010 0 0110 El 205868 O O OD HD IA aie dma16 for direct
393. usse Glock oh wora w With RPT ok crass Moves TAn aars g Table 4 46 Table 4 46 MOVBS aars An Table 4 46 Table 4 46 Execution dest src PC PC L W Flags Affected destis An OF SF ZF CF are set accordingly dest is aars XSF XZF are set accordingly src is adrs TAG bit is set to bit 17th value Opcode Instructions Pio fas HI 13 12 11 10 o Js v e fs a a pa n ro MOVES Ar adis ST TSTST TTT es dma16 for direct or offset16 long relative see section 4 13 MOVES adii An opele ams dma16 for direct or offset16 long relative see section 4 13 Description Copy value of src byte to dest Syntax MOVBS An adrs Move data memory byte string to An word string MOVB adrs An Move An byte string to data memory See Also MOVU MOV MOVT MOVB MOVS Example 4 14 30 1 MOVBS A2 0x0200 Transfer the byte string at data memory location 0x0200 to accumulator string A2 Example 4 14 30 2 MOVBS 0x0200 A2 Transfer accumulator string A2 to data memory byte string location 0x0200 4 124 Individual Instruction Descriptions 4 14 33 MOVS Move String from Source to Destination Syntax Cep name ws sc Glock ok wora w win ner ci ass mos eris a aves ta wow read aves Tabie 46 ta mov rasta tan recae Tae sae o wow Jana omar mse 2 wa 2 mast Tana o 1 E LE ET mos anae 1 ome a wow fanna T
394. ut string and the length of the output string in the string multiply operations the result of multiplying a string by aninteger can be one word longer than the input string Unpredictable results may occur if parameter Igr is not at least equal to Igr 1 5 9 11 Constant Functions The only two constant functions implemented in C are x er const and xfer single cmm func xfer_const int out int constant in int lg lt transfers 1g 2 integers from program ROM starting at address constant in to RAM starting at address out Note that constant inis not doubled because it is used in AO in a MOV AO A0 operation The C compiler takes care of this cmm func xfer single int out int constant in transfers a single value An example of the use of x er const is int array 8 i const int atan 80 8 640 integers JUR ica E for 1 0 1 lt 80 1 xfer_const array amp atan i 8 STR_LENGTH 8 now use array normally XL Code Development Tools 5 47 Implementation Details 5 10 Implementation Details This section is C specific 5 10 1 Comparisons We use the CMP instruction for both signed and unsigned comparisons The two integers a and b to be compared are in AO and AO CMP AO0 AO0 AO contains a AO contains b AO A0 ACO AZ ANEG 5 0 1 0 0 5 1 1 0 0 0 5 0 0 1 1 5 0 0 1 0 0 1 1 0 5 5 1 1 0 FFFF 0 1 0 1 0 FFFF 0 0 0 FFFF FFFF 1 1 0 FFFF FFFE 1 0 0 FFFE F
395. values The left most column is the address Data memory is always addressable as bytes by MSP50C614 instructions Each value displayed in this window is actually two consecutive byte data Data memory values consist of the usual 16 bits plus a 17th bit called the tag bit If the tag bit is set the background is yellow otherwise it is white The tag bit can be changed by clicking the right mouse button on the data memory value to be changed The value is displayed in red if it has changed since the last time it was displayed To edit a memory value double click on the value to bring a small blinking cursor Keep the mouse pointer within this window and enter a new hex value Changes are only taken into account when the chip is not in run mode To add or remove a watch select the location by double clicking the data memory value and press W on the keyboard The selected location will be added if Watch window does not already contain this location or removed if Watch window contains this location from the Watch window Code Development Tools 5 17 Software Emulator Watch Window Watch window displays the data memory location and data to be watched It mirrors the value displayed in the RAM window The Watch window is provided as a help to display locations that may not be visible in the RAM window without scrolling See Ram Window above to know more about how to use Watch window Figure 5 18 CPU Window 5 18
396. w of TIMER2 INT1 and INT2 are the second and third highest priority interrupts in the C614 Refer to Section 2 7 Interrupt Logic for a summary of the interrupt logic and to Section 2 6 3 Interrupt Vectors for a listing of the interrupt vectors Both the period and the count down registers are readable and writeable as port addressed registers Timer Registers 16 bit wide location 15 14 13 12 11 05 04 03 02 01 00 PRD1 registert P P P P P P P P P P P address Ox3A TIMER1 Period TIM1 registert T T T T T T T T T T T address Ox3B TIMER1 Count Down Triggers INT1 on underflow PRD2 register P PP P P PP P P P P address 0x3E TIMER2 Period TIM2 register I T T T T T T T T T T address 0x3F TIMER2 Count Down Triggers INT2 on underflow P period register initial counter value T count down register counts from the value in P 0x0000 default state of both registers after RESET LOW t TIMER1 may be associated with the comparator function if the comparator enable bit is set Refer to Section 3 3 Comparator for details Reading from eitherthe PRD orthe TIM returns the current state of the register This can be used to monitor the progress of the TIM register at any time Writing to the PRD register does not change the TIM register until the TIM register has finished decrementing to 0x0000 The new value in the PRD register is then loaded to the TIM register and counting resumes from the new value p
397. w of the C614 functionality IMPORTANT a one bit comparator is not currently supported Typical connections to implement reset functionality are shown in Figure 1 3 1 5 C605 and C604 Preliminary Information Two related products the MSP50C605 C605 and MSP50C604 C604 use the C614 core The C605 has a 224K byte data ROM built into the chip and 32 I O port pins The C605 can provide up to 30 minutes of uninterrupted speech The C604 is designed to support slave operation with an external host microcontroller In this mode the C604 can be programmed with a code that communicates with the host via a command set This command set can be de signed to support LPC CELP MELP and ADPCM coders by selecting the ap propriate command The C604 can also be used stand alone in master mode The C604 and the C605 use the P614 as the development version device De tails on C605 and C604 processors are found in Appendix A and B Note MSP50C605 and MSP50C604 MSP50C605 and MSP50C604 are in the Product Preview stage of develop ment For more information contact your local TI sales office See Appen dices A and B for more information LL S M J C605 and C604 Preliminary Information Figure 1 1 Functional Block Diagram for the C614 S VDD
398. wannen er forss bm H H 3 e a Ex retar Co ICI CS jors Ame E me pm mum 22 CS CN CL CTO TES ICI 2 wm a ow rama IEC EO Eom P urs ene 9 T m9 EC mm edie ewe 0 o js mer me HH AECI ICI EC LC NN NN RE RECEN ER NN NN mas aai Sd te m A Ie mw A T we qum e mens T mw LS LOL S erus eared EO NN Assembly Language Instructions 4 201 Instruction Set Summary dest src src1 mod Clock c k Words w An adrs Table 4 46 With RPT clk Table 4 46 Ani Anl ng 3 m SLS S ST S adrs Table 4 46 Table 4 46 N R Table 4 46 I l An An adrs next A Table 4 46 la An An imm16 next A An An PH next A An An An next A An An An next A D 3 na 3 NR 3 NR 3 Z D Rx imm16 Rx R5 NR 3 Z m o O An imm8 w Zz JJ D o Rx imm8 An An adrs Table 4 46 ta An An pma16 N R An An An An An An An An PH N CG l wo Gl N lor m m m w oo XM pae om s m mm m sm m m sus sus sms sms mms sms sms D R9 vectors gt lt An adrs Table 4 46 Table 4 46 1b gt lt An An imm16 next A An An An next A TFn flagaars TFn cc Rx lt m pe wo i gt lt Com fe ons gt lt gt lt HE He X O 0 Ww An
399. way as RAM variables special purpose functions have to be used to utilize constants in a program The most general of these functions is xfer const which transfers values from the program ROM to the RAM Also constants MUST BE GLOBAL BEWARE OF The common C types float struct union and long are not implemented Note that long is a subset of string of integer The fact that all RAM allocations in the assembler are global has the following implications for C variables Only the file containing the main routine can contain global variable definitions Global variables referenced in other files must have been declared as ex ternal keyword extern at the beginning of the file Y A function referenced in a file but not defined in that same file must be introduced with a function prototype in the file where it is referenced no need for the extern keyword Code Development Tools 5 41 C Compiler 5 9 4 C Directives 5 9 4 1 define 5 9 4 2 undefine 5 42 C has a limited number of directives and some additional directives not found in ANSI C compilers The following directives are recognized by the compiler This directive is used to introduce 2 types of macros in typical C fashion Without Arguments defines a replacement string for a given string Example define PI 3 1415926535 Every occurrence of the token PI will henceforth be replaced with the string 3 1415926535 If there is no rep
400. ws Step This menu option key equivalent F7 allows the user to execute one instruction in the program window Note that the program window does not need to have the focus to execute a Step instruction If the step instruction leads into a gray area i e a program line or group of program lines that cannot be stepped into the system will automatically execute instructions until it gets out of the gray area Software Emulator Step Over This menu option key equivalent F8 allows the user to step over a call instruction in the program window Note that the program window does not need to have the focus to execute a Step instruction If the Step Over instruction leads into a gray area i e a program line or group of program lines that cannot be stepped into the system automatically execute the instructions until it gets out of the gray area Stepping over a line that does not contain a call or macro call is equivalent to a single step instruction Figure 5 24 Debug Menu Code Development Tools 5 23 Software Emulator 5 24 Fast Run This menu option key equivalent CTRL F9 allows the user to execute a portion of the program window until a breakpoint is encountered The windows are not refreshed until the program stops so that the execution speed is maximized If no breakpoint is encountered the user can stop the program by hitting the STOP option CTRL F10 inthe debug menu Since the emulator typically
401. x0000 Internal Test Code 2048 x 17 bit reserved 0x07FF 0x0800 User ROM 30704 x 17 bit C605 read only P614 EPROM Ox7F00 Macro Call Vectors 255 x 17 bit overlaps interrupt vectqr locations bene Usable Interrupt Vectors Ox7FF7 8 x 17 bit Ox7FF8 Unusable Interrupt Vectors reserved RESET vector Ox7FFE Ox7FFF Data Memory Architecture Peripheral Ports RAM 008 640 x 17 bit Ox 10 Data ROM Ox 18 0x 00000 BEN DATA ROM PE daa slow goe 229 376 x 8 bit Ox 28 0x 38000 MSP50C605 Preliminary Data gt 5 Architecture Figure A 3 MSP50C605 100 Pin PJM Package 80 51 MSP50C605 100 PIN PJM PLASTIC PACKAGE A 6 Architecture Table A 1 MSP50C605 100 Pin PJM Plastic Package Pinout Description Description Pin Description Pin Description Pin Description Pin NC 1 NC NC 76 NC 2 NC NC 77 NC 3 NC NC 78 NC 4 NC NC 79 DACM 5 NC NG 80 VCC3 6 VCC NC 81 DACP 7 VCCI PC7 82 VCC 8 SCAN_OUT PC6 83 PF7 9 TEST PC5 84 PF6 10 SYNC PC4 85 PES 11 SCNCLK PC3 86 PF4 12 SCANIN PC2 87 PF3 13 INITZ PC1 88 PF2 14 PE7 PCO 89 PFI 15 PE6 GND 90 PFO 16 PES VCC2 91 GND 17 PE4 PD7 92 NC 18 PES PD6 93 NC 19 PE2 PD5 94 NC 20 PE PD4 95 NC 21 PEO PD3 96 NC 22 PLL PD2 97 NC 23 X1 PD1 98 NC 24 X2 PDO 99 NC 25 GND3 100 MSP50C605 Preliminary Data A 7 A 8 Appendix B MSP50C604 Preliminary Data This Appendix contains preliminary data for the MSP
402. x2F to bit 9 of the ClkSpdCtrl regis ter and bits 5 through 1 to bits 15 through 11 of ClkSpdCtrl register a eo e This software controlled trim for the RTO is not a replacement for the external reference resistor mounted at pins OSC y and OSCoyt Also note that this adjustment has no effect on the rate of the CRO reference oscillator 2 10 Execution Timing For executing program code the C614 s core processor has a three level pipeline The pipeline consists of instruction fetch instruction decode and instruction execution A single instruction cycle is limited to one program Fetch plus one data memory read or write The master clock consists of two phases with non overlap protection A fully static implementation eliminates pre charge time on busses or in memory blocks This design also results in a very low power dissipation Figure 2 9 illustrates the basic timing relationship between the master clock and the execution pipeline MSP50C614 Architecture 2 33 Reduced Power Modes Figure 2 10 Instruction Execution and Timing DATA ADD 2 11 Reduced Power Modes 2 34 The power consumption of the C614 is greatest when the DAC circuitry is called into operation i e when the synthesizer speaks There are however a number of reduced power modes sleep states on the C614 which may be engaged during quiet intervals The performance and flexibility of the reduced power modes make the C614 ideal f
403. xecution defaults to a NOP A Ccc instruction cannot be followed by a return RET instruction No restriction applies if IRET is used instead of RET Syntax Alternate Syntax Description CA pma16 CNBE pma16 Conditional call on above unsigned t CNA pma16 CBE pma16 Conditional call on not above unsigned t CB pma16 Conditional call on below unsigned CNB pma16 Conditional call on not below unsigned CC pma16 Conditional call on CF 1 CNC pma16 Conditional call on CF 0 CE pma16 Conditional call on equal CNE pma16 Conditional call on not equal CG pma16 CNLE pma16 Conditional call on greater signed CNG pma16 CLE pma16 Conditional call on not greater signed t CIN1 pma16 Conditional call on IN1 1 CNIN1 pma16 Conditional call on IN1 0 CIN2 pma16 Conditional call on IN2 1 CNIN2 pma16 Conditional call on IN2 0 CL pma16 CNGE pma16 Conditional call on less signed CNL pma16 CGE pma16 Conditional call on not less signed CO pma16 Conditional call on OF 1 CNO pma16 Conditional call on OF 0 CS pma16 Conditional call on SF 1 CNS pma16 Conditional call on SF 0 CTAG pma16 Conditional call on TAG 1 CNTAG pma16 Conditional call on TAG 0 CTF1 pma16 Conditional call on TF1 1 CNTF1 pma16 Conditional call on TF1 0 CTF2 pma16 Conditional call on TF2 1 CNTF2 pma16 Conditional call on TF2 0 CZ pma16 Conditional call on ZF 1 CNZ pma16 Conditional call on ZF 0 CRA pma16 CRNBE pma16 Conditional call on Rx
404. xternal variables in C declare them as extern Note that only the file containing the main routine can contain global variable declarations If cmm6xx asmis included in a project file the resulting linked file will have a start vector address address Ox7FFF of _main1 corresponding to a line in cmm6xx asm that forces ajumpto_main0 The C compiler au tomatically defines a_main0 label just prior to forcing a call to main if there is a C file containing the main routine If not it is up to the user to define a _maino0 label in one of the assembly language routines this will be the starting point of the program Assembler 5 7 Assembler The MSP50P614 MSP50C614 assembler is implemented as a Windows DLL Dynamic Linked Library 5 7 1 Assembler DLL The current name of the DLL file is asm6xx d11 It can be invoked from any Windows program provided that the user included the file called sm6xx 1ib in the Windows project The syntax of the call is extern int FAR PASCAL ASM MAIN LPSTR source file short warn short err passl struct error struct LPSTR include list mE short i w passl error LPSTR source file struct error struct short pass pass where error was detected short type type of error error warning short error msg error message number short file number file number in object file table long line number line number in file where error occurred
405. y is stopped in sleep by virtue of the idle state control The disadvantage of the asynchronous response however is that it can render irregularities in the timing of response to these same inputs 7 1 Note Idle State Clock Control Bit If the idle state clock control bit is set and the ARM bit is clear the only event that can wake the C614 after an IDLE instruction is a hardware RESET low to high When at sleep the device will not respond to the input ports nor to the internal timers LL 4 os Reduced Power Modes Table 2 3 Programmable Bits Needed to Control Reduced Power Modes deeper sleep relatively less power Label for Gone BH Control Bit Idle state clock control bit 10 ClkSpdCtrl register OX3D Enable reference oscillator bit 09 CRO or bit 08 RTO ClkSpdCtrl register OX3D ARM bit 14 IntGenCtrl register 0x38 Enable PDM pulsing bit 02 DAC Control register 0x34 IDLE instruction executes the mode PLL multiplier bits 07 through 00 Programmed value is 0 255 ClkSpdCtrl register OX3D MSP50C614 Architecture 2 37 Reduced Power Modes Table 2 4 Status of Circuitry When in Reduced Power Modes Refer to Table 2 3 Component deeper sleep relatively less power Determined by Controls LIGHT DEEP ie clock PLL PLL clock circuitry MR PLL clock circuitry AE Master clock MC status C614 periphery MC rate 2 38 EEDEN PDM

Texas Instruments MSP50C614 User's Manual

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