Texas Instruments DAC8555EVM User's Manual
Contents
1. Supplies power Vss to the negative rail of op amp U2 for bipolar mode or ties it to AGND for unipolar mode Capacitive load drive output of DAC is routed to pin 2 of JMP6 and may be used as the output terminal JMP10 2 3 1 2 JMP6 Open Open Optional Signal Conditioning Op Amp U4B One half of the OPA2132 dual package op amp U4 is used for reference buffering U4A while the other half is unused This unused op amp U4B is left for whatever op amp circuit application the user desires to implement The 1206 footprint for the resistors and capacitors surrounding the U4B op amp are not populated and are made available for easy configuration Test points TP5 and TP6 are not installed so it is up to the user on how to connect the input signals to this op amp No test point has been made available for the output because of space restrictions but a wire can be soldered to the output of the op amp via an unused component pad that connects to it The op amp circuit can be configured by populating the corresponding components to those that match the circuit design while leaving all other unused component footprints unpopulated Jumper Settings Table 7 shows the function of each specific jumper setting of the EVM Table 7 Jumper Settings and Functions Reference Jumper Setting Function ENABLE pin is set high through pull up resistor R1 ENABLE can be driven by GPIO2 ee J2 8 JMP1 32. TP4 BH INT SCL cs ssr gt H TOUT DGND AGKD BST 19 gps spa L 20 lt DAUGHTER SERIAL 1 J2A TOP SAM TSM 110 01 L DV P J2B BOTTOM SAM SSW 110 22 F D VS K U4B 43 3VD 1 8VD 5VA VCC VSS 5VA 3 3VA VDD Jis waka WS OTS ek Doe astra te d l i i i i OPA2227UA j p n oH TEXAS C i 4 VA VA Z I l I l m 4 S A sva 4 es i33 INSTRUMENTS z DGND AGND S l l g 48VD vt 10 I2d d d l Il2d d d 9 DATA ACQUISITION PRODUCTS 43 3VD 5VD HIGH PERFORMANCE ANALOG DIVISION SEMICONDUCTOR GROUP DAUGHTER POWER vss voc VDD 4BVA 6730 SOUTH TUCSON BLVD TUCSON AZ 85706 USA VCC 15V Analog TITLE VDD 42 7V to 5 0V Digital ENGINEER J PARGUIAN DAC8555EVM J3A TOP SAM_TSM 105 01 L DV P VSS OV to 15V Anak zb J8B BOTTOM SAM SSW 105 22 F D VS K 5 S DRAWN EY ATE BENJAMIN DOCUMENT CONTROL NO6486604 sIZE B DATE 11 Oct 2006 REV A SHEET 10F 1 FILE CAUSERDATA Projects DAC8555 DAC8555EVM ddb FCC Warning This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general customer use It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment
3. eese 8 5 DAC8555EVM PCB Layer 3 Power Plane cesses 8 6 DAC8555EVM PCB Layer 4 Bottom Signal Layer eee 9 7 DAC8555EVM PCB Bottom Silkscreen Image eeeeeeeeeeeeeeeene 9 8 DACS8555EVM Drill Drawifig ens te step rene enun reor pr omb ne mam exe tw aces 10 9 INL and DNL Characterization Graph of DAC A c sees 11 10 INL and DNL Characterization Graph of DAC B cessere 12 11 INL and DNL Characterization Graph of DAC C cesses 13 12 INL and DNL Characterization Graph of DAC D eese 14 List of Tables 1 DAG8555EVMIPatts L St eaen rrr rnt n ne nu neu rtr Emp Sae a at x man E EEU KE RR Re cee 15 2 Factory Default Jumper Settings 2a x n Renee Ro RE Ee eR ER ARR RE EREOEXUNRDUE 16 3 DAC Output Channel Mapping ceceeeeeeeeee ence eee eee ee ee III Imre 17 4 Unity Gain Output Jumper Settings saine recen mox rex Rex Rx HaRR eR REX ERE 18 5 Output Gain of 2 Jumper Settings ecceeeeeeeeee eee cece ee ence eee eeeeeeeeeeeeeeeeeeeeeeees 18 6 Capacitive Load Drive Output Jumper Settings cessere 19 7 Jumper Settings and Functions cccceeee cess cence eee eee eeeeeeeeeeeeeeeeeeeeeeeeeeenaee 19 2 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Overview 1 Overview 1 1 1 2 1 2 1 1 2 2 This sectio
4. DAC Max DNL 0 78 7340 LSB DAC Min DNL 0 60 Code 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 amp 0000 65535 48745 Code Figure 12 INL and DNL Characterization Graph of DAC D 14 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback WB TEXAS INSTRUMENTS www ti com 2 3 Bill of Materials The parts list showing the components used in the assembly of the DAC8555EVM is given in Table 1 PCB Design and Performance Table 1 DAC8555EVM Parts List QTY PER MFR ITEM BOARD Ref Des MFR PART NUMBER DESCRIPTION 1 4 R11 R14 Panasonic ERJ 3GEYOROOV Chip Resistor 0O 1 10W 0603 2 1 R24 Panasonic ERJ 8GEYJ101V Chip Resistor 1002 1 4W 1206 Tom 2 R5 R6 Panasonic ERJ 3GEYJ302V Chip Resistor 3kQ 1 10W 0603 3 7 ng R P panasonic ERJ 3EKF1002V Chip Resistor 10k 1 16W 0603 4 1 R16 Panasonic ERJ 3EKF2002V Chip Resistor 20kQ 1 16W 0603 5 1 R10 Bourns 3214W 1 203E Series 5T Pot 20kQ BOURNS 32X4W 6 1 R15 Bourns 3214W 1 104E Series 5T Pot 100kQ BOURNS 32X4W Not a Installed 7 R17 R23 Panasonic Chip Resistor 1 4W 1206 7 1 C12 TDK C1608C0G1H102J Multilayer Ceramic Capacitor 1nF 0603 COG 8 4 C4 C7 TDK C1608X7R1E104K Multilayer Ceramic Capacitor 0 1uF 0603 X7R 9 2 C10 C11 TDK C2012X7R1E105K Multilayer Ceramic Capacitor 1uF 0805 X7R 10 3 C1 C2 C3 TDK C32
5. ENABLE pin is set low and DAC is enabled LDAC pin is set high through pull up resistor R2 LDAC can be driven by GPIOO J2 2 JMP2 Cc LDAC pin is set low and DAC update is accomplished via software RSTSEL pin is set high through pull up resistor R3 RSTSEL can be driven by GPIO4 ee J2 14 JMP3 Cc RSTSEL pin is set low 1 Indicates the corresponding pins that are shorted or closed SLAU204 December 2006 DAC8555EVM User s Guide 19 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com EVM Operation Table 7 Jumper Settings and Functions continued Reference Jumper Setting Function eo RST pin is set high through pull up resistor R4 RST can be driven by GPIOS J2 19 JMP4 a0 RST pin is set low ee Disconnects VggrH to the inverting input of the op amp U2 JMP5 Ce Connects VperH to the inverting input of the op amp U2 ee Disconnects the inverting input of the op amp U2 from the gain resistor R9 JMP6 fo Connects the inverting input of the op amp U2 from the gain resistor R9 for output gain of 2 sae 5V analog supply is selected for AVpp o JMP7 1 3 3 3V analog supply is selected for AVpp e s 9 1 3 Routes the adjustable buffered onboard 5V reference to the VngeH input of the cele DAC8555 JMP8 1 3 Routes the user supplied reference f
6. INSTRUMENTS www ti com PCB Design and Performance DACBOffse V DAC B Slope pV LSB Eng Points TestCode DAC B Output V 0 004618 76 3080 64714 342817 DAC B Max INL 3 47 Code 53436 DAC B Min INL 1 88 Code 13142 10000 15000 20000 25000 30000 35000 Code DAC B Max DNL 0 64 Code 19820 DAC B Min DNL 0 56 Code 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65535 8426 Code Figure 10 INL and DNL Characterization Graph of DAC B 12 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com PCB Design and Performance DAC Offset DACSlope uV LSB EndPoints TestCode DAC Output MJ 0 001671 76 3049 64714 4 936315 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65535 Code Figure 11 INL and DNL Characterization Graph of DAC C DAC Max INL 3 99 Code 23167 DAC Min INL 1 30 Code 42317 DAC Max DNL 0 40 Code 52218 DAC Min DNL 0 39 Code 15180 SLAU204 December 2006 DAC8555EVM User s Guide 13 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com PCB Design and Performance DAC Offset V DAC Slope uV LSB End Points TestCode DAC Output V 0 002310 76 3050 64714 4 940308 DAC Max INL 2 98 Code 56818 DAC Min INL 2 17 18447 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65535 Code aj
7. the analog and digital signals from each other In the layout process carefully consider the placement of the power and ground planes A solid plane is ideal but because of its greater cost a split plane can sometimes be used satisfactorily When considering a split plane design analyze the component placement and carefully split the board into its analog and digital sections starting from the DUT The ground plane plays an important role in controlling the noise and other effects that otherwise contribute to the error of the DAC output To ensure that the return currents are handled properly route the appropriate signals only in their respective sections meaning that the analog traces should only lay directly above or below the analog section and the digital traces in the digital section Minimize trace length but use the largest possible trace width allowable within the design These design practices are illustrated in Figure 2 through Figure 8 The DAC8555EVM board is constructed on a four layer PCB using a copper clad FR 4 laminate material The PCB has a dimension of 43 1800mm 1 7000in by 82 5500mm 3 2500in and the board thickness is 1 5748mm 0 062in Figure 3 through Figure 7 show the individual artwork layers Note Board layouts are not to scale These are intended to show how the board is laid out they are not intended to be used for manufacturing DAC8555EVM PCBs 6 DAC8555EVM User s Guide SLAU204 December 2006 Submit Doc
8. conductor width is 10 mils Minimum conductor spacing is 6 mils Number of finished layers 4 Board dimensions 3250 mils x 1700 mils 1 63mil 1 6002mm PTH 6 47 244mil 1 2mm PTH 5 40mil 1 016mm PTH 42 39 37mil Imm PTH 43 23 622mil 0 6mm PTH 50 15mil 0 381mm PTH 147 Total Figure 8 DAC8555EVM Drill Drawing EVM Performance The EVM performance test is executed using a high density DAC bench test board an Agilent 3458A digital multimeter and a PC running LabVIEW software The EVM board is tested for linearity for all codes between 485 and 64741 The DUT is then allowed to settle for 1ms before the meter is read This process is repeated for all codes to generate the measurements for INL and DNL Results of the DAC8555EVM tests are shown in Figure 9 through Figure 12 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback 4i TEXAS INSTRUMENTS www ti com PCB Design and Performance DACA Offset DACA Slope uV LSB End Points TestCode DACA Output V 0 002599 76 3103 64714 4 940945 DACA INL 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65535 Code Figure 9 INL and DNL Characterization Graph of DAC A DAC A Max INL 2 30 Code 5237 DAC Min INL 2 07 Code 43894 DAC A Max DNL 0 43 Code 33627 DAC Min DNL 0 55 Code 49494 SLAU204 December 2006 DAC8555EVM User s Guide 11 Submit Documentation Feedback 4i TEXAS
9. open Open Open vical is disconnected from the inverting input of the output op amp U2 JMP6 must be JMP10 2 3 4 2 Supplies power Vas to the negative rail of op amp U2 for bipolar mode or ties it to AGND for unipolar mode Close Close Configures op amp U2 for a gain of 2 output without a voltage offset JMP5 must be JMP6 spem Open Open ors input of op amp U2 is disconnected from the gain resistor R9 JMP5 must be 18 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com 3 4 3 3 5 3 6 EVM Operation Capacitive Load Drive It may be required to drive a wide range of capacitive loads However under certain conditions all op amps may become unstable depending on the op amp configuration gain and load value These factors are just few of the issues that can affect op amp stability and should be considered during implementation In unity gain configuration the OPA627 op amp U2 performs very well with very large capacitive loads Increasing the gain enhances amplifier ability to drive even more capacitance and adding a load resistor even improves the capacitive load drive capability Table 6 shows the jumper setting configuration for a capacitive load drive Table 6 Capacitive Load Drive Output Jumper Settings Jumper Setting Reference Unipolar Bipolar Function JMP5 Open Open VngrH is disconnected from the inverting input of the output op amp U2
10. or combination in which such TI products or services might be or are used EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 15 75V to 15 75V and the output voltage range of 15V to 15V Exceeding the specified input range may cause unexpected operation and or irreversible damage to the EVM If there are questions concerning the input range please contact a TI field representative prior to connecting the input power Applying loads outside of the specified output range may result in unintended operation and or possible permanent damage to the EVM Please consult the EVM User s Guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is designed to operate properly with certain components above 60 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transistors and current sense resistors These types of devices can be identified using the EVM schematic located in the EVM User s Guide When placing measurement probes near these devices during operation please be aware that these devices may be very warm to the touch Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Cop
11. 16X7R1C106M Multilayer Ceramic Capacitor 104F 1206 X7R Not i Installed 2 C8 C9 DK Multilayer Ceramic Capacitor 1206 x 16 bit Quad Voltage Output Serial Input DAC 11 1 U1 exas Instruments DAC8555IPW TSSOP 16 12 1 U2 Texas Instruments OPA627AU 8 SOP D Precision Op Amp 13 1 U3 Texas Instruments REF02AU 5V 8 SOP D Precision Voltage Reference 14 1 U4 Texas Instruments OPA2132UA 8 SOP D Dual Precision Op Amp ined 2 J1 J5 On Shore Technology ED555 3DS 3 Pin Terminal Connector 15 2 J2A J4A Samtec TSM 110 01 L DV P SMT Header 10x2x0 1 20 pin 025in2 16 1 J3A Samtec TSM 105 01 L DV P SMT Header 5x2x0 1 10 pin 025in2 17 2 J2B J4B Samtec SSW 110 22 F D VS K SMT Socket 10x2x0 1 20 pin 025in 18 1 J3B Samtec SSW 105 22 F D VS K SMT Socket 5x2x0 1 10 pin 025in 19 6 JMP1 JMP6 Samtec TSW 102 07 G S 2 position Jumper 1in spacing 20 10 JMP7 JMP16 Samtec TSW 103 07 G S 3 position Jumper 1in spacing 21 1 TP4 Keystone Electronics 5011 Testpoint Large Loop Not TP1 TP2 TP3 xu Installed 5 TP5 TP6 Keystone Electronics 5000 Testpoint Mini Loop 22 16 N A Samtec SNT 100 BK G H Shorting Block SLAU204 December 2006 Submit Documentation Feedback DAC8555EVM User s Guide 15 3 TEXAS INSTRUMENTS www ti com EVM Operation 3 3 1 3 2 3 3 EVM Operation This section covers the operation of the EVM in detail in order to provide guidance to the user in evaluating the onboard DAC as well as how to i
12. 5 6k adapter interface card or the HPA449 platform please contact your Texas Instruments representative visit the Tl web site or email the Data Converter Applications Support Team at dataconvapps list ti com The DAC outputs can be monitored through the selected pins of the J4 header connector All outputs can be switched through their respective jumpers JMP11 JMP12 JMP13 and JMP14 for the purpose of stacking Stacking allows a total of eight DAC channels to be used provided the SYNC signals are unique for each EVM board stacked In addition the option of selecting one DAC output that can be fed to the noninverting side of the output op amp U2 is also possible by using a jumper across the selected pins of J4 The output op amp U2 must first be correctly configured for the desired waveform characteristic For more information refer to Section 3 of this user s guide A block diagram of the EVM is shown in Figure 1 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com Overview External Reference DAC Module O SCLK RST RSTSEL Vpgel DAC Out O TP3 eee JMP9 JMP10 um Vss Figure 1 DAC8555EVM Functional Block Diagram SLAU204 December 2006 DAC8555EVM User s Guide 5 Submit Documentation Feedback P TEXAS INSTRUME
13. FO2 precision reference is powered by Voc 4 15V through either terminal J1 3 or J3 1 SLAU204 December 2006 DAC8555EVM User s Guide 3 Submit Documentation Feedback B TEXAS INSTRUMENTS www ti com Overview CAUTION When applying an external voltage reference through TP2 or J4 20 make sure that it does not exceed 5V maximum External voltage references in excess of 5V can permanently damage the DAC8555 being tested U1 1 3 EVM Basic Functions 4 The DAC8555EVM is designed to provide a demonstration platform for testing certain operational characteristics of the DAC8555 digital to analog converter Functional evaluation of the DAC8555 can be accomplished with the use of any microprocessor TI DSP or some sort of waveform generator Headers J2A top side and J2B bottom side are pass through connectors provided to interface a host processor or waveform generator with the DAC8555EVM using a custom built cable These connectors enable the control signals and data to pass between the host and the device A mating adapter interface card 5 6k adapter interface is also available to fit with Tl s TMS320C5000 and TMS320C6000 DSP Starter Kits DSKs This card resolves most of the trouble involved with building a custom cable Additionally there is also an MSP430 based platform HPA449 that uses the MSP430F449 microprocessor to which this EVM can connect and interface as well For more details or information regarding the
14. NTS www ti com PCB Design and Performance 1 3 1 Related Documentation from Texas Instruments The following documents provide information regarding Texas Instrument integrated circuits used in the assembly of the DAC8555EVM The latest revisions of these documents are available from the TI web site at http www ti com Data Sheet Literature Number DAC8555 SLAS475 REF02 SBVS003 OPA627 SBOS165 OPA2132 SBOS054 2 PCB Design and Performance This section discusses the layout design of the DAC8555EVM PCB describing the physical and mechanical characteristics of the EVM as well as a brief description of the demonstration board test performance procedures performed The list of components used in this evaluation module is also included 2 1 PCB Layout The DAC8555EVM is designed to preserve the performance quality of the DAC8555 the device under test DUT as specified in the data sheet In order to take full advantage of the EVM capabilities use care during the schematic design phase to properly select the right components and to build the circuit correctly The circuit design should include adequate bypassing identifying and managing the analog and digital signals and understanding the components electrical and mechanical attributes The primary design concerns during the layout process are optimal component placement and proper signal routing Place the bypass capacitors as close as possible to the device pins and properly separate
15. Output Channel Mapping Reference Jumper Position Function JMP14 1 2 DAC output A VoytA is routed to J4 2 2 3 DAC output A Vou7A is routed to J4 10 JMP12 1 2 DAC output B Vou1B is routed to J4 4 2 3 DAC output B Vou7B is routed to J4 12 IPAS 1 2 DAC output C Voy7C is routed to J4 6 2 3 DAC output C Vou1C is routed to J4 14 JMP14 1 2 DAC output D Voy7D is routed to J4 8 2 3 DAC output D Voy7D is routed to J4 16 In order to allow exclusive control of each EVM different SYNC signals must be selected for each DAC8555 This difference is not easily accomplished as it involves hardware alterations The EVM board that sits on the bottom of the stack can use the SYNC signal coming from J2B 7 The pin of J2A 7 can be cut so that the SYNC signal coming from the bottom EVM board in the stack does not pass through The EVM board that sits on top can use the CNTL signal coming from J2 1 The signal of J2 1 must be jumpered across to J2 7 of the EVM board that sits on the top of the stack The LDAC SYNC and ENABLE control signals are shared The DAC8555 only responds when the correct SYNC signal is generated The raw outputs of the DAC can be probed through the even numbered pins of J4 the output terminal which also provides mechanical stability when stacking or plugging into any interface card In addition it provides easy access for monitoring up to eight DAC channels when stack
16. WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies TI from all claims arising from the handling or use of the goods Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Please read the User s Guide and specifically the Warnings and Restrictions notice in the User s Guide prior to handling the product This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process
17. ain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Telephony www ti com telephony Low Power www ti com lpw Video amp Imaging www ti com video Wireless Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2007 Texas Instruments Incorporated
18. her supply power while the I O and digital section are powered by 5V Vpp The Vcc supply source is primarily used to provide the positive rail of the external output op amp U2 the reference chip U3 and the reference buffer U4 The negative rail of the output op amp U2 can be selected between Vss and AGND via jumper JMP10 The external op amp is installed as an option to provide output signal conditioning or to boost capacitive load drive or for other desired output mode requirements CAUTION To avoid potential damage to the EVM board be sure that the correct cables are connected to their respective terminals as labeled on the EVM board Stresses above the maximum listed voltage ratings may cause permanent damage to the device Reference Voltage The 5V precision voltage reference is provided to supply the external voltage reference for the DAC through the REFO2 U3 via jumper JMP8 by shorting pins 1 and 2 The reference voltage goes through an adjustable 100kQ potentiometer R15 in series with 20kQ R16 to allow the user to adjust the reference voltage to its desired settings The voltage reference is then buffered through U4A as seen by the device under test The test points TP2 TP3 and TP4 are also provided as well as J4 18 and J4 20 in order to allow the user to connect another external reference source if the onboard reference circuit is not desired The external voltage reference should not exceed 5V DC The RE
19. in other environments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference EVALUATION BOARD KIT IMPORTANT NOTICE Texas Instruments TI provides the enclosed product s under the following conditions This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use Persons handling the product s must have electronics training and observe good engineering practice standards As such the goods being provided are not intended to be complete in terms of required design marketing and or manufacturing related protective considerations including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards This evaluation board kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility restricted substances RoHS recycling WEEE FCC CE or UL and therefore may not meet the technical requirements of these directives or other related directives Should this evaluation board kit not meet the specifications indicated in the User s Guide the board kit may be returned within 30 days from the date of delivery for a full refund THE FOREGOING WARRANTY IS THE EXCLUSIVE
20. ing two EVMs together 3 4 Output Op Amp The DAC8555EVM includes an optional signal conditioning circuit for the DAC output through an external operational amplifier U2 The output op amp is set to unity gain configuration by default Only one DAC output channel can be monitored at any given time JMP15 selects which pin of J4 is the input Either J4 1 or J4 3 can be used as the op amp signal input The default setting for JMP15 selects J4 1 A shorting jumper can be placed between one of the DAC outputs and the op amp input For example a jumper across J4 1 and J4 2 places the DAC A output as the input for the op amp if board jumpers are in the default position If JMP15 is in the alternate position then a shorting block between J4 3 and J4 2 makes the DAC B output the input to the op amp The output of U2 passes through JMP16 In the default position the output connects to J4 5 When JMP16 is in the alternate position the output from U2 connects to J4 7 The output can be monitored from or passed to another device from the J4 connector The jumper arrangement of JMP15 and JMP16 connecting to J4 allows U2 to be used in the stacked board arrangement discussed above in Section 3 3 The following subsections describe the different configurations of the output amplifier U2 SLAU204 December 2006 Submit Documentation Feedback DAC8555EVM User s Guide 17 EVM Operation 3 4 1 Unity Gain Output Wy TEXAS INSTRUMENTS www ti co
21. j i TEXAS User s Guide INSTRUMENTS SLAU204 December 2006 DAC8555EVM User s Guide This user s guide describes the characteristics operation and use of the DAC8555 Evaluation Module EVM It covers all matters related to proper use and configuration of this EVM along with the devices that it supports The physical printed circuit board PCB layout schematic diagram and circuit descriptions are also included For a more detailed description of the DAC8555 see the product data sheet available from the Texas Instruments web site at http www ti com Additional support documents are listed in the section of this guide entitled Related Documentation from Texas Instruments Throughout this document the acronym EVM and the phrases evaluation module and demonstration board are synonymous with the DAC8555EVM TMS320C5000 TMS320C6000 are trademarks of Texas Instruments LabVIEW is a trademark of National Instruments SLAU204 December 2006 DAC8555EVM User s Guide 1 Submit Documentation Feedback i TEXAS INSTRUMENTS www ti com Contents 1 lm 3 2 PCB Design and Performance csseseeseeseeesee eene 6 3 2 Rerum EE 16 4 fee I 22 List of Figures 1 DAC8555EVM Functional Block Diagram eeseeeernnnm HH 5 2 DAC8555EVM PCB Top Silkscreen Image eene 7 3 DAC8555EVM PCB Layer 1 Top Signal Layer eeeeeeeeene 7 4 DAC8555EVM PCB Layer 2 Ground Plane
22. m The buffered output configuration can be used to prevent loading of the DAC8555 though it may add some slight distortion because of the feedback resistor and capacitor The feedback circuit can be altered by simply desoldering R8 and C12 and replacing them with components of desired value If desired R8 and C12 can be removed altogether by replacing R8 with a 0Q resistor Table 4 shows the jumper setting for the unity gain configuration of the DAC external output buffer in unipolar or bipolar mode Table 4 Unity Gain Output Jumper Settings Jumper Setting Reference Unipolar Bipolar Function JMP5 Open Open Disconnect VngeH from the inverting input of the op amp JMP10 2 3 1 2 Supplies Vas to the negative rail of the op amp or ties it to AGND JMP6 Open Open Disconnect negative input of op amp from the gain resistor R9 3 4 2 Output Gain of 2 There are two types of configurations that will yield an output gain of 2 depending on the setup of jumpers JMP5 and JMP6 These configurations allow the user to choose whether the DAC output will use VageH as an offset Table 5 shows the proper jumper settings of the EVM for the DAC8555 output gain of 2 Table 5 Output Gain of 2 Jumper Settings Jumper Setting Reference Unipolar Bipolar Function Close Close Inverting input of the output op amp U2 is connected to VrEFH for use as its offset JMP5 voltage with a gain of 2 JMP6 must be
23. machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice Tl is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expe
24. n gives a general overview of the DAC8555EVM and describes some of the factors that must be considered when using this demonstration board Features The DAC8555EVM is a simple evaluation module designed for a quick and easy way to evaluate the functionality and performance of the high resolution quad channel serial input DAC8555 digital to analog converter DAC This EVM features a serial interface to communicate with any host microprocessor or TI DSP based system Power Requirements This subsection describes the power requirements for this device Supply Voltage The DC power supply requirement for the digital section Vpp of this EVM is typically 5V connected to the J5 1 terminal or via the J3 10 terminal when plugged in with another EVM board or interface card and is referenced to ground through the J5 2 and J3 5 terminals The DC power supply requirements for the analog section of this EVM are Vcc and Vss range from 15 75V to 15 75V maximum connecting through J1 3 and J1 1 respectively or through terminals J3 1 and J3 2 The 5V connects through terminals J5 3 or J3 3 and the 3 3V connects through terminal J3 8 All of the analog power supplies are referenced to analog ground through terminals J1 2 and J3 6 The analog power supply for the device under test U1 can be powered by either 5V4 or 3 3V by selecting the proper position of jumper JMP7 This configuration allows the DAC8555 analog section to operate from eit
25. nterface the EVM to a specific host processor Refer to the DAC8555 datasheet for information about its serial interface and other related topics The EVM board is factory tested and configured Default Settings The EVM is set to its factory default configuration as described in Table 2 to operate in 5V mode Table 2 Factory Default Jumper Settings Reference Jumper Position Function JMP1 CLOSE ENABLE pin is tied to DGND JMP2 CLOSE LDAC pin is tied to DGND Software LDAC is used JMP3 CLOSE RSTSEL pin is tied to DGND JMP4 OPEN RST pin is tied to Vpp JMP5 OPEN n not routed to the inverting input of the op amp for voltage offset with gain of 2 JMP6 OPEN Output op amp U2 is not configured for a gain of 2 JMP7 1 2 Analog supply for the DAC8555 is 5V4 JPM8 1 2 Onboard external buffered reference U3 is routed to VggeH JMP9 1 2 VperL is tied to AGND JMP10 1 2 Negative supply rail of U2 op amp is supplied with Vss JMP11 1 2 DAC output A VoytA is routed to J4 2 JMP12 1 2 DAC output B Vou1B is routed to J4 4 JMP13 1 2 DAC output C Vou1C is routed to J4 6 JMP14 1 2 DAC output D Vou1D is routed to J4 8 JMP15 1 2 J4 1 is connected to the noninverting input of the output op amp U2 JMP16 1 2 J4 5 is connected to the output of the op amp U2 Host Processor Interface The host processor drives the DAC Thus proper DAC operation depends on a successful configuration between
26. r e Figure 7 DAC8555EVM PCB Boittom Silkscreen Image SLAU204 December 2006 DAC8555EVM User s Guide 9 Submit Documentation Feedback PCB Design and Performance e Texas Instruments Inc 12500 TI Boulevard Dallas TX 75243 DAC8555 EVM DOCUMENT CONTROL 6486603 Mechanical Layer 1 27 Nov 2006 e e T E S o 2 Dy ooo T 8 a I I 202 n ve x x Kio vvv E M e 2 2 10 DACBSSS RIVA LAYER 1247 5 tmj 9 1247 5 mn 1 3250 m1 Wy TEXAS INSTRUMENTS www ti com Notes 1 2 B 9 09ou 11 12 13 14 o v x PWB to be manufactured RoHS compliant and marked as per IPC 1066 PWB to be fabricated to meet or exceed IPC 6012 Class 3 standards workmanship shall conform to IPC A 600 Class 3 current revisions Board material ond construction to be UL approved ond marked on the finished board Laminate Material Copper clad FR 4 high Tg material Tg gt 175 degrees C Td gt 350 degrees C Copper Weight 1 oz finished all layers Finished Thickness 0 062 0 010 inch Minimum plating thickness in through holes 0 001 inch Board Finish Immersion silver LPI soldermask both sides using appropriate layer artwork color green LPI silkscreen as required color white Vendor information to be incorporated on back side whenever possible Minimum copper
27. rom TP2 or J4 20 to the VggeH input of the ele 9 DAC8555 13 VnerL is tied to AGND an REFL is tied to i JMP9 1 3 Routes the user supplied negative reference from TP3 or J4 18 to the VggeL input of the e e 9 DAC8555 This voltage should be within the range of OV to VggeH sae Negative supply rail of the op amp U2 is powered by Vss for bipolar operation e JMP10 1 3 Negative supply rail of the op amp U2 is tied to AGND for unipolar operation Coco 1 3 3 Routes VouTA to J4 2 o JMP11 1 Routes VourA to J4 10 e s 9 20 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com EVM Operation Table 7 Jumper Settings and Functions continued Reference Jumper Setting Function 1 53 Routes VoyrB to J4 4 eee outes OU O MES JMP12 13 Routes Voy7B to J4 12 e s 9 1 3 Routes Voy7C to J4 6 JMP13 1 3 Routes VoytC to J4 14 efs e UNE Routes VourD to J4 8 eae outes OU o O JMP14 NES Routes VourD to J4 16 Ca E Routes J4 1 to U2 noninverting input e JMP15 1 3 Routes J4 3 to U2 noninverting input Coco E Routes U2 output to J4 5 e JMP16 1 3 Routes U2 output to J4 7 Ca SLAU204 December 2006 Submit Documentation Feedback DAC8555EVM User s Guide 21 3 TEXAS INSTRUMENTS www ti com Schematic 4 Schematic 22 DAC8555EVM User s Guide SLAU204 December 2006 Submi
28. rtise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is Solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obt
29. t Documentation Feedback REVISION HISTORY REV ENGINEERING CHANGE NUMBER APPROVED VCC Cc3 10uF IO V DVDD VrefH 2 ds LDAC I MM a try JMP11 A1 ENABLE ENABLE 1 E AB VrefL i9 7 A800 RSTSEL A4 12 14 9 a 6 a a af a REFN 18 Ale E fo oE fro CHEF 20 pep ole cle ce cle 3 POS 95 vs OUTPUT HEADER 1oK C12 ep OUT C il gt OUT_D J4A TOP SAM_TSM 110 01 L DV P nF J4B BOTTOM SAM SSW 110 22 F D VS K JMP6 R9 DAC8555IPW 2 SGH c TOK lt vec ola 1 OPA OUT HB f TP1 vee VIN VOUT C6 TEMP TRM rd C1 E Q4 o oo uF iOuF 0 1uF REFO2AU a l 1 3 R10 20K OPA2132UA VrefH TP2 REFIN GO EXTERNAL J2A ae REFERENCE CNTL GPIO0 TP3 SCLK 3 je Gi 4 REFin NOTE Voltage range of REFin input should not exceed 5 LKX DGND 6 LD ovren sync 77 CLKR GPIO X ENABLE gt rsx ero pS 2 SD 73 FSR DGND 75 ak VrefL gt DX eios FE nsrsEL gt DR GPIO4 5
30. the host processor and the EVM board In addition properly written code is also required to operate the DAC As discussed earlier a custom cable can be made specific to the host interface platform The EVM allows interface to the host processor through header connector J2 for the serial control signals and the serial data input The output can be monitored through header connector J4 An interface adapter card is also available for specific TI DSP DSKs as well as an MSP430 based microprocessor see Section 1 3 of this manual Using the interface card alleviates the tedious task of building customized cables and allows easy configuration of a simple evaluation system The DAC8555 interfaces with any host processor capable of handling SPI protocols or the popular TI DSPs For more information regarding the DAC8555 data interface please refer to the DAC8555 datasheet EVM Stacking Stacking multiple EVMS is possible if there is a need to evaluate two DAC8555s yielding a total of eight output channels A maximum of two EVMs can be stacked since the output terminal J4 dictates the number of DAC channels that can be connected without colliding Table 3 shows how the DAC output channels are mapped into the output terminal J4 with respect to the jumper positions of JMP11 JMP12 JMP13 and JMP14 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com EVM Operation Table 3 DAC
31. umentation Feedback 3 TEXAS INSTRUMENTS www ti com PCB Design and Performance JMP16 C 3c12 m Coana ca o MEE IW e E a 7 MP6 CI m NPI CNPR MS Wed i z 2 pe J u2 MP8 LJ LJL JL R4 z I N 2 U3_OUT C2 ul c3 R2R3 g o I I 1 16 SCLK 5 xra 3 we SO C J E JE 3 a 4 a mo LJ C3 Cyc7 RI R6 o i 1 P jr tsa n CIC 3g z OUTB QC e R UC 36 R12 R5 i T sms Wy R21 DAC8555E VM sore i y ri TP6 SDI T T A sU LU Q we p 5 Tim 2 our D im RL J C JR s ms fn C Jez vss AGND vop a 19 20 4REFN 5 C 2 10 ved 19 20 TP3 _AVCC_AGND VSS LREN Figure 2 DAC8555EVM PCB Top Silkscreen Image S C 2006 exos ingtrumen ts vi 3A z VCC DGND 5VA 3VA JMP7 5VA DGND VOD AVOD JS SLAU204 December 2006 Submit Documentation Feedback QU eee T Figure 3 DAC8555EVM PCB Layer 1 Top Signal Layer DAC8555EVM User s Guide 7 Wy TEXAS INSTRUMENTS www ti com PCB Design and Performance 1000 0 0 0 0 1090 0 m 3 e 1000 m m Kat 1 omen Figure 5 DAC8555EVM PCB Layer 3 Power Plane 8 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com PCB Design and Performance j Ti Figure 6 DAC8555EVM PCB Layer 4 Bottom Signal Layer B MOS S099085 9 CT Sat rm 1s s VJA ADF e0888 8 CSA OSA M7 LI LJ VIA CJC Jen er os S or LLL er 308 BSL al
32. yright 2006 Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination
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