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Spectrum Brands C6x User's Manual

1. 11 Connector Pinouts VME CBA 32 DCBAZ 1 VME DCBAZ 32 Figure 13 Connector Layout Part Number 500 00191 Revision 2 00 63 64 2 68 nee CERA J3 Seen h Ji J2 1 E 67 JTAG IN JTAG OUT ss jg Connector Connector DSP LINK3 Ribbon Cable Connector 63 Monaco Technical Reference Connector Pinouts 11 1 VME Connectors 64 Spectrum Signal Processing VME connector P1 is a standard 96 pin DIN 3 row connector VME connector P2 is standard 160 pin DIN 5 row connector The Monaco board will be factory configured to route either the PMC or DSP LINK3 connector to P2 Refer to the appropriate pinout for your board for this Table 16 VME P1 Connector Pinout pint Arow Sigal B Row Signal row Signal Ao cw ce bor cam Don Ds 0 sem ou 0 som ou De 0 cn os Do oo cor wo Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Connector Pinouts Table 17 VME P2 Connector Pinout PMC to VME P2 Pine ZRow Signal A Row Sigal E Row Signal c Row Signal D Row Sra e ew Ines e melu E cw momens e mens aen e mor memes e mec cm Part Number 500 00191 65 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Connector Pinouts Table 18 VME P2 Connector DSP LINK3 to VME P2 rine zRowS
2. rir nn AEAT nc 59 EL EE DEE sa ear peter arca eege Ee tte de database ada eres Tira tasas 60 10 3 Performance and Data Throughput nn rca 61 Elek EE dg eh eher 63 14 1 YME Conneciors SPRRREFERFERIUEREIFEFTFEFFREINER a a ER aa 64 11525 el ee lte 67 11 9 PEM GONNECIOS Age AAA Ge DE R 71 tiA JTAG Connectors EE 73 Part Number 500 00191 vii Monaco Technical Reference Spectrum Signal Processing Table of Contents viii Part Number 500 00191 Revision 2 00 Spectrum Signal Processing List of Figures Monaco Technical Reference Table of Contents Figure 1 BlockDiagram 2 1 bith ehh ad drid Neil ei al 4 Figure 2 Board Layout Hu lis rd ito alta lali lolis ici ii 6 Figure 3 Processor Node Block Diagram eae aerea near ana 10 Figure 4 DSP Memory Map 13 Figure 5 DSP Memory Map for External Memory Space CET 14 Figure 6 Serial PortROULING cid id ie dida 17 Figure 7 Global Bus Arbitration oooooocncccnnnicnnnnnnnncccnonccnnnrna narran cnn cnn 20 Figure 8 Primary VME A24 A32 Memory Map e nn nr nnnn cnn anna 24 Figure 9 A24 Secondary Interface Memory Map 25 Figure 10 PCI Memory Map 33 Figure 11 JTAG Chaln ddr 37 Figure 12 Interrupt ROUINO cnn none 40 Figure 13 Connector Layout EE 63 Part Number 500 00191 ix Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Table of Contents x Part Number 500 00191 Revision 2 00 Spectrum Signal Processin
3. Reserved Local SDRAM CE2 Processor Expansion Module PEM CE3 Figure 4 DSP Memory Map Part Number 500 00191 Revision 2 00 Reserved Internal Data RAM Reserved Monaco Technical Reference Processor Nodes Memory Size 64 KB 4 MB 64KB 512 KB 16 M 512 KB 4MB 2MB 6 MB 16 MB 16 MB 2 GB 64 MB 64 KB 2GB 2GB 64 KB 13 Monaco Technical Reference Spectrum Signal Processing Processor Nodes External Memory Space CEl is dedicated to accessing registers global shared RAM and DSP LINK3 Node A only Node A differs from nodes B C and D since it is the only node with access to the DSP LINK3 The following figure shows the memory map for this region Address Node A Nodes B C and D l po l 0140 0000 Global Shared SRAM Global Shared SRAM 512K x 32 512K x 32 015F FFFC 0160 0000 DSP LINK3 Standard Access 0163 FFFC 0164 0000 DSP LINK3 Standard Fast Access Reserved 0167 FFFC 0168 0000 DSP LINK3 RDY Controlled Access 016B FFFC 016C 0000 Hurricane Registers Hurricane Registers 016C 1FFC 016D 0000 Node A VPAGE Register Node B C or D VPAGE Register 016D 7FFC 016D 8000 Shared Bus Registers Shared Bus Registers 016D FFFC 016E 0000 SCV64 Register Set R W SCV64 Register Set R W 016E 7FFC 016E 8000 Reserved Reserved 016E FFFC 016F 0000 IACK Cycle Space Read Only IACK Cycle Space Read Only 016F FFFC 0170 0000 One Mbyte window to the One Mbyte window to the VME Addres
4. are set to 1 The KIPL 2 1 status bits D 2 1 in the VSTATUS Register determine the offset of the address to read within the IACK cycle space e KIPL2 is inverted to determine IACK address bit A3 e KIPLI is inverted to determine IACK address bit A2 The following table summarizes how the KIPL 2 1 bits in the VSTATUS Register initialize the VPAGE Register and set the IACK cycle address Table 12 KIPL Status Bits and the IACK Cycle Bo oonsrroooon Pro on o ooon fo o mem on on mem on 0 1 mem Po o 1 o eroon Do fo o gem Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Interrupt Handling SCV64 interrupts can be generated from the VMEbus vectored or internally by the SCV64 auto vectored e If the interrupt was caused by an external VMEbus interrupt the SC V64 initiates an JIACK cycle on the VMEbus The IACK cycle is acknowledged by the interrupter which puts its interrupt vector on the lower 8 data bits of the DSP s data bus e If the KIPL lines were set due to an internal auto vectored interrupt source the SCV64 initiates an IACK cycle on the VMEbus but no value is place on the lower 8 data bits The SCV64 terminates the cycle by asserting the KAVEC signal The KAVEC bit bit D3 in the VSTATUS Register can be read to determine which type of interrupt was generated After an IACK cycle is performed it is set to O if the value on th
5. u uuuunsssnnsnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnannnnnnnnnnnnnnnnnnnnnnnnnnnn 20 3 2 2 Burst Cycle BUS ACCESS eens eeeeaeeeenee sense arrancan ranma 20 Part Number 500 00191 v Revision 2 00 Monaco Technical Reference Table of Contents 3 2 3 Locked Cycles 4 VME64 Bus Interface 4 1 VME Operation 4 2 SCV64 Primary Slave A32 A24 Interface 4 3 A24 Secondary Slave Interface 4 4 Master A32 A24 A16 SCV64 Interface 5 DSP LINKS Interface 5 1 DSP LINK3 Data Transfer Operating Modes 5 2 Address Strobe Control Mode 5 3 Interface Signals 5 4 DSP LINK3 Reset GbCllntertace 6 1 Hurricane Configuration 6 2 Hurricane Implementation 7 JTAG DEDUGGING EE 8 Interrupt Handling 4 22ecennesuedonenans 8 1 Overview 8 2 DSP LINKS Interrupts to Node A 8 3 PEM Interrupts 8 4 PCI Bus Interrupts 8 5 Hurricane Interrupt 8 6 SCV64 Interrupt 8 7 Bus Error Interrupts 8 8 Inter processor Interrupts 8 9 VME Host Interrupts To Any Node 9 Registers EE VPAGE Register VSTATUS Register VINTA Register VINTB Register VINTC Register VINTD Register KIPL Enable Register vi Spectrum Signal Processing Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Revision 2 00 Table of Contents DSP LINK3 Register eet dee ane nile Ran 54 ID Register 2 2 a nenn 55 VME A24 Status Hegister AA 56 VME A24 Control Register AA 57 O ee NOA 59 10 1 Board Identification
6. DMA and other local interrupt capability On board logic routes VME bus error and the inter processor VINTx interrupts to INT4 as well This interrupt can be individually enabled or disabled for each node using the KIPL Enable Register address 016D 8014h Bits DO D4 enable the interrupt for each node when set to 1 The SC V64 interrupt is disabled from reaching the node when the corresponding bit is set to 0 Bit Interrupted Node DO Node A D1 Node B D2 Node C D3 Node D 41 Monaco Technical Reference Spectrum Signal Processing Interrupt Handling 42 The KIPL 2 0 status bits D 2 0 in the VSTATUS Register indicate the priority level of the SCV64 interrupt These bits reflect the state of the KIPL lines from the SCV64 If all three active low bits are set to 1 inactive then an SCV 64 interrupt did not cause the INT4 interrupt If the interrupt was due to an SCV64 interrupt it is serviced by performing an IACK cycle to the SCV64 An IACK cycle is a special type of VME read cycle to a specific location in the IACK cycle space base address 016F 0000h For an IACK read cycle bits D 0 7 of the VPAGE Register must be initialized in the following way e KADDRO bit DO is set to 0 e The value of the KIPLO bit in the VSTATUS Register is inverted and placed in the KADDRI bit bit D1 e KSIZEO bit D2 is set to 1 e KSIZEI bit D3 is set to 0 e All three KFC bits bits D 6 4
7. Fast Access mode writes will now generate ASTRB cycles The DSP LINK3 slave attached to the Monaco board should then latch the lower addresses 30 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference DSP LINK3 Interface 5 3 Interface Signals The DSP LINK3 interface consists of two 16 bit bi directional buffers for data a 16 bit address latch and a control signal buffer The control signals are terminated via a SCSI terminator The DSP LINK3 interface signals are e 32 data I O lines D 31 0 e 16 address outputs A 15 0 A15 and A14 are used for slave device board selection e DSTRB ASTRB R W and RST outputs e Tri state ready RDY input e 4 open collector interrupt inputs IRQO to IRQ3 These interrupt are logically OR ed and routed to the INT line of node A s C6x Refer to DSP LINKS specification for details available from Spectrum s internet web site at http www spectrumsignal com 5 4 DSP LINK3 Reset Part Number 500 00191 Revision 2 00 Bit DO of the DSP LINKS register controls the DSP LINK3 reset line This register is located at address 016D 8018h of node A Setting bit DO to 1 asserts the DSP LINK3 reset line setting it to 0 releases the reset DSP LINK3 resets must be at least 1 us long This reset is entirely under software control The DSP LINK3 reset line will also be asserted during SYSRESET or secondary control register board res
8. Global Shared SRAM and SCV64 Registers In order to access these CE1 resources the C6x must toggle the state of its Timer 0 pin TOUTO The state of this pin is controlled by the DataOut bit of the C6x Timer O Control Register Once TOUT has been toggled the CE1 resources are available to the C6x until the C6x is reset Part Number 500 00191 Revision 2 00 Monaco Technical Reference Processor Nodes Spectrum Signal Processing 2 8 Serial Port Routing Part Number 500 00191 Revision 2 00 Each C6x has two serial ports Serial Port O of each DSP is routed to the PEM connector associated with the DSP node Routing for Serial Port 1 on nodes A B C and D is determined by jumpers J7 to J10 as shown in the figure and following tables The jumper setting selects routing either to the PMC JN5 and VME P2 connectors or to the PEM connector associated with the DSP node Serial Port routing for the Monaco board is shown the figure Complete pinouts for the connectors are given in the Connector Pinouts chapter Figure 6 Serial Port Routing IL Serial Port 0 Node Node Node D D D out JP10 C6x PEM PEM o Serial 1 2 9 Port 1 IN Serial Port 0 VME Node Node Node C P1 C C JP9 PEM PEM OUT 7 Serial S
9. PEM Specification for mechanical and functional details of the PEM interface A separate A24 VMEbus Slave interface is used for direct access to the DSP s Host Port Interface This interface can be used for downloading code and as a control path from the host to the DSP Data transfer rates depend upon both the code executing in the DSP and the VMEbus Master performing the transfers but can be as high as 30 Mbytes second Jumper block JP1 selects the VME A24 base address for this slave interface Interrupt Lines There are four external interrupt inputs on each C6x They are INT4 INTS INT6 and INT7 All four must be configured as rising edge triggered interrupts upon initialization See the Interrupt Handling chapter for further information 15 Monaco Technical Reference Spectrum Signal Processing Processor Nodes 2 7 16 Processor Booting The C6x can boot from either the VME bus via its Host Port Interface HPI port or from an 8 bit EEPROM on an installed PEM module The jumpers listed in the following table select the booting method for each node Table 5 Processor Boot Source Jumpers Jumper Node PEM Boot HPI Boot JP2 Node A IN OUT JP3 Node B IN OUT JP4 Node C IN OUT JP5 Node D IN OUT The Monaco board uses the CE1 memory space of the Cox memory map 1 for the boot space upon power up or reset Immediately after booting the C6x cannot access the resources in its CE1 space such as the Hurricane registers
10. Part Number 500 00191 9 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Processor Nodes JTAG Test Bus L C6x Host Port De Interface HPI Bus Node Local ee Sat ee S i Zeg pe Resources 1 I I I I I I DSP Seri 1 erial 1 gt Port 1 I I I I A 128K x 32 SBSRAM I I I I I PEM Site E f I I I I 4M x 32 Shared with SDRAM Node Pair DSP LINK3 Interface Node A Only Address Buffer and Data Latches Es Global Shared Bus 7 Figure 3 Processor Node Block Diagram 10 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Processor Nodes 2 1 Processor Memory Configuration Each C6X DSP processor implements a 4 Gigabyte full 32 bit address space This address space is partitioned into internal memory space and external memory space External memory space is accessed through four memory select lines CEO CE1 CE2 and CE3 2 1 1 Internal Memory Internal memory space is further separated into three distinct regions e internal program RAM 64Kbytes e internal peripheral registers 2 Mbytes e internal data RAM 64 Kbytes These three regions define memory space which is implemented in the DSP processor 2 1 2 External Memory External memory is segmented into 4 regions e external memory interface CE
11. Pins 9 10 VME A24 slave interface base address bit A19 0 JP1 Pins 11 12 VME A24 slave interface base address bit A18 0 Pins 13 14 VME A24 slave interface base address bit A17 a I N Node A boot mode 0 Node B boot mode c U Go Node C boot mode Node D boot mode Node A Serial Port 1 Routing VME P2 Node B Serial Port 1 Routing VME P2 Node C Serial Port 1 Routing VME P2 Node D Serial Port 1 Routing VME P2 Default position Note The default VME A24 slave interface base address is set to 80 0000h Part Number 500 00191 7 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Introduction 8 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Processor Nodes 2 Processor Nodes The Monaco board supports one two or four embedded C6X processor nodes shared across the Global Shared Bus The three possible processor configurations are described in the following figure Table 3 Processor Configurations Populated Configuration Node A Node B Node C Node D 7 Each DSP node consists of e One TMS320C6201 DSP operating at 200 MHz for Monaco or one TMS320C6701 DSP operating at 167 MHz for Monaco67 e 128K of 32 bit Synchronous burst SRAM SBSRAM e 4Mof32 bit Synchronous DRAM SDRAM e Processor Expansion Module PEM interface e Aslave Host Port Interface to VME A24 bus e Two serial ports e A DSP LINK3 interface DSP node A only
12. TDI gt TDI TDO Routed back to JTAG IN if Node C nothing is C6x connected to JTAG OUT TDI TDO Node B hd C6x TDI The Test Bus Controller TDO 166 TBC is disabled bypassed if an external TDI Node A debugger is connected to JTAG INor TBC I CBX the JTAG IN connector Figure 11 JTAG Chain The JTAG IN input is buffered to reduce the load on an external JTAG device The JTAG OUT output is buffered to guarantee enough drive to external JTAG loads Up to three Monaco boards can be chained together through JTAG 37 Monaco Technical Reference Spectrum Signal Processing JTAG Debugging 38 For multiple Monaco boards the JTAG cable of the external debugger should be connected to the JTAG IN of the first board The JTAG OUT of the first board should be connected to the JTAG IN of second board The JTAG OUT of the second board should be connected to the JTAG IN of third board and so on The JTAG OUT connector of the last board is not connected to anything Note All hardware must be powered off before the JTAG cable are connected and the JTAG chain is set up Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Interrupt Handling 8 Interrupt Handling 8 1 Overview Part Number 500 00191 Revision 2 00 Each Cox has four interrupt pins which are configurable as either leading or falling edge triggered interrupts For the Monaco board all C6x interrupt
13. handling Spectrum board products Monaco Technical Reference Spectrum Signal Processing Preface Document Rev Date Changes Section Change _ _ lt aaaaaasassssssasisiIiIsasssssssss History 2 00 Sept 1999 Updated for TMS320C6201B and TMS320C6701 n a DSPs iv Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Table of Contents Table of Contents Rit el tee DEE 1 MAA EE 1 E le 2 UE EA EE 2 e 2 1 29 EE 2 124 Senal Pofts un EE 2 1 252 TAGS are ee ben UE Seege Ate AE 2 1 3 Reference Rei 3 1 4 General Bus ee 4 1 5 On Board Power Supply nono nn cnn cc ronca rn 4 1 6 Reset Conditions iii rada 5 1 6 1 VME SYSRESET usina ia 5 1 6 2 VME A24 Slave Interface Heset cnn rra rrn rra 5 1 06 38 TAG RESEN nee ltd toa 5 ee Ne EE 6 1 8 Jumper EE 7 2 ee 9 2 1 Processor Memory Configuration rs24srssennnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nn 11 2 dit lAternal Mem ty ici Aen eats ds 11 2 1 2 External E un EE 11 2 2 Synchronous Burst SAM deeg ee 15 23 Synchronous RETTEN 15 2 4 Processor Expansion Module 15 2 5 HOSE FO oireeni a os e eeh eech ti 15 KA gll eterg ENES priori 15 2 7 Processor BOO e nn ee ee een NEE EOE ee 16 2 8 serial Port ROUINO tota at 17 3 Global Shared NET 19 a MOMO eer hns EEan eege TE ga atado aces E co eege dE eteieeees T tira 19 3 2 Arbitral EE 19 3 2 1 Single Cycle Bus Access
14. host reads and writes data to this address for single cycle transfers to the HPID register The HPIA is not incremented for this HPI access mode 01 0000h 01 4000h 01 8000h 01 C0000h VME hosts which increment their target address can use this address space for DMA transfers to the HPID register Up to 4K of 32 bit data can be transferred in this space Data written to this space is automatically transferred to the HPID register and the HPIA register automatically increments by 4 bytes as each word is transferred 26 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference VME64 Bus Interface Before a host can transfer data through a node s HPI the VME host must set the HWOB bit of the node s HPIC register to 1 This only has to be done once after the Monaco board is reset To access an address within a C6x s memory space the VME host loads the address into the HPIA register Data is then transferred through the HPID register e The HPID at offset 8h auto increments four bytes after every cycle allowing it to be used for burst DMA data transfers e The HPID at offset Ch does not auto increment and is therefore intended for single cycle accesses only e The HPID DMA Space offers a 16K address space to VME hosts which increment their target address during DMA transfers This allows them to transfer data in blocks of 16K 32 bit words to the HPID register used for DMA
15. register to 1 e To clear an interrupt to node B set bit DO of this register to 0 50 Part Number 500 00191 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Registers VINTC Register Address 016D 800Ch D31 D8 Reserved D7 D1 This register allows any processor to generate or clear an interrupt to node C Upon reset this value is 0 e To generate an interrupt to node C set bit DO of this register to 1 e To clear an interrupt to node C set bit DO of this register to 0 Part Number 500 00191 51 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Registers VINTD Register Address 016D 8010h D31 D8 Reserved D7 Di This register allows any processor to generate or clear an interrupt to node D Upon reset this value is 0 e To generate an interrupt to node D set bit DO of this register to 1 e To clear an interrupt to node D set bit DO of this register to 0 52 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Registers KIPL Enable Register Address 016D 8014h D31 D8 Reserved The KIPL Enable Register is used to enable interrupts generated from the SCV64 to be sent to a particular processor node The KIPL lines represent VME interrupts location monitor interrupt SCV64 DMA and SCV64 timer interrupts These enable bits do not affect the individual
16. select from a wide variety of third party modules 1 2 3 PEM Four independent high speed full bandwidth bi directional dataflow channels between standard mezzanine boards Processor Expansion Modules or PEMs and the C6x processors are supported Application specific interfaces mounted to the PEM are available for computer telephony digital radio as well as customer specified interfaces 1 2 4 Serial Ports Two serial ports from each C6x are available at each PEM site for on board I O expansion For each C6x one of the serial ports is always routed to the PEM site the second can be routed to either the PEM site or the VME P2 connector 1 2 5 JTAG The secondary VME interface allows access to the on board JTAG Test Bus Controller TBC from a host single board computer for diagnostic purposes 2 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Introduction 1 3 Reference Documents Part Number 500 00191 Revision 2 00 Monaco Installation Guide from Spectrum Monaco Programming Guide from Spectrum DSP LINK3 Specification from Spectrum PEM Specification from Spectrum TMS320C6000 Peripherals Reference Guide from Texas Instruments SCV64 User Manual from Tundra Semiconductor Corporation Hurricane Data Sheet from Spectrum Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC IEEE P1386 1 Draft 2 0 available from IEEE VME64 ANSI VITA 1 1994 availa
17. transfers 4 4 Master A32 A24 A16 SCV64 Interface As a VME master the Monaco board supports A16 A24 or A32 transactions from any node to the VME64 bus through the SCV64 chip Any node can program the SCV64 s DMA Controller for VME Master Accesses and can directly master the VMEbus Each node has its own VPAGE Register to support the KFC KSIZE and upper 12 and lower 2 address bits to the SCV64 The upper 11 bits extend the 20 bit address space of the C6x to the full 32 bit address space of the VME bus Any node can monitor the status of the KIPL interrupt lines BUSERRORs for each node and KAVEC line by reading the VSTATUS Register The Monaco board supports Auto Syscon capabilities allowing it to become the System Controller board when placed in the leftmost slot of the VME backplane If it is to be the System Controller it should typically be booted from a PEM module equipped with a boot PROM Upon reset the SCV64 is in Bus Isolation Mode BI Mode which isolates the SC V64 from the VME64 bus The SCV64 is released from BI Mode by a write to the SCV64 Location Monitor from any node of the Monaco board Part Number 500 00191 27 Revision 2 00 Monaco Technical Reference VME64 Bus Interface 28 Spectrum Signal Processing Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference DSP LINK3 Interface 5 DSP LINK3 Interface The Monaco board provides a DSP LINK3 interface through a ribbo
18. 0 Spectrum Signal Processing Monaco Technical Reference Interrupt Handling 8 3 PEM Interrupts There are two active low driven interrupts from the PEM connectors for each node These interrupts PEM INT1 and PEM INT are OR ed together Their output is routed to INT6 of each node s DSP and inverted to create a rising edge trigger The Monaco board does not latch the PEM interrupts They must be cleared on the PEM module that generated them 8 4 PCI Bus Interrupts The four active low interrupt signals from the PCI bus INTA INTB INTC and INTD are physically tied together and routed to INTS of each of C6x DSPs They are also buffered through a de bounce circuit because they are open collector On node A the PCI bus interrupt is also shared with the Hurricane interrupt on INTS of the C6x through an OR gate The interrupt is not latched and its source must be cleared on the PMC module 8 5 Hurricane Interrupt The interrupt signal from the Hurricane chip is routed to each of the board s C6x processors On node A the PCI bus interrupt is also shared with the Hurricane interrupt on INTS of the C6x through an OR gate For nodes B C and D the Hurricane interrupt is routed to INT7 of the Cox 8 6 SCV64 Interrupt Part Number 500 00191 Revision 2 00 An interrupt line from the SCV64 VME interface is routed to the INT4 interrupt input of all four C6x processors The interrupt provides VME SCV64 timers and
19. 00h D31 D24 D23 D20 Reserved Reserved KADDR31 KADDR30 KADDR29 KADDR28 os 5 o KADDR27 KADDR26 KADDR25 KADDR24 KADDR23 KADDR22 KADDR21 KADDR20 MA AA oe ee oe E KFC2 KFC1 KFCO KSIZE1 KSIZEO KADDR1 KADDRO This register sets certain SCV64 address and control lines in order to extend the address range of the C6x processors and set up the type of VME cycle to be performed Each node has its own register Except for D7 all other reserved bits are disconnected D7 will store what is written to it These register is undefined upon reset and should be initialized Refer to the SCV64 User Manual for complete information on these signals KADDR 31 20 Sets the upper 12 address bits that are latched to the SCV64 when the KFC 2 0 KSIZE 1 0 KADDR 1 0 C6x accesses the VME address space This extends the 20 address bits of the C6x to the full 32 bits of the VME address space This allows a C6x access the entire VME bus as a master by setting these bits to 1 Mbyte region being accessed A write to this register latches data lines D19 8 and presents them to the SCV 64 upper address lines KADDR31 20 respectively For example a write to the VPAGE register with data equal to 8 0000h causes the next outbound VME cycle base address 0170 0000h with offset 0x0 to be addressed at VME address 8000 0000h Sets the access type as User or Supervisor Program or Data accesses Directly affects th
20. 2 bit of SBSRAM per processing node e 4M x 32 bit of SDRAM per processing node e Shared access to a 132 MBytes s PMC module site via the Spectrum Hurricane chip e 512K x 32 bit of fast globally shared SRAM accessible to the processor nodes PCI interface and VME64 interface e VME64 master slave interface provided by Tundra Semiconductor s SCV64 chip e VME A24 slave interface access to the C6x Host Port Interfaces HPIs e JTAG debugging support e Two PEM Processor Expansion Module sites e DSP LINK3 I O interface supporting IndustryPack modules Monaco Technical Reference Spectrum Signal Processing Introduction 1 2 Interfaces In addition to the VME bus which provides the primary interface to the host computer the Monaco board features PMC PEM serial port DSP LINK3 and JTAG interfaces 1 2 1 VME Two VMEbus interfaces are provided on the Monaco board The primary dataflow interface supports VME64 master and slave modes for fast data transfer through the SCV64 interface chip A secondary interface gives the VME A24 bus direct access to the Host Port Interface HPI of each C6x This provides direct control and data transfer to and from the DSP without interfering with dataflow on the Monaco s Global Shared Bus 1 2 2 PMC The Spectrum Hurricane PCI bridge chip supports high speed data transfer from an on board PMC site to the shared memory The industry standard IEEE 1386 PMC module site allows developers to
21. 29 PCI 33 signals DSP LINK3 31 internal memory space of DSP 11 internal peripheral register values C6x 12 inter processor interrupts 44 interrupt bus error 43 DSP LINK3 to node A 40 enable from SCV64 to anode 53 handling 39 Hurricane 41 INT4 identify source 47 inter processor 44 lines 15 node A to 49 node B to 50 node C to 51 node D to 52 PCI 41 PEM 41 routing 40 SCV64 41 enable to a node 53 VME host to any node 44 J JN1 connector 67 JN2 connector 68 JN4 connector 69 JN5 connector 70 JTAG 2 connector 73 IN 73 OUT 73 debugging 37 reset 5 JTAG chain 37 JTAG IN connector 73 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Part Number 500 00191 Revision 2 00 JTAG OUT connector 73 jumper settings 7 setting DSP boot source 16 K KIPL enable register 53 status bits 42 L locked cycle global shared bus access 21 locking global shared bus 21 precautions to follow 21 memory configuration DSP 11 global shared bus 19 map DSP 13 external memory space CE1 14 PCI 33 primary VME A24 A32 24 secondary VME A24 25 Monaco67 1 P P1 connector 64 P2 connector 65 PCI IDSEL line of device 36 interface 33 interrupts 41 memory map 33 PEM 2 15 connector 71 PEM 1 71 PEM 2 72 interrupts 41 performance specifications 61 pinout See connector PMC 2 connector 67 JN1 67 JN2 68 JN4 69 JN5 70 Mon
22. DSP SYSTEMS WORLDWIDE E Monaco Quad C6x VME64 Board Technical Reference Document Number 500 00191 Revision 2 00 September 1999 Copyright 1999 Spectrum Signal Processing Inc All rights reserved including those to reproduce this document or parts thereof in any form without permission in writing from Spectrum Signal Processing Inc All trademarks are registered trademarks of their respective owners Spectrum Signal Processing reserves the right to change any of the information contained herein without notice Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Preface About Spectrum Contacting Spectrum Customer Feedback Preface Spectrum Signal Processing offers a complete line of DSP hardware software and I O products for the DSP Systems market based on the latest DSP microprocessors bus interface standards I O standards and software development environments By delivering quality products and DSP expertise tailored to specific application requirements Spectrum can consistently exceed the expectations of our customers We pride ourselves in providing unrivaled pre and post sales support from our team of application engineers Spectrum s excellent relationships with third party vendors provide customers with a diverse and top quality product offering In 1994 Spectrum achieved ISO 9001 quality certification Spectrum s Applications Engineers are available to provi
23. INK3 interface while it has locked the Global Shared Bus by asserting TOUTO the bus will be released Node A s next access to the bus will re lock it to node A providing that TOUTO is still asserted 3 Some SCV64 inbound cycles can occur while the bus is locked If a C6x has locked the bus and is performing a VME outbound cycle while a VME inbound cycle is in progress the Cox will be temporarily backed off and the SCV64 cycle will proceed The Global Shared Bus will be returned to that C6x node after the SCV64 cycle finishes No other Cox will get ownership of the bus 4 Ifa debugger is being used when one processor has the bus locked for an extended time while another processor is trying to get the bus the debugger may timeout Part Number 500 00191 21 Revision 2 00 Monaco Technical Reference Global Shared Bus 22 Spectrum Signal Processing Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference VME64 Bus Interface 4 VME64 Bus Interface There are two separate VMEbus slave interfaces on the Monaco board One is implemented by the SCV64 and provides A32 and A24 VMEbus masters access to the global shared bus The second slave interface provides direct access to the Test Bus Controller for debugging and to the Host Port Interfaces HPIs of each Cox The HPI provides support for code download control and data transfers from the VME64 bus 4 1 VME Operation The Monaco board require
24. KBERR interrupt bits KIPL END When set to 1 interrupts to node D that are generated from the SCV64 KIPL lines are enabled Active high KIPL ENC When set to 1 interrupts to node C that are generated from the SCV64 KIPL lines are enabled Active high KIPL ENB When set to 1 interrupts to node B that are generated from the SCV64 KIPL lines are enabled Active high KIPL ENA When set to 1 interrupts to node A that are generated from the SCV64 KIPL lines are enabled Active high These bits are set to 0 upon reset Note KIPL interrupts must also be enabled by register writes to the SCV64 Refer to the SCV64 data book for further information Part Number 500 00191 53 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Registers DSP LINK3 Register Address 016D 8018h D31 D8 Reserved Processor node A uses this register assert or release reset to the DSP LINK3 interface its local bus It is also used to control the operation of DSP LINK3 standard fast accesses DL3 RESET Setting this bit DO to 1 asserts reset to the DSP LINK3 e Setting this bit DO to 0 releases the DSP LINK3 from reset Set to 1 upon reset Application code must set it to 0 to release the DSP LINK3 from reset ASTRB_EN e Setting this bit D1 to 1 enables ASTRB accesses to DSP LINK3 Accesses to the standard fast region when ASTRB_EN is set will be ASTRB accesse
25. O 16 Mbytes e external memory interface CEI 4 Mbytes e external memory interface CE2 16 Mbytes e external memory interface CE3 16 Mbytes External memory CEO CE1 CE2 and CE3 consists of node local memory resources which are accessed on the DSP Local Bus but are external to the DSP processor The type of memory in each of the four CE regions is determined by settings in the internal peripheral registers All remaining memory in the 4 GB address space is reserved The internal peripheral registers for Monaco must be initialized to the values in the following table upon reset for the board to operate Part Number 500 00191 11 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Processor Nodes Table 4 C6x Internal Peripheral Register Values Global Control Register 0x0000 3078 NOHOLD External HOLD disable off 0x0180 0000 SDCEN SDRAM clock enable on SSCEN SBSRAM clock enable on CLK1EN CLKOUT1 enable on CLK2EN CLKOUT2 enable on SSCRT SBSRAM clock rate select 1 2x CPU clock RBTR8 off requester controls EMIF until a high priority request occurs EMIF CEO Control Register OxFFFF 3F43 MTYPE 32 bit wide SBSRAM 0x0180 0008 No other bits are used EMIF CE1 Control Register 0x30E4 0421 MTYPE 32 bit wide asynchronous interface 0x0180 0004 write setup 3 cycles write strobe 3 cycles write hold 2 cycles read setup 4 cycles read strobe 4 cycles read hold 1 cycle all cycles ar
26. R W own node No Access R W own node No Access R W own node No Access R W 32 bit only R W Rw RW Hurricane DMA E No Access access only No Access No Access No Access No Access Target Internal program amp data RAM Local SDRAM Local SBSRAM Global Shared RAM Hurricane Registers PMC Site SCV64 Registers Global Shared Bus Registers R W R W R W VMEbus as master 512K of 32 bit Asynchronous RAM implemented in four 512K x 8 bit Asynchronous RAM devices is provided on the Global Shared Bus The C6x DSPs can only perform 32 bit accesses to the Global Shared RAM Byte accesses are not supported 3 2 Arbitration Part Number 500 00191 Revision 2 00 Arbitration of the Global Shared Bus is implemented using a next bus owner token that is passed serially from one device to the next Token passing follows a strict hierarchical sequence ordered by bus servicing priority There are six devices participating in the process These are in decreasing priority e SCV64 e Hurricane e DSP Node A e DSP Node B e DSP Node C e DSP Node D 19 Monaco Technical Reference Spectrum Signal Processing Global Shared Bus 20 Bus ownership is cycled between the two highest priority devices SCV64 and Hurricane until neither device requires the bus Then the DSP Nodes are processed round robin After one pass through the DSP chain the cycle loops back to include the SCV64 and Hurricane This eliminates any arbitration latency
27. S 1 2 Port 1 IN Serial Node Node Foro B B Node B PEM PEM JP8 C6x 1 2 QUE Serial H Port 1 IN Serial Node Node Port 0 A A PEM PEM dao 1 2 OUT 5 SE Serial a F Port 1 IN PMC Connector JN5 Node D Serial Port 0 Node D VME Node C Serial Port 0 Node C Pa Node B Serial Port 0 Node B Node A Serial Port 0 Node A 17 Monaco Technical Reference Spectrum Signal Processing Processor Nodes Pin assignments for the serial ports are given in the following tables Table 6 PEM Connections for Serial Port 0 and 1 PEM 1 Port 0 PEM 2 Port 1 CLKS External clock CLKR Receive clock CLKX Transmit clock DR Received serial data D Transmitted serial data F Receive frame synchronization Transmit frame synchronization The serial port routing jumper corresponding to the node J7 J8 J9 or J10 must be OUT for port 1 to be routed to the node s PEM 2 connector Table 7 VME and PMC Connections for Serial Port 1 Node A J7 IN Node B J8 IN Node C J9 IN Node D J10 IN PMC JN5 VME P2 PMC JN5 VME P2 PMCJN5 VME P2 PMC JN5 VME P2 CLKX Transmit clock 29 D 22 10 ER 30 Z 21 18 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Global Shared Bus 3 Global Shared Bus 3 1 Memory The Global Shared Bus provides access between devices on the Monaco board as shown in the following table Table 8 Global Shared Bus Access C VME Bus Nodes Site via SCV64
28. Technical Reference Spectrum Signal Processing VME64 Bus Interface The Host Port Interface HPI allows a VME host to access the memory map of any C6X The board transfers 32 bit VME accesses automatically through the 16 bit Host Port Interface as two 16 bit words The interface consists of three read write 32 bit registers that are accessed through the VME A24 slave interface e HPI Address register HPIA e HPI Control register HPIC A C6x can also read and write to its HPI Control register HPIC at address 0188 0000h e HPI Data register HPID VME address bits A 3 2 select which register is being accessed in each node s HPI register address space These bits are mapped to the HCNTRL 1 0 control pins of the C6x The following table shows how the HPI interface is addressed Table 9 HPI Register Addresses VME address AAN C6x Node Node Node Node Register A B C D Description HPIC 00 2000h 00 3000h 00 4000h 00 5000h State for reading setting the Control Register value HPIA 00 2004h 00 3004h 00 4004h 00 5004h Used to read set the HPI address pointer The HPIA points into the C6x memory space HPID 00 2008h 00 3008h 00 4008h 00 5008h A VME host reads and writes data to this address for DMA transfers to the HPID register The HPIA register automatically increments by 4 bytes as each word is transferred through the HPID register HPID 00 200Ch 00 300Ch 00 400Ch 00 500Ch A VME
29. aco Technical Reference SCV64 Register Values power supply 4 processor See DSP Processor Expansion Module See PEM R reference documents 3 register 45 address summary 45 C6x internal peripheral 12 DSP LINK3 54 Host Port Interface addresses 26 Hurricane register set 34 ID 55 KIPL enable 53 SCV64 VME64 75 VINTA 49 VINTB 50 VINTC 51 VINTD 52 VME A24 control register 57 VME A24 status register 56 VPAGE 27 46 VSTATUS 27 47 reset 5 DSP LINK3 31 assert or release 54 JTAG 5 VME A24 slave interface reset 5 VME SYSRESET 5 routing interrupts 40 serial ports 17 S SBSRAM 15 SCV64 VME64 interface interrupts 41 master 27 memory map primary 24 secondary interface 25 primary slave 23 register initialization 75 secondary slave 24 VPAGE register 46 SDRAM 15 serial ports 2 pin assignments 18 79 Monaco Technical Reference Index 80 port VME and PMC connections 18 routing 17 setting via jumpers 7 single cycle global shared bus access 20 specifications data throughput 61 performance 61 synchronous burst SRAM 15 synchronous DRAM 15 SYSRESET 5 T TBC 37 Test Bus Controller 37 throughput specifications 61 TMS320C6201 1 9 TMS320C6701 1 9 token passing 19 TOUTO 16 21 V VINTA register 49 VINTB register 50 Spectrum Signal Processing VINTC register 51 VINTD register 52 VME 2 A24 control register 57 A24 slave interface base a
30. al Processing Monaco Technical Reference Specifications 10 Specifications 10 1 Board Identification Part Number 500 00191 Revision 2 00 Power current and data throughput specifications depend upon the type and version of processors used on the board Monaco Monaco boards currently use the TMS320C6201B DSP Earlier Monaco versions used the TMS320C6201 Monaco boards with this processor may have heat sinks or fans installed over the DSPs due to the higher power consumption of the earlier DSP Monaco67 Monaco67 boards use the TMS320C6701 DSP The processor type and version can be identified by examining the DSPs on the board earlier DSPs have the marking C21 while TMS320C6201B chips are marked C31 Boards equipped with earlier TMS320C6201 revision 2 1 chips may also have heat sinks or fans attached to the cover of the DSPs The board s 600 level part number may also be used to determine which DSPs are used on the board The following table presents a partial list of Monaco part numbers 200 MHz TMS320C6201 200 MHz TMS320C6201B 167 MHz TMS320C6701 600 00078 600 0027 1 600 00254 600 00112 600 00272 600 00256 600 00127 600 00273 600 00128 600 00129 600 00220 600 02097 600 02100 59 Monaco Technical Reference Spectrum Signal Processing Specifications 10 2 General Table 14 Specifications Parameter Monaco Monaco Monaco67 TMS320C6201B TMS320C6201 TMS320C6701 Current Consumption 5 Volt
31. as bus ownership is transferred between devices and grants the highest priority to those devices interfacing to external buses VME and PCT which require the fastest response The arbitration cycle is shown in the following figure Note Because there is no ownership timer for either Hurricane or SCV64 chip the system designer must ensure that processors are not held off from the shared resources for unreasonable lengths of time Highest Priority Lowest priority E SO amp ASS i E Seene Round Robin i VME amp PCI Bus DSP i cocoa Round Robin rennen F Figure 7 Global Bus Arbitration Access to the Global Shared Bus can use single burst or locked cycles 3 2 1 Single Cycle Bus Access For single cycle accesses a device requests the global shared bus by simply initiating a read or write access to the bus When the bus is free the device acquires it and performs the single cycle access The bus is then released 3 2 2 Burst Cycle Bus Access Burst cycles are used during DMA transfers from a C6x processor to the Global Shared Bus A 6 bit bus ownership timer on each node prevents a Cox from owning the bus for more than 640 ns when another device is requesting the bus When the burst cycles are begun the timer is started If another device requests the bus when the timer expires the bus is released otherwise ownership is maintained and the timer is reset and started again If multiple DSPs request the bus thi
32. ble from ANSI Monaco Technical Reference Spectrum Signal Processing Introduction 1 4 General Bus Architecture The following block diagram shows the main components of the Monaco board y y C LAA cl C6x Host Port Inteface HPI Node A C6x PEM Site F PEM Site e SBSRAM SBSRAM SBSRAM DSP LINK3 Interface 1 128K x 32 128K x 32 I 128K x 32 Jas m Um a 4 EEN o RT A SDRAM SDRAM SDRAM SBSRAM 4M x 32 4M x 32 4M x 32 l 128K x 32 SDRAM i i 4M x 32 I PMC 1 l Site N I I I N Address Buffer Address Buffer Address Buffer Address Buffe I 1 and and and an x Data Latches Data Latches Data Latches Data Latches PCI Bus p ontroller Hurricane Global Shared Bus Global Shared SCV64 A24 VME SRAM VME64 Slave 512K x 32 Interface Interface VME P2 Connector VME P1 Connector Figure 1 Block Diagram 1 5 On Board Power Supply There is an on board high efficiency DC DC power converter that supplies 2 5V and 3 3V power to the board from the VME 5V supply The circuit efficiency is approximately 90 The 3 3V supply is available to the PEM and PMC sites as well as 5V and 12V Up to 16 5 Watts is available from th
33. d only 016E 0050h I to Reserved 1 016E 007Ch 016E 0080h Status Register 0 00000000h 016E 0084h Status Register 1 00000080h 016E 0088h General Control Register 0000001Ch 016E 008Ch VMEbus Interrupter Requester 00000000h 016E 0090h VMEbus Requester Register 000000CFh 016E 0094h VMEbus Arbiter Register 00000034h 016E 0098h ID Register Read only 016E 009Ch Control and Status Register 00000002h 016E 00A0h Level 7 Interrupt Status Register Read only Part Number 500 00191 75 Revision 2 00 Monaco Technical Reference SCV64 Register Values Table 27 SCV64 Register Initialization C6x Address Register 016E 00A4h 016E 00A8h 016E 00ACh 016E 00B0h 016E 00B4h 016E 00B8h 016E 00BCh 016E 00COh 016E 00C4h 016E 00C8h 016E 00CCh 016E 00DOh 016E 00D4h 016E 00D8h 016E 00DCh 016E 00E0h 016E 00E4h I to Local Interrupt Status Register Spectrum Signal Processing Value Read only Level 7 Interrupt Enable Register 00000001h Local Interrupt Enable Register 00000000h VMEbus Interrupt Enable Register 00000000h Local Interrupts 1 and 0 Control Register 00000089h Local Interrupts 3 and 2 Control Register 000000A8h Local Interrupts 5 and 4 Control Register 000000CBh Miscellaneous control register Delay line control register Delay line status register 1 Delay line status register 2 Delay line status register 3 Mailbox register 0 Mailbox register 1 Mailbox register 2 Mailbox register 3 00000000h Dynamically co
34. ddress setting via jumpers 7 A24 slave interface reset 5 A24 status register 56 bus backplane connectors 23 interface 23 SCV64 VME64 master 27 primary slave 23 secondary slave 24 operation 23 connector P1 64 P2 DSP LINK3 to VME 66 PMC to VME 65 interrupts host to any node 44 SYSRESET 5 VME A24 control register 57 VME A24 status register 56 VPAGE register 27 46 VSTATUS register 27 47 Part Number 500 00191 Revision 2 00
35. de technical support Monday to Friday 8 00 AM to 5 00 PM Pacific Standard Time Telephone 1 800 663 8986 or 604 421 5422 Fax 604 421 1764 Email support spectrumsignal com Internet http www spectrumsignal com To help us assist you better and faster please have the following information ready e A concise description of the problem e The names of all Spectrum hardware components e The names and version numbers of all Spectrum software components e The minimum amount of code that demonstrates the problem e The versions of all software packages including compilers and operating systems At Spectrum we know that accurate and easy to use manuals are important to help you develop your applications and products If you wish to comment on this manual please e mail us at documentation O spectrumsignal com or fax us at 604 421 1764 Please include the following information e The full name document number and version of the manual e A description of any inaccuracies you may have found e Comments about what you liked or did not like about the manual It may be helpful for us to call you to discuss your comments If this would be acceptable please include your name organization and telephone number with your comments Note Spectrum board products are static sensitive and can be damaged by electrostatic discharges if not properly handled Use proper electrostatic precautions whenever Part Number 500 00191 Revision 2 00
36. e 3 3V supply for the PEM and PMC sites The combined 3 3V current consumption of modules on these sites must not exceed 5 Amps When adding modules to the Monaco board ensure that the power requirements for the modules are within the specified limits and that the system power supply and cooling are sufficient to meet the added requirements 4 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Introduction 1 6 Reset Conditions The Monaco board responds to three types of reset conditions e VME SYSRESET VME bus SYSRESET line e VME A24 Slave Interface Reset VME A24 Control Register bit DO e JTAG reset JTAG chain TRST line The following table indicates which hardware components are reset by the specific reset condition Table 1 Reset Summary Reset Condition Y Component is Reset Hardware SYSRESET Slave Interface Reset JTAG Reset Procssernodes vp vo fo lt lt VME A24 slave interface registers lt i lt JTAG withinDsPs YP BEZ PEMintertace Lt El LEUKEN JOSP LINKS interface Li JL xv TI Part Number 500 00191 Revision 2 00 lt lt lt 1 6 1 VME SYSRESET A VME SYSRESET is initiated when the SYSRESET line on the VME bus is driven low All devices and registers on the Monaco board are reset to their default conditions 1 6 2 VME A24 Slave Interface Reset The VME A24 slave interface reset is initiated from the VME bus by setti
37. e address modifiers used for the VME Master cycle Sets the number of bytes transferred for VME Master cycles Directly affects D32 D16 or D8 access type These bits allow the node which is little endian in order to access the PEM and PMCs to access the SCV64 which is big endian Note Although access to VPAGE is local to each processor node any read or write to the register requires that the Global Shared Bus to be acquired The DSP s cycles are extended until any current Global Shared Bus operations are complete when accessing the VPAGE Register Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Registers VSTATUS Register Address 016D 8000h D31 D24 D23 Reserved D16 D15 Reserved D14 D13 D12 D11 D10 Reserved VINTD VINTC VINTB VINTA Ja es o e oe oa BUSERRD BUSERRC BUSERRB BUSERRA KAVEC KIPL2 KIPL1 KIPLO This register is used by a processor to identify the source of an INT4 interrupt VINTD VINTC VINTB VINTA BUSERRD BUSERRC BUSERRB Part Number 500 00191 Revision 2 00 Status of the user defined interrupt to node D Set to 1 when another processor has set the VINTD interrupt register Active High Status of the user defined interrupt to node C Set to 1 when another processor has set the VINTC interrupt register Active High Status of the user defined interrupt to node B Set to 1
38. e clockout1 cycles EMIF CE2 Control Register OxFFFF 3F33 MTYPE 32 bit wide SDRAM 0x0180 0010 No other bits are used EMIF CE3 Control Register 0x72B7 0A23 MTYPE 32 bit wide asynchronous interface Used for PEM Must be address 0x01800004 reconfigured for individual value 0x30E40421 PEM MTYPE 32 bit wide asynchronous interface 0x0180 0014 write setup 7 cycles write strobe 10 cycles write hold 3 cycles read setup 7 cycles read strobe 10 cycles read hold 3 cycle all cycles are clockout1 cycles EMIF SDRAM Control 0x0544 A000 RFEN 0 internal refresh enable OFF Only external SDRAM 0x0180 0018 refresh can be used SDWID 1 SDRAM width select two 16 bit SDRAMs Other timing parameters are SDRAM specific and should not be modified by the user EMIF SDRAM Timing 0x0000 061A Refresh timer implemented in external hardware This register is 0x0180 001C not used 12 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing C6x Addr 0000 0000 0000 1000 0040 0000 0048 0000 0140 0000 0180 0000 01A0 0000 0200 0000 0300 0000 0400 0000 8000 0000 8001 0000 FFFF FFFF Upon Reset PEM EEPROM Boot Mode Memory Contents SCV64 Registers see the following CE1 Internal Program RAM Reserved Local SBSRAM Reserved CEO External Memory Space CE1 External Memory Space CE1 After TOUTO is toggled DSP LINK3 Shared SRAM memory map Internal Peripheral Space
39. e lower 8 bits is a valid interrupt vector or to 1 if the value is not a valid interrupt vector Auto vectored interrupt sources can be cleared by accessing the SCV64 register set Refer to the SCV64 User Manual for more information 8 7 Bus Error Interrupts Bus error interrupts BUSERR_x are generated whenever an access cycle from a node or SCV64 DMA to the VME bus causes the SCV64 to generate a bus error This interrupt is routed only to INT4 of the C6x responsible for causing the VME bus error On board logic routes enabled SC V64 interrupts and the inter processor VINTx interrupts to INT4 as well Any node can also determine the status of the bus error interrupts by reading the VSTATUS Register at address 016D 8000h A 1 in any of the following bit positions of the register indicates which nodes have pending bus error interrupts Bit Node Whose Access Caused the Bus Error D4 Node A D5 NodeB D6 Node C D7 Node D To clear the interrupt the interrupted C6x writes a 1 to the same bit in the VSTATUS Register It must also clear the appropriate bits in the SCV64 DCSR register before the board can access the VME bus again Part Number 500 00191 43 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Interrupt Handling 8 8 8 9 44 Inter processor Interrupts The Inter processor interrupts VINTx are shared with the SCV interrupt They allow any processor to interrupt any o
40. et conditions 31 Monaco Technical Reference DSP LINK3 Interface 32 Spectrum Signal Processing Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference PCI Interface 6 PCI Interface The Hurricane chip provides the interface between the Global Shared SRAM on the Global Shared Bus and the PMC site which supports a 32 bit 33 MHz PCI bus Although the DSPs cannot directly master the PCI bus the Hurricane s DMA controller provides flexible data transfer between the Global Shared Bus SRAM and the PMC Embedded PCI buses require Hurricane PCI configuration cycle generation Pre emptive arbitration is not used If a node requests the Global Shared bus when the bus is not currently in use then it will be granted the bus It is up to the bus ownership timers of the Hurricane and PMC devices to prevent bus hogging PMC modules can directly master the Global Shared SRAM The memory map of the Monaco seen by a PMC module is shown in the following figure PCI Offset Address Access 0000 0000h Global Shared SRAM 001F FFFFh 0020 0000h Hurricane Control Registers 002F FFFFh 0030 0000h Reserved 003F FFFFh Figure 10 PCI Memory Map 6 1 Hurricane Configuration Before the PMC site can be accessed the Monaco initialization software must configure the Hurricane registers with the values shown in the following table Only the indicated values should be initialized all other values should be le
41. ft alone As can be seen these registers can be accessed from a C6x the PMC s PCI bus and a host on the VME bus Part Number 500 00191 33 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing PCI Interface Table 11 Hurricane Register Set DSP Offset Address Offset SCV64 Offset op oxorec 0078 00200078 oo Lem or 0160 0070 soe om Lem 34 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference PCI Interface Address Offset SCV64 Offset Ox2E 0x016C 00B8 0x002000B8 0x0020 00B8 Y Hurricane 0x39 0x016C 00E4 0x0020 00E4 0x0020 00E4 0x016C 00E8 0x0020 00E8 0x0020 00E8 MABE Map Bank Enable 0x0001 0100 CSER Chip Select Enable BER Mask Broadcast Ox3E 0x016C 00F8 0x002000F8 0x0020 00F8 DBIC DSP bus interface control OX3A PCI Configuration Registers g 7 UV O bi 2 Part Number 500 00191 35 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing PCI Interface Hurricane C6x PCI Bus Slave A32 A24 Register Description Value Initialize DSP Offset Address Offset SCV64 Offset 0x016C 013C 0x0020013C 0x0020 013C 0x0120 0100 0x016C 0140 0x0020 0140 0x0020 0140 BARO Shadow Register OXFFOO 0000 Y 6 2 Hurricane Implementation The Hurricane PCI to DSP Bridge Data Sheet should be read in order to understand how it is used with the Monaco board On the DSP port of the Hurricane on
42. g Monaco Technical Reference Table of Contents List of Tables Table 1 Reset SUMMA Y cece eeceaeeeeaaeseeneeceaeeeeaaeeeaaeseeaeeseeeeecaaeseeaaeseeeeeseieeeeiaeeeeseeees 5 Table 2 Jumper Setlings rin aa ira 7 Table 3 Processor Co nfigurati NS ineen eek tebe estas aged tina bb 9 Table 4 C6x Internal Peripheral Register Values nana 12 Table 5 Processor Boot Source Jumpers 16 Table 6 PEM Connections for Serial Port O and 18 Table 7 VME and PMC Connections for Serial Port 18 Table 8 Global Shared Bus Access 19 Table 9 HPI Register Addresses mnmn400nnnnnnnonnnnnnnonnnnnnnonnnnnnonnunnnnannnnnnnannnnnnnannnnnnnannnnnnn 26 Table 10 DSP LINK3 Data Transfer Operating Modes erra 30 Table 11 Hurricane Register Get 34 Table 12 KIPL Status Bits and the IACK CyCle 0 ceccccceceeeeeeceeeeeceeeeeeeaeeeeaeeseeeeeseaeeesaeeeeneeeeaees 42 Table 13 Register Address Gummanm nenn 45 Table 14 Specificationsanue naeh ach nein E Mena neccesary 60 Table 15 Data Access Transfer Pertommmanmce oococccccnnonocococoncnnnnnnnononnnnncnnnnnnnnnnnnnnnnnnnnnnnnnncnncanannns 61 Table 16 VME P1 Connector Pinout cnc nnnnn nn nn naar E 64 Table 17 VME P2 Connector Pinout PMC to VME P 65 Table 18 VME P2 Connector DSP LINK3 to VME P 66 Table 19 PMC Connector JN1 Pinout ussessnseensnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 67 Table 20 PMC Connector JN iii id it A A SEA 68 Table 21 PMC C
43. g modes as shown in the following memory map Part Number 500 00191 23 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing VME64 Bus Interface VME Offset Address Access 0000 0000h Global Shared SRAM DSP lower 1Mbyte 000F FFFFh 0010 0000h and Hurricane Global Shared SRAM accessible Upper 1 Mbyte 001F FFFFh 0020 0000h Hurricane Control Registers 002F FFFFh 0030 0000h Reserved 003F FFFFh Figure 8 Primary VME A24 A32 Memory Map Note The full A24 memory map occupies one quarter of the available A24 space This can be reduced to the standard 512K 16M 32 of the available A24 space by mapping only the lower 512 Kbytes 128k x 32 of the global shared SRAM This is entirely programmable in the SCV64 base address registers Only SCV64 A21 and A20 are used for decode on SCV64 VME slave accesses to the board D16 and DOSEO writes are not supported on the primary A32 A24 interface 4 3 A24 Secondary Slave Interface 24 Jumper block JP1 sets address bits A23 A17 of the VME A24 slave interface This base address defines a 128K byte addressed memory space accessed by the VME bus Access to this space from the VME bus bypasses the SCV64 VME bus interface chip All A24 VME transfer types are accepted except for LOCK and MBLT types As shown in the following memory map the A24 slave interface provides the VME bus direct access to e The Host Port Interface HPD registers of each C6x pr
44. hnical Reference Connector Pinouts 72 Table 24 PEM 2 Connector Pinout DEDO DD eo J Ds w sm Spectrum Signal Processing Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Connector Pinouts 11 4 JTAG Connectors Both JTAG connectors use 2 x 7 0 1 x 0 1 bare pin headers Table 25 JTAG IN Connector Pinout ate ea Part Number 500 00191 73 Revision 2 00 Monaco Technical Reference Connector Pinouts 74 Spectrum Signal Processing Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference SCV64 Register Values Appendix A SCV64 Register Values This appendix briefly describes the default register settings for the SCV64 on the Monaco board The following table shows the default values that are programmed into the registers by the initialization code supplied with the Monaco board Table 27 SCV64 Register Initialization 016E 0000h DMA Local Address 00000000h 016E 0004h DMA VMEbus Address 00000000h 016E 0008h DMA Transfer Count 00000000h 016E 000Ch Control and Status 00000000h 016E 0010h VMEbus Slave Base Address See notes 016E 0014h Rx FIFO Data Read only 016E 0018h Rx FIFO Address Register Read only 016E 001Ch Rx FIFO Control Register Read only 016E 0040h Slave A64 Base Address 00000000h 016E 0044h Master A64 Base Address 00000000h 016E 0048h Local Address Generator Read only 016E 004Ch DMA VMEbus Transfer Count Rea
45. ications 61 data transfer operating modes DSP LINK3 29 Address Strobe Control 30 debugging JTAG 37 DSP booting 16 jumpers to set boot source 16 identifying which processor the software is running on 55 memory configuration 11 memory map 13 external memory space CE1 14 processor configurations 9 registers Host Port Interface register addresses 26 internal peripheral 12 DSP LINK3 connector to VME 66 data transfer operating modes 29 Address Strobe Control 30 interface 29 signals 31 77 Monaco Technical Reference Index 78 interrupts to node A 40 register 54 reset 31 assert or release 54 standard fast accesses control 54 E EEPROM 16 enable interrupt from SCV64 to a node 53 external memory space of DSP 11 F features of the board 1 fixed point 1 floating point 1 G generate interrupt to node A 49 to node B 50 to node C 51 to node D 52 global shared bus 19 access burst cycle 20 locked cycle 21 locking 21 precautions to follow 21 single cycle 20 arbitration 19 memory 19 H handling interrupts 39 Host Port Interface 15 26 register addresses 26 HPI See Host Port Interface Hurricane 33 configuring 33 implementation 36 interrupts 41 register set 34 ID register 55 Spectrum Signal Processing identifying processor the software is running on 55 IDSEL line 36 INT4 interrupt identify source 47 interface DSP LINK3
46. ionai A Row Signal B Row Signal Row Sigal ORow Sat o ew mam e aas oma Te ew mar e oar aa o ore mam me Damm en 66 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing 11 2 PMC Connectors Part Number 500 00191 Revision 2 00 Monaco Technical Reference Connector Pinouts The PMC Connectors use a standard CMC style 1mm pitch SMT connector Table 19 PMC Connector JN Pinout ene Sonat Pme E mor 7 INTI ee sor iso ew o oo LE 67 Monaco Technical Reference Connector Pinouts 68 Table 20 PMC Connector JN2 moss ei a al ae o e Spectrum Signal Processing Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Connector Pinouts Table 21 PMC Connector JN4 Part Number 500 00191 69 Revision 2 00 Monaco Technical Reference Connector Pinouts 70 Table 22 Non standard PMC Connector JN5 ene Sonat Pme son DE ama o amo DE ee fe aw o a o aa Spectrum Signal Processing Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Connector Pinouts 11 3 PEM Connectors Both PEM connectors use 60 pin 0 8mm pitch SMT connectors PEM CONI is the closest to the front panel Table 23 PEM 1 Connector Pinout ae remos eo Fao a awe Le omw Ds w o Lan Part Number 500 00191 71 Revision 2 00 Monaco Tec
47. iting 10h to the VSTATUS register All other interrupts are cleared when the source of the interrupt is cleared This interrupt is cleared on reset Status of the interrupt vector last received on the data bus High if the vector was not valid During the IACK cycle a non vectored interrupt source causes this bit to be set denoting a non valid vector value on the bus This bit is cleared on reset The next SCV64 register IACK or VMEOUT cycle updates KAVEC This signal is active high The interrupt level of pending interrupts in the SCV64 These signals are active low For example a value of 0x0 indicates that interrupt level 7 is pending Part Number 500 00191 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Registers VINTA Register Address 016D 8004h D31 D8 Reserved D7 D1 This register allows any processor to generate or clear an interrupt to node A Upon reset this value is 0 e To generate an interrupt to node A set bit DO of this register to 1 e To clear an interrupt to node A set bit DO of this register to 0 Part Number 500 00191 49 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Registers VINTB Register Address 016D 8008h D31 D8 Reserved D7 Di This register allows any processor to generate or clear an interrupt to node B Upon reset this value is 0 e To generate an interrupt to node B set bit DO of this
48. ly bank 0 is used to access the Global Shared Bus All other Hurricane DSP banks are unused There are two devices on the PMC site s PCI bus the Hurricane chip and the PMC device The IDSEL line from each of the two PCI devices is connected to the following Address Data lines PCI Device IDSEL Connection Hurricane AD16 PMC Module AD17 36 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference JTAG Debugging 7 JTAG Debugging Part Number 500 00191 Revision 2 00 The Monaco board supports JTAG in circuit emulation from a built in 74ACT8990 Test Bus Controller The 74ACT8990 Test Bus Controller permits the VME interface to operate the JTAG chain There are also two JTAG connectors for an XDS510 or White Mountain debugger JTAG IN J1 and JTAG OUT J2 which can route the JTAG chain off board JTAG in circuit emulation is fed to the Test Bus Controller from the VME A24 secondary interface C source debugging using an emulator board running a debug monitor on an adjacent computer is supported through the JTAG IN connector If a JTAG IN connection with a clock signal is present the Test Bus Controller is automatically disconnected JTAG data lines are routed to each available C6x node The full JTAG chain is shown in the following diagram Unpopulated processor nodes are bypassed TDO TDO Node D JTAG OUT C6x
49. n cable connector The interface supports up to 4 slave DSP LINK3 devices The ribbon cable can be up to 12 inches 30 cm long The DSP LINK3 interface is accessed from node A s local bus only it is not accessible from any other node nor from the VME bus Accesses to the DSP LINK3 interface do not require the Global Shared Bus As a result DSP LINK3 accesses can happen concurrently with Global Shared Bus access by other devices such as the other processors or the SCV64 chip If a DSP LINK3 access is interleaved within global shared SRAM accesses node A acquires the Global Shared Bus performs the SRAM access releases the Global Shared Bus performs the DSP LINK3 access acquires the Global Shared Bus and then performs the next Global Shared Bus SRAM access using a control register 5 1 DSP LINK3 Data Transfer Operating Modes The Monaco board supports four data transfer operating modes e Standard Access e Standard Fast Access e Address Strobe Control e Ready Control Access The three access data transfer operating modes Standard Standard Fast and Ready Control of the DSP LINK3 interface use three 64K address spaces accessed from node A Each of the three access modes is assigned its own 64K memory space Address Strobe Control cycles are multiplexed with the Standard Fast Access mode space The following table shows how the DSP LINK3 data transfer operating modes are supported Part Number 500 00191 29 Revisi
50. nfigured by SCV64 initialization routine Dynamically configured by SCV64 initialization routine Dynamically configured by SCV64 initialization routine Dynamically configured by SCV64 initialization routine Not used Not used Not used Not used Reserved 016E 01FCh 76 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Index Part Number 500 00191 Revision 2 00 A A24 slave interface reset 5 arbitration global shared bus 19 Auto Syscon capability 27 backplane connectors VME bus 23 base address VME A24 slave interface setting via jumpers 7 block diagram 4 processor node 10 board layout diagram 6 boot mode setting via jumpers 7 boot source of DSP setting 16 booting DSP 16 burst cycle global shared bus access 20 bus global shared See global shared bus VME backplane connectors 23 interface 23 SCV64 VME64 master 27 primary slave 23 secondary slave 24 operation 23 bus error interrupts 43 C C6x See DSP CEI external memory space 14 chain JTAG 37 clear interrupt to node A 49 to node B 50 to node C 51 to node D 52 clock speed 1 Monaco Technical Reference SCV64 Register Values configurations DSP processor 9 configuring Hurricane 33 connector 63 JTAG 73 IN 73 OUT 73 layout 63 PEM 71 PEM 1 71 PEM 2 72 PMC 67 JN1 67 JN2 68 JN4 69 INS 70 VME P1 64 P2 DSP LINK3 to VME 66 PMC to VME 65 D data throughput specif
51. ng bit DO of the VME A24 Control Register to 0 All devices and registers on the Monaco board are reset to their default conditions except for the SCV64 VME interface chip The VME A24 Control Register is located at VME A24 Base Address 1004h The base address for the VME A24 slave interface is set by jumper block JP1 1 6 3 JTAG Reset The JTAG path can be reset by asserting the TRST line of the JTAG chain by an EMURST from the XDS or TBC Only the JTAG path of the DSPs is reset by this action no other devices or registers on the board are affected Monaco Technical Reference Introduction 1 7 Board Layout Spectrum Signal Processing The following diagram shows the board layout of the Monaco board JP10 JP9 JP8 J 1 JTAG IN Connector JTAG OUT Connector Figure 2 Board Layout JP4 JP5 PEM Site Nodes C and D PEM Site Nodes A and B PMC Site J8 DSP LINK3 Ribbon Cable Connector Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Introduction 1 8 Jumper settings Table 2 Jumper Settings JP1 Pins 1 2 VME A24 slave interface base address bit A23 JP1 Pins 3 4 VME A24 slave interface base address bit A22 JP1 Pins 5 6 VME A24 slave interface base address bit A21 JP1 Pins 7 8 VME A24 slave interface base address bit A20 JP1
52. o determine the state of the HINT lines from each processor node Each bit corresponds to one of the four processor nodes The state of the bit is simply a reflection of the HINT bit value in the corresponding Cox HPIC register A 1 in the bit position indicates that the corresponding C6x processor has requested an interrupt HINT_A Bit DO is set to 1 when node A is requesting a host interrupt HINT_B Bit D1 is set to 1 when node B is requesting a host interrupt HINT_C Bit D2 is set to 1 when node C is requesting a host interrupt HINT_D Bit D3 is set to 1 when node D is requesting a host interrupt This read only register is accessed from the VME A24 bus It is located at offset 1000h from the base address set by jumper JP1 A23 A17 56 Part Number 500 00191 Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Registers VME A24 Control Register VME A24 Secondary Base Address 1004h D31 D8 Reserved The VME host uses this register to reset all Monaco board devices except for the SCV64 bus interface chip e To reset the board the VME host writes a 0 to bit DO This read write register is accessed from the VME A24 bus It is located at offset 1004h from the base address set by jumper JP1 A23 A17 Part Number 500 00191 57 Revision 2 00 Monaco Technical Reference Registers 58 Spectrum Signal Processing Part Number 500 00191 Revision 2 00 Spectrum Sign
53. ocessor e The Test Bus Controller TBC for JTAG debugging operation e Control and Status registers of the Monaco board D16 and DO8EO accesses are not supported on the slave A24 secondary interface Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Part Number 500 00191 Revision 2 00 VME64 Bus Interface VME Offset Address 00 0000h Test Bus Controller Registers JTAG 00 OFFFh 00 1000h VME A24 Status Register Read Only FPGA 00 1003h 00 1004h VME A24 Control Register Read Write 00 1007h 00 1008h Reserved 00 1FFFh 00 2000h Node A HPI Registers 00 2FFFh 00 3000h Node B HPI Registers 00 3FFFh C6x 00 4000h Node C HPI Registers 00 4FFFh 00 5000h Node D HPI Registers 00 5FFFh 00 6000h Reserved 00 FFFFh 01 0000h Node A HPID DMA Space HPIA incremented 16KB all addresses mapped to 00 2008h 01 3FFCh 01 4000h Node B HPID DMA Space HPIA incremented 16KB all addresses mapped to 00 3008h 01 3FFCh C6x 01 BOOOh Node C HPID DMA Space HPIA incremented 16 KB all addresses mapped to 00 4008h 01 3FFCh 01 C000h Node D HPID DMA Space HPIA incremented 16 KB all addresses mapped to 00 5008h 01 FFFCh Figure 9 A24 Secondary Interface Memory Map Refer to the JTAG Debugging chapter for information on using the Test Bus Controller for JTAG operation The VME A24 Status Register and the VME A24 Control Register are described in the Registers chapter 25 Monaco
54. on 2 00 Monaco Technical Reference DSP LINK3 Interface Spectrum Signal Processing Table 10 DSP LINK3 Data Transfer Operating Modes Base Address Standard 0160 0000h Access 0164 0000h 0164 0000h 0168 0000h 5 2 ASTRB_EN Bit x Address Strobe Control Mode Description For slave boards that are similar to DSP LINK1 slave boards and operate with a fixed access time For DSP LINK slave boards that have fast fixed access time This memory space is shared with the Address Strobe Control operating mode For slave boards that require more than the 16 KWords of addressing provided by the standard DSP LINK3 address lines The bus master uses the ASTRB cycle to place the page address onto the DSP LINK3 data lines It determines which address page is accessed on the slave board This allows access to up to 2 address pages with each address page having an address depth of 2 The ASTRB Cycle has the same timing as the Standard Fast transfer cycle For DSP LINK3 slave boards that require variable length access times DSTRB is active until the slave asserts the DSP LINK3 ready signal RDY to end the cycle The Address Strobe Control mode uses the same node A 64K address space as the Standard Fast Access mode The Address Strobe Control mode is enabled for this space by setting bit D1 the ASTRB_EN bit of the DSP LINK3 register to 1 This register is located at address 016D 8018h of node A Standard
55. onnector JN 69 Table 22 Non standard PMC Connector INS 70 Table 23 PEM 1 Connector Pinout nn nnnnnn nn e nn rn naar nn TEA 71 Table 24 PEM 2 Connector PinOut nn nn nano nn rn naar aair e ai 72 Table 25 JTAG IN Connector Piot 73 Table 26 JTAG OUT Connector uunsessnsesnensnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnsnnnnnnn 73 Table 27 SCV64 Register Initialization nn 75 Part Number 500 00191 xi Revision 2 00 Monaco Technical Reference Spectrum Signal Processing Table of Contents xii Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Introduction 1 Introduction 1 1 Features Part Number 500 00191 Revision 2 00 This manual describes the features architecture and specifications of the Monaco Quad C6x VME64 Board You can use this information to program the board at a driver level extend the standard hardware functionality or develop custom configurations Spectrum s Monaco VME64 board consists of four TMS320C6x processing nodes It is available with either fixed point or floating point TMS320C6x processors Product Operation Processors Processor Clock Speed Monaco Fixed point TMS320C6201 200 MHz Monaco67 Floating point TMS320C6701 167 MHz Both the Monaco and the Monaco67 are referred to as Monaco in this manual unless otherwise noted Monaco has the following features e Up to four TMS320C6201 or TMS320C6701 processing nodes e 128K x 3
56. s 12 Volts 12 Volts Hen 60 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Specifications 10 3 Performance and Data Throughput The following table gives the data transfer rates between different memory processor and interface resources on the Monaco board Monaco boards using the TMS320C6201 processor have a clock speed of 200 MHz Monaco67 boards using the TMS230C6701 processor have a clock speed of 167 MHz Table 15 Data Access Transfer Performance clock Spoed Units Target 200 167 MHz Comment ova Soran E TT feemste EC TT oam o CS egen Ho fu TT osP unka standard Lal esp o ESET a ap o can Rages us e TT VMEbus master read 2 MB s Coupled read Typical value for a real slave which is slower than for an ideal VME slave VMEbus master write MB s De coupled write Typical value for a real slave which is slower than for an ideal VME slave HPI read 14 MB s Maximum speed Se internal C6x memory when the C6x is not accessing memory HPI write 28 MB s Maximum speed to internal C6x memory when the C6x is not accessing memory hwer ton SSCS Pe man LI MAC CN mea Joen w TT Part Number 500 00191 61 Revision 2 00 Monaco Technical Reference Specifications 62 Spectrum Signal Processing Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Connector Pinouts
57. s e Setting this bit D1 to 0 disables ASTRB accesses to DSP LINK3 Accesses to the standard fast region when ASTRB_EN is cleared will be DSTRB accesses Set to 0 upon reset This read write register is not accessible from nodes B C or D 54 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference ID Register Registers Part Number 500 00191 Revision 2 00 Address 016D 801Ch D31 D8 Reserved This register allows DSP software to identify which processor it is running on Each of the four bits in the register correspond to a particular processor node A node can read the status of all four bits but can only write to its own bit To identify its processor the DSP program first locks the Global Shared Bus for its use by asserting TOUTO It then reads the value of this register and stores the result This value is toggled inverted and written back to the register The register is read once again and compared to the first reading to determine which bit was changed by the write operation Because only the bit corresponding to the node can be changed this bit will identify the node that the application is running on TOUTO should then be de asserted to release the Global Shared Bus Monaco Technical Reference Spectrum Signal Processing Registers VME A24 Status Register VME A24 Secondary Base Address 1000h D31 D8 Reserved The VME host reads this register t
58. s Space VME Address Space VME base address set by VPAGE register VME base address set by VPAGE register DSP as VME Master R W DSP as VME Master R W 017F FFFC Figure 5 DSP Memory Map for External Memory Space CE1 14 Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference 2 2 2 3 2 4 2 5 2 6 Part Number 500 00191 Revision 2 00 Processor Nodes Synchronous Burst SRAM The board provides 128K of 32 bit synchronous burst SRAM SBSRAM on each C6x local bus The Monaco board supports 1 wait state operation Synchronous DRAM The board provides 4M of 32 bit synchronous DRAM on each Cox bus The Monaco board supports 1 wait state operation An additional 4M of 32 bit synchronous DRAM per DSP can also be supported on a PEM module Burst data transfer rates from CPU to SDRAM are 400 Mbytes s on a Monaco with 200 MHz TMS320C6201 chips Processor Expansion Module The Processor Expansion Module PEM provides a simple and flexible interface from the DSP to VO It is similar to a PMC module although physically narrower The Monaco board is designed to support two DSPs per PEM site with a pair of connectors for each DSP While both DSP devices share the same PEM the two DSP buses are kept separate to allow very fast PEM data transfer rates The PEM is capable of booting the DSPs from local ROM with up to 4 MBytes of addressable boot space available to each DSP Refer to the
59. s a VME chassis 6U with power supply The board automatically becomes VMEbus system controller Syscon if it resides at the top of the VMEbus grant daisy chain This capability is provided by the Tundra SCV64 interface chip Refer to the SCV64 User Manual for details The Monaco board has two VME backplane connectors a 3 row P1 connector and a 5 row P2 connector The board may be installed in either a 5 row VME backplane or a 3 row backplane The two additional rows on the VME P2 connector Z and D only serve to route serial port signals from DSP processor nodes A B C and D to the VME backplane if the board is configured for that option Note If the Monaco board is installed in a 3 row VME chassis serial port routing will be restricted to the PEM and PMC sites only 4 2 SCV64 Primary Slave A32 A24 Interface The primary interface to the VME64 bus is based on Tundra Semiconductor Corporation s SCV64 VME64 Interface chip This chip enables the Monaco board to act as a master or a slave on the VME64 bus and also provides VME interrupt capabilities Transfer rates of 40 MBytes sec are supported between the SCV64 and the Global Shared Bus SRAM once the bus has been acquired The SCV64 cannot be pre empted from the Global Shared Bus and it does not have a bus ownership timer A host on the VME64 bus can access both the lower half 1 Mbyte of Global SRAM and the Hurricane control registers on a Monaco board in either A24 or A32 addressin
60. s are configured as rising edge triggered interrupts The NMI interrupts for the Cox DSPs are not used they are tied high The following block diagram shows how interrupts are routed to these pins on the Monaco board 39 Monaco Technical Reference Spectrum Signal Processing Interrupt Handling KIPL D Enable SCV64 Interrupt e N VME Interrupt BUSERR_D VINTD F PCI Interrupt PEM INT1 D PEM INT2 9 Hurricane VME BUSERR_C nterrupt E 4 PCI Interrupt PEM INT1 e PEM INT2 Q Hurricane KIPL B Enable VME Interrupt BUSERR_B E 4 PCI Interrupt PEM INT1 gt PEM INT2 9 Hurricane KIPL A Enable VME Interrupt BUSERR_A VINTA F PCI Interrupt i Hurricane Hurricane A PEM INT1 gt INTA De Bounce Logic q PEM INT2 o PCI Bus INTB Interrupts INTC INTD INTO Note DSP LINK3 Nri C6x i Interface De Bounce Logic x interrupts Interrupts INT are rising edge INT3 triggered Figure 12 Interrupt Routing 8 2 DSP LINK3 Interrupts to Node A The four active low interrupts from the DSP LINK3 interface are logically OR ed and routed to the INT7 interrupt input of the node A C6x The open collector signals are de bounced The interrupts are not latched on the Monaco board and must be cleared on the DSP LINK3 board that generated them 40 Part Number 500 00191 Revision 2 0
61. s scheme allocates time to them fairly so that none are locked out Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Global Shared Bus Although this is a non prioritized scheme the back off function of the SCV64 interface resolves collisions between a bus master and the VMEbus if there is contention for the VMEbus Note There are no ownership timers for the Hurricane or SCV64 If the Hurricane holds the bus too long the VME bus could timeout 3 2 3 Locked Cycles A C6x can lock the Global Shared Bus in order to perform Read Modify Write RMW or other atomic accesses to it by driving its Timer 0 TOUTO low After the TOUTO is driven low the next access to the Global Shared Bus acquires the bus The bus is not released until the C6x drives the Timer 0 TOUTO pin high Caution The capability of locking the Global Shared Bus from a C6x should be used carefully because other devices will not acquire the bus once it is locked This capability is intended for read modify write accesses to the Global Shared RAM and registers It is highly recommended that Bus locking not be used It can lead to a deadlock condition and in particular result in debugger timeouts The following precautions should be observed when locking the Global Shared Bus 1 VME bus timeouts can occur because the SC V64 cannot access the board while a C6x has locked the bus 2 If node A accesses the DSP L
62. ther processor through the VINTx registers There are four of these registers one for each of the processors To generate an interrupt to a particular processor a 1 is written to bit DO of the VINT register corresponding to the processor to be interrupted These registers are accessible from any of the four processors Node C for example can interrupt node B by writing 1 to the VINTB Register address 016D 8008h The VSTATUS Register address 016D 8000h also indicates that a node has a pending interrupt whenever any of the following bits is set to 1 Bit Interrupted Node D8 Node A D9 Node B D10 Node C D11 Node D A processor clears an interrupt by clearing its corresponding bit VINT x register In the case where node C interrupts node B for example node B would clear the interrupt by writing 0 to the VINTB Register address 016D 8008h VME Host Interrupts To Any Node A VME host can interrupt a particular node on the Monaco board using DSPINT in the HPIC register of the Host Port Interface HPI Refer to the TMS320C6x documentation for further information on using DSPINT Part Number 500 00191 Revision 2 00 Spectrum Signal Processing Monaco Technical Reference Registers 9 Registers Part Number 500 00191 Revision 2 00 This section provides a reference to the registers that are unique to the Monaco board Information for the registers within the SCV64 bus interface chip the ACT8990 Test B
63. us Controller TBC and the Hurricane PCI interface chip can be found in their respective data sheets Most of the registers described in this section are accessed from the processor nodes Of these most are shared among nodes A B C and D A few though are unique to each node The registers that are not accessible from the processor nodes are part of the VME A24 Host Port Interfaces and to the TBC The following table summarizes the registers described in this section Table 13 Register Address Summary Access Register VPAGE Register for node A VPAGE Register for node B VPAGE Register for node C VPAGE Register for node D VSTATUS Register VINTA Register VINTB Register VINTC Register VINTD Register KIPL_EN Register DSP LINK3 Register ID Register VME A24 Status Register VME A24 Control Register Privilege R W R W R W R W Read Only VME A24 slave interface VME A24 slave interface R W Bus Node A only Node B only Node C only Node D only All nodes All nodes All nodes All nodes All nodes All nodes Node A only All nodes A processor can only write its own bit within this register Address 016D 0000h 016D 0000h 016D 0000h 016D 0000h 016D 8000h 016D 8004h 016D 8008h 016D 800Ch 016D 8010h 016D 8014h 016D 8018h 016D 801Ch base 1000h base 1004h 45 Monaco Technical Reference Registers Spectrum Signal Processing VPAGE Register 46 Address 016D 00
64. when another processor has set the VINTB interrupt register Active High Status of the user defined interrupt to node A Set to 1 when another processor has set the VINTA interrupt register Active High Status of the last bus cycle access made to the SCV64 by node D including SCV64 register and VME master accesses Set to 1 if there was an error Cleared by writing 80h to the VSTATUS register All other interrupts are cleared when the source of the interrupt is cleared This interrupt is cleared on reset Status of the last bus cycle access made to the SCV64 by node C including SCV64 register and VME master accesses Set to 1 if there was an error Cleared by writing 40h to the VSTATUS register All other interrupts are cleared when the source of the interrupt is cleared This interrupt is cleared on reset Status of the last bus cycle access made to the SC V64 by node B including SCV64 register and VME master accesses Set to 1 if there was an error Cleared by writing 20h to the VSTATUS register All other interrupts are cleared when the source of the interrupt is cleared This interrupt is cleared 47 Monaco Technical Reference Registers 48 BUSERRA KAVEC KIPL2 0 Spectrum Signal Processing on reset Status of the last bus cycle access made to the SC V64 by node A including SCV64 register and VME master accesses Set to 1 if there was an error Cleared by wr

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