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Samsung KS57C2308 User's Manual

1. meo s 2 o ves Ye s s 2 o Ye Ye s re Pore s 2 o nw ve Ye s s ve ve No Locations FF8H FFFH not mapped NOTES 1 the WMOD register is read only 2 U means that the value is unknown 3 The carry flag can be read or written by specific bit manipulation instructions only REGISTER DESCRIPTIONS In this section register descriptions are presented in a consistent format to familiarize you with the memory mapped I O locations in bank 15 of the RAM Figure 4 1 describes the features of the register description format Register descriptions are arranged in alphabetical order Programmers can use this section as a quick reference source when writing application programs Counter registers buffer registers and reference registers as well as the stack pointer and port I O latches are not included in these descriptions More detailed information about how these registers are used is included in Part Il of this manual Hardware Descriptions in the context of the corresponding peripheral hardware module descriptions 4 4 ELECTRONICS 557 2308 2308 2316 2316 MEMORY Register and bit IDs Name of individual used for bit addressing bit or related bits Associated Register location Register ID Register name hardware module in RAM bank 15 Output Mode Con
2. A lt a ACT P1 3 TCLo H 27 P2 2 CLO 30 P2 3 BUZ 31 P3 0 LCDCK 32 P3 1 SCDSY O 33 P1 1 INT1 25 P1 2 INT2 H 26 P2 0 TCLOO 28 NOTE The bold pins are used for OTP write Figure 16 1 KS57P2308 P2316 Pin Assignments 80 QFP 16 2 ELECTRONICS 557 2308 2308 2316 2316 557 2308 2316 Table 16 1 Pin Descriptions Used to Read Write the EPROM Main Chip During Programming Serial data pin Output port when reading and input port when writing can be assigned as Input push pull output port respectively TEST Vpp TEST 1 Power supply pin for EPROM cell writing indicates that OTP enters into the writing mode When 12 5 V is applied OTP is in writing mode and when 5 V is applied OTP is in reading mode Option RESET RESET 9 Chip initialization Vpp Vpp Vss 12 13 Logic power supply Vpp should be tied to 5 V during programming Table 16 2 Comparison of KS57P2308 P2316 and KS57C2308 C2316 Features OPERATING MODE CHARACTERISTICS When 12 5 V is supplied to the Vpp TEST pin of the KS57P2308 P2316 the EPROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 16 3 below Table 16 3 Operating Mode Selection Criteria Address R w A15 A0 0000H EPROM read EPROM program 1
3. 1 M Beim j Examples 1 The extended accumulator contains the value register pair HL the value OAAH and the carry flag is set to 1 SCF lt SBC EA OAAH 1H lt 0 JPS XXX Jump to XXX no skip after SBC 2 If the extended accumulator contains the value register pair HL the value OAAH and the carry flag is cleared to 0 RCF C lt SBC EAHL EA lt 0C3H OAAH 19H lt 0 JPS XXX Jump to XXX no skip after SBC 5 80 ELECTRONICS 557 2308 2308 2316 2316 SBC Subtract With Carry SBC Continued SAM47 INSTRUCTION SET Examples 3 If SBC A HL is followed by an ADS the SBC skips on no borrow to the instruction immediately after the ADS An ADS A im instruction immediately after the SBC A HL instruction does not skip even if an overflow occurs This function is useful for decimal adjustment operations a 8 6 decimal addition the contents of the address specified by the HL register is 6H RCF LD SBC ADS JPS A 8H A HL A 0AH XXX 5 C e 0 A 8H A lt 8H 6H C 0 2 2H C 0 Skip this instruction because no borrow after SBC result b 3 4 decimal addition the contents of the address specified by the HL register is 4H RCF LD SBC ADS JPS ELECTRONIC
4. A 6H A HL A 0AH XXX 0 A lt 3H lt 3H 6H 9H A lt 9H 4H 0 No skip lt 7 The skip function for ADS is inhibited after an ADC A HL instruction even if an overflow occurs 5 25 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 ADS aad And Skip Overflow ADS dst src Add 4 bit immediate data to A and skip on overflow Add 8 bit immediate data to EA and skip on overflow A HL Add indirect data memory to A and skip on overflow EA RR Add register pair RR contents to EA and skip on 2 2 5 overflow RRb EA Add EA to register pair RRb and skip on overflow Description The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected If there is an overflow from the most significant bit of the result the skip signal is generated and a skip is executed but the carry flag value is unaffected If ADS follows an ADC A HL instruction in a program ADC skips the ADS instruction if an overflow occurs If there is no overflow the ADS instruction is executed normally This skip condition is valid only for ADC A HL instructions however an overflow occurs following an ADS instruction the next instruction is not skipped ___ a at so ACA rim skip onoveriow _ EA imm
5. Bits 0 3 of the display RAM are synchronized with the common signal output pins COMO 1 2 and COM3 When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal is sent to the corresponding segment pin Each bias has select and no select signals Table 12 7 Select No Select Signals for LCD Static Display Mode SG Select _ Noselct 0 0 SELECT NO SELECT T LCDCK Figure 12 8 Select No select Bias Signals in Static Display Mode ELECTRONICS 12 11 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 Table 12 8 Select No Select Signals for LCD 1 2 Bias Display Mode SELECT NO SELECT T LCDCK Figure 12 9 Select No select Bias Signals in 1 2 Bias Display Mode 12 12 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER Table 12 9 Select No Select Signals for LCD 1 3 Bias Display Mode SELECT NO SELECT T LCDCK Figure 12 10 Select No select Bias Signals in 1 3 Bias Display Mode ELECTRONICS 12 13 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 Figure 12 11 LCD Signal Waveforms in Static Mode 12 14 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER COM3 Timing COM2 Open Strobe COM1 Possible COMO EM Ee ee ESEXETES E ESSE OCELE E ACEP a ESE ES ee
6. lt EA skip on overflow ds a4 at o aeu o i i i i 4 AcAs Hijskip on overiow AS m __ 1 1 0 1 1 1 o RRb lt RRb skip on overflow 1 extended accumulator contains the value register pair HL the value OAAH and the carry flag 0 ADS EA HL EA lt 6DH ADS skips on overflow but carry flag value is not affected JPS This instruction is skipped since ADS had an overflow JPS YYY Jump to YYY 5 26 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET ADS Add And Skip On Overflow ADS Continued Examples 2 If the extended accumulator contains the value register pair HL the value 12H and the carry flag 0 ADS EAHL EA lt 12H 0D5H JPS Jump to XXX no skip after ADS If ADC A HL is followed by an ADS the ADC skips on overflow to the instruction immediately after the ADS An ADS A im instruction immediately after the ADC A HL does not skip even if overflow occurs This function is useful for decimal adjustment operations 8 9 decimal addition the contents of the address specified by the HL register is 9H RCF C lt 0 LD A 8H 8H ADS A 6H lt 8H 6H 0EH ADC A 9 0
7. N Lese ee i PES ES ES eo eer TA Led ee lt EE N NE s m OHER um DEARER m ACLARE m Le X sas ESETESE S agro ESSET gt gt pe x pe x x gt gt 0 X Figure 12 12 LCD Connection Example in Static Mode ELECTRONICS 12 15 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 2 Vss cD 0 1 2 V CD VLCD VLcp 0 1 2V LCD Figure 12 13 LCD Signal Waveforms at 1 2 Duty 1 2 Bias 12 16 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER Timing Strobe CEEE we we se _ CEEE Bs seen ses er sow ses _ sen son EM EIE seem ser sem epe ALBAE Figure 12 14 LCD Connection Example at 1 2 Duty 1 2 Bias ELECTRONICS 12 17 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 VICO Vic1 2 Vss Vi co 2 Vss
8. Device Number KS57C2308 write down the ROM code number Attachment Check one Diskette PROM Customer Checksum Company Name Signature Engineer Please answer the following questions Application Product Model ID Audio Video Telecom LCD Databank Caller ID LCD Game Industrials Home Appliance Office Automation Remocon Other Please describe detail its application For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book 557 2316 Device Number 557 2316 write down the ROM code number Attachment Check one Diskette PROM Customer Checksum Company Name Signature Engineer Please answer the following questions Application Product Model ID Audio Video Telecom LCD Databank Caller ID LCD Game Industrials Home Appliance Office Automation Remocon Other Please describe in detail its application For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book 557 SERIES OTP FACTORY WRITING ORDER FORM 1 2 Product Descript
9. Duty and Bias Selection for LCD Display o toD display ott o o 14au 13bas __ oueduyt2bas 11 18 auty 12bias __ 0 0 o 4 19 MEMORY 557 2308 2308 2316 2316 PCON Power Control Register FB3H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write Bit Addressing 4 4 4 4 3 2 CPU Operating Mode Control Bits Enable normal CPU operating mode 0 1 Initiate idle power down mode 1 Initiate stop power down mode 1 0 CPU Clock Frequency Selection Bits o 0 if SCMOD 0 0 fx 64 if SCMOD 0 1 fxt 4 1 if SCMOD 0 0 fx 8 if SCMOD 0 1 fxt 4 If SCMOD 0 0 fx 4 if SCMOD 0 1 fxt 4 NOTE fx is the main system clock fxt is the subsystem clock 4 20 ELECTRONICS 557 2308 2308 2316 2316 MEMORY PMG1 Port 0 Mode Flags Group 1 Port 3 and 6 FE8H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W W Bit Addressing 8 8 8 8 8 8 8 8 PM6 3 P6 3 Mode selection Set P6 3 to input mode Set P6 3 to output mode 6 2 P6 2 I O Mode Selection Set P6 2 to input mode 1 Set P6 2 to output mode PM6 1 P6 1 I O Mode Selection Set P6 1 to input mode Set P6 1 to output mode PM6 0 P6 0 I O Mode Selection Flag
10. 0 BITR EMB LD H 0AH 5 If bank 0 AH 0 0AOH O 0 then skip RET 5 38 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET BIST Bit Test and Skip on True BTST dst b Fest carey it and sip se 1 0 ves DA b Test specified bit and skip if memory bit is set memas 2 s mmbGL _____ 2 aes omas ise amis Description specified bit within the destination operand is tested If it is 1 the instruction that immediately follows the BTST instruction is skipped otherwise the instruction following the BTST instruction is executed The destination bit value is not affected operand Operation Notation o i ms Far as as as uz at ao wu Ee EE Te me Elda 1 Skip if memb 7 2 L 3 2 L 1 0 1 pisei 0000000 roto for foe faa fae Second Byte Bit Addresses memab 1 0 bt bo a2 at ao _______ 22 al FroHFFFH _________ Examples 1 If RAM bit location 30H 2 is set to 0 the following instruction sequence will execute the RET instruction BTST 30H 2 If 30H 2 1 then skip RET If 30H 2 0 return JP LABEL2 ELECTRONICS 5 39 SAM47 INSTRUCTION SET 557 2308 2
11. or Vss levels in order to check the current input option Reason If the input level of a port pin is set to when a pull up resistor is enabled it will draw unnecessarily large current Disable the pull up resistors of input pins connected to the external device by making the necessary modifications to the PUMOD register Configure the output pins that are connected to the external device to low level Reason When the external device s Vpp source is turned off and if the microcontroller s output pins set to high level 0 7 V 15 supplied to the Vpp of the external device through its input pin This causes the device to operate at the level Vpp 0 7 V In this case total current consumption would not be reduced Determine the correct output pin state necessary to block current pass in according with the external transistors PNP NPN ELECTRONICS 557 2308 2308 2316 2316 POWER DOWN RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption please configure unused pins according to the guidelines described in Table 8 2 Table 8 2 Unused Pin Connections for Reducing Power Consumption Pin Share Pin Names Recommended Connection P0 0 INT4 Input mode Connect to Vpp 1 Output mode No connection 0 2 50 P0 3 Sl P1 0 INTO Connect to Vpp 1 P1 1 INT1 P1 2 INT2 P1 3 TCLO P2 0 TCLOO Input mode Connect to Vpp P2 1 Output mode No connection P2 2 CLO P2
12. 1 1 SP 1 SP 2 lt EMB ERB ARA 1 1 0 31 1 0 1 I 1 12 11 ato SP 3 SP 4 PC7 0 SP 5 SP 6 PC13 8 SP lt SP 6 The stack pointer value is 00H and the label PLAY is assigned to program memory location OESFH Executing the instruction CALL PLAY at location 0123H will generate the following values SP OFFH OH OFEH EMB ERB OFDH 2H OFCH 6H OH 1H PC Data is written to stack locations as follows ELECTRONICS 5 45 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 CALLS Call Procedure Short CALLS dst Description Example 5 46 ADR11 Call direct in page 11 bits The CALLS instruction unconditionally calls a subroutine located at the indicated address The instruction increments the PC twice to obtain the address of the following instruction Then it pushes the result onto the stack decreasing the stack pointer six times The higher bits of the PC with the exception of the lower 11 bits are cleared The subroutine call must therefore be located within the 2 Kbyte block 0000 07 of program memory ADR11 11211011 1 alo SP 1 SP 2 EMB ERB SP 3 SP 4 PC7 0 SP 5 SP 6 10 8 a5 a4 a2 PC13 11 00 PC10 0 ADR10 0 SP SP 6 The stack pointer value is 00H and the label PLAY is assigned t
13. I PROGRAMMING TIP Initializing the Stack Pointer To initialize the stack pointer SP 1 When EMB 1 SMB 15 Select memory bank 15 LD EA 00H Bit 0 of SP is always cleared to 0 LD SP EA Stack area initial address OFFH lt SP 1 2 When EMB 0 LD EA 00H LD SP EA Memory addressing area 00 7 F80H FFFH 2 12 ELECTRONICS 557 2308 2308 2316 2316 ADDRESS SPACES PUSH OPERATIONS Three kinds of push operations reference the stack pointer SP to write data from the source register to the stack PUSH instructions CALL instructions and interrupts In each case the SP is decreased by a number determined by the type of push operation and then points to the next available stack location PUSH Instructions A PUSH instruction references the SP to write two 4 bit data nibbles to the stack Two 4 bit stack addresses are referenced by the stack pointer one for the upper register value and another for the lower register After the PUSH has executed the SP is decreased by two and points to the next available stack location CALL Instructions When a subroutine call is issued the CALL instruction references the SP to write the PC s contents to six 4 bit stack locations Current values for the enable memory bank EMB flag and the enable register bank ERB flag are also pushed to the stack Since six 4 bit stack locations are used per CALL you may nest subroutine calls up to the number of le
14. Od Co IRQS N TRANSMIT COMPLETE _ SET SMOD 3 Figure 13 2 SIO Timing in Transmit Receive Mode HIGH IMPEDANCE IRQS N TRANSMIT COMPLETE SET SMOD 3 Figure 13 3 SIO Timing in Receive Only Mode ELECTRONICS 13 4 557 2308 2308 2316 2316 SERIAL I O INTERFACE SERIAL I O BUFFER REGISTER SBUF The serial I O buffer register SBUF can be read or written using 8 bit RAM control instructions Following a RESET the value of SBUF is undetermined When the serial interface operates in transmit and receive mode SMOD 1 1 transmit data in the SIO buffer register are output to the SO pin 0 2 at the rate of one bit for each falling edge of the SIO clock Receive data are simultaneously input from the SI pin 3 to SBUF at the rate of one bit for each rising edge of the SIO clock When receive only mode is used incoming data are input to the SIO buffer at the rate of one bit for each rising edge of the SIO clock 5 PROGRAMMING Setting Transmit Receive Modes for Serial I O 1 Transmit the data value 48H through the serial I O interface using an internal clock frequency of fxx 24 and in MSB first mode BITS EMB SMB 15 LD 4 LD SBUF EA LD 0 LD SMOD EA SIO data transfer SCK 04 EXTERNAL DEVICE SO P0 2 KS57C2308 C2316 2 Use CPU clock to transfer and receive serial data at high speed BITR EMB LD EA TDATA TDATA address BANKO 20
15. V LCD 1 3 VLCD 0 1 3 V LCD VLCD VLCD 1 3 VLCD 0 VLCD Figure 12 19 LCD Signal Waveforms at 1 4 Duty 1 3 Bias 12 22 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER j lt N Figure 12 20 LCD Connection Example at 1 4 Duty 1 3 Bias ELECTRONICS 12 23 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 NOTES 42 24 ELECTRONICS 557 2308 2308 2316 2316 SERIAL I O INTERFACE SERIAL I O INTERFACE OVERVIEW serial I O interface SIO has the following functional components 8 bit mode register SMOD Clock selector circuit 8 bit buffer register SBUF S bit serial clock counter Using the serial I O interface 8 bit data be exchanged with an external device The transmission frequency is controlled by making the appropriate bit settings to the SMOD register The serial interface can run off an internal or an external clock source or the TOLO signal that is generated by the 8 bit timer counter TCO If the TOLO clock signal is used you can modify its frequency to adjust the serial data transmission rate SERIAL OPERATION SEQUENCE The general operation sequence of the serial I O interface can be summarized as follows Set SIO mode to transmit and receive or to receive only Select MSB first or LSB first transmission mode Set the SCK clock signal in the mode r
16. WDMOD Control Controls Controls watchdog timer operation timer operation 8 8 bit F98H F99H F99H 8 bit write 8 bit write only ASH WDTCF Clear the watchdog timer s counter 1 bit write only o NOTE U means the value is undetermined after a RESET Clear Signal Bits Instruction nterrup Clock Request Selector 1 R W CPU Clock Start Signals By Interrupts RESET Clock Input By 1 pulse period BT input clock 2 1 2 duty Stop Clear Bits NOTE WAIT means stabilization time Instruction after Stabilization time after STOP mode release Figure 11 1 Basic Timer Circuit Diagram ELECTRONICS 11 3 TIMERS TIMER COUNTERS 557 2308 2308 2316 2316 BASIC MODE REGISTER The basic timer mode register BMOD is a 4 bit write only register Bit 3 the basic timer start control bit is also 1 bit addressable All BMOD values are set to logic zero following RESET and interrupt request signal generation is set to the longest interval BT counter operation cannot be stopped BMOD settings have the following effects Restart the basic timer Control the frequency of clock signal input to the basic timer Determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt By loading different values into the BMOD regis
17. i i o CAc eu c s Ee rte tte fete tebe Examples 1 The extended accumulator contains the value register pair HL the value OAAH and the carry flag is set to 1 SCF lt ADC EAHL EA 0C3H 0AAH 1H 6EH C 1 JPS XXX Jump to XXX no skip after ADC 2 If the extended accumulator contains the value 0C3H register pair HL the value OAAH and the carry flag is cleared to 0 RCF lt ADC EAHL EA 6DH C lt 1 JPS XXX Jump to XXX no skip after ADC 5 24 ELECTRONICS 557 2308 2308 2316 2316 ADC aaa with carry ADC Continued SAM47 INSTRUCTION SET Examples 3 If ADC A HL is followed by an ADS A im the ADC skips on carry to the instruction immediately after the ADS An ADS instruction immediately after the ADC does not skip even if an overflow occurs This function is useful for decimal adjustment operations a 8 9 decimal addition the contents of the address specified by the HL register is 9H RCF LD ADS ADC ADS JPS A 8H A 6H A HL A 0AH XXX 0 8H lt 8H 6H OEH lt 9 C 0 7H lt 1 Skip this instruction because 1 after ADC result b 3 4 decimal addition the contents of the address specified by the HL register is 4H RCF LD ADS ADC ADS JPS ELECTRONICS
18. C OR memb 7 2 L 3 2 L 1 0 Popa pote fas fae faa fae rote for fee ao fae fa fo memab 1 0 bt bo a3 a2 at ao FBOH TBFH 1 1 bt bo a2 at ao FFOH FFFH Examples 1 The carry flag is logically ORed with the P1 0 value RCF 0 BOR C P1 0 IfP1 0 1 thenC lt 1 if P1 0 0 then lt 0 2 The P1 address is FF1H and register L contains the value 9H 1001B The address 7 2 is 111100B and L 3 2 10B The resulting address is 11110010 or FF2H specifying P2 The bit value for the BOR instruction L 1 0 is 01B which specifies bit 1 Therefore P1 L P2 1 LD L 9H BOR C P1 L P1 Lis specified as 2 1 OR P2 1 ELECTRONICS 5 35 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 BOR sit Logical or BOR Continued Examples 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 00108 and FLAG 3 0 is 00008 The resulting address is 00100000B or 20H The bit value for BOR instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BOR C H FLAG COR FLAG 20H 3 5 36 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET 5 Bit Test and Skip False BTSF dst b Test specified memory bit and skip if bit equals 0 2 2 5 oman 2 Description specified bit within the destination operand i
19. Samsung reputation Mask Charge US Won Customer Information Company Name Telephone number Signatures Person placing the order Technical Manager For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book KS57 SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK Customer Information Company Name Department Telephone Number Fax Date Risk Order Information Device Number KS57C write down the ROM code number Package Number of Pins Package Type Intended Application Product Model Number Customer Risk Order Agreement We hereby request SEC to produce the above named product in the quantity stated below We believe our risk order product to be in full compliance with all SEC production specifications and to this extent agree to assume responsibility for any and all production risks involved Order Quantity and Delivery Schedule Risk Order Quantity PCS Delivery Schedule Signatures Person Placing the Risk Order SEC Sales Representative For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book 557 2308
20. and RAM locations OEFH through OEDH contain the values 2H 3H and 4H respectively The instruction POP HL leaves the stack pointer set to OEFH and the data pointer pair HL set to 34H 5 72 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET PUSH Push Onto Stack PUSH src SB Push SMB and SRB values onto stack EARE Description The SP is then decreased by two and the contents of the source operand are copied into the RAM location addressed by the stack pointer thereby adding a new element to the top of the stack Operand ee Code Operation Notation r 5 1 lt RRp 5 2 lt RRL SP SP 2 SP 1 SMB SP 2 SRB SP lt 5 2 Example As an interrupt service routine begins the stack pointer contains the value OFAH and the data pointer register pair HL contains the value 20H The instruction PUSH HL leaves the stack pointer set to OF8H and stores the values 2H and in RAM locations OF9H and OF8H respectively ELECTRONICS 5 73 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Reset Carry RCF Description The carry flag is cleared to logic zero regardless of its previous value je Jjiji il o o i i o ceo 2 Example Assuming the carry flag is set to logic one the instruction resets clears the carry flag to logic zero 5 74 ELECTRONICS 557 2308 2308 23
21. 2308 2316 2316 SAM47 INSTRUCTION SET LD Load LD Continued Description RR imm 1 0 2 1 RR DAA 1 1 paca EREEREER pm o ojojojojre n o e 7 1 1 je mmm nm pp pens 1 1 1 HL 1 1 0 0 1 1 0 1 DACADA 1 E a7 a6 a5 4 a2 at a0 REA 1 1 0 14 11 1 0 0 ENENESEXEXEXEEZEN GHLEA 1 1 0 1 1 to 0 1 1 RAM location 30H contains the value The RAM location values are 40H 41H and OAH 3H respectively The following instruction sequence leaves the value 40H in point pair HL OAH in the accumulator and in RAM location 40H and 3H in register E LD HL 30H HL lt 30H LD A HL lt LD HL 40H HL lt 40H LD EA QHL A lt E lt LD HL A RAM 40H lt OAH ELECTRONICS 5 61 SAM47 INSTRUCTION SET LD Load LD Continued 557 2308 2308 2316 2316 Examples 2 If an instruction such as LD A im LD EA imm or LD HL imm is written more than two times in succession only the first LD is executed the next instructions are treated as NOPs Here are two examples of this redundancy effect LD lt 1 LD NOP LD A
22. 2308 2316 2316 SAM47 INSTRUCTION SET RRC Rotate Accumulator Right Through Carry RRC A Description The four bits in the accumulator and the carry flag are together rotated one bit to the right Bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position A 1 1 C A 0 lt A n 1 lt 1 2 3 accumulator contains the value 5H 0101 and the carry flag is cleared to logic zero instruction RRC A leaves the accumulator with the value 2H 0010B and the carry flag set to logic one ELECTRONICS 5 79 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 SBC Subtract With Carry SBC dst src A HL Subtract indirect data memory from A with carry EA RR Subtract register pair RR from EA with carry RRb EA Subtract EA from register pair RRb with carry Description SBC subtracts the source and carry flag value from the destination operand leaving the result in the destination SBC sets the carry flag if a borrow is needed for the most significant bit otherwise it clears the carry flag The contents of the source are unaffected If the carry flag was set before the SBC instruction was executed a borrow was needed for the previous step in multiple precision subtraction In this case the carry bit is subtracted from the destination along with the source operand oporana Binary Gods OpertonNouion
23. ViN VDD leakage All input pins except those specified current below for ILIH2 VIN VDD XIN XOUT XTIN Input low leakage All input pins except XIN XOUT current and XT our 2 0 XTIN and Output high ILOH1 Vout leakage All output pins current Output low Vour 0V leakage All output pins current Pull up RI 1 Ports 0 7 resistor ViN 0 V Vpp 5 V 3 V VIN 0 V Vpp 5 V RESET LCD voltage 25 50 93 140 dividing resistor RL2 Pen impedance output Vpp 5 V Vico voltage mE lo 15uA I 0 3 deviation DS SEG output V Vpp 5 V Vico SEGi voltage lo 15 I 0 31 deviation TORA ELECTRONICS 16 5 557 2308 2316 557 2308 2308 2316 2316 Table 16 5 D C Electrical Characteristics Concluded TA 40 to 85 C TnT 1 8 V to 5 5 V voltage 0 2 0 2 VLC1 Output 25 C 0 4 0 4 0 4 voltage 0 2 0 2 VLC2 Output VLC2 25 C 0 2 Vpp 0 2 0 2 voltage 0 2 a 2 Supply Main operating Current 1 Vpp 5 V 1096 CPU fx 4 SCMOD 000B crystal oscillator C1 C2 22pF Vpp 10 Main Idle mode Vpp 5V 10 CPU fx 4 SCMOD 000B crystal oscillator C1 C2 22pF Vpp 10 003 Sub operating 3V
24. o v Peso e 18 8 Pcro 8 _ S SP 2 lt ERB SP 1 a13 a12 11 a10 5 3 SP 4 PC7 0 SP 5 SP 6 lt PC13 8 a7 a5 a4 a2 al PC13 0 ADR13 0 SP SP 6 CALLS ADR1 1 1 1 1 1 10 1 SP 2 EMB ERB SP 3 SP 4 PC7 0 SP 5 5 6 10 8 a7 a5 a4 a2 al PC13 11 00 PC10 0 ADR10 0 SP SP 6 First Byte Condition eee 1 a ELECTRONICS 5 15 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Table 5 16 Program Control Instructions Binary Code Summary Continued PC13 8 lt SP 1 SP PC7 0 lt SP 2 SP 3 EMB ERB lt SP 5 SP 4 SP SP 6 PC13 8 lt SP 1 SP PC7 0 lt SP 2 SP 3 PSW lt SP 4 SP 5 SP SP 6 PC13 8 lt SP 1 SP 7 0 lt SP 3 SP 2 EMB ERB lt SP 5 SP 4 SP lt SP 6 then skip Table 5 17 Data Transfer Instructions Binary Code Summary XCH 1 1 xm ppm aem EADA 1 1 3 1 E e DA 1 Far ss s Pes Par ESSI Eee ppp p emen E A
25. zas O O 0 bt bo 22 at 40 ee Eee LX dde CmembQL 1 1 1 1 0 C memb 7 3 2 L 1 0 aa c H DA b 1 11 1 3 0 bt 22 at a0 161 22 at FOH FFFH ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET LDB Load Bit LDB Examples Continued 1 The carry flag is set and the data value at input pin P1 0 is logic zero The following instruction clears the carry flag to logic zero LDB C P1 0 The P1 address is FF1H and the L register contains the value 9H 1001B The address memb 7 2 is 111100 and L 3 2 is 108 The resulting address is 11110010B or FF2H P2 is addressed The bit value L 1 0 is specified as 018 bit 1 LD L 49H LDB C P1 L P1 L specifies P2 1 and C P2 1 The H register contains the value 2H and FLAG 20H 3 The address for H is 0010B and for FLAG 3 0 the address 15 00008 The resulting address is 00100000B or 20H The bit value is 3 Therefore H FLAG 20H 3 FLAG EQU 20H33 LD H 2H LDB C H FLAG FLAG 20H 3 The following instruction sequence sets the carry flag and the loads the 1 data value to the output pin P2 0 setting it to output mode SCF Cet LDB 2 0 P20 1 The P1 address is FF1H and L 9H 1001B The a
26. 01000001 in the extended accumulator 5 28 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET BAND Bit Logical And BAND C src b Logical AND carry flag with memory bit CGH DAb Description The specified bit of the source is logically ANDed with the carry flag bit value If the Boolean value of the source bit is a logic zero the carry flag is cleared to 0 otherwise the current carry flag setting is left unaltered The bit value of the source operand is not affected operand Binary Gods Operation Noiaton mna ToT oem ms sa ee C memb L 1 C C AND memb 7 2 L 3 2 L 1 0 5 6 5 s 77 or ao 20 C seora eye ______ _____ memab 1 0 bt 0 22 ao FBOH FBEH 5 22 Examples 1 The following instructions set the carry flag if P1 0 port 1 0 is equal to 1 and assuming the carry flag is already set to 1 SMB 15 Cen BAND C P1 0 If P1 0 1 C e 1 If P1 0 lt 2 Assume P1 address is FF1H and the value for register is 9H 1001B The address memb 7 2 is 1111008 L 3 2 is 108 The resulting address is 11110010 FF2H specifying P2 The bit value for the BAND instruction L 1 0 is 01B which spe
27. 1 to enable TCO Clear TMODO 6 to 0 to select the external clock source at the TCLO pin Select TCLO edge detection for rising or falling signal edges by loading the appropriate values to TMODO 5 and TMODO 4 Table 11 5 TMODO Settings for TCLO Edge Detection TMODO 5 TMODO 4 TCLO Edge Detection 0 Risingedges 0 1 Faling edges 11 14 ELECTRONICS 557 2308 2308 2316 2316 TIMERS TIMER COUNTERS TCO CLOCK FREQUENCY OUTPUT Using timer counter 0 a modifiable clock frequency can be output to the TCO clock output pin TCLOO To select the clock frequency load the appropriate values to the TCO mode register TMODO The clock interval is selected by loading the desired reference value into the reference register TREFO To enable the output to the TCLOO pin the following conditions must be met TCO output enable flag TOEO must be set to 1 mode flag for P2 0 must be set to output mode 1 Output latch value for P2 0 must be set to 0 In summary the operational sequence required to output TCO generated clock signal to the TCLOO pin is as follows Load a reference value to TREFO Set the internal clock frequency in TMODO Initiate TCO clock output to TCLOO TMODO 2 1 Set P2 0 mode flag to 1 Clear P2 0 output latch to 0 Set flag to 1 o Each overflows an interrupt request is generated the state of the output
28. 2316 2316 MEMORY IEW IRQW intw Interrupt Enable Request Flags FBAH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 Always logic zero IEW INTW Interrupt Enable Flag Disable INTW interrupt requests 1 Enable INTW interrupt requests IRQW INTW Interrupt Request Flag Generate INTW interrupt This bit is set when the timer interval is set to 0 5 seconds or 3 91 ms NOTE Since INTW is a quasi interrupt the IRQW flag must be cleared by software ELECTRONICS 4 13 MEMORY 557 2308 2308 2316 2316 IMODO External Interrupt 0 INTO Mode Register FB4H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W Bit Addressing 4 4 4 4 3 Interrupt Sampling Clock Selection Bit Select CPU clock a sampling clock 1 Select sampling clock frequency of the selected system clock fxx 64 2 Bit 2 Always logic zero 1 0 External Interrupt Mode Control Bits 4 14 ELECTRONICS 557 2308 2308 2316 2316 MEMORY IMOD1 External Interrupt 1 INT1 Mode Register FB5H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 4 4 4 4 3 4 Bits 3 1 Always logic zero 0 External Interrupt 1 Edge Detection Control Rising edge detection Falling edge detection ELECTRONICS 4 15 MEMORY 557 2308 2308 2316 2316 IMOD2 External Interrupt 2 INT2 Mode Re
29. 2316 MEMORY Table 4 1 for Memory Bank 15 Continued Address Register Bte eno nw ven e amp t a 2 v o w ves No No Location FB9H is not mapped wr amp v v ew ww ve ve s Location FBBH is not mapped mo w ro oro wr o o s mos rH ir mor o mo E ro s amp o s 2 NE mW RM AUS IM m DN s 2 9 ses s 2 o s v o w s ve s Locations FD1H FD5H are not mapped EE PNE4 2 EO 4 0 W No No Yes PNE5 3 PNE5 2 4 5 0 Locations FD8H FDBH are not mapped PUMOD 2 w No No Yes FDDH 7 6 PMS 4 Locations FDEH FDFH are not mapped wl rs eo Locations 2 are not mapped rs FESH Locations not mapped PMG1 3 PM3 2 ET 1 0 W No No Yes FESH 6 3 PM6 2 PM6 1 1 6 0 Locations FEAH FEBH FEDH 4 NN at oe FEFH are not mapped ELECTRONICS 4 3 MEMORY 557 2308 2308 2316 2316 Table 4 1 Map for Memory Bank 15 Concluded Address Register eka mw
30. 5 lt P4 SMB 0 LD ADATA EA 046 lt 047 lt LD BDATA EA F8EH lt F8FH lt E 2 If EMB 1 ADATA EQU 46H BDATA EQU SMB 15 LD EA P4 E lt P5 A lt P4 SMB 0 LD ADATA EA 046H 047 E LD BDATA EA 08EH A 08FH E ELECTRONICS 3 11 ADDRESSING MODES 557 2308 2308 2316 2316 5 PROGRAMMING 8 Bit Addressing Modes Continued 8 Bit Indirect Addressing 1 If EMB 0 ADATA EQU 46H SMB 1 Non essential instruction since EMB 0 LD HL ZADATA LD EA HL A lt 046 E lt 047H 2 IfEMB 1 ADATA EQU 46H SMB 1 LD HL ZADATA LD EA HL A 146H 147H 3 12 ELECTRONICS 557 2308 2308 2316 2316 MEMORY OVERVIEW To support program control of peripheral hardware I O addresses for peripherals are memory mapped to bank 15 of the RAM Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location Access to bank 15 is controlled by the select memory bank SMB instruction and by the enable memory bank flag EMB setting If the EMB flag is 0 bank 15 can be addressed using direct addressing regardless of the current SMB value 1 bit direct and indirect addressing can be used for specific locations in bank 15 regardless of the current EMB value MAP FOR HARDWARE REGISTERS Table 4 1 contains detailed information about I
31. 557 2308 2308 2316 2316 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW The KS57C2308 C2316 single chip CMOS microcontroller has been designed for high performance using Samsung s newest 4 bit CPU core SAM47 Samsung Arrangeable Microcontrollers With features such as LCD direct drive capability 8 bit timer counter and serial I O the KS57C2308 C2316 offer an excellent design solution for a wide variety of applications that require LCD functions Up to 40 pins of the 80 pin QFP package can be dedicated to I O Six vectored interrupts provide fast response to internal and external events In addition the KS57C2308 C2316 s advanced CMOS technology provides for low power consumption and a wide operating voltage range OTP 557 2308 2316 microcontroller is also available in OTP One Time Programmable version KS57P2308 P2316 KS57P2308 P2316 microcontroller has an on chip 8 16 Kbyte one time programmable EPROM instead of masked ROM The KS57P2308 P2316 is comparable to KS57C2308 C2316 both in function and in pin configuration ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES Memory 512 x 4 bit RAM 8Kx8 bit ROM KS57C2308 P2308 16 K x 8 bit ROM KS57C2316 P2316 Pins Input only 8 pins 10 24 pins Output 8 pins sharing with segment driver outputs LCD Controller Driver Maximum 16 digit LCD direct drive capability 82 segment 4 common pins Display modes Static 1 2 du
32. 557 2308 2308 2316 2316 TIMERS and TIMER COUNTERS Table 11 4 TCO Register Overview Register Type Description RAM Addressing Reset Name Address Mode Value TMODO Control Controls TCO enable disable bit 8 bit F90H F91H 8 bit write only 2 clears and resumes counting 00 3 is operation bit 3 sets input also 1 bit and clock frequency bits writeable TCNTO Counter Counts clock pulses matching 8 bit F94H F95H 8 bit the frequency setting read only TREFO Reference Stores reference value for the 8 bit F96H F97H 8 bit timer counter 0 interval setting write only TOEO Flag Controls timer counter 0 output 1 bit F92H 2 1 bit to the TCLOO pin write only Clocks fxx 210 fxx 28 26 fxx 24 TMODO 7 TMODO 6 TMODO 5 Selector TMODO 4 TMODO 3 TMODO 2 TMODO 1 Inverted TMODO 0 Serial Figure 11 2 TCO Circuit Diagram ELECTRONICS 11 11 TIMERS TIMER COUNTERS 557 2308 2308 2316 2316 TCO ENABLE DISABLE PROCEDURE Enable Timer Counter 0 Set TMODO 2 to logic one Set TCO interrupt enable flag IETO to logic Set TMODO 3 to logic one TCNTO IRQTO and TOLO are cleared to logic zero and timer counter operation starts Disable Timer Counter 0 Set TMODO 2 to logic zero Clock signal input to the counter register TCNTO is halted The current TCNTO value is retained and can be read if necessary 11 12 ELECTRONICS 557 2308
33. Clear IRQS flag and 3 bit clock counter to logic zero then initiate serial transmission When SIO transmission starts this bit is cleared by hardware to logic zero Enable Disable SIO Data Shifter and Clock Counter Bit Disable the data shifter and clock counter the contents of IRQS flag is retained when serial transmission is completed Enable the data shifter and clock counter The IRQS flag is set to logic one when serial transmission is completed Serial I O Transmission Mode Selection Bit Receive only mode output buffer is off Transmit and receive mode output buffer is on LSB MSB Transmission Mode Selection Bit Transmit the most significant bit MSB first Transmit the least significant bit LSB first 4 27 MEMORY 557 2308 2308 2316 2316 TMODO Timer Counter 0 Mode Register F91H F90H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write Ww w WwW Bit Addressing 8 8 8 8 1 8 8 8 8 7 Bit 7 Always logic zero 6 4 Timer Counter 0 Input Clock Selection Bits External clock input at TCLO on rising edge 1 External clock input at TCLO pin on falling edge 1 o 0 1 210 4 09 kHz NOTE Selected system clock of 4 19 MHz 3 Clear Counter and Resume Counting Control Bit 1 Clear TCNTO IRQTO and and resume counting immediately This bit is cleared au
34. HL Compare and skip if A equals indirect data memory EA HL Compare and skip if EA equals indirect data memory EA RR Compare and skip if EA equals RR Description CPSE compares the source operand subtracts it from the destination operand and skips the next instruction if the values are equal Neither operand is affected by the comparison operand Binary Code operation Notation d3 a2 at do 0 rjj e ___ a3 do amp uec eee 1 lerena The extended accumulator contains the value 34H and register pair HL contains 56H second instruction RET in the instruction sequence CPSE EA HL RET is not skipped That is the subroutine returns since the result of the comparison is not equal ELECTRONICS 5 49 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 5 Decrement and Skip on Borrow DECS dst Ro Decrement register R skip on borrow 1 5 RR o o Decrement register pair RR skip on borrow Description The destination is decremented by one An original value of will underflow to OFFH If a borrow occurs a skip is executed The carry flag value is unaffected m Jo
35. IRQx flags can be addressed directly at their specific RAM addresses regardless of the current value of the enable memory bank EMB flag When a specific IRQx flag is set to logic one the corresponding interrupt request is generated The flag is then automatically cleared to logic zero when the interrupt has been serviced Exceptions are the watch timer interrupt request flags IRQW and the external interrupt 2 flag IRQ2 which must be cleared by software after the interrupt service routine has executed IRQx flags are also used to execute interrupt requests from software In summary follow these guidelines for using IRQx flags is set to request an interrupt when an interrupt meets the set condition for interrupt generation 2 IRQx is set to 1 by hardware and then cleared by hardware when the interrupt has been serviced with the exception of IRQW and IRQ2 3 When IRQx is set to 1 by software an interrupt is generated When two interrupts share the same service routine start address interrupt processing may occur in one of two ways When only one interrupt is enabled the IRQx flag is cleared automatically when the interrupt has been serviced When two interrupts are enabled the request flag is not automatically cleared so that the user has an opportunity to locate the source of the interrupt request In this case the IRQx setting must be cleared manually using a BTSTZ instruction Table 7 8 Interrupt Reque
36. L 1 1 1 1 1 Skip if memb 7 2 1 3 2 L 1 0 0 a QH e DO E E HHHH Skip if H DA 3 0 b 0 5 2 Skip if mema b 1 and clear mp memb L Skip if memb 7 2 1 3 2 L 1 0 1 and clear H DA b fife te Skip if H DA 3 0 b 1 and clear o o bt bo 22 1 1 1 1 _ ss memb L memb 7 2 L 3 2 L 1 0 lt 1 H DA b DA 3 0 b lt 1 EO EZ c 5 20 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET Table 5 20 Bit Manipulation Instructions Binary Code Summary Continued operand Binary Code Operation Notation BITR DA b 1 DAb O me rm mema b lt 0 ____ __ memb L memb7 2 13 21 1 1 01 0 H DAb 1 1 1 1 1 1 1 H DA3 0 b 0 C memb L A ee C AND memb 7 2 L 3 2 L 1 0 C H DA b ee C AND H DA 3 0 b bt aa at 40 L 1 0 as a C H DA b C C OR H DA 3 0 b Soe C memb L C C XOR memb 7 2 1 3 2 L 1 0 C H DA b ALME C XOR H DA
37. LD WMOD EA BITS IEW 2 Sample real time clock processing method CLOCK BTSTZ IRQW 0 5 second check RET No return Yes 0 5 second interrupt generation Increment HOUR MINUTE SECOND 11 26 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The 557 2308 2316 microcontroller can directly drive an up to 128 dot 32 segments x 4 commons LCD panel Its LCD block has the following components LCD controller driver Display RAM for storing display data 32 segment output pins SEGO SEGS1 4 output pins COMO COM3 Four LCD operating power supply pins The frame frequency duty and bias and the segment pins used for display output are determined by bit settings in the LCD mode register LMOD The LCD control register LCON is used to turn the LCD display on and off to switch current to the dividing resistors for the LCD display and to output LCD clock LCDCK and synchronizing signal LCDSY for LCD display expansion Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control When a subsystem clock is selected as the LCD clock source the LCD display is enabled even during main clock stop and idle modes VLCO VLC2 CONTROLLER DRIVER SEGO SEG23 gt gt SEG24 SEG31 8 0 8 7 Figure 12 1 LCD Function Diagra
38. Operating Voltage Range 18Vto5 5V Package Type 80 pin QFP ELECTRONICS 557 2308 2308 2316 2316 PRODUCT OVERVIEW BLOCK DIAGRAM Watch Dog Basic Watch P1 3 TCLO P2 0 TCLOO P4 0 P4 3 P5 0 P5 3 P6 0 P6 3 KS0 KS3 P7 0 P7 3 KS4 KS7 P8 0 P8 7 SEG24 SEG31 INTO INT1 INT2 8 Bit Timer Counter 0 Interrupt Control Block Internal Interrupts Port Port 4 Port 6 Port 7 Instruction Decoder XN XTOUT LCD Drive Controller Instruction Register 4 Bit Accumulator Port 0 Counter Program Status Word Input Port 1 Port 2 Arithmetic and Logic Unit Port 8 Stack Pointer Port Serial BIAS VLCO VLC2 LCDCK P3 0 LCDSY P3 1 COMO0 COMS3 SEGO SEG23 P8 0 P8 7 SEG24 SEG31 PO O INT4 P0 1 SCK P0 2 SO P0 3 SI P1 0 INTO P1 4 INT1 P1 2 INT2 P1 3 TCLO P2 0 TCLOO P2 1 P2 2 CLO P2 3 BUZ P3 0 LCDCK P3 1 LCDSY P3 2 P3 3 512 x 4 Bit 8 16 Kbyte Data Program Port Memory Memory 0 2 P0 3 SCK SO SI Figure 1 1 KS57C2308 C2316 Simplified Block Diagram ELECTRONICS 1 3 PRODUCT OVERVIEW 557 2308 2308 2316 2316 ASSIGNMENTS 73 J 5 10 71 L3 SEG12 70 L3 SEG13 69 J SEG14 68 J SEG15 67 J SEG16 66 J SEG17 65 1 SEG18 SEG2 SEG1 SEGO COMO COM1 COM2 SEG19 SEG20 SEG21 SEG22 SEG23 P8 0 SEG24 COM3 P8 1 SEG25 BIAS
39. Set P6 0 to input mode 1 Set P6 0 to output mode PM3 3 P3 3 I O Mode Selection Flag Set P3 3 to input mode Set P3 3 to output mode PM3 2 P3 2 I O Mode Selection Flag Set P3 2 to input mode Set P3 2 to output mode 1 1 P3 1 I O Mode Selection Set P3 1 to input mode 1 Set P3 1 to output mode PM3 0 P3 0 I O Mode Selection Flag Set P3 0 to input mode Set P3 0 to output mode 1 N ELECTRONICS 4 MEMORY 557 2308 2308 2316 2316 2 Port I O Mode Flags Group 2 Port 2 4 5 7 FEDH FECH Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write Ww WwW Addressing 8 8 8 8 8 8 8 8 PM7 P7 I O Mode Selection Flag Set P7 to input mode 1 Set P7 to output mode 2 Always logic zero PM5 P5 O Mode Selection Flag Set P5 to input mode Set P5 to output mode PM4 P4 O Mode Selection Flag Set P4 to input mode 1 Set P4 to output mode 3 Bit 3 Always logic zero PM2 P2 O Mode Selection Flag Set P2 to input mode 1 Set P2 to output mode 1 0 Bits 1 0 Always logic zero 4 22 ELECTRONICS 557 2308 2308 2316 2316 MEMORY n channel Open Drain Mode Register FD7H FD6H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W W W Bit Addressing 8 8 8 8 8 8 8 8 PNE5 3 P5 3 N Channel Open Drain Configurable Bit Configure P5 3 as a push pu
40. Transmit data lt Receive data LD RDATA EA address BANKO 20H 7FH BITS SMOD 3 510 start POP EA POP SB IRET SCK 1 EXTERNAL SO P0 2 DEVICE SI P0 3 KS57C2308 C2316 High Speed SIO Transmission ELECTRONICS 13 7 SERIAL I O INTERFACE 557 2308 2308 2316 2316 NOTES ELECTRONICS 13 8 557 2308 2308 2316 2316 ELECTRICAL DATA OVERVIEW ELECTRICAL DATA In this section information on KS57C2308 C2316 electrical characteristics is presented as tables and graphics The information is arranged in the following order Standard Electrical Characteristics Absolute maximum ratings DQ electrical characteristics Main system clock oscillator characteristics Subsystem clock oscillator characteristics capacitance electrical characteristics Operating voltage range Miscellaneous Timing Waveforms A C timing measurement point Clock timing measurement at Clock timing measurement at XTIN TCL timing Input timing for RESET Input timing for external interrupts Serial data transfer timing Stop Mode Characteristics and Timing Waveforms RAM data retention supply voltage in stop mode Stop mode release timing when initiated by RESET Stop mode release timing when initiated by an interrupt request ELECTRONICS 14 1 ELECTRICAL DATA 557 2308 2308 2316 2316 Table 14 1 Abs
41. ising edge 1 Fling edge detecion 9 Bath ising and ating ee deien 00 Rising edge detection Falling edge detection IMODO IMOD1 ELECTRONICS 7 8 557 2308 2308 2316 2316 INTERRUPTS EXTERNAL INTERRUPTO and INTERRUPT1 MODE REGISTERS Continued When a sampling clock rate of fxx 64 is used for INTO an interrupt request flag must be cleared before 16 machine cycles have elapsed Since the INTO pin has a clock driven noise filtering circuit built into it please take the following precautions when you use it To trigger an interrupt the input signal width at INTO must be at least two times wider than the pulse width of the clock selected by IMODO This is true even when the INTO pin is used for general purpose input NOISE FILTER CLOCK SELECTOR CPU clock 64 Figure 7 5 Circuit Diagram for INTO and Pins When modifying the IMOD registers it is possible to accidentally set an interrupt request flag To avoid unwanted interrupts take these precautions when writing your programs Disable all interrupts with a DI instruction Modify the IMOD register Clear all relevant interrupt request flags Enable the interrupt by setting the appropriate IEx flag op Enable all interrupts with an El instructions ELECTRONICS 7 9 INTERRUPTS 557 2308 2308 2316 2316 EXTERNAL INTERRUPT 2 MODE REGISTER IMOD2 The mode
42. lt OAFH 0AAH JPS Jump to XXX JPS was not skipped since no borrow occurred after SBS 5 82 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET SCF Set Carry Flag SCF Description The SCF instruction sets the carry flag to logic one regardless of its previous value er _____ Example If the carry flag is cleared to logic zero the instruction SCF sets the carry flag to logic one ELECTRONICS 5 83 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 SMB Select Memory Bank SMB n Description SMB instruction sets the upper four bits of a 12 bit data memory address to select a specific memory bank The constants 0 n and 15 are usually used as the SMB operand to select the corresponding memory bank All references to data memory addresses fall within the following address ranges Please note that since data memory spaces differ for various devices in the SAM47 product family the value of the SMB instruction will also vary Addresses Register Areas Bak sme 000H 01FH Working registers 020 Stack and general purpose registers nOOH 7FFH General purpose registers n n n 1 14 n 1 14 F80H FFFH l O mapped hardware registers The enable memory bank EMB flag must always be set to 1 in order for the SMB instruction to execute successfully for memory banks 0 15 Format Binary Code Operation Notat
43. serves as a data pointer the instructions LDI LDD XCHI and XCHD can make very efficient use of working registers as program loop counters by letting you transfer a value to the L register and increment or decrement it using a single instruction 1 BIT ACCUMULATOR 4 BIT ACCUMULATOR 8 BIT ACCUMULATOR Figure 2 6 1 Bit 4 Bit and 8 Bit Accumulator Recommendation for Multiple Interrupt Processing If more than four interrupts are being processed at one time you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank When the routines have executed successfully you can restore the register contents from the stack to working memory using the POP instruction 2 10 ELECTRONICS 557 2308 2308 2316 2316 ADDRESS SPACES 5 PROGRAMMING TIP Selecting the Working Register Area The following examples show the correct programming method for selecting working register area 1 When ERB 0 VENT2 1 0 INTO lt 1 ERB lt 0 Jump to INTO address INTO PUSH SB PUSH current SMB SRB SRB 2 Instruction does not execute because ERB 0 PUSH HL PUSH HL register contents to stack PUSH WX PUSH WX register contents to stack PUSH YZ PUSH YZ register contents to stack PUSH EA PUSH EA register contents to stack SMB 0 LD EA 00H LD 80H EA LD HL 40H INCS HL LD WX
44. when RESET signal is generated in power down mode the most of data memory contents are held WORKING REGISTERS 32 x 4 Bits GENERAL PURPOSE REGISTERS AND STACK AREA 224 x 4 Bits GENERAL PURPOSE REGISTERS 224 x 4 Bits LCD DATA REGISTERS 32 x 4 Bits MEMORY MAPPED AEERESS REGISTERS BANK 15 128 x 4 Bits Figure 2 3 Data Memory RAM Map ELECTRONICS 2 5 ADDRESS SPACES 557 2308 2308 2316 2316 Memory Banks 0 1 and 15 BankO 000 lowest 32 nibbles of bank 0 QOOH 01FH used as working registers the next 224 nibbles 020 can be used both as stack area and as general purpose data memory Use the stack area for implementing subroutine calls and returns and for interrupt processing Bank 1 100H 1FFH The lowest 224 nibbles of bank1 100H 1DFH are for general purpose use Use the remaining of 32 nibbles 1E0H 1FFH as display registers or as general purpose memory Bank15 F80H FFFH The microcontroller uses bank 15 for memory mapped peripheral Fixed RAM locations for each peripheral hardware address are mapped into this area Data Memory Addressing Modes The enable memory bank flag controls the addressing mode for data memory banks 0 1 or 15 When the EMB flag is logic zero the addressable area is restricted to specific locations depending on whether direct or indirect addressing is used With direct addressing you can access l
45. z 5 No operation 00 Select memory bank Select register bank Reference code EMB 0 1 Load enable memory bank flag EMB and the enable ERB 0 1 register bank flag ERB and program counter to vector ADR address then branch to the corresponding location Table 5 10 Program Control Instructions High Level Summary Operation Description Cycles Compare and skip if register equals im 2 5 HL im Compare and skip if indirect data memory equals im 2 65 Compare and skip if A equals R 2 5 1 5 2 5 2 5 3 JP JR rect its CALL CALLS RET ___ __ Return from subroutine IRET ___ Return from interrupt F gt SRET Return from subroutine and skip JPS 42 ELECTRONICS 5 9 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Table 5 11 Data Transfer Instructions High Level Summary Operation Description Exchange A and direct data memory contents Exchange A and register Ra contents Exchange A and indirect data memory Exchange EA and direct data memory contents Exchange EA and register pair RRb contents Exchange EA and indirect data memory contents Exchange A and indirect data memory contents increment contents of register L and skip on carry Exchange and indirect data memory contents decrement contents of register L and skip on carry Load 4 bit immediate data to A Load indirect data memory contents to A Load direct data memo
46. 0 IF P1 0 1 then C lt 1 if P1 0 0 then lt 0 2 The P1 address 15 FF1H and register L contains the value 9H 10018 The address memb 7 2 is 111100B and L 3 2 10B The resulting address is 11110010B or FF2H specifying P2 The bit value for the BXOR instruction L 1 0 is 01B which specifies bit 1 Therefore P1 L P2 1 LD L 9H BXOR C P1 L P1 L is specified as P2 1 XOR P2 1 ELECTRONICS 5 43 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 BXOR Bit Exclusive OR BXOR Continued Examples 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000 The resulting address is 00100000B or 20H The bit value for the BOR instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BXOR C H FLAG C XOR FLAG 20H 3 5 44 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET CALL Call Procedure CALL Operation Description Example dst ADR14 Call direct in page 14 bits CALL calls a subroutine located at the destination address The instruction adds three to the program counter to generate the return address and then pushes the result onto the stack decreasing the stack pointer by six The EMB and ERB are also pushed to the stack Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 16 Kbyte program memory address space
47. 09 kHz 30 ms TREFO value 7AH 1 79H 3 Load the value 79H to the TREFO register BITS EMB SMB 15 LD EA 79H LD TREFO EA LD EA 4CH LD TMODO EA ELECTRONICS 11 21 TIMERS and TIMER COUNTERS 557 2308 2308 2316 2316 OVERVIEW The watch timer is a multi purpose timer which consists of three basic components 8 bit watch timer mode register WMOD Clock selector Frequency divider circuit Watch timer functions include real time and watch time measurement and interval timing for the main and subsystem clock It is also used as a clock source for the LCD controller and for generating buzzer BUZ output Real Time and Watch Time Measurement To start watch timer operation set bit 2 of the watch timer mode register WMOD 2 to logic one The watch timer starts the interrupt request flag IRQW is automatically set to logic one and interrupt requests commence in 0 5 second intervals Since the watch timer functions as a quasi interrupt instead of a vectored interrupt the IRQW flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed Using a System or Subsystem Clock Source The watch timer can generate interrupts based on the system clock frequency or on the subsystem clock When the zero bit of the WMOD register is set to 1 the watch timer uses the subsystem clock signal fxt as its source if WMOD 0 0
48. 0FFH Bank 0 cated by register WX Indirect 4 bit address indi x 000H 0FFH Bank 0 cated by register WL NOTE means don t care 5 PROGRAMMING 4 Bit Addressing Modes 4 Bit Direct Addressing 1 If EMB 0 ADATA EQU 46H BDATA EQU SMB 15 Non essential instruction since EMB 0 LD A P3 A lt SMB 0 Non essential instruction since EMB 0 LD ADATA A 046H A LD LCON lt A 2 If EMB 1 ADATA EQU 46H BDATA EQU 8EH SMB 15 LD A P3 A lt SMB 0 LD ADATA A 046 lt A LD lt A 3 8 ELECTRONICS 557 2308 2308 2316 2316 ADDRESSING MODES 5 PROGRAMMING TIP 4 Bit Addressing Modes Continued 4 Bit Indirect Addressing Example 1 1 If EMB 0 compare bank 0 locations 040 046 with bank 0 locations 060 066 ADATA EQU 46H BDATA EQU 66H SMB 1 Non essential instruction since EMB 0 LD HL ZBDATA LD WX ADATA COMP LD A WL lt bank 0 040 046 CPSE A HL If bank 0 060 066 A skip SRET DECS L JR COMP RET 2 If EMB 1 compare bank 0 locations 040 046 to bank 1 locations 160 166 ADATA EQU 46H BDATA EQU 66H SMB 1 LD HL BDATA LD WX ADATA COMP LD A WL A lt bank 0 040 046 CPSE A HL If bank 1 160H 166H A skip SRET DECS L JR COMP RET ELECTRONICS 3 9 ADDRESSING MODES 557 2308 2308 2316 2316 4 Bit Indir
49. 1 020 Stack and general purpose registers 100H 1DFH General purpose registers 1 1 1 1E0H 1FFH LCD Data registers F80H FFFH l O mapped hardware registers 0 1 5 PROGRAMMING Clearing Data Memory Banks 0 and 1 Clear banks 0 and 1 of the data memory area RAMCLR 5 1 RAM 100H 1FFH clear LD HL 00H LD A 0H RMCL1 LD HL A INCS HL JR RMCL1 SMB 0 RAM 010 clear LD HL 10H RMCLO LD HL A INCS HL JR RMCLO ELECTRONICS 2 7 ADDRESS SPACES 557 2308 2308 2316 2316 WORKING REGISTERS Working registers mapped to RAM address 000H 01FH in data memory bank 0 are used to temporarily store intermediate results during program execution as well as pointer values used for indirect addressing Unused registers may be used as general purpose memory Working register data can be manipulated as 1 bit units 4 bit units or using paired registers as 8 bit units WORKING REGISTER DATA 006 MEMORY 007 008H REGISTER 10 REGISTER 017H REGISTER Figure 2 4 Working Register Map 2 8 ELECTRONICS 557 2308 2308 2316 2316 ADDRESS SPACES Working Register Banks For addressing purposes the working register area is divided into four register banks bank 0 bank 1 bank 2 and bank 3 Any one of these banks can be selected as the working register bank by the register bank selection instruction SRB n and by settin
50. 2308 2316 2316 TIMERS TIMER COUNTERS TCO PROGRAMMABLE TIMER COUNTER FUNCTION Timer counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency Its 8 bit TCO mode register is used to activate the timer counter and to select the clock frequency The reference register TREFO stores the value for the number of clock pulses to be generated between interrupt requests The counter register TCNTO counts the incoming clock pulses which are compared to the TREFO value as is incremented When there is match TREFO an interrupt request is generated To program timer counter 0 to generate interrupt requests at specific intervals choose one of four internal clock frequencies divisions of the system clock fxx and load a counter reference value into the TREFO register is incremented each time an internal counter pulse is detected with the reference clock frequency specified by 0 4 0 6 settings To generate an interrupt request the TCO interrupt request flag IRQTO is set to logic one the status of TOLO is inverted and the interrupt is generated The content of TCNTO is then cleared to and TCO continues counting The interrupt request mechanism for TCO includes an interrupt enable flag IETO and an interrupt request flag IRQTO TCO OPERATION SEQUENCE The general sequence of operations for using TCO
51. 24H 25H the binary code is 22H Opcode Symbol Instruction ORG 0020H 83 00 Al LD HL 00H 83 03 2 LD HL 03H 83 05 LD HL 05H 8310 4 LD HL 10H 83 26 5 LD HL 26H 83 08 6 LD HL 08H 83 OF A7 LD HL 0FH 83 FO A8 LD HL 0FOH 83 67 9 LD HL 067H 41 08 10 5981 01 00 11 TJP SUB2 ORG 0100H 20 REF A1 LD HL 00H 21 REF A2 LD HL 03H 22 REF A3 LD HL 05H 23 REF A4 LD HL 10H 24 REF 5 LD HL 26H 25 REF A6 LD HL 08H 26 REF A7 LD HL 0FH 27 REF 8 LD HL 0FOH 30 REF 9 LD HL 067H 31 REF 10 CALL SUB1 32 REF 11 JP SUB2 ELECTRONICS 5 77 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Return From Subroutine RET Description pops the PC values successively from the stack incrementing the stack pointer by six Program execution continues from the resulting address generally the instruction immediately following a CALL or CALLS Binary Code Operation Notation PC13 8 lt 5 1 SP PC7 0 SP 2 SP 3 PSW lt EMB ERB SP SP 6 Example The stack pointer contains the value OFAH RAM locations OFAH OFBH OFCH and and OFDH contain 1H OH 5H and 2H respectively The instruction RET leaves the stack pointer with the new value of 00H and program execution continues from location 0125H During a return from subroutine PC values are popped from stack locations as follows SP 4 6 00H 5 78 ELECTRONICS 557 2308
52. 3 BFLAG EQU 85H 3 CFLAG EQU OBAH 0 SMB 0 BITS AFLAG BITS BFLAG BTST CFLAG BITS BFLAG BITS P3 0 1 Bit Indirect Addressing ELECTRONICS 1 If EMB 0 AFLAG EQU 34H 3 BFLAG EQU 85H 3 CFLAG EQU 0 SMB 0 LD H 0BH BTSTZ H CFLAG BITS CFLAG 2 IfEMB 1 AFLAG EQU 34H 3 BFLAG EQU 85H 3 CFLAG EQU OBAH 0 SMB 0 LD H 0BH BTSTZ H CFLAG BITS CFLAG ADDRESSING MODES 34H 3 1 F85H 3 lt 1 If FBAH O 1 skip Else if 0 0 F85H 3 BMOD 3 1 FF3H 0 P3 0 1 34H 3 lt 1 85H 3 1 If OBAH O 1 skip Else if OBAH 0 0 085H 3 1 0 P3 0 1 H 0BH If 1 lt 0 and skip Else if OBAH 0 0 FBAH 0 lt 1 H 0BH If OBAH O 1 0BAH 0 lt 0 and skip Else 0 0 0BAH 0 lt 1 3 7 ADDRESSING MODES 557 2308 2308 2316 2316 4 BIT ADDRESSING Table 3 3 4 Bit Direct and Indirect RAM Addressing Operand Addressing Mode EMB Flag Addressable Memory Hardware I O Notation Description Setting Area Bank Mapping Direct 4 bit address indicated F80H FFFH Bank 15 All 4 bit by the RAM address DA and addressable the memory bank selection peripherals 000H FFFH SMB 0 1 15 SMB 15 HL Indirect 4 bit address indi 000 Bank 0 cated by the memory bank selection and register HL 1 000H FFFH SMB 0 1 All 4 bit addressable peripherals SMB 15 Indirect 4 bit address indi x 000H
53. 3 0 b o bt 2 at ao Second Byte Bit Addresses Addresses mema b ewer at FFon FF 5 5 21 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Table 5 20 Bit Manipulation Instructions Binary Code Summary Concluded Name Opeand Binary Gods Operation Notation s TEE DT ET Te mme o memb L C 1 1 1 o o 7 2 1 3 21 L 1 0 C ae H DAb C 1 1 1 1 1 1 0 0 0 lt bt aa at 40 Lo _ O CmembQL 1 1 1 1 0 1 o o Ce memb 7 2 L 3 2 L 1 0 BEHHEFBEE MN C H DAb 1 1 1 1 0 1 0 DA3 0 b BBHOHBEBEE RN 1 o bt a2 ar ao FBOH FBEH Pits or Poo ae oo Frome 5 22 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction of the SAM47 instruction set Information is arranged in a consistent format to improve readability and for use as a quick reference resource for application programmers If you are reading this user s manual for the first time please just scan this very detailed information briefly in order to acquaint yourself with the basic fe
54. 3 BUZ P3 2 P3 3 Input mode Connect to Vpp P3 1 LCDSY Output mode No connection P3 0 LCDCK No connection 2 0 Connect XT jy to Vss SCMOD 2 to 41 TEST Connect to Vss NOTES 1 Digital mode at P1 0 and P1 1 2 Used as segment LECTI ELECTRONICS 8 7 POWER DOWN 8 8 NOTES 557 2308 2308 2316 2316 ELECTRONICS 557 2308 2308 2316 2316 RESET RESET OVERVIEW When a RESET signal is input during normal operation or power down mode a hardware reset operation is initiated and the CPU enters idle mode Then when the standard oscillation stabilization interval of 31 3 ms at 4 19 MHz has elapsed normal system operation resumes Regardless of when the RESET occurs during normal operating mode or during a power down mode most hardware register values are set to the reset values described in Table 9 1 The current status of several register values is however always retained when a RESET occurs during idle or stop mode If a RESET occurs during normal operating mode their values are undefined Current values that are retained in this case are as follows Carry flag Data memory values General purpose registers E A L H X W Z and Y OSCILLATION STABILIZATION 31 3 ms 4 19 MHz RESET INPUT NORMAL MODE IDLE MODE OPERATING MODE OR eja HE POWER DOWN MODE RESET OPERATION Figure 9 1 Timing for Oscillati
55. 3H NOP LD 2 23H lt 1H LD HL 10H HL lt 10H LD HL 20H NOP LD A 3H lt LD EA 35 NOP LD 10H 3H The following table contains descriptions of special characteristics of the LD instruction when used in different addressing modes Instruction LD A im LD A RRa LD A DA LD A Ra LD Ra im LD RR imm LD DA A LD Ra A 5 62 Operation Description and Guidelines Since the redundancy effect occurs with instructions like LD EA imm if this instruction is used consecutively the second and additional instructions of the same type will be treated like NOPs Load the data memory contents pointed to by 8 bit RRa register pairs HL WX WL to the A register Load direct data memory contents to the A register Load 4 bit register Ra E L H X W Z Y to the A register Load 4 bit immediate data into the Ra register E L H X W Y Z Load 8 bit immediate data into the Ra register EA HL WX YZ There is a redundancy effect if the operation addresses the HL or EA registers Load contents of register A to direct data memory address Load contents of register A to 4 bit Ra register E L H X W Z Y ELECTRONICS 557 2308 2308 2316 2316 LD Load LD Concluded Examples Instruction LD EA HL LD EA DA LD EA RRb LD HL A LD DA EA LD RRb EA LD HL EA ELECTRONICS SAM47 INSTRUCTION SET Operation Description and
56. 4 Voltage Dividing Resistor Circuit Diagrams ELECTRONICS 12 7 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 COMMON SIGNALS The common signal output pin selection COM pin selection varies according to the selected duty cycle You must therefore be open any unused COM pins according to this guideline In static mode be open the COM1 2 and pins In 1 2 duty mode be open the COM2 and In 1 3 duty mode be open the Table 12 6 Common Signal Pins Used Per Duty Cycle Display Mode COMO Pin COMI Pin 2 Pin Pin NIC NIC NIC 12 duty NC 1 3 NIC 1 4 NOTE NC means that no connection is required f T LCDCK Frame frequency Figure 12 5 LCD Common Signal Waveform Static 12 8 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER COMO 1 1 2 DUTY COMO 1 1 3 DUTY T LCDCK Frame frequency Figure 12 6 LCD Common Signal Waveform at 1 2 Bias 1 2 1 3 Duty ELECTRONICS 12 9 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 COMO 2 1 8 DUTY COMO 3 1 4 DUTY T LCDCK Frame frequency Figure 12 7 LCD Common Signal Waveform at 1 3 Bias 1 3 1 4 Duty 12 10 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER SEGMENT SEG SIGNALS The 32 LCD segment signal pins are connected to corresponding display RAM locations at 1
57. A 9H LD 90H A F90H A bank 15 is selected LD 34H A 034 lt A bank 0 is selected SMB 0 Non essential instruction since EMB 0 LD 90H A F90H A bank 15 is selected LD 34H A 034 A bank 0 is selected SMB 15 Non essential instruction since EMB 0 LD 20H A 020H A bank 0 is selected LD 90H A F90H A bank 15 is selected SMB 1 Select memory bank 1 LD A 9H LD 90H A 190H lt A bank 1 is selected LD 34H A 134 A bank 1 is selected SMB 0 Select memory bank 0 LD 90H A 090H A bank 0 is selected LD 34H A 034 A bank 0 is selected SMB 15 Select memory bank 15 LD 20H A Program error but assembler does not detect it LD 90H A F90H A bank 15 is selected 2 18 ELECTRONICS 557 2308 2308 2316 2316 ADDRESS SPACES ERB FLAG ERB The 1 bit register bank enable flag ERB determines the range of addressable working register area When the ERB flag is 1 the working register area from register banks 0 to 3 is selected according to the register bank selection register SRB When the ERB flag is 0 register bank 0 is the selected working register area regardless of the current value of the register bank selection register SRB When an internal RESET is generated bit 6 of program memory address OOOOH is written to the ERB flag This automatically initializes the flag When a vectored interrupt is generated bit 6 of the
58. EA All key strobe outputs to low level LD A 3H LD IMOD2 A Select KSO KS7 enable SMB 0 BITR IROW BITR IRQ2 BITS IEW BITS IE2 CLKS1 CALL WATDIS Execute clock and display changing subroutine BTSTZ IRQ2 JR CIDLE CALL SUB2MA Subsystem clock main system clock switch subroutine EI RET CIDLE IDLE Engage idle mode NOP NOP NOP JPS CLKS1 NOTE You must program at least three NOP instructions after IDLE and STOP instructions to avoid flowing of leakage current due to the floating state in the internal bus LECTI ELECTRONICS 8 5 POWER DOWN 557 2308 2308 2316 2316 PORT PIN CONFIGURATION FOR POWER DOWN The following method describes how to configure I O port pins to reduce power consumption during power down modes stop idle Condition 1 If the microcontroller is not configured to an external device 1 2 Connect unused port pins according to the information in Table 8 2 Disable pull up resistors for input pins configured to or Vss levels in order to check the current input option Reason If the input level of a port pin is set to when a pull up resistor is enabled it will draw unnecessarily large current Condition 2 If the microcontroller is configured to an external device and the external device s Vpp source 8 6 is turned off in power down mode Connect unused port pins according to the information in Table 8 2 Disable pull up resistors for input pins configured to
59. Guidelines Load data memory contents pointed to by 8 bit register HL to the A register and the contents of HL 1 to the E register The contents of register L must be an even number If the number is odd the LSB of register L is recognized as a logic zero an even number and it is not replaced with the true value For example LD HL 36H loads immediate 36H to HL and the next instruction LD EA HL loads the contents of 36H to register A and the contents of 37H to register E Load direct data memory contents of DA to the A register and the next direct data memory contents of DA 1 to the E register The DA value must be an even number If it is an odd number the LSB of DA is recognized as a logic zero an even number and it is not replaced with the true value For example LD EA 37H loads the contents of 36H to the A register and the contents of 37H to the E register Load 8 bit RRb register HL WX YZ to the EA register H W and Y register values are loaded into the E register and the L X and Z values into the A register Load A register contents to data memory location pointed to by the 8 bit HL register value Load the A register contents to direct data memory and the E register contents to the next direct data memory location The DA value must be an even number If it is an odd number the LSB of the DA value is recognized as logic zero an even number and is not replaced with the true value Load cont
60. INCS Increment and Skip on Carry INCS dst Ro Increment register R skip on carry 1 5 Da Inorement direct data ____ 2 245 _____ Inorement data memory skip on carry __ 2 2 S 8 Description instruction INCS increments the value of the destination operand by one original value of OFH will for example overflow to OOH If a carry occurs the next instruction is skipped The carry flag value is unaffected oporana Binary Gods Operation 2a onenen 8 ____ 11 1 0 01 11 0 1 0 1 skip on carry 1 lt HL 1 skip on carry 1 1 0 9101110 RRbeRRb t skiponcary _ Example Register pair HL contains the value 7EH 01111110B RAM location 7EH contains OFH The instruction sequence INCS HL lt INCS HL Skip INCS HL lt 1 leaves the register pair HL with the value 7 and RAM location 7 with the value 1H Since a carry occurred the second instruction is skipped The carry flag value remains unchanged 5 54 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET IRET Return From Interrupt Operation Description Example IRET is used at the end of an interrupt service routine It pops the PC values successively
61. INTERRUPTS OVERVIEW The 557 2308 2316 interrupt control circuit has five functional components Interrupt enable flags IEx Interrupt request flags IRQx Interrupt master enable register IME Interrupt priority register IPR Power down release signal circuit Three kinds of interrupts are supported Internal interrupts generated by on chip processes External interrupts generated by external peripheral devices Quasi interrupts used for edge detection and as clock sources Table 7 1 Interrupt Types and Corresponding Port Pin s Interrupt Type Corresponding Port Pins INTO INT1 4 P1 0 P1 1 0 INTB INTTO INTS Not applicable Quasi interrupts INT2 KSO KS7 P1 2 P6 0 P7 3 INTW Not applicable ELECTRONICS 7 1 INTERRUPTS 557 2308 2308 2316 2316 Vectored Interrupts Interrupt requests may be processed as vectored interrupts in hardware or they can be generated by program software A vectored interrupt is generated when the following flags and register settings corresponding to the specific interrupt INTn are set to logic one Interrupt enable flag IEx Interrupt master enable flag IME Interrupt request flag IRQx Interrupt status flags ISO 151 Interrupt priority register IPR If all conditions are satisfied for the execution of a requested service routine the start address of the interrupt is loaded into the program counter and the program starts executing t
62. LCDCK and LCDSY signal outputs 1 Enable LCDCK and LCDSY signal outputs Always logic zero 0 LCD Display Control LCD output low turns display off cut off current to dividing resistor and output port 8 latch contents 1 If LMOD 3 0 turns display off output port 8 latch contents If LMOD 3 1 COM and SEG output in display mode LCD display on NOTES 1 You can manipulate 0 when you try to turn ON OFF LCD display internally If you want to control LCD ON OFF or LCD contrast externally you should set the LCON 0 to 0 refer to chapter 12 if you need more information 2 To select the LCD bias you must properly configure both LMOD register and the external LCD bias circuit connection 4 18 ELECTRONICS 557 2308 2308 2316 2316 MEMORY LMOD Lcp Mode Register F8DH F8CH Bit Identifier RESET Value Read Write Bit Addressing 7 6 5 4 ELECTRONICS 7 6 5 4 3 2 1 0 __7 6 5 4 3 2 a o 0 0 0 0 0 0 0 0 W W W W W w w 8 8 8 8 1 8 8 8 8 LCD Output Segment and Pin Configuration Bits Segments 24 27 28 31 4 Segment 24 27 1 bit output at 8 4 8 7 1 0 Segment 28 31 1 bit output at P8 0 P8 3 1 bit output only at P8 0 P8 3 and 8 4 8 7 LCD Clock LCDCK Frequency Selection Bits _ ____ 1 0 iwz meHz __ NOTE Assuming watch timer clock fw 32 768 kHz
63. Load a signal divider value to the TREFO register Clear TMODO 6 to 0 to enable external clock input at the TCLO pin Set TMODO 5 and TMOD0 4 to desired TCLO signal edge detection Set port 2 0 mode flag to output 1 Clear P2 0 output latch to O Set TOEO flag to 1 to enable output of the divided frequency to the TCLOO pin o gt m 5 PROGRAMMING External TCLO Clock Output to the TCLOO Pin Output external TCLO clock pulse to the TCLOO pin divided by four EXTERNAL TCLO CLOCK PULSE BITS EMB SMB 15 LD EA 01H LD TREFO EA LD EA 0CH LD TMODO EA LD EA 04H LD PMG2 EA P2 0 lt output mode BITR P2 0 Clear P2 0 output latch BITS TOEO 11 16 ELECTRONICS 557 2308 2308 2316 2316 TIMERS TIMER COUNTERS TCO MODE REGISTER 0 is the 8 bit mode control register for timer counter 0 It is addressable by 8 bit write instructions One bit 0 3 is also 1 bit writeable RESET clears all bits to logic zero and disables TCO operations TMODO 2 is the enable disable bit for timer counter 0 When 3 is set to 1 the contents of TCNTO IRQTO TOLO are cleared counting starts from and TMODO 3 is automatically reset to 0 for normal TCO operation When TCO operation stops TMODO 2 0 the contents of the TCO counter register TCNTO are retained until TCO is re enabled TMODO 6 TMODO 5 and TMOD0 4 bit s
64. O mapping for peripheral hardware in bank 15 register locations F80H FFFH Use the I O map as a quick reference source when writing application programs The I O map gives you the following information Register address Register name mnemonic for program addressing Bit values both addressable and non manipulable Read only write only or read and write addressability 1 bit 4 bit or 8 bit data manipulation characteristics ELECTRONICS 4 1 MEMORY 557 2308 2308 2316 2316 Table 4 1 Map for Memory Bank 15 Memory Bank 15 Addressing Mode 22222 Memory Bank 15 F81H s 9 Ser sme Location F84H is not mapped DCUM NS TEC HG M ea 5 4 F89H Locations FSAH F8BH are not mapped E P L ENG Location F8FH is not mapped F90H TMODO 3 2 0 0 pege F91H o are 8 So Location F93H is mapped F94H TCNTO 3 2 0 R No No Yes F95H 7 3 6 5 4 5 1 N owl _7 6 5 4 a F99H Jf 5 o O 5 w wes Yes N Locations are not S po s pr De ss mM moo s v 9 w Em moor v w v o wo wv 2 0 emp ELECTRONICS T m 557 2308 2308 2316
65. SMDS2 is a new and improved version of SMDS2 Samsung also offers support software that includes debugger assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be sized moved scrolled highlighted added or removed completely SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM57 The SASM57 is an relocatable assembler for Samsung s KS57 series microcontrollers The SASM57 takes a source file containing assembly language statements and translates into a corresponding source code object code and comments The SASM57 supports macros and conditional assembly It runs on the MS DOS operating system It produces the relocatable object code only so the user should link object file Object files can be linked with other object files and loaded into memory HEX2ROM HEX2ROM file generates R
66. When aport pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD Figure 10 4 Port 3 and 6 Circuit Diagram ELECTRONICS 10 9 VO PORTS 557 2308 2308 2316 2316 PORT 4 AND 5 CIRCUIT DIAGRAM PUMOD x X port number 4 5 CMOS Push Pull or N Channel Open Deain H NOTE When a port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD Figure 10 5 Port 4 and 5 Circuit Diagram 10 10 ELECTRONICS 557 2308 2308 2316 2316 VO PORTS PORT 7 CIRCUIT DIAGRAM Output Latch NOTE When a port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD Figure 10 6 Port 7 Circuit Diagram ELECTRONICS 10 11 VO PORTS 557 2308 2308 2316 2316 NOTES 10 12 ELECTRONICS 557 2308 2308 2316 2316 TIMERS and TIMER COUNTERS TIMERS and TIMER COUNTERS OVERVIEW 557 2308 2316 microcontroller has three timer and timer counter modules 8 bit basic timer BT 8 bit timer counter TCO Watch timer WT The 8 bit basic timer BT is the microcontroller s main interval timer It generates an
67. are loaded into the accumulator and the contents of the register L are incremented by one If an overflow occurs e g if the resulting value in register L is the next instruction is skipped The contents of data memory and the carry flag value are not affected 1 1 1 lt HL thenL L skip if L Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains the value OFH LD HL 2FH LDI A HL A lt lt L 1 JPS XXX Skip JPS YYY 2 lt 0H The instruction JPS is skipped since an overflow occurred after the LDI A HL and the instruction JPS YYY is executed ELECTRONICS 5 69 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Operation Summary Cycles Description operation is performed by a NOP instruction It is typically used for timing delays One NOP causes 1 cycle delay with a 1 us cycle time five NOPs would therefore cause a 5 us delay Program execution continues with the instruction immediately following the NOP Only the PC is affected At least three NOP instructions should follow a STOP or IDLE instruction won Example Three NOP instructions follow the STOP instruction to provide a short interval for clock stabilization before power down mode is initiated STOP NOP
68. by RESET IDLE INSTRUCTION MODE INTERRUPT ACKNOWLEDGE IME 1 RELEASE SIGNAL NORMAL MODE IDLE MODE NORMAL MODE ae CLOCK NORMAL OSCILLATION SIGNAL Figure 8 2 Timing When Idle Mode is Released by an Interrupt LECTI ELECTRONICS 8 3 POWER DOWN 557 2308 2308 2316 2316 STOP MODE TIMING DIAGRAMS 8 4 OSCILLATION STOP STABILIZATION INSTRUCTION 31 3 ms 4 19 MHz q NORMAL STOP IDLE NORMAL gt lt lt OSCILLATION CLOCK STOPS OSCILLATION RESUMES SIGNAL Figure 8 3 Timing When Stop Mode is Released by RESET OSCILLATION STABILIZATION STOP BMOD SETTING INSTRUCTION 1 NORMAL MODE STOP MODE IDLE MODE NORMAL MODE lt lt ee eren OSCILLATION CLOCK STOPS SIGNAL SSS lt n OSCILLATION RESUMES Figure 8 4 Timing When Main Stop or Main Sub Stop Mode is Release by an Interrupt ELECTRONICS 557 2308 2308 2316 2316 POWER DOWN 5 PROGRAMMING Reducing Power Consumption for Key Input Interrupt Processing The following code shows real time clock and interrupt processing for key inputs to reduce power consumption In this example the system clock source is switched from the main system clock to a subsystem clock and the LCD display is turned on KEYCLK DI CALL MA2SUB Main system clock subsystem clock switch subroutine SMB 15 LD EA 00H LD P2
69. designed to support the large register files that are typical of most KS57 series microcontrollers The SAM47 instruction set includes 1 bit 4 bit and 8 bit instructions for data manipulation logical and arithmetic operations program control and CPU control I O instructions for peripheral hardware devices are flexible and easy to use Symbolic hardware names can be substituted as the instruction operand in place of the actual address Other important features of the SAM47 instruction set include 1 byte referencing of long instructions REF instruction Redundant instruction reduction string effect Skip feature for ADC and SBC instructions Instruction operands conform to the operand format defined for each instruction Several instructions have multiple operand formats Predefined values or labels can be used as instruction operands when addressing immediate data Many of the symbols for specific registers and flags may also be substituted as labels for operations such DA mema memb b and so on Using instruction labels can greatly simplify programming and debugging tasks INSTRUCTION SET FEATURES In this section the following SAM47 instruction set features are described in detail Instruction reference area Instruction redundancy reduction Flexible bit manipulation ADC and SBC instruction skip condition NOTE The ROM size accessed by instruction may change for different devices in the SAM47 produ
70. for interrupt service routines are stored in this area along with the values of the enable memory bank EMB and enable register bank ERB flags that are used to set their initial value for the corresponding service routines The 16 byte area can be used alternately as general purpose ROM REF Instructions Locations 0020 007 are used as a reference area look up table for 1 byte REF instructions The REF instruction reduces the byte size of instruction operands REF can reference one 2 byte instruction two 1 byte instructions and one 3 byte instruction which are stored in the look up table Unused look up table addresses can be used as general purpose ROM Table 2 1 Program Memory Address Ranges ROM Area Function Address Ranges Area Size in Bytes General purpose program memory 000 001 REF instruction look up table area 0020 007 General purpose program memory 0080H 1FFFH KS57C2308 8064 KS57C2308 0080 KS57C2316 16256 KS57C2316 ELECTRONICS 2 1 ADDRESS SPACES 557 2308 2308 2316 2316 GENERAL PURPOSE MEMORY AREAS The 20 byte area at ROM locations 000 001 and the 8 064 byte 16 256 byte area at ROM locations 0080H 1FFFH 0080 are used as general purpose program memory Unused locations in the vector address area and REF instruction look up table areas can be used as general purpose program memory However care must be taken not to overwrite live data whe
71. from interrupt IRET Restore carry flag from stack with other PSW bits NOTES 1 operand has three bit addressing formats memb L DA b 2 refers to the specific interrupt being executed and is not an instruction 2 20 ELECTRONICS 557 2308 2308 2316 2316 ADDRESS SPACES 5 PROGRAMMING TIP Using the Carry Flag as a 1 Bit Accumulator 1 Set the carry flag to logic one 1 EA lt 0C3H HL OAAH HL 0AAH EA HL EA lt 0C3H 1H C lt 1 2 Logical AND bit 3 of address 3FH with P3 3 and output the result to P4 0 LD LDB BAND LDB ELECTRONICS H 3H Set the upper four bits of the address to the H register value C H 0FH 3 C e bit 3 of SFH C P3 3 P3 3 P4 0 C Output result from carry flag to P4 0 ADDRESS SPACES 557 2308 2308 2316 2316 NOTES 2 22 ELECTRONICS 557 2308 2308 2316 2316 ADDRESSING MODES ADDRESSING MODES OVERVIEW The enable memory bank flag EMB controls the two addressing modes for data memory When the EMB flag is set to logic one you can address the entire RAM area when the EMB flag is cleared to logic zero the addressable area in the RAM is restricted to specific locations The EMB flag works in connection with the select memory bank instruction SMB n You will recall that the SMB n instruction is used to select RAM bank 0 1 or 15 The SMB se
72. interrupt is inhibited Then when the high priority interrupt is returned from its service routine by an IRET instruction the inhibited service routine is started ELECTRONICS 7 7 INTERRUPTS 557 2308 2308 2316 2316 5 PROGRAMMING Setting the INT Interrupt Priority The following instruction sequence sets the INT1 interrupt to high priority BITS EMB SMB 15 DI IPR 3 lt 0 LD A 3H LD IPR A IPR 3 lt 1 EXTERNAL INTERRUPT 0 AND 1 MODE REGISTERS IMODO and IMOD1 The following components are used to process external interrupts at the INTO and INT1 pins Noise filtering circuit for INTO Edge detection circuit Two mode registers IMODO and IMOD1 The mode registers are used to control the triggering edge of the input signal IMODO and IMOD1 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger The INT4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling edges Since INT2 is a qusi interrupt the interrupt request flag IRQ2 must be cleared by software IMODO IMOD1 and 2 are addressable by 4 bit write instructions RESET clears all IMOD values to logic Zero selecting rising edges as the trigger for incoming interrupt requests Table 7 5 IMODO and IMOD1 Register Organization mons s EWecoronoSeungs E 5 o
73. interrupt request at a fixed time interval when the appropriate modification is made to its mode register The basic timer also functions as watchdog timer and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a RESET The 8 bit timer counter TCO is programmable timer counter that is used primarily for event counting and for clock frequency modification and output In addition TCO generates a clock signal that can be used by the serial I O interface The watch timer WT module consists of an 8 bit watch timer mode register a clock selector and a frequency divider circuit Watch timer functions include real time and watch time measurement main and subsystem clock interval timing buzzer output generation It also generates a clock signal for the LCD controller ELECTRONICS 11 1 TIMERS TIMER COUNTERS 557 2308 2308 2316 2316 BASIC OVERVIEW The 8 bit basic timer BT has five functional components Clock selector logic 4 bit mode register BMOD 8 bit counter register BCNT 8 bit watchdog timer mode register WDMOD Watchdog timer counter clear flag WDTCF The basic timer generates interrupt requests at precise intervals based on the frequency of the system clock Basic timer s counter register BCNT outputs timer pulses to the watchdog timer s counter register WOTCNT when an overflow occurs in BCNT Yo
74. mode LCD clock segment or port output and display on off LMOD be manipulated using 8 bit write instructions bit 3 LMOD 3 can be also written by 1 bit instructions The LCD clock signal LCDCK determines the frequency of COM signal scanning of each segment output which is also referred to as the frame frequency Since LCDCK is generated by dividing the watch timer clock fw the watch timer must have been enabled when the LCD display is turned on RESET clears the LMOD register values to logic zero The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source and running The LCD mode register LMOD controls the output mode of the 8 pins used for normal outputs 8 0 8 7 Bits LMOD 7 6 define the segment output and normal bit output configuration Table 12 4 LCD Mode Register LMOD Organization o o o Segments 24 27 paz 1 0 28 01 Toit 0 83 1 bit output only at P8 0 P8 3 and P8 4 P8 7 0002 wisi LMOD 3 LMOD 2 LMOD 1 LMOD O Duty and Bias Selection for LCD Display oosyo 00 7 0 0 _ 1 1 3 duty 1 2 bias __ Lg 1 _ o3 d ELECTRONICS 12 5 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 Table 12 5 L
75. mode register PNE is used to configure ports 4 and 5 to n channel open drain or as push pull outputs When a bit in the PNE register is set to 1 the corresponding output pin is configured to n channel open drain when set to 0 the output pin is configured to push pull The PNE register consists of an 8 bit register PNE can be addressed by 8 bit write instructions only PIN ADDRESSING FOR OUTPUT PORT 8 The addresses for the port 8 1 bit output pin buffers are located in bank 1 of data memory instead of bank 15 To address port 8 output pins use the settings EMB 1 and SMB 1 The LCD mode register LMOD is used to control whether the pin address is used for LCD data output or for normal data output Table 10 5 LMOD 7 and LMOD 6 Setting for Port 8 Output Control LMOD 7 LMOD 6 LCD Output Segments 1 Bit Output Pins Tam Seg 24 31 IEEE ____ Seg 24 27 P8 4 P8 7 Seg 28 31 1 a Seg 28 31 P8 0 P8 3 Seg 24 27 Each address in RAM bank 1 corresponds to a 4 bit register location The LSB bit 0 of the register location is used as the port buffer for either LCD segment output or normal 1 bit data output Locations that are unused for LCD or port I O can be used as normal data memory After a RESET the values contained in the port 8 output buffer are left undetermined Table 10 6 shows port 8 pin addresses and also the corresponding LCD segment names if the pins are used to output
76. pin coordinate data table 80 QFP 1420C 0 NOTE Dimensions in millimeters Figure 15 1 80 QFP 1420C Package Dimensions ELECTRONICS 15 1 MECHANICAL DATA 557 2308 2308 2316 2316 NOTES 15 2 ELECTRONICS 557 2308 2308 2316 2316 557 2308 2316 KS57P2308 P2316 OTP OVERVIEW The KS57P2308 P2316 single chip CMOS microcontroller is the OTP One Time Programmable version of the KS57C2308 C2316 microcontroller It has an on chip EPROM instead of masked ROM The EPROM is accessed by a serial data format The 557 2308 2316 is fully compatible with the KS57C2308 C2316 both in function and in pin configuration Because of its simple programming requirements the KS57P2308 P2316 is ideal for use as an evaluation chip for the 557 2308 2316 ELECTRONICS 16 1 557 2308 2316 557 2308 2308 2316 2316 73 J SEG10 72 J SEG11 70 1 SEG13 68 J SEG15 67 J SEG16 66 SEG17 65 L1 SEG18 SEG2 SEG1 SEGO COMO COM1 COM3 BIAS VLCO SDATWLC1 SCLKVLC2 Vpp VDD Vss Vss XOUT XIN Vpp TEST XTIN XTOUT RESET RESET PO O INT4 P0 1 SCK P0 2 SO P0 3 SI P1 0 INTO SEG19 SEG20 SEG21 SEG22 SEG23 P8 0 SEG24 P8 1 SEG25 P8 2 SEG26 P8 3 SEG27 P8 4 SEG28 KS57P2308 KS57P2316 P8 5 SEG29 TOP VIEW 5 P8 6 SEG30 P8 7 SEG31 P7 3 KS7 P7 2 KS6 P7 1 KS5 P7 0 KS4 P6 3 KS3 P6 2 KS2 P6 1 KS1 P6 0 KSO P5 3 P5 2 P5 1 O Q ON wake jd
77. register for external interrupt 2 at the KSO KS7 pins IMOD2 is addressable only by 4 bit write instructions RESET clears all IMOD2 bits to logic zero FB6H IMOD2 2 IMOD2 1 IMOD2 0 IMOD22 IMOD21 IMOD20 If a rising or falling edge is detected at any one of the selected KS pin by the IMOD2 register the IRQ2 flag is set to logic one and a release signal for power down mode is generated Table 7 6 IMOD2 Register Bit Settings IMOD2 Effect of IMOD2 Settings Select rising edge at INT2 pin Select falling edge at 54 57 Select falling edge at 50 57 Ignore selection of falling edge at KS4 KS7 IMOD22 IMOD21 IMOD20 __ o __ 1 Loo q Select falling edge at KS2 KS7 Lg Y Jj LECTRONI 7 10 ELECTRONICS 557 2308 2308 2316 2316 INTERRUPTS RISING EDGE DETECTION CIRCUIT FALLING EDGE DETECTION CIRCUIT gt p ps gt gt gt gt 2 CLOCK SELECTOR Figure 7 6 Circuit Diagram for INT2 and KS0 KS7 Pins ELECTRONICS 7 11 INTERRUPTS 557 2308 2308 2316 2316 INTERRUPT FLAGS There are three types of interrupt flags interrupt request and interrupt enable flags that correspond to each interrupt the interrupt master enable flag which enables or disables all interrupt processing Interrupt Master Enable Flag IME The interrupt master enable flag IME enables or disables all interrupt processing Therefore even when an IRQx f
78. routine initialization and thereby process multiple interrupts simultaneously If more than four interrupts are being processed at one time you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank When the routines have executed successfully you can restore the register contents from the stack to working memory using the POP instruction Power Down Mode Release An interrupt with the exception of INTO can be used to release power down mode stop or idle Interrupts for power down mode release are initiated by setting the corresponding interrupt enable flag Even if the IME flag is cleared to zero power down mode will be released by an interrupt request signal when the interrupt enable flag has been set In such cases the interrupt routine will not be executed since IME 0 ELECTRONICS 7 2 557 2308 2308 2316 2316 INTERRUPTS Interrupt is generated INT xx Request flag IRQx lt 1 High priority interrupt YES 0 1 151 0 1 0 Stores the contents of PC PSW stack area set PC contents to corresponding vector address Are both interrupt sources of shared vector address used IRQx flag value remains 1 Reset corresponding IRQx flag Jump to interrupt start address Jump to interrupt start address Verify interrupt source and clear IRQx with a BTSTZ inst
79. the last data to be written to the stack The program counter contents and program status word are stored in the stack area prior to the execution of a CALL or a PUSH instruction or during interrupt service routines Stack operation is a LIFO Last In First Out type The stack area is located in general purpose data memory bank 0 During an interrupt or a subroutine the PC value and the PSW are saved to the stack area When the routine has completed the stack pointer is referenced to restore the PC and PSW and the next instruction is executed The SP can address stack registers in bank 0 addresses 000H 0FFH regardless of the current value of the enable memory bank EMB flag and the select memory bank SMB flag Although general purpose register areas can be used for stack operations be careful to avoid data loss due to simultaneous use of the same register s Since the RESET value of the stack pointer is not defined in firmware we recommend that you initialize the stack pointer by program code to location OOH This sets the first register of the stack area to OFFH NOTE A subroutine call occupies six nibbles in the stack an interrupt requires six When subroutine nesting or interrupt routines are used continuously the stack area should be set in accordance with the maximum number of subroutine levels To do this estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly
80. the REF instruction look up table ORG 0020H JMAIN MAIN 0 MAIN KEYCK BTSF KEYFG 1 KEYFG CHECK WATCH TCALL CLOCK 2 CALL CLOCK INCHL LD HL A 3 HL lt A INCS HL ABC LD EA 00H 47 EA ORG 0080H MAIN NOP NOP REF KEYCK BTSF KEYFG 1 byte instruction REF JMAIN KEYFG 1 jump to MAIN 1 byte instruction REF WATCH KEYFG 0 CALL CLOCK 1 byte instruction REF INCHL LD HL A INCS HL REF ABC LD EA 00H 1 byte instruction 2 4 ELECTRONICS 557 2308 2308 2316 2316 ADDRESS SPACES DATA MEMORY RAM OVERVIEW In its standard configuration the 512 x 4 bit data memory has four areas 32 4 bit working register area in bank 0 224 x 4 bit general purpose area in bank 0 which is also used as the stack area 224 x 4 bit general purpose area in bank 1 32 x 4 bit area for LCD data in bank 1 128 x 4 bit area in bank 15 for memory mapped I O addresses To make it easier to reference the data memory area has three memory banks bank 0 bank 1 and bank 15 The select memory bank instruction SMB is used to select the bank you want to select as working data memory Data stored in RAM locations are 1 4 and 8 bit addressable One exception is the LCD data register area which is 1 bit and 4 bit addressable only Initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power RESET However
81. the SC2 SC1 and SCO bits is not allowed CARRY FLAG C The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a ADC SBC The carry flag can also be used as a 1 bit accumulator for performing Boolean operations involving bit addressed data memory If an overflow or borrow condition occurs when executing arithmetic instructions with carry ADC SBC the carry flag is set to 1 Otherwise its value is 0 When a RESET occurs the current value of the carry flag is retained during power down mode but when normal operating mode resumes its value is undefined The carry flag can be directly manipulated by predefined set of 1 bit read write instructions independent of other bits in the PSW Only the ADC and SBC instructions and the instructions listed in Table 2 7 affect the carry flag Table 2 7 Valid Carry Flag Manipulation Instructions Operation Type instructions Carry Ftag Manipulation Clear carry flag to 0 reset carry flag Boolean manipulation BAND operand 1 AND the specified bit with contents of carry flag and save the result to the carry flag BOR C operand 1 OR the specified bit with contents of carry flag and save the result to the carry flag C operand 1 XOR the specified bit with contents of carry flag and save the result to the carry flag Interrupt routine INTn 2 Save carry flag to stack with other PSW bits Return
82. watch Timer Mode Register F89H F88H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 note 0 0 0 Read Write W W W W R W W W Bit Addressing 8 8 8 8 1 8 8 8 7 Enable Disable Buzzer Output EJ Disable buzzer BUZ signal output Enable buzzer BUZ signal output 6 Bit 6 Always logic zero 5 4 Output Buzzer Frequency Selection Bits 2 kHz buzzer 802 signal output 4 kHz buzzer BUZ signal output 8 kHz buzzer 802 signal output 16 kHz buzzer BUZ signal output 3 Input Level Control Input level to XTIN pin is low 1 bit read only addressable for test 1 Input level to XTIN pin is high 1 bit read only addressable for test 2 Enable Disable Watch Timer Bit Disable watch timer and clear frequency dividing circuits Enable watch timer 1 Watch Timer Speed Control Normal speed set IRQW to 0 5 seconds 1 High speed operation set IRQW to 3 91 ms 0 Watch Timer Clock Selection Select the system clock fxx 128 as the watch timer clock 1 Select a subsystem clock as the watch timer clock NOTE RESET sets WMOD 3 to the current input level of the subsystem clock If the input level is high WMOD 3 set to logic one if low WMOD 3 is cleared to zero along with all the other bits in the WMOD register 4 32 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET SAM47 INSTRUCTION SET OVERVIEW The SAM47 instruction set is specifically
83. 01 J102 1 39 40 A e 2 2 Q 2 2 m gt TARGET SYSTEM J102 J101 1 2 1 2 Target Cable for 40 Pin Connector Part Name AS40D A Order Code SM6306 39 40 39 40 Figure 17 4 TB572308A 16A Adapter Cable for 80 QFP Package KS57C2308 P2308 C2316 P2316 17 6 ELECTRONICS 557 SERIES MASK ROM ORDER FORM Product description Device Number KS57C write down the ROM code number Product Order Form Package Petet Wafer Package Marking Check One Standard 10 10 chars each line Device Name Device Name aes Assembly site code Y Last number of assembly year WW Week of assembly Delivery Dates and Quantities ROM code Po Not applicable See ROM Selection Form PT Please answer the following questions For what kind of product will you be using this order New product Upgrade of an existing product A Replacement of an existing product Other If you are replacing an existing product please indicate the former product name What are the main reasons you decided to use a Samsung microcontroller in your product Please check all that apply Price Product quality Features and functions Development system Technical support Delivery on time Used same micom before Quality of documentation
84. 10 CPU fxt 4 SCMOD 1001B 32 kHz crystal oscillator 1004 Sub Idle mode 3 V 10 CPU fxt 4 SCMOD 1101B 32 crystal oscillator 005 Stop mode CPU fxt 4 SCMOD 1101B 9 Stop mode CPU fx 4 SCMOD 0100B NOTES 1 D C electrical values for supply current to Ippe do not include current drawn through internal pull up resistors and through LCD voltage dividing resistors 2 Data includes the power consumption for sub system clock oscillation 3 When the system clock mode register SCMOD is set to 0100B the sub system clock oscillation stops The main system clock oscillation stops by the STOP instruction ELECTRONICS 16 6 557 2308 2308 2316 2316 557 2308 2316 Table 16 6 System Clock Oscillator Characteristics Ta 40 C 85 C 1 8 V to 5 5 V Clock Parameter Test Condition Typ Configuration Ceramic Oscillator Stabilization occurs when Vpp is equal to the minimum oscillator voltage range Crystal XIN XOUT Oscillator T Stabilization time 2 Vonza vess XIN input high and low 83 3 level width txL RC Frequency 1 0 4 a 2 Oscillator R 20 Vpp 5 V 20 R 38 Vpp 1 0 NOTES 1 Oscillation frequency and Xy input frequency data are for oscillator characteristics only 2 Stabilization time is the interv
85. 16 2316 SAM47 INSTRUCTION SET R EF Reference Instruction REF Operation Description dst NOTE The instruction referenced by REF determines the instruction cycles The REF instruction is used to rewrite into 1 byte form arbitrary 2 byte or 3 byte instructions or two 1 byte instructions stored in the REF instruction reference area in program memory REF reduces the number of program memory accesses for a program 1 7 0 TJP and TCALL are 2 byte pseudo instructions that are used only to specify the reference area 1 When the reference area is specified by the TJP instruction 7 6 00 PC13 0 lt 5 0 memc 1 7 0 2 When reference area is specified by the TCALL instruction memc 7 6 01 5 4 SP 1 SP 2 12 0 SP 3 EMB ERB PC13 12 PC13 0 lt memc 5 0 memc 1 7 0 SP SP 4 When the reference area is specified by any other instruction the and memc 1 instructions are executed Instructions referenced by REF occupy 2 bytes of memory space for two 1 byte instructions or one 2 byte instruction and must be written as an even number from 0020H to 007FH in ROM In addition the destination address of the and TCALL instructions must be located with the 3FFFH address and TCALL are reference instructions for JP JPS and CALL CALLS If the instruction following a REF is subject to the redundancy effect the redundant instruc
86. 308 2316 2316 BIST Bit Test and Skip on True BTST Examples 5 40 Continued 2 You can use BTST in the same way to test a port pin address bit BTST P2 0 If P2 0 1 then skip RET If P2 0 0 then return JP LABEL3 3 P2 2 P2 3 and P3 0 P3 3 are tested LD L 0AH BP2 BTST P1 L First P1 OAH P2 2 1111008 10B 10B 0F2H 2 RET INCS L JR BP2 4 Bank 0 location 0A0H 0 is tested and regardless of the current EMB value BTST has the following effect FLAG EQU 0 BITR EMB LD H 0AH BTST H FLAG If bank 0 AH 0H 0 0 1 then skip RET ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET BISTZ Bit Test and Skip on True Clear Bit BTSTZ dst b Test specified bit skip and clear if memory bit is set Description The specified bit within the destination operand is tested If itis a 1 the instruction immediately following the BTSTZ instruction is skipped otherwise the instruction following the BTSTZ is executed The destination bit value is cleared me Skip if mema b 1 and clear 1 Skip if memb 7 2 L 3 2 L 1 0 1 and clear H DAb 11 11 11 11 11 11 0 1 Skipif H DA3 0 b 1 and clear o bt bo a2 at 20 wama i s 161 a2 at FOH FFFH Examples 1 Port pin P2 0 is
87. 308 2316 2316 JP Jump JP Operation Description Example 5 56 dst ADR14 Jump to direct address 14 bits JP causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand The destination can be anywhere in the 16 K byte program memory address space oprana Binary Gods Operation Notation aa PO13 0 ADRIS O o o as aia fart a so ao as ss es eo ar so The label is assigned to the instruction at program location 07FFH The instruction JP SYSCON at location 0123H will load the program counter with the value 07FFH ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET J PS Jump Short JPS Operation Description Example dst ADR12 Jump direct in page 12 bits JPS causes an unconditional branch to the indicated address with the 4 K byte program memory address space Bits 0 11 of the program counter are replaced with the directly specified address The destination address for this jump is specified to the assembler by a label or by an actual address in program memory ADR12 1 ato a9 13 12 13 12 rar sss oe The label SUB is assigned to the instruction at program memory location OOFFH The instruction JPS SUB at l
88. 30H 2 0 2 You can use BITR in the same way to manipulate a port address bit BITR P2 0 P2 0 lt 0 ELECTRONICS 5 31 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 BITR Bit Reset BITR Continued Examples 3 For clearing P2 2 P2 3 and P3 0 P3 3 to 0 BP2 LD L 0AH BITR P1 L First 1 P2 2 1111008 10B 10B 0F2H 2 INCS L JR BP2 4 f bank 0 location 0 is cleared and regardless of whether the EMB value is logic zero BITR has the following effect FLAG EQU 0 BITR EMB LD H 0AH BITR H FLAG Bank 0 0H 0 0A0H 0 lt 0 NOTE Since the BITR instruction is used for output functions the pin names used in the examples above may change for different devices in the SAM47 product family 5 32 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET BITS BITS dst b Das Serspecfied memory bi Te H DA b Description This instruction sets the specified bit within the destination without affecting any other bits in the destination BITS can manipulate any bit that is addressable using direct or indirect addressing modes operand Binary Gods Operation me w o 9 o paso Far 6 o sz at _ nes memb L memb 7 2 L 3 2 b L 1 0 lt 1 aa a o o bt bo 22 at a0 Second Byte Bi
89. 4 The standard stabilization time for system clock oscillation following a RESET is 31 3 ms at 4 19 MHz NOTES 11 4 ELECTRONICS 557 2308 2308 2316 2316 TIMERS TIMER COUNTERS BASIC TIMER COUNTER BCNT BCNT is an 8 bit counter for the basic timer It can be addressed by 8 bit read instructions RESET leaves the BCNT counter value undetermined BCNT is automatically cleared to logic zero whenever the BMOD register control bit BMOD 3 is set to 1 to restart the basic timer It is incremented each time a clock pulse of the frequency determined by the current BMOD bit settings is detected When BCNT has incremented to hexadecimal FFH 255 clock pulses it is cleared to OOH and an overflow is generated The overflow causes the interrupt request flag IRQB to be set to logic one When the interrupt request is generated BCNT immediately resumes counting with incoming clock signal NOTE Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing If after two consecutive reads the BCNT values match you can select the latter value as valid data Until the results of the consecutive reads match however the read operation must be repeated until the validation condition is met BASIC TIMER OPERATION SEQUENCE The basic timer s sequence of operations may be summarized as follows Set counter buffer bit BMOD 3 to logic one to restart the bas
90. 40 PIN CONNECTOR 40 PIN CONNECTOR EXTERNAL TRIGGERS on 5 1248 Figure 17 2 TB572308A 16A Target Board Configuration ELECTRONICS 17 3 DEVELOPMENT TOOLS 557 2308 2308 2316 2316 Table 17 1 Power Selection Settings for TB572308A 16A To User Vcc Settings Operating Mode To User Vcc The SMDS2 SMDS2 TB570502A supplies Vcc to the target OFF ON 0504A TARGET board evaluation chip and SYSTEM the target system To User Vcc The SMDS2 SMDS2 1B572308A supplies Vcc only to the 16 External TARGET target board evaluation Voc SYSTEM chip The target system Vss gt must have its own power supply SMDS2 SMDS2 Table 17 2 Main clock Selection Settings for TB572308A 16A Sub Clock Setting Operating Mode Set the XI switch to MDS EVA CHIP when the target board is KS57E2308 connected to the SMDS2 SMDS2 connection 100 pin connector SMDS2 SMDS2 Set the XI switch to XTAL when the target board is used EVA CHIP as a standalone unit and is KS57E2308 not connected to the SMDS2 SMDS2 XN XouT m TARGET BOARD 17 4 ELECTRONICS 557 2308 2308 2316 2316 DEVELOPMENT TOOLS Table 17 3 Sub clock Selection Settings for TB572308A 16A Sub Clock Setting Operating Mode Set the XTI switch to MDS EVA CHIP when the target board is KS57E2308 connected to the n SMDS2 SMDS2 connec
91. 6 1 6 0 7 5 PROGRAMMING Configuring I O Ports to Input or Output Configure ports 3 and 6 as an output port BITS EMB SMB 15 LD EA 0FFH LD PMG1 EA P6 c Output PULL UP RESISTOR MODE REGISTER PUMOD The pull up resistor mode registers PUMOD1 and PUMOD2 are used to assign internal pull up resistors by software to specific ports When a configurable port pin is used as an output pin its assigned pull up resistor is automatically disabled even though the pin s pull up is enabled by a corresponding PUMOD bit setting PUMOD is addressable by 8 bit write instructions only and PUMOD by 4 bit write instruction only RESET clears PUMOD register values to logic zero automatically disconnecting all software assignable port pull up resistors Table 10 4 Pull Up Resistor Mode Register PUMOD Organization PUMOD ID Bit 3 7 Bit 2 6 Bit 1 5 Bit 0 4 PUMOD FDCH PUR3 PUR2 PUR1 PURO FDDH PUR7 PUR6 PUR5 PUR4 NOTE When bit 1 a pull up resistor is assigned to the corresponding I O port for port 3 for port 2 and so on ELECTRONICS 10 3 VO PORTS 557 2308 2308 2316 2316 PROGRAMMING Enabling and Disabling I O Port Pull Up Resistors P2 and are enabled to be pull up resistors BITS EMB SMB 15 LD EA 0CH LD PUMOD EA enable the pull up resistors of P2 and P3 N CHANNEL OPEN DRAIN MODE REGISTER PNE The n channel open drain
92. 7H C t ADS Skip this instruction because C 1 after ADC result JPS XXX 3 4 decimal addition the contents of the address specified by the HL register is 4H RCF 0 LD A 3H ADS A 6H A 3H 6H 9H ADC A HL A lt 9H 4H C 0 0 ADS A 0AH No skip lt 7H The skip function for ADS is inhibited after an ADC A HL instruction even if an overflow occurs JPS XXX ELECTRONICS 5 27 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 D Logical And AND dst src Logical AND A immediate data to A A HL Logical AND A indirect data memory to A d EA RR Logical AND register pair RR to EA 2 RRb EA Logical AND EA to register pair RRb Description The source operand is logically ANDed with the destination operand The result is stored in the destination The logical AND operation results in 1 whenever the corresponding bits in the two operands are both 1 otherwise a 0 bit is stored The contents of the source are unaffected Operand Binary Code operation Notation 1 a 0 olol acannon e C pote o If the extended accumulator contains the value 11000011 and register pair HL the value 55H 01010101 the instruction AND EA HL leaves the value 41H
93. C 1 8 V to 5 5 V Clock Parameter Test Condition Typ Configuration Crystal XTIN XToU Oscillation frequency 1 32 768 35 kHz Oscillator i C2 s NoosisVeasv a ME LL Clock input high and low 15 us level width txTL txTH NOTES 1 Oscillation frequency XT y input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillating stabilization after a power on occurs Table 14 5 Input Output Capacitance TA 25 C Vpp 0 V Brama Input f 1 MHz Unmeasured pins capacitance are returned to Vss Output COUT capacitance capacitance LECTRONI 14 6 ELECTRONICS 557 2308 2308 2316 2316 ELECTRICAL DATA Table 14 6 A C Electrical Characteristics TA 40 C to 85 C 1 8 V to 5 5 V With subsystem clock fxt 14 frequency 1 8 V to 5 5V TCLO high tTiLo Vpp 2 7 V to 5 5 V ft SCK cycle time Vpp 2 7 V to 5 5 V External source Internal scK source Vpp 1 8 V to 5 5 V External source Internal scK source SCK high low 1 8 V to 5 5 V ns width External source Internal sCK source 1 8 V to 5 5 V 1600 External source _ Internal scK source 2 150 SI setup time to tsIK External scK source Internal scK source 51 hold time to External SCK source Internal sour
94. CAL DATA TIMING WAVEFORMS INTERNAL RESET lt STOP MODE U IDLE MODE Y p OPERATING 4 RETENTION MODE gt 4 EXECUTION OF STOP INSTRUCTION Figure 14 2 Stop Mode Release Timing When Initiated By RESET IDLE MODE NORMAL STOP MODF OPERATING 4 DATA RETENTION 4 STOP INSTRUCTION POWER DOWN MODE TERMINATING SIGNAL INTERRUPT REQUEST Figure 14 3 Stop Mode Release Timing When Initiated By Interrupt Request ELECTRONICS 14 9 ELECTRICAL DATA 557 2308 2308 2316 2316 0 8 Vpp 0 8 Vpp MEASUREMENT POINTS 0 2 Vp 47 0 2 Vpp Figure 14 4 A C Timing Measurement Points Except for XIN and XTIN Figure 14 5 Clock Timing Measurement at XIN Figure 14 6 Clock Timing Measurement at XTIN 14 10 ELECTRONICS 557 2308 2308 2316 2316 ELECTRICAL DATA Figure 14 7 TCLO Timing Figure 14 8 Input Timing for RESET Signal INTO 1 2 4 KSO to KS7 Figure 14 9 Input Timing for External Interrupts and Quasi Interrupts ELECTRONICS 14 11 ELECTRICAL DATA 557 2308 2308 2316 2316 OUTPUT DATA Figure 14 10 Serial Data Transfer Timing 14 12 ELECTRONICS 557 2308 2308 2316 2316 MECHANICAL DATA MECHANICAL DATA This section contains the following information about the device package Package dimensions in millimeters Pad diagram Pad
95. CD Clock Signal LCDCK Frame Frequency and LCD sync Signal LCDSY LCDCK frequency Static 1 2 Duty 1 3 Duty 1 4 Duty fw 29 64 Hz 64 16 32 16 21 21 16 16 fw 28 128 Hz 128 32 64 32 43 43 32 32 fw 27 256 Hz 256 64 128 64 85 85 64 64 fw 26 512 Hz 512 128 256 128 171 171 128 128 NOTES 1 fw 32 768 kHz 2 The number in parentheses is a frequency for LCDSY LCD DRIVE VOLTAGE LCD Power Supply 1 2 Bias 1 3 Bias NOTE TheLCD panel display may deteriorate if DC voltage is applied between the common and segment signals Therefore always drive the LCD panel with AC voltage LCD VOLTAGE DIVIDING RESISTORS On chip voltage dividing resistors for the LCD drive power supply can be configured by internal voltage dividing resistors Using these internal voltage dividing resistors you can drive either a 3 V or a5 V LCD display using external bias Bias pins are connected externally to the V cp pin so that it can handle the different LCD drive voltages To cut off the current supply to the voltage dividing resistors clear LCON 0 when you turn the LCD display off 12 6 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER Static and 1 3 Bias VLCD Vat VDD 5 V 1 2 Bias VL CD 2 5 Vpp 5 V BIAS PIN Static and 1 3 Bias VLCD 5 Vat VDD 5 V Static and 1 3 Bias VLCD V at VDD 3 V R Voltage dividing resistor R External resistor Figure 12
96. CO can be used to measure specific time intervals TCO has a reloadable counter that consists of two parts an 8 bit reference register TREFO into which you write the counter reference value and an 8 bit counter register TCNTO whose value is automatically incremented by counter logic An 8 bit mode register TMODO is used to activate the timer counter and to select the basic clock frequency to be used for timer counter operations To dynamically modify the basic frequency new values can be loaded into the TMODO register during program execution 0 FUNCTION SUMMARY 8 bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency External event counter Counts various system events based on edge detection of external clock signals at the TCO input pin TCLO To start the event counting operation TMODO 2 is set to 1 and TMODO 6 is cleared to 0 Arbitrary frequency output Outputs selectable clock frequencies to the TCO output pin TCLOO External signal divider Divides the frequency of an incoming external clock signal according to a modifiable reference value TREFO and outputs the modified frequency to the TCLOO pin Serial I O clock source Outputs a modifiable clock signal for use as the SCK clock source ELECTRONICS 11 9 TIMERS TIMER COUNTERS TCO COMPONENT SUMMARY Mode register Reference register TREFO Counter register TCNTO Clock selec
97. CT OVERVIEW 557 2308 2308 2316 2316 PULL UP RESISTOR RESISTOR ENABLE ENABLE LCD SEGMENT amp PORT 8 DATA CIRCUIT TYPE A Figure 1 7 Pin Circuit Type E P4 P5 Figure 1 9 Pin Circuit H 16 8 LCD SEGMENT COMMON DATA SCHMITT TRIGGER Figure 1 8 Pin Circuit Type H 15 SEG COM Figure 1 10 Pin Circuit Type B RESET 1 8 ELECTRONICS 557 2308 2308 2316 2316 ADDRESS SPACES ADDRESS SPACES PROGRAM MEMORY ROM OVERVIEW ROM maps for KS57C2 308 C2316 devices are mask programmable at the factory KS57C2308 has 8K x 8 bit program memory and KS57C2316 has 16K x 8 bit program memory aside from the differences in the ROM size the two products are identical in other features In its standard configuration the device s 8 192 x 8 bit 16 384 x 8 bit program memory has four areas that are directly addressable by the program counter PC 12 byte area for vector addresses 96 byte instruction reference area 20 byte general purpose area 8064 byte general purpose area KS57C2308 16256 byte general purpose area KS57C2316 General Purpose Program Memory Two program memory areas are allocated for general purpose use One area is 20 bytes in size and the other is 8 064 bytes 16 256 bytes Vector Addresses A 12 byte vector address area is used to store the vector addresses required to execute system resets and interrupts Start addresses
98. E REGISTER WDMOD The watchdog timer mode register WDMOD is a 8 bit write only register located at RAM address F98H F99H WDMOD register controls to enable or disable the watchdog function WOMOD values are set to logic A5H following RESET and this value enables the watchdog timer and watchdog timer is set to the longest interval because BT overflow signal is generated with the longest interval Watchdog Timer Enable Disable Control 5AH Disable watchdog timer function Any other value Enable watchdog timer function WATCHDOG TIMER COUNTER WDCNT The watchdog timer counter WDCNT is a 3 bit counter WDCNT is automatically cleared to logic zero and restarts whenever the WDTCF register control bit is set to 1 RESET stop and wait signal clears the WDONT to logic zero also WDONT increments each time a clock pulse of the overflow frequency determined by the current BMOD bit setting is generated When WDCNT has incremented to hexadecimal 07H it is cleared to and an overflow is generated The overflow causes the system RESET When the interrupt request is generated BCNT immediately resumes counting incoming clock signals WATCHDOG TIMER COUNTER CLEAR FLAG WDTCF The watchdog timer counter clear flag WDTCF is a 1 bit write instruction When WDTCF is set to one it clears the WDCNT to zero and restarts the WDCNT WDTCF register bits 2 0 are always logic zero Table 11 3 Watchdog Timer Interv
99. EA LD YZ EA POP EA POP EA register contents from stack POP YZ POP YZ register contents from stack POP WX POP WX register contents from stack POP HL POPHL register contents from stack POP SB POP current SMB SRB IRET The POP instructions execute alternately with the PUSH instructions If an SMB n instruction is used in an interrupt service routine a PUSH and POP SB instruction must be used to store and restore the current SMB and SRB values as shown in Example 2 below 2 When ERB 2 1 VENT2 1 1 INTO lt 1 ERB lt 1 Jump to INTO address INTO PUSH SB Store current SMB SRB SRB 2 Select register bank 2 because of ERB 1 SMB 0 LD EA 00H LD 80H EA LD HL 40H INCS HL LD WX EA LD YZ EA POP SB Restore SMB SRB IRET ELECTRONICS 2 11 ADDRESS SPACES 557 2308 2308 2316 2316 STACK OPERATIONS STACK POINTER SP The stack pointer SP is an 8 bit register that stores the address used to access the stack an area of data memory set aside for temporary storage of data and addresses The SP can be read or written by 8 bit control instructions When addressing the SP bit 0 must always remain cleared to logic zero F80H SP3 SP2 5 1 o F81H SP7 SP6 SP5 SP4 There are two basic stack operations writing to the top of the stack push and reading from the top of the stack pop A push decrements the SP and a pop increments it so that the SP always points to the top address of
100. EPROM verify EPROM read protection NOTE 0 means low level 1 means high level exu ELECTRONICS 16 3 557 2308 2316 557 2308 2308 2316 2316 Table 16 4 Absolute Maximum Ratings Ta 25 C Parameter Conditions Supply Voltage Input Voltage All I O ports 0 3 to Vpp 0 3 0 3 to Vpp 0 3 One I O pin active mA All I O ports active Output Current Low One I O pin active 30 Peak value Units Output Voltage Output Current High Total value for ports 0 2 3 and 5 100 Peak value Total value for ports 4 6 and 7 Operating Temperature 40 to 85 C NOTE The values for Output Current Low are calculated as Peak Value x A Duty Table 16 5 D C Electrical Characteristics Ta 40 C to 85 C Vpp 1 8 V to 5 5 V Input high Vind All input pins except those 0 7 voltage specified below for Vino cee ONE Xin m Xn and Output high Vout Vpp 4 5 V to 5 5 V voltage Ports 0 2 3 4 5 6 7 and BIAS 1 Vpp 4 5V to 5 5V Port 8 ONLY lop 100 pA 16 4 ELECTRONICS 557 2308 2308 2316 2316 557 2308 2316 Table 16 5 D C Electrical Characteristics Continued TA 40 C to 85 C Vpp 1 8 V to 5 5 V Output low Vout Vpp 4 5 V to 5 5 V Ports 0 2 7 voltage lg 15 mA VoL2 Vpp 4 5 V to 5 5 V Port 8 only loL 100 pA Input high
101. ESET Occurs During or Subcomponent Power Down Mode Normal Operation Ports Pull up resistor mode reg NE O Basic Timer Count register BCNT Mode register BMOD Timer Counters 0 and 1 Reference a T FFH Watchdog Timer WDT mode register WDMOD WDT clear flag WDTCF Watch Timer Watch timer mode register WMOD b 00 SE LCD Driver Controller Display data memory Undefined Serial Interface SIO interface SBU i Undefined am ELECTI 5 RON 9 3 RESET 9 4 NOTES 557 2308 2308 2316 2316 ELECTRONICS 557 2308 2308 2316 2316 VO PORTS PORTS OVERVIEW The KS57C2308 C2316 has 9 ports There total of 8 input pins 8 output and 24 configurable I O pins for a maximum number of 40 pins Pin addresses for all ports are mapped to bank 15 of the RAM The contents of I O port pin latches can be read written or tested at the corresponding address using bit manipulation instructions Port Mode Flags Port mode flags PM are used to configure ports to input or output mode by setting or clearing the corresponding I O buffer Pull Up Resistor Mode Register PUMOD The pull up resistor mode registers PUMOD are used to assign internal pull up resistors by software to specific ports When a configurable I O port pin is used as an output pin its assigned pull up resistor is automatically disabled even though the pin s pull up is ena
102. FH Code direct addressing 0020 007 Select bank register 8 bits Logical exclusive OR Logical OR Logical AND Contents addressed by RR ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET OPCODE DEFINITIONS Table 5 7 Opcode Definitions Direct Table 5 8 Opcode Definitions Indirect om n m HL 1 0 1 WX 1 1 0 WL 1 1 1 i Immediate data for indirect addressing om 0 0 0 0 1 1 1 1 0 0 1 1 PIP 999 9 9 r Immediate data for register CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS A machine cycle is defined as one cycle of the selected CPU clock Three different clock rates can be selected using the PCON register In this document the letter S is used in tables when describing the number of additional machine cycles required for an instruction to execute given that the instruction has a skip function S skip The addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped whether it is a 1 byte 2 byte or 3 byte instruction A skip is also executed for SMB and SRB instructions The values in additional machine cycles for 5 for the three cases in which skip conditions occur are as follows Case 1 No skip S 0 cycles Case 2 Skip is 1 byte or 2 byte instruction S 1 cycle Case 3 Skip is 3 byte instruction S 2 cycles NOTE REF instructions are skipp
103. H 7FH LD SBUF EA LD EA 4FH LD SMOD EA 510 start BITS IES STEST BTSTZ IRQS JR STEST LD EA SBUF SMB 0 LD RDATA EA RDATA address 20 7 ELECTRONICS 13 5 SERIAL I O INTERFACE 557 2308 2308 2316 2316 5 PROGRAMMING Setting Transmit Receive Modes for Serial I O Continued 3 Transmit and receive Data through SIO interface using an internal clock frequency of 4 09 kHz at 4 19 MHz in LSB first mode BITR EMB LD EA TDATA TDATA address BANKO 20H 7FH LD SBUF EA LD LD SMOD EA 510 start 5 IES INTS PUSH SB Store SMB SRB PUSH EA Store EA BITR EMB LD EA TDATA EA lt Transmit data TDATA address BANKO 20 7 EA SBUF Transmit data lt gt Receive data LD RDATA EA address BANKO 20H 7FH BITS SMOD 3 510 start POP EA POP SB IRET SCK po EXTERNAL SO P0 2 DEVICE SI P0 3 KS57C2308 C2316 ELECTRONICS 13 6 Bg 557 2308 2308 2316 2316 SERIAL I O INTERFACE I PROGRAMMING TIP Setting Transmit Receive Modes for Serial I O Continued 4 Transmit and receive Data through SIO interface using an external clock in LSB first mode BITR EMB LD EA TDATA TDATA address BANKO 20H 7FH LD SBUF EA LD EA 0FH LD SMOD EA 510 start 5 IES INTS PUSH SB Store SMB SRB PUSH EA Store EA BITR EMB LD EA TDATA EA lt Transmit data TDATA address BANKO 20 7 EA SBUF
104. HL 1101 1 A HL then L L 1 skip if L OH XCHD A HL 1101 1 1 A then L L 1 skip i if L OFH Cp pepe E o ET 26 as as a2 at 40 ERRE 5 16 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET Table 5 17 Data Transfer Instructions Binary Code Summary Continued Ra im RR imm EA HL EA DA EA RRb RRb EA HL EA RII 7070 2 1 cere ee RR lt imm ________ DA amp A een 0 EM 4 Far ss ss ot at Fe EE EA lt RRb ERE ee DA 1 Eie pata tits fofeala o toi i o o lmjeame y A HL A lt HL then L lt L 1 skip L 0H A HL 1 A lt HL then L lt L 1 skip L mow 5 Exam fefefe fcre em ELECTRONICS 1 C 0 A n 1 lt 1 2 ES 1 r2 aly 1 5 2 2 1 1 1 a 1 lt SMB 5 2 lt SRB c 2 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Table 5 17 Data Transfer Instructions Binary Code Summary Concluded operand Binary
105. LCD segment data Pin addresses that are not used for LCD segment output can be used for normal 1 bit output LECTRONI 10 4 ELECTRONICS 557 2308 2308 2316 2316 VO PORTS Table 10 6 Port 8 Pin Addresses and LCD Segment Correspondence Port 8 Pin Number RAM Address LCD Segment P8 0 1F8H SEG24 P8 1 1F9H SEG25 P8 4 1FCH SEG28 P8 5 1FDH SEG29 ELECTRONICS 10 5 VO PORTS 557 2308 2308 2316 2316 PORT 0 CIRCUIT DIAGRAM PUMOD 0 4 gt 0 PO O INT4 1 52 P0 2 SO 3 5 When and SO act as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD Figure 10 1 Port 0 Circuit Diagram 10 6 ELECTRONICS 557 2308 2308 2316 2316 VO PORTS PORT 1 CIRCUIT DIAGRAM INTO INT1 INT2 TCLO Clock Selector CPU clock fxx 64 Figure 10 2 Port 1 Circuit Diagram ELECTRONICS 10 7 VO PORTS 557 2308 2308 2316 2316 PORT 2 CIRCUIT DIAGRAM PUMOD 2 P2 0 TCLOO P2 1 P2 2 CLO P2 3 BUZ NOTE When a port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD Figure 10 3 Port 2 Circuit Diagram 10 8 ELECTRONICS 557 2308 2308 2316 2316 VO PORTS PORT 3 AND 6 CIRCUIT DIAGRAM X port number 3 6 NOTE
106. LE or STOP instruction in a program In idle mode the CPU clock stops while peripherals and the oscillation source continue to operate normally When RESET occurs during normal operation or during a power down mode a reset operation is initiated and the CPU enters idle mode When the standard oscillation stabilization time interval 31 3 ms at 4 19 MHz has elapsed normal CPU operation resumes In main stop mode main system clock oscillation is halted assuming main clock is selected as system clock and it is currently operating and peripheral hardware components powered down sub stop mode assuming sub clock is selected sub system clock oscillation is halted by setting SCMOD 2 to 1 The effect of stop mode on specific peripheral hardware components CPU basic timer timer counter 0 watch timer and LCD controller serial and on external interrupt requests is detailed in Table 8 1 NOTE Do not use stop mode if you are using an external clock source because Xy input must be restricted internally to to reduce current leakage Idle or main stop modes are terminated either by a RESET or by an interrupt which is enabled by the corresponding interrupt enable flag IEx When power down mode is terminated by RESET a normal reset operation is executed Assuming that both the interrupt enable flag and the interrupt request flag are set to 1 power down mode is released immediately upon entering power down m
107. M Address Structure 3 2 ELECTRONICS 557 2308 2308 2316 2316 ADDRESSING MODES EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt vector address When a RESET is generated internally bit 7 of program memory address OOOOH is written to the EMB flag initializing it automatically When a vectored interrupt is generated bit 7 of the respective vector address table is written to the EMB This automatically sets the EMB flag status for the interrupt service routine When the interrupt is serviced the EMB value is automatically saved to stack and then restored when the interrupt routine has completed At the beginning of a program the initial EMB and ERB flag values for each vectored interrupt must be set by using VENT instruction The EMB and ERB can be set or reset by bit manipulation instructions BITS BITR despite the current SMB setting 5 PROGRAMMING Initializing the EMB and ERB Flags The following assembly instructions show how to initialize the EMB and ERB flag settings ORG 0000 ROM address assignment VENTO 1 0 RESET lt 1 ERB lt 0 branch RESET VENT1 0 1 INTB EMB 0 ERB 1 branch INTB VENT2 0 1 INTO lt 0 ERB 1 branch INTO VENTS3 0 1 INT1 EMB lt 0 ERB lt 1 branch INT1 VENT4 0 1 INTS EMB 0 ERB lt 1 branch INTS VENTS 0 1 INTTO lt 0 ERB lt 1 b
108. NOP NOP 5 70 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET OR Logical OR OR dst src Logical OR immediate data to A A HL Logical OR indirect data memory contents to A EA RR Logical OR double register to EA RRb EA Logical OR EA to double register Description source operand is logically ORed with the destination operand The result is stored in the destination The contents of the source are unaffected Operand Binary Code operation Notation a a e a e Ken 1 If the accumulator contains the value 11000011 and register pair HL the value 55H 01010101B the instruction OR EA QHL leaves the value 0D7H 11010111B in the accumulator ELECTRONICS 5 71 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Pop From Stack POP dst SB Pop SMB and SRB values stack W nuna Description The contents of the RAM location addressed by the stack pointer is read and the SP is incremented by two The value read is then transferred to the variable indicated by the destination operand Operand Operation Notation r r RR lt SP lt SP 1 SP SP 2 SRB lt SP SMB lt SP 1 SP SP 2 1 SP value is equal to
109. Not Affected by the EMB Value Addressing Method Affected Hardware Program Examples 000 4 bit indirect addressing using Not applicable LD A WX and WL register pairs 8 bit indirect addressing using SP PUSH EA POP EA FBOH FBFH 1 bit direct addressing PSW SCMOD BITS EMB FFOH FFFH IEx IRQx I O BITR IE4 FCOH FFFH 1 bit indirect addressing using the BSC I O BTST FC3H L L register BAND C P3 L 3 4 ELECTRONICS 557 2308 2308 2316 2316 ADDRESSING MODES SELECT BANK REGISTER SB The select bank register SB is used to assign the memory bank and register bank The 8 bit SB register consists of the 4 bit select register bank register SRB and the 4 bit select memory bank register SMB as shown in Figure 3 2 During interrupts and subroutine calls SB register contents can be saved to stack in 8 bit units by the PUSH SB instruction You later restore the value to the SB using the POP SB instruction lt SMB F83H lt SRB F82H M T SMB3 SMB2 SMB1 SMB 0 SRB 1 SRB 0 Figure 3 2 SMB and SRB Values in the SB Register Select Register Bank SRB Instruction The select register bank SRB value specifies which register bank is to be used as a working register bank The SRB value is set by the SRB n instruction where n 0 1 2 3 One of the four register banks is selected by the combination of ERB flag status and the SRB value that is set us
110. O Bit Manipulation for Multi Level Interrupt Handling Before INT Effect of Isx Bit Setting After INT ACK 51 iso 160 0 o o _ Alinterupt requests are seniced l current settings in the IPR register are serviced __2 1 Noadditonalinterrupt requests will be serviced ___ 1 1 __ Normal Program Single Processing Int Status 0 2 Level INT Disable Interrupt 3 Level SET IPR INT Disable Status 1 Interrupt INT Enable Modify Status P Low or High INT Enable Status 0 Level Interrupt Low or High High Level Generated Level Interrupt Interrupt Status 1 Generated Generated Figure 7 4 Multi Level Interrupt Handling LECTRONI 7 6 ELECTRONICS 557 2308 2308 2316 2316 INTERRUPTS INTERRUPT PRIORITY REGISTER IPR The 4 bit interrupt priority register IPR is used to control multi level interrupt handling Its reset value is logic zero Before the IPR can be modified by 4 bit write instructions all interrupts must first be disabled by a DI instruction By manipulating the IPR settings you can choose to process all interrupt requests with the same priority level or you can select one type of interrupt for high priority processing A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt cannot be interrupted
111. OM code from HEX file which has been produced by assembler ROM code must be needed to fabricate a microcontroller which has a mask ROM When generating the ROM code file by HEX2ROM the value FF is filled into the unused ROM area upto the maximum ROM size of the target device automatically TARGET BOARDS Target boards are available for all KS57 series microcontrollers All required target system cables and adapters are included with the device specific target board OTPs One time programmable microcontroller OTP for the KS57C2308 C2316 microcontroller and OTP programmer Gang are now available ELECTRONICS 17 1 DEVELOPMENT TOOLS 557 2308 2308 2316 2316 Compatible SMDS2 TARGET lt PROM MTP WRITER UNIT APPLICATION SYSTEM gt RAM BREAK DISPLAY UNIT PROBE ADAPTER TRACE TIMER UNIT n TB572308A 16A lt SAM4 BASE UNIT TARGET BOARD gt POWER SUPPLY UNIT Figure 17 1 SMDS Product Configuration SMDS2 17 2 ELECTRONICS 557 2308 2308 2316 2316 DEVELOPMENT TOOLS 572308 16 TARGET BOARD The TB572308A 16A target board is used for the KS57C2308 P2308 C231 6 P2316 microcontroller It is supported by the SMDS2 development system 572308 16 To User Vcc ON 23 IDLE STOP 2100 144 QFP 557 2308 O 2 2 Br e e
112. P8 2 SEG26 VLC0 P8 3 SEG27 VLC1 P8 4 SEG28 VLC2 P8 5 SEG29 VDD KS57C2308 P8 6 SEG30 Vss KS57C2316 P8 7 SEG31 P7 3 KS7 O GQ XOUT TOP VIEW XIN P7 2 KS6 TEST P7 1 KS5 XTIN P7 0 KS4 XTOUT P6 3 KS3 RESET P6 2 KS2 PO O INT4 P6 1 KS1 P0 1 SCK P6 0 KSO P0 2 SO P5 3 P0 3 SI 5 2 P1 0 INTO P5 1 P1 3 TCLO H 27 P2 2 CLO H 30 P2 3 BUZ O 31 P3 0 LCDCK 32 P3 1 SCDSY O 33 P1 1 INT1 H 25 P1 2 INT2 H 26 P2 0 TCLOO 28 Figure 1 2 KS57C2308 C2316 80 QFP Pin Assignment Diagram 1 4 ELECTRONICS 557 2308 2308 2316 2316 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1 1 KS57C2308 C2316 Pin Descriptions Description Reset Circuit We Value Type 4 bit input port Input Jo 1 bit and 4 bit read and test are possible 4 bit pull up resistors are software assignable 4 bit input port 1 bit and 4 bit read and test are possible 4 bit pull up resistors are software assignable 4 bit I O port TCLOO 1 bit and 4 bit read write and test are possible 4 bit pull up resistors are software assignable CLO BUZ 4 bit I O port LCDCK 1 bit and 4 bit read write and test are possible LCDSY Each individual pin can be specified as input or output 4 bit pull up resistors are software assignable 4 bit ports N channel open drain output up to 5 V 1 4 and 8 bit read write and test are possible Ports 4 and 5 can be paired to support 8 bit data transfer 4 bit pull up resistors are soft
113. PT STATUS FLAGS 150 151 PSW bits 150 and 151 contain the current interrupt execution status values You can manipulate ISO and 151 flags directly using 1 bit RAM control instructions By manipulating interrupt status flags in conjunction with the interrupt priority register IPR you can process multiple interrupts by anticipating the next interrupt in an execution sequence The interrupt priority control circuit determines the ISO and 151 settings in order to control multiple interrupt processing When both interrupt status flags are set to 0 all interrupts are allowed The priority with which interrupts are processed is then determined by the IPR When an interrupt occurs ISO and 151 are pushed to the stack as part of the PSW and are automatically incremented to the next higher priority level Then when the interrupt service routine ends with an IRET instruction 150 and 151 values are restored to the PSW Table 2 6 shows the effects of ISO and 151 flag settings Table 2 6 Interrupt Status Flag Bit Settings 151 150 Status of Currently Effect of ISO and IS1 Settings Value Value Executing Process on Interrupt Request Control __ f o Alinteruptrequests are serviced 1 1 Only high priority interrupt s as determined in the interrupt priority register IPR are serviced pt 202 s Nomoreinterupt requests are serviced du ox Not applicable these bit settings are undefined Since interrupt status flags
114. R WX Current PC13 8 10H WX 00H 1000 Jump to address 1000H and execute JPS AAA 3 Here is another example ORG 1100H LD A 0H LD A 1H LD A 2H LD A 3H LD 30H A Address lt A JPS YYY XXX LD EA 00H EA 00H JR QEA Jump to address 1100H Address 30H If LD EA 01H were to be executed in place of LD EA 00H the program would jump to 1001H and address 30H would contain the value 1H If LD 02 were to be executed the jump would be to 1002H and address 30H would contain the value 2H ELECTRONICS 5 59 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 LD Load LD dst src GHLEA Load contents of EA indirect data memory 2 Description The contents of the source are loaded into the destination The source s contents are unaffected N instruction such as LD A im LD EA imm or LD HL imm is written more than two times in succession only the first LD will be executed the other similar instructions that immediately follow the first LD will be treated like a NOP This is called the redundancy effect see examples below Am 7 1 Far ae as at az at Be 0 o 1 a2 do 1 2 07 5 60 ELECTRONICS 557 2308
115. Rb lt RRb EA skip on carry mo T wu propere po 9 9 688 ss Li ACAD spon toros EA RR lt EA skip on borrow 1 0 1 1 1 LR RRb lt RRb EA skip on borrow xs 777141111111 OS 1 1 01 1 1 11 01 0 RR RRA skip on borrow ms e OS DA 1 0 DA DA 1 skip on carry rar as os foe as we ar 20 pep p pep 89e 89 eripe can o risjojojo r o mo oj BRbcHRbet skponcar ELECTRONICS 5 19 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Table 5 20 Bit Manipulation Instructions Binary Code Summary Opeand Binary Code Operation Notation ss Gpe o o Skip it Dab 47 a6 a5 a4 2 at 20 mema EZSESEZRSEZESEXESN Skip if mema b 1 dil L Skip if memb 7 2 1 3 2 L 1 0 1 H DAb 1 1 1 1 1 1 3 0 6 1 ERRE EPE 70 1 1 SkpitDAb O mema bini b tls Skip if mema b 0 ee memb
116. Resistor Control Bit Disconnect port 7 pull up resistor Connect port 7 pull up resistor 1 PUR6 Connect Disconnect Port 6 Pull Up Resistor Control Bit Disconnect port 6 pull up resistor 1 Connect port 6 pull up resistor 5 Connect Disconnect Port 5 Pull Up Resistor Control Disconnect port 5 pull up resistor Connect port 5 pull up resistor 1 PUR4 Connect Disconnect Port 4 Pull Up Resistor Control Bit Disconnect port 4 pull up resistor Connect port 4 pull up resistor PUR3 Connect Disconnect Port 3 Pull Up Resistor Control Bit Disconnect port 3 pull up resistor Connect port 3 pull up resistor PUR2 Connect Disconnect Port 2 Pull Up Resistor Control Bit Disconnect port 2 pull up resistor Connect port 2 pull up resistor 1 PUR1 Connect Disconnect Port 1 Pull Up Resistor Control Bit Disconnect port 1 pull up resistor 1 Connect port 1 pull up resistor PURO Connect Disconnect Port 0 Pull Up Resistor Control Bit Disconnect port 0 pull up resistor Connect port 0 pull up resistor 1 NOTE Pull up resistors for all I O ports are automatically disabled when they are configured to output mode N ELECTRONICS 4 MEMORY 557 2308 2308 2316 2316 SCMOD System Clock Mode Control Register FB7H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W Bit Addressing 1 1 1 1 3 2 and 0 CPU Clock Selection and Main System Clock Oscillation Control Bits 0010 Select main syst
117. S A HL A 0AH XXX 0 lt 4H 0 lt 1 No skip 9H The skip function of ADS is inhibited after SBC A HL instruction even if an overflow occurs SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 SBS Subtract SBS dst src A HL Subtract indirect data memory from A skip on borrow EA RR Subtract register pair RR from EA skip on borrow RRb EA Subtract EA from register pair RRb skip on borrow Description source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected A skip is executed if a borrow occurs The value of the carry flag is not affected i 4 0 t A CA HD sip on borrow ee 1 1 M h risp 1 The accumulator contains the value register pair HL contains the value and the carry flag is cleared to logic zero RCF 0 SBS lt 0C3H 0C7H SBSinstruction skips on borrow butcarry flag value is not affected JPS XXX Skip because a borrow occurred JPS YYY Jump to YYY is executed 2 The accumulator contains the value register pair HL contains the value and the carry flag is set to logic one SCF C lt 1 SBS
118. S EMB SMB 15 LD EA 4CH LD TMODO EA 5 2 Clear IRQTO and and restart TCO counting operation BITS EMB SMB 15 BITS TMODO 3 11 18 ELECTRONICS 557 2308 2308 2316 2316 TIMERS TIMER COUNTERS TCO COUNTER REGISTER The 8 bit counter register for timer counter 0 TCNTO is read only and can be addressed by 8 bit RAM control instructions RESET sets all TCNTO register values to logic zero OOH Whenever 3 is enabled is cleared to logic zero and counting resumes TCNTO register value is incremented at the selected edge each time an incoming pulse with reference clock specified by TMODO register specifically TMODO 6 TMODO 5 and TMODO 4 is input Each time is incremented the new value is compared with the reference value stored in the TCO reference buffer TREFO When TCNTO TREFO an match signal occurs in the comparator the interrupt request flag IRQTO is set to logic one and an interrupt request is generated to indicate that the specified timer counter interval has elapsed REFERENCE VALUE n pot ste nf of spe m nj o 311 lt INTERVAL TIME TIMER START INSTRUCTION IRQTO SET IRQTO SET TMODO 3 IS SET Figure 11 3 Timing Diagram ELECTRONICS 11 19 TIMERS TIMER COUNTERS 557 2308 2308 2316 2316 TCO REFERENCE REGISTER TREFO The TCO re
119. Vico 2 Vss Vico Vict 2 Vss VLCD 1 2 VI 0 1 2 V LCD VLCD V cD 0 1 2 V LCD VLCD Vicp 1 2 VLCD 0 1 2 V LCD V LCD Figure 12 15 LCD Signal Waveforms at 1 3 Duty 1 2 Bias 12 18 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER Timing Strobe Bit 0 Bit2 ESESET 8 e essere gt x Figure 12 16 LCD Connection Example at 1 3 Duty 1 2 Bias ELECTRONICS 12 19 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 Vss 1 3 Vi 0 1 3 VLCD 1 3 VL CD 0 1 3 VLCD 1 3 VLCD 0 1 3 Vi cD VLCD Figure 12 17 LCD Signal Waveforms at 1 3 Duty 1 3 Bias 12 20 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER Timing Strobe Bit 0 Bit2 cea 3 xd eoe EXEXES alae ea es gt x gt Figure 12 18 LCD Connection Example at 1 3 Duty 1 3 Bias ELECTRONICS 12 21 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 Vico VLC gt Vss
120. al LCDSY for LCD display expansion and to control the flow of current to dividing resistors in the LCD circuit Following a RESET all LCON values are cleared to 0 This turns the LCD display off and stops the flow of current to the dividing resistors The effect of the 0 setting is dependent upon the current setting of LMOD 3 Table 12 2 LCD Control Register LCON Organization LCON 3 o This bit is used for internal testing only always logic zero LCON 2 0 Disable LCDCK and LCDSY signal outputs Enable LCDCK and LCDSY signal outputs LCON 1 Always logic zero LCON O LCD output low display off cut off current to dividing resistor and output port 8 latch contents If LMOD 3 07 LCD display off output port 8 latch contents If LMOD 3 1 COM and SEG output in display mode LCD display Table 12 3 LCON 0 and LMOD 3 Bit Settings LCON O LMOD 3 SEGO SEG31 P amp 0 P87 Output low LCD display off Output low Output latch Cut off current to LCD display off contents dividing resistors COM output corresponds to display SEG output Output latch LCD display on corresponds to contents display mode 1 LCD display off LCD display off Output latch LCD display off contents LECTRONI 12 4 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER LCD MODE REGISTER LMOD The LCD mode control register LMOD is used to control display
121. al Time BMOD BT Input Clock WDCNT Input Clock WDT Interval Time Main Clock Sub frequency frequency Clock x000b fxx 212 x 28 fxx 212 x 28 x 23 1 75 2 224 256 sec fxx 29 x 28 fxx 29 28x 23 218 7 250 28 32 sec fxx 25 x 28 fxx 25 x 28 x 23 13 6 15 6 ms 1 75 2 sec NOTES 1 Clock frequencies assume a system oscillator clock frequency of 4 19 MHz Main clock or 32 768 kHz Sub clock 2 system clock frequency 3 the WDMOD changes such as disable and enable you must set WDTCF flag to 1 for starting WDCNT from zero state ELECTRONICS 11 7 TIMERS TIMER COUNTERS 557 2308 2308 2316 2316 5 PROGRAMMING Using the Watchdog Timer RESET DI BITS EMB SMB 15 LD EA 00H LD SP EA LD A 0DH WDCNT input clock is 7 82 ms LD BMOD A MAIN BITS WDTCF Main routine operation period must be shorter than watchdog timers period JP MAIN LECTRONI 11 8 ELECTRONICS 557 2308 2308 2316 2316 TIMERS TIMER COUNTERS 8 BIT TIMER COUNTER 0 TCO OVERVIEW Timer counter 0 TCO is used to count system events by identifying the transition high to low or low to high of incoming square wave signals To indicate that an event has occurred or that a specified time interval has elapsed TCO generates an interrupt request By counting signal transitions and comparing the current counter value with the reference register value T
122. al required for oscillator stabilization after a power on occurs or when stop mode is terminated ELECTRONICS 16 7 557 2308 2316 557 2308 2308 2316 2316 Table 16 7 Subsystem Clock Oscillator Characteristics TA 40 C 85 C 1 8 V to 5 5 V Clock Parameter Test Condition Typ Configuration Crystal XTIN XTOU Oscillation frequency 1 32 768 35 kHz Oscillator Stabilization time 2 4 5 V to 5 5 V Noosisvwasv 10 ii a m input high and low 15 us level width txTL txTH NOTES 1 Oscillation frequency XT y input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillating stabilization after a power on occurs Table 16 8 Input Output Capacitance TA 25 C 0 V Input CIN f 1 MHz Unmeasured pins capacitance are returned to Vss Output capacitance capacitance ELECTRONICS 16 8 557 2308 2308 2316 2316 557 2308 2316 Table 16 9 Electrical Characteristics TA 40 C to 85 Vpp 1 8 V to 5 5 V OO Instruction cycle Vpp 2 7 V to 5 5 V time 1 Vpp 1 8 V to 4 5 V With subsystem clock fxt TCLO input Vpp 2 7 V to 55V frequency Vpp 18V to 55V Vpp 18V to 550 1 8 V to 5 5V TCLO input ae tTiLo Vpp 2 7 V
123. and register pair HL contains 55H 01010101 the instruction XOR EA HL leaves the value 96H 10010110B in the extended accumulator ELECTRONICS 5 93 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 NOTES 5 94 ELECTRONICS Oscillator Circuits Interrupts Power Down RESET Ports Timers and Timer Counters LCD Controller Driver Electrical Data Mechanical Data KS57P2308 P2316 OTP 557 2308 2308 2316 2316 OSCILLATOR CIRCUITS OSCILLATOR CIRCUITS OVERVIEW The KS57C2308 C2316 microcontroller has two oscillator circuits a main system clock circuit and a subsystem clock circuit The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits Specifically a clock pulse is required by the following peripheral modules LCD controller Basic timer Timer counter 0 Watch timer Clock output circuit Serial I O interface CPU Clock Notation In this document the following notation is used for descriptions of the CPU clock fx Main system clock fxt Subsystem clock fxx Selected system clock ELECTRONICS 6 1 OSCILLATOR CIRCUITS 557 2308 2308 2316 2316 Clock Control Registers When the system clock mode control register SCMOD and the power control register PCON are both cleared to zero after RESET the normal CPU operating mode is enabled a main system clock of fx 64 is selected and main system clock oscillation is initiated PCON is u
124. ations are initiated When the SIO transmission starts SMOD 3 is cleared to logical zero Table 13 1 SIO Mode Register SMOD Organization Most significant bit MSB is transmitted first Least significant bit LSB is transmitted first Receive only mode output buffer is off Transmit and receive mode output buffer is on Disable the data shifter and clock counter retain contents of IRQS flag when serial transmission is halted Enable the data shifter and clock counter set IRQS flag to 1 when serial transmission is completed Clear IRQS flag and 3 bit clock counter to 0 initiate transmission and then reset this bit to logic zero Bit not used value is always 0 SMOD 7 SMOD 6 SMOD 5 Clock Selection R W Status of SBUF External clock at SCK pin SBUF is enabled when SIO operation is halted or when SCK goes high __ 1 UseTOLO clock from TCO 1 CPU clock fxx 4 fxx 8 fxx 64 Enable SBUF read write 1 4 09 kHz clock fxx 210 SBUF is enabled when SIO operation is halted or when SCK goes high 262 kHz clock 6024 NOTES 1 system clock 2 kHz frequency ratings assume a system clock fxx running at 4 19 MHz 3 SIO clock selector circuit cannot select a fxx 2 clock if the CPU clock is fxx 64 ELECTRONICS 13 3 SERIAL I O INTERFACE 557 2308 2308 2316 2316 SERIAL I O TIMING DIAGRAMS Dee Cos X X pa X os X X m X m X s
125. atures of the instruction set The information elements of the instruction description format are as follows Instruction name mnemonic Full instruction name Source destination format of the instruction operand Operation overview from the High Level Summary table Textual description of the instruction s effect Binary code overview from the Binary Code Summary table Programming example s to show how the instruction is used ELECTRONICS 5 23 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 with carry ADC dst src A HL Add indirect data memory to A with carry EA RR Add register pair RR to EA with carry RRb EA Add EA to register pair RRb with carry Description source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected If there is an overflow from the most significant bit of the result the carry flag is set otherwise the carry flag is cleared If ADC is followed by ADS instruction in a program ADC skips the ADS instruction if an overflow occurs If there is no overflow the ADS instruction is executed normally This condition is valid only for ADC A HL instructions If an overflow occurs following an ADS instruction the next instruction will not be skipped oporana Binary Gods Operation Norton aom o o
126. bit indirect addressing For 8 bit indirect addressing an even numbered RAM address must always be used as the instruction operand 1 BIT ADDRESSING Table 3 2 1 Bit Direct and Indirect RAM Addressing Operand Addressing Mode EMB Flag Addressable Memory Hardware I O Notation Description Setting Area Bank Mapping DA b Direct a bit is indicated by the F80H FFFH Bank 15 All 1 bit RAM address DA memory addressable bank selection and a the peripherals specified bit number b SMB 15 1 000H FFFH SMB 0 1 15 mema b Direct a bit is indicated by the x FBOH FBFH Bank 15 150 IS1 EMB addressable area mema and ERB IEx IRQx a the bit number b Pn n memb L Indirect a bit is indicated by x Bank 15 BSCn x the addressable area Pn n memb 7 2 upper L 3 2 lower and the bit number L 1 0 DA b Indirect bit is indicated by 000 Bank 0 the addressable area upper DA 3 0 lower memory bank selection and the bit number b 1 000H FFFH SMB 0 1 15 All 1 bit addressable peripherals SMB 15 NOTE means don t care 3 6 ELECTRONICS 557 2308 2308 2316 2316 5 PROGRAMMING 1 Bit Addressing Modes 1 Bit Direct Addressing 1 If EMB 0 AFLAG EQU 34H 3 BFLAG EQU 85H 3 CFLAG EQU 0 SMB 0 BITS AFLAG BITS BFLAG BTST CFLAG BITS BFLAG BITS P3 0 2 IfEMB 1 AFLAG EQU 34H
127. bled by a corresponding PUMOD bit setting N Channel Open Drain Mode Register PNE The n channel open drain mode register PNE is used to configure outputs as n channel open drain outputs or as push pull outputs ELECTRONICS 10 1 VO PORTS 557 2308 2308 2316 2316 Table 10 1 I O Port Overview 0 0 0 3 4 bit input port 1 bit and 4 bit read and test are possible P0 1 and 0 2 are software configurable as input or output for sck and SO by SMOD register 4 bit pull up resistors are software assignable 1 0 1 3 FF1H 4 bit input port 1 bit and 4 bit read and test are possible 4 bit pull up resistors are software assignable 2 0 2 3 4 bit I O port 1 bit and 4 bit read write and test is possible 4 bit pull up resistors are software assignable 3 P3 0 P3 3 4 bit I O Port 1 bit and 4 bit read write and test are possible 4 bit pull up resistors are software assignable Each pin is individually software configurable as input or output 4 0 4 3 4 bit I O port Each pin be set to N channel P5 0 P5 3 open drain output up to 5 volts 1 4 and 8 bit read write test are possible Ports 4 and 5 can be paired to support 8 bit data transfer Pull up resistors are software assignable pull up resistor are automatically disable for output P6 0 P6 3 4 bit port Port 6 pins are individually P7 0 P7 3 software configurable as input or output 1 and 4 bit read write test are possib
128. by any other interrupt source Table 7 3 Standard Interrupt Priorities Default Priority INTB 4 INTO INT1 INTS INTTO The MSB of the IPR the interrupt master enable flag IME enables and disables all interrupt processing Even if an interrupt request flag and its corresponding enable flag are set a service routine cannot be executed until the IME flag is set to logic one The IME flag mapped FB2H 3 be directly manipulated by El and DI instructions regardless of the current enable memory bank EMB value Table 7 4 Interrupt Priority Register Settings Result of IPR Bit Setting IPR2 PRO it Setti __ f o o ___ Normal interrupt handing according to default priority settings __ f o 1 Process INTB and INT4 interrupts at highest priority __ 1 0 Process INTO interrupts at highest priority __ 1 Process interrupts at highest priority ________ __ _ of Process INTS interrupts at highest priority __ o 1 jProessNITOitemupsathighestpiorty NOTE During normal interrupt processing interrupts are processed in the order which they occur If two or more interrupt requests are received simultaneously the priority level is determined according to the standard interrupt priorities in Table 7 3 the default priority assigned by hardware when the lower three IPR bits 0 In this case the higher priority interrupt request is serviced and the other
129. can be addressed by write instructions programs can exert direct control over interrupt processing status Before interrupt status flags can be addressed however you must first execute a DI instruction to inhibit additional interrupt routines When the bit manipulation has been completed execute an EI instruction to re enable interrupt processing 5 PROGRAMMING Setting ISx Flags for Interrupt Processing The following instruction sequence shows how to use the 150 and IS1 flags to control interrupt processing INTB DI Disable interrupt BITR IS1 161 lt 0 BITS IS0 Allow interrupts according to IPR priority level Enable interrupt ELECTRONICS 2 17 ADDRESS SPACES 557 2308 2308 2316 2316 FLAG flag is used to allocate specific address locations in the RAM by modifying upper 4 bits of 12 bit data memory addresses this way it controls the addressing mode for data memory banks 0 1 or 15 When the EMB flag is 0 the data memory address space is restricted to bank 15 and addresses 000 07 of memory bank 0 regardless of the SMB register contents When the EMB flag is set to 1 the general purpose areas of bank 0 1 and 15 can be accessed by using the appropriate SMB value 5 PROGRAMMING TIP Using the EMB Flag to Select Memory Banks EMB flag settings for memory bank selection 1 When EMB 0 SMB 1 Non essential instruction since EMB 0 LD
130. can be summarized as follows Set TMODO 2 to 1 to enable TCO Set TMODO 6 to 1 to enable the system clock fxx input Set TMODO0 5 and TMOD0 4 bits to desired internal frequency fxx 2 Load a value to TREFO to specify the interval between interrupt requests Set the TCO interrupt enable flag IETO to 1 Set TMODO 3 bit to 1 to clear TCNTO IRQTO and and start counting TONTO increments with each internal clock pulse ON OA amp When the comparator shows TCNTO TREFO the IRQTO flag is set to 1 an interrupt request is generated 9 Output latch TOLO logic toggles high or low 10 TONTO is cleared to and counting resumes 11 Programmable timer counter operation continues until TMODO 2 is cleared to O ELECTRONICS 11 13 TIMERS TIMER COUNTERS 557 2308 2308 2316 2316 TCO EVENT COUNTER FUNCTION Timer counter 0 can monitor or detect system events by using the external clock input at the TCLO pin as the counter source The TCO mode register selects rising or falling edge detection for incoming clock signals The counter register is incremented each time the selected state transition of the external clock signal occurs With the exception of the different TMOD0 4 TMOD0 6 settings the operation sequence for TCO s event counter function is identical to its programmable timer counter function To activate the TCO event counter function Set TMODO 2 to
131. ce Output delay for Vpp 2 7 V to 5 5 V scK to SO External source Internal scK source External SCK source Interrupt input INTO tINTL high low width INT1 INT2 INT4 KSO KS7 RESET Input Low tRSL Input Width NOTES 1 Unless otherwise specified Instruction Cycle Time condition values assume a main system clock fx source 2 Minimum value for INTO is based on a clock of 2t y or 128 fx as assigned by the IMODO register setting ELECTRONICS 14 7 ELECTRICAL DATA 557 2308 2308 2316 2316 CPU Clock Main OSC Frequency 1 0475 MHz 1 00 MHz 750 kHz 500 kHz ui T I 3 1 8 3 4 Supply Voltage V CPU CLOCK 1 n x oscillator frequency n 4 8 64 Figure 14 1 Standard Operating Voltage Range Table 14 7 RAM Data Retention Supply Voltage in Stop Mode TA 40 C to 85 C Dam renton supply Toon 189 93 w Release signal set time tsREL Normal operation Foo u Oscillator stabilization wait twAIT Released by RESET time 1 Released by interrupt 2 NOTES 1 During oscillator stabilization wait time all CPU operations must be stopped to avoid instability during oscillator start up 2 Use basic timer mode register BMOD interval timer to delay execution of CPU instructions during the wait time LECTRONI 14 8 ELECTRONICS 557 2308 2308 2316 2316 ELECTRI
132. ch to the basic timer s interrupt service routine INTA and to set the EMB value to 0 and the ERB value to 1 VENT2 then branches to INTB VENTS to INTC and so on setting the appropriate EMB and ERB values Each interrupt service routine is executed according to the devices ELECTRONICS 5 89 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Exchange or EA with Nibble or Byte XCH Operation Description Example 5 90 dst src Exchange A and data memory contents Exchange A and register Ra contents Exchange A and indirect data memory 1 Exchange EA and direct data memory comers 2 2 EARR Exchange EA and register pair RRB contents FEA HL Exchange EA and indirect data memory contents The instruction XCH loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source Operand Binary Code operation Notation ma o Am olio 1 1 1 Ae one avant Far 6 as at as at ro NE rre fo feta fo ue Double register HL contains the address 20H The accumulator contains the value 00111111B and internal RAM location 20H the value 75H 01110101B The instruct
133. cifies bit 1 Therefore P1 L P2 1 LD L 9H BAND C P1 L P1 Lis specified as P2 1 C AND 2 1 ELECTRONICS 5 29 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 BAND Bit Logical And BAND Continued Examples 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000 The resulting address is 00100000B or 20H bit value for the BAND instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BAND C H FLAG CAND FLAG 20H 3 5 30 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET BITR Bit Reset BITR dst b Clear specified memory bit to logic zero H DA b Description A BITR instruction clears to logic zero resets the specified bit within the destination operand No other bits in the destination are affected operand Binary Code me Pa eeo o ofofo Far 0 _ 1 1 1 1 1 1 1 memb7 2 13 21 1 1 01 lt 0 Fo 3 po o as Tee fas Fo or Pao eye ______ memab 1 o b1 bo a2 ao FBOH FBEH Fr per eo se Pat 20 FRA Fron Examples 1 If the bit location 30H 2 in the RAM has a current value of 1 The following instruction clears the third bit of location 30H to 0 BITR 30H 2
134. ck Timing Measurement at XIN Figure 16 7 Clock Timing Measurement at XTIN 16 12 ELECTRONICS 557 2308 2308 2316 2316 557 2308 2316 Figure 16 8 0 Timing Figure 16 9 Input Timing for RESET Signal INTO 1 2 4 KSO to KS7 Figure 16 10 Input Timing for External Interrupts and Quasi Interrupts ELECTRONICS 16 13 557 2308 2316 557 2308 2308 2316 2316 OUTPUT DATA Figure 16 11 Serial Data Transfer Timing 16 14 ELECTRONICS 557 2308 2308 2316 2316 557 2308 2316 Address First Location Vpp 5V Vpp 12 5V Program One 1 5 Pulse Increment X NO Verify Byte Verify 1 Byte Last Address Increment Address 5 V Figure 16 12 OTP Programming Algorithm ELECTRONICS 16 15 557 2308 2316 557 2308 2308 2316 2316 NOTES 16 16 ELECTRONICS 557 2308 2308 2316 2316 DEVELOPMENT TOOLS Development Tools OVERVIEW Samsung provides a powerful and easy to use development support system in turnkey form The development support system is configured with a host system debugging tools and support software For the host system any standard computer that operates with MS DOS as its operating system can be used One type of debugging tool including hardware and software is provided the sophisticated and powerful in circuit emulator SMDS2 for KS57 586 KS88 families of microcontrollers The
135. contents to A Logical OR double register to EA Logical OR EA to double register Exclusive OR immediate data to A Exclusive OR indirect data memory to A Exclusive OR register pair RR to EA Exclusive OR register pair aa to EA N N Table 5 13 Arithmetic Instructions High Level Summary Add indirect data memory to A with carry Add register pair RR to EA with carry Add EA to register pair RRb with carry im Add 4 bit immediate data to A and skip on carry EA imm Add 8 bit immediate data to EA and skip on carry A HL Add indirect data memory to A and skip on carry EA RR Add register pair RR contents to EA and skip on carry RRb EA Add EA to register pair RRb and skip on carry Subtract indirect data memory from A with carry Subtract register pair RR from EA with carry Subtract EA from register pair RRb with carry Subtract indirect data memory from A skip on borrow Subtract register pair RR from EA skip on borrow Subtract EA from register pair RRb skip on borrow Decrement register R skip on borrow Decrement register pair RR skip on borrow Increment register R skip on carry Increment direct data memory skip on carry Increment indirect data memory skip on carry Increment register pair RRb skip on carry ELECTRONICS 5 11 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Table 5 14 Bit Manipulation Instructions High Level Summary 5 2 BTST Test specified bit and skip if carry f
136. ct 2 The number of memory bank selected by SMB may change for different devices in the SAM47 product family The port names used instruction set may change for different devices in SAM47 product family The interrupt names and the interrupt numbers used in the instruction set may change for different devices in the SAM47 product family ELECTRONICS 5 1 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Instruction Reference Area Using the 1 byte REF Reference instruction you can reference instructions stored in the addresses 0020 007 of program memory the REF instruction look up table The location referenced by REF may contain either two 1 byte instructions or a single 2 byte instruction The starting address of the instruction being referenced must always be an even number 3 byte instructions such as JP or CALL may also be referenced using REF To reference these 3 byte instructions the 2 byte pseudo commands TJP and TCALL must be written in the reference The PC is not incremented when an REF instruction is executed After it executes the program s instruction execution sequence resumes at the address immediately following the REF instruction By using REF instructions to execute instructions larger than one byte as well as branches and subroutines you can reduce the program size To summarize the REF instruction can be used in three ways Using the 1 byte REF instruction to execute one 2 byte or two 1 byt
137. ct the CPU clock frequency and to control CPU operating and power down modes The PCON can be addressed directly by 4 bit write instructions or indirectly by the instructions IDLE and STOP PCON 3 and PCON 2 can be addressed only by the STOP and IDLE instructions respectively to engage the idle and stop power down modes Idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag EMB PCON bits 1 and 0 can be written only by 4 bit RAM control instruction PCON is a write only register There are three basic choices Main system clock fx or subsystem clock fxt Divided fx clock frequency of 4 8 or 64 Divided fxt clock frequency of 4 PCON 1 and 0 settings are also connected with the system clock mode control register SCMOD If SCMOD 0 0 the main system clock is always selected by the PCON 1 and 0 setting if SCMOD 0 1 the subsystem clock is selected RESET clears PCON register values and SCMOD to logic zero Table 6 1 Power Control Register PCON Organization PCON Bit Settings Resulting CPU Operating Mode PCON 3 PCON 2 __ o Normal CPU operating mode 1 0 _ STOP mode ELECTRONICS 6 5 OSCILLATOR CIRCUITS 557 2308 2308 2316 2316 5 PROGRAMMING Setting the CPU Clock To set the CPU clock to 0 95 us at 4 19 MHz BITS EMB SMB 15 LD LD PCON A INSTRUCTION CYCLE TIMES The
138. ddress memb 7 2 is 111100B and L 3 2 is 10B The resulting address 11110010B specifies P2 The bit value L 1 0 is specified as 01B bit 1 Therefore P1 L P2 1 SCF Ce 1 LD L 9H LDB P1 L C P1 L specifies P2 1 P2 1 lt 1 In this example H 2H and FLAG 20H 3 and the address 20H is specified Since the bit value is 3 H FLAG 20H 3 FLAG EQU 20H 3 RCF 0 LD H 2H LDB H FLAG C FLAG 20H 3 0 NOTE Port pin names used in examples 4 and 5 may vary with different SAM47 devices ELECTRONICS 5 65 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 LDC Load Code Byte LDC dst src EA WX Load code byte from WX to EA dL 3 EA QEA Load code byte from EA to EA Description This instruction is used to load a byte from program memory into extended accumulator address of the byte fetched is the 6 highest bit values in the program counter and the contents of an 8 bit working register either WX or EA The contents of the source are unaffected _ o o EAC o __ 1 following instructions will load of four values defined by the define byte DB directive to the extended accumulator LD EA 00H CALL DISPLAY JPS MAIN ORG 0500H DB 66H DB 77H DB 88H DB 99H DISPLAY LDC EA lt add
139. ddress by RESET lt 0 Jump to INTB address by INTB lt 0 Jump to INTO address by INTO lt 0 Jump to INT1 address INT1 lt 0 Jump to INTS address by INTS lt 0 Jump to INTTO address by INTTO 2 When a specific vectored interrupt such as INTO and INTTO is not used the unused vector interrupt locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations ORG 0000H VENTO 1 0 RESET VENT1 0 0 INTB ORG 0006 0 0 1 1 VENT4 0 0 INTS ORG 000 0010 EMB lt 1 ERB lt 0 Jump to RESET address by RESET EMB lt 0 ERB lt 0 Jump to INTB address by INTB INTO interrupt not used EMB lt 0 ERB lt 0 Jump to INT1 address by INT1 lt 0 ERB lt 0 Jump to INTS address by INTS INTTO interrupt not used 3 If an INTO interrupt is not used and if its corresponding vector interrupt area is not fully utilized or if it is not written by a ORG instruction in Example 2 a CPU malfunction will occur ORG 0000H VENTO 1 0 RESET VENT1 0 0 INTB 0 0 INT1 VENTA 0 0 INTS 5 0 0 INTTO ORG 0010H General purpose ROM area EMB EMB EMB EMB EMB lt lt 1 0 ERB 0 ERB 0 ERB 0 ERB lt 0 Jump to RESET address by RESET lt 0 Jump to address by lt 0 Jump to INT1 address by INTO lt 0 Jump to INTS address by INT1 lt 0 Jump to INTTO address by INTS In thi
140. e wait time 215 fxx 7 82 ms 1 1 1 Input clock frequency fxx 2 131 kHz Interrupt interval time wait time 213 fxx 1 95 ms NOTES 1 When a RESET ocours the oscillator stabilization wait time is 31 3 ms 217 fxx at 4 19 MHz 2 is the system clock rate given a clock frequency of 4 19 MHz ELECTRONICS 557 2308 2308 2316 2316 MEMORY CLMOD clock Output Mode Register FDOH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write WwW Addressing 4 4 4 4 3 Enable Disable Clock Output Control Bit Disable clock output Enable clock output 2 Bit 2 Always logic zero 1 0 Clock Source and Frequency Selection Control Bits Select CPU clock source fx 4 fx 8 fx 64 or fxt 4 1 05 MHz 524 kHz 65 5 kHz or 8 19 kHz Lo 4 Select system clock fxx 8 524 kHz AEA Select system clock fxx 16 262 kHz Select system clock fxx 64 65 5 kHz NOTE fxx is the system clock given a clock frequency of 4 19 MHZ ELECTRONICS 4 7 MEMORY 557 2308 2308 2316 2316 IEO 1 IRQO de INTO 1 Interrupt Enable Request Flags FBEH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 IE1 INT1 Interrupt Enable Flag Disable interrupt requests the INT1 pin 1 Enable interrupt requests at the INT1 pin IRQ1 INT1 Interrupt Request Flag Generate INT1 interrupt This bit is set and cleared by hardware when risi
141. e instructions Branching to any location by referencing a branch address that is stored in the look up table Calling subroutines at any location by referencing a call address that is stored in the look up table If necessary an REF instruction can be circumvented by means of a skip operation prior to the REF in the execution sequence In addition the instruction immediately following an REF can also be skipped by using an appropriate reference instruction or instructions Two byte instructions can be referenced by using an REF instruction An exception is XCH A DA note If the MSB value of the first 1 byte instruction in the reference area is 0 the instruction cannot be referenced by a REF instruction Therefore if you use REF to reference two 1 byte instructions stored in the reference area specific combinations must be used for the first and second 1 byte instruction These combinations are described in Table5 1 Table 5 1 Valid 1 Byte Instruction Combinations for REF Look Ups First 1 Byte Instruction Second 1 Byte Instruction instruction Operand instruction Operand A im 5 note INCS DECS note INCS note INCS DECS note NOTE The MSB value of the instruction is O R RRb INCS note R DECS note R R RRb 5 2 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET Reducing Instruction Redundancy When redundant instructions such as LD A im and LD EA im
142. ear SCMOD 3 to 0 to enable main system clock oscillation Until main osc is stabilized system clock must not be changed Then after a certain number of machine cycles has elapsed select the main system clock by clearing all SCMOD values to logic zero After RESET CPU operation starts with the lowest main system clock frequency of 15 3 us at 4 19 MHz after the standard oscillation stabilization interval of 31 3 ms has elapsed Table 6 6 details the number of machine cycles that must elapse before a CPU clock switch modification goes into effect 6 10 ELECTRONICS 557 2308 2308 2316 2316 OSCILLATOR CIRCUITS Table 6 6 Elapsed Machine Cycles During CPU Clock Switch AFTER SCMOD 0 0 SCMOD 0 1 aed 1 N A 1 MACHINE CYCLE 1 MACHINE CYCLE 0 0 0 SCMOD 0 0 121 8 MACHINE CYCLES 8 0 0 0 16 MACHINE CYCLES 16 MACHINE CYCLES fx Afxt MACHINE CYCLE 1 1 NOTES 1 Even if oscillation is stopped by setting SCMOD 3 during main system clock operation the stop mode is not entered 2 Since the input is connected internally to Vas to avoid current leakage due to the crystal oscillator in stop mode do not set SCMOD 3 to 1 or STOP instruction when an external clock is used as the main system clock 3 When the system clock is switched to the subsystem clock it is necessary to disable any interrupts which may occur during the time intervals shown i
143. ect Addressing Example 2 1 If EMB 0 exchange bank 0 locations 040 046 with bank 0 locations 060 066 ADATA EQU 46H BDATA EQU 66H SMB 1 Non essential instruction since EMB 0 LD HL ZBDATA LD WX ADATA TRANS LD A WL A bank 0 040 046 XCHD A HL Bank 0 060 066 JR TRANS If EMB 1 exchange bank 0 locations 040 046 to bank 1 locations 160 166 ADATA EQU 46H BDATA EQU 66H SMB 1 LD HL BDATA LD WX ADATA TRANS LD A WL A bank 0 040H 046H XCHD A HL Bank 1 160H 166H JR TRANS ELECTRONICS 557 2308 2308 2316 2316 ADDRESSING MODES 8 BIT ADDRESSING Table 3 4 8 Bit Direct and Indirect RAM Addressing Instruction Addressing Mode EMB Flag Addressable Memory Hardware I O Notation Description Setting Area Bank pe Direct 8 bit address indicated F80H FFFH 15 8 bit by the RAM address DA addressable even number and memory peripherals bank selection 000H FFFH 0 1 SMB 15 15 Indirect the 8 bit address indi 000 Bank 0 cated by the memory bank selection and register HL the 4 bit L register value must be an even number 1 000H FFFH 0 1 All 8 bit addressable peripherals SMB 15 5 PROGRAMMING 8 Bit Addressing Modes 8 Bit Direct Addressing 1 If EMB 0 ADATA EQU 46H BDATA EQU 8EH SMB 15 Non essential instruction since EMB 0 LD EA P4 lt
144. ectrical values for supply current Ipp to Ippe do not include current drawn through internal pull up resistors and through LCD voltage dividing resistors 2 Data includes the power consumption for sub system clock oscillation 3 When the system clock mode register SCMOD is set to 0100B the sub system clock oscillation stops The main system clock oscillation stops by the STOP instruction LECTRONI 14 4 ELECTRONICS 557 2308 2308 2316 2316 ELECTRICAL DATA Table 14 3 Main System Clock Oscillator Characteristics Ta 40 C 85 C 1 8 V to 5 5 V Clock Parameter Test Condition Typ Configuration Ceramic Oscillator Stabilization time 2 Stabilization occurs when Vpp is equal to the minimum oscillator voltage range Crystal xour Oscillation frequency 1 Oscillator I 2 XIN input high and low 83 3 level width txL RC Frequency 1 5V 0 4 2 MHz Oscillator R 20 5 V 2 0 R 38 3 V 1 0 NOTES 1 Oscillation frequency and Xy input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillator stabilization after a power on occurs or when stop mode is terminated ELECTRONICS 14 5 ELECTRICAL DATA 557 2308 2308 2316 2316 Table 14 4 Subsystem Clock Oscillator Characteristics TA 40 C 85
145. ecuted the SP is incremented by two and points to the next free stack location RET and SRET Instructions The end of a subroutine call is signaled by the return instruction RET or SRET The RET or SRET uses the SP to reference the six 4 bit stack locations used for the CALL and to write this data back to the PC the EMB and the ERB After the RET or SRET has executed the SP is incremented by six and points to the next free stack location IRET Instructions The end of an interrupt sequence is signaled by the instruction IRET IRET references the SP to locate the six 4 bit stack addresses used for the interrupt and to write this data back to the PC and the PSW After the IRET has executed the SP is incremented by six and points to the next free stack location POP RET OR SRET IRET SP SP 2 SP SP 6 SP SP 6 NOTE PC13 is used for KS57C2316 P2316 microcontroller Figure 2 8 Pop Type Stack Operations 2 14 ELECTRONICS 557 2308 2308 2316 2316 ADDRESS SPACES BIT SEQUENTIAL CARRIER BSC The bit sequential carrier BSC is a 16 bit general register that can be manipulated using 1 4 and 8 bit RAM control instructions RESET clears all BSC bit values to logic zero Using the BSC you can specify sequential addresses and bit locations using 1 bit indirect addressing memb L Bit addressing is independent of the current EMB value In this way programs can process 16 bit data by moving the bit location sequ
146. ed in one machine cycle ELECTRONICS 5 7 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 HIGH LEVEL SUMMARY This section contains a high level summary of the SAM47 instruction set in table format The tables are designed to familiarize you with the range of instructions that are available in each instruction category These tables are a useful quick reference resource when writing application programs If you are reading this user s manual for the first time however you may want to scan this detailed information briefly and then return to it later on The following information is provided for each instruction Instruction name Operand s Brief operation description Number of bytes of the instruction and operand s Number of machine cycles required to execute the instruction The tables in this section are arranged according to the following instruction categories control instructions Program control instructions Data transfer instructions Logic instructions Arithmetic instructions Bit manipulation instructions 5 8 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET Table 5 9 CPU Control Instructions High Level Summary Operation Description Cycles 1 Set carry flag to logic one Reset carry flag to logic zero A Complement carry flag m Enable all interrupts Disable all interrupts Engage CPU idle mode Engage CPU stop mode
147. egister SMOD Set SIO interrupt enable flag IES to 1 Initiate SIO transmission by setting bit 3 of the SMOD to 1 When the SIO operation is complete IRQS flag is set and an interrupt is generated gt ELECTRONICS 13 1 SERIAL I O INTERFACE 557 2308 2308 2316 2316 INTERNAL BUS LSB or MSB first 50 IRQS 1 555 TOLO 90 Qi 02 CPU CLK CLOCK 3 BIT COUNTER 502 10 SELECTOR x 2 4 SMOD 7 SMOD 6 swos SMOD 3 SMOD 2 SMOD 1 0 8 BITS INTERNAL BUS nstruction Execution fxx System Clock Figure 13 1 Serial I O Interface Circuit Diagram LECTRONI 13 2 ELECTRONICS 557 2308 2308 2316 2316 SERIAL I O INTERFACE SERIAL MODE REGISTER SMOD The serial I O mode register SMOD is an 8 bit register that specifies the operation mode of the serial interface Its reset value is logical zero SMOD is organized in two 4 bit registers as follows SMOD register settings enable you to select either MSB first or LSB first serial transmission and to operate in transmit and receive mode or receive only mode SMOD is a write only register and can be addressed only by 8 bit RAM control instructions One exception to this is SMOD 3 which can be written by a 1 bit RAM control instruction When SMOD 3 is set to 1 the contents of the serial interface interrupt request flag IRQS and the 3 bit serial clock counter are cleared and SIO oper
148. eleased by an interrupt When a RESET signal is generated the standard stabilization interval for system clock oscillation following a RESET is 31 3 ms at 4 19 MHz Watchdog Timer Function The basic timer can also be used as a watchdog timer to detect an inadvertent program loop that is system or program operation error For this purpose instruction that clears the watchdog timer BITS WDTCF within a given period should be executed at proper points in a program If an instruction that clears the watchdog timer is not done within the period and the watchdog timer overflows reset signal is generated and system is restarted with reset status An operation of watchdog timer is as follows Write some value except 5AH to Watchdog Timer Mode register WOMOD Each time BCNT overflows an overflow signal is sent to the watchdog timer counter WDCNT If WDTCNT overflows system reset will be generated LECTRONI 11 2 ELECTRONICS 557 2308 2308 2316 2316 TIMERS TIMER COUNTERS Table 11 1 Basic Timer Register Overview Register Type Description RAM Addressing Reset Name Address Mode Value BMOD Control Controls the clock frequency 4 bit F85H 4 bit write only mode of the basic timer also the BMOD 3 1 bit oscillation stabilization interval after write only power down mode release or RESET BONT Counter Counts clock pulses matching the 8 bit F86H F87H 8 bit read LU BMOD preme mm setting Errem note
149. em clock enable main system clock 1 Select sub system clock fxt enable main system clock Select main system clock disable sub system clock 110 1 Select sub system clock fxt disable main system clock Bit 1 Always logic zero NOTE SCMOD bits and 0 cannot be modified simultaneously by a 4 bit instruction they can only be modified by separate 1 bit instructions 4 26 ELECTRONICS 557 2308 2308 2316 2316 MEMORY SMOD serial 0 Mode Register FE1H FEOH Bit 7 6 5 4 3 2 1 0 identifier 7 6 5 3 2 3 RESET Value 0 0 0 0 0 0 0 0 Read Write R W Bit Addressing 8 8 8 8 1 8 8 8 8 7 5 ELECTRONICS Serial I O Clock Selection and SBUF R W Status Control Bits Use an external clock at the SCK pin Enable SBUF when SIO operation is halted or when SCK goes high 1 Use the clock from timer counter 0 Enable SBUF when SIO operation is halted or when SCK goes high 1 x Use the selected CPU clock fxx 4 8 or 64 is the system clock Enable SBUF read write operation x means don t care 1 0 0 4 09 kHz clock 210 1 1 1 262 kHz clock fxx 24 Note You cannot select a fxx 24 clock frequency if you have selected a CPU clock of fxx 64 NOTE kHz freniiencv evetam clack of A Bit 4 Always logic zero Initiate Serial I O Operation Bit
150. entially and then incrementing or decreasing the value of the L register BSC data can also be manipulated using direct addressing For 8 bit manipulations the 4 bit register names 5 0 and BSC2 must be specified and the upper and lower 8 bits manipulated separately If the values of the L register are at BSCO L the address and bit location assignment is FCOH O If the L register content is at BSCO L the address and bit location assignment is FC3H 3 Table 2 4 BSC Register Organization me Sz Br Bo BSCO FCOH BSCO 3 5 0 2 BSC0 1 BSC0 0 BSC1 FC1H BSC1 3 BSC1 2 BSC1 1 BSC1 0 BSC2 FC2H BSC2 3 BSC2 2 BSC2 1 BSC2 0 BSC3 FC3H BSC3 3 BSC3 2 BSC3 1 BSC3 0 I PROGRAMMING TIP Using the BSC Register to Output 16 Bit Data To use the bit sequential carrier BSC register to output 16 bit data 5937H to the P3 0 pin BITS EMB SMB 15 LD EA 37H LD BSCO EA BSCO lt BSC1 lt LD EA 59 LD 5 2 BSC2 lt 5 lt E SMB 0 LD L 0H i AGN LDB C BSCO L LDB P3 0 C P3 0 INCS L JR AGN RET ELECTRONICS 2 15 ADDRESS SPACES 557 2308 2308 2316 2316 PROGRAM COUNTER A 13 bit program counter PC stores addresses for instruction fetches during program execution KS57C2316 microcontroller has 14 bit program counter PCO PC13 Whenever a reset operation or an interrupt occurs bits PC12 through PCO PC13 through PCO for KS57C2316 are set to t
151. ents of EA to the 8 bit RRb register HL WX YZ The E register is loaded into the H W and Y register and the A register into the L X and Z register Load the A register to data memory location pointed to by the 8 bit HL register and the E register contents to the next location HL 1 The contents of the L register must be an even number If the number is odd the LSB of the L register is recognized as logic zero an even number and is not replaced with the true value For example LD HL 36H loads immediate 36H to register HL the instruction LD HL EA loads the contents of A into address 36H and the contents of E into address 37H 5 63 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 LDB Load Bit LDB LDB Operation Description 5 64 dst src b dst b src Load carry bit to a specified memory bit 2 memb L C Load carry bit to a specified indirect memory bit H DA b C Load memory bit to a specified carry bit C memb L Load indirect memory bit to a specified carry bit C H DA b The Boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand One of the operands must be the carry flag the other may be any directly or indirectly addressable bit The source is unaffected ____ ee aa membQLC 1 1 1 1 1 1 0 0 7 2 IL 3 2 L 1 0 C O 1 0 0 aa
152. er LD WX 00H LDC EA WX E lt upper 4 bits of 0100H address A lt lower 4 bits of 0100H address LD HL EA RAM 30H 7 RAM 6 ELECTRONICS 5 67 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 LDD Load Data Memory and Decrement LDD dst A HL Load indirect data memory contents to A decrement 1 2 65 register L contents and skip on borrow Description The contents of a data memory location are loaded into the accumulator and the contents of the register L are decreased by one If a borrow occurs e g if the resulting value in register L is OFH the next instruction is skipped The contents of data memory and the carry flag value are not affected A HL 1 1 1 1 lt HL thenL lt L 1 skip if L OFH Example In this example assume that register pair HL contains 20H and internal RAM location 20H contains the value OFH LD HL 20H LDD A HL A lt lt 1 PS XXX Skip PS YYY H 2Hand L lt OFH he instruction is skipped since a borrow occurred after the LDD A HL and instruction JPS YYY is executed 5 68 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET LDI Load Data Memory and Increment LDI Operation Description Example dst src A HL Load indirect data memory to A increment register L 1 2 65 contents skip on overflow The contents of a data memory location
153. ettings are used together to select the TCO clock source This selection involves two variables Synchronization of timer counter operations with either the rising edge or the falling edge of the clock signal input at the TCLO pin and Selection of one of four frequencies based on division of the incoming system clock frequency for use in internal TCO operation Table 11 6 Mode Register TMODO Organization TMODO 7 Always logic zero F91H TMODO 6 TMODO 5 TMODO 4 Specify input clock edge and internal frequency Disable timer counter 0 retain TCNTO contents Enable timer counter 0 Always logic zero Always logic zero TMODO 2 TMODO 1 TMODO 0 TMODO 3 1 Clear TCNTO IRQTO and TOLO and resume counting immediately This bit is automatically cleared to logic zero immediately after counting resumes ELECTRONICS 11 17 TIMERS TIMER COUNTERS 557 2308 2308 2316 2316 Table 11 7 TMODO 6 TMODO 5 0 4 Settings TMODO 6 TMODO 5 TMODO 4 Resulting Counter Source and Clock Frequency External clock input TCLO on rising edges 1 External clock input TCLO on falling edges 1 fxx 28 16 4 kHz 1 fxx 2 65 5 kHz 0024 262 kHz NOTE selected system clock of 4 19 MHz __ _ 0 0 e280 wosk __ _ 1 I PROGRAMMING Restarting TCO Counting Operation 1 Set TCO timer interval to 4 09 kHz BIT
154. ference register TREFO is an 8 bit write only register It is addressable by 8 bit RAM control instructions RESET initializes the TREFO value to TREFO is used to store a reference value to be compared to the incrementing TCNTO register in order to identify an elapsed time interval Reference values will differ depending upon the specific function that TCO is being used to perform as a programmable timer counter event counter clock signal divider or arbitrary frequency output source During timer counter operation the value loaded into the reference register is compared to the value When TCNTO TREFO the TCO output latch TOLO is inverted and an interrupt request is generated to signal the interval or event The TREFO value together with the clock frequency selection determines the specific TCO timer interval Use the following formula to calculate the correct value to load to the TREFO reference register j frequency setting TCO timer interval TREFO value 1 TREFO value 0 TCO OUTPUT ENABLE FLAG TOEO The 1 bit timer counter 0 output enable flag TOEO controls output from timer counter 0 to the TCLOO pin TOEO is addressable by 1 bit write instructions MSB LSB NOTE U indicates unknown state When you set the TOEO flag to 1 the contents of can be output to the TCLOO pin Whenever a RESET occurs TOEO is automatically set to logic zero di
155. from the stack and restores them to the program counter The stack pointer is incremented by six and the PSW enable memory bank EMB bit and enable register bank ERB bit are also automatically restored to their pre interrupt values Program execution continues from the resulting address which is generally the instruction immediately after the point at which the interrupt request was detected If a lower level or same level interrupt was pending when the IRET was executed IRET will be executed before the pending interrupt is processed Since the 14 bit of an interrupt return address is not stored in the stack this bit location is always interpreted as a logic zero The starting address in the ROM must for this reason be located in 0000 Binary Code Operation Notation PC13 8 lt SP 1 SP PC7 0 lt SP 2 SP 3 PSW c SP 4 SP 5 SP SP 6 stack pointer contains the value An interrupt is detected in the instruction at location 0122H RAM locations OFDH OFCH and OFAH contain the values 2H 3H and 1H respectively The instruction IRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 123H During a return from interrupt data is popped from the stack to the program counter The data in stack locations is organized as follows SP 6 00H ELECTRONICS 5 55 SAM47 INSTRUCTION SET 557 2308 2
156. g the status of the register bank enable flag ERB Generally working register bank 0 is used for the main program and banks 1 2 and 3 for interrupt service routines Following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing Table 2 3 Working Register Organization and Addressing SRB Settings Selected Register Bank a Always set to bank 0 o o mo o 31 B 34 o Ba Paired Working Registers Each of the register banks is subdivided into eight 4 bit registers These registers named Y Z W X H L E and A can either be manipulated individually using 4 bit instructions or together as register pairs for 8 bit data manipulation The names the 8 bit register pairs in each register bank are EA HL WX YZ and WL Registers L X and Z always become the lower nibble when registers are addressed 8 bit pairs This makes total of eight 4 bit registers or four 8 bit double registers in each of the four working register banks Figure 2 5 Register Pair Configuration ELECTRONICS 2 9 ADDRESS SPACES 557 2308 2308 2316 2316 Special Purpose Working Registers Register A is used as a 4 bit accumulator and double register EA as an 8 bit accumulator The carry flag can also be used as a 1 bit accumulator 8 bit double registers WX WL and HL are used as data pointers for indirect addressing When the HL register
157. gister FB6H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W Bit Addressing 4 4 4 4 3 Bits 3 Always logic zero 2 0 External Interrupt 2 Edge Detection Selection Select rising edge at INT2 pin 0 0 1 SelectfalngedgeatKS4 KS7 I I I Select falling edge at 52 57 o 1 1 Select falling edge at KSO KS7 Ignore selection of falling edge at KS4 KS7 4 16 ELECTRONICS 557 2308 2308 2316 2316 MEMORY IPR Interrupt Priority Register FB2H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W Bit Addressing 1 4 4 4 4 IME Interrupt Master Enable Bit Disable all interrupt processing Enable processing for all interrupt service requests 2 0 Interrupt Priority Assignment Bits Normal interrupt handling according to default priority settings 1 Process INTB and INT4 interrupts highest priority Process INTO interrupts at highest priority Jaa Process INT1 interrupts at highest priority 1 Process INTS interrupts at highest priority 110 1 Process INTTO interrupts at highest priority ELECTRONICS 4 17 MEMORY 557 2308 2308 2316 2316 LcD Output Control Register F8EH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write Bit Addressing 4 4 4 4 3 LCD Bias Selection This bit is used for internal testing only always logic zero 2 LCD Clock Output Disable Enable Disable
158. he previous routine are automatically pushed onto the stack and then popped back when the routine is completed After the return from interrupt IRET you do not need to set the EMB and ERB values again Instead use BITR and BITS to clear these values in your program routine The starting addresses for vector interrupts and reset operations are pointed to by the VENTn instruction These starting addresses must be located ROM ranges 0000H 3FFFH Generally the VENTn instructions are coded starting at location OOOOH The format for VENT instructions is as follows VENTn d1 d2 ADDR EMB lt 91 0 or 1 ERB lt 92 0 or 1 PC lt ADDR address to branch n device specific module address code n 0 EMB 1 EMT 12 11 a10 ROM 2 x n 7 6 EMB ERB ERB 0 1 ROM 2 x n 5 4 13 12 ADR ROM 2 x n 3 0 PC11 8 ROM 2 x n 1 7 0 PC7 0 n 0 1 2 3 4 5 6 7 as ss os 5 88 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET VENT Load EMB ERB and Vector Address VENTn Example Continued The instruction sequence ORG VENTO VENT1 VENT2 VENT7 0000H 1 0 RESET 0 1 INTA 0 1 INTB 0 1 INTG causes the program sequence to branch to the RESET routine labeled RESET setting EMB to 1 and ERB to 0 when RESET is activated When a basic timer interrupt is generated VENT1 causes the program to bran
159. he result of Then the execution Reason Instruction e instruction 1 is sequence is ADC A HL Overflow ADS cannot skip ADS A im instruction 3 even if it XXX No overflow 2 3 has a skip function XXX SBC A HL Borrow 2 3 ADS cannot skip ADS A im instruction 3 even if it XXX No borrow has a skip function XXX ELECTRONICS 5 5 SAM47 INSTRUCTION SET SYMBOLS and CONVENTIONS Table 5 4 Data Type Symbols Symbol Data Type Immediate data Address data b Bitdata mereetad essngdss Table 5 5 Register Identifiers Full Register Name 4 bit accumulator A 4 bit working registers E L H X W 2 Y 8 bit extended accumulator EA 8 bit memory pointer HL 8 bit working registers Select register bank n Select memory bank n Carry flag Program status word Port n m th bit of port n Interrupt priority register Enable memory bank flag Enable register bank flag 5 6 KS57C2308 P2308 C2316 P2316 Table 5 6 Instruction Operand Notation Symbol DA Direct address Indirect address prefix Source operand Destination operand Contents of register R Bit location 4 bit immediate data number 8 bit immediate data number Immediate data prefix 000H 1FFFH immediate address n bit address A E L H X W Z Y E L H X W Z Y EA HL WX YZ HL WX WL HL WX YZ WX WL FBOH FBFH FFOH FFFH FCOH FF
160. he service routine from this address EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM during interrupt service routines The flags are stored at the beginning of the program with the VENT instruction The initial flag values determine the vectors for resets and interrupts Enable flag values are saved during the main routine as well as during service routines Any changes that are made to enable flag values during a service routine are not stored in the vector address When an interrupt occurs the EMB and ERB flag values before the interrupt is initiated are saved along with the program status word PSW and the enable flag values for the interrupt is fetched from the respective vector address Then if necessary you can modify the enable flags during the interrupt service routine When the interrupt service routine is returned to the main routine by the IRET instruction the original values saved in the stack are restored and the main program continues program execution with these values Software Generated Interrupts To generate an interrupt request from software the program manipulates the appropriate IRQx flag When the interrupt request flag value is set it is retained until all other conditions for the vectored interrupt have been met and the service routine can be initiated Multiple Interrupts By manipulating the two interrupt status flags ISO and 151 can control service
161. he vector address Usually the PC is incremented by the number of bytes of the instruction being fetched One exception is the 1 byte REF instruction which is used to reference instructions stored in the ROM PROGRAM STATUS WORD PSW The program status word PSW is an 8 bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced PSW values are mapped as follows MSB LSB FBOH IS1 ISO EMB ERB FB1H SC2 SC1 SCO The PSW can be manipulated by 1 bit or 4 bit read write and by 8 bit read instructions depending on the specific bit or bits being addressed The PSW can be addressed during program execution regardless of the current value of the enable memory bank EMB flag Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt After the interrupt has been processed the PSW values are popped from the stack back to the PSW address When a RESET is generated the EMB and ERB values are set according to the RESET vector address and the carry flag is left undefined or the current value is retained PSW bits 150 151 SCO SC1 and SC2 are all cleared to logical zero Table 2 5 Program Status Word Bit Descriptions Enable memory bank flag R W scnsonsoo Program spres e n 2 16 ELECTRONICS 557 2308 2308 2316 2316 ADDRESS SPACES INTERRU
162. iN 20V 5 V Conditions VOL2 Vpp 4 5 V to 5 5 V Port 8 only loL 100 pA ILIH1 ViN VDD All input pins except those specified below for 2 2 VIN VDD XIN XOUT XTIN and XToyt ILIL1 VIN 0 V All input pins except XIN XOUT XTIN and XTout ILIL2 VIN 0V XTIN and XToyt ILOH1 VOUT VDD All output pins VouT 0 V All output pins ILOL 0 es 3 140 5 Vpp 5 V Vico lo 15 0 3 Vpp 5 V VLCo SEGi lo 15 I 0 31 4 9 5 04 14 3 ELECTRICAL DATA 557 2308 2308 2316 2316 Table 14 2 D C Electrical Characteristics Concluded Ta 40 C to 85 C Vpp 1 8 V to 5 5 V voltage _ 0 2 n 2 VLC1 Output VLC1 25 C 0 4 0 4 0 4 Vpp voltage 0 2 0 2 VLC2 Output Vic2 25 0 2 0 2 0 2 voltage 0 2 2 Supply Main operating Current 1 VDD 5V 10 CPU fx 4 SCMOD 000B crystal oscillator C1 C2 22pF 10 Main Idle mode Vpp 5 V 10 CPU fx 4 SCMOD 000B crystal oscillator C1 C2 22pF Vpp 3 V 10 Sub operating Vpp 3 V 10 CPU fxt 4 SCMOD 1001B 32 2 crystal oscillator Sub Idle mode Vpp 3 V 10 CPU fxt 4 SCMOD 1101B 32 2 crystal oscillator Stop mode CPU fxt 4 SCMOD 1101B Stop mode CPU fx 4 SCMOD 0100B NOTES 1 D C el
163. ic timer BONT is then incremented by one per each clock pulse corresponding to BMOD selection BONT overflows if BCNT 255 When an overflow occurs the IRQB flag is set by hardware to logic one The interrupt request is generated BONT is then cleared by hardware to logic zero 0L 0 gt Basic timer resumes counting clock pulses ELECTRONICS 11 5 TIMERS TIMER COUNTERS 557 2308 2308 2316 2316 5 PROGRAMMING Using the Basic Timer 1 To read the basic timer count register BCNT BITS EMB SMB 15 BCNTR LD EA BCNT LD YZ EA LD CPSE EA YZ JR BCNTR 2 When stop mode is released by an interrupt set the oscillation stabilization interval to 31 3 ms at 4 19 MHz BITS EMB SMB 15 LD A 0BH LD BMOD A Wait time is 31 3 ms NOP STOP Get into stop for power down mode NOP NOP NOP NORMAL NORMAL STOP MODE IDLE MODE CPU OPERATING MODE OPERATING MODE OPERATION 81 3 ms STOP STOP MODE 16 INSTRUCTION RELEASED BY INTERRUPT 3 To set the basic timer interrupt interval time to 1 95 ms at 4 19 MHz BITS EMB SMB 15 LD A 0FH LD BMOD A BITS IEB Basic timer interrupt enable flag is set to 1 4 Clear BCNT and the IRQB flag and restart the basic timer BITS EMB SMB 15 BITS BMOD 3 11 6 ELECTRONICS 557 2308 2308 2316 2316 TIMERS TIMER COUNTERS WATCHDOG TIMER MOD
164. ing the SRB n instruction The current SRB value is retained until another register is requested by program software PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and subroutine calls RESET clears the 4 bit SRB value to logic zero Select Memory Bank SMB Instruction To select one of the four available data memory banks you must execute an SMB n instruction specifying the number of the memory bank you want 0 1 or 15 For example the instruction SMB 1 selects bank 1 and SMB 15 selects bank 15 And remember to enable the selected memory bank by making the appropriate EMB flag setting The upper four bits of the 12 bit data memory address are stored in the SMB register If the SMB value is not specified by software or if a RESET does not occur the current value is retained RESET clears the 4 bit SMB value to logic zero The PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack area during interrupts and subroutine calls ELECTRONICS 3 5 ADDRESSING MODES 557 2308 2308 2316 2316 DIRECT AND INDIRECT ADDRESSING 1 bit 4 bit and 8 bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand Indirect addressing specifies a memory location that contains the required direct address The KS57 instruction set supports 1 bit 4 bit and 8
165. ing they are enabled If an interrupt s status latch was previously enabled by an interrupt this interrupt can also be serviced t If the IME bit bit 3 of the IPR is logic zero e g all instructions are disabled the instruction sets the IME bit to logic one enabling all interrupts 5 52 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET ID LE Idle Operation IDLE Operation Description Example IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of the power control register PCON After an IDLE instruction has been executed peripheral hardware remains operative In application programs an IDLE instruction must be immediately followed by at least three NOP instructions This ensures an adequate time interval for the clock to stabilize before the next instruction is executed If more than three NOP instructions are not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus The instruction sequence IDLE NOP NOP NOP sets bit 2 of the PCON register to logic one stopping the CPU clock The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed ELECTRONICS 5 53 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316
166. ings in the power control register PCON and the system clock mode register SCMOD determine whether a main system or a subsystem clock is selected as the CPU clock and also how this frequency is to be divided This makes it possible to switch dynamically between main and subsystem clocks and to modify operating frequencies SCMOD 3 SCMOD 2 SCMOD 0 select the main system clock fx or a subsystem clock fxt and start or stop main or sub system clock oscillation PCON 1 and 0 control the frequency divider circuit and divide the selected fx clock by 4 8 64 or fxt clock by 4 NOTE A clock switch operation does not go into effect immediately when you make the SCMOD and PCON register modifications the previously selected clock continues to run for a certain number of machine cycles For example you are using the default CPU clock normal operating mode and a main system clock of fx 64 and you want to switch from the fx clock to a subsystem clock and to stop the main system clock To do this you first need to set SCMOD 0 to 1 This switches the clock from fx to fxt but allows main system clock oscillation to continue Before the switch actually goes into effect a certain number of machine cycles must elapse After this time interval you can then disable main system clock oscillation by setting SCMOD 3 to 1 This same stepped approach must be taken to switch from a subsystem clock to the main system clock first cl
167. ion 9 1 of 0 a3 ae at do Example If the EMB flag is set the instruction SMB 0 selects the data memory address range for bank 0 000 as the working memory bank 5 84 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET SRB Select Register Bank SRB n Description The SRB instruction selects one of four register banks in the working register memory area The constant value used with SRB is 0 1 2 or 3 The following table shows the effect of SRB settings ERB Setting SRB Settings Selected Register Bank x Always set to bank 0 Bank 0 NOTE x not applicable The enable register bank flag ERB must always be set for the SRB instruction to execute successfully for register banks 0 1 2 and 3 In addition if the ERB value is logic zero register bank 0 is always selected regardless of the SRB value of 1 do Example If the ERB flag is set the instruction SRB 3 selects register bank 3 018 01 as the working memory register bank ELECTRONICS 5 85 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 SRET Return From Subroutine and Skip SRET Return from subroutine and skip Description SRET is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a CALL or CALLS instruction SRET skips the resulting address which is general
168. ion EA HL leaves RAM location 20H with the value 00111111B and the extended accumulator with the value 75H 01110101 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET XCH D Exchange and Decrement XCHD dst src A HL Exchange A and data memory contents decrement 1 2 65 contents of register L and skip on borrow Description The instruction XCHD exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then decrements the contents of register L If the content of register L is OFH the next instruction is skipped The value of the carry flag is not affected A HL 1 1 1 1 1 1 HL then L L 1 skip if L OFH Example Register pair HL contains the address 20H and internal RAM location 20H contains the value OFH LD HL 20H LD A 0H XCHD A HL A OFH and L lt L 1 HL lt 0 JPS XXX Skipped since a borrow occurred JPS YYY He 2H L lt 0FH YYY XCHD A HL 2FH lt lt 2FH L L 1 OEH The JPS YYY instruction is executed since a skip occurs after the XCHD instruction ELECTRONICS 5 91 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Exchange and Increment XCHI dst src A HL Exchange A and data memory contents increment 1 2 65 contents of register and skip on overflow Description The instruction XCHI exchanges the contents of the accumulator with
169. ion Device Number KS57P write down the ROM code number Product Order Form Package Pellet Wafer If the product order form is package Package Type Package Marking Check One Standard Custom A C Custom B Max 10 chars Max 10 chars each line SEC YWW YWW YWW Device Name Device Name 2271 Assembly site code Y Last number of assembly year WW Week of assembly Delivery Dates and Quantity ROM Code Release Date Required Delivery Date of Device Please answer the following questions What is the purpose of this order New product development Upgrade of an existing product Replacement of an existing microcontroller Other If you are replacing an existing microcontroller please indicate the former microcontroller name What the main reasons you decided to use a Samsung microcontroller in your product Please check all that apply Price Product quality Features and functions Development system Technical support Delivery on time Used same micom before Quality of documentation Samsung reputation Customer Information Company Name Telephone number Signatures Person placing the order Technical Manager For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back c
170. ion leakage current could be flown because of the floating state in the internal bus Given that bit 3 of the PCON register is cleared to logic zero and all systems operational the instruction sequence STOP NOP NOP NOP sets bit 3 of the PCON register to logic one stopping all controller operations with the exception of some peripheral hardware The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed ELECTRONICS 5 87 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Load EMB ERB and Vector Address VENTn dst EMB 0 1 Load enable memory bank flag EMB and the enable 2 2 ERB 0 1 register bank flag ERB and program counter to ADR vector address then branch to the corresponding location Description The VENT instruction loads the contents of the enable memory bank EMB and enable register bank flag ERB into the respective vector addresses It then points the interrupt service routine to the corresponding branching locations The program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines The EMB and ERB flags should be modified using VENT before the vector interrupts are acknowledged Then when an interrupt is generated the EMB and ERB values of t
171. l selected as serial CPU clock is selected clock clock clock as the serial clock Timer counter 0 Operates only if Operates only if Operates only if Timer counter 0 TCLO is selected as TCLO is selected TCLO is selected as operates counter clock counter clock counter clock Watch timer Operates only if sub Watch timer stops Watch timer stops Watch timer clock fxt is selected operates as counter clock LCD controller Operates only if sub LCD controller stops LCD controller stops LCD controller clock fxt is selected operates as LCD clock LCDCK External INT1 and INT2 are INTO INT1 and INT2 INT1 and INT2 are INT1 and INT2 are interrupts acknowledged INTO is not serviced acknowledged INTO acknowledged INTO is not serviced is not serviced is not serviced All CPU operations are disabled Mode release Interrupt request Only RESET input Interrupt request signals except INTO signal signals except INTO pre enabled by IEx or RESET input pre enabled by IEx or RESET input NOTES 1 Subclock stops by setting SCMOD 2 to 1 2 Main and sub clock oscillation continues ELECTRONICS 8 2 RO 557 2308 2308 2316 2316 POWER DOWN IDLE MODE TIMING DIAGRAMS OSCILLATION IDLE STABILIZATION INSTRUCTION 31 3 ms 4 19 MHz q NORMAL MODE IDLE MODE NORMAL MODE j T s n n Y a CLOCK NORMAL OSCILLATION SIGNAL Figure 8 1 Timing When Idle Mode is Released
172. lag is set DA b Test specified bit and skip if memory bit is set Test specified memory bit and skip if bit equals 0 2 Test specified bit skip and clear if memory bit is set Load specified memory bit to carry bit C memb L Load specified indirect memory bit to carry bit C H DA b 5 12 ELECTRONICS Set specified memory bit Clear specified memory bit to logic zero Logical AND carry flag with specified memory bit 2 Logical OR with specified memory bit Exclusive OR carry with specified memory bit Load carry bit to a specified indirect memory bit E72 RR 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET BINARY CODE SUMMARY This section contains binary code values and operation notation for each instruction in the SAM47 instruction set in an easy to read tabular format It is intended to be used as a quick reference source for programmers who are experienced with the SAM47 instruction set The same binary values and notation are also included in the detailed descriptions of individual instructions later in Section 5 If you are reading this user s manual for the first time please just scan this very detailed information briefly Most of the general information you will need to write application programs can be found in the high level summary tables in the previous section The following information is provided for each instruction Instruction name Operand s Binary values Operation nota
173. lag is set and its corresponding IEx flag is enabled the interrupt service routine is not executed until the IME flag is set to logic one The IME flag is located in the IPR register IPR 3 It can be directly be manipulated by El and DI instructions regardless of the current value of the enable memory bank flag EMB ME IPR2 IPRi IPRO EffectofBitSettings Inhibit all interrupts Enable all interrupts Interrupt Enable Flags IEx IEx flags when set to logical one enable specific interrupt requests to be serviced When the interrupt request flag is set to logical one an interrupt will not be serviced until its corresponding IEx flag is also enabled Interrupt enable flags can be read written or tested directly by 1 bit instructions IEx flags can be addressed directly at their specific RAM addresses despite the current value of the enable memory bank EMB flag Table 7 7 Interrupt Enable and Interrupt Request Flag Addresses Ades Sz o o mw re o e Eme Memo FBEH IE1 IRQ1 NOTES 1 IEx refers to all interrupt enable flags 2 IRQx refers to all interrupt request flags 3 IEx 0 is interrupt disable mode 4 IEx 1 is interrupt enable mode LECTRONI 7 12 ELECTRONICS 557 2308 2308 2316 2316 INTERRUPTS Interrupt Request Flags IRQx Interrupt request flags are read write addressable by 1 bit or 4 bit instructions
174. latch is inverted and the TCO generated clock signal is output to the TCLOO pin 5 PROGRAMMING TIP TCO Signal Output to the TCLOO Pin Output a 30 ms pulse width signal to the TCLOO pin BITS EMB SMB 15 LD EA 79H LD TREFO EA LD EA 4CH LD TMODO EA LD EA 04H LD PMG2 EA P2 0 output mode BITR P2 0 Clear P2 0 output latch BITS TOEO ELECTRONICS 11 15 TIMERS and TIMER COUNTERS 557 2308 2308 2316 2316 TCO SERIAL I O CLOCK GENERATION Timer counter 0 can supply a clock signal to the clock selector circuit of the serial I O interface for data shifter and clock counter operations These internal SIO operations are controlled in turn by the SIO mode register SMOD This clock generation function enables you to adjust data transmission rates across the serial interface and TREFO register settings to select the frequency and interval of the TCO clock signals to be used as SCK input to the serial interface The generated clock signal is then sent directly to the serial clock selector circuit the TOEO flag may be disabled 0 EXTERNAL INPUT SIGNAL DIVIDER By selecting an external clock source and loading a reference value into the TCO reference register TREFO you can divide the incoming clock signal by the TREFO value and then output this modified clock frequency to the TCLOO pin The sequence of operations used to divide external clock input can be summarized as follows
175. le 4 bit pull up resistors are software assignable Ports 6 and 7 can be paired for 8 bit data transfer 8 0 8 7 1F8H 1FFH Output port for 1 bit data for use as CMOS driver only Table 10 2 Port Pin Status During Instruction Execution Instruction Type Example Input Mode Status Output Mode Status 1 bit test BTST Input or test data at each pin Input or test data at output latch 1 bit input LDB C P1 3 4 bit input m A PO 8 bit input 4 1 bit output BITR P2 3 Output latch contents undefined Output pin status is modified 4 bit output P2 A Transfer accumulator data to the Transfer accumulator data to the 8 bit output T P6 EA output latch output pin LECTRONICS 10 2 ELECTRO 557 2308 2308 2316 2316 VO PORTS PORT MODE FLAGS PM FLAGS Port mode flags PM are used to configure I O ports to input or output mode by setting or clearing the corresponding I O buffer For convenient program reference PM flags are organized into two groups PMG1 and 2 as shown Table 10 3 They are addressable by 8 bit write instructions only When a PM flag is 0 the port is set to input mode when it is 1 the port is enabled for output RESET clears all port mode flags to logical zero automatically configuring the corresponding ports to input mode Table 10 3 Port Mode Group Flags PM Group ID Bit 3 7 Bit 2 6 Bit 1 5 Bit 0 4 FE8H PM3 3 PM3 2 PM3 1 PM3 0 FE9H PM6 3 PM6 2 PM
176. ll Configure P5 3 as a n channel open drain 5 2 P5 2 N Channel Open Drain Configurable Bit Configure P5 2 as a push pull Configure P5 2 as a n channel open drain 5 1 P5 1 N Channel Open Drain Configurable Configure P5 1 as a push pull Configure P5 1 as a n channel open drain 5 0 P5 0 N Channel Open Drain Configurable Configure P5 0 as a push pull gt Configure P5 0 as a n channel open drain PNE4 3 P4 3 N Channel Open Drain Configurable Bit Configure P4 3 as a push pull Configure P4 3 as a n channel open drain PNE4 2 P4 2 N Channel Open Drain Configurable Bit Configure P4 2 as a push pull le Configure P4 2 as a n channel open drain PNEA 1 P4 1 N Channel Open Drain Configurable Bit Configure P4 1 as a push pull Configure 4 1 as n channel open drain PNE4 0 P4 0 N Channel Open Drain Configurable Bit Configure P4 0 as a push pull Configure P4 0 as a n channel open drain N ELECTRONICS 4 MEMORY 557 2308 2308 2316 2316 5 Program Status Word FB1H FBOH Bit 7 6 5 4 3 2 1 0 RESET Value 1 0 0 0 0 0 0 0 Read Write R W R R R R W R W R W R W Bit Addressing 2 8 8 8 1 4 8 1 4 8 1 4 8 1 4 8 Carry No overflow borrow condition exists An overflow or borrow condition does exist 5 2 5 0 Skip Condition Flags skip condition exists no direct manipulation of these bits is a
177. llowed A skip condition exists no direct manipulation of these bits is allowed 151 ISO Interrupt Status Flags EEN Service all interrupt requests 1 Service only the high priority interrupt s as determined in the interrupt priority register IPR KEE Do not service any more interrupt requests Undefined EMB Enable Data Memory Bank Flag Restrict program access to data memory to bank 15 and to the locations 000 07 in the bank 0 only Enable full access to data memory banks 0 1 2 and 15 ERB Enable Register Bank Flag Select register bank 0 as working register area 1 Select register banks 0 1 2 or 3 as working register area in accordance with the select register bank SRB instruction operand NOTES 1 The value of the carry flag after a RESET occurs during normal operation is undefined If a RESET occurs during power down mode IDLE or STOP the current value of the carry flag is retained 2 The flag can only be addressed by a specific set of 1 bit manipulation instructions See Section 2 for detailed information 4 24 ELECTRONICS 557 2308 2308 2316 2316 MEMORY PUMOD Pull Up Resistor Mode Register FDDH FDCH Bit 7 6 5 4 3 2 1 0 identifier Pur7 Pure PUR5 PUR2 PUR PURO RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W w W Bit Addressing 8 8 8 8 8 8 8 8 PUR7 onnect Disconnect Port 7 Pull Up
178. ly the instruction immediately after the point at which the subroutine was called Then program execution continues from the resulting address and the contents of the location addressed by the stack pointer are popped into the program counter PC13 8 lt SP 1 SP PC7 0 lt SP 3 SP 2 EMB ERB lt SP 4 SP SP 6 Example If the stack pointer contains the value and RAM locations OFBH OFCH and OFDH contain the values 1H and 2H respectively the instruction SRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 0125H then skips unconditionally During a return from subroutine data is popped from the stack to the PC as follows SP 4 6 00H 5 86 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET STOP Stop Operation STOP Operation Description Example The STOP instruction stops the system clock by setting bit 3 of the power control register PCON to logic one When STOP executes all system operations are halted with the exception of some peripheral hardware with special power down mode operating conditions In application programs a STOP instruction must be immediately followed by at least three NOP instructions This ensures an adequate time interval for the clock to stabilize before the next instruction is executed If more than three NOP instructions are not used after STOP instruct
179. m ELECTRONICS 12 1 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 LCD CIRCUIT DIAGRAM SEG31 P8 7 SEG30 P8 6 SEG29 P8 5 SEG28 P8 4 SEG27 P8 3 SEG26 P8 2 SEG25 P8 1 SEG24 P8 0 SEG23 SEG22 SEG21 SEG20 SEG19 TIMING COM CONTROLLER CONTROL LCD VOLTAGE CONTROL s Port 3 latch Figure 12 2 LCD Circuit Diagram LECTRONI 42 2 ELECTRONICS 557 2308 2308 2316 2316 LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA RAM addresses of bank 1 are used as LCD data memory These locations can be addressed by 1 bit 4 bit instructions When the bit value of a display segment is 1 the LCD display is turned on when the bit value is 0 the display is turned off Display RAM data are sent out through segment pins SEGO SEG31 using a direct memory access DMA method that is synchronized with the fj cp signal RAM addresses in this location that not used for LCD display can be allocated to general purpose use COM3 COM2 COM1 COMO Figure 12 3 LCD Display Data RAM Organization Table 12 1 Common Signal Pins Used per Duty Cycle NC 18 1 2 18 NOTE no connection is required am ELECTRONICS 12 3 LCD CONTROLLER DRIVER 557 2308 2308 2316 2316 LCD CONTROL REGISTER The LCD control register LCON is used to turn the LCD display on and off to output LCD clock LCDCK and synchronizing sign
180. m are used consecutively in a program sequence only the first instruction is executed but the following redundant instructions are ignored that is they are handled like a NOP instruction When LD HL imm instructions are used consecutively the following redundant instructions are also ignored In the following example only the LD A instruction will be executed The 8 bit load instruction which follows it is interpreted as redundant and is ignored LD A im Load 4 bit immediate data im to accumulator LD Load 8 bit immediate data to extended accumulator In this example the statements LD A 2H and LD A 3H are ignored BITR EMB LD A 1H 4 Execute instruction LD A 2H Ignore redundant instruction LD A 3H Ignore redundant instruction LD 23H A Execute instruction 023H lt 1H If consecutive LD HL imm instructions load 8 bit immediate data to the 8 bit memory pointer pair HL are detected only the first LD is executed and the LDs which immediately follow are ignored For example LD HL 10H HL 10H LD HL 20H Ignore redundant instruction LD A 3H A LD EA 35H Ignore redundant instruction LD HL A 10H 3H If an instruction reference with a REF instruction has a redundancy effect the following conditions apply Ifthe instruction preceding the REF has a redundancy effect this effect is cancelled and the referenced instruction is not
181. me by a reset is 31 3 ms at 4 19 MHz main oscillation clock 6 8 ELECTRONICS 557 2308 2308 2316 2316 OSCILLATOR CIRCUITS Table 6 5 System Operating Mode Comparison Condition STOP IDLE Mode Start Current Method Consumption A Main operating mode Main oscillator runs Sub oscillator runs stops System clock is the main oscillation clock Main Idle mode Main oscillator runs IDLE instruction Sub oscillator runs stops System clock is the main oscillation clock Main Stop mode Main oscillator runs STOP instruction Sub oscillator runs System clock is the main oscillation clock Sub operating mode Main oscillator is stopped by C SCMOD 3 Sub oscillator runs System clock is the sub oscillation clock Sub Idle Mode Main oscillator is stopped by IDLE instruction SCMOD 3 Sub oscillator runs System clock is the sub oscillation clock Sub Stop mode Main oscillator is stopped by Setting SCMOD 2 to 1 SCMOD 3 This mode can be released Sub oscillator runs only by an external reset System clock is the sub oscillation clock Main Sub Stop mode Main oscillator runs STOP instruction Sub oscillator is stopped by This mode can be released SCMOD 2 by an interrupt and reset System clock is the main oscillation clock NOTE The current consumption is A gt B gt C gt D gt E ELECTRONICS 6 9 OSCILLATOR CIRCUITS 557 2308 2308 2316 2316 SWITCHING THE CPU CLOCK Together bit sett
182. n Table 6 6 4 means not available 5 fx Main system clock fxt Sub system clock M C Machine Cycle When fx is 4 19 MHz and fxt is 32 768 kHz 5 PROGRAMMING Switching Between Main System and Subsystem Clock 1 Switch from the main system clock to the subsystem clock MA2SUB BITS SCMOD 0 Switches to subsystem clock CALL DLY80 Delay 80 machine cycles BITS SCMOD 3 Stop the main system clock RET DLY80 LD A 0FH DEL1 NOP NOP DECS A JR DEL1 RET 2 Switch from the subsystem clock to the main system clock SUB2MA BITR SCMOD 3 Start main system clock oscillation CALL DLY80 Delay 80 machine cycles CALL DLY80 Delay 80 machine cycles BITR SCMOD 0 Switch to main system clock RET ELECTRONICS 6 11 OSCILLATOR CIRCUITS 557 2308 2308 2316 2316 CLOCK OUTPUT MODE REGISTER CLMOD The clock output mode register CLMOD is a 4 bit register that is used to enable or disable clock output to the CLO pin and to select the CPU clock source and frequency CLMOD is addressable by 4 bit write instructions only RESET clears CLMOD to logic zero which automatically selects the CPU clock as the clock source without initiating clock oscillation and disables clock output CLMOD 3 is the enable disable clock output control bit CLMOD 1 and are used to select one of four possible clock sources and frequencies normal CPU clock fxx 8 fxx 16 or fxx 64 Table 6 7 Clock Output M
183. n writing programs that use special purpose areas of the ROM VECTOR ADDRESS AREA The 12 byte vector address area of the ROM is used to store the vector addresses for executing system resets and interrupts The starting addresses of interrupt service routines are stored in this area along with the enable memory bank EMB and enable register bank ERB flag values that are needed to initialize the service routines 12 byte vector addresses are organized as follows PC6 PC5 PC4 PC3 PC2 PC1 NOTE 1 is used for KS57C2316 P2316 microcontroller To set up the vector address area for specific programs use the instruction VENTn The programming tips on the next page explain how to do this VECTOR ADDRESS AREA 12 Bytes GENERAL PURPOSE AREA 20 Bytes INSTRUCTION REFERENCE AREA GENERAL PURPOSE AREA 8 064 Bytes 16 256 Bytes Figure 2 1 ROM Address Structure Figure 2 2 Vector Address Structure 2 2 ELECTRONICS 557 2308 2308 2316 2316 I PROGRAMMING Defining Vectored Interrupts ADDRESS SPACES The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory 1 When all vector interrupts are used ORG 0000H VENTO 1 0 RESET VENT1 0 0 INTB VENT2 0 0 INTO VENT3 0 0 INT1 VENTA 0 0 INTS 5 0 0 INTTO EMB EMB EMB EMB EMB EMB ETTTTT 1 ERB 0 ERB 0 ERB 0 ERB 0 ERB 0 ERB lt 0 Jump to RESET a
184. n x oscillator frequency n 4 8 64 Figure 16 2 Standard Operating Voltage Range Table 16 10 RAM Data Retention Supply Voltage in Stop Mode TA 40 C to 85 C Release signal set time tsREL Normal operation lus Oscillator stabilization wait Released by RESET H time 1 Released by interrupt 2 NOTES 1 During oscillator stabilization wait time all CPU operations must be stopped to avoid instability during oscillator start up 2 Use the basic timer mode register BMOD interval timer to delay execution of CPU instructions during the wait time 16 10 ELECTRONICS 557 2308 2308 2316 2316 557 2308 2316 TIMING WAVEFORMS INTERNAL RESET 4 14 STOP MODE a IDLE MODE Y p OPERATING lt DATA RETENTION MODE gt 4 EXECUTION OF STOP INSTRUCTION Figure 16 3 Stop Mode Release Timing When Initiated By RESET IDLE MODE NORMAL STOP MDE OPERATING 4 DATA RETENTION 4 STOP INSTRUCTION POWER DOWN MODE TERMINATING SIGNAL INTERRUPT REQUEST Figure 16 4 Stop Mode Release Timing When Initiated By Interrupt Request ELECTRONICS 16 11 557 2308 2316 557 2308 2308 2316 2316 0 8 MEASUREMENT POINTS Figure 16 5 A C Timing Measurement Points Except XIN XTjn Figure 16 6 Clo
185. ng or falling edge detected at INT1 pin IEO INTO Interrupt Enable Flag Disable interrupt requests at the INTO pin 1 Enable interrupt requests at the INTO pin IRQO INTO Interrupt Request Flag Generate INTO interrupt This bit is set and cleared automatically by hardware when rising or falling edge detected at INTO pin 4 8 ELECTRONICS 557 2308 2308 2316 2316 MEMORY IE2 1802 INT2 Interrupt Enable Request Flags FBFH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 EE Always logic zero IE2 INT2 Interrupt Enable Flag Disable INT2 interrupt requests the 2 pin Enable INT2 interrupt requests at the INT2 pin IRQ2 INT2 Interrupt Request Flag Generate INT2 quasi interrupt This bit is set and is not cleared automatically by hardware when a rising or falling edge is detected at INT2 or KSO KS7 respectively Since INT2 is a quasi interrupt IRQ2 flag must be cleared by software ELECTRONICS 4 9 557 2308 2308 2316 2316 IE4 IRQ4 Interrupt Enable Request Flags FB8H IEB IRQB Interrupt Enable Request Flags FB8H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 IEA IRQ4 IEB IRQB INT4 Interrupt Request Flag Generate INT4 interrupt This bit is set and cleared automatically by hardware when rising or falling signal edge detec
186. nterrupt every 3 91 ms At its normal speed WMOD 1 0 the watch timer generates an interrupt request every 0 5 seconds High speed mode is useful for timing events for program debugging sequences Check Subsystem Clock Level Feature The watch timer can also check the input level of the subsystem clock by testing WMOD 3 If WMOD 3 is 1 the input level at the XT N pin is high if WMOD 3 is 0 the input level at the XT N pin is low ELECTRONICS 11 23 TIMERS TIMER COUNTERS 557 2308 2308 2316 2316 Enable Disable Selector Circuit e a r e fw 2 22 256 Dividing Circuit Clock Selector 32 768 kHz fw 2 512 Hz fx Main System Clock 4 19 MHz fxt Subsystem Clock 32 768 kHz 6509128 fw Watch Timer Frequency fxx System Clock Figure 11 4 Watch Timer Circuit Diagram 11 24 ELECTRONICS 557 2308 2308 2316 2316 TIMERS TIMER COUNTERS WATCH TIMER MODE REGISTER WMOD The watch timer mode register WMOD is used to select specific watch timer operations It is 8 bit write only addressable An exception is WMOD bit the XT y input level control bit which is 1 bit read only addressable A RESET automatically sets WMOD 3 to the current input level of the subsystem clock XT high if logic one low if logic zero and all other WMOD bits to logic zero In summary WMOD settings control the foll
187. ntinue ordering this device Yes If so how much will you be ordering PCS Application Product Model ID Audio LCD Databank Caller ID LCD Game Industrials Home Appliance Office Automation Remocon Other Please describe detail its application NOTES 1 Once you choose a read protection you cannot read again the programming code from the EPROM 2 OTP writing will be executed in our manufacturing site 3 writing program is completely verified by a customer Samsung does not take on any responsibility for errors occurred from the writing program For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book
188. o program memory location 0345H Executing the instruction CALLS PLAY at location 0123H will generate the following values SP OH OFEH EMB ERB 2H OFCH 5H 1H PC 0345H Data is written to stack locations as follows ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET CCF Complement Carry Flag CCF Description carry flag is complemented if 1 it is changed to 0 and vice versa p __ 1 Example If the carry flag is logic zero the instruction CCF changes the value to logic one ELECTRONICS 5 47 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Complement Accumulator COM A Description The accumulator value is complemented if the bit value of A is 1 it is changed to 0 and vice versa If the accumulator contains the value 4H 0100 the instruction COM A leaves the value OBH 1011B in the accumulator 5 48 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET CPSE Compare and Skip if Equal CPSE dst src operation oporana Operation Summary Bytes Ram Compare and skip it register equals 2 2 5_ GHLfm Compare and skip data memory cauas fm 2 2 S aR CompareandskitAcqash 2 a A
189. ocation OEABH will load the program counter with the value OOFFH Normally the instruction jumps to the address in the block in which the instruction is located If the first byte of the instruction code is located at address xFFEH or xFFFH the instruction will jump to the next block If the instruction JPS SUB were located instead at program memory address OFFEH or OFFFH the instruction JPS SUB would load the PC with the value 10FFH causing a program malfunction ELECTRONICS 5 57 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 J R Jump Relative Very Short JR dst im Branch to relative immediate address WX Branch relative to contents of WX register EA Branch relative to contents of EA Description JR causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the PC The range of the relative address is current PC 15 to current PC 16 The destination address for this jump is specified to the assembler by a label an actual address or by immediate data using a plus sign or a minus sign For immediate addressing the range is from 2 to 16 and the range is from 1 to 15 If a 0 1 or any other number that is outside these ranges are used the assembler interprets it as an error For JR WX and JR EA branch relative instructions the valid range for the relative address is OH OFFH The destination address fo
190. ocations 000H 07FH of bank 0 and bank 15 With indirect addressing only bank 0 000 can be accessed When the EMB flag is set to logic one all three data memory banks can be accessed according to the current SMB value For 8 bit addressing two 4 bit registers are addressed as a register pair Also when using 8 bit instructions to address RAM locations remember to use the even numbered register address as the instruction operand Working Registers The RAM working register area in data memory bank 0 is further divided into four register banks bank 0 1 2 and 3 Each register bank has eight 4 bit registers and paired 4 bit registers are 8 bit addressable Register A is used as a 4 bit accumulator and register pair EA as an 8 bit extended accumulator The carry flag bit can also be used as a 1 bit accumulator Register pairs WX WL and HL are used as address pointers for indirect addressing To limit the possibility of data corruption due to incorrect register addressing it is advisable to use register bank 0 for the main program and banks 1 2 and 3 for interrupt service routines LCD Data Register Area Bit values for LCD segment data are stored in data memory bank 1 Register locations in this area that are not used to store LCD data can be assigned to general purpose use 2 6 ELECTRONICS 557 2308 2308 2316 2316 ADDRESS SPACES Table 2 2 Data Memory Organization and Addressing 000H 01FH Working registers 0
191. ode Sub stop mode can be terminated by RESET only When an interrupt is used to release power down mode the operation differs depending on the value of the interrupt master enable flag IME Ifthe IME flag 0 program execution starts immediately after the instruction issuing a request to enter power down mode is executed The interrupt request flag remains set to logical one Ifthe IME flag 1 two instructions are executed after the power down mode release and the vectored interrupt is then initiated However when the release signal is caused by INT2 or INTW the operation is identical to the IME 0 condition Assuming that both interrupt enable flag and interrupt request flag are set to 1 the release signal is generated when power down mode is entered ELECTRONICS 8 1 POWER DOWN 557 2308 2308 2316 2316 Table 8 1 Hardware Operation During Power Down Modes System clock Main clock fx Sub clock fxt Main clock fx 1 Main fx or sub clock fxt STOP Setting SCMOD 2 to STOP IDLE 1 Clock oscillator Main clock oscillation Sub clock oscillation Main clock oscillation Only CPU clock stops stops stops stops 2 Basic timer stops Basic timer stops Basic timer stops Basic timer operates Serial operates only if operates only if operates only if operates only if a interface external is external SCK is external SCK is clock other than the selected as serial selected as seria
192. ode Register CLMOD Organization O 0 CPU clock fx4 8 fx 64 C sk mamam Tm 64 65 5 2 CLMOD 3 Result of CLMOD 3 Setting Clock output is disabled 2 1 Clock output enabled NOTE Assumes that fxx 4 19 MHz 6 12 ELECTRONICS 557 2308 2308 2316 2316 OSCILLATOR CIRCUITS CLOCK OUTPUT CIRCUIT The clock output circuit used to output clock pulses to the CLO pin has the following components 4 bit clock output mode register CLMOD Clock selector Port mode flag CLO output pin P2 2 CLMOD 3 CLMOD 2 CLMOD 1 CLMOD 0 fxx 8 fxx 16 fxx 64 CPU clock Figure 6 7 CLO Output Pin Circuit Diagram CLOCK OUTPUT PROCEDURE The procedure for outputting clock pulses to the CLO pin may be summarized as follows Disable clock output by clearing CLMOD 3 to logic zero Set the clock output frequency CLMOD 1 CLMOD 0 Load 0 to the output latch of the CLO pin P2 2 Set the P2 2 mode flag PM2 to output mode Enable clock output by setting CLMOD 3 to logic one Qr NM ELECTRONICS 6 13 OSCILLATOR CIRCUITS 557 2308 2308 2316 2316 5 PROGRAMMING CPU Clock Output to the CLO Pin To output the CPU clock to the CLO pin 6 14 BITS SMB EMB 15 EA 04H PMG2 EA P2 lt Output mode P2 2 Clear P2 2 pin output latch A 9H CLMOD A ELECTRONICS 557 2308 2308 2316 2316 INTERRUPTS
193. olute Maximum Ratings Ta 25 C Symbol w o ees OOo oo i ew _ Output Current High All I O ports active _ CAN Output Current Low One I O pin active aM e Total value for ports 0 2 3 and 5 100 Peak value u i Total value for ports 4 6 and 7 NOTE The values for Output Current Low are calculated as Peak Value x Duty DD loL TA Table 14 2 D C Electrical Characteristics TA 40 C to 85 Vpp 1 8 V to 5 5 V Parameter Symbol Input high All input pins except those 0 7 Vpp voltage D specified below for Vino Input low Ports 2 3 4 and 5 NC NEN Xin Xout XTn and voltage Ports 0 2 3 4 5 6 7 and BIAS Port 8 ONLY 14 2 C ELECTRONICS 557 2308 2308 2316 2316 ELECTRICAL DATA Table 14 2 D C Electrical Characteristics Continued Ta 40 C to 85 C Vpp 1 8 V to 5 5 V Output low voltage Input high leakage current Input low leakage current Output high leakage current Output low leakage current Pull up resistor LCD voltage dividing resistor SEG output impedance COM output voltage deviation SEG output voltage deviation ELECTRONICS _ Min Units __ _ i 3 1 0 7 25 47 100 V
194. on Stabilization After RESET ELECTRONICS 9 1 RESET 557 2308 2308 2316 2316 HARDWARE REGISTER VALUES AFTER RESET Table 9 1 gives you detailed information about hardware register values after a RESET occurs during power down mode or during normal operation Table 9 1 Hardware Register Values After RESET Hardware Component If RESET Occurs During If RESET Occurs During or Subcomponent Power Down Mode Normal Operation Program counter PC Lower five bits of address 0000H Lower five bits of address 0000 are transferred to 12 13 8 are transferred to 12 13 8 and the contents of 0001H to and the contents of 0001H to PC7 0 PC7 0 Program Status Word PSW Bank enable flags EMB ERB Bit 6 of address 0000H in Bit 6 of address 0000H in program memory is transferred to program memory is transferred to the ERB flag and bit 7 of the the ERB flag and bit 7 of the address to the EMB flag address to the EMB flag Stack pointer SP Undefined Undefined Data Memory RAM Working registers E A L H X W Z Y Undefined Bank selection registers SMB SRB PO BSC register BSCO BSC3 x 0 _____ Power control register PCON EHI Clock output mode register CLMOD System clock control reg SCMOD EE LECTRONI 9 2 ELECTRONICS 557 2308 2308 2316 2316 RESET Table 9 1 Hardware Register Values After RESET Continued Hardware Component If RESET Occurs During If R
195. on of rising 20 Input A 1 or falling edge KSO KS7 Quasi interrupt inputs with falling edge 44 51 P6 0 P7 3 Input detection BUZ 2 4 16 kHz frequency output for buzzer 31 2 3 Input sound with 4 19 MHz main system clock or 32 768 kHz subsystem clock XIN Crystal ceramic or RC oscillator pins for main 15 14 XOUT system clock For external clock input use and input 5 reverse phase to XTIN Crystal oscillator pins for subsystem clock 17 18 XTOUT For external clock input use XT iN and input XT n s reverse phase to XTour e _ o fem 141 21 11 sr Pests Test sona input mustbe comecei ves NOTES 1 Pull up resistors for all I O ports are automatically disabled if they are configured to output mode 2 D Type has a schmitt trigger circuit at input 1 6 ELECTRONICS 557 2308 2308 2316 2316 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS gt P CHANNEL P CHANNEL OUT lt N CHNNEL N CHANNEL OUTPUT DISABLE Figure 1 3 Pin Circuit Type A Figure 1 5 Pin Circuit Type C PULL UP PULL UP RESISTOR RESISTOR RESISTOR RESISTOR P CHANNEL o lt ENABLE ENABLE P CHANNEL DATA CIRCUIT OUTPUT TYPE DISABLE SCHMITT TRIGGER CIRCUIT TYPE A Figure 1 4 Pin Circuit Type A 1 P1 P0 0 P0 3 Figure 1 6 Pin Circuit Type D P0 1 P0 2 P2 P3 P6 P7 ELECTRONICS 1 7 PRODU
196. over of this book 557 2308 OTP FACTORY WRITING ORDER FORM 2 2 Device Number KS57P2308 write down the ROM code number Customer Checksums Company Name Signature Engineer Read Protection Please answer the following questions Are you going to continue ordering this device Yes If so how much will you be ordering PCS Application Product Model ID Audio LCD Databank Caller ID LCD Game Industrials Home Appliance Office Automation Remocon Other Please describe detail its application NOTES 1 Once you choose a read protection you cannot read again the programming code from the EPROM 2 OTP writing will be executed in our manufacturing site 3 writing program is completely verified by a customer Samsung does not take on any responsibility for errors occurred from the writing program For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book 557 2316 OTP FACTORY WRITING ORDER FORM 2 2 Device Number KS57P2316 write down the ROM code number Customer Checksums Company Name Signature Engineer Read Protection i Yes Please answer the following questions Are you going to co
197. owing watch timer functions Watch timer clock selection WMOD 0 Watch timer speed control WMOD 1 Enable disable watch timer WMOD 2 XT input level control WMOD 3 Buzzer frequency selection WMOD 4 and WMOD 5 Enable disable buzzer output WMOD 7 Table 11 8 Watch Timer Mode Register WMOD Organization WMOD 7 Disable buzzer BUZ signal output F89H mew Enable buzzer BUZ signal output Always logic zero WMOD 5 4 2 kHz buzzer BUZ signal output 4 kHz buzzer BUZ signal output 8 kHz buzzer BUZ signal output 16 kHz buzzer BUZ signal output WMOD 3 Input level to pin is lo 1 bit read only F88H il Input level to XTiN pin is high 1 bit read only WMOD 2 Disable watch timer clear frequency dividing circuits und Enable watch timer WMOD 1 Normal mode sets IRQW to 0 5 seconds High speed mode sets IRQW 3 91 ms WMOD 0 Select the system clock fxx 128 as the watch timer clock fw Select subsystem clock as watch timer clock fw NOTE System clock frequency fxx is assumed to be 4 19 MHz subsystem clock fxt is assumed to be 32 768 kHz am ELECTRONICS 11 25 TIMERS TIMER COUNTERS 557 2308 2308 2316 2316 5 PROGRAMMING Using the Watch Timer 1 Select a subsystem clock as the LCD display clock a 0 5 second interrupt and 2 kHz buzzer enable BITS EMB SMB 15 LD EA 04H LD PMG2 EA P2 3 lt output mode BITR P2 3 LD EA 85H
198. p ofo o 1 1 1 1 1 RR RR 1 skip on borrow Examples 1 Register pair HL contains the value 7FH 01111111B The following instruction leaves the value 7EH in register pair HL DECS HL 2 Register A contains the value OH The following instruction sequence leaves the value OFFH in register A Since a borrow occurs the CALL PLAY1 instruction is skipped and the CALL PLAY2 instruction is executed DECS A Borrow occurs CALL PLAY1 Skipped CALL PLAY2 Executed 5 50 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET DI Disable Interrupts DI Operation Operand Operation Summary Disable all interrupts Description Bit 3 of the interrupt priority register IPR IME is cleared to logic zero disabling all interrupts Interrupts can still set their respective interrupt status latches but the CPU will not directly service them CREEBERERC 1 If the IME bit bit 3 of the IPR is logic one 0 all instructions are enabled the instruction DI sets the IME bit to logic zero disabling all interrupts ELECTRONICS 5 51 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Enable Interrupts Description Bit 3 of the interrupt priority register IPR IME is to logic one This allows interrupts to be serviced when they occur assum
199. r these jumps can be specified to the assembler by a label that lies anywhere within the current 256 byte block Normally the JR OWX and JR instructions jump to the address in the page in which the instruction is located However if the first byte of the instruction code is located at address xxFEH or xxFFH the instruction will jump to the next page eee PC13 0 ADR 15 to PC 16 PC13 0 PC13 8 0 PC13 8 First Byte Condition _______ Condtion mem oo e vw wo ______ 5 58 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET J R Jump Relative Very Short JR Continued Examples 1 A short form for a relative jump to label KK is the instruction JR KK where KK must be within the allowed range of current 15 to current PC 16 The JR instruction has in this case the effect of an unconditional JP instruction 2 In the following instruction sequence if the instruction LD WX 02H were to be executed in place of LD WX 00H the program would jump to 1004H and JPS would be executed If LD EA 03H were to be executed the jump would be to1006H and JPS DDD would be executed ORG 1000H JPS AAA JPS BBB JPS CCC JPS DDD LD WX 00H WX 00H LD EA WX ADS WX EA WX lt WX WX J
200. ranch INTTO RESET BITR EMB ELECTRONICS 3 3 ADDRESSING MODES 557 2308 2308 2316 2316 ENABLE MEMORY BANK SETTINGS EMB 1 When the enable memory bank flag EMB is set to logic one you can address the data memory bank specified by the select memory bank SMB value 0 1 or 15 using 1 4 or 8 bit instructions You can use both direct and indirect addressing modes The addressable RAM areas when EMB 1 are as follows If SMB 0 000 If SMB 1 100H 1FFH If SMB 15 F80H FFFH EMB 0 When the enable memory bank flag EMB is set to logic zero the addressable area is defined independently of the SMB value and is restricted to specific locations depending on whether a direct or indirect address mode is used If EMB 0 the addressable area is restricted to locations 000 07 in bank 0 and to locations FB0H FFFH in bank 15 for direct addressing For indirect addressing only locations 000 in bank 0 are addressable regardless of SMB value To address the peripheral hardware register bank 15 using indirect addressing the EMB flag must first be set to 1 and the SMB value to 15 When a RESET occurs the EMB flag is set to the value contained in bit 7 of ROM address 0000H EMB Independent Addressing At any time several areas of the data memory can be addressed independent of the current status of the EMB flag These exceptions are described in Table 3 1 Table 3 1 RAM Addressing
201. rated and skip is executed However the carry flag value is unaffected The instructions BTST BTSF and CPSE also generate a skip signal and execute a skip when they meet a skip condition and the carry flag value is also unaffected Instructions Which Affect the Carry Flag The only instructions which do not generate a skip signal but which do affect the carry flag are as follows ADC LDB C operand SBC BAND C operand SCF BOR C operand RCF BXOR C operand CCF IRET RRC 5 4 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET ADC and SBC Instruction Skip Conditions The instructions ADC A HL SBC A HL can generate a skip signal and set or clear the carry flag when they are executed in combination with the instruction ADS If an ADS A stim instruction immediately follows an ADC A HL or SBC A HL instruction in a program sequence the ADS instruction does not skip the instruction following ADS even if it has a skip function If however ADC A HL or SBC A HL instruction is immediately followed by an ADS instruction the ADC or skips on overflow or if there is no borrow to the instruction immediately following the ADS and program execution continues Table 5 3 contains additional information and examples of the ADC A HL and SBC A HL skip feature Table 5 3 Skip Conditions for ADC and SBC Instructions Sample If t
202. respective address table in program memory is written to the ERB flag setting the correct flag status before the interrupt service routine is executed During the interrupt routine the ERB value is automatically pushed to the stack area along with the other PSW bits Afterwards it is popped back to the 0 bit location The initial ERB flag settings for each vectored interrupt are defined using VENTn instructions 5 PROGRAMMING TIP Using the ERB Flag to Select Register Banks ERB flag settings for register bank selection 1 When ERB 0 SRB 1 Register bank 0 is selected since ERB 0 the SRB is configured to bank 0 LD EA 34H Bank 0 EA 34 LD HL EA Bank 0 HL lt EA SRB 2 Register bank 0 is selected LD YZ EA BankO YZ lt EA SRB 3 Register bank 0 is selected LD WX EA BankO WX EA SRB 1 Register bank 1 is selected LD EA 34H Bank1EA 34 LD HL EA Bank 1 HL lt Bank 1 EA SRB 2 Register bank 2 is selected LD YZ EA Bank 2 YZ lt BANK2 EA SRB 3 Register bank 3 is selected LD WX EA Bank 3 WX lt Bank EA ELECTRONICS 2 19 ADDRESS SPACES 557 2308 2308 2316 2316 SKIP CONDITION FLAGS SC2 SC1 SCO The skip condition flags SC2 SC1 and SCO in the PSW indicate the current program skip conditions and are set and reset automatically during program execution Skip condition flags can only be addressed by 8 bit read instructions Direct manipulation of
203. ress 0500H 66H RET If the instruction LD EA 01H is executed in place of LD EA 00H The content of 0501H 77H is loaded to the EA register If LD EA 02H is executed the content of address 0502H 88H is loaded to EA 5 66 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET LDC Load Code Byte LDC Continued Examples 2 The following instructions will load one of four values defined by the define byte DB directive to the extended accumulator ORG 0500 DB 66H DB 77H DB 88H DB 99H DISPLAY LD WX 00H LDC EA WX EA address 0500H 66H If the instruction LD WX 01H is executed in place of LD WX 00H then lt address 0501H 77H If the instruction LD WX 02H is executed in place of LD WX 00H then lt address 0502H 88H 3 Normally the LDC EA EA and the LDC EA WX instructions reference the table data on the page on which the instruction is located If however the instruction is located at address xxFFH it will reference table data on the next page In this example the upper 4 bits of the address at location 0200H is loaded into register E and the lower 4 bits into register A ORG 01FDH 01FDH LD WX 00H 01FFH LDC EA WX lt upper 4 bits of 0200H address A lt lower 4 bits of 0200H address 4 Here is another example of page referencing with the LDC instruction ORG 0100 DB 67H SMB 0 LD HL 30H Even numb
204. rite instructions In other words SCMOD 0 SCMOD 2 and SCMOD 3 cannot be modified simultaneously by a 4 bit write Bit 1 is always logic zero A subsystem clock can be selected as the system clock by manipulating the SCMOD 3 and SCMOD 0 bit settings If SCMOD 3 0 SCMOD 0 1 the subsystem clock is selected and main system clock oscillation continues If SCMOD 3 1 and SCMOD 0 1 fxt is selected but main system clock oscillation stops If you have selected fx as the CPU clock setting SCMOD 3 to 1 will stop main system clock oscillation But this mode must not be used To stop main system clock oscillation safely main oscillation clock should be stopped only by a STOP instruction in main system clock mode Table 6 3 System Clock Mode Register SCMOD Organization SCMOD Register Bit Settings Resulting Clock Selection SCMOD 3 SCMOD 2 SCMOD 0 fx Oscillation fxt Oscillation CPU Clock note NOTE CPU clock is selected by PCON register settings ELECTRONICS 6 7 OSCILLATOR CIRCUITS 557 2308 2308 2316 2316 Table 6 4 Main Sub Oscillation Stop Mode Mode Condition Method to issue Osc Stop Osc Stop Release Source 2 Main oscillator runs Sub oscillator runs stops System clock is the main oscillation clock Main Oscillation STOP Mode Main oscillator runs Sub oscillator runs System clock is the sub oscillation clock Sub oscillation STOP Mode Main oscillator run
205. ruction Figure 7 1 Interrupt Execution Flowchart ELECTRONICS 7 3 557 2308 2308 2316 2316 INTERRUPTS fee ett t dg 4 IEB IE2 IEW IETO IES IE1 IEO Power Down Mode Release Signal Interrupt Control Unit Noise Filtering Circuit Edge Detection Circuit Vector Interrupt Generator Figure 7 2 Interrupt Control Circuit Diagram ELECTRONICS 7 4 557 2308 2308 2316 2316 INTERRUPTS MULTIPLE INTERRUPTS The interrupt controller can service multiple interrupts in two ways as two level interrupts where either all interrupt requests or only those of highest priority are serviced or as multi level interrupts when the interrupt service routine for a lower priority request is accepted during the execution of a higher priority routine Two Level Interrupt Handling Two level interrupt handling is the standard method for processing multiple interrupts When the 151 and 150 bits of the PSW FBOH 3 and FBOH 2 respectively are both logic zero program execution mode is normal and all interrupt requests are serviced see Figure 7 3 Whenever an interrupt request is accepted IS1 and ISO are incremented by one and the values are stored in the stack along with the other PSW bits After the interrupt routine has been serviced the modified 151 and ISO values are automatically restored from the stack by an IRET instruction 150 and 151 can be manipulated directly by 1 bit write inst
206. ructions regardless of the current value of the enable memory bank flag EMB Before you can modify an interrupt service flag however you must first disable interrupt processing with a DI instruction When 151 0 150 1 all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register IPR Normal Program High or Low Level Interrupt Processing Processing Status 0 High Level Interrupt Processing INT Disable Status 2 SET IPR INT Enable Low or High Level High Level Interrupt Interrupt Generated Generated Figure 7 3 Two Level Interrupt Handling ELECTRONICS 7 5 INTERRUPTS 557 2308 2308 2316 2316 Multi Level Interrupt Handling With multi level interrupt handling a lower priority interrupt request can be executed by manipulating the interrupt status flags ISO and 151 while a high priority interrupt is being serviced see Table 7 2 When an interrupt is requested during normal program execution interrupt status flags ISO and IS1 are set to 1 and 0 respectively This setting allows only highest priority interrupts to be serviced When a high priority request is accepted both interrupt status flags are then cleared to 0 by software so that a request of any priority level can be serviced In this way the high and low priority requests can be serviced in parallel see Figure 7 4 Table 7 2 151 and IS
207. ry contents to A Load register contents to A Load 4 bit immediate data to register Bytes Cycles o N o o o Load 8 bit immediate data to register Load contents of A to direct data memory Load contents of A to register Load indirect data memory contents to EA Load direct data memory contents to EA Load register contents to EA Load contents of A to indirect data memory Load contents of EA to data memory Load contents of EA to register HL EA Load contents of EA to indirect data memory LDI A HL Load indirect data memory to A increment register L contents and skip on carry LDD A HL Load indirect data memory contents to A decrement register L contents and skip on carry LDC EA WX Load code byte from WX to EA EA EA Load code byte from EA to EA RRC A Push register pair onto stack Rotate right through carry bit SB Push SMB and SRB values onto stack Pop to register pair from stack SB 58 Pop SMB and SRB values from stack 5 10 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET Table 5 12 Logic Instructions High Level Summary Logical AND A immediate data to A Logical AND A indirect data memory to A Logical AND register pair RR to EA Logical AND EA to register pair RRb Logical OR immediate data to A Logical OR indirect data memory
208. s Sub oscillator runs System clock is the main oscillation clock Main oscillator runs stops Sub oscillator runs System clock is the sub oscillation clock NOTES 1 This mode must be used STOP instruction Main oscillator stops CPU is in idle mode Sub oscillator still runs stops Set SCMOD 3 to 1 0 Main oscillator stops halting the CPU operation Sub oscillator still runs stops STOP instruction 1 Main oscillator stops CPU is in idle mode Sub oscillator still runs Set SCMOD 3 to 1 Main oscillator stops CPU still operates Sub oscillator still runs Set SCMOD 2 to 1 Main oscillator still runs CPU operates Sub oscillator stops Set SCMOD 2 to 1 Main oscillator still runs stops Sub oscillator stops halting the CPU operation Interrupt and reset After releasing stop mode main oscillation starts and oscillation stabilization time is elapsed And then the CPU operates Oscillation stabilization time is 1 256 x BT clock fx Reset Interrupt can t start the main oscillation Therefore the CPU operation can never be restarted BToverflow and reset After the overflow of basic timer 1 256 x BT clock fxt CPU operation and main oscillation automatically start Set SCMOD 3 to 0 or reset Set SCMOD 2 to 0 or reset 2 Oscillation stabilization time by interrupt is 1 256 x BT clocks Oscillation stabilization ti
209. s example when an INTS interrupt is generated the corresponding vector area is not VENTA INTS but VENT5 INTTO This causes an INTS interrupt to jump incorrectly to the INTTO address and causes a CPU malfunction to occur ELECTRONICS 2 3 ADDRESS SPACES 557 2308 2308 2316 2316 INSTRUCTION REFERENCE AREA Using 1 byte REF instructions you can easily reference instructions with larger byte sizes that are stored in addresses 0020 007 of program memory This 96 byte area is called the REF instruction reference area or look up table Locations in the REF look up table may contain two 1 byte instructions one 2 byte instruction or one 3 byte instruction such as a JP jump or CALL The starting address of the instruction you are referencing must always be an even number To reference a JP or CALL instruction it must be written to the reference area in a two byte format for JP this format is for CALL it is TCALL By using REF instructions you can execute instructions larger than one byte In summary there are three ways you can use the REF instruction Using the 1 byte REF instruction to execute one 2 byte or two 1 byte instructions Branching to any location by referencing a branch instruction stored in the look up table Calling subroutines at any location by referencing a call instruction stored in the look up table I PROGRAMMING TIP Using the REF Look Up Table Here is one example of how to use
210. s tested If it is a 0 the BTSF instruction skips the instruction which immediately follows it otherwise the instruction following the BTSF is executed The destination bit value is not affected operand Binary Code x Operation Notation Dp 0 1 9 Far 6 ao at Cnn memb L Skip if memb 7 2 L 3 2 L 1 0 0 as ae mE RETER T m Fo o or se a0 Second Byte ______ Bit Addresses Addresses mema b ft 22 at FOH FFFH Examples 1 If RAM bit location 30H 2 is set to 0 the following instruction sequence will cause the program to continue execution from the instruction identified as LABEL2 BTSF 30H 2 If 830H 2 0 then skip RET If 830H 2 1 return JP LABEL2 2 You can use BTSF in the same way to test a port pin address bit BTSF P2 0 If P2 0 0 then skip RET If P2 0 1 then return JP LABEL3 ELECTRONICS 5 37 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 5 Test and Skip False BTSF Continued Examples 3 P2 2 P2 3 and 0 are tested LD L 0AH BP2 BTSF P1 L First 1 2 2 1111008 10B 10B OF2H 2 RET INCS L JR BP2 4 Bank 0 location 0 is tested and regardless of the current EMB value BTSF has the following effect FLAG EQU
211. sabling all TCO output Even when the TOEO flag is disabled timer counter 0 can continue to output an internally generated clock frequency via to the serial I O clock selector circuit TCO OUTPUT LATCH TOLO TOLO is the output latch for timer counter 0 When the 8 bit comparator detects a correspondence between the value of the counter register TCNTO and the reference value stored in the TREFO register the TOLO value is inverted the latch toggles high to low or low to high Whenever the state of TOLO is switched the TCO signal is output TCO output may be directed to the TCLOO pin or it can be output directly to the serial clock selector circuit as the SCK signal Assuming TCO is enabled when bit 3 of the TMODO register is set to 1 the TOLO latch is cleared to logic zero along with the counter register TCNTO and the interrupt request flag IRQTO and counting resumes immediately When is disabled TMODO 2 0 the contents of the latch are retained and can be read if necessary 11 20 ELECTRONICS 557 2308 2308 2316 2316 TIMERS and TIMER COUNTERS I PROGRAMMING TIP Setting a TCO Timer Interval To set a 30 ms timer interval for TCO given fxx 4 19 MHz follow these steps 1 Select the timer counter 0 mode register with a maximum setup time of 62 5 ms assume the TCO counter clock fxx 210 and TREFO is set to 2 Calculate the TREFO value TREFO value 1 30 ms 4
212. sed to select normal CPU operating mode or one of two power down modes stop or idle Bits 3 and 2 of the PCON register can be manipulated by a STOP or IDLE instruction to engage stop or idle power down mode The system clock mode control register SCMOD lets you select the main system clock fx or a subsystem clock fxt as the CPU clock and to start or stop main or sub system clock oscillation The resulting clock source either main system clock or subsystem clock is referred to as the CPU clock The main system clock is selected and oscillation started when all SCMOD bits are cleared to logic zero By setting SCMOD 3 SCMOD 2 and SCMOD O to different values CPU can operate a subsystem clock source and start or stop main or sub system clock oscillation To stop main system clock oscillation you must use the STOP instruction assuming the main system clock is selected or manipulate SCMOD 3 to 1 assuming the sub system clock is selected The main system clock frequencies can be divided by 4 8 or 64 and a subsystem clock frequencies can only be divided by 4 By manipulating PCON bits 1 and 0 you select one of the following frequencies as CPU clock fx 4 fxt 4 fx 8 fx 64 Using a Subsystem Clock If a subsystem clock is being used as the selected system clock the idle power down mode can be initiated by executing an IDLE instruction The subsystem clock can be stopped by setting SCMOD 2 to 1 The watch timer bu
213. skipped Ifthe instruction following the REF has a redundancy effect the instruction following the REF is skipped 5 PROGRAMMING Example of the Instruction Redundancy Effect ORG 0020H ABC LD 30 Stored REF instruction reference area ORG 0080H LD EA 40H Redundancy effect is encountered REF ABC No skip EA 30H REF ABC lt 30 LD EA 50H Skip ELECTRONICS 5 3 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Flexible Bit Manipulation In addition to normal bit manipulation instructions like set and clear the SAM47 instruction set can also perform bit tests bit transfers and bit Boolean operations Bits can also be addressed and manipulated by special bit addressing modes Three types of bit addressing are supported mema b memb L H DA b The parameters of these bit addressing modes are described in more detail in Table 5 2 Table 5 2 Bit Addressing Modes and Parameters Addressing Mode Addressable Peripherals Address Range ERB EMB 151 150 IEx IRQx FBOH FBFH H DA b All bit manipulatable peripheral hardware All bits of the memory bank specified by EMB and SMB that are bit manipulatable Instructions Which Have Skip Conditions The following instructions have a skip function when an overflow or borrow occurs XCHI INCS XCHD DECS LDI ADS LDD SBS If there is an overflow or borrow from the result of an increment or decrement a skip signal is gene
214. st Flag Conditions and Priorities Interrupt Internal Pre condition for IRQx Flag Setting Interrupt IRQ Flag Source External Priority Name INTB Reference time interval signal from basic IRQB timer INT4 Both rising and falling edges detected at INT4 IRQ4 INTO Rising or falling edge detected at INTO pin 2 Rising or falling edge detected INT1 pin IRQ1 INTS Completion signal for serial transmit and 4 IRQS receive or receive only operation INTTO Signals for TCNTO and TREFO registers 5 IRQTO match 2 note E Rising edge detected at INT2 or falling edge IRQ2 50 57 detected at KSO KS7 Timeinterval of 0 5 s or 3 19 ms IRo NOTE The quasi interrupt INT2 is only used for testing incoming signals ELECTRONICS 7 13 INTERRUPTS 5 PROGRAMMING TIP Enabling the INTB and INT4 Interrupts To simultaneously enable INTB and INT4 interrupts INTB INT4 7 14 DI BTSTZ IRQB JP INT4 El IRET BITR IRQ4 El IRET IRQB 1 KS57C2308 P2308 C2316 P2316 If no INT4 interrupt if yes INTB interrupt is processed INT4 is processed ELECTRONICS 557 2308 2308 2316 2316 POWER DOWN POWER DOWN OVERVIEW The 557 2308 2316 microcontroller has two power down modes to reduce power consumption idle and stop Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP Several NOP instructions must always follow an ID
215. t Addresses LO ee was or 22 at FOH FFFH Examples 1 If the bit location 30H 2 in the RAM has a current value of 0 the following instruction sets the second bit of location 30H to 1 BITS 30H 2 30H 2 lt 1 2 You can use BITS in the same way to manipulate a port address bit BITS P2 0 P2 0 lt 1 ELECTRONICS 5 33 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 BITS sit set BITS Continued Examples 3 For setting P2 2 P2 3 and P3 0 P3 3 to 1 LD L 0AH BITS P1 L First 1 2 2 1111008 10B 10B OF2H 2 INCS L JR BP2 4 f bank 0 location 0 is set to 1 and the EMB 0 BITS has the following effect FLAG EQU 0 BITR EMB LD H 0AH BITS H FLAG Bank 0 AH 0 0 lt 1 NOTE Since the BITS instruction is used for output functions pin names used in the examples above may change for different devices in the SAM47 product family 5 34 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET BOR Bit Logical or BOR C src b Logical OR carry with specified memory bit 2 2 CGH DAb Description The specified bit of the source is logically ORed with the carry flag bit value The value of the source is unaffected Operand Binary Code operation Notation C mema b C C OR mema b C memb L
216. ted at INT4 pin INTB Interrupt Enable Flag Disable INTB interrupt requests 1 Enable interrupt requests INTB Interrupt Request Flag Generate INTB interrupt This bit is set and cleared automatically by hardware when reference interval signal received from basic timer ELECTRONICS 557 2308 2308 2316 2316 MEMORY IES IRQS ints Interrupt Enable Request Flags FBDH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 EE Always logic zero IES INTS Interrupt Enable Flag Disable INTS interrupt requests 1 Enable INTS interrupt requests IRQS INTS Interrupt Request Flag Generate INTS interrupt This bit is set and cleared automatically by hardware when serial data transfer completion signal received from serial I O interface ELECTRONICS 4 11 MEMORY 557 2308 2308 2316 2316 IRQTO Interrupt Enable Request Flags FBCH Bit 3 2 1 0 Identifier O0 IETO RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 Always logic zero IETO INTTO Interrupt Enable Flag Disable INTTO interrupt requests Enable INTTO interrupt requests IRQTO INTTO Interrupt Request Flag Generate INTTO interrupt This bit is set and cleared automatically by hardware when contents of TCNTO and TREFO registers match 4 12 ELECTRONICS 557 2308 2308
217. ter you can dynamically modify the basic timer clock frequency during program execution Four BT frequencies ranging from fxx 21 to fxx 25 are selectable Since BMOD s reset value is logic zero the default clock frequency setting is 212 The most significant bit of the BMOD register BMOD 3 is used to restart the basic timer When BMOD 3 is set to logic one enabled by a 1 bit write instruction the contents of the BT counter register BCNT and the BT interrupt request flag IRQB are both cleared to logic zero and timer operation is restarted The combination of bit settings in the remaining three registers BMOD 2 BMOD 1 and BMOD 0 determines the clock input frequency and oscillation stabilization interval Table 11 2 Basic Timer Mode Register BMOD Organization Basic Timer Restart Bit Restart basic timer clear BCNT and BMOD 3 to 0 BMOD 2 BMOD 1 Basic Timer Input Clock 212 1 02 kHz 2 0 fxx 250 ms 29 8 18 kHz 217 fxx 31 3 ms __ _ 1 o EENNUN 1 Clock frequencies and stabilization intervals assume a system oscillator clock frequency fxx of 4 19 MHz 2 selected system clock frequency 3 Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released The data in the table column Oscillation Stabilization can also be interpreted as Interrupt Interval Time
218. the RAM location addressed by register pair HL and then increments the contents of register L If the content of register L is OH a skip is executed The value of the carry flag is not affected A HL 11 a 1 c HL then L L skip if L 0H Example Register pair HL contains the address 2FH and internal RAM location 2FH contains OFH LD HL 2FH LD A 0H XCHI A HL lt OFHandL L 120 HL lt 0 JPS XXX Skipped since an overflow occurred JPS YYY H lt 2H L lt OH YYY XCHI A HL 20H lt lt 20H Le L 1 1H The JPS YYY instruction is executed since a skip occurs after the XCHI instruction 5 92 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET XOR Logical Exclusive OR XOR dst src Exclusive OR immediate data to A A HL Exclusive OR indirect data memory to A EA RR Exclusive OR register pair RR to EA RRb EA Exclusive OR register pair RRb to EA ro Description performs bitwise logical operation between the source and destination variables and stores the result in the destination The source contents are unaffected Operand Binary Code operation Notation o a olo acaxonmy ote If the extended accumulator contains 11000011
219. the system clock fxx is used as the signal source according to the following formula System clock fxx Watch tmerceck fw s SISISIT GIU RO die 2 m 128 This feature is useful for controlling timer related operations during stop mode When stop mode is engaged the main system clock fx is halted but the subsystem clock continues to oscillate By using the subsystem clock as the oscillation source during stop mode the watch timer can set the interrupt request flag IRQW to 1 thereby releasing stop mode Clock Source Generation for LCD Controller The watch timer supplies the clock frequency for the LCD controller f Therefore if the watch timer is disabled the LCD controller does not operate 11 22 ELECTRONICS 557 2308 2308 2316 2316 TIMERS TIMER COUNTERS Buzzer Output Frequency Generator The watch timer can generate a steady 2 kHz 4 kHz 8 kHz or 16 kHz signal to the BUZ pin To select the desired BUZ frequency load the appropriate value to the WMOD register This output can then be used to actuate an external buzzer sound To generate a BUZ signal three conditions must be met WMOD 7 register bit is set to 1 output latch for I O port 2 3 is cleared to 0 port 2 3 output mode PM2 set to output mode Timing Tests in High Speed Mode By setting WMOD 1 to 1 the watch timer will function in high speed mode generating an i
220. tion 100 pin connector SMDS2 SMDS2 XTIN Set the XTI switch to XTAL when the target board is used EVA CHIP as a standalone unit and is KS57E2308 not connected to the SMDS2 SMDS2 XTIn XTAL TARGET BOARD Table 17 4 Using Single Header Pins as the Input Path for External Trigger Sources Connector from external trigger EXTERNAL sources of the TRIGGERS application system 1 1 CH2 You can connect an external trigger source to one of the two external trigger channels CH1 or CH2 for the SMDS2 breakpoint and trace functions IDLE LED This LED is ON when the evaluation chip KS57E2308 is in idle mode STOP LED This LED is ON when the evaluation chip KS57E2308 is in stop mode ELECTRONICS 17 5 DEVELOPMENT TOOLS RESET 3 PO O INT4 J P0 2 SO 21 P1 0 INTO O P1 2 INT2 31 P2 0 TCLOO P2 2 CLO L3 P3 0 LCDCK P0 1 SCK Cj P0 3 SI 3 P1 3 TCLO 3 HOLOJNNOO 557 2308 2308 2316 2316 3 5 2 P5 3 O P6 0 KS0 P6 1 KS1 C3 P6 2 KS2 P6 3 KS3 C P7 0 KS4 P7 1 KS5 7 2 56 P7 3 KS7 P8 7 SEG31 P8 6 SEG30 4 P8 5 SEG29 P8 4 SEG28 P8 3 SEG27 P8 2 SEG26 C P8 1 SEG25 P8 0 SEG24 C SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 HOLO3NNOO NId 0F Figure 17 3 40 Pin Connectors for TB572308A 16A TARGET BOARD J1
221. tion The tables in this section are arranged according to the following instruction categories CPU control instructions Program control instructions Data transfer instructions Logic instructions Arithmetic instructions Bit manipulation instructions ELECTRONICS 5 13 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Table 5 15 CPU Control Instructions Binary Code Summary oem nny Goze Operation Ratton SCF SMB c Cops pe er Dr asss sss o 1 0 0 5 0 meme 1 12 11 10 ROM 2 x n 7 6 EMB ERB ROM 2 x n 5 4 13 12 ROM 2 x n 3 0 PC11 8 ROM 2 x n 1 7 0 PC7 0 n 0 1 2 3 4 5 6 7 Fes ae oo 13 R EJ 5 14 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET Table 5 16 Program Control Instructions Binary Code Summary oporana Binary Code Operation me opel ao co o A L 1 ADR14 HEB PC13 0 lt ADR13 0 0 o att a9 1 0 0 11 1 10 a9 0 lt PC13 12 ADR11 eee PC13 0 ADR 1510 PC 16 Errors
222. tion is skipped If however the REF follows a redundant instruction it is executed On the other hand the binary code of a REF instruction is 1 byte The upper 4 bits become the higher address bits of the referenced instruction and the lower 4 bits of the referenced instruction becomes the lower address producing a total of 8 bits or 1 byte see Example 3 below NOTE If the MSB value of the first one byte binary code in instruction is 0 the instruction cannot be referenced by a REF instruction ELECTRONICS 5 75 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 Reference Instruction REF Continued Examples 1 Instructions can be executed efficiently using REF as shown in the following example ORG 0020H LD HL 00H LD EA FFH TCALL SUB1 DDD SUB2 ORG 0080H REF AAA LD HL 00H REF BBB LD EA FFH REF CCC CALL SUB1 REF DDD JP SUB2 2 The following example shows how the REF instruction is executed in relation to LD instructions that have a redundancy effect ORG 0020H LD EA 40H ORG 0100H LD EA 30H REF AAA Not skipped REF AAA LD EA 50H Skipped SRB 2 5 76 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET R EF Reference Instruction REF Concluded Examples 3 In this example the binary code of REF 1 at locations 20 21 is 20H for REF A2 at locations 22H 23H it is 21H and for REF at
223. to 5 5 V Vop 18V to 55V 400 ns tkcy 2 50 1600 2 150 ae width SCK cycle time 2 7 V to 5 5 V Internal sck source _____ Internal sck source _____ source to 55V c SCK source Intemalscksouce Intemalscksouce source high low 5 5 V width SCK source Internal source 1 8 V to 5 5 V External source Internal source SI setup time to tSIK External source SCK high Internal sck source _____ Internal sck source _____ source 2 hold time to SCK 2 Internal sck source Internal sck source source 7 to 5 5 V 100 9 External source Output delay for Vpp 2 7 V to 5 5 V Internal sck source Internal sck source source SCK source Internal sck source Internal sck source source Interrupt input high low width INTO tINTL INT1 INT2 INT4 KSO KS7 RESET Input Low tRSL Input 10 us Width NOTES 1 Unless otherwise specified Instruction Cycle Time condition values assume a main system clock fx source 2 Minimum value for INTO is based a clock of 2t y 128 fx as assigned by the IMODO register setting ELECTRONICS 16 9 557 2308 2316 557 2308 2308 2316 2316 CPU Clock Main OSC Frequency 1 0475 MHz 1 00 MHz 750 kHz 500 kHz B IE IT T T T I 1 8 3 4 Supply Voltage V CPU CLOCK 1
224. toggled by checking the P2 0 value level BTSTZ P2 0 BITS P2 0 JP LABEL3 If P2 0 1 then P2 0 lt 0 and skip If P2 0 0 then P2 0 lt 1 2 For toggling port pins P2 2 P2 3 and P3 0 P3 3 LD L 0AH BP2 BTSTZ P1 L First 1 P2 2 1111008 10B 10B OF2H 2 BITS P1 L INCS L JR BP2 ELECTRONICS 5 41 SAM47 INSTRUCTION SET 557 2308 2308 2316 2316 BISTZ Bit Test and Skip on True Clear Bit BTSTZ Continued Examples 3 Bank 0 location 0A0H 0 is tested and EMB 0 FLAG EQU 0 BITR EMB LD H 0AH BTSTZ H FLAG If bank 0 AH 0 0A0H 0 1 clear and skip BITS H FLAG If OAOH O 0 then OAOH O lt 1 5 42 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET BXOR sit Exclusive BXOR C src b Exclusive OR carry with memory bit Description The specified bit of the source is logically XORed with the carry bit value The resultant bit is written to the carry flag The source value is unaffected Ee E mm ILS C C XOR memb 7 2 L 3 2 L 1 0 aa 2 C H DAb 1 1 1 1 0 1 1 1 DA 3 0 b bt bo 22 at a0 memab 1 0 bt bo a3 a2 at ao FBOH TBFH 1 1 bt bo a2 at ao FFOH FFFH Examples 1 The carry flag is logically XORed with the P1 0 value RCF Ce BXOR C P1
225. tomatically when counting starts 2 Enable Disable Timer Counter 0 Bit Disable timer counter 0 retain TCNTO contents Enable timer counter 0 1 0 Bit 1 0 Always logic zero 4 28 ELECTRONICS 557 2308 2308 2316 2316 MEMORY TOE Timer Output Enable Flag Register F92H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W Bit Addressing 3 Bit3 U Unknown TOEO Timer Counter 0 Output Enable Flag Disable timer counter 0 output the TCLOO Enable timer counter 0 output at the TCLOO pin 1 0 Bits 1 0 U Unknown N ELECTRONICS 4 MEMORY 557 2308 2308 2316 2316 WDFLAG Watchdog Timer Counter Clear Flag Register F9AH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W Bit Addressing 1 4 1 4 1 4 1 4 WDTCF Watchdog Timer Counter Clear Flag Clears the watchdog timer counter 2 0 Bits 2 0 0 Always logic zero NOTE After watchdog timer is cleared by writing 1 this bit is cleared to 0 automatically 4 30 ELECTRONICS 557 2308 2308 2316 2316 MEMORY WDMOD watchdog Timer Mode Register F99H F98H Bit 7 6 5 4 3 2 1 0 RESET Value 1 0 1 0 0 1 0 1 Read Write W W W W w Bit Addressing 8 8 8 8 8 8 8 8 WDMOD Watchdog Timer Enable Disable Control 5AH Disable watchdog timer function Enable watchdog timer function ELECTRONICS 4 31 MEMORY 557 2308 2308 2316 2316 WMOD
226. tor circuit 8 bit comparator Output latch TOLO Output enable TOEO Interrupt request flag IRQTO Interrupt enable flag IETO 11 10 557 2308 2308 2316 2316 Activates the timer counter and selects the internal clock frequency or the external clock source at the TCLO pin Stores the reference value for the desired number of clock pulses between interrupt requests Counts internal or external clock pulses based on the bit settings in TMODO and TREFO Together with the mode register lets you select one of four internal clock frequencies or an external clock Determines when to generate an interrupt by comparing the current value of the counter register TCNTO with the reference value previously programmed into the reference register TREFO Where a clock pulse is stored pending output to the serial I O circuit or to the TCO output pin TCLOO When the contents of the TCNTO and TREFO registers coincide the timer counter interrupt request flag IRQTO is set to 1 the status of TOLO is inverted and an interrupt is generated Must be set to logic one before the contents of the TOLO latch can be output to TCLOO Cleared when TCO operation starts and the TCO interrupt service routine is executed and set to 1 whenever the counter value and reference value coincide Must be set to logic one before the interrupt requests generated by timer counter 0 can be processed ELECTRONICS
227. trol Register CPU Bit 3 2 1 0 RESET 0 0 Read Write Bit Addressing 4 4 4 CLMOD 3 Enable Disable Clock Output Control Bit 0 Disable ____ Enable cookout f CLMOD 2 Bit 2 o zero __ CLMOD 1 0 Clock Source and Frequency Selection Control B n o 1 Select system clock 524 kHz at 419 MHz IP UNT EE ERR 1 Select system clock 55 krz afas f R Read only Bit value immediately Bit number in W Write only following a RESET MSB to LSB order R W Read write Type of addressing Description of the Bit identifier used that must be used to effect of specific for bit addressing address the bit bit 1 bit 4 bit or 8 bit Figure 4 1 Register Description Format ELECTRONICS 4 5 MEMORY 557 2308 2308 2316 2316 BMOD Basic Timer Mode Register F85H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W Bit Addressing 1 4 4 4 4 3 Basic Timer Restart Bit Restart basic timer then clear flag BCNT BMOD 3 to logic zero 2 0 Input Clock Frequency and Signal Interrupt Interval Time Control Bits Input clock frequency fxx 212 1 02 kHz Interrupt interval time wait time 220 fxx 250 ms 1 1 Input clock frequency fxx 29 8 18 kHz Interrupt interval time wait time 217 fxx 31 3 ms 1 1 Input clock frequency 27 32 7 kHz Interrupt interval tim
228. tting is always contained in the upper four bits of a 12 bit RAM address For this reason both addressing modes EMB 0 and EMB 1 apply specifically to the memory bank indicated by the SMB instruction and any restrictions to the addressable area within banks 0 1 or 15 Direct and indirect 1 bit 4 bit and 8 bit addressing methods can be used Several RAM locations are addressable at all times regardless of the current EMB flag setting Here are a few guidelines to keep in mind regarding data memory addressing When you address peripheral hardware locations in bank 15 the mnemonic for the memory mapped hardware component can be used as the operand in place of the actual address location Always use an even numbered RAM address as the operand in 8 bit direct and indirect addressing With direct addressing use the RAM address as the instruction operand with indirect addressing the instruction specifies a register which contains the operand s address ELECTRONICS 3 1 ADDRESSING MODES 557 2308 2308 2316 2316 Addressing DA HL DA b H DA b Working Registers General Registers and Stack BANK 1 General Registers BANK 1 Display Registers BANK 15 Peripheral Hardware Registers NOTES 1 X means don t care 2 Blank columns indicate RAM areas that are not addressable given the addressing method and enable memory bank EMB flag setting shown in the column headers Figure 3 1 RA
229. ty 1 2 bias 1 3 duty 1 2 or 1 3 bias 1 4 duty 1 3 bias 8 Bit Basic Timer Programmable interval timer Watchdog timer 8 Bit Timer Counter 0 Programmable 8 bit timer External event counter Arbitrary clock frequency output Serial I O interface clock generator Watch Timer Real time and interval time measurement Four frequency outputs to BUZ pin Clock source generation for LCD 8 Bit Serial Interface 8 bit transmit receive mode 8 bit receive only mode LSB first or MSB first transmission selectable or external clock source 1 2 557 2308 2308 2316 2316 Bit Sequential Carrier Support 16 bit serial data transfer in arbitrary format Interrupts Three internal vectored interrupts Three external vectored interrupts Two quasi interrupts Memory Mapped I O Structure Data memory bank 15 Two Power Down Modes 1 mode only CPU clock stops Stop mode main or sub system oscillation stops Oscillation Sources Crystal ceramic or RC for main system clock Crystal or external oscillator for subsystem clock Main system clock frequency 4 19 MHz typical Subsystem clock frequency 32 768 kHz CPU clock divider circuit by 4 8 or 64 Instruction Execution Times 0 95 1 91 15 3 us at 4 19 MHz main 122 us at 32 768 kHz subsystem Operating Temperature 40 85 C
230. u can use the basic timer as a watchdog timer for monitoring system events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and following RESET Bit settings in the basic timer mode register BMOD turns the BT on and off selects the input clock frequency and controls interrupt or stabilization intervals Interval Timer Function The measurement of elapsed time intervals is the basic timer s primary function The standard interval is 256 BT clock pulses To restart the basic timer set bit 3 of the mode register BMOD to logic one The input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD 2 BMOD 0 The 8 bit counter register BCNT is incremented each time a clock signal is detected that corresponds to the frequency selected by BMOD BCNT continues incrementing as it counts BT clocks until an overflow occurs An overflow causes the BT interrupt request flag IRQB to be set to logic one to signal that the designated time interval has elapsed An interrupt request is then generated BCNT is cleared to logic zero and counting continues from OOH Oscillation Stabilization Interval Control Bits 2 0 of the BMOD register are used to select the input clock frequency for the basic timer This setting also determines the time interval also referred to as wait time required to stabilize clock signal oscillation when power down mode is r
231. unit of time that equals one machine cycle varies depending on whether the main system clock fx or a subsystem clock fxt is used and on how the oscillator clock signal is divided by 4 8 or 64 Table 6 2 shows corresponding cycle times in microseconds Table 6 2 Instruction Cycle Times for CPU Clock Rates Oscillation Selected Resulting Cycle Time ps Source CPU Clock Frequency fx 4 19 MHz fx 64 65 5 kHz IT 3 19 kHz 1220 6 6 ELECTRONICS 557 2308 2308 2316 2316 OSCILLATOR CIRCUITS SYSTEM CLOCK MODE REGISTER SCMOD The system clock mode register SCMOD is a 4 bit register that is used to select the CPU clock and to control main and sub system clock oscillation SCMOD is mapped to the RAM address FB7H When main system clock is used as clock source main system clock oscillation can be stopped by STOP instruction or setting SCMOD 3 not recommended When the clock source is subsystem clock main system clock oscillation is stopped by setting SCMOD 3 SCMOD 0 SCMOD2 and SCMOD 3 cannot be simultaneously modified Sub oscillation goes into stop mode only by SCMOD 2 PCON which revokes stop mode cannot stop the sub oscillation The stop of sub oscillation is released only by reset RESET clears all SCMOD values to logic zero selecting the main system clock fx as the CPU clock and starting clock oscillation The reset value of the SCMOD is 0 SCMOD 3 SCMOD 2 and SCMOD 0 bits can be manipulated by 1 bit w
232. vels permitted in the stack Interrupt Routines An interrupt routine references the SP to push the contents of the PC and the program status word PSW to the stack Six 4 bit stack locations are used to store this data After the interrupt has executed the SP is decreased by six and points to the next available stack location During an interrupt Sequence subroutines may be nested up to the number of levels which are permitted in the stack area INTERRUP PUSH CALL When INT is acknowledged After PUSH SP SP 2 After CALL SP lt SP 6 PC7 4 NOTE PC13 is used for KS57C2316 P2316 microcontroller Figure 2 7 Push Type Stack Operations ELECTRONICS 2 13 ADDRESS SPACES 557 2308 2308 2316 2316 OPERATIONS For each push operation there is corresponding pop operation to write data from stack back to the source register or registers for the PUSH instruction it is the POP instruction for CALL the instruction RET or SRET for interrupts the instruction IRET When a pop operation occurs the SP is incremented by a number determined by the type of operation and points to the next free stack location POP Instructions A POP instruction references the SP to write data stored in two 4 bit stack locations back to the register pairs and SB register The value of the lower 4 bit register is popped first followed by the value of the upper 4 bit register After the POP has ex
233. ware assignable 4 bit I O ports Port 6 pins are individually KSO KS3 software configurable as input or output 1 bit KS4 KS7 and 4 bit read write and test are possible 4 bit pull up resistors are software assignable Ports 6 and 7 can be paired to enable 8 bit data transfer Output port for 1 bit data for use as CMOS Output driver only LCD segment signal output Output LCD segment signal output Output P8 0 P8 7 SEGO SEG23 SEG24 SEG31 COMO COMS Vi co Vice LCD power supply Voltage dividing resistors 9 11 are assignable by mask option BIAS LCD power control LCDCK LCD clock output for display expansion a ELECTRONICS 1 5 LCD common signal output Output r z z z ied S m PRODUCT OVERVIEW 557 2308 2308 2316 2316 Table 1 1 557 2308 2316 Pin Descriptions Continued Pin Description Reset Circuit Type Value Type LCDSY LCD synchronization clock output for LCD 33 P3 1 Input display expansion TCLO External clock input for timer counter 0 sO vo Serial interace data oupa __________2 p sx VO Serial VO imerace cock signal a Pos D INTO External interrupts The triggering edge for 24 P1 0 Input A 1 INTO and is selectable Only INTO is 25 P1 1 synchronized with the system clock INT2 Quasi interrupt with detection of rising edge 26 P1 2 Input A 1 signals INT4 External interrupt input with detecti
234. x Operation Notation _ r RR lt SP RRH lt SP 1 SP 2 SRB SMB lt SP 1 SP 2 E Table 5 18 Logic Instructions Binary Code Summary oporana Binary Code Operation Notation er SEE cs x3 lt EA AND RR Se emm 07 1 1 Soe 1 1 10 1 0 2 RRb RRb OR EA ala EN EN juvet A XOR im 11 DE EN EN 1 JAcAXORHD ______ piene m 07 rior emm 7 ERBEHIT _ 07 5 18 ELECTRONICS 557 2308 2308 2316 2316 SAM47 INSTRUCTION SET Table 5 19 Arithmetic Instructions Binary Code Summary _ Mpp EARR 11 1 11 lt E C RRb EA pipe yet lt RRb EBEZESESES 1 1 lt EA imm skip on carry 5 xeu EA RR EA E E skip on carry me COH R
235. zzer and LCD display operate normally with a subsystem clock source since they operate at very slow speeds 122 us at 32 768 kHz and with very low power consumption 6 2 ELECTRONICS 557 2308 2308 2316 2316 Main System Oscillator Circuit Oscillator Stop SCMOD 2 fx Main system clock fxt Sub system clock fxx System clock ELECTRONICS Stop 1 8 1 4096 Frequency Dividing Circuit 1 2 3 2 clear Figure 6 1 Clock Circuit Diagram 1 16 fx 1 2 161 Y Y OSCILLATOR CIRCUITS Watch Timer Sub System LCD Controller Oscillator Circuit Basic Timer Timer Counter Watch Timer LCD Controller Clock Output Circuit SIO CPU clock CPU stop signal By IDLE or STOP instruction a Wait release signal Oscillator Control Circuit 4 Internal RESET signal lt lt Power down release 6 3 OSCILLATOR CIRCUITS 557 2308 2308 2316 2316 MAIN SYSTEM OSCILLATOR CIRCUITS SUBSYSTEM OSCILLATOR CIRCUITS XIN XOUT 32 768 kHz Figure 6 2 Crystal Ceramic Oscillator Figure 6 5 Crystal Ceramic Oscillator External Clock Figure 6 3 External Oscillator Figure 6 6 External Oscillator XIN R Figure 6 4 RC Oscillator 6 4 ELECTRONICS 557 2308 2308 2316 2316 OSCILLATOR CIRCUITS POWER CONTROL REGISTER PCON The power control register PCON is a 4 bit register that is used to sele

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