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Samsung FLEX-MUXONENAND KFN8GH6Q4M User's Manual

Contents

1. ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Pairing of pages in MLC block XX Represents a Page number XX in an MLC block gt Represents Pairing of pages in an MLC block FLASH MEMORY 78 7A 7B v ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Program Operation Flow Diagram p Start i Write 0 to interrupt register zi Add F241h DQ 0000h I IMMA p Select DataRAM for DDP 2 Add F101h DQ DBS Write Program Command Add F220h Y DQ 0080h _ Write Data into DataRAM ADD DataRAM DQ Data 4KB Wait for INT register m Xo _ low to high transition p Data Input __ NO Add F241h DQ 15 INT Ec Completed YES Read Controller Status Register Write DFS FBA of Flash sf RA ASE T Add F100h DQ DFS FBA P Add F240h DQ 1 0 Read Write Protection Status i 10 0 _ Add F24Eh DQ US LS LTS M 4 YES Write FSA of Flash
2. NI NI peseq si pue ndu e qejie e Yous YouAsy 2 s L smeis JIQ Aq peieorpu smeis wo1 sng snieis SJAVHEJEG 40 JOJBOIPUI LNI JAVHEJEG JO SseJppy ev ZY LY L JIB4 O SSBq snoieJud L JIB4 O ssed snolA id 01 pijeAuj snoi eud L JIB4 O SSEd jueuno PIJEAU jueJano 0 0 pienu JSUQ 1ejsiDes SNJEJS 1 llonuoo JSUQ 19 SIHOH SNJEJS 1 llonuoo 99u2 2 51 snjejs puewwog uieJ6oJd N iis INI v v snjejs SINVHEIEG SINVHEIEG ejep ejep amp jep indui puz indui jndul ISL sLoav Z UBIH 00dV ELECTRONICS Bunjes sseJppy FLASH MEMORY iming See AC Characteristics Table 5 7 and Table 5 9 Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx 6 13 Interleave Cache Program Operation T Zdiyo uo sanssi JSOU 91094 Apeas SUN JO 4 1 NI USUM 9 6
3. 2 RP 222 2 2 2 2 2 222 222 INT igi E343 s IOBE bit s NOTE 1 Bootcode copy operation starts 400us later than POR activation The system power should reach Vcc after POR triggering level typ 1 5V within 400us for valid boot code data 2 1KB Bootcode copy and internal update operation take 250us estimated from sectorO and 1 pageO blockO of Flash array to BootRAM Host can read Bootcode in BootRAM 1K bytes after Bootcode copy completion 3 INT register goes Low to High on the condition of Bootcode copy done and RP rising edge If RP goes Low to High before Bootcode copy done INT register goes to Low to High as soon as Bootcode copy done ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 6 16 Warm Reset Timing See AC Characteristics Table 5 6 CE OE X RP tRP lt tReady1 RDY High Z High Z tReady2 INT bit Operation 1 2 3 1 Status C Idle X Reset Ongoing X BootRAM Access nr Bit Polling Idle NOTE 1 The status which can accept any register based operation Load Program Erase command etc 2 The status where reset is ongoing 3 The status allows only BootRAM BL 1 read operation for Boot Sequence Refer to 7 2 2 Boot Sequence 4 To read BL2 of Boot Sequence Host should wait INT until
4. 1012 1013 03F5h Block1014 03F6h Block1015 03F7h Block1016 03F8h Block1017 03F9h Block1018 1019 1020 1021 O3FDh Block1022 1023 29 O3FFh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 7 2 Internal Memory Spare Area Assignment The figure below shows the assignment of the spare area in the Internal Memory NAND Array Main Main Main Main Main Main Main Main Spare Spare Spare area area area area area area area area area area area area area area area area 256W 256w 256w 256W 256w 256W 256W 256W w aw aW ew ew sw ew lt gt lt p lt gt lt gt lt gt lt gt lt gt lt gt lt gt Note1 Note1 Note2 Note2 Note2 Note2 Note3 Note3 Note3 Note3 Note3 Note3 Note3 Note3 Note3 Note3 LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB ee 18 2 W 4 W 5 W enw 8 w
5. When INT bit goes to 1 after second data transfer from DataRAMs to Page Buffers are complete user may check the Status Register to check the Cache program status During Cache Program previous bit shows the status of previous program operation For the final 4KB program of Interleave Cache Program scheme host should issue Program Command 0080h on each chip If host issues 0080h on only a chip another chip will be on operation as it is not finished Ongo status bit will show the ongoing status of each chip Its oper ation is same as Cache Program operation on each chip Error bit will show the pass fail status of each chip of Interleave Cache program and previous current bit will show where the error occurred accordingly Note that OTP block and 1st block OTP cannot be Interleave Cache Programmed Interleave Cache Program operation must be utilized within a same area partitioned as SLC or MLC 1 Data Write Issue Program Command Page A 3 Check for INT bit 1 then Data write Page B Page A Sector Sector 3 Program Page Buffer 4 KB Page B ad DataRAM1 2 Copy to Page Buffer 4KB 2 Data Write Issue Program Command Page A 4 Check for bit 1 then Data write Page B Page A Sector Sector lt DataRAMO 4 Program Page Buffer A 4 KB Page
6. Block571 023Bh Block572 023Ch Block573 023Dh Block574 023Eh Block575 29 023Fh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block576 0240h Block577 0241h Block578 0242h Block579 0243h Block580 0244h Block581 0245h Block582 0246h Block583 0247h Block584 0248h Block585 0249h Block586 024Ah Block587 024Bh Block588 024Ch Block589 024Dh Block590 024Eh Block591 024Fh Block592 0250h Block593 0251h Block594 0252h Block595 0253h Block596 0254h Block597 0255h Block598 0256h Block599 0257h Block600 0258h Block601 0259h Block602 025Ah Block603 025Bh Block604 025Ch Block605 025Dh Block606 025Eh Block607 025Fh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block608 0260h Block609 0261h Block610 0262h Block611 0263h Block612 0264h Block613 0265h Block614 0266h Block615 0267h Block616 0268h Block617
7. Block667 029Bh Block668 029Ch Block669 029Dh Block670 029Eh Block671 029Fh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block672 02A0h Block673 02A1h Block674 02A2h Block675 02A3h Block676 02A4h Block677 02A5h Block678 02A6h Block679 O2A7h Block680 02A8h Block681 02A9h Block682 02AAh Block683 02ABh Block684 02ACh Block685 02ADh Block686 2 Block687 02AFh Block688 02BOh Block689 02B1h Block690 02B2h Block691 02B3h Block692 02B4h Block693 02B5h Block694 02B6h Block695 02B7h Block696 02B8h Block697 02B9h Block698 02BAh Block699 02 Block700 02BCh Block701 02BDh Block702 02 Block703 24 02BFh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block704 02COh Block705 02C1h Block706 02C2h Block707 02C3h Block708 02C4h Block709 02C5h Block710 02C6h Block711 02C7h Block712 02C8h
8. MLC are stored After shipment it is initially programmed as data FCOOh Lock bit 15 14 11b binary Boundary address 9 0 000h To change PI Block contents i e lock bits and boundary address Erase Program sequence should be followed as below PI Block Boundary Information setting steps e Enter PI Block access mode Refer to Chapter 3 12 1 1 e Issue PI Block erase Refer to Chapter 3 12 1 2 e Issue program Refer to Chapter 3 12 1 3 Exit Block Access mode amp Update new Partition Information PI block Access mode exit can be done through a Warm Cold Hot NAND Flash Reset However Update can only be done by two methods Update Command and Cold Reset The following flow chart shows two methods for updating the and exiting Pl access mode PI Block Boundary Information setting Flow Chart Start Y PI Block Access mode entry Y PI Block Erase2 Y PI Program Lock bit Boundary of Address Y Block Update Y Cold Reset Warm Hot NAND Flash Reset Block Access Mode exit Y PI Update done NOTE 1 1 2 Refer to Chapter 3 12 1 2 3 Refer to Chapter 3 12 1 3 4 Refer to Chapter 3 12 1 4 NN ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 12 1 1 Block Access mode entry The
9. Read Controller status register Add F240h DQ 10 Error utor _____ Fail DQ iogJo YES Program Pass Program completed Program Error DBS DFS is for DDP nw YES Program Pass DQ 10 0 NO Program Fail Y d Program Interleave can work in Auto INT Mode Interrupt register must not be written 2 Previous Program Status Check DBS must be changed to indicate chip Program has been issued prior to current program ongoing 3 Final Program Status Check 1 Check the chip status before command issues NOTE 1 DBS must be set before data input 2 FSA must be 00 and BSC must be 000 within program operation 3 BSA must be 1000 and BSC must be 000 76 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 9 1 Cache Program Operation See Timing Diagram 6 12 The Cache Program is to enhance the performance of Program Operation Employing Cache Program operation transfer time from Host to DataRAM can be shadowed therefore write performance will increase In Cache Program since 4KB data is to be programmed into NAND Flash Array in another advanced way 1 4KB Data write from host to DataRAMs 2 Cache Program command issue This will turn INT pin to busy state OnGo bit sets to
10. Block219 OODBh Block220 00DCh Block221 00DDh Block222 OODEh Block223 OODFh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block224 OOEOh Block225 00 1 226 OOE2h Block227 00 228 00E4h Block229 00E5h Block230 00E6h Block231 00E7h Block232 00E8h Block233 00E9h Block234 OOEAh Block235 OOEBh Block236 Block237 OOEDh Block238 OOEEh Block239 OOEFh Block240 OOFOh Block241 OOF 1h Block242 OOF 2h Block243 OOF 3h Block244 245 OOF5h Block246 OOF6h Block247 OOF7h Block248 OOF8h Block249 OOF9h Block250 OOFAh Block251 OOFBh Block252 OOFCh Block253 OOFDh Block254 OOFEh Block255 17 OOFFh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block256 0100h Block257 0101h Block258 0102h Block259 0103h Block260 0104h Block261 0105h Block262 0106h Block263 0107h B
11. SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block128 0080h Block129 0081h Block130 0082h Block131 0083h Block132 0084h Block133 0085h Block134 0086h Block135 0087h Block136 0088h Block137 0089h Block138 008Ah Block139 008Bh Block140 008Ch Block141 008Dh Block142 008 143 008Fh Block144 0090h Block145 0091h Block146 0092h Block147 0093h Block148 0094h Block149 0095h Block150 0096h Block151 0097h Block152 0098h Block153 0099h Block154 009Ah Block155 009Bh Block156 009Ch Block157 009Dh Block158 159 009Fh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block160 Block161 00 1 162 00A2h Block163 Block164 00 4 165 00A5h Block166 00A6h Block167 7 Block168 00A8h Block169 00A9h Block170 00AAh Block171 OOABh Block172 00ACh Block1
12. BRWL 4 e meg sete Ese lt CE tcER tt kK tcez CLK A 1 ove AVD tavDO ll p tBDH gt tAVDH tACS AIDQ15 Da Dara Dave Was ss toEz gt lt gt ll gt 1RDY Hi Z tRDYA Hi Z RDY x 115 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 6 3 Asynchronous Read VA Transition Before AVD Low See AC Characteristics Table 5 5 A DQO AIDQ15 AVD RDV NOTE VA Valid Read Address RD Read Data See timing diagram 6 20 6 21 for tASO A DQO AIDQ15 AVD Valid RD Hi Z tAAVDS He tWEA Hi Z Hi Z 6 4 Asvnchronous Read VA Transition After AVD Low See AC Characteristics Table 5 5 tRC X tcER lt toE lt gt tcEz lt tca toEz vA X Valid RD gt gt lt tace tAAVDS tAAVDH tWEA N y gt lt tAVDP Hi Z Hi Z RDY NOTE VA Valid Read Address RD Read Data See timing diagram 6 21 6 22 for tASO ELECTRONICS 116 Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex M
13. 0269h Block618 026Ah Block619 026Bh Block620 026Ch Block621 026Dh Block622 026Eh Block623 026Fh Block624 0270h Block625 0271h Block626 0272h Block627 0273h Block628 0274h Block629 0275h Block630 0276h Block631 0277h Block632 0278h Block633 0279h Block634 027Ah Block635 027Bh Block636 027Ch Block637 027Dh Block638 027Eh Block639 2 027Fh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block640 0280h Block641 0281h Block642 0282h Block643 0283h Block644 0284h Block645 0285h Block646 0286h Block647 0287h Block648 0288h Block649 0289h Block650 028Ah Block651 028Bh Block652 028Ch Block653 028Dh Block654 028Eh Block655 028Fh Block656 0290h Block657 0291h Block658 0292h Block659 0293h Block660 0294h Block661 0295h Block662 0296h Block663 0297h Block664 0298h Block665 0299h Block666 029Ah
14. Cache Program this bit will stay as Fail status until the end of Cache Program Error Information 10 Load Program Cache Program and Erase Result Pass Fail PI Lock Status Pl This bit shows whether the PI block is locked or unlocked Locking the has the effect of Program Erase protect to guard against accidental re programming of data stored in the PI block The PI status bit is automatically updated at power on and PI update operation by Update command ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY OTP Lock Status OTP This bit shows whether the OTP block is locked or unlocked Locking the OTP has the effect of a write protect to guard against accidental re programming of data stored in the OTP block The OTP status bit is automatically updated at power on OTP Lock Information 6 OTP Locked Unlocked Status OTP Block Unlock Status Default OTP Block Lock Status Disable OTP Program Erase 1st Block OTP Lock Status OTP This bit shows whether the 1st Block OTP is locked or unlocked Locking the 1st Block OTP has the effect of a Program Erase protect to guard against accidental re programming of data stored in the 1st block The OTP status bit is automatically updated at power on OTP Lock Information 5 1st Block OTP Locked Unlocked Status 1st Block OTP Unlock S
15. Spare Area Assignment in the Internal Memory NAND Array Information Description Invalid Block information in 1st and 2nd page of an invalid block Managed by internal ECC logic for Logical Sector Number area 4bit ECC parity values ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 7 3 External Memory BufferRAM Address Map The following table shows the External Memory address map in Word and Byte Order Note that the data output is unknown while host reads a register bit of reserved area and dual buffering is not applicable Division Address word order Address byte order Size total 128KB Usage Description Main area 64KB 0000h 00FFh 00000h 001FEh 512B 1KB 0100h 01FFh 00200h 003FEh 512B BootM 0 BootRAM Main block0 page0 sector0 BootM 1 BootRAM Main blockO pageO sectori 0200h 02FFh 00400h 005FEh 512B 0300h 03FFh 00600h 007FEh 512B 0400h 04FFh 00800h 009FEh 512B 0500h 05FFh 00A00h 00BFEh 512B 0600h 06FFh 00C00h 00DFEh 512B 0700h 07FFh O00E00h 00FFEh 512B 0800h 08FFh 01000h 011FEh 512B 0900h 09FFh 01200h 013FEh 512B DataM 0 0 DataRAM Main nth page sectorO DataM 0 1 DataRAM Main nth page sector1 Da
16. The Read Identification Data command consists of two cycles It gives out the devices identification data according to the given address The first cycle is 0090h to the boot partition address and second cycle is read from the addresses specified in Identification Data Description Table Identification Data Description Address Data Out 0000h Manufacturer ID OOECh 0001h Device ID 0002h Current Block Write Protection Status NOTE 1 Refer to Device ID Register Chapter 2 8 3 2 To read the write protection status FBA has to be set before issuing this command ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 2 Device Bus Operation The device bus operations are shown in the table below Operation ADQO 15 Standbv High Z Warm Reset X High Z Add In Data In Add In Data Out Asynchronous Write Asynchronous Read Start Initial Burst Read Add In Burst Data Burst Read Out Terminate Burst Read oe High Z Terminate Burst Read Cycle via RP High Z Terminate Current Burst Read Cycle and Start Add In New Burst Read Cycle Start Initial Burst Write Add In Burst Write Data In Terminate Burst Write ee High Z Terminate Burst Write Cycle via RP High Z Terminate Current Burst Write Cycle and Start Add In New B
17. Version ID N A F003h 1E006h Data Buffer size Data buffer size F004h 1E008h Boot Buffer size Boot buffer size F005h 1E00Ah Amount of buffers Amount of data boot buffers FOO6h 1E00Ch Technology Info about technology F007h FOFFh 1EO00Eh 1E1FEh Reserved Reserved for user F100h 1E200h Start address 1 Chip address for selection of NAND Core in DDP amp Block address F101h 1E202h Start address 2 Chip address for selection of BufferRAM in DDP F102h F106h 1E204h 1E20Ch Reserved Reserved for user F107h 1E20Eh Start address 8 NAND Flash Page amp Sector Address F108h F1FFh 1E210h 1E3FEh Reserved Reserved for user F200h 1E400h Sector Count Sector Number for the page data transfer from the memory and the BufferRAM F201h F21Fh 1E402h 1E43Eh Reserved Reserved for vendor specific purposes F220h 1E440h Command Host control and memory operation commands F221h 1E442h System Configuration 1 memory and Host Interface Configuration F222h F22Fh 1E444h 1E45Eh Reserved Reserved for user F230h F23Fh 1E460h 1E47Eh Reserved Reserved for vendor specific purposes F240h 1E480h Controller Status Controller Status and result of memory operation F241h 1E482h Interrupt Memory Command Completion Interrupt Status F242h F24Bh
18. 0043h Block68 0044h Block69 0045h Block70 0046h Block71 0047h Block72 0048h Block73 0049h Block74 004Ah Block75 004Bh Block76 004Ch Block77 004Dh Block78 004Eh Block79 004Fh Block80 0050h Block81 0051h Block82 0052h Block83 0053h Block84 0054h Block85 0055h Block86 0056h Block87 0057h Block88 0058h Block89 0059h Block90 005Ah Block91 005Bh Block92 005Ch Block93 005Dh Block94 005Eh Block95 005Fh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block96 0060h Block97 0061h Block98 0062h Block99 0063h Block100 0064h Block101 0065h Block102 0066h Block103 0067h Block104 0068h Block105 0069h Block106 006Ah Block107 006Bh Block108 006Ch Block109 006Dh Block110 006 Block111 006Fh Block112 0070h Block113 0071h Block114 0072h Block115 0073h Block116 0074h Block117 0075h Block118 0076h Block119 0077h Block120 0078h Block121 0079h Block122 007Ah Block123 007Bh Block124 007Ch Block125 007Dh Block126 007Eh Block127 15 007Fh
19. AE Add FF02h DQ ERS 12 8 ER4 4 0 Write System Configuration Y Register Write FSA of Flash Read ECC Status Register4 2 4 Add F107h DQ FPA FSA xe E Add F221h Add FF03h DQ ER7 12 8 ER6 4 0 l SA Write 0 to INT register or NO _ Write 0 to INT register or PIN Add F241h DQ 0000h __ eee 77 Add F241h DQ 0000h Finished to load finalpage ___ v E p Write Superload Command ves arite Load command WT Add F220h DQ 0003h Add F220h DQ 0000n Host reads data from DataRAM 0 15 N N Host reads data from Wait for INT register or PIN DataRAM 0 19 ae S low to high transition Superload Completed Add F241h DQ 15 INT ku Wait for INT register or PIN high to low transition DBS DFS is for DDP Add F241h DQ 15 INT NOTE 1 FSA must be 00 and BSC must be 000 always for Superload operation 2 BSA must be 1000 3 In case of Superload operation the number of sectors to be loaded is 8 sectors 4 Write 0 to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 5 6 For the first load hosts must issue Load 0000h command In case of Superload operation only synchronous read mode is valid Host should read data out until end of DataRAM 804FH After Reading out the last data Add 804F Additional clock should not be asserted
20. Add F101h DQ DBS Y Read Write Protection Status Add F24Eh DQ US LS LTS v Write 0 to interrupt register Add F241h DQ 0000h Write Erase Command Add F220h DQ 0094h Wait for register low to high transition Add F241h DQ 15 INT Read Controller Status Register Add F240h DQ 10 Error DQ tojo YES NO Erase completed N _ DBS DFS is for DDP If erase operation results an error map out the failing block and replace it with another block 4 N NOTE 1 Write 0 to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 In order to perform the Internal Erase Routine the following command sequence is necessary e The Host selects Flash Core of DDP chip e The Host sets the block address of the memory location e The Erase Command initiates the Internal Erase Routine During the execution of the Routine the host is not required to provide further controls or timings During the Internal erase routine all commands except the Reset command and Erase Suspend Command written to the device will be ignored A reset or power off during an erase operation will cause data corruption at the corresponding location Block ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND1
21. ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 6 2 LSB Page Recovery Read MLC NAND Flash cell has paired pages LSB page and MSB page LSB page has lower page address and MSB page has higher page address in paired pages If power off occurs during MSB page program the paired LSB page data can become corrupt LSB page recovery read is a way to read LSB page though page data are corrupted When uncorrectable error occurrs as a result of LSB page read after power up issue LSB page recovery read Its command is 0005h Flow chart below shows LSB page read sequence LSB Page Recovery read flow chart Start d Y DQ 10 0 Write DFS FBA of Flash Boc 90 Add F100h DQ DFS YES Read ECC Status Register1 Bo 7 Select DataRAM for DDP Add FF00h DQ ER1 12 8 ERO 4 0 Add F100h DQ DFS Write DFS FBA of Flash v Select DataRAM for DDP Add F101h DQ DBS Add F101h DQ DBS Write FPA FSA of Flash Add F107h DQ FPA FSA Y Write BSA BSC of DataRAM L Write System Configuration Register Add F221h DQ ECC Y Write 0 to INT register2 Add F241h DQ 0000h Y Write Load Command Add F220h DQ 0000h Wait for INT register low to high transition
22. F101h DQ O000h D8S Write BSA BSC of DataRAM Add F200h DQ 0800n9 Write 0 to interrupt register A M Add F241h DQ 0000h Write 0 to interrupt register Add F241h DQ 0000h CN e Write OTP Access Command Y 77 Add F220h DQs0065h Write Program command Add F220h 7 7 DQ 0080h Wait for INT register low to high transition Add F241h DQ 15 INT Wait for INT register low to high transition Add F241h DQ 15 INT Write Data into DataRAM Add 1stWord sector4 of main the page49 Do Cold reset DQ XXF3h Locking bit Automatically updated Update Controller Status Register Add F240h DQ 5 1 OTPBL a N 151 Block OTP lock completed DBS DFS is for DDP NOTE 1 FBA NAND Flash Block Address could be omitted or any address 2 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 3 Data input could be done anywhere between Start and Write Program Command FBA must be 0000 FSA must be 00 within program operation The 0196h is the page49 of NAND Flash Array address map 4 5 6 BSA must be 1000 and BSC must be 000 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 13 5 OTP and 1st Block OTP Lock Operation OTP and 1st Block can b
23. area is a separate part of the Flash Array memory It is accessed by issuing Access command 66h instead of writing a Flash Block Address FBA in the StartAddress1 register After being accessed through the Access Command the contents memory area can be programmed erased or loaded using the same operations as a normal program erase or load operation to the NAND Flash Array memory PI Block Access mode entry Flow Chart Start Y Write DFS of Flash Add F100h DQ DFS FBA v Select DataRAM for DDP Add F101h DQ DBS Write 0 to interrupt register Add F241h DQ 0000h Y Write Access Command Add F220h DQ 0066h Y Wait for INT register low to high transition Add F241h DQ 15 INT 7 PI Block Access mode entry completed DBS DFS is for DDP NOTE 1 FBA NAND Flash Block Address could be omitted or any address 2 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 12 1 2 Block Erase The Block Erase Operation erases the entire block including Partition Information Block Access mode entry must be done before issuing Erase operation for PI Block Erasing the PI Area e Issue
24. 1 Note that before issuing Cache Program Command host should make sure that the target blocks are unlocked 3 4KB data will be sequentially transferred to a page buffer in NAND Flash Array 4 When this transfer operation is complete programming into NAND Flash Array will automatically start and at the same time INT bit will turn to 1 to indicate that DataRAMs are now ready to be written with next 4KB data 5 When second 4KB is written to two DataRAMs another Cache Program command is issued and INT bit will go to 0 If host wants to program data less than 8 sectors unwanted area to be programmed must written to all 175 When INT bit goes to 1 after second data transfer from DataRAMs to Page Buffers are complete user may check the Status Register to check the Cache program status During Cache Program Error bit shows the status of previous program operation For the final 4KB program of Cache Program scheme host should issue Program Command 0080h And when the final page is programmed INT bit will turn to 1 and OnGo status bit which indicates the overall Cache Program ongoing status will go to 0 At the completion of Cache Program operation Error bit will show the pass fail status overall status of program and previous current bit will show where the error occurred accordingly Refer to the below diagram Note that Cache Program command cannot be performed on OTP block and 1st block OTP Cache
25. 801Ch 10038h 801Dh 1003Ah Abit ECC parity values 801Eh 1003Ch 801Fh 1003Eh Managed by internal ECC logic Managed by internal ECC logic Managed by internal ECC logic Managed by internal ECC logic ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Word Byte Dur Address Address DataS 0 2 8020h 10040h BI Bad block Information 8021h 10042h 8022h 10044h 8023h 10046h 8024h 10048h 8025h 1004Ah 4bit ECC parity values 8026h 1004Ch 8027h 1004Eh DataS 0 3 8028h 10050h BI Bad block Information 8029h 10052h 802Ah 10054h 802Bh 10056h 802Ch 10058h 802Dh 1005Ah 4bit ECC parity values 802Eh 1005Ch 802Fh 1005Eh DataS 1_0 8030h 10060h BI Bad block Information 8031h 10062h 8032h 10064h 8033h 10066h 8034h 10068h 8035h 1006Ah 4bit ECC parity values 8036h 1006Ch 8037h 1006Eh DataS 1 1 8038h 10070h BI Bad block Information 8039h 10072h 803Ah 10074h 803Bh 10076h 803Ch 10078h 803Dh 1007Ah 4bit ECC parity values 803Eh 1007Ch 803Fh 1007Eh DataS 1 2 8040h 10080h BI Bad block Information 8041h 10082h 8042h 10084h 8043h 10086h 8044h 10088h 8045h 1008Ah 4bit ECC parity values 8046h 1008Ch 8047h 1008Eh Managed by internal ECC logic Managed by internal ECC logic Managed by int
26. Access Mode happens after during an Erase Suspend Operation the erase routine could fail Therefore to exit from the Access Mode without causing the erase operation to fail Flash Core Reset command should be issued PI Block Page Allocation Information This is located at the 1st word of sectorO of pageO of main area the Block The allocated word in 1st page is programed with data FCOOh initially after shipment whole block is set as MLC except Block 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lock Reserved 1111 Boundary Address end of SLC area PI Lock bits and Boundary Address PI Block can be locked only by programming lock bits into 15 14 of the 1st word of sector0 pageO of the main memory area of PI The first block is a SLC block The MLC block will be defined from the next block of the block designated by boundary address programmed into 9 0 of the 1st word of sector0 pageO of the main memory area of SLC area Default SLC area Boundary Y BlockN Address BlockN 1 1023 NAND Flash Array ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 12 1 Block Boundary Information setting It is 1st word sectorO of pageO of main area of Block The Lock bits for Block and Boundary address of SLC
27. DataRAM1 3 Copy to Page Buffer 4KB NOTE 2 and 2 are concurrent 3 3 and 3 are concurrent 4 and 4 are concurrent ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Interleave Cache Program Operation Flow Diagram Start l go 3 Y i 1 i 1 Select a chip for DDP Select a chip for DDP M id dix oec qe e ee as Select DataRAM for DDP Add 100 DQ DFS Add F100h DQ DFS Add F101h DQ DBS Add F101h DQ DBS Add F101h DQ DBS l Write Data into DataRAMO 1 Check INT register Add DataRAM DQ Data 4KB if itis ready VENE t Add F101h DOQ DBS Add F241h DQ 8040h Add F241h DQ 8040h Y U Y ite d Check INT register l 1 DQ DES FRA I Read Controller d 2 if it is ready tatus Register _ _ _ AMS Register Satus Me ne Add F241h DQ 8040h Y Add F240h Add F240h Read Write Protection Status 27055 Add F24Eh DQ US LS LTS l Read Controller ou sss ___ Status Register Y DQ 4 DQ 2 20 Add F240h DQ 10 Error Write FPA FSA of
28. For host frequency over 66MHz BRWL should be 6 or 7 while HF is 1 For host frequency range 40MHz 66MHz BRWL should be set to 4 7 while is 0 For host frequency under 40MHz BRWL should be set to 3 7 while HF is 0 Burst Read Write Latency BRWL Information 14 12 Definition Description Burst Read Latency Specifies the access latency in the burst Burst Write Latency read write transfer for the initial access ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Burst Length BL Host must follow burst length set by BL when reading data in synchronous burst read Burst Length Main Burst Length Spare Continuous Default 4 words 8 words 16 words 32 words Reserved NOTE 1 In case of BootRAM Main 512word Spare 16word In case of DataRAM Main 1Kword Spare 32word Burst Length BL Information 11 9 Definition Description Specifies the size of the burst length during a synchronous Burst Length linear burst read and wrap around And also burst length during a synchronous linear burst write Error Correction Code ECC Information 8 Item Definition Description 0 with correction default ECC Error Correction Code Operation 1 without correction bypassed RDY Polarity RDYpol Information 7 Definition Description 1 high for ready default RDY
29. Program completed Program Error Add F200h DQ 0800n 9 y Write System Configuration Register Add F221h DQ ECC If program operation results an error map out the block including the page in error and copy the DBS DFS is for DDP target data to another block NOTE 1 DBS must be set before data input 2 Data input could be done anywhere between Start and Write Program Command 3 FSA must be 00 within program operation 4 BSA must be 1000 and BSC must be 000 5 Writing System Configuration Register is optional 6 Write 0 to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 During the execution of the Internal Program Routine the host is not required to provide any further controls or timings Furthermore all com mands except a Reset command will be ignored A reset during a program operation will cause data corruption at the corresponding location If a program error is detected at the completion of the Internal Program Routine map out the block including the page in error and copy the target data to another block An error is signaled if DQ10 1 of Controller Status Register F240h If Power off occurs during a Program operation the page that is being programmed might be corrupted Data from paired pages may be affected ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNA
30. The Output Enable access time tOE is the delay from the falling edge of OE to valid data at the output 3 7 2 Synchronous Read Mode Operation RM 1 WM X See Timing Diagrams 6 1and 6 2 In a Synchronous Read Mode data is output with respect to a clock input The device is capable of a continuous linear burst operation and a fixed length linear burst operation of a preset length Burst address sequences for continuous and fixed length burst operations are shown in the table below Burst Address Sequences Burst Address Sequence Decimal Continuous Burst 4 word Burst 8 word Burst 16 word Burst 32 word Burst 0 1 2 3 4 5 6 0 1 2 3 0 0 1 2 3 4 5 6 7 0 0 1 2 3 4 13 14 15 0 0 1 2 3 4 29 30 31 0 1 2 3 4 5 6 7 1 2 3 0 1 1 2 3 4 5 6 7 0 1 1 2 3 4 5 14 15 0 1 1 2 3 4 5 30 31 0 1 around 2 3 4 5 6 7 8 2 3 0 1 2 2 3 4 5 6 7 0 1 2 2 3 4 5 6 15 0 1 2 2 3 4 5 6 31 0 1 2 the burst mode the initial word will be output asynchronously regardless BRWL While the following words will be determined by BRWL value The latency is determined by the host based on the BRWL bit setting in the System Configuration 1 Register The default BRWL is 4 latency cycles At clock frequencies of 40MHz or lower latency cycles can be reduced to 3 BRWL can be set up to 7 latency cycles The BRWL registers in System Configuration 1 Register can
31. reset occurs Flex MuxOneNAND supports 4 commands for changing Write Protection states of the blocks lock unlock lock tight by one block and All Block Unlock at once All Block Unlock command fails if there are lock tight blocks in flash Write Protection Status The current block Write Protection status can be read in NAND Flash Write Protection Status Register F24Eh There are three bits US LS LTS which are not cleared by hot reset and NAND Flash Core Reset These Write Protection status registers are updated when FBA is set and when Write Protection command is entered The followings summarize locking status By default 2 0 values are 010 For example gt If host executes unlock block operation then 2 0 values turn to 100 gt If host executes lock tight block operation then 2 0 values turn to 001 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 4 3 1 Unlocked NAND Array Write Protection State An Unlocked block can be programmed or erased The status of an unlocked block can be changed to locked or locked tight using the appro priate software command Locked tight state can be achieved in 2 steps First the block should be locked via the lock command Then Lock tight command must be issued Only one block can be released from lock state to unlock state with Unlock command and addresses The unlocked block can be changed
32. with 4 7 clock latency Appropriate wait cycles are determined by programmable read latency Flex MuxOneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter register The device includes one block sized OTP One Time Programmable area and user controlled 1st block OTP Block 0 that can be used to increase system security or to provide identification capabilities ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 1 3 Product Features Device Architecture e Design Technology e Supply Voltage e Host Interface e 5KB Internal BufferRAM Array Device Performance e Host Interface Type e Programmable Burst Read Latency e Multiple Reset Modes e Low Power Dissipation e Reliable CMOS Floating Gate Technology System Hardware e Voltage detector generating internal reset signal from Vcc Hardware reset input RP e Data Protection Modes User controlled One Time Programmable OTP area Internal 4bit ECC Internal Bootloader supports Booting Solution in system Handshaking Feature e Detailed chip information Package size e 4G products 8G products e 16G products TBD M die 1 8V 1 7V 1 95V 16 bit 1KB BootRAM 4KB DataRAM SLC 4K 128 B Page Size 256K 8K B Block Size 64pages 4K 128 B Page Size 512K 16K B Block Size 128pages
33. 01 jueuuno SNJEJS 12 0 0 399u2 SNJEJS 1 llonuoo xoeuo 1ejsiBes SNJEJS 1 llonuoo LNI 1 smes SAVH4ejeq c b 1 1527 uw ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 6 14 Block Erase Operation Timing See AC Characteristics Table 5 7 and Table 5 9 Erase Command Sequence Read Status Data lt y tWEA AVD A DQO AIDQ15 twPL twPH tBERSI CLK INT bit tcez lt gt tcez gt Hi Z NOTE 1 AA Address of address register CA Address of command register ECD Erase Command EMA Address of memory to be erased SA Address of status register 2 For In progress and complete status refer to status register 3 Status reads in this figure is asynchronous read but status read in synchronous mode is also supported ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 6 15 Cold Reset Timing POR triggering level System Power Bootcode copy done A Sep __ _____
34. 0172h Block371 0173h Block372 0174h Block373 0175h Block374 0176h Block375 0177h Block376 0178h Block377 0179h Block378 017Ah Block379 017Bh Block380 017Ch Block381 017Dh Block382 017Eh Block383 19 017Fh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block384 0180h Block385 0181h Block386 0182h Block387 0183h Block388 0184h Block389 0185h Block390 0186h Block391 0187h Block392 0188h Block393 0189h Block394 018Ah Block395 018Bh Block396 018Ch Block397 018Dh Block398 018Eh Block399 018Fh Block400 0190h Block401 0191h Block402 0192h Block403 0193h Block404 0194h Block405 0195h Block406 0196h Block407 0197h Block408 0198h Block409 0199h Block410 019Ah Block411 019Bh Block412 019Ch Block413 019Dh Block414 019Eh Block415 019Fh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block416 01A0h Blo
35. 01D2h Block467 01D3h Block468 01D4h Block469 01D5h Block470 01D6h Block471 01D7h Block472 01D8h Block473 01D9h Block474 01DAh Block475 01DBh Block476 01DCh Block477 01DDh Block478 01DEh Block479 01DFh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block480 01E0h Block481 01E1h Block482 01E2h Block483 01E3h Block484 01E4h Block485 01E5h Block486 01E6h Block487 01E7h Block488 01E8h Block489 01E9h Block490 O1EAh Block491 01 492 01ECh Block493 01EDh Block494 01 495 01EFh Block496 01FOh Block497 01 1 498 01F2h Block499 01F3h 500 01F4h Block501 01F5h 502 01F6h Block503 01F7h Block504 01F8h Block505 01F9h Block506 01 507 01 508 01FCh Block509 01FDh Block510 01FEh Block511 21 01FFh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page A
36. Add F241h DQ 15 INT Y Read Controller status register Add F240h DQ 10 Error Y Read ECC Status Register1 Add FF00h DQ ER1 12 8 ERO 4 0 ER2 4 0 Read ECC Status Register2 Add FF01h DQ ER3 12 8 Write FPA FSA of Flash Add F107h DQ FPA FSA Y 4 4 0 Write BSA BSC DataRAM Add F200h DQ 0800h Read ECC Status Register3 Add FF02h DQ ER5 12 8 ER6 4 0 Read ECC Status Register4 Add FF03h DQ ER7 12 8 Y DataRAM Host reads data from A s eem Sy Write System Configuration Register Add F221h DQ ECC joe Write 0 to INT register Add F241h DQ 0000h L Read ECC Status Register2 Add FF01h DQ ER3 12 8 ER2 4 0 Read ECC Status Register3 Add FF02h DQ ER5 12 8 ER4 4 0 Read ECC Status Register4 Add FF03h DQ ER7 12 8 ER6 4 0 Y Read Completed Write LSB Page Recovery Read Command Add F220h DQ 0005h Host reads data from DataRAM Load Error NOTE 1 BSA must be 1000 Wait for INT register low to high transition Add F241h DQ 15 INT Y Read Controller status register Add F240h DQ 10 Error _ 0 02 2 Write 0 to interrupt register step may be ignored when
37. Array Internal BufferRAM Flex MuxOneNAND DRAM NOTE 1 Step 2 and Step 3 can be copied into DRAM through two DataRAMs Flex MuxOneNAND Boot Sequence ELECTRONICS 138 Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 7 3 Partition of Flex MuxOneNAND Flex MuxOneNAND is the combo device which has SLC and MLC partition in one chip Generally write intensive data require SLC reliability but read and density oriented data such as music and movie satisfy with MLC reliability Therefore some of the mobile phone is using both SLC reliability memory and MLC reliability memory to meet both requirements of reliability oriented and density oriented data using separate chip but in case of Flex MuxOneNAND only one chip of Flex MuxOneNAND can meet the both requirement And also Flex MuxOneNAND has internal Error Correction Circuit and common NOR interface User can take full advantage of advances in NAND Flash memory capacity Last Block Address n 1 Block MLC Partition k 1 n 1 Blocks K 1 Block k Block SLC Partition 0 K Blocks 2 Block 1 Block First Block Address 0 Block SLC Array for Power Up Data Register NOTE 1 Kis the boundary address the end of SLC Samsung will decide the value of K before final specification open K TBD 2 For the partitionning method samsung will support applic
38. Block Block Address F100h FLASH MEMORY Page Address F107h Block960 03COh Block961 03C1h Block962 03C2h Block963 03C3h Block964 03C4h Block965 03C5h Block966 03C6h Block967 03C7h Block968 03C8h Block969 03C9h Block970 03CAh Block971 03CBh Block972 03CCh Block973 03CDh Block974 975 976 977 03D1h Block978 03D2h Block979 03D3h Block980 03D4h Block981 03D5h Block982 03D6h Block983 03D7h Block984 03D8h Block985 03D9h Block986 987 03DBh Block988 03DCh Block989 03DDh Block990 03DEh Block991 03DFh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block992 993 994 O3E2h Block995 Block996 O3E4h Block997 O3E5h Block998 O3E6h Block999 O3E7h Block1000 03E8h Block1001 1002 1003 Block1004 1005 O3EDh Block1006 Block1007 O3EFh Block1008 03FOh Block1009 03F1h Block1010 03F2h Block1011
39. Block Access mode entry revised 27 Chapter 3 12 1 2 Pl Block Erase revised 28 Chapter 3 12 1 3 Block Program Operation revised 29 Chapter 3 12 1 4 Pl Update revised 30 Chapter 3 13 OTP Operation SLC only revised 31 Chapter 3 13 1 OTP Block Load Operation revised 32 Chapter 3 16 2 Invalid Block Replacement Operation revised 33 Chapter 5 5 AC Characteristics for Asynchronous Read revised 34 Chapter 6 3 Asynchronous Read VA Transition Before AVD Low tOEH removed 35 Chapter 6 4 Asynchronous Read VA Transition After AVD Low tOEH removed 36 Chapter 7 4 DDP and QDP Description inserted Q N 1 0 New Format font size color etc Feb 04 2008 Final Corrected errata Added a comment Chapter 3 11 1 amp 3 12 1 2 amp 3 12 1 3 amp 3 12 1 4 Chapter 2 8 17 Start Buffer Register F200h R W revised Chapter 3 1 2 Load Data Into Buffer Command revised Chapter 3 12 2 PI Block Load Operation revised Chapter 4 3 DC Characteristics revised 1 1 Chapter 3 6 2 LSB Page Recovery read flow chart revised Aug 07 2008 Final Chapter 3 9 1 Cache Program Operation revised Chapter 3 13 1 OTP Block Read Operation Flow Chart revised Chapter 3 13 2 OTP Block Program Operation Flow Chart revised Chapter 3 13 3 OTP Block Lock Operation Flow Chart revised Chapter 3 13 4 1st Block OTP Lock Operation revised Chapter 3 13 5 OTP and 1st Block OTP Lock Operation Fl
40. Block713 02C9h Block714 02CAh Block715 02CBh Block716 02CCh Block717 02CDh Block718 02CEh Block719 02CFh Block720 02D0h Block721 02D1h Block722 02D2h Block723 02D3h Block724 02D4h Block725 02D5h Block726 02D6h Block727 02D7h Block728 02D8h Block729 02D9h Block730 02DAh Block731 02DBh Block732 02DCh Block733 02DDh Block734 02DEh Block735 02DFh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block736 02E0h Block737 02E1h Block738 02E2h Block739 02E3h Block740 02E4h Block741 02E5h Block742 02E6h Block743 02E7h Block744 02E8h Block745 02E9h Block746 O2EAh Block747 02 Block748 02bECh Block749 02EDh Block750 02 Block751 02 Block752 02F0h Block753 02F1h Block754 02F2h Block755 02F3h Block756 02F4h Block757 02F5h Block758 02F6h Block759 02F7h Block760 02F8h Block761 02F9h Block762 O2FAh Block763 02FBh Block764 02FCh Block765 O2FDh Block766 O2FEh Block767 25 O2FFh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Fl
41. Chart revised Erase Interleave Flow Chart updated 24 Chapter 3 12 Partition Information Block corrected errata 25 Chapter 3 12 1 Block Load Operation revised 26 Chapter 3 12 2 Block Boundary Information setting updated 27 OTP Operation revised 28 Chapter 3 13 2 OTP Block Program Operation revised 29 Chapter 3 13 3 OTP Block Lock Operation and Flow Chart revised 30 Chapter 3 13 4 1st Block OTP Lock Operation revised 31 Chapter 3 13 5 OTP and 1st Block OTP Lock Operation revised 32 Chapter 3 16 Invalid Block Operation revised 33 Chapter 4 1 Absolute Maximum Ratings revised 34 Chapter 4 2 Operating Conditions revised 35 Chapter 4 3 DC Characteristics revised 36 Chapter 5 1 AC Test Conditions revised 37 Chapter 5 3 Valid Block Characteristics revised 38 Chapter 5 4 AC Characteristics for Synchronous Burst Read revised 39 Chapter 5 8 AC Characteristics for Burst Write Operation revised 40 Chapter 5 9 AC Characteristics for Load Program Erase Performance revised 41 Chapter 6 15 Cold Reset Timing revised 42 Chapter 7 3 Partition of Flex MuxOneNAND corrected errata oL n n a 0 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Revision History Revision No History Draft Date Remark 0 2 Corrected errata Oct 3
42. Diagrams 6 16 6 17 and 6 18 Parameter Symbol Ready1 RP amp Reset Command Latch to BootRAM Access BufferRAM Ready2 RP amp Reset Command Latch During Load Routines to INT High Note1 NAND Flash Array Ready2 RP amp Reset Command Latch During Program Routines to INT High Note1 NAND Flash Array Ready2 NAND Flash Array RP amp Reset Command Latch During Erase Routines to INT High Note1 Ready2 NAND Flash Array RP Pulse Width Note2 tRP RP amp Reset Command Latch NOT During Internal Routines to INT High Note1 NOTE 1 These parameters are tested based on INT bit of interrupt register Because the time on INT pin is related to the pull up and pull down resistor value 2 The device may reset if tRP tRP min 200ns but this is not guaranteed ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 5 7 AC Characteristics for Asynchronous Write See Timing Diagrams 6 5 Parameter WE Cycle Time AVD low pulse width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE Setup Time CE Hold Time WE Pulse Width WE Pulse Width High WE Disable to AVD Enable CE Low to RDY Valid CE Disable to Output amp RDY High Z 5 8 AC Characteristics for Burst Write Operation See Timing Diagram
43. Do not further erase or program block A but instead complete the operation by creating an Invalid Block Table or other appropriate scheme Block Replacement Operation Sequence ja n 1 th Block nth gt error occurs page Buffer memory of the controller EES Block B 7 1st 2 n 1 th nth gt ud page 107 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 4 0 DC CHARACTERISTICS 4 1 Absolute Maximum Ratings Parameter Symbol Rating Vcc Vcc 0 5 to 2 45 All Pins VIN 0 5 to 2 45 Extended 30 to 125 Temperature Under Bias Tbias Industrial 40 to 125 Voltage on any pin relative to Vss Storage Temperature Tstg 65 to 150 Short Circuit Output Current los 5 TA Extended Temp 30 to 85 TA Industrial Temp 40 to 85 Recommended Operating Temperature NOTE 1 Minimum DC voltage is 0 5V on Input Output pins During transitions this level should not fall to POR level typ 1 5V 1 8V device Maximum DC voltage may overshoot to Vcc 2 0V for periods 20ns 2 Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet Exposure to absolute maximum rating conditions for extended periods may affect reliabi
44. FBA which is 0000h of NAND Flash Array address map Issue a Program command to program the data from the DataRAM into the OTP When the OTP Block programming is complete do a Cold Warm Hot NAND Flash Core Reset to exit the OTP Access mode ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY OTP Block Program Operation Flow Chart Start v Write DFS of Flash Add F100h DQ DFS FBA Y Select DataRAM for DDP Add F101h DQ DBS Y Write 0 to interrupt register Add F241h DQ 0000h L 4 Y Write OTP Access Command Add F220h DQ 0065h Y Wait for INT register low to high transition Add F241h DQ 15 INT Write Data into DataRAM Add DP DQ Data in patalnputt Completed NO DBS DFS is for DDP NOTE Write FBA of Flash Add F100h DQ FBA Y Write FSA of Flash Add F107h DQ FPA FSA3 Y Write BSC of DataRAM Add F200h DQ 0800h Y Write 0 to interrupt register Add F241h DQ 0000h 2 v Write Program command Add F220h DQ 0080h Automatically checked Y Automatically NO updated OTPL 0 ves Wait for INT register low to hig
45. Flash Array memory into Page Buffer and transferring from the Page Buffer to the DataRAM are finished By reading the same address more than twice utilizing asynchronous read Figure 6 20 6 21 the host will read tog gled value of DQ6 and the rest of DQ s are not guaranteed to be fixed value DQ6 toggle is only for reading status of BufferRAM which is being loaded by internal operation that is BufferRAM DQ6 toggle bit can be useful at Cold Reset to determine the ready busy state of Flex MuxOneNAND Since INT pin is initially at High Z state when host needs to check the completion of boot code copy operation the host cannot judge the ready busy status of Flex MuxOneNAND by INT pin Therefore by checking DQ6 toggle of BootRAM the host should detect the completion of boot code copy Status DQ15 DQ7 DQ6 DQ5 DQO In Progress Data Loading X Don t Care Toggle X Don t Care ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 15 ECC Operation The Flex MuxOneNAND device has on chip ECC with the capability of correcting up to 4 bit errors in the NAND Flash Array memory main and spare areas 512 16 B As the device transfers data from a BufferRAM to the NAND Flash Array memory Page Buffer for Program Operation the device initiates a background operation which generates an Error Correction Code ECC During a Load operation from the Flash Arra
46. Flash Core Reset command should be issued For the duration of the Erase Suspend period the following commands are not accepted e Block Erase Erase Suspend Erase Suspend and Erase Resume Operation Flow Chart Start Write DFS of Flash gt Add F100h DQ DFS v Write 0 to interrupt register Add F241h DQ 0000h Select DataRAM for DDP Y Add F101h DQ DBS Y _ Select DataRAM for DDP Etude Add F101h DQ DBS Write 0 to interrupt register Add F241h DQ 0000h Y L apie ERE Write Erase Suspend Y Command Write Erase Resume uri Se Es Command Add F220hDQ 00BOh Add F220h DQ 0030h Wait for INT register low to high transition for 500us Wait for INT register Another Operation EU ERE ERES low to high transition 2 Add F241h DQ 15 NT 00949 g ranson Load Program OTP Access Add F241h DQ 1 5 INT Hot Reset Flash Reset CMD Reset Lock Lock tight Unlock Another Operation Check Controller Status Register in case of Block Erase 085 DFS is for DDP NOTE 1 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 2 If OTP access mode exit happens with Reset operation during Erase Suspend mode Reset operatin could hurt the erase opera
47. Flash Md _ Add F107h DQ FPA FSA YES YES Last PGM ilu Write Data into DataRAMO 1_ mos Y _ for a chip Add DataRAM DQ Data 4KB a Write BSA BSC of DataRAM P VES Add F200h DQ 0800n YES Y Write DFS FBA of Flash lt N Wto Data ImtoDataRa N 1 Add F100h DQ DFS complete Write System Configuration Add DataRAM DQ Data 4KB Register 4 abc E EC Read Write Protection Status _ Add F221hDQ ECC Write DFS FBA ofFlash Add F24Eh DQ US LS LTS Add F100h DQ DFS FBA i Write Cache PGM CMD Y Write FPA FSA of Flash 77 Add F220h DQ 007Fh Read Write Protection Status Add F107h DQ FPA FSA Add F24Eh DQ US LS LTS DTP MEE ME Ee Write System Genflauration Te it firet inm NO Y Registe 18 first noc Write FSA of Flash po MS Add F107h DQ FPA FSA Add 221 DQ ECC Write System Configuration Add F220h DQ 0080h a F ee d YES Lo ri i _____ Write CMD9 Register Add F221hDQ ECC 4 Wait for register DBS DFS is for DDP Y low to high transition If prog
48. Lock tight command locked tight blocks will revert to a locked state following a Cold or Warm Reset When there are Lock tight blocks in the flash array All Block Unlock Command will fail and there will be no change in the lock status of the blocks of the Flash array Thus All Block Unlock command succeeds only when there are no tightly locked blocks in Flash Locked tight Lock Tight Command Sequence Start block address rLock tight block command 002Ch 3 4 4 NAND Flash Array Write Protection State Diagram unlock RP pin High amp Start block address 000h RP pin High All Block Unlock Command Lock Start block address unlock Lock block Command Lock or RP pin High Cold reset or amp Warm reset Start block address Unlock block Command Lock lt Power On RP pin High amp Start block address pom reset Lock tight block Command arm rese Lock Lock NOTE If the 1st Block is set to be OTP Block 0 will always be Lock Status ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Data Protection Operation Flow Diagram Add F100h DQ DFS v Select DataRAM for DDP Add F101h DQ DBS Write SBA of Flash Add F24Ch DQ SBA i Write 0 to interrupt register Add F241h DQ 0000h a v Write lock u
49. NAND Flash array or in the BufferRAM BufferRAM On chip internal buffer consisting of BootRAM and DataRAM BootRAM A 1KB portion of the BufferRAM reserved for Boot Code buffering DataRAM A 4KB portion of the BufferRAM reserved for Data buffering 2KB x2 Sector Part of a Page of which 512B is the main data area and 16B is the spare data area Possible data unit to be read from memory to BufferRAM or to be programmed to memory 4224B of which 4096 is in main area and 128B in spare area DDP Dual Die Package QDP Quad Die Package OTP One Time Programmable Data unit ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 3 Pin Configuration 2 3 1 4Gb KFM4GH6Q4M 8Gb KFN8GH6Q4M Tum ni NK TIN vss Vss ADQ2 ADQ14 OE ADQ6 NA ff Core 20 S ADQ4 ADQ5 0012 KA k N ADQ15 NC 10 Aa w 1 AN CU dii p NC E apai3 4 bo 24 V ao NC E y fe 7 ES Ko a es Ww AVD NC b ie CN S y 5 TOP VIEW Balls Facing Down 63ball FBGA Flex MuxOneNAND Chip 63ball 10mm x 13mm x max 1 0mmt 0 8mm ball pitch FBGA 4Gb 63ball 10mm x 13mm x max 1 2mmt 0 8mm ball pitch FBGA 8Gb ELECT
50. Program operation must be utilized within a same area partitioned as SLC or MLC auis lt 544 ni et or 3 Program Page Buffer 3 Write to DataRAM Page B 4 KB Page B 4 DataRAM1 2 Copy to Page Buffer 2 and 2 are concurrent 3 3 are concurrent ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Cache Program Operation Flow Diagram LastPGM Write Data into DataRAMO 1 Write Data into DataRAMO 1 Add DataRAM DQ Data 4KB Start Y Select DataRAM for DDP1 Add F101h DQ DBS Add DataRAM DQ Data 4KB Y Y Y Add DataRAM Write Data into DataRAMO 1 DQ Data 4KB Y Write DFS FBA of Flash Add F100h DQ DFS FBA v Read Write Pr otection Status Write DFS FBA of Flash Add F100h DQ DFS FBA Y Write DFS FBA of Flash Add F24Eh DQ US LS LTS Read Write Protection Status Add F24Eh DQ US LS LTS Add F100h DQ DFS FBA Y Y Y P Write FPA FSA of Flash m Read Write Protection Status l Write FPA FSA of Flash I F24Eh DQ US LS LTS Add F107h DQ FPA FSA2 a zi Add F107h DQ FPA 5 2
51. S D OOOOOO D D O Y Y v 0 3240 05 3 60 1 140 10 TOP VIEW BOTTOM VIEW 2 0 2000 A 8G product KFN8GH6Q4M ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY A1 INDEX 10 00 0 10 i 10 00 0 10 20 10 MAX 0 80 9 7 20 Datum 654 34 B b E ES n MAT 960 Qe 8 QOOOOQG B x D CN CHO ODDO 8 p p _ is S D E e D 6 D OO OO D v v Y 0 32 0 05 3 60 PERN 1 3 0 10 TOP VIEW Subs J BOTTOM VIEW 2020 166 product KFKAGH6Q4M ELECTRONICS
52. Superload command is issued Data is being loaded from NAND to page buffer until whole data in DataRAM is read The read from the DataRAM can be only syn chronous read mode The status information related to load operation can be checked by the host if required When host accesses DataRAM the address of DataRAM must be a multiple of 4 Superload operation must be utilized within a same area partitioned as SLC or MLC Superload Operation Flow Chart Diagram Start Read ECC Status Register1 x _ ET A OO peer ee aces Add FF00h DQ ER1 12 8 ERO 4 0 v Write DFS FBA of Flash F100h DQ DFS Read ECC Status Register2 Add FFO1h DQ ER3 12 8 ER2 4 0 v Select DataRAM for DDP Add F101h DC DBS Read ECC Stat R ter3 Add F101h DQ DBS pead atus Register3 res Read ECC Status Register1 Add FF02h DQ ER5 12 8 ER4 4 0 mL EU MEE Add FF00h DQ ER1 12 8 ERO 4 0 Y Y Write FPA FSA of Flash Add F107h DQ FPA FSA Read ECC Status Register Add FF03h DQ ER7 12 8 ER6 4 0 Add FF01h DQ ER3 12 8 ER2 4 0 Y Write BSA BSC of DataRAM x Y Add F200hDQ 0800h Write DFS FBA of Flash e __ Read ECC Status Register3 Add F100h DQ FBA
53. Supported BufferRAMO Spare 32W 8010h 802Fh J BufferRAM1 Spare 32W 8030h 804Fh Not Supported Reserved Spare 8050h 8FFFh Reserved Register 9000h EFFFh P Register 4KW FOOOh FFFFh 7 Reserved area is available Synchronous read NOTE Continuous burst read should be done with in the address range of the selected buffer RAM dataRAMO or DataRAM1 3 7 2 2 4 8 16 32 Word Linear Burst Read Operation See Timing Diagram 6 1 An alternate Burst Read Mode enables a fixed number of words to be read from consecutive address The device supports a burst read from consecutive addresses of 4 8 16 and 32 words with a linear wrap around When the last word in the burst has been reached assert CE and OE high to terminate the operation In this mode the start address for the burst read can be any address of the address map with one exception The device does not support a 32 word linear burst read on the spare area of the BufferRAM ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 7 2 3 Programmable Burst Read Latency Operation See Timing Diagrams 6 1 and 6 2 Upon power up the number of initial clock cycles from Valid Address AVD to initial data defaults to four clocks The number of clock cycles n which are inserted after the clock which is latching the address The host can read the first data
54. Synchronous Burst Read Up to 66MHz 83MHz clock frequency Linear Burst 4 8 16 32 words with wrap around Continuous 1K words Sequential Burst Synchronous Write Up to 66MHz 83MHz clock frequency Linear Burst 4 8 16 32 1K words with wrap around Continuous 1K words Sequential Burst Asynchronous Random Read 76ns access time Asynchronous Random Write Latency 3 4 Default 5 6 and 7 1 40MHz Latency 3 available 1 66MHz Latency 4 5 6 and 7 available Over 66MHz Latency 6 7 available Cold Warm Hot NAND Flash Core Reset Typical Power Standby current 10uA Single Synchronous Burst Read current 66MHz 83MHz single 20 25mA Synchronous Burst Write current 66MHz 83MHz single 20 25mA Load current 50mA Program current 35mA Erase current 40mA Endurance 50K Program Erase Cycles SLC 10K Program Erase Cycles MLC Data Retention 10 Years SLC 10 Years MLC Write Protection for BootRAM Write Protection for NAND Flash Array Write Protection during power up Write Protection during power down INT pin indicates Ready Busy Polling the interrupt register status bit by ID register 63ball 10mm x 13mm x max 1 0mmt 0 8mm ball pitch FBGA 63ball 10mm x 13mm x max 1 2mmt 0 8mm ball pitch FBGA 63ball 10mm x 13mm x max 1 4mmt 0 8mm ball pitch FBGA TBD ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16
55. The 0196h is the page49 of NAND Flash Array address map 6 BSA must be 1000 and BSC must be 000 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 13 4 1st Block OTP Lock Operation 1st Block can be used as for secured booting operation 1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked however once 1st Block is locked to be OTP 1st Block OTP cannot be erased or programmed Note that once OTP Block is locked 1st Block OTP lock is impossible also OTP Block cannot be locked freely after locking 1st Block OTP OTP Block and 1st Block OTP should be locked at the same time Locking the 1st Block OTP Programming to the 1st Block OTP area can be prevented by locking the OTP area Locking the OTP area is accomplished by programming XXF3h to the 1st word of sector4 of main of the page49 memory area in the OTP block At device power up this word location is checked and if XXF3h is found the OTPg bit of the Controller Status Register is set to 1 indicating the 1st Block is locked When the Program Operation finds that the status of the 1st Block is locked the device updates the Error Bit of the Controller Status Register as 1 fail 1st Block OTP Lock Operation Steps Issue the OTP Access Command Fill data to be programmed into DataRAM data can be input at anytime between the Start and Write
56. command into Command Register when INT is at ready state INT will automatically turn to busy state as command is issued Once the desired operation is completed INT will go back ready state 2 Write 0000h to INT bit of Interrupt Status Register and then write command into Command Register Once the desired operation is com pleted INT will go back to ready state OOFOh and OOF3h may be accepted during busy state of some operations Refer to the right most column of the command register table below F220h default 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Command Acceptable Operation command during busy Load a page unit into buffer OOFOh OOF3h Superload a page unit from buffer OOFOh OOF3h LSB page recovery Read 1 update 2 Program a page unit from buffer amp Finish Program operation at Cache Program operation Cache Program operation OOFOh Unlock NAND array a block OOFOh OOF3h Lock NAND array a block OOFOh OOF3h Lock tight NAND array a block OOFOh All Block Unlock OOFOh Block Erase OOFOh OOF3h Erase Suspend OOFOh Erase Resume OOFOh OOF3h Reset NAND Flash Core OOFOh OOF 3h OOFOh OOF 3h Reset Flex MuxOneNAND 9 Access OOFOh 00F3h Access to Partition Information PI Block OOFOh OOF3h NOTE 1 LSB page recovery Read command can always be issued but not in the PI Block access mod
57. does not have to always be a page 0 MLC Block Page 127 128 Page 127 128 Page 31 32 Page 31 1 Page 2 3 Page 2 3 Page 1 2 Page 1 32 Page 0 1 Page 0 2 Data register Data register From the LSB page to MSB page Ex Random page program Prohibition DATA IN Data 1 Data 128 DATA IN Data 1 Data 128 SLC Block Page 63 64 Page 63 64 Page 31 32 Page 31 1 Page 2 3 Page 2 3 Page 1 2 Page 1 32 Page 0 1 Page 0 2 Data register Data register From the LSB page to MSB page Ex Random page program Prohibition DATA IN Data 1 Data 64 DATA IN Data 1 Data 64 NOTE The figure explains the order of page programming in a block x indicates that the corresponding page is the Xth page to be written in the block ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Paired Page Address Information In case of MLC partition when Program Cache Program Interleave cache program Copy back with random data in operations are abnor mally aborted eg power down not only page data under program but also paired page data may be damaged Paired Page Address Paired Page Address
58. flash ELECTRONICS All Block Unlock Failed Samsung strongly recommends to follow the above flow chart Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 5 Data Protection During Power Down Operation See Timing Diagrams 6 19 The device is designed to offer protection from any involuntary program erase during power transitions RP pin which provides hardware protection is recommended to be kept at VIL before Vcc drops to 1 5V 3 6 Load Operation See Timing Diagrams 6 9 The Load operation is initiated by setting up the start address from which the data is to be loaded The Load command is issued in order to ini tiate the load During a Load operation the device Transfers the data from NAND Flash array into the BufferRAM ECC is checked and any detected and corrected error is reported in the status response as well as any unrecoverable error Once the BufferRAM has been filled an interrupt is issued to the host so that the contents of the BufferRAM can be read The read from the BufferRAM can be an asynchronous read mode or synchronous read mode The status information related to load operation can be checked by the host if required Load Operation Flow Chart Diagram Start i _ Y Write DFS FBA of Flash Write Load Command F100h DQ D
59. from the DataRAM into the OTP When the 1st Block OTP lock is complete do a Cold Reset to exit the OTP Access mode and update 1st Block OTP lock bit 5 and OTP lock bit 6 e 1st Block OTP lock bit 5 and OTP lock bit 6 of the Controller Status Register will be set to 1 and the OTP and 1st Block will be locked Unlike other remaining main area of the NAND Flash Array memory once the OTP block and the 1st block OTP are locked it cannot be unlocked ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY OTP and 1st Block OTP Lock Operation Flow Chart d Start ___Write FBA of Flash M B Add F100h DQ FBA Write DFS FBA of Flash Add F100h DQ DFS FBA me FFA FSA or ria v v DOsoDOUNDBS Write BSA BSC of DataRAM Add F200h DQ 0800h v n m TM DI Write 0 to interrupt register prec cox Add F241h DQ 0000h Write 0 to interrupt register oa Add F241h DQ 0000h Y Write OTP Access Command Add F220h DQ 0065h Write Program command Y Add F220h Y DQ 0080h Wait for INT register low to high transition Add F241h DQ 15 INT un Wait for INT register low to high transition Add F241h DQ 15 INT Write Data into DataRAM 22 Add istWord 00
60. lt gt tAVDP 1 VA Valid Read Address RD Read Data 2 Before IOBE is set to 1 RDY and INT pin are High Z state 3 Refer to chapter 5 5 for tASO description and value Hi Z ELECTRONICS 130 Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx 6 22 INT auto mode See AC Characteristics Table 5 10 FLASH MEMORY tWB gt 4 INT bit 4 Write command into INT will automatically INT will automatically turn back to ready state Command Register turn to Busy State when designated operation is completed WE N ADQ m m m m m m m NOTE 1 INT pin polarity is based on IOBE 1 and INT pol 1 default setting ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 7 0 TECHNICAL AND APPLICATION NOTES From time to time supplemental technical information and application notes pertaining to the design and operation of the device in a system are included in this section Contact your Samsung Representative to determine if additional notes are available 7 1 Methods of Determining Interrupt Status There are two methods of determining Interrupt Status on the Flex MuxOneNAND Using the INT pin or monitoring the Interrupt Status Regis ter Bit The Flex MuxOneNAND INT pin is an output pin function used to
61. memory interface BootBufSize 2 8 7 Amount of Buffers Register F005h R This Read register describes the number of each Buffer F005h default 0201h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DataBufAmount BootBufAmount Number of Buffers Information Register Information Description DataBufAmount The number of data buffers 2 2N 1 BootBufAmount The number of boot buffers 1 2N N20 2 8 8 Technology Register F006h R This Read register describes the internal NAND array technology FOO6h default 0001h Technology Information Technology Register Setting NAND SLC 0000h NAND MLC 0001h Reserved 0002h FFFFh NOTE Flex OneNAND has underlying MLC technology ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 8 9 Start Address1 Register F100h R W This Read Write register describes the NAND Flash block address which will be loaded programmed or erased F100h default 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DFS Reserved 00000 FBA Device Number of Block FBA 4Gb 1024 FBA 9 0 8Gb DDP 2048 DFS 15 amp FBA 9 0 NOTE For QDP See Section 7 4 Start Address1 Information Register Information Description FBA NAND Flash Block Address DFS Flash Core of DDP Device Flash Core Select 2 8 10 Start Address2 Register F101h R W This Rea
62. output will go to high z by toez 2 It is the following clock of address fetch clock ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 5 5 AC Characteristics for Asynchronous Read See Timing Diagrams 6 3 and 6 4 KFM4GH6Q4M KFN8GH6Q4M Parameter KFKAGH6Q4M TBD Min Max Access Time from CE Low 76 Asynchronous Access Time from AVD Low 76 Asynchronous Access Time from address valid 76 Read Cycle Time Low Time Address Setup to rising edge of AVD Address Hold from rising edge of AVD Output Enable to Output Valid 20 CE Setup to AVD falling edge CE Disable to Output amp RDY High 27 20 OE Disable to Output High 27 AVD High to OE Low CE Low to RDY Valid WE Disable to AVD Enable Address to OE low NOTE 1 If OE is disabled at the same time or before CE is disabled the output will go to high z by tOEZ If CE is disabled at the same time or before OE is disabled the output will go to high z by tCEZ If CE and OE are disabled at the same time the output will go to high z by tOEZ These parameters are not 100 tested 2 This Parameter is valid at toggle bit timing in asynchronous read only timing diagram 6 20 and 6 21 5 6 AC Characteristics for Warm Reset RP Hot Reset and NAND Flash Core Reset See Timing
63. the Access Command Refer to Chapter 3 12 1 1 e Issue an Erase command to erase the PI area PI Block Erase Operation Flow Chart In Block Access Mode Start Y Write FBA of Flash 2 Add F220h DQ 0094h Wait for register low to high transition Add F241h DQ 15 INT Read Controller _ gt Status Register YES 0 Add F240h d _DQ 10 1 Error NO d PI Erase Complete Erase Error DBS DFS is for DDP NOTE 1 FBA NAND Flash Block Address must be 0000h 2 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 12 1 3 Block Program Operation The Block Program Operation accesses the PI area and programs content from the DataRAM on chip buffer to the designated page s of the PI A memory location in the PI area can be program The PI area is programmed using the same sequence as normal program operation after being accessed by the PI Block Access mode entry command see section 3 8 for more information Programming the PI Area e Issue the Access Command Refer to Chapter 3 12 1 1 e Write data into the DataRAM In case of PI Lock Add 0200h DQ 3XXXh The lower 10 bits 9 0 are boundary
64. with new lock command Therefore each block has its own lock unlock lock tight state Unlocked Unlock Command Sequence Start block address Unlock block command 0023h Unlocked All Block Unlock Command Sequence Start block address 000h All Block Unlock command 0027h NOTE Even though SBA is fixed to 000h Unlock will be done for all block All block unlock is not valid if there is a lock tight block With DDP all block unlock command must be issued on each chip 3 4 3 2 Locked NAND Array Write Protection State A Locked block cannot be programmed or erased All blocks default to a locked state following a Cold or Warm Reset Unlocked blocks can be changed to locked using the Lock block command The status of a locked block can be changed to unlocked or locked tight using the appro priate software command Locked Lock Command Sequence Start block address Lock block command 002Ah ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 4 3 3 Locked tight NAND Array Write Protection State A block that is in a locked tight state can only be changed to locked state after a Cold or Warm Reset Unlock and Lock command sequences will not affect its state This is an added level of write protection security A block must first be set to a locked state before it can be changed to locked tight using the
65. 0 1 8V 01 3 3V 10 11 reserved DevicelD 2 Muxed Demuxed 0 Muxed 1 Demuxed DevicelD 3 Single DDP 0 Single 1 DDP QDP 0000 128Mb 0001 256Mb 0010 512Mb 0011 1Gb 0100 2Gb 0101 4Gb 0110 8Gb 0111 16Gb DevicelD 9 8 Separation 10 Flex SLC amp MLC 01 MLC 00 51 11 reserved DevicelD 7 4 Density Device ID Default Device DevicelD 15 0 KFM4GH6Q4M 0250h KFN8GH6Q4M 0268h KFKAGH6Q4M 0268h NOTE 1 The base density of all the three device is 4Gb DDP and QDP use 2 and 4 multiplexed chips respectively hence DDP and QDP device ID is same ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx 2 8 4 Version ID Register F002h This register is reserved for future use 2 8 5 Data Buffer Size Register F003h This Read register describes the size of the Data Buffer F003h default 0800h 15 14 13 12 11 10 9 8 7 6 FLASH MEMORY DataBufSize ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 8 6 Boot Buffer Size Register F004h R This Read register describes the size of the Boot Buffer F004h default 0200h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BootBufSize Register Information Description Total boot buffer size in Words equal to 1 buffer of 512 Words 1x 512 29 in the
66. 0 2007 Preliminary Chapter 2 1 Detailed Product Description revised Chapter 2 2 Definitions revised Chapter 2 8 3 Device ID Register FOO1h R revised Chapter 2 8 8 Technology Register FOO6h R revised Chapter 2 8 10 Start Address2 Register F101h R W revised Chapter 2 8 16 Start Address8 Register F107h R W revised Chapter 2 8 18 Command Register F220h R W revised 9 Chapter 2 8 22 Interrupt Status Register F241h R W revised 10 Chapter 3 1 Command Based Operation revised 11 Chapter 3 3 Reset Mode Operation revised 12 Chapter 3 4 3 NAND Array Write Protection States revised 13 Chapter 3 4 3 1 Unlocked NAND Array Write Protection State revised 14 Chapter 3 4 3 3 Locked tight NAND Array Write Protection State revised 15 Chapter 3 4 4 NAND Flash Array Write Protection State Diagram revised 16 Chapter 3 6 2 LSB Page Recovery Read revised 17 Chapter 3 7 2 Synchronous Read Mode Operation revised 18 Chapter 3 7 2 1 Continuous Linear Burst Read Operation revised 19 Chapter 3 9 Program Operation revised 20 Chapter 3 9 1 Cache Program Operation revised 21 Chapter 3 9 2 Interleave Cache Program Operation revised 22 Chapter 3 11 1 Block Erase Operation revised 23 Chapter 3 11 2 Erase Suspend Erase Resume Operation revised 24 Chapter 3 12 Partition Information Block SLC Only revised 25 Chapter 3 12 1 Block Boundary Information setting revised 26 Chapter 3 12 1 1
67. 0 BootS 1 sector 0 of page O block 0 sector 1 of page O block 0 DataRAM Spare area 8010h 804Fh 8 sector x 16byte NAND spare area 128B 8010h 8017h 16B 8018h 801Fh 16B 8020h 8027h 16B 8028h 802Fh 16B DataS 0 0 DataS 0 1 DataS 0 2 DataS 0 3 sector 0 of nth page sector 1 of nth page sector 2 of nth page sector 3 of nth page 8030h 8037h 16B 8038h 803Fh 16B 8040h 8047h 16B 8048h 804Fh 16B DataS 1 0 DataS 1 1 DataS 1 2 DataS 1 3 sector 4 of nth page sector 5 of nth page sector 6 of nth page sector 7 of nth page NAND Flash array consists of 4KB page size and 256KB SLC 512KB MLC block size ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 7 5 External Memory Spare Area Assignment Equivalent to 1word of NAND Flash Word Byte Address Address 8000h 10000h BI Bad block Information 8001h 10002h 8002h 10004h 8003h 10006h 8004h 10008h 8005h 1000Ah Abit ECC parity values 8006h 1000Ch 8007h 1000Eh BootS 1 8008h 10010h BI Bad block Information 8009h 10012h 800Ah 10014h 800Bh 10016h 800Ch 10018h 800Dh 1001Ah Abit ECC parity values 800Eh 1001Ch 800Fh 1001Eh 8010h 10020h BI Bad block Information 8011h 10022h 8012h 10024h 8013h 10026h 8014h 10028h 8015h 1002Ah Abit ECC parity values 8016h 1002Ch 8017h 1002Eh 8018h 10030h BI Bad block Information 8019h 10032h 801Ah 10034h 801Bh 10036h
68. 16G KFKAGH6Q4M DEBx FLASH MEMORY Sector allocation according to BSC CASE1 FSA 00 BSC 000 Sectoro Sectori Sector2 Sector3 Sector4 Sector5 Sector6 Sector7 BSC 001 Sectoro BSC 010 Sectoro Sectori BSC 011 Sectoro Sectori Sector2 BSC 100 Sectoro Sector1 Sector2 Sector3 BSC 101 Sectoro Sector1 Sector2 Sector3 Sector4 BSC 110 Sector1 Sector2 Sector3 Sector4 Sector5 BSC 111 Sectoro Sector1 Sector2 Sector3 Sector4 Sector5 Sector6 Sector allocation according to BSC CASE2 FSA 01 BSC 001 Sector1 BSC 010 Sector1 Sector2 BSC 011 Sector1 Sector2 Sector3 Sector allocation according to BSC CASE3 FSA 10 BSC 001 Sector2 BSC 010 Sector2 Sector3 Sector allocation according to BSC CASE4 FSA 11 BSC 001 Sector3 The first sector from Flash The first sector is determined by FSA In case of FSA 01 CASE2 the first sector is Sector1 is transferred to the 1st sector sector0 of DataRAMO and the other sectors are transferred sequentially ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 8 18 Command Register F220h R W Command can be issued by two following methods and user may select one way or the other to issue appropriate command 1 Write
69. 1E484h 1E496h Reserved Reserved for user F24Ch 1E498h Start Block Address Start memory block address in Write Protection mode F24Dh 1E49Ah Reserved Reserved for user F24Eh 1E49Ch Write Protection Status Current memory Write Protection status unlocked locked tight locked F24Fh FEFFh 1E49Eh 1FDFEh Reserved Reserved for user FFOOh 1FEO0h ECC Status Register 1 ECC status of sectorO and sector 1 FFOth 1FEO2h ECC Status Register 2 ECC status of sector2 and sector 3 FF02h 1FEO4h ECC Status Register 3 ECC status of sector4 and sector 5 FFO3h 1FEO6h ECC Status Register 4 ECC status of sector6 and sector 7 FFOAN FFFFh 1FE08h 1FFFEh ELECTRONICS Reserved 36 Reserved for vendor specific purposes Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 8 2 Manufacturer ID Register F000h This Read register describes the manufacturer s identification Samsung Electronics Company manufacturer s ID is OOECh F000h default OOECh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 8 3 Device ID Register F001h This Read register describes the device F001h see table for default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DevicelD Device Identification Device Identification Description DevicelD 1 0 Vcc 0
70. 6 6 7 and 6 8 Burst mode operations enable high speed synchronous read and write operations Burst operations consist of a multi clock sequence that must be performed in an ordered fashion After CE goes low the address to access is latched on the next rising edge of clk that ADV is low During this first clock rising edge WE indicates whether the operation is going to be a read WE high or write WE low The size of a burst can be specified in the BL as either a fixed length or continuous Fixed length bursts consist of 4 8 16 and 32 words Continuous burst write has the ability to start at a specified address and burst within the designated DataRAM The latency count stored in the BRWL defines the number of clock cycles that elapse before the initial data value is transferred between the processor and Flex MuxOneNAND device The RDY output will be asserted as soon as a burst is initiated and will be de asserted to indicate when data is to be transferred into or out of the memory The processor can access other devices without incurring the timing penalty of the initial latency for a new burst by suspend ing burst mode Bursts are suspended by stopping clk clk can be stopped high or low Note that the RDY output will continue to be active and as a result no other devices should directly share the RDY connection to the controller To continue the burst sequence clk is restarted after valid data is available on the bus Same as the normal bu
71. 60 INI ILON ojne NI UO peseq SI JO pue jndul puewwoy M yous M 2 1 15 SNJEJS Aq pejeorpu smeis moq Asng smeis S AIWYE EC 10 Jojeorpul oi AIVHEJEG Jo sseJppy uv ZY LV gr 7 L LNI L JIE4 O SSEd 0 0 snoi eud L IIE4 0 sseq jueuno 01 pjenu 1ejsiBes SNJEJS 399u2 1ejsibes SNJEJS JejsiBes SNJEJS 2225 u HALNI t 1 x SS 1 SINVEIEG SAVHeeG SAVHejeg 2 124 gir gir 1ndu ev gr Dwusespu Soay Sseuppv 24 Q ssed L l e4 O Sseq snoi eud 0 p xi3 rea Q Sseg jueuno pjenu
72. 6G KFKAGH6Q4M DEBx FLASH MEMORY Erase Interleavel DDP Flow Chart Select DataRAM for DDP Add F100h DQ DFS Add F101h DQ DBS HW command been issued Has Final Erase YES Final Erase status check Y Wait for INT register Select DataRAM for low to high transition Add F101h DQ DBS 2755 Add F241h DQ 5 El Y Write Erase Command Add F220h DQ 0094h Read Controller status register Add F240 DQ 10 Error Y Select DataRAM for DDP XESErase Pass DQ 10 0 NO Erase Fail Select DataRAM for DDP Add F101h DQ DBS Wait for INT register low to high transition 3 Add F241h DQ 5 EI Read Controller status register Add F240h DQ 10 Error Add F241h DQ 15 INT INT 1 Ready _ EE MN Erase Error Add F100h DQ DFS Y Select DataRAM for DDP Add F101h DQ DBS v Write Erase Command Add F220h DQ 0094h Erase Interleave can work in Auto INT Mode Interrupt register must not be written 1 Check the chip status before command issues 2 Previous Erase Status Check NO Erase Fail YES Erase Pass N Erase completed DBS must be changed to indicate chip Erase has been issued pr
73. 73 00ADh Block174 OOAEh Block175 OOAFh Block176 OOBOh Block177 00 1 178 00B2h Block179 00 3 180 00B4h Block181 00 5 182 00 6 183 00B7h Block184 185 OOB9h Block186 OOBAh Block187 OOBBh Block188 00BCh Block189 00BDh Block190 OOBEh Block191 16 OOBFh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block192 00COh Block193 00C1h Block194 00C2h Block195 00C3h Block196 00C4h Block197 00C5h Block198 00C6h Block199 00C7h Block200 00C8h Block201 00C9h Block202 00CAh Block203 00CBh Block204 00CCh Block205 00CDh Block206 207 208 209 00D1h Block210 00D2h Block211 0003 212 00D4h Block213 00D5h Block214 0006 215 00D7h Block216 217 00D9h Block218 00DAh
74. A of Flash Add F100h DQ DFS FBA Y Write BSA BSC of DataRAM Add F200h DQ 0800n _ Y Write 0 to interrupt register3 Add F241h DQ 0000h Y Write FPA FSA of Flash Add F107h DQ 0000n Y Write Update PI command Add F220h DQ 0005h Wait for register low to high transition Add F241h DQ 15 INT updated DBS DFS is for DDP NOTE 1 FBA NAND Flash Block Address must be 0000h 2 BSA must be 1000 and BSC must be 000 3 Write 0 to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 4 FPA must be 00h and FSA must be 00 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 12 2 Block Load Operation A PI Block Load Operation accesses the area and transfers identified content from the PI to the DataRAM on chip buffer thus making the PI contents available to the Host The area is a separate part of the Flash Array memory It is accessed by issuing Access command 66h After being accessed with the Access Command the contents of memory area are loaded using the same operations as a normal load operation to the NAND Flash Array memory see section 3 6 for more information To exit the access mode after PI Block Load Operatio
75. AM Write Protection Operation At system power up voltage detector in the device detects the rising edge of Vcc and releases the internal power up reset signal which trig gers boot code loading And the designated size data 1KB is copied from the first page of the first block in the NAND flash array to the BootRAM After the bootcode loading is completed the BootRAM is always locked to protect the boot code from the accidental write 3 4 2 NAND Flash Array Write Protection Operation The device has both hardware and software write protection of the NAND Flash array Hardware Write Protection Operation The hardware write protection operation is implemented by executing a Cold or Warm Reset On power up the NAND Flash Array is in its default locked state The entire NAND Flash array goes to a locked state after a Cold or Warm Reset Software Write Protection Operation The software write protection operation is implemented by writing a Lock command 002Ah or a Lock tight command 002Ch to command register F220h Lock 002Ah and Lock tight 002Ch commands write protects the block defined in the Start Block Address Register F24Ch 3 4 3 NAND Array Write Protection States There are three lock states in the NAND Array unlocked locked and locked tight On power up all blocks in the NAND array go to Locked state The lock status is maintained for each block in the NAND array Any changes made to lock status of blocks are lost when Cold warm
76. Block819 0333h Block820 0334h Block821 0335h Block822 0336h Block823 0337h Block824 0338h Block825 0339h Block826 033Ah Block827 033Bh Block828 033Ch Block829 033Dh Block830 033Eh Block831 26 033Fh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block832 0340h Block833 0341h Block834 0342h Block835 0343h Block836 0344h Block837 0345h Block838 0346h Block839 0347h Block840 0348h Block841 0349h Block842 034Ah Block843 034Bh Block844 034Ch Block845 034Dh Block846 034Eh Block847 034Fh Block848 0350h Block849 0351h Block850 0352h Block851 0353h Block852 0354h Block853 0355h Block854 0356h Block855 0357h Block856 0358h Block857 0359h Block858 035Ah Block859 035Bh Block860 035Ch Block861 035Dh Block862 035Eh Block863 035Fh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block864 0360h Block865 0361
77. Block915 0393h Block916 0394h Block917 0395h Block918 0396h Block919 0397h Block920 0398h Block921 0399h Block922 039Ah Block923 039Bh Block924 039Ch Block925 039Dh Block926 039Eh Block927 039Fh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block928 929 930 03A2h Block931 932 03A4h Block933 03A5h Block934 03A6h Block935 936 03A8h Block937 03A9h Block938 939 940 Block941 03ADh Block942 943 944 03BOh Block945 03 1 946 03B2h Block947 03B3h Block948 03B4h Block949 03B5h Block950 03B6h Block951 03B7h Block952 03B8h Block953 03B9h Block954 955 03 956 03BCh Block957 03BDh Block958 959 28 O3BFh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h
78. FS k 5 S E Y Add F220h DQ 0000h Host reads data from Y DataRAM Select DataRAM for DDP Add F101h DQ DBS Wait for INT register low to high transition Read completed b Y Add F241h DQ 15 INT _ Write FPA FSA of Flash Add F107h DQ FPA FSA Y Read ECC Status Register1 ro Add FF00h DQ ER1 12 8 ER0 4 0 Write BSA BSC of DataRAM Add F200h DQ 0800h Y Read ECC Status Register2 Y r nivis e Add FF01h DQ ER3 12 8 ER2 4 0 Write System Configuration Register Y Lu na S ZS Z Z U a ag sim a Add F221h DQ ECC Read ECC Status Registers bee ec Add FF02h DQ ER5 12 8 ERA 4 0 a 4 2 Y Write 0 to interrupt register Read ECC Status Register4 Add F241h DQ 0000h _ Add FFO3h DQ ER7 12 8 ER6 4 0 DBS DFS is for DDP NOTE 1 BSA must be 1000 2 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 6 1 Superload Operation See Timing Diagrams 6 10 The Superload operation is used to read multiple pages During Superload operation up to 4bit errors are corrected Once the first data is loaded an interrupt status returns to ready The data in DataRAM should be read after next
79. Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY KFM4GH6Q4M KFN8GH6QA4M KFKAGH6QAM 4Gb Flex MuxOneNAND M die INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS AND IS SUBJECT TO CHANGE WITHOUT NOTICE NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS AS IS BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND 1 For updates or additional information about Samsung products contact your nearest Samsung office 2 Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where Product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply Flex MuxOneNAND is a trademark of Samsung Electronics Company Ltd Other names and brands may be claimed as the property of their rightful owners Samsung Electronics reserves the right to change products or specification without notice 1 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Revision History Document
80. G KFKAGH6Q4M DEBx FLASH MEMORY 2 0 DEVICE DESCRIPTION 2 1 Detailed Product Description The Flex MuxOneNAND is an advanced generation high performance MLC NAND based Flash memory Which can be programmed as both SLC and MLC It integrates on chip a convertible SLC and Flash Array memory with two independent data buffers boot RAM buffer a page buffer for the Flash array and a one time programmable block The combination of these memory areas enable high speed pipelining of reads from host BufferRAM Page Buffer and NAND Flash Array Clock speeds up to 66MHz 83MHz with a x16 wide I O yields 83MByte second SLC 71MByte second MLC read bandwidth The Flex MuxOneNAND also includes a Boot RAM and boot loader This enables the device to efficiently load boot code at device startup from the NAND Array without the need for off chip boot device One block of the NAND Array is set aside as an OTP memory area and 1st Block Block 0 can be used as OTP area This area available to the user can be configured and locked with secured user information On chip controller interfaces enable the device to operate in systems without NAND Host controllers 2 2 Definitions B capital letter Byte 8bits W capital letter Word 16bits b lower case letter Bit ECC Error Correction Code Calculated ECC ECC that has been calculated during a load or program access Written ECC ECC that has been stored as data in the
81. G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Read Interrupt RI This is the Read interrupt bit RI Interrupt 7 Default State Interrupt Status Conditions Cold Warm hot Function 1 0 off At the completion of a Load Superload or LSB Page sets itself to 1 Recovery Read Operation Pending 0000h 0003h 0005h 0 is written to this bit Cold Warm Hot reset is being performed or command is written to Command Register INT auto mode clears to O Write Interrupt WI This is the Write interrupt bit WI Interrupt 6 Default State Interrupt Cold Warm hot Function 0 0 off Status Conditions At the completion of an Program Operation 0080h and 007Fh 0 is written to this bit Cold Warm Hot reset is being performed or com mand is written to Command Register in INT auto mode sets itself to 1 Pending clears to 0 Erase Interrupt El This is the Erase interrupt bit El Interrupt 5 Default State Interrupt Cold Warm hot Function 0 0 off Status Conditions At the completion of an Erase Operation 0094h and 0030h 0 is written to this bit Cold Warm Hot reset is being performed or com mand is written to Command Register in INT auto mode sets itself to 1 Pending clears to 0 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEB
82. INT 1 default setting Method 2 Write command into Command Register at INT ready state Auto INT Mode 1 Write command into Command Register This will automatically turn INT from high to low 1 2 INT pin will turn back to high once the operation is completed 1 INT pin INT bit Write command into INT will automatically INT will automatically turn back to ready state Command Register turn to Busy State when designated operation in completed NOTE 1 INT pin polarity is based on IOBE 1 and INT pol 1 default setting ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 8 19 System Configuration 1 Register F221h R R W This Read Write register describes the system configuration F221h default 40COh Read Mode RM Read Mode Asynchronous read default Synchronous read Read Mode Information 15 Definition Description Selects between asynchronous read mode and Read synchronous read mode Burst Read Write Latency BRWL Latency Cycles Read Write BRWL under 40MHz 40MHz 66MHz over 66MHz HF 0 HF 0 HF 1 000 010 Reserved 011 3 up to 40MHz min 3 N A 3 N A 100 default 4 min 4 N A 101 5 N A 110 6 min 111 7 Default value of BRWL and HF value is BRWL 4 HF 0
83. KB 9000h BFFFh 12000h 17FFEh 24KB Reserved Reserved Reserved 8KB C000h CFFFh 18000h 19FFEh 8KB Reserved Reserved Reserved 16KB D000h EFFFh 1A000h 1DFFEh 16KB Reserved Reserved Registers 8KB FOOOh FFFFh ELECTRONICS 1E000h 1FFFEh 8KB 31 Registers Registers Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 7 4 External Memory Map Detail Information The tables below show Word Order Address Map information for the BootRAM and DataRAM main and spare areas BootRAM Main area 0000h 01FFh 2 sector x 512byte NAND main area 1KB 0000h 00FFh 512B 0100h 01FFh 512B BootM 0 BootM 1 sector 0 of page O block 0 sector 1 of page O block 0 e DataRAM Main area 0200h 09FFh 8 sector x 512byte NAND main area 0200h 02FFh 512B 0300h 03FFh 512B 0400h 04FFh 512B 0500h 05FFh 512B DataM 0 0 DataM 0 1 DataM 0 2 DataM 0 3 sector 0 of nth page sector 1 of nth page sector 2 of nth page sector 3 of nth page 0600h 06FFh 512B 0700h 07FFh 512B 0800h 08FFh 512B 0900h 09FFh 512B DataM 1 0 DataM 1 1 DataM 1 2 DataM 1 3 sector 4 of nth page sector 5 of nth page sector 6 of nth page sector 7 of nth page BootRAM Spare area 8000h 800Fh 2 sector x 16byte NAND spare area 32B 8000h 8007h 16B 8008h 800Fh 16B BootS
84. NAND Flash Sector Address 00 NOTE 1 Only 6bits must be used for 64pages in SLC area SLC 64pages MLC 128pages 2 Sectors 4 7 in a page are not directly addessable using FSA However they can be accessed using BSA and BSC See Below FSA must be 00 in program operation 2 8 17 Start Buffer Register F200h R W This Buffer Sector Count BSC specifies the number of sectors to be loaded F200h default 0000h 15 14 13 6 5 4 Reserved 0000 Reserved 00000 The BufferRAM Sector Address BSA is the sector 0 3 address in the internal BootRAM and DataRAM where data is placed NOTE 1 In case of Program and Load Internally BSA fix first sector of DataRAMO BSA 1000 Description BSC Value Number of Sectors 000 Default 8 sectors 001 1 sectors 010 2 sectors BSC rr 011 3 sectors uffer Sector Coun CASE1 FSA 00 100 4 sectors 101 5 sectors 110 6 sectors 111 7 sectors 001 1 sectors BSC CASE2 FSA 01 Buffer Sector Count 010 2 sectors 011 3 sectors BSC EAR 001 1 sectors uffer Sector Coun CASE3 FSA 10 010 2 sectors BSC CASE4 FSA 11 Buffer Sector Count 001 4 sectors NOTE 1 BSC is used only on load operation 2 Operation not guaranteed for cases not defined in above table CASE1 CASE2 CASE3 CASE4 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND
85. ND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Program Interleave DDP Flow Chart Start Y Select DataRAM for DDP Add F101h DQ DBS Y Write Data into DataRAM Add DataRAM DQ Data 4KB Y Write DFS FBA of Flash Add F100h DQ DFS FBA Read Write Protection Status Add F24Eh DQ US LS LTS Write FPA FSA of Flash Add F220h DQ 0080h Select DataRAM for DDP Add F101h DQ DBS INI w Check for INT register high Add F241h DQ 15 INT INT 1 Ready 222 Select DataRAM for DDP1 Add F101h DQ DBS Write Data into DataRAM Add DataRAM DQ Data 4KB v Write DFS FBA of Flash Add F100h DQ DFS FBA Read Write Protection Status Add F24Eh DQ US LS LTS Y Write FSA of Flash Add F220h DQ 0080h Y Select DataRAM for DDP Add F101h DQ DBS Wait for register low to high transition Add F241h DQ 6 WI Y Read Controller status register Add F240h DQ 10 Error NO Has Final Program command been issued YES Final Program status check Select DataRAM for DDP Add F101h DQ DBS Wait for INT register low to high transition g Add F241h DQ 6 WI
86. OBE should be 0 for INT 2 active for Host access 3 active for Internal operation without host access 4 Vccq is equivalent to Vcc IO ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 5 0 AC CHARACTERISTICS 5 1 AC Test Conditions Parameter Value 66MHz Value 83MHz Input Pulse Levels OV to Vcc OV to Vcc CLK 3ns 2ns other inputs 5ns 2ns Input Rise and Fall Times Input and Output Timing Levels VCC 2 Vcc 2 Output Load CL 30pF CL 30pF Vcc Input amp Output Vcc 2 Test Point Vcc 2 OV Input Pulse and Test Point Device Under Test CL 30pF including scope and Jig capacitance Output Load 5 2 Device Capacitance 25 C Vcc 1 8V f 1 0MHz Item Test Condition Input Capacitance Vin 0V Control Pin Capacitance Vin 0V Output Capacitance VouT 0V INT Capacitance Vour 0V NOTE 1 Capacitance is periodically sampled and not 10090 tested 5 3 Valid Block Characteristics Parameter i Unit Valid Block Number Blocks NOTE 1 The device may include invalid blocks when first shipped Additional invalid blocks may develop while being used The number of valid blocks is presented with both cases of invalid blocks considered Invalid
87. Program commands Write XXF3h data into the 1st word of sector4 of main of the page49 memory area of the DataRAM Issue a Flash Block Address FBA which is 0000h of NAND Flash Array address map Issue a Program command to program the data from the DataRAM into the OTP When the 1st Block OTP lock is complete do a Cold Reset to exit the OTP Access mode and update 1st Block OTP lock bit 5 e 1st Block OTP lock bit 5 of the Controller Status Register will be set to 1 and the 1st Block will be locked Even though the OTP area can only be programmed once without erase capability it can be locked when the device starts up to prevent any changes from being made Unlike other remaining main area of the NAND Flash Array memory once the 1st block OTP is locked it cannot be unlocked Once 1st block is set as OTP Flash Write Protection status register F24Eh indicates only Lock state although Lock tight or Unlock command is issued ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 1st Block OTP Lock Operation Flow Chart Start 22 Write FBA of Flash Add F100h DQ FBAJ Y Write DFS FBA Flash FS TEEN Add F100h DQ DFS RS TEA TOM OL Tia 2 Add F107h DQ 0196h v v
88. Q15 ADQ0 lt _ gt lt BootRAM CLK B StateMachine gt CE1 DataRAMO CE2 r E 9 lt DataRAM1 NAND Flash Array wE 3 RP gt Correction AD Internal Registers Logic INT INT1 Address Command Configuration 2 Status Registers OTP RDY One Block 2 6 Memory Array Organization The Flex MuxOneNAND architecture integrates several memory areas on a single chip 2 6 1 Internal NAND Array Memory Organization The on chip internal memory is a convertible SLC and MLC NAND array used for data storage and code The internal memory is divided into a main area and a spare area Main Area The main area is the primary memory array A block incorporates 64pages SLC or 128pages MLC A main page size is 4KB and a main page is comprised of 8 sectors each size of which is 512Byte Spare Area The spare area is used for invalid block information and ECC storage Spare area internal memory is associated with corresponding main area memory A spare page size is 128B and a spare page is comprised of 8 sectors each size of which is 16Byte ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Internal Memory Array Information Area Se
89. Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block320 0140h Block321 0141h Block322 0142h Block323 0143h Block324 0144h Block325 0145h Block326 0146h Block327 0147h Block328 0148h Block329 0149h Block330 014Ah Block331 014Bh Block332 014Ch Block333 014Dh Block334 014Eh Block335 014Fh Block336 0150h Block337 0151h Block338 0152h Block339 0153h Block340 0154h Block341 0155h Block342 0156h Block343 0157h Block344 0158h Block345 0159h Block346 015Ah Block347 015Bh Block348 015Ch Block349 015Dh Block350 015Eh Block351 015Fh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block352 0160h Block353 0161h Block354 0162h Block355 0163h Block356 0164h Block357 0165h Block358 0166h Block359 0167h Block360 0168h Block361 0169h Block362 016Ah Block363 016Bh Block364 016Ch Block365 016Dh Block366 016Eh Block367 016Fh Block368 0170h Block369 0171h Block370
90. QO je X D2 p X D 07 tACH tACH twES lt WE l l twEH lt tRDYS l tRDYS Hi Z tRDYA i Hi Z tRDYA lt l RDY 118 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 6 8 Start Initial Burst Write Operation See AC Characteristics Table 5 8 iu ce NER gt tCEHP ddum s e ewm CES CLK tcLKH tCLKL teEH i lt t 1 1 ER aem O 1 2 3 d PLEILEPLE LAE LALI LT LT LT Li Li 11 tRDYO AVD AN dir tAVDH twps twbH tACS A DQO AIDQ15 X ZA n x tACH OE twES 4 7 Z 7 tRDYS gt 4 Hi Z y tRDYA lt gt RDY N ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 6 9 Load Operation Timing See AC Characteristics Table 5 7 and Table 5 9 Load Command Sequence last two cycles Read Data tAAVDS lt AVD tAVDP tAAVDH ADQ0 15 AA LMA X LCD SA BA Datn t lt gt twEA DS __ ics es tH CE Pd tCER gt l tWPL m t
91. RONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 3 2 16Gb Product KFKAGH6Q4M TBD SS n Vss Vss ADQ2 x NL P 554 P NC wo Z Ro A 4 Z ON ADQ6 ue N __ Oe ADQ3 ADQ7 0014 OE N PON CN AT ADQ8 pat ADQ4 ADQ5 ri N Se EO SS ii 55 A N fi D he S ADQ15 NC ADQ10 NS NL pe gt SY DQ12 vec Core ee Ncc ki I9 K x X N N NC N Z ADQ13 INT2 NC E 2 WO di MB gt 2 2 E _ P k 4 TOP VIEW Balls Facing Down 63ball FBGA OneNAND Chip 63ball 10mm x 13mm x max 1 4mmt 0 8mm ball pitch FBGA 9 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 4 Pin Description Pin Name Nameand Description Host Interface Multiplexed Address Data bus Inputs for addresses during read operation which are for addressing BufferRAM amp Register ADQ15 ADQO Inputs data during program and commands for all operations outputs data during memory array register read cycles Data pins float to high impedance when the chip is deselected
92. Title Flex MuxOneNAND Revision History Revision No History Draft Date Remark 0 0 1 Initial issue Nov 28 2006 Advanced 0 1 Corrected errata Aug 13 2007 Preliminary Chapter 1 3 Product Features revised Chapter 2 8 16 Start Address8 Register F107 revised Chapter 2 8 18 Command Register F220h revised Chapter 2 8 19 System Configuration 1 Register F221h corrected errata Chapter 2 8 21 Controller Status Register F240h revised Chapter 2 8 22 Interrupt Status Register F241h revised Chapter 3 1 2 Load Data Into Buffer Command Chapter 3 3 Reset Mode Operation revised Chapter 3 3 1 Cold Reset Mode Operation revised Chapter 3 4 3 NAND Array Write Protection States corrected errata Chapter 3 4 3 1 Unlocked NAND Array Write Protection State Chapter 3 4 4 Data Protection Operation Flow Diagram revised Chapter 3 4 4 All Block Unlock Flow Diagram revised Chapter 3 6 Load Operation Flow Chart Diagram revised Chapter 3 6 1 Superload Operation revised Chapter 3 6 2 LSB Page Recovery Read updated Chapter 3 8 Synchronous Write revised Chapter 3 9 Program Operation Flow Diagram revised Program Interleave Flow Chart updated 20 Chapter 3 9 1 Cache Program Operation Flow diagram revised 21 Chapter 3 9 2 Interleave Cache Program Operation revised 22 Chapter 3 10 Copy Back Program Operation with Random Data Input Flow Chart revised 23 Chapter 3 11 1 Block Erase Operation Flow
93. Writing System Configuration Register is optional 4 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 ELECTRONICS Random Data Input Add Random Address in Selected DataRAM DQ Data Write DFS FBA of Flash Add F100h DQ DFS FBA Read Write Protection Status Add F24Eh DQ US LS LTS Y Write FPA FSA of Flash Add F200h DQ 0800h2 __ 81 Add F221h DQ ECC Write 0 to interrupt register Add F241h DQ 0000h Write Program Command Add F220h DQ 0080h Wait for INT register low to high transition Add F241h DQ 15 INT Read Controller Status Register Add F240h DQ 10 Error _ ves Copy back completed Copy back Error DBS DFS is for DDP Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 11 Erase Operation 3 11 1 Block Erase Operation See Timing Diagram 6 14 The device can be erased one block at a time To erase a block is to write all 1 s into the desired memory block by executing the Internal Erase Routine All previous data is lost Block Erase Operation Flow Chart Start Y Write DFS FBA of Flash Add F100h DQ DFS FBA v Select DataRAM for DDP
94. Y is Write FPA FSA of Flash Write oe Write System Configuration Add F107h DQ FPA FSA2 ro NM Register tee DORECG Add F221h DQ ECC Write 5 BSC of DataRAM Y Y 5 Write 0 to interrupt register Write 0 to interrupt register Add F241h DQ 0000h Add F241h DQ 0000h ad m Write System Configuration v Y Register Write Cache PGM CMD _ Write Finish PGM CMD Add F220h DQ 007Fh Add F220h DQ 0080h Add F221h DQ ECC y Wait for INT register low to high transition M Wait for INT register Write 0 to interrupt register low to high transition Add F241h DQ 0000h Add F241h DQ 8040h Add F241h DQ 8040h Y Write Cache PGM CMD Read Controller __ Add F220h DQ 007Fh Status Register Add F240h DQ 10 Error Read Controller Status Register Y Wait for INT register Add F240h DQ 10 Error low to high transition Y pue A Add F241h DQ 8040h DQ 10 0 DQ 10 0 YES es complete DBS DFS is for DDP If program operation results in an error map out the block including the page error and copy the target data to another block Program Error NOTE 1 DBS must be set before data input 2 FSA must be 00 and BSC must be 000 within p
95. address In case of PI Unlock Add 0200h DQ FXXXh The lower 10 bits 9 0 are boundary address e Write 0000h into Flash Block Address FBA that is address of NAND Flash Array address map e Issue a Program command to program the data from the DataRAM into the PI Block Program Operation Flow Chart In Block Access Mode Write Program command EcL SR NE Add F220h Start ki ar E DQ 0080h Write Data into DataRAM Wait for INT register low to high transition Add F241h DQ 15 INT 1 Write DFS of Flash Read Controller Status Register YES Add F240h DQ 10J Error 77 Add F107h DQ 0000n NO Y 7 TR Pl Programming completed PI Program Error Write BSA BSC of DataRAM ka d Add F200h DQ 0800h Y Write 0 to interrupt register DBS DFS is for Add F241h DQ 0000h Locking the PI Programming to block can be prevented by locking the area Locking the area is accomplished by programming 3XXXh to 1st word of sector0 of main of the pageO memory area in the PI block XXXh out of 3XXXh is a boundary block address that ends SLC area Once Lock bits are programmed as lock status PI block will be protected from program and erase Boundary address is alterable before PI block is locked but it is not recommended At device p
96. and F241h DOQMSJANT Add F220h DQ 0065h Y Host reads data from Wait for INT register DataRAM low to high transition eis ete pu NO MN Y i 2 Add F241h DAMSIPINT Reading completed d v Write FSA of Flash ALAS EARS SALEDA Do Cold Warm Hot Add F10rh FSA INAND Flash Core Reset v Write BSA BSC of DataRAM m F200h DQ 0800h OTP Exit 7 DBS DFS is for DDP NOTE 1 FBA NAND Flash Block Address could be omitted or any address 2 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 3 BSA must be 1000 and BSC must be 000 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 13 2 OTP Block Program Operation An OTP Block Program Operation accesses the OTP area and programs content from the DataRAM on chip buffer to the designated page s of the OTP A memory location in the OTP area can be programmed only one time no erase operation permitted The OTP area is programmed using the same sequence as normal program operation after being accessed by the command see section 3 9 for more information Programming the OTP Area e Issue the OTP Access Command Write data into the DataRAM data can be input at anytime between the Start and Write Program commands Issue a Flash Block Address
97. ation 1 Definition Description Selects between asynchronous Write Mode and Write Mode synchronous Write Mode MRS Mode Register Setting Description Mode Description Asynch Read amp Asynch Write Default Sync Read amp Asynch Write Sync Read amp Synch Write Other Cases Reserved NOTE 1 Operation not guaranteed for cases not defined in above table Boot Buffer Write Protect Status BWPS Boot Buffer Write Protect Status Information 0 Definition Description Boot Buffer Write Protect Status O locked fixed ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 8 20 System Configuration 2 Register F222h This register is reserved for future use 2 8 21 Controller Status Register F240h R This Read register shows the overall internal status of the Flex MuxOneNAND and the controller F240h default 0000h 2 1 Previous Current OnGo This bit shows the overall internal status of the Flex MuxOneNAND device In Cache Program Operation OnGo bit shows the overall status of Cache Program process OnGo Information 15 Definition Description 0 ready 1 busy Internal Device Status Error This bit shows the overall Error status In case of Cache Program Error bit will show the accumulative error status of Cache Program operation so that if an error occurs during
98. ation note and guidance code ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 7 4 DDP and QDP Description CHIP 1 Comp DFS L3 Oa FLASH CE amp amp DDP OPT INT zi SRAM DES Comp Oo BUFFER L 5S DFS FLASH Comp CORE DDP Dual Die Package 8Gb DDP Flex OneNAND contains two chips of 4Gb which are multiplexed such that they provide a single address range interface with dou ble the storage capacity Since the address range is single the BootRAM the bufferRAM and the register set are multiplexed BootRAM The bootRAM of chip1 is selected always and the contents of the block 0 of chip1 are copied to it at startup DataRAM DBS setting in Start Address2 Register See Section 2 8 10 decides which DataRAM is selected Register Set In the case of write both registers in chip1 and chip2 will be written Regardless of DBS Reading out from register of chip1 chip2 follows the DBS setting See Section 2 8 10 QDP Quad Die Package A QDP is made up of 2 DDP chips and is effectively 2 separate Flex OneNAND devices in the same die There are 2 chip select pins CE1 and CE2 on a QDP device using which one of the two devices can be selected Since there are separate chip sele
99. be read during a burst read mode by using the AVD signal with the address F221h ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 7 2 1 Continuous Linear Burst Read Operation See Timing Diagram 6 2 First Clock Cycle The initial word is output at tIAA after the rising edge of the first CLK cycle The RDY output indicates the initial word is ready to the system by pulsing high If the device is accessed synchronously while it is set to Asynchronous Read Mode the first data can still be read out Subsequent Clock Cycles Subsequent words are output Burst Access Time from Valid Clock to Output tBA after the rising edge of each successive clock cycle which automatically increments the internal address counter Terminating Burst Read The device will continue to output sequential burst data until the system asserts CE high or RP low wrapping around until it reaches the des ignated address see section 2 7 3 for address map information Alternately a Cold Warm Hot Reset or a WE low pulse will terminate the burst read operation Synchronous Read Boundary Division Add map word order BootRAM Main 0 5KW 0000h 01FFh Not Supported BufferRAMO Main 1KW 0200h 05FFh E Not Supported BufferRAM1 Main 1KW 0600h 09FFh lt N Reserved Main 0A00h 7FFFh BootRAM Spare 16W 8000H 800Fh me Not Supported Not
100. be written with a Boot Partition address Thus the command based interface is active only in the boot partition The remaining address range except for the boot area address range 0200h FFFFh can be used as a read write data buffer with a few exceptions like ID registers Writes outside the boot partition are treated as normal writes to the buffers or registers The command consists of one or more cycles depending on the command After completion of the command the device starts its execution Writing incorrect information including address and data to the boot partition or writing an improper command will terminate the previous com mand sequence and make the device enter the ready status The defined valid command sequences are stated in Command Sequences Table Command based operations are mainly used when Flex MuxOneNAND is used as Booting device and all command based operations only supports asynchronous reads and writes With DDP com mand based operation except reset is applicable only on chip1 Command Sequences Command Definition 1st cycle 2nd cycle BP OOFOh BP BP 00E0h 0000h BP XXXXh 0090h Data Reset Flex MuxOneNAND Load Data into Buffer Read Identification Data 9 NOTE 1 BP Boot Partition BootRAM Area 0000h 01FFh 8000h 800Fh 2 Load Data into Buffer operation is available within a block 128KB SLC 256KB MLC Chip1 only in case of DDP 3 Load 4KB un
101. becomes ready and then Host can issue load command Refer to 7 2 2 Boot Sequence 7 1 Methods of Determining Interrupt status ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 6 17 Hot Reset Timing See AC Characteristics Table 5 6 AVD BP Note 3 Y ADAI or F220h or tReady2 INT bit High Z i RDV Flex MuxOneNAND Operation Operation or Idle J Flex MuxOneNAND reset J Idle NOTE 1 Internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferRAM data are kept unchanged after Warm Hot reset operations 2 Reset command Command based reset or Register based reset 3 BP Boot Partition BootRAM area 0000h 01FFh 8000h 800Fh 4 for BP and OOF3h for F220h ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 6 18 NAND Flash Core Reset Timing See AC Characteristics Table 5 6 AVD ADQi F220h OOFOh tReady2 INT bit High Z RDY Flex MuxOneNAND o Operation or Idle 1 Flash Core reset Idle peration 6 19 Data Protection Timing During Power Down The devic
102. blocks are defined as blocks that contain five or more bad bits which cause status failure during Program and Erase operation Do not erase or program factory marked bad blocks 2 The 1st block which is placed on 00h block address is guaranteed to be a valid block up to 1K program erase cycles with 4bit 528Byte ECC ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 5 4 AC Characteristics for Synchronous Burst Read See Timing Diagrams 6 1 and 6 2 Parameter Clock Clock Cycle Initial Access Time Burst Access Time Valid Clock to Output Delay tBA AVD Setup Time to CLK tAVDS AVD Hold Time from CLK tAVDH AVD High to OE Low tavDo Address Setup Time to CLK tacs Address Hold Time from CLK tACH Data Hold Time from Next Clock Cycle Output Enable to Data Disable to Output amp RDY High 2 tcez OE Disable to Output High Z toez CE Setup Time to CLK tces 6 CLK High or Low Time tCLKH L tcLk 3 CLK 2 to RDY valid tRDYO to RDY Setup Time tRDYA RDY Setup Time to CLK tRDYS CE low to RDY valid 1 If OE is disabled at the same time or before CE is disabled the output will go to high z by toez If CE is disabled at the same time or before OE is disabled the output will go to high z by tcez If CE and OE are disabled at the same time the
103. ck36 0024h Block5 0005h Block37 0025h Block6 0006h Block38 0026h Block7 0007h Block39 0027h Block8 0008h Block40 0028h Block9 0009h Block41 0029h Block10 000Ah Block42 002Ah Block 000Bh Block43 002Bh Block12 000Ch Block44 002Ch Block13 000Dh Block45 002Dh Block14 000Eh SLC Block46 002Eh SLC Block Block15 000Fh 0000h 00FCh Block47 002Fh 0000h 00FCh Block16 0010h is Block48 0030h MLC Block17 0011h 0000h 01FCh Block49 0031h 0000h 01FCh Block18 0012h Block50 0032h Block19 0013h Block51 0033h Block20 0014h Block52 0034h Block21 0015h Block53 0035h Block22 0016h Block54 0036h Block23 0017h Block55 0037h Block24 0018h Block56 0038h Block25 0019h Block57 0039h Block26 001Ah Block58 003Ah Block27 001Bh Block59 003Bh Block28 001Ch Block60 003Ch Block29 001Dh Block61 003Dh Block30 001Eh Block62 003Eh Block31 001Fh Block63 003Fh Only four sectors are addressable see Start Address Register ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block64 0040h Block65 0041h Block66 0042h Block67
104. ck417 O1A1h Block418 01A2h Block419 01A3h Block420 01A4h Block421 01A5h Block422 01A6h Block423 O1A7h Block424 01A8h Block425 01A9h Block426 01AAh Block427 01ABh Block428 01ACh Block429 01ADh Block430 O1AEh Block431 01AFh Block432 01BOh Block433 01B1h Block434 01B2h Block435 01B3h Block436 01B4h Block437 01B5h Block438 01B6h Block439 01B7h Block440 01B8h Block441 01B9h Block442 01BAh Block443 01BBh Block444 01BCh Block445 01BDh Block446 01BEh Block447 20 01BFh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block448 01COh Block449 01C1h Block450 01C2h Block451 01C3h Block452 01C4h Block453 01C5h Block454 01C6h Block455 01C7h Block456 01C8h Block457 01C9h Block458 01CAh Block459 01CBh Block460 01CCh Block461 01CDh Block462 01CEh Block463 01CFh Block464 01D0h Block465 01D1h Block466
105. cks lies in the same word of OTP area Therefore if OTP Block is locked prior to 1st Block OTP lock 1st Block OTP cannot be locked Locking the OTP Programming to the OTP area can be prevented by locking the OTP area Locking the OTP area is accomplished by programming XXFCh to the 1st word of sector4 of main of the page49 memory area in the OTP block At device power up this word location is checked XXFCh is found the OTP bit of the Controller Status Register is set to 1 indicating the OTP is locked When the Program Operation finds that the status of the OTP is locked the device updates the Error Bit of the Controller Status Register as 1 fail OTP Lock Operation Steps Issue the OTP Access Command Fill data to be programmed into DataRAM data can be input at anytime between the Start and Write Program commands Write XXFCh data into the 1st word of sector4 of main of the page49 memory area of the DataRAM Issue a Flash Block Address FBA which is 0000h of NAND Flash Array address map Issue a Program command to program the data from the DataRAM into the OTP When the OTP lock is complete do a Cold Reset to exit the OTP Access mode and update OTP lock bit 6 OTP lock bit 6 of the Controller Status Register will be set to 1 and the OTP will be locked ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY OTP Block Lock O
106. ctor Main SLC Main MLC 512B Spare SLC Spare MLC 16B Internal Memory Array Organization Sector Main Area Spare Area 512B 16B T Main Area Spare Area SectorO Sector1 Sector2 Sector3 Sector4 Sector5 Sector6 Sector7 Sector Sector Sector 4KB 512Bx8 128B 16Bx8 Block MLC Main Area Spare Area 4KB Page0 128B Page0 Page 0 I 4 Page127 128B Page127 Page 127 UTERE ii i i 9 c 512 16 Block SLC Main Area Spare Area 4KB Page0 128B Page0 Page 0 E i 4KB Page63 128B Page63 Page 63 256 8KB ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 6 2 External BufferRAM Memory Organization The on chip external memory is comprised of 3 buffers used for Boot Code storage and data buffering The BootRAM is a buffer that receives Boot Code from the internal memory and makes it available to the host at start up There are 4KB bi directional data buffers 2KB x2 DataRAMO and DataRAM1 During Boot Up the BootRam is used by the host to initialize the main memory and deliver boot code from NAND Flash core to host External Bu
107. cts for the two devices they have different address ranges and register sets which can be directly accessed by the processor Thus each of the registers BufferRAMs can be selected by using the CE pin and then using the same settings that apply to a DDP chip ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 8 0 PACKAGE DIMENSIONS TBD A1 INDEX 10 00 0 10 10 0020 10 20 10 MAX 0 80x9 7 20 a lt gt Datum A lt 6 5 4 3 2 1 i B X X P x N MEAT OO Datum g 0 80 Q OOOO E D B O OIO O e e D 8 e Dg p _ Fs a 8 D E OOOOOO 47 F ale D G OO OO D f 0 32 0 05 TOP VIEW 7 BOTTOM VIEW 9 0 2000 A B 4G product KFM4GH6Q4M INDEX 10 00 0 10 A J 10 00 0 10 0 80x9 7 20 B x x z E TAI O x Y OO O 08 3 D ooloe J4s5 D amp es 7 g l Pg J Fa 2 4 D E OOOOOO FI D F OOOOOO
108. d DataRAM 3 3 3 Hot Reset Mode Operation See Timing Diagrams 6 17 A Hot Reset means that the host resets the device by Reset command The reset command can be either Command based or Register Based Upon receiving the Reset command the device logic stops all current operation and executes an internal reset operation and resets the current NAND Flash core operation During an Internal Reset Operation the device initializes internal registers and makes output signals go to default status The BufferRAM data is kept unchanged after Warm Hot reset operations Hot reset has no effect on contents of BootRAM and DataRAM 3 3 4 NAND Flash Core Reset Mode Operation See Timing Diagrams 6 18 The Host can reset the NAND Flash Core operation by issuing a NAND Flash Core reset command NAND Flash core reset will abort the cur rent NAND Flash core operation During a NAND Flash core reset the content of memory cells being altered is no longer valid as the data will be partially programmed or erased Flash Core Reset has an effect on neither contents of BootRAM and DataRAM register values ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 4 Write Protection Operation The Flex MuxOneNAND can be write protected to prevent re programming or erasure of data The areas of write protection are the BootRAM and the NAND Flash Array 3 4 1 BootR
109. d Write register describes the method to select the BufferRAM of DDP Device BufferRAM Select F101h default 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBS Reserved 000000000000000 Start Address2 Information Register Information Description DBS BufferRAM and Register of DDP Device BufferRAM Select gt DBS should be set to 1 when accessing the BufferRAM of the second chip MSB chip in DDP gt Since chip has 2 BufferRAMs multiplexed the BufferRAM which corresponds to the Flash core that is intended to be accessed must be selected using DBS gt Data in BufferRAM of one chip is not accessible to the Flash Core of the other chip in a DDP See Section 7 4 2 8 11 15 Start Address3 7 Register F102h F106h This Register is reserved for future use ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 8 16 Start Address8 Register F107h R W This Read Write register describes the NAND Flash start page address in a block for a page load program operation and the NAND Flash start sector address in a page for a load or program operation F107h default 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0000000 FPA FSA Start Address8 Information Description Default Value Range 0000000 1111111 7 bits for 128 pages 00 sector0 01 sector1 10 Sector2 11 sector3 NAND Flash Page Address 0000000
110. ddress F107h Block512 0200h Block513 0201h Block514 0202h Block515 0203h Block516 0204h Block517 0205h Block518 0206h Block519 0207h Block520 0208h Block521 0209h Block522 020Ah Block523 020Bh Block524 020Ch Block525 020Dh Block526 020Eh Block527 020Fh Block528 0210h Block529 0211h Block530 0212h Block531 0213h Block532 0214h Block533 0215h Block534 0216h Block535 0217h Block536 0218h Block537 0219h Block538 021Ah Block539 021Bh Block540 021Ch Block541 021Dh Block542 021Eh Block543 021Fh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block544 0220h Block545 0221h Block546 0222h Block547 0223h Block548 0224h Block549 0225h Block550 0226h Block551 0227h Block552 0228h Block553 0229h Block554 022Ah Block555 022Bh Block556 022Ch Block557 022Dh Block558 022Eh 559 022Fh Block560 0230h Block561 0231h Block562 0232h Block563 0233h Block564 0234h Block565 0235h Block566 0236h Block567 0237h Block568 0238h Block569 0239h Block570 023Ah
111. dress inputs Reset Pin When low RP resets internal operation of Flex MuxOneNAND RP status is do not care during power up and bootloading When high RP level must be equivalent to Vcc IO level Chip Enable I CE low activates internal control logic and CE high deselects the device places it in standby state CE CE1 and places DQ in Hi Z The CE input enables device for Single or DDP input enables the first DDP device KFN8GH6Q4M QDP KFKAGH6QAM Chip Enable The CE2 input enables the second device KFN8GH6QAM in QDP KFKAGH6QAM Output Enable OE low enables the device s output data buffers during a read cycle OE Power Supply VCC Core Power for Flex MuxOneNAND Core Vcc This is the power supply for Flex MuxOneNAND Core Power for Flex MuxOneNAND I O This is the power supply for Flex MuxOneNAND I O Vcc IO is internally separated from Vcc Core Vcc VSS Ground for Flex MuxOneNAND VCC IO 1 Do Not Use Leave it disconnected These pins are used for testing No Connection Lead is not internally connected NOTE Do not leave power supply Vcc Core Vcc lO VSS disconnected 10 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 5 Block Diagram BufferRAM Bootloader 1st Block OTP Block 0 AD
112. e 2 In PI Block Access mode PI update can be issued 3 Reset Flex MuxOneNAND Hot reset command makes the registers and Flash core into default state ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 8 18 1 Two Methods to Clear Interrupt Register in Command Input To clear Interrupt Register in command input user may select one from either following methods First method is to turn INT to low by manually writing 0000h to INT bit of Interrupt Register 1 Second method is to input command while INT is high and the device will automatically turn INT to low 1 Second method is equivalent with method used in general NAND Flash User may choose the desirable method to clear Interrupt Register Method 1 Manually set INT 0 before writing command into Command Register Manual INT Mode 1 Clear Interrupt Register F241h by writing 0000h into INT bit of Interrupt Register This operation will make INT pin turn low 1 2 Write command into Command Register This will make the device to perform the designated operation 3 INT pin will turn back to high once the operation is completed 1 INT pin1 INT bit Write 0 into Write command into INT will automatically turn to high INT bit of Command Register when designated operation is completed Interrupt Register NOTE 1 INT pin polarity is based on 1 and
113. e is designed to offer protection from any involuntary program erase during power transitions RP pin provides hardware protection and is recommended to be kept at ViL before Vcc drops to 1 5V tpp 1 5V Vcc mu ov RP INT Flex MuxOneNAND A Flex MuxOneNAND Logic Reset amp NAND Array Write Protected Operation ka ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 6 20 Toggle Bit Timing in Asynchronous Read VA Transition Before AVD Low See AC Characteristics Table 5 5 tRC cE X a N s gt Q OE tAso tavDO tcez WE lt gt tCA tcE lt 4 toEz A DQO 1 1 Hi Z AIDQ15 va X Status RD DX v XK Status RD tAAVDS tAAVDH AVD lt gt tAVDP E Hi Z 2 Note NOTE 1 VA Valid Read Address RD Read Data 2 Before IOBE is set to 1 RDY INT pin are High Z state 3 Refer to chapter 5 5 for tASO description and value 6 21 Toggle Bit Timing in Asynchronous Read VA Transition After AVD Low See AC Characteristics Table 5 5 tRC x N tcEz A toez tCA A DQO AIDQ15 Status RD AVD Hi Z RDY2 NOTE tAAVDS tAAVDH VA Status RD 3 Hi Z
114. e locked simultaneously for locking bit lies in the same word of OTP area 1st Block OTP can be accessed just as any other Flash Array Blocks before it is locked however once 1st Block is locked to be OTP 1st Block OTP cannot be erased or programmed Also OTP area can only be programmed once without erase capability it can be locked when the device starts up to prevent any changes from being made Locking the OTP and 1st Block OTP Programming to the OTP area and 1st Block OTP area can be prevented by locking the OTP area Locking the OTP area is accomplished by programming XXFOh to the 1st word of sector4 of main of the page49 memory area in the OTP block At device power up this word location is checked and if XXFOh is found the OTP and OTPg bit of the Controller Status Register is set to 1 indicating the OTP and 1st Block is locked When the Program Operation finds that the status of the OTP and 1st Block is locked the device updates the Error Bit of the Controller Status Register as 1 fail OTP and 1st Block OTP simultaneous Lock Operation Steps e Issue the OTP Access Command Fill data to be programmed into DataRAM data can be input at anytime between the Start and Write Program commands Write XXFOh data into the 1st word of sector4 of main of the page49 memory area of the DataRAM Issue a Flash Block Address FBA which is 0000h of NAND Flash Array address map Issue a Program command to program the data
115. ernal ECC logic Managed by internal ECC logic Managed by internal ECC logic ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Equivalent to 1word of NAND Flash Word Byte Address Address DataS 1_3 8048h 10090h BI Bad block Information 8049h 10092h 804Ah 10094h 804Bh 10096h 804Ch 10098h 804Dh 1009Ah Abit ECC parity values 804Eh 1009Ch 804Fh 1009Eh Buf Managed by internal ECC logic NOTE In case of with ECC mode Flex MuxOneNAND automatically generates ECC code for both main and spare data of memory during program operation but does not update ECC code to spare bufferRAM during load operation ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 8 Registers Section 2 8 of this specification provides information about the Flex MuxOneNAND4G registers 2 8 1 Register Address Map This map describes the register addresses register name register description and host accessibility Address word order Address byte order Name Host Access Description FOOOh 1E000h Manufacturer ID R Manufacturer identification FOO1h 1E002h Device ID Device identification F002h 1E004h
116. ersion izati rganization 1st Generation 6 x16 Organization Operating Voltage Range Page Architecture Q 1 8V 1 7 V to 1 95V 4 4KB Page ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 1 2 General Overview Flex MuxOneNAND is a monolithic integrated circuit with a Flash array using NOR Flash interface The chip integrates system features including e A BootRAM 1KB and bootloader 4KB DataRAM buffers High Speed x16 Host Interface e On chip Error Correction e On chip NOR interface controller This on chip integration enables system designers to reduce external system logic and use high density NAND Flash in applications that would otherwise have to use more NOR components Flex MuxOneNAND takes advantage of the higher performance NAND program time low power and high density and combines it with the synchronous read performance of NOR The NOR Flash host interface makes Flex MuxOneNAND an ideal solution for mobile applications that have large advanced multimedia applications and operating systems and need high performance When integrated into a Samsung Multi Chip Package with Samsung Mobile DDR SDRAM designers can complete a high performance small footprint solution The device operates up to a maximum host driven clock frequency of 66MHz 83MHz for synchronous reads at Vcc or Vccq Refer to chapter 4 2
117. es Designated as user area Manufacturer 50 63 14 pages Used by the device manufacturer Three Possible OTP Lock Sequence Refer to Chapter 3 13 3 3 13 5 for more information Since OTP Block and 1st Block OTP can be locked only by programming into 1st word of sector4 page49 of the main memory area of OTP OTP Block and 1st Block OTP lock sequence is restricted into three following cases Note that user should be careful because locking OTP Block before locking 1st Block OTP will disable locking 1st Block OTP 1 OTP Block Lock Only Once the OTP Block is locked 1st Block OTP Lock is impossible 2 1st Block OTP Lock Only Locking 1st Block OTP does not lock the OTP block but the OTP Block Lock cannot be performed thereafter 3 OTP Block Lock and 1st Block OTP Lock simultaneously This simultaneous operation can be done by programming into 1st word of sector4 page49 of the main memory area of OTP ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY OTP Block Area Structure Page 4KB 128B Sector main area 512B Manufacturer Area 14pages page 50 to page 63 One Block 64pages 256KB 8KB User Area 50pages page 0 to page 49 1st Block OTP Area Structure Page 4KB 128B Sector main area 512B lt Sector spare 16 One Block 64pages 256KB 8KB User Area 64pa
118. ex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 7 1 1 The INT Pin to a Host General Purpose I O INT can be tied to a Host GPIO to detect the rising edge of INT signaling the end of a command operation COMMAND INT Y This can be configured to operate either synchronously or asynchronously as shown in the diagrams below Synchronous Mode Using the INT Pin When operating synchronously INT is tied directly to a Host GPIO RDY could be connected as one of following guides Host Flex MuxOneNAND Host Flex MuxOneNAND CE CE CE CE AVD AVD AVD AVD CLK 7 CLK CLK CLK RDY WAIT RDY RDY OE OE OE OE GPIO INT GPIO INT Handshaking Mode Non Handshaking Mode Asynchronous Mode Using the INT Pin E um When configured to operate in an asynchronous mode AVD and OE of the Flex MuxOneNAND are tied to corresponding pins of the Host CLK is tied to the Host Vss Ground RDY is tied to a no connect OE of the Flex MuxOneNAND and Host are tied together and INT is tied to a GPIO Host Flex MuxOneNAND CE CE AVD AVD Vss CLK RDY OE OE GPIO INT ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 7 1 2 Polling the Interrupt Register Status Bit An alternate method of determining the end of an operation is to continuousl
119. ex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block768 0300h Block769 0301h Block770 0302h Block771 0303h Block772 0304h Block773 0305h Block774 0306h Block775 0307h Block776 0308h Block777 0309h Block778 030Ah Block779 030Bh Block780 030Ch Block781 030Dh Block782 030Eh Block783 030Fh Block784 0310h Block785 0311h Block786 0312h Block787 0313h Block788 0314h Block789 0315h Block790 0316h Block791 0317h Block792 0318h Block793 0319h Block794 031Ah Block795 031Bh Block796 031Ch Block797 031Dh Block798 031Eh Block799 031Fh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block800 0320h Block801 0321h Block802 0322h Block803 0323h Block804 0324h Block805 0325h Block806 0326h Block807 0327h Block808 0328h Block809 0329h Block810 032Ah Block811 032Bh Block812 032Ch Block813 032Dh Block814 032Eh Block815 032Fh Block816 0330h Block817 0331h Block818 0332h
120. fferRAM Internal Nand Array Memory Memory Boot code BootRAM 1KB Host Nand Array DataRAMO 2KB DataRAM1 2KB OTP Block The external memory is divided into a main area and a spare area Each buffer is the equivalent size of a Sector The main area data is 512B The spare area data is 16B External Memory Array Information Area BootRAM DataRAMO DataRAM1 Total Size 1KB 32B 2KB 64B 2KB 64B Number of Sectors 2 4 4 Main 512B 512B 512B Spare 16B 16B 16B Sector External Memory Array Organization Main area data Spare area data 512B 16B 7 BootRAM 0 lt Sector 512 16 Byte BootRAM l BootRAM 1 DataRAM 0 0 DataRAM 0 1 DataRAM 0 2 DataRAM 0 3 DataRAMO 4KByte DataRAM 1 0 DataRAM 1 1 DataRAM 1 2 DataRAM 1 3 ELECTRONICS DataRAM1 Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 7 Memory Map The following tables are the memory maps for the Flex MuxOneNAND 2 7 1 Internal NAND Array Memory Organization The following tables show the Internal Memory address map in word order Block Address Page Address Block Block Address Page Address F100h F107h F100h F107h Block0 0000h 0000h 00FCh Block32 0020h Block 0001h Block33 0021h Block2 0002h Block34 0022h Block3 0003h Block35 0023h Block4 0004h Blo
121. ges page 0 to page 63 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 13 1 OTP Block Load Operation An OTP Block Load Operation accesses the OTP area and transfers identified content from the OTP to the DataRAM on chip buffer thus making the OTP contents available to the Host The OTP area is a separate part of the NAND Flash Array memory It is accessed by issuing OTP Access command 65h instead of a Flash Block Address FBA value in Start Address1 Register After being accessed with the OTP Access Command the contents of OTP memory area are loaded using the same operations as a normal load operation to the NAND Flash Array memory see section 3 6 for more information To exit the OTP access mode after an OTP Block Load Operation a Cold Warm Hot or NAND Flash Core Reset operation is performed OTP Block Read Operation Flow Chart Start Write DFS FBA of Flash Write 0 to interrupt register F100h DQ DFS FBA Add F241h DQ 0000h Select DataRAM for DDP Write Load Command Add F101h DQ DBS Add F220h m 4 222 DQ 0000h Write 0 to interrupt register Add F241h DQ 0000h t Wait for INT register low to high transition Write OTP Access Comm
122. h Block866 0362h Block867 0363h Block868 0364h Block869 0365h Block870 0366h Block871 0367h Block872 0368h Block873 0369h Block874 036Ah Block875 036Bh Block876 036Ch Block877 036Dh Block878 036Eh Block879 036Fh Block880 0370h Block881 0371h Block882 0372h Block883 0373h Block884 0374h Block885 0375h Block886 0376h Block887 0377h Block888 0378h Block889 0379h Block890 037Ah Block891 037Bh Block892 037Ch Block893 037Dh Block894 037Eh Block895 227 037Fh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx Block Block Address F100h Page Address F107h Block Block Address F100h FLASH MEMORY Page Address F107h Block896 0380h Block897 0381h Block898 0382h Block899 0383h Block900 0384h Block901 0385h Block902 0386h Block903 0387h Block904 0388h Block905 0389h Block906 038Ah Block907 038Bh Block908 038Ch Block909 038Dh Block910 038Eh Block911 038Fh Block912 0390h Block913 0391h Block914 0392h
123. h 0000h 0000h N A Interrupt Status Register R W 8080h 8010h 8010h N A Start Block Address R W 0000h 0000h N A N A NAND Flash Write Protection Status R Note 5 0002h 0002h N A N A ECC Status Register 1 R Note 2 0000h 0000h 0000h N A ECC Status Register 2 R Note 2 0000h 0000h 0000h N A ECC Status Register 3 R Note 2 0000h 0000h 0000h N A ECC Status Register 4 R Note 2 0000h 0000h 0000h N A NOTE 1a RDYpol RDYconf INTpol IOBE are reset by Cold reset The other bits are reset by cold warm hot reset 1b The other bits except OTPL and OTPBL are reset by cold warm hot reset 2 ECC Status Register 1 4 are reset when any command is issued 3 Refer to Device ID Register FOO1h 4 Resetting during IDLE state this is valid But resetting during BUSY state refer to Chapter 2 8 21 5 To read NAND Flash Write Protection status Block Address register must be written before ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 3 1 Cold Reset Mode Operation See Timing Diagram 6 15 At system power up the voltage detector in the device detects the rising edge of Vcc and releases an internal power up reset signal This trig gers boot code loading Bootcode loading means that the boot loader in the device copies designated sized data 1KB from the beginning of memory i
124. h transition Add F241h DQ 15 INT Read Controller Status Register Add F240h DQ 10 0 Pass Y OTP Programming completed Y DQ 14 1 Lock DQ 10 1 Error Update Controller Status Register Add F240h Wait for INT register low to high transition Add F241h DQ 15 INT Do Cold Warm Hot INAND Flash Core reset Y OTP Exit 1 FBA NAND Flash Block Address could be omitted or any address 2 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 3 Data input could be done anywhere between Start and Write Program Command 4 FBA must be 0000 5 FSA must be 00 within program operation 6 BSA must be 1000 and BSC must be 000 Read Controller Status Register Add F240h DQI10 1 Error Y Do Cold Warm Hot INAND Flash Core reset Y OTP Exit ELECTRONICS 96 Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 13 3 OTP Block Lock Operation Even though the OTP area can only be programmed once without erase capability it can be locked when the device starts up to prevent any changes from being made Unlike the main area of the NAND Flash Array memory once the OTP block is locked it cannot be unlocked for locking bit for both blo
125. ion Load operation Operation ECC Code Update to ECC Code at BufferRAM Spare ECC Status amp Result Update 1bit 4bit Flash Array Spare Area Area to Registers Error ECC operation Update Pre written ECC code loaded Update Correct ECC bypass Not update Pre written code loaded Invalid Not correct NOTE 1 Pre written ECC code ECC code which is previously written to NAND Flash Spare Area in program operation ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 16 Invalid Block Operation Invalid blocks are defined as blocks in the device s NAND Flash Array memory that contain five or more invalid bits which cause status failure during Program and Erase operation The information regarding the invalid block s is called the Invalid Block Information Devices with invalid block s have the same quality level as devices with all valid blocks and have the same AC and DC characteristics An invalid block s does not affect the performance of valid block s because it is isolated from the bit line and the common source line by a select transistor The system that adopts Flash memory must be able to mask out the invalid block s by software The 1st block is always fully guaranteed to be a valid block by an internal ECC engine Due to invalid marking during load operation for indentifying invalid block a load error
126. ior to current erase ongoing 3 Final Erase Status Check NOTE 1 Erase Suspend and Erase Resume Operations are not supported in Erase Interleave DDP 83 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 11 2 Erase Suspend Erase Resume Operation The Erase Suspend Erase Resume Commands interrupt and restart a Block Erase operation so that user may perform another urgent opera tion on the block that is not being designated by Erase Operation Erase Suspend During a Block Erase Operation When Erase Suspend command is written during a Block Erase operation the device requires a maximum of 500us to suspend erase opera tion Erase Suspend Command issue during Block Address latch sequence is prohibited After the erase operation has been suspended the device is ready for the next operation including a load program Lock Unlock Lock tight Hot Reset NAND Flash Core Reset Command Based Reset or OTP Access The subsequent operation can be to any block that was NOT being erased A special case arises in Erase Suspend operation pertaining to the OTP A Reset command is used to exit from the OTP Access mode If the Reset triggered exit from the OTP Access Mode happens after an Erase Suspend Operation the erase routine could fail Therefore to exit from the OTP Access Mode without causing the erase suspend resume operation to fail a NAND
127. is reserved as a One Time Programmable Block memory area Also 1st Block of NAND Flash Array can be used as OTP OTP area and 1st block OTP area must be utilized as a SLC block The OTP block can be read programmed and locked using the same operations as any other NAND Flash Array memory block OTP block cannot be erased Note that Cache program and Finish Cache program cannot be performed on OTP and 1st Block OTP area OTP block is fully guaranteed to be a valid block by an internal ECC engine Entering the OTP Block The OTP block is separately accessible from the rest of the NAND Flash Array by using the OTP Access command instead of the Flash Block Address FBA Exiting the OTP Block To exit the OTP Access Mode a Cold Warm Hot or NAND Flash Core Reset operation is performed Exiting the OTP Block during an Erase Operation If the Reset triggered exit from the OTP Access Mode happens during an Erase Suspend Operation the erase routine could fail Therefore to exit from the OTP Access Mode without suspending the erase operation a Flash Core Reset command should be issued The OTP Block Page Assignment OTP area is one block size 128KB 4KB 64 Pages and is divided into two areas The 50 page User Area is available as an OTP storage area The 14 page Manufacturer Area is programmed by the manufacturer prior to shipping the device to the user OTP Block Page Allocation Information Area Page Use User 0 49 50 pag
128. it into DataRAMO DataRAM1 Current Start address FPA is automatically incresed by 4KB unit after the load 4 0000h Data is Manufacturer ID Chip1 only in case of DDP 0001h Data is Device ID Chip1 only in case of DDP 0002h gt Current Block Write Protection Status Chip1 only in case of DDP 5 WE toggling can terminate Read Identification Data operation ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 1 1 Reset Flex MuxOneNAND Command The Reset command is given by writing OOFOh to the boot partition address Reset will return all default values into the device 3 1 2 Load Data Into Buffer Command Load Data into Buffer command is a two cycle command Two sequential designated command activates this operation Sequentially writing 00 0000h to the boot partition O000h 01FFh 8000h 800Fh will load one page to DataRAMO and DataRAM1 This operation refers to FBA FSA must be 00 and BSA must be 1000 At the end of this operation FPA will be automatically increased by 1 So continuous issue of this command will sequentially load data in next page to DataRAMO DataRAM1 This page address increment is restricted within a block The default value FBA and is 0 Therefore initial issue of this command after power on will load the first page of memory which is usu ally boot code 3 1 3 Read Identification Data Command
129. k tight Note 1 tLock All Block Unlock Time Note 1 tABU Erase Suspend Time Note 1 tESP Erase Resume Time Note 1 tERS1 Number of Partial Program Cycles in the page Including main and NOP SLC spare area MLC Block Erase time Note 1 tBERS1 NOTE 1 These parameters are tested based on INT bit of interrupt register Because the time on INT pin is related to the pull up and pull down resistor value 5 10 AC Characteristics for INT Auto Mode See Timing Diagram 6 22 Parameter Symbol Min Max Unit Command Input to INT Low tws 200 ns ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx 6 0 TIMING DIAGRAMS 6 1 8 Word Linear Burst Read Mode with Wrap Around See AC Characteristics Table 5 4 FLASH MEMORY LL BRWLAA ________ R tces tCLKL ls l tcez 4 2 4 lt gt SER III OOGO O nuns tRDYO AVD X tAVDO RE tt tAVDH lt tacs ya po X D7 X T D2 X 00 tacH toEz lt Ec m k Hi Z IRDYA 16 3 SUUM T Hi Z RDY N 6 2 Continuous Linear Burst Read Mode with Wrap Around See AC Characteristics Table 5 4
130. lity 4 2 Operating Conditions Voltage reference to GND KFM4GH6Q4M Typ Parameter Symbol Vcc core Vcc 1 8 Supply Voltage Vcc IO Vss NOTE 1 Vcc Core or Vcc should reach the operating voltage level prior to or at the same time as Vcc IO Vccq ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 4 3 DC Characteristics RMS Value Typ Parameter Test Conditions Input Leakage Current Vin Vss to Vcc Vour Vss to Vcc or OE ViH Note 1 Output Leakage Current Active Asynchronous Read Current Note 2 CE VIL OE VIH Active Burst Read Current Note 2 CE VIL OE VIH WE ViH Active Burst Write Current Note 2 CE VIL OE VIH WE VIL Active Asvnchronous Write Current Note 2 CE VIL OE ViH Active Load Current Note 3 CE VIL OE VIH WE VIH Active Program Current Note 3 CE VIL OE VIH WE VIH Active Erase Current Note 3 CE VIL OE VIH WE VIH Standby Current RP Vcc 0 2V Input Low Voltage Input High Voltage Note 4 Output Low Voltage lol 100 uA Vcc Vccmin Vccq Vccamin Output High Voltage 100 pA Vcc Vccmin VcCq VCCqmin NOTE 1 CE should be for RDY I
131. lock is unlocked 1 current Flash block is locked Locked Status Or First Block of NAND Flash Array is Locked to be OTP Locked Tight Status 1 current NAND Flash block is locked tight ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 2 8 26 ECC Status Register 1 FF00h This Read register shows the Error Correction Status The Flex MuxOneNAND can correct up to 4 bit errors ECC can be performed on the NAND Flash main and spare memory areas The ECC status register can also show the number of errors in a sector as a result of an ECC check in during a load operation ECC status bits are also updated during a boot loading operation FFOOh default 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ER1 Reserved ERO 2 8 27 ECC Status Register 2 FF01h FFO1h default 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ER3 Reserved ER2 2 8 28 ECC Status Register 3 FF02h R FFO2h default 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ER5 Reserved ERA 2 8 29 ECC Status Register 4 FFO3h FFO3h default 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ER7 Reserved ER6 Error Status ECC Status No Error 1bit error correctable 2bit error correctable 3bit error correctable 4bit error correctable Uncorrectable ECC location I
132. lock264 0108h Block265 0109h Block266 010Ah Block267 010Bh Block268 010Ch Block269 010Dh Block270 010Eh Block271 010Fh Block272 0110h Block273 0111h Block274 0112h Block275 0113h Block276 0114h Block277 0115h Block278 0116h Block279 0117h Block280 0118h Block281 0119h Block282 011Ah Block283 011Bh Block284 011Ch Block285 011Dh Block286 011Eh Block287 011Fh ELECTRONICS SLC 0000h 00FCh MLC 0000h 01FCh Block288 0120h Block289 0121h Block290 0122h Block291 0123h Block292 0124h Block293 0125h Block294 0126h Block295 0127h Block296 0128h Block297 0129h Block298 012Ah Block299 012Bh Block300 012Ch Block301 012Dh Block302 012Eh Block303 012Fh Block304 0130h Block305 0131h Block306 0132h Block307 0133h Block308 0134h Block309 0135h Block310 0136h Block311 0137h Block312 0138h Block313 0139h Block314 013Ah Block315 013Bh Block316 013Ch Block317 013Dh Block318 013Eh Block319 18 013Fh SLC 0000h 00FCh MLC 0000h 01FCh Flex MuxOneNAND4G KFM4GH6
133. m 0 1 0 1 0 1 Reset during Program Erase Load 0 1 0 1 0 1 Program Erase to the locked block Load to the BootRAM 0 1 OTP Program Fail Lock 0 1 OTP Program Fail 0 1 NOTE 1 1 for Pl Block Lock for Block Unlock 2 1 for 1st Block OTP Lock for 1st Block OTP Unlock 3 1 for OTP Block Lock 0 for OTP Block Unlock 4 After Finish Cache Program operation pass fail status of Current Cache Program and Previous Cache Program will be updated 2 8 22 Interrupt Status Register F241h R W This Read Write register shows status of the Flex MuxOneNAND interrupts F241h defaults 8080h after Cold Reset 8010h after Warm Hot Reset 10 2 1 Reserved 0000000 Reserved 0000 Interrupt INT This is the master interrupt bit The INT bit is wired directly to the INT pin on the chip Upon writing 0 to the INT bit the INT pin goes low if INTpol is high and goes high if INTpol is low INT Interrupt 15 Default State Interrupt Cold Warm hot Function 1 1 off Status Conditions Commands in the command table in page43 Refer sets itself to 1 to Chapter 2 8 18 are completed Pending 0 is written to this bit Cold Warm Hot reset is being performed or command is written to Command Register in INT auto mode clears to 0 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8
134. may occur 3 16 1 Invalid Block Identification Table Operation A system must be able to recognize invalid block s based on the original invalid block information and create an invalid block table Invalid blocks are identified by erasing all address locations in the NAND Flash Array memory except locations where the invalid block s infor mation is written prior to shipping An invalid block s status is defined by the 1st word in the spare area Samsung makes sure that the first page in the block either SLC partition MLC partition of every invalid block has non FFFFh data at the 1st word of sectorO of pages 0 or 1 the spare area Since the invalid block information is also erasable in most cases it is impossible to recover the information once it has been erased Any intentional erase of the original invalid block information is prohibited The following suggested flow chart can be used to create an Invalid Block Table ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Invalid Block Table Creation Flow Chart Start v Set Block Address 0 Increment Block Address A Check FFFFh at the 1st word of sector 0 Y of spare area in the first page in the block Create or update No Check pnr SLC partition or MLC partition Invalid Block s Table FFFFh Yes No Las
135. moved to BootRAM automatically and then fetched by CPU through the same interface as SRAM s NOR Flash s if the size of the boot code is less than 1 If its size is larger than 1KB and less than or equal to 3KB only 1KB of it can be moved to BootRAM automatically and fetched by CPU and the rest of it can be loaded into one of the DataRAMs whose size is 2KB by Load Command and CPU can take it from the DataRAM after finishing the code fetch ing job for BootRAM If its size is larger than 3KB the 1KB portion of it can be moved to BootRAM automatically and fetched by CPU and its remaining part can be moved to DRAM through two DataRAMs and taken by CPU to reduce CPU fetch time A typical boot scheme usually used to boot the system with Flex MuxOneNAND is explained at Partition of NAND Flash Array and Flex Mux OneNAND Boot Sequence In this boot scheme boot code is comprised of BL1 where BL stands for Boot Loader BL2 and BL3 Moreover the size of the boot code is larger than 3KB the 3rd case above BL1 is called primary boot loader in other words Here is the table of detailed explanations about the function of each boot loader in this specific boot scheme 7 2 1 Boot Loaders in Flex MuxOneNAND Boot Loaders in Flex MuxOneNAND Boot Loader Description BL1 Moves BL2 from NAND Flash Array to DRAM through two DataRAMs BL2 Moves OS image or BL3 optionally from NAND Flash Array to DRAM through two DataRams BL3 Optional Moves or wri
136. n FLASH MEMORY Therefore using hardware ECC of Flex MuxOneNAND accumulation of 4 bit error can be avoided Copy Back Program Operation with Random Data Input will be effectively utilized at modifying certain bit byte word or sector of source page to destination page while it is being copied Copy Back Program Operation with Random Data Input Flow Chart NOTE Start v Write DFS FBA of Flash Add F100h DQ DFS FBA v Select DataRAM for DDP Add F101h DQ DBS v Read ECC Status Register1 Write System Configuration ett kabel iii APSE Register Add FF00h DQ ER1 12 8 ERO 4 0 v Read ECC Status Register2 Y Y Write FPA FSA of Flash Add F107h DQ FPA FSA Y Write BSA BSC DataRAM Write System Configuration F Write 0 to interrupt register Register Add F221h DQ ECC 22222 Add F241h DQ 0000h rus Write Load Command Add F220h DQ 0000h Wait for INT register low to high transition Add F241h DQ 15 INT Read ECC Status Register3 Add FF02h DQ ER5 12 8 ER4 4 0 Y Read ECC Status Register4 Add FF03h DQ ER7 12 8 ER6 4 0 1 1000 FSA must be 00 BSC must be 000 within program operation 2 3
137. n a Cold Warm Hot Flash Core Reset operation is performed PI Block Read Operation Flow Chart In Block Access Mode Start Y Write DFS FBA of Flash Write 0 to interrupt register 77 Add F100h DQ DFS i Add F241h DQ 0000h _ Select DataRAM for es Add F101h DQ DBS Add F220h Y DQ 0000h Write 0 to interrupt register Add F241h DQ 0000h L Q Wait for INT register 4 low to high transition Write PI Access Command Add 241 DQO ISISINT Add F220h DQ 0066h v Y Host reads data from Wait for INT register DataRAM low to high transition se ee E s OX Add F241 DQITSISINT Reading completed v NAE po tari oe INAND Flash Core Reset Y PI Block Access mode exit Y Write BSA BSC of DataRAM P mam Add F200h 00 BSC V K D DBS DFS is for DDP NOTE 1 FBA NAND Flash Block Address could be omitted or any address 2 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 3 BSA must be 1000 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 13 OTP Operation SLC only One Block of the NAND Flash Array memory
138. nformation Definition Error status of 1st selected sector Main and Spare area Error status of 2nd selected sector Main and Spare area Error status of 3rd selected sector Main and Spare area Error status of 4th selected sector Main and Spare area Error status of 5th selected sector Main and Spare area Error status of 6th selected sector Main and Spare area Error status of 7th selected sector Main and Spare area Error status of 8th selected sector Main and Spare area ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 0 DEVICE OPERATION This section of the data sheet discusses the operation of the Flex MuxOneNAND device It is followed by AC DC Characteristics and Timing Diagrams which may be consulted for further information The Flex MuxOneNAND supports a limited command based interface in addition to a register based interface for performing operations on the device 3 1 Command Based Operation Flex OneNAND supports a limited command based interface The address range of BootRAM 0000h 01FFh 8000h 800Fh called the Boot Partition is actually a read only area This is because it contains bootloader code which must not be overwritten Therefore any attempt of data write to the Boot Partition is interpreted by Flex OneNAND as a Command based operation Commands can only
139. nlock lock tight Command Add F220h DQ 002Ah 0023h 002Ch Wait for register low to high transition Add F241h DQ 15 INT Read Controller Status Register Add F240h DQ 10 Error Dano YES NO LockUnlockLock Tight l Error completed J Samsung strongly recommends to follow the above flow chart NOTE 1 Write 0 to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 DBS DFS is for DDP ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY All Block Unlock Flow Diagram NOTE 1 Write 0 to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 Start Write DFS of Flash Add F100h DQ DFS v Select DataRAM for DDP Add F24Ch DQ SBA 000h Y Gi Write 0 to interrupt register Add F241h DQ 0000h Write Block Unlock Command Add F220h DQ 0027h Wait for INT register low to high transition Add F241h DQ 15 INT Read Controller Status Register Add F240h DQ 10 Error DBS DFS is for DDP YES All Block Unlock completed 2 All Block Unlock command fails if there are lock tight blocks in
140. notify the Host when a command has been completed This provides a hard ware method of signaling the completion of a program erase or load operation In its normal state the INT pin is high if the INT polarity bit is default In case of normal INT mode before a command is written to the com mand register the INT bit must be written to 0 for the INT pin transitions to a low state indicating start of the operation In case of INT auto mode INT bit is written to 0 automatically right after command issued Upon completion of the command operation by the Flex Mux OneNAND s internal controller INT returns to a high state INT pin is a DQ type output except Reset and Interleave Cache program in DDP allowing two INT outputs to be Or tied together In case of Reset and Interleave Cache Program in DDP INT pin operates as an open drain with 50K ohm INT is an INT does not float to a hi Z condi tion when CE is disabled or OE is disabled Refer to section 2 8 for additional information about INT INT can be implemented by tying INT to a host GPIO or by continuous polling of the Interrupt status register INT Type Mono INT Type DDP General Operation DQ type DQ type Reset Operation Cold Warm Hot and Flash Core Reset and final command of Interleave cache program DQ type Open drain with 50K ohm ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Fl
141. nto the BootRAM This sequence is the Cold Reset of Flex MuxOneNAND The POR Power On Reset triggering level is typically 1 5V Boot code copy operation activates 400us after POR Therefore the system power should reach 1 7V within 400us from the POR triggering level for bootcode data to be valid It takes approximately 250us to copy 1KB of boot code Upon completion of loading into the BootRAM it is available to be read by the host The INT pin is not available until after IOBE 1 and IOBE bit can be changed by host 3 3 2 Warm Reset Mode Operation See Timing Diagrams 6 16 A Warm Reset means that the host resets the device by using the RP pin When the a RP low is issued the device logic stops all current oper ations and executes internal reset operation and resets current NAND Flash core operation synchronized with the falling edge of RP During an Internal Reset Operation the device initializes internal registers and makes output signals go to default status The BufferRAM data is kept unchanged after Warm Hot reset operations The device guarantees the logic reset operation in case RP pulse is longer than tRP min 200ns The device may reset if tRP tRP min 200ns but this is not guaranteed Warm reset will abort the current NAND Flash core operation During a warm reset the content of memory cells being altered is no longer valid as the data will be partially programmed or erased Warm reset has no effect on contents of BootRAM an
142. or outputs are disabled Interrupt Notifies the Host when a command is completed After power up it is at hi z condition Once IOBE is set to 1 it does not float INT INT1 to hi z condition even when CE is disabled or OE is disabled Especially only when reset Cold Warm Hot NAND Flash Core command in DDP are issued it operates as open drain output with internal resistor 50Kohm The INT is the interrupt for Single or DDP device INTI is the interrupt for the first DDP device KFN8GH6Q4M QDP KFKAGH6QAM Interrupt The INT2 is the interrupt for the second device KFN8GH6Q4M QDP KFKAGH6QAM Ready __ Indicates data valid synchronous read modes and is activated while is low Clock CLK synchronizes the device to the system bus frequency in synchronous read mode The first rising edge of CLK in conjunction with AVD low latches address input Write Enable __ WE controls writes to the bufferRAM and registers Datas are latched on the WE pulse s rising edge Address Valid Detect Indicates valid address presence on address inputs During asynchronous read operation all addresses are valid while AVD is low and during synchronous read operation all addresses are latched on CLK s rising edge while AVD is held low for one clock cycle Low for asynchronous mode indicates valid address for burst mode causes starting address to be latched on rising edge on CLK High device ignores ad
143. ow Chart revised ELECTRONICS NOOR N Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 1 0 INTRODUCTION This specification contains information about the Samsung Electronics Company Flex MuxOneNAND Flash memory product family Sec tion 1 0 includes a general overview revision history and product ordering information Section 2 0 describes the Flex MuxOneNAND device Section 3 0 provides information about device operation Electrical specifications and timing waveforms are in Sections 4 0 through 6 0 Section 7 0 provides additional application and technical notes pertaining to use of the Flex MuxOneNAND Package dimensions are found in Section 8 0 Density Part No Vcc core amp IO Temperature PKG 4Gb KFM4GH6Q4M DEBx 1 8V 1 7V 1 95V Extended 63FBGA LF 8Gb KFN8GH6Q4M DEBX 1 8V 1 7V 1 95V Extended 63FBGA LF 16Gb TBD KFKAGH6Q4M DEBX 1 8V 1 7V 1 95V Extended 63FBGA LF 1 1 Ordering Information KFx xH6Q4M Samsung OneNAND Memory Speed 6 66MHz lo Im Ix Ix Device Type 8 83MHz type Single Chip N Mux type Dual Chip Product Line designator K Mux type Quad Chip B Include Bad Block Density 4G 4Gb 8G 8Gb Operating Temperature Range AG 16Gb TBD E Extended Temp 30 C to 85 C Package Technology D FBGA Lead Free H Flex V
144. ower up and PI Update operation this word is updated internally If 3XXXh is found i e the status of PI is locked Program Erase operations to block result in an error and the device updates the Error Bit of the Controller Status Register as 1 fail NOTE 1 Only the 1st word of 1st page of PI block PI block Boundary Information can be programmed in PI Block The rest of the block cannot be programmed 2 FBA NAND Flash Block Address must be 0000h 3 FPA must be 00h and FSA must be 00 4 BSA must be 1000 and BSC must be 000 5 Write 0 to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 12 1 4 Update Once new partition information is programmed into the PI block an internal register that is invisible to users must be updated for the changes PI to be applied This internal register which stores partition information i e the last address of SLC area and lock bits will be automatically updated through cold reset However the internal register can also be updated by issuing Partition Information Update command 05h after PI Access mode entry Update the Area e Issue the Access mode Refer to Chapter 3 12 1 1 e Issue the update command PI Block Update In PI Block Access Mode Start Y Write DFS FB
145. peration Flow Chart Start D Write FBA ofFlash M Add F100h v Write DFS FBA of Flash Wite FPA ESA F100h DQ DFS _ OLTA Add F107h DQ 0196h2 Y Y Add F1015 8 Write BSA BSC of DataRAM Add F200h DQ 0800n9 qm 07 i Write 0 to interrupt register pouce M Add F241h DQ 0000h Write 0 to interrupt register irc E Add F241h DQ 0000h Y L Pat 2 3 Write Access Command X Add F220h DQ 0065h Write Program command Add F220h v Wait for INT register DQ 0080n low to high transition Add F241h DQ 15 INT Wait for INT register J low to high transition 3 Add F241h DQ 15 INT Write Data into DataRAM Add istWord 0 00 sector4 main0 page49 DQ XXFCh Locking bit Do Cold reset updated Automatically Update Controller Status Register Add F240h DQ 6 1 OTPL DBS DFS is for DDP C OTP lock completed NOTE 1 FBA NAND Flash Block Address could be omitted or any address 2 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 3 Data input could be done anywhere between Start and Write Program Command 4 FBA must be 0000 5 FSA must be 00 within program operation
146. ram operation Write mu Add F241h DQ 8040h results in an error Add F220h DQ 0080h map out the block Read Controller including the page in ___ Status Register error and copy the Add F240h DQ 10 Error target data to another LA block Program Error 27 NOTE 1 DBS must be set before data input 2 FSA must be 00 and BSC must be 000 within program operation 3 BSA must be 1000 4 Writing System Configuration Register is optional 5 Host is strongly recommended to see the INT register F241h of each chip 6 Once PGM command is issued onto a chip the same command PGM must be issued onto another chip If not Samsung cannot gurantee the following oper ation T If error bit is set at this step DQ 1 4 shoulde be checked in order to find where the error occurred ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx 3 10 Copy Back Program Operation with Random Data Input The Copy Back Program Operation with Random Data Input in Flex MuxOneNAND consists of 3 phases Load data into DataRAM Modify data and program into designated page Data from the source page is saved in one of the on chip DataRAM buffers and modified by the host then programmed into the destination page As shown in the flow chart data modification is possible upon completion of load operation ECC is also available at the end of load operatio
147. rogram operation 3 BSA must be 1000 4 Writing System Configuration Register is optional 5 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 ELECTRONICS 78 Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 9 2 Interleave Cache Program Operation The Interleave Cache Program is available only on DDP Host can write data on a chip while programming another chip with this operation Interleave Cache Program is executing as following 1 4KB Data are written from host to DataRAMs in Chip1 2 Cache Program command issue This will turn INT bit to busy state OnGo bit sets to 1 Note that before issuing Interleave Cache Program Command host should make sure that the target blocks are unlocked 3 4KB data will be sequentially transferred to each page buffer in NAND Flash Array 4 While these data are transferring Host can write another 4KB Data to DataRAM in Chip2 5 When the transfer operation is completed programming into NAND Flash Array will automatically start and at the same time INT bit will turn to 1 to indicate that DataRAMs are now ready to be written with next 4KB data 6 Second 4KB is writable on Chip1 when INT1 goes to 1 7 When second 4 is written to two DataRAMs of Chip1 another Cache Program command is issued and INTI bit will go to
148. rst mode the latency is determined by the host based on the BRWL bit setting in the System Configuration 1 Register The default BRWL is 4 latency cycles At clock frequencies of 40MHz or lower latency cycles can be reduced to 3 at frequency range from 40MHz to 66MHz latency cycle should be over 4 Over clock frequency of 66MHz latency cycle should be over 6 For BufferRAMs both Start Initial Burst Write and Burst Write is supported Refer to Chapter 3 2 However for Register Access only Start Initial Burst Write is supported Therefore Synchronous Burst Write on Register is prohibited Refer to Chapter 3 2 and 6 8 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 9 Program Operation See Timing Diagrams 6 11 The Program operation is used to program data from the on chip BufferRAMs into the NAND FLASH memory array The device has two 2KB data buffers 1 Page 4KB 128B in size A page has 8 sectors of 512B each main area and 16B spare area The device can be programmed in units of 8 sectors at once Addressing for program operation Within a block the pages must be programmed consecutively from the LSB least significant bit page of the block to MSB most significant bit pages of the block Random page address programming is prohibited Once users start to write data on a certain page the page is a LSB page therefore LSB page
149. s 6 6 6 7 and 6 8 Parameter Symbol 5 5 Clock CLK Clock Cycle E Setup to tavps AVD Hold Time from CLK Address Setup Time to tacs Address Hold Time from CLK Data Setup Time to twos Data Hold Time from CLK WE Setup Time to twes NOI OO N a WE Hold Time from CLK 6 High Low Time 3 N CE high pulse width 10 CLK to RDY Valid 11 CLK to RDY Setup Time 11 RDY Setup Time to troys CE low to RDY valid tcer 15 15 Clock to CE disable 4 5 4 5 CE Setup Time to tces CE Disable to Output amp RDY High Z NOTE 1 Target Clock frequency is 83Mhz ELECTRONICS tcez 113 20 20 Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 5 9 AC Characteristics for Load Program Erase Performance See Timing Diagrams 6 9 6 10 6 11 6 12 6 13 and 6 14 Parameter Sector Load time Note 1 Page Load time Note 1 Page Program time Note 1 OTP Access Time Note 1 torP Lock Unlock Loc
150. sector4 main of the page49 Do Cold reset DQ XXFOh Automaticallv updated Update Controller Status Register Add F240h DQ 5 1 OTPBL DQ 6 1 OTPL p and 1st Block OTP lock completed DBS 5 is for DDP NOTE 1 FBA NAND Flash Block Address could be omitted or any address 2 Write O to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 3 Data input could be done anywhere between Start and Write Program Command 4 FBA must be 0000 5 FSA msut be 00 within program operation The 0196h is the page49 of NAND Flash Array address map 6 BSA msut be 1000 and BSC must be 000 ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 14 DQ6 Toggle Bit The Flex MuxOneNAND device has DQ6 Toggle bit Toggle bit is another option to detect whether an internal load operation is in progress or completed Once the BufferRAM BootRAM DataRAMO DataRAM1 is at a busy state during internal load operation DQ6 will toggle Toggling DQ6 will stop after the device completes its internal load operation The Flex MuxOneNAND device s DQ6 Toggle will be valid only when host reads BufferRAM which will be loaded by internal load operation DQ6 toggle can be used 350ns after load command 0000h of Command based Operation issue until data sensing from the NAND
151. signal polarity 0 low for ready INT Polarity INTpol Information 6 INT bit of Interrupt Status Register INT Pin output 0 busy High 1 ready Low 0 busy Low 1 ready High 4 default ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Buffer Enable IOBE is the I O Buffer Enable for the INT and RDY signals At startup INT and RDY outputs are High Z Bits 6 and 7 become valid after IOBE is set to 1 can be reset by a Cold Reset or by writing 0 to bit 5 of System Configuration1 Register Buffer Enable Information 5 Definition Description I O Buffer Enable for INT and 0 disable default RDY signals 1 enable RDY Configuration RDY conf RDY Configuration Information 4 Item Definition Description O active with valid data default REY conf RDY configuration 1 active one clock before valid data HF Enable HF Description HF Disable default under 66MHz HF Enable over 66MHz HF Information 2 Definition Description Selects between HF Disable and HF Enable High Frequency ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Write Mode WM Write Mode Asynchronous Write default Synchronous Write Write Mode Inform
152. t WE 7 twPH RD1 or tRD2 lt twc CLK VIL INT bit tcez 0 tcez lt gt Hi Z RDY L ee NOTE 1 AA Address of address register CA Address of command register LCD Load Command LMA Address of memory to be loaded BA Address of BufferRAM to load the data SA Address of status register 2 In progress and complete refer to status register 3 Status reads in this figure is asynchronous read but status read in synchronous mode is also supported ELECTRONICS FLASH MEMORY See AC Characteristics Table 5 7 and Table 5 9 Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx 6 10 Superload Operation Timing Superload Operation Timing Diagram pees snuouuou s Ajuo JAVHEJEQ ped JSOH uju 1s Pea soH SI Bursues 10025 Jo eseo ul s Bursues eseo peuouBi eq 49381691 1dnuueju o 0 ojne NI Ul 000 uju puz 40000 Buas 1s pue sad sJa peoi 10 sseuppy sseuppy uju s umes Sumos Woy ae speaJ JSOH L U spe i S uju u z
153. t Block m 3 16 2 Invalid Block Replacement Operation Within its life time additional invalid blocks may develop with NAND Flash Array memory Refer to the device s qualification report for the actual data The following possible failure modes should be considered to implement a highly reliable system In the case of a status read failure after erase or program a block replacement should be done Program status failure during a page program does not affect the data of the other pages in the same block within a SLC partition while Progrm status failure could contaminate the data of the paired page within a MLC partition So users must make sure how software handle the program failure occurrs Block Failure Modes and Countermeasures Failure Mode Detection and Countermeasure sequence Erase Failure Status Read after Erase gt Block Replacement Program Failure Status Read after Program gt Block Replacement Four Bit Failure in Load Operation Error Correction by ECC mode of the device ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Referring to the diagram for further illustration when an error happens the nth page of block A during program operation copy the data in the 1st n 1 th page to the same location of block B via DataRAM Then re program the nth page to the nth page of block B or any free block
154. taM 0 2 DataRAM Main nth page sector2 DataM 0 3 DataRAM Main nth page sector3 DataM 1 0 DataRAM Main nth page sector4 DataM 1 1 DataRAM Main nth page sector5 DataM 1 2 DataRAM Main nth page sector6 DataM 1 3 DataRAM Main nth page sector7 0A00h 7FFFh 01400h 0FFFEh 59K Reserved Reserved Spare area 8KB 8000h 8007h 10000h 1000Eh 16B 8008h 800Fh 10010h 1001Eh 16B BootS 0 BootRAM Spare blockO pageO sectoro BootS 1 BootRAM Spare blockO pageO sectori 8010h 8017h 10020h 1002Eh 16B 8018h 801Fh 10030h 1003Eh 16B 8020h 8027h 10040h 1004Eh 16B 8028h 802Fh 10050h 1005Eh 16B 8030h 8037h 10060h 1006Eh 16B 8038h 803Fh 10070h 1007Eh 16B 8040h 8047h 10080h 1008Eh 16B 8048h 804Fh 10090h 1009Eh 16B DataS 0_0 DataRAM Spare nth page sectorO DataS 0 1 DataRAM Spare nth page sector1 DataS 0 2 DataRAM Spare nth page sector2 DataS 0 3 DataRAM Spare nth page sector3 DataS 1 0 DataRAM Spare nth page sector4 DataS 1 1 DataRAM Spare nth page sector5 DataS 1 2 DataRAM Spare nth page sector6 DataS 1 3 DataRAM Spare nth page sector7 8050h 8FFFh 100A0h 11FFEh 8032B Reserved Reserved Reserved 24
155. tatus Default 1st Block OTPLock Status Disable 1st Block OTP Program Erase Previous Cache Program status Previous This bit shows the previous program status of Cache Program This value is invalid only at the first Read Controller Status Register step of Cache Program operation Refer to 6 12 and 6 13 Previous 2 Previous Status of previous program Pass Fail Current Cache Program Status Current This bit shows the current program status only at Final Cache Program Current Information 1 Current Status of current program Pass Fail Time Out TO This bit determines if there is a time out for load program and erase operations It is fixed at time out TO Information 0 Definition Description Time Out 0 no time out ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Controller Status Register Output Modes Controller Status Register 15 0 13 12 9 8 7 6 5 4 3 2 11 2 1 Reserved ved PIL OTPB 3 Reserved Previous Current ved OTPL Operation Ongoing 0 1 0 1 0 1 Operation OK 0 1 0 1 0 1 Operation Fail 0 1 0 1 0 1 Program fail on Cache Program 0 1 0 1 0 1 Previous program fail during Cache Program 0 1 0 1 0 1 Program fail after Finish Cache Progra
156. tes the image through USB interface Flash Array Flex MuxOneNAND is divided into the partitions as described at Partition of Flash Array to show where each component of code is located and how much portion of the overall NAND Flash Array each one occupies In addition the boot sequence is listed below and depicted at Boot Sequence 7 2 2 Boot Sequence Boot Sequence 1 Power is on BL1 is loaded into BootRAM 2 BL1 is executed in BootRAM BL2 is loaded into DRAM through two DataRams by BL1 3 2 is executed in DRAM OS image is loaded into DRAM through two DataRams by BL2 4 OS is running ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Block 1023 A Reservoir Partition 6 x Sector0 Sector Sector2 Sector3 Sector4 Sector5 Sector6 Sector7 File System Partition 5 X Page 63 Page 62 Block 162 N l m Block 2 Page 2 BL3 Block 1 1 BL2 Page 0 Block 0 BAN g Partition of NAND Flash array Reservoir 2 File System step 3 DataRam 4KB x 222 12 Boot Ram BL 1 2 step 1 Step2 Flash
157. th 50K ohm for Reset Cold Hot Warm NAND Flash Core operations and Cache program operation case at DDP option the pull up resis tor value is related to tr INT And appropriate value can be obtained with the following reference charts INT pol High Default Vcc Ready Vcc Lem Busy State tf tr 4 KFN8GH6Q4M Vcc 1 8V Ta 25 C 30pF lt gt 5 x 2 1K 10K 20K 30K 40K 50K Open 100K Rp ohm ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY INT pol Low Vcc or Vccq tr Ready ci e rox Vcc Busy State KFN8GH6QAM Vcc 1 8V Ta 25 C 30pF tr tf Ibusy mA tr ns 1K 10K 20K 30K 40K 50K Open 100K ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 7 2 Boot Sequence One of the best features Flex MuxOneNAND has is that it can be a booting device itself since it contains an internally built in boot loader despite the fact that its core architecture is based on NAND Flash Thus Flex MuxOneNAND does not make any additional booting device necessary for a system which imposes extra cost or area overhead on the overall system As the system power is turned on the boot code originally stored in the first block which is SLC area is
158. tion So if a user wants to exit from OTP access mode without the erase operation stop Reset NAND Flash Core command should be used Erase Resume When the Erase Resume command is executed the Block Erase will restart The Erase Resume operation does not actually resume the erase but starts it again from the beginning When an Erase Suspend or Erase Resume command is executed the addresses are in Don t Care state ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 12 Partition Information Block SLC Only One Block of the SLC Flash Array memory is reserved for Partition Information Block The block can be read programmed and erased using the same operations as any other NAND Flash Array memory block Only Load Erase and Program can be performed PI Block is not able to cover with internal ECC Engine in OneNAND so it has to be accessed under ECC off mode PI block is guaranteed to be a valid block up to 1K program erase cycles Entering the PI Block The block is separately accessible from the rest of the Flash Array by using the Access command instead of the Flash Block Address FBA Exiting the Block To exit the Access Mode a Cold Warm Hot Flash Core Reset operation is performed Exiting the Block during an Erase Operation If the Reset triggered exit from the
159. u speed 3soH 121 i l ae eg Dunes puz JSL spe 11soH sseJppv t INI LOS ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 6 11 Program Operation Timing See AC Characteristics Table 5 7 and Table 5 9 Program Command Sequence last two cycles Read Status Data tAVDP tWEA AVD K 7 gt k N N N le AIDQO AIDQ15 CE OE WE ics tPGM1 or tPGM2 CLK INT bit RDY NOTE 1 AA Address of address register CA Address of command register PCD Program Command Address of memory to be programmed BA Address of BufferRAM to write the data BD Program Data SA Address of status register 2 In progress and complete refer to status register 3 Status reads in this figure is asynchronous read but status read in synchronous mode is also supported ELECTRONICS FLASH MEMORY See AC Characteristics Table 5 7 and Table 5 9 Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx 6 12 Cache Program Operation Timing enssi p nb SI 1 dnsaju 0
160. urst Write Cycle NOTE 1 L VIL Low H VIH High X Don t Care ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 3 Reset Mode Operation The Flex MuxOneNAND has 4 reset modes Cold Warm Hot Reset and NAND Flash Array Reset Section 3 3 discusses the operation of these reset modes The Register Reset Table shows the which registers are affected by the various types of Reset operations Internal Register Reset Table NAND Flash Internal Registers Cold Reset Default Warm Reset RP Core Reset Manufacturer ID Register 00 Device ID Register Note 3 N A N A N A Version ID Register R N A N A N A N A Data Buffer size Register R 0800h N A N A N A Boot Buffer size Register R 0200h N A N A N A Amount of Buffers Register R 0201h N A N A N A Technology Register R 0001h N A N A N A Start Address1 Register R W DFS FBA 0000h 0000h 0000h N A Start Address2 Register R W DBS 0000h 0000h 0000h N A Start Address8 Register R W FPA 0000h 0000h 0000h N A Start Buffer Register R W BSC BSA 0000h 0000h 0000h N A Command Register R W 0000h 0000h 0000h N A System Configuration 1 Register R W 40COh Note 1a Note 1a N A Controller Status Register R Note 1b Note 4 0000
161. using INT auto mode Refer to chapter 2 8 18 1 Read Completed DBS DFS is for DDP ELECTRONICS 67 Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 7 Read Operation See Timing Diagrams 6 1 6 2 6 3 and 6 4 The device has two read modes Asynchronous Read and Synchronous Burst Read The initial state machine automatically sets the device into the Asynchronous Read Mode 0 to prevent the spurious altering of memory content upon device power up or after a Hardware reset No commands are required to retrieve data in Asynchronous Read Mode The Synchronous Read Mode is enabled by setting RM bit of System Configuration Register F221h to Synchronous Read Mode 1 See section 2 8 19 for more information about System Configuration1 Register 3 7 1 Asynchronous Read Mode Operation RM 0 WM 0 See Timing Diagrams 6 3 and 6 4 In an Asynchronous Read Mode data is output with respect to a logic input AVD AE mE Output data will appear on DQ15 DQO when a valid address is asserted on A15 A0 while driving AVD and CE to VIL WE is held at The function of the AVD signal is to latch the valid address Address access time from AVD low tAA is equal to the delay from valid addresses to valid output data The Chip Enable access time tCE is equal to the delay from the falling edge of CE to valid data at the outputs
162. uxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 6 5 Asynchronous Write See AC Characteristics Table 5 7 CLK VIL tcs twc tCH tcez lt e AVD ADQ15 ADQ0 RDY tcER NOTE VA Valid Read Address WD Write Data ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx 6 6 8 Word Linear Burst Write Mode See AC Characteristics Table 5 8 FLASH MEMORY E BRWL 4 0000 ii tcEs l cy 1 O 1 2 3 4 nd 1 T UEST OEST f 11 PM vos 0 t MES tt AVD 3 N twos tWDH 4 tacs Z AEE E Gor tACH OE twES IE WE tt N tRDYA 4 2 5 Hi Z gt gt 6 7 Burst Write Operation followed by Burst Read See AC Characteristics Table 5 8 4 eee eee set ees ee gt tces tcES ii ae 2 lt gt N l 0 1 2 3 4 CLK LY PY fi lab lt favos tAVDS 4 AVD two VDH twou BA 4 tACS gt tAVDO gt A D
163. with the n 1 th rising edge The number of total initial access cycles is programmable from three to seven cycles After the number of programmed burst clock cycles is reached the rising edge of the next clock cycle triggers the next burst data Four Clock Burst Read Latency BRWL 4 case Rising edge of the clock cycle following last read latency 22 triggers next burst data lt tRDYS NOTE BRWL 4 HF 0 is recommended for 40MHz 66MHz For frequency over 66MHz BRWL should be 6 or 7 while HF 1 Also for frequency under 40MHz BRWL can be reduced to 3 and HF 0 3 7 3 Handshaking Operation The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read To set the number of initial cycles for optimal burst mode the host should use the programmable burst read latency configuration see section 2 8 19 System Configuration1 Register The rising edge of RDY which is derived at one cycle prior of data fetch clock indicates the initial word of valid burst data 3 7 4 Output Disable Mode Operation When the CE or OE input is at output from the device is disabled The outputs are placed in the high impedance state ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 3 8 Synchronous Write RM 1 WM 1 See Timing Diagram 6
164. x Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY Reset Interrupt RSTI This is the Reset interrupt bit RSTI Interrupt 4 Default State Interrupt Conditions Cold Warm hot Function 0 1 off At the completion of an Reset Operation sets itself to 1 OOBOh OOFOh OOF3h or Pending warm reset is released 0 is written to this bit or clears to 0 command is written to Command Register in INT auto mode 2 8 23 Start Block Address Register F24Ch R W This Read Write register shows the NAND Flash block address in the Write Protection mode Setting this register precedes a Lock Block command Unlock Block command or Lock Tight Command F24Ch default 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 000000 SBA Device Number of Block SBA 4Gb 1024 9 0 2 8 24 Start Block Address Register F24Dh R W This register is reserved for future use 2 8 25 NAND Flash Write Protection Status Register F24Eh R This Read register shows the Write Protection Status of the NAND Flash memory array To read the write protection status FBA DFS and DBS also in case of DDP has to be set before reading the register F24Eh default 0002h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0000000000000 US LS LTS Write Protection Status Information 2 0 Definition Description Unlocked Status 1 current Flash b
165. y memory Page the on chip ECC engine generates a new ECC The Load ECC result is compared to the originally programmed ECC thus detecting the number of errors Up to 4 bit errors are corrected ECC is updated by the device automatically After a Load Operation the Host can determine whether there was error by reading the ECC Sta tus Register Refer to section 2 8 26 2 8 29 Error types are divided into error correctable error 1bit 4bit and uncorrectable error more than 4bit When the device reads the NAND Flash Array memory main and spare area data with an ECC operation the device doesn t place the newly generated ECC for main and spare area into the buffer Instead it places the ECC which was generated and written during the program oper ation into the buffer An ECC operation is also done during the Boot Loading operation 3 15 1 ECC Bypass Operation In an ECC bypass operation the device does not generate ECC as a background operation In a Program Operation the ECC code to NAND Flash Array memory spare area is not updated During a Load operation the on chip ECC engine does not generate a new ECC internally Also the ECC Status Registers are invalid The error is not corrected and detected by itself so that ECC bypass operation is not recommended for host ECC bypass operation is set by the 9bit of System Configuration 1 Register see section 2 8 19 ECC Code and ECC Result by ECC Operation Program operat
166. y monitor the Interrupt Status Register Bit instead of using the INT pin When using interrupt register instead of INT pin INT must be unconnected Command INT Y This can be configured in either a synchronous mode or an asynchronous mode Synchronous Mode Using Interrupt Status Register Bit Polling When operating synchronously CE AVD CLK RDY OE and DQ pins on the host and Flex MuxOneNAND are tied together RDY could be connected as one of following guides Host Flex MuxOneNAND Host Flex MuxOneNAND CE CE CE CE AVD 4 AVD e AVD CLK CLK CLK CLK RDY WAIT RDY RDY OE OE OE OE DQ DQ DQ DQ Handshaking Mode Non Handshaking Mode Asynchronous Mode Using Interrupt Status Register Bit Polling When configured to operate in an asynchronous mode AVD OE and DQ of the Flex MuxOneNAND are tied to corresponding pins of the Host CLK is tied to the Host Vss Ground RDY is NOT connected Host Flex MuxOneNAND CE CE AVD AVD Vss CLK RDY OE OE DQ DQ ELECTRONICS Flex MuxOneNAND4G KFM4GH6Q4M DEBx Flex MuxOneNAND8G KFN8GH6Q4M DEBx Flex MuxOneNAND16G KFKAGH6Q4M DEBx FLASH MEMORY 7 1 3 Determining Rp Value DDP QDP Only For general operation INT operates as normal output pin so that tF is equivalent to tR below 10ns But since INT operates as open drain wi

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