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Ricoh R5C841 User's Manual

1. RICOH GROUP FORMAT 6 02 BW 4 A 2 4 6 8 10 12 14 16 18 1 9 7 9 11 13 15 17 19 W V U N e M L H G F E D V 0 80 0 031 0 50 0 05 20 15 0 006 S AB WISTAB mm inch DIMENSIONAL TOLERANCE SPECIFIED CR VISUAL GRADE DIMENSION X CLASS 2 x lt 16 01N0 1 2 16 lt YE 63 101 0 3 63 X 250 02 03105 ANGLE TOL SCALE 250 X 1000 0 5 0 5 8 1000 X lt 4000 x NIS PART NAME DATE NOTICE DRAW UP DAE 2004 7 5 SIGN CSP208PIN P3 PACKAGE OUTLINE 6 APPROVED BY CHECKED BY DESIGNED BY DRAWN BY PART NO gt ER 2 D TYOSHIMURA H GOTOH K sHIMOKAWA 08 5 003 RICON R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet NOTICE 1 The products and the product specifications described in this Data Sheet are subject to change discontinuation of production without notice for reasons such as improvement Therefore before deciding to use the products please refer to Ricoh sales representatives for the latest information thereon 2 This Data Sheet may not be copied or otherwise reproduced in whole or in part without prior written consent of Ricoh 3 Please be sure to take any necessary form
2. OUTEPMEZ Control VPPENO VPPENT 0 2 SPKROUT gt SEER USBOM 1394 Func 1 TPAPO 1394 OHCI gt Registers Controller TPBPO CPS Cable Port 0 PHY LINK Core PRNO a Registers TPBIASO _ 1 gt LINK gt XO Interface FANI gt EO PLL Cable Port 1 TPBP1 gt gt Arbitration TPBN1 amp Control TPBIAS1 4 SD VF Func 2 soci SD EON SDCDAT 3 0 Registers Interface Clock Control Memory Stick MDIO 19 00 RICOH 2004 Interface MS Registers Clock Control xD Registers xD Picture Card Interface XDCD 1 0 XDLED XDR B 1 10 2 1 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 3 PIN DESCRIPTION 3 1 Pin Assignments 208 pin CSP CSP Pin Assignment Bottom View A B C D E F G H J K L M N P R T U O O O O O H O O O O O MDIO00 SPKROUT UDIO5 1001 GND PCICLK HAT AD30 AD26 IDSEL 21 AD19 AD17 QOO Cro X3 IO 0049 0 5 HWSPND GBRST UDIO2 INTA amp INTC NC AD22 20 AD18 Or ore ee Eu E YA O NC TEST RLOUT UDIOO INTB PCIRST REQ PME SRIRQ H 5 o e 05 MDIO07 VCC 9004 GND GND CLKRUN GNT DEVSEL O fl MDIO08 MDIO10 MDIO11 M SERR MDIO12 MDIO14 MDIO15 015 22 212 ONE C AD12 AD1 TPBIAS1 CPS PCI3V O
3. CADR REG CE1 CE2 pa 6b gt lt OE CDATA Data t6f WAIT ER Data Latched 16 bit Card Memory Read Timing RICOH 2004 Rev 1 10 5 10 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet Memory Write VCC_ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta 0 70 C Syms Parameter mn uw CADR 25 0 REG CE 2 1 te Time CADR 25 0 REG and CE Tsu 20 2 1 before WE Low Tsu RM Hold Time CADR 25 0 REG and CE Thl 10 2 1 after WE High Thl EIE Programmable Pulse Duration WEZ Low Tpw 20 Tpw Programmable CDATA 15 0 oat Time CDATA 15 0 before WE Tsu 20 Low Tsu Hold Time CDATA 15 0 after WE High Thl 10 Thl Programmable wam Note1 Tcyc is PCICLK cycle time Typically 30ns Note2 Tsu Tpw can be programmed by setting 16 bit Memory Timing 0 register 16 bit Card Memory Write Timing POI o Weis uen eeu Mee ax CADR REG X X CE1 CE2 Ta t7c i la Ub gt WE i CDATA Data t WAIT 16 bit Card Memory Write Timing RICOH 2004 Rev 1 10 5 11 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet Read VCC_ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta
4. mow vo sus 7 sow f wo 7 ro _ ap Rd NE R n ee vo 7 _ ama jan e ___ amos 9 v e an v e a 1 AD6 ADS v lt e n Q 55565 gt q 70 Q Q La eae an p pu E EE UE PU NN wem heme o wem 9 7 Deme o vereno 7 o wem 7 _ ume vo wwe __ wo sw vo _ ___ _ 9 1 ow cow e es wo wma vo og ____ _ ___ __ v6 65 6 em 39 7 ana mew ___ vo o iii lt SIS RIGOHE2004 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 16 bit Card Interface CardBu
5. Latency 3 0 Min Grant 3 0 pr25nr e RICOH 2004 REv 1 10 4 18 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 4 20 3 2 1394 OHCI Register aPh 4 20 3 3 PCI CardBus Bridge Configuration Space E 16bitMemEnh 16bitlOEnh LegacyldxSel PrefetchEn l O1AdrMode Tim Tim SIRQEn sRPCINTDs LEDPo VPPENPol VCCxENPol rel eee sn Dis Dis En Dis Dis Dis toLED1 En HEC Oa 0 la En DecodeDis SPKROUT DelatedClr CBCLKRUN 5VReadEn ae a a 1 a og m _ ipe eS ee i o __ _______ ___ O o O 4Bh RICOH 2004 REv 1 10 4 19 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 4 20 3 4 Memory Stick Configuration Space Card Detect ese et cL 0 CLK CLKselection 1 0 0 EM PMETrgIn PMETrgRM Card Card Inserted by Removed by MSCD MSCD BR ee Subsystem Vendor ID 7 0 55h Subsystem Vendor ID 15 8 mm Subsystem ID 7 0 MSLED MSLED NUN RN RA Write Enable OXFD E eei CLKRUNDis MSPWRPOl se LEDDwetonSe t INTSEL 1 0 15 25224 4 20 3 5 SD Card Configuration Space ee ee LED Control 2 0
6. MIN Grant amp MAX Latency 15 0 ACh Writable Subsystem Vendor ID 15 0 AEh Writable Subsystem ID 15 0 80h 1394 Misc Control 15 0 9Ch 1394 Misc Control 2 7 0 9 1394 Misc Control 3 7 0 BEh Writable MIN GNT amp MAX LAT 15 0 98h PHY Power Management 7 0 99h PHY Shadow 7 0 SD Card Interface Config Space 2Ch Subsystem Vendor ID 15 0 2Eh Subsystem ID 15 0 ACh Writable Subsystem Vendor ID 15 0 AEh Writable Subsystem ID 15 0 BOh SD Clock Control 23 0 BAh PME Trigger Disable 7 0 BCh SD Card Detect Control 23 0 EOh SD Capabilities O 15 0 E2h SD Capabilities 1 15 0 E4h SD Capabilities RSV 31 0 E8h SD Maximum Current Capabilities 31 0 ECh SD Maximum Current Capabilities RSV 31 0 F8h SD Misc Control 31 0 FCh Key 7 0 Memory Stick Interface Config Space 2Ch Subsystem Vendor ID 15 0 2Eh Subsystem ID 15 0 40h Memory Stick Clock Control 23 0 2004 REv 1 10 4 8 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 4Ah PME Trigger Enable 7 0 ACh Writable Subsystem Vendor ID 15 0 AEh Writable Subsystem ID 15 0 F8h MS Misc Control 31 0 FCh Key 7 0 xD Picture Card Interface Config Space 2Ch Subsystem Vendor ID 15 0 2Eh Subsystem ID 15 0 40h xD Picture Card Clock Control 23 0 4 PME Trigger Enable 7 0 ACh Writable Subsystem Vendor ID 15 0 AEh Writable Subsystem
7. input han yaaga 24 Wee3wes v fn W2 mowe Y Ws ampa 24 Wis momove os vom 24 ww vom owe 24 www von outputtowvotege 59 v 10 RM RM NERA SRM Input Leakage Current Vin 0 Pull up 102 Hi Z Output Leakage Current _____ Vout 0 VCC_3V 10 Note 9 Applied CD1 CCD1 CD2 CCD2 MDIOOO MDIOO1 MDIOOS pins Note 10 Applied for OUT SPKROUT VCC5EN VCC3EN VPPEN1 MDIO04 MDIOO5 MDIOOG6 pins Note 11 Applied for VS1 CVS1 VS2 CVS2 pins Note 12 Applied for GBRST HWSPND MDIOO7 pins RICOH 2004 Rev 1 10 5 3 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 2 6 Cable Interface ROUT 1 65 1 95V 3 0 3 6 Ta 0 70 C Simbo Parameter Max unt Teatconaiton nor eu ee Differential Input Voltage 118 260 mV Cable input during data 13 14 reception Cable input during arbitration TpB Common Mode Input 1 165 2 515 100Mbps speed signaling off Voltage 0 935 2 515 200Mbps speed signaling 0 523 2 515 400Mbps speed signaling VOD Differential Output Voltage 172 Cable output load 560 13 14 ppr TpB Common Mode 1 81 0 44 Driver enable speed signal off EI 14 Output Cur
8. Connect_Detect TpBias_Disable Strb_TX Strb Enable Receipt Signals Receipt Signals Data Rx i i Data Rx Arb A Rxetc Arb A Rxetc Driver n river i Tx Data_Enable i Enable o Receipt Signals TPBN Receipt Signals Strb_Rx i Strb_Rx Arb B Rx etc 270 Rx etc System A System B gt means port number in this figure Example TPBIAS TPBIASO or TPBIAS1 Each port consists of two twist pairs TPA and TPB The TPA and the TPB are used in order to monitor transmission reception of a control signal Arbitration signal and data and the state of a cable line the insert of a cable It is necessary for the TPA and the TPB to be connected to a termination of 55Q resistances according to the cable impedance This termination resistance should be arranged near the R5C841 On TPA side TPBIAS should be placed to the center node of the termination resistance in order to set up cable s common mode DC potential A capacitor of 0 33uF for decoupling should be connected to the TPBIAS On TPB side a termination 5 1 and a capacitor of 270pF should be connected to between the center node of the termination resistance and AGND See the application manual for the substrate layout RICOH 2004 REv 1 10 4 23 R5C841 P
9. symbol Note ______ SDA UDIO4 SCL UDIO3 sx suexmemeg teur Bus tee tme between a STOP and START condition 47 _ t HD STA Hold time repeated START condition After this 4 0 us period the first clock pulse is generated ae IE tow __ LOWperiod ofthe scLclock 1 uw periodofthe scl clock 40 uw tsusm Set up tine fora repeated START sonaton ar uoo Data holdtimerori2G busdevews fo sus 29 fie ___ Rise tme ofboth SDA ana Sct saras _____ w Fatime SOA ana SCL signals _____ tus Serup tme ter STOP eonan _______ o tsp Pulse width of spikes which must be suppressed by n a n a ns ee _____ Capacitive load for each bus line 40 All values referred to levels see 5 2 11 Serial ROM if SDA SCL timing SDA UDIO4 SCL UDIO3 tup pat tsu paT RICOH 2004 Rev 1 10 5 17 x4 I0 10 0 004 P3 1616 PACKAGE CODE 5 208 16 00 0 630 COO V x C gio 5 Sig E ee 7 0 12 0 005
10. 1 21 ee AZO et e emen 50 _ _ __ NER f pp po 251 2222 OO 429 OFRAMER ee 55 1 AM __ cR 256 __ 25 J 40ADIS 58 __ __ 59 60 INPACKHRFU SDCDR 20171 REGE COBER eee 62 SPKRHBVD2 CAUDIO 0 XDRB 63 STSCHGHBVD1 CSTSCHG AA 7 lt 309 5 JOADSO p m _ m uo 68 3 3 Pin Functions Outline In this chapter the detailed signal pins in the R5C841 are explained Every signal is divided according to their relational interface Card Interface signal pin is multi functional pin Card Interface mode is configured automatically by the card insertion CardBus card or 16 bit card And the pin function is redefined again mark means the signal is on either active or asserted when the signal is low level Otherwise no mark means the signal is asserted when the signal is high level The following the notations are used to describe the signal type IN Input Pin OUT Output Pin OUT TS Three State Output Pin OUT OD Open Drain Output Pin y o Input Output Pin OD Input Output Pin Output is Open Drain s hiz Sustained Tri State is a
11. Class Code 7 0 specific register level programming interface Class Code 15 8 sub class code Class Code 23 16 base class code Subsystem Vendor ID 7 0 at Subsystem Vendor ID 15 8 CUm Subsystem ID 7 0 NM Subsystem ID 15 8 e J rieotCockSeec to ClKSelection 1 0 PMETrgDis PMETrgDis PMETrgDis Card Card Card Removed by Inserted by Interrupt by SDCD SDCD SDCDAT1 Card Detect Eme So 0 m 9 men __ Counter cut SDLED SDLED d Write Enable a ee EC II E e CapabilityO 7 0 CapabilityO 15 8 Capability1 7 0 Capability1 15 8 Maximum Current for 3 3V Maximum Current for 3 0V Maximum Current for 1 8V RICOH 2004 REv 1 10 4 20 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Card Data Sheet 4 20 3 6 xD Picture Card Configuration Space Subsystem Vendor ID 7 0 Subsystem Vendor ID 15 8 a Subsystem ID 7 0 77h 78h XDLED XDLED aw 31 79h Write Enable OXFD 7A CLKRUNDs XDPWRPoI BH _ 1 Card Detect Mode 1 0 7Dh selection ___ 7Eh PMETrgIn PMETrgRM Card Card Inserted by Removed by XDCD XDCD 4 21 LED Output R5C841 can output the activity signals of the PC card the 1394OHCI the SD Card the Memory Stick and the xD PictureCard as LEDO LED1 and LED2 The R5C
12. Timing of the Start Frame and the Stop Frame is as follows 2004 REv 1 10 4 5 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet Start Frame timing with source sampled a low pulse on IRQ1 SL START FRAME FRAME IRQ1 FRAME IRQ2 FRAME i H los por ps sa Drive Source iRQ1 Host Controller 1 Start Frame pulse can be 4 8 clocks wide Stop Frame Timing with Host using 17 IRQSER sampling period IRQ14 IRQ15 IOCHCK FRAM FRAM FRAM iz 6 5 T STOP FRAME NEXT CYCLE 12 Rit IRQSER Driver None IRQ15 None Host Controller H Host SL Slave Control R Recovery T Turn around S Sample Stop Pulse is 2 clocks wide for Quiet mode and 3 clocks wide for Continuous mode There be none one or more Idle states during the Stop Frame The next IRQSER cycle s Start Frame pulse may or may not start immediately after the turn around clock of the Stop Frame IRQSER Sampling Periods IRQ Data Frame Signal Sampled of clocks past Start 1 2 ARO ee 8 RIGOH 2004 1 10 4 6 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 4 8 Card Type Detection If once a valid insertion is detected the socket state machine in the R5C841 starts to interrogate the PC Card to determine whether it is a CardBus Card a 16 bit PC Card or an ExpressCard The R5C841 supports VCC val
13. UDIOO works as SRIRQ default And GPIO and LEDO are also enabled SRIRQ output enables a Wired OR structure that simply transfer a state of one or more device s IRQ to the host controller Both of a device and a host controller enables a transferring start A transferring called an IRQSER Cycle consists of three frame types one Start Frame several IRQ Data Frames and one Stop Frame When the SR_PCI_INT_Disable bit bit5 of the PC Card Misc control register is Low frames of INTA INTB INTC and INTD PCI Interrupt signals are output following IOCHK frame are output When it is High IRQx only are output from SRIRQ All cycle uses PCICLK as its clock source The IRQSER Start Frame has two operation modes Quiet Active mode and Continuous Idle mode On the Quiet Active mode any device can initiate a Start Frame By occurring of interruptive requests the R5C841 outputs 1 pulse of PCICLK Low and Serialized IRQ is kept on Hi Z during the rest of a Start Frame After that IRQ DATA Frame follows In Continuous Idle mode only Host Controller can initiate a Start Frame The R5C841 becomes waiting state to detect 4 8 PCICLK of Start Pulse These modes change automatically by monitoring the Stop pulse width in a Stop Frame Quiet Active mode is repeated when width of Stop Pulse is 2PCICLK and Continuous Idle mode is repeated when it is 3PCICLK After assertion of the GBRSTZ the default is Continuous Idle mode
14. 20 Current VCC_MD3V Note 19 Applied SDCDAT 3 0 SDCCMD pins Note 20 Applied for SDCCLK pin 5 2 9 Memory Stick Interface ROUT 1 65 1 95V VCC_MD3V 3 0 3 6V Ta 0 70 C sm Parameter Typ Unit Gondiron High Voltage 0 8x VCC Y SY 3 Output Low Voltage lout 8mA 8mA HI Z Output Leakage Current Note 21 Applied for 5 3 0 MSCCLK MSBS pins 5 2 10 xD Picture Card Interface VCC_ROUT 1 65 1 95V VCC_MD3V 3 0 3 6V Ta 0 70 C Parameter Typ wax Unit Test Condition Note OT O wr e rmn Lm Output Low Voltage lou 8mA 22 23 HI Z Output Leakage 23 Current Note 22 Applied for XDDAT 7 0 pins Note 23 Applied for XDRE XDWE XDCE XDALE XDCLE XDWP pins RICOH 2004 Rev 1 10 5 5 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 2 11 Serial ROM Interface For 3 3V signaling VCC_ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta 0 70 C Output fall time from V IHmin to V with up to 3 mA sink with a bus capacitance from current at V OL1 10 pF to 400 pF Note 24 Applied for UDIO3 4 On use of Serial ROM pins 5 2 12 Power Consumption Power Supply Current PowerPin Parameter win Typ we Unt Condition T Not _ E Power Supply Current PCI
15. LED 2004 1 10 3 5 lt SIS gt 99 lt 3 gt gt R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 16 bit Card Interface CardBus Card Interface Pin Characteristics Dir bir SVtolerant PwrRail Drive mm ___ o wm we wm a ae ow ue 7 w m ae sem 7 Eom wwe ie Ew pue pam vo om vo 7 w m eum w o 7 Ems eco vey Docs lie wes ww 7 1 heo ie wes e 7 MDIO02 O PU MDIO02 O PU sv sma E MDIO05 SD O MDIOOS SD O MS 5 xD O PD xD O PD MDIOO6 MDIO06 MDIOO7 EE GE MDIOO7 8 SD l O PUY MDIOO8 SD l O PUY MS O TSy MS O TSy xD O PU xD O PU MDIOOO SD l O PUY MDIOO9 SD l O PUY MS l O PUY MS l O PUY xD O PU xD O PU MDIO10 SD l O PUY MDIO10 SD l O PUY MS MS VO xD VO PD xD MDIO11 SD l O PUY MDIO11 SD VO PU MS VO MS VO xD VO PD xD VO PD MDIO12 SD l O PUY MDIO12 SD l O PUY MS MS xD VO PD xD VO PD MDIO13 SD MDIO13 SD VO PU MS
16. TPBIASO vec PCI3V VCCSEN VCC3EN 2 4730 01 CADR2 CADR4 CADR6 CADR24 CADR15 GND WE CADR13 CADR8 CADRO WAIT amp VS2 CADR23 CADR22 CADR20 CADR18 CADR17 1 ACC PHY3V Or CDATA9 CDATAB BVD1 CADR1 CADR3 5 CADR25 CADR12 CADR21 4 IORD CE2 O CDATA10 CDATA1 BVD2 INPACK RESET CADR16 GND CADR19 IOWR CADR9 OE 10 2004 1 10 V W O AD16 O VCC PERR O AD13 AD9 VPPENO VPPEN1 CDATA11 CDATAS CDATA12 CDATAG CDATA13 CDATA7 O CDATA14 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard CSP Pin List Signal Name Signal Name Signal Name Data Sheet Signal Name TEST HWSPND SPKROUT RI_OUT PME GBRST UDIO5 UDIO4 UDIO3 UDIO2 UDIO1 UDIOO SRIRQ INTA INTB INTC CLKRUN PCIRST PCICLK GNT REQ AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C BE3 IDSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 C BE2 FRAME IRDY TRDY DEVSEL __ 4 10 11 17 17 RICOH 2004 STOP PERR SERR PAR C BE1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 C BEO AD7 AD6 ADS AD4 AD3 AD2 AD1 ADO VCCSEN VCC3
17. the PC Card Misc Control 4 register for setting of UDIO3 and UDIOA Without the Serial ROM With the Serial ROM L gt R5C841 100kQ R5C841 10kQ VCC_3V VCC_3V SPKROUT gt SPKROUT gt UDIO4 UDIO4 gt UDIO4 e UDIO3 UDIO3 UDIO3 gt SDA SCL 100kQ Serial ROM RICOH 2004 REv 1 10 4 17 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 4 20 3 Format The R5C841 starts accesses to the Serial ROM by detecting a pull down of the SPKROUT when the first PCI Reset is deasserted after deassertion of the GBRST The accessed data is stored to each register as follows The retry states don t allow slave access during accesses to the Serial ROM Each parts register of 1394 OHCI LINK Configuration Space 1394 OHCI Registers Space PCl CardBus Bridge Configuration Space SD Card Configuration Space Memory Stick Configuration Space and xD Picture Card Configuration Space 4 20 3 1 13940HCI LINK Configuration Space Subsystem ID 15 8 04h LEDTX 1 LEDTXO LEDRX 1 LEDRQO on D2PhyPM 1 0 D2ForcePM D3PhyPM 1 0 D3ForcePM CPSDis PODis P1Dis PruCShadow2o shadow _ 1 17 N 22h 1394LED 1394LED LEDDurationSel 1 0 toLED 12 toLEDO Pe
18. wo we v e wo _ woseo wo v oom ww foo e ra mu some _____ Dwo o oo wo pe m ee kai 1 125 CUR CN RE 009 jro v vo pes 3 ano 9 v ja 9 v Pe an f wo jaos 9 v Pe amy 0 wo jaw vo v Pe c ae 0 wo 0 vo Pe aps 0 wo ja Jof v Pe noo ADU e wo v Pe ___ 1 je e ___ wo ja 9 v ___ an __ wo vo v Pe wo vo v ___ ann f wo 9 v Pe ___ ame f wo 9 v e ame f wo 9 om wo vo v e jrmwee vo R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 16 bit Card Interface CardBus Card Interface Pin Characteristics PinName Di PinName Dir SVtolerant PwrRail Drive
19. 0 70 C Syms owe Unt CADR 25 0 REG a Time CADR 25 0 REG before ORD Tsu 20 Low Tsu 2 M Hold Time CADR 25 0 and REG after ORD Thl 10 High Thl Pi Programmable IORD Pulse Duration IORD Low Tpw 20 1 3 Tpw 3 31Tcyc Programmable 2 1 PCE Vals belay ADR CDATA 15 0 Fus fag vaiaso OREL WAT Fm vaio bey aor SOT Owe 1 l1 9 1 INPACK m vaio belay 10RD tow Aor we 1 Note1 Tcyc is PCICLK cycle time Typically 30ns Note3 Tsu Tpw be programmed by setting 16 bit Timing 0 register 16 bit Card 1 0 Read Timing car cea eS A CADR X y t8d CE1 CE2 X t n p t8h lt gt lt t8b t8c IORD gt t8e CDATA Data t8g taf WAIT M ot INPACK 171 t8k _ Data Latched 16 bit Card I O Read Timing RICOH 2004 Rev 1 10 5 12 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet Write ROUT 1 65 1 95 VCC_3V 3 0 3 6V Ta 0 70 C aam Unt Now CADR 25 0 REG Time CADR 25 0 and REG before Tsu 20 I
20. 2000 Standard Specification Compliant with 1394 Release 1 1 1 0 Standard Specification Support Cycle Master Provide the Asynchronous receive transmit FIFO and isochronous receive transmit FIFO Support Self ID physical DMA Data transmission rate 100 200 and 400Mbps 2 ports of 1394 Cable interface 24 576MHz crystal oscillator and Internal 393 216MHz PLL Support Cable Power monitoring CPS Set Initial values of Power Class and CMC by PCI Configuration registers Card Interface 50 Compliant with SD Memory Card Specification Version 1 01 Compliant with SD Input Output SDIO Card Specification Version 1 0 Compliant with SD Host Controller Standard Specification Version 1 0 Memory Stick Compliant with Memory Stick Standard Format Specification Version 1 4 Compliant with Memory Stick PRO Format Specification Version 1 00 e xD Picture Card Compliant with xD Picture Card Specification Version 1 00 Compliant with xD Picture Card Host Guideline Version 1 00 Backward compatible with the Smart Media ExpressCard Interface Compliant with EXPRESSCARD STANDARD Draft Release 1 0 USB Interface Type only Pass USB signals from a USB HOST to a Card Slot System Interrupt Support INTA INTB and INTC for PC system interrupt Each unit is programmable Support Serialized IRQ IRQx support for ISA system interrupt Support Remote Wak
21. Card interface or the xD Picture Card interface This signal is connected to the interrupt line of the PCI bus UDIOO SRIRQ TS USER DEFINABLE INPUT OUTPUT These signals can be used as user definable UDIO4 GPIOO input output Users can define functions such as GPIO LED IRQ and so on for each pin in the PC Card Misc Control 4 Register For details refer to PCI CardBus Bridge Registers Descripion in the registers description GPIO General Purpose UDIO2 GPIO1 UDIOS GPIO2 UDIO4 GPIO3 UDIOS LEDO OUT OD RING INDICATE OUTPUT When 16 bit card is inserted and Ring Indicate Enable bit in PME the Interrupt and General Control register is set to on the IO Card is forwarded to POWER MANAGEMENT EVENT When PME En bit Power Management Control Status register is set or when Power Status is set to any state mode except DO this signal is assigned as PME RICOH 2004 1 10 3 13 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 3 3 3 16 bit PC Card Interface signals mm me me Denn 16 bit PC Card Interface Pin Descriptions 16 bit Card DATA BUS SIGNALS 15 0 Input buffer is disabled when the card socket power supply is off or card is not inserted REG OUT TS 16 bit Card ATTRIBUTE MEMORY SELECT This signal selects Attribute Memory access or common memory access during 16bit memory cycle Attribute memory a
22. Crystal OSC External Clock Driver R5C841 R5C841 XO Xl 10pF 10pF 5 il 5 Recommended Conditions Crystal Oscillator Normal Frequency 24 576MHz Frequency Tolerance xbOppm at 25 C Temperature stability 50 to 25 C Operating Temperature Range 20 70 C Load Capacitance 10pF Driver Level 0 1mW Equivalent Series Resistance 500hm Max Insulation resistance 500M ohm Min at DC100V 15V Shunt Capacitance 7 0pF Max External Clock Driver Normal Frequency 24 576MHz Frequency Tolerance xbOppm at 25 C 4 22 6 PLL The PHY block of the R5C841 produces 393 216MHz of the internal clock that is 16 times as long as the 24 576MHz produced by the internal PLL circuit Setting the Sleep Mode of the PHY block can stop the PLL circuit Refer to the Power Management Ch 4 11 for settings of the Sleep Mode PLL External Circuit R5C841 FILO 0 01uF AGND RICOH 2004 REv 1 10 4 25 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Card Data Sheet 4 22 7 Reference Voltage Circuit and Reference Current Circuit The PHY block of R5C841 supports terminals of the external parts for the Reference voltage circuit and the Reference current circuit Each terminal should be connected to indicated capacitors and resistors Reference Voltage Circuit Reference Current Circuit R5C841 R5C841 VREF REXT 0 01uF 2 AGND 4 23 Function s Selection The R5C84
23. Output Duration LEDO PC_Card LED 1394 LED SD_Card LED Memory Stick LED xD LED LED1 PC_Card LED 1394 LED SD_Card LED Memory Stick LED xD LED LED2 1394 LED RICOH 2004 REv 1 10 4 21 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Data Sheet 4 21 1 PC Card LED CardBus R2 The trigger signals of the PC Card LED are as follows CardBus CFRAM CINT R2 Card command by IORD IOWR OE WE IREQ Bit 13 and bit 12 of the Config Func 0 A2h register can set the counter s duration bit 13 12 the LED Output Duration 64 msec default 1 msec No Duration Time through Test Mode 3 8psec 4 21 2 1394 LED The 1394 LED signal indicates the condition of the IEEE1394 interface block in the R5C841 This signal is asserted when the R5C841 is on transmission reception Bit 2 and bit 1 of the Config Func 1 9Eh register can set the counter s duration the LED Output Duration 64 msec default 1 msec No Duration Time through Test Mode 3 8usec gt 0 0 4 21 3 SD LED The SD LED signal indicates conditions of the SD Card interface in the R5C841 This signal is asserted when the R5C841 is on the transmission the reception and the debounce duration of the card detection Bit 29 and bit 28 of the Config SD Func 2 F8h register can set the counter s duration bit 29 28 the LED Output Duration 64 msec default 1
24. R5C841 into D1 enables the ack tardy generation Software must ensure that IntEve ack tardy is Ob and should unmask wake up interrupt events such as IntEvent phy and IntEvent ack tardy before placing the R5C841 into D1 LPS is deasserted and stopping supply of SCLK is requested to the PHY The PCI configuration space is retained and capable of access The GUID register is retained but the1394 OHCI register is lost Functional interrupts are masked But when the LinkOn signal that is occurred by accepting LinkOn packet or PHY INTERRUPT is accepted from the PHY PME is generated by PME EN after setting PME STS LPS is deasserted and stopping SCLK supply is requested to the PHY The PCI configuration Space is capable of access but all register except the PME context is lost The GUID register is retained but the1394 OHCI register is lost On transitioning back to DO the internal reset is automatically done even if PCIRST is not asserted Functional interrupts are masked But when the LinkOn signal is accepted from the PHY PME is generated by PME EN after setting PME STS D3cold D3cold indicates the state that VCC_RIN ROUT and AVCC are changed to the auxiliary power D3hot state D3cold supports functions like D3hot s in case of an internal regulator disabled RICOH 2004 REv 1 10 4 11 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet PHY fun
25. Signals Timing Card Input VCC_ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta 0 70 C symbol mn We um CAD 31 0 CC BE 3 0 CPAR CFRAME Z CDEVSEL CIRDY CTRDY CSTOP CPERR CSERR CCLKRUN CREQ t13b Hold Time Signal Hold Time after CCLK High 0 ns CardBus Interface Input Signals Timing CCLK 0 325Vcc CardBus Input Signals Timing RICOH 2004 Rev 1 10 5 15 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 3 5 Hardware Suspend mode Timing chart for keeping the value of the internal register on the Suspend mode Hardware Suspend Timing VCC PCI3V PCI RST Symbol Parameter HWSPND to PCIRST delay PCICLK 33MHz 5 3 6 Global Reset signals Timing chart for initializing the internal register on the Power s on Global Reset Timing VCC RIN VCC ROUT 1 65V Disabled regulator i VCC_RIN 3 0V Enabled regulator a Tpres i GBRST 24N PCI RST Ds 0 5VCC_PCI3V HWSPND gt Tpspnd VCC_PCI3V 3 0V 4 PCICLK 33MHz RICOH 2004 Rev 1 10 5 16 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 3 7 Serial ROM Interface signals SDA UDIO4 SCL UDIO3 VCC_ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta 0 70 C
26. an open drain output driver The assertion and deassertion of CINT is asynchronous to CCLK CSTSCHG CardBus Card Status Change This signal is an input signal used to alert the system to changes in the READY WP or BVD 2 1 conditions of the card It is also used for the system and or CardBus card interface Wake up CSTSCHG is asynchronous to CCLK CAUDIO CardBus Card Audio This signal is a digital audio input signal from a CardBus Card to the system s speaker CAUDIO has no relationship to CCLK CCD1 CardBus Card Detect 1 CCD 2 1 pins are used to detect the card insertion CCD 2 1 pins are used in conjunction with CVS 2 1 to decode card type information CCD2 CardBus Card Detect 2 CCD 2 1 pins are used to detect the card insertion CCD 2 1 pins are used in conjunction with CVS 2 1 to decode card type information CVS1 CardBus Card Voltage Sense 1 CVS 2 1 pins are used in conjunction with CCD 2 1 to decode card type information CVS2 CardBus Card Voltage Sense 2 CVS 2 1 pins are used in conjunction with CCD 2 1 to decode card type information 3 3 5 Socket Power Control signals Socket Power Control Signal Descriptions 3 3 6 Other signals desorption Other Signals Descriptions SPKROUT y o SPEAKER OUTPUT This signal is a digital audio output from SPKR and Connecting this signal to pull down sets the Serial ROM mode HWSPND Hardware Suspend This signal
27. hand setting CINT ISA Disable bit Config AOh bit6 disables the 32bit Function Interrupt to route into the ISA Interrupt and enables to route into the INT Interrupt And also setting the Card Status Change Interrupt Configuration register on the 16bit Control registers the 16bit Card Status Change Interrupt to route into the ISA Interrupt But the R5C841 doesn t support IRQ ISA function on 1394 OHCI On the 1394 the R5C841 transmits interrupt signals to the host on the end of the DMA transaction and also transmits interrupts of the LINK layer and the PHY layer The IntEvent register and the IntMask register in the OHCI registers control these interrupts The IntEvent register is used to indicate generations of an interrupt event and the IntMask register is used to enable the selected interrupt Writing into the IntEventClear by software enables to clear the interrupt On the SD Card interface the Memory Stick interface and the xD Picture Card interface the R5C841 can inform card insert remove event or an error as an interrupt to the system interrupt signals are open drain outputs When ISA IRQ mode is enabled IRQx signals are programmable to either positive edge mode or level mode RI_OUT be reassigned to interrupt signal such as Remote Wakeup signal In addition to primary interrupt functions the R5C841 supports Serialized IRQ When SRIRQ Enable bit bit 7 of the PC Card Misc Control register is set to 1b
28. in the memory mapped I O space by the Memory Stick Register Base Address register 4 1 9 xD Picture Card Control Register Space The xD Picture Card Control registers are 256byte of register assigned to control the xD Picture Card These registers are used to set for access to the xD Picture Card to give commands and to read write data These are placed the memory mapped I O space by the xD Picture Card Register Base Address register 4 2 CardBus Card Configuration Mechanism The R5C841 provides a mechanism to access to configuration spaces of a CardBus Card which is compliant with the PCI specifications The R5C841 supports functions of changing Type 1 PCI configuration command into Type 0 CardBus configuration command and transferring them 4 3 Address Window and Mapping Mechanism The R5C841 supports two kinds of PCl Card Bridge Interface functions and determines automatically whether an inserted card is a CardBus Card or a 16 bit Card Each interface can be set independently On the CardBus Card interface the transaction is implemented by two I O windows and two memory map I Os or a prefetchable memory window that defined in the PCI configuration space The CardBus Card address and the PCI system address use a flat address in common So the address range specified by a base register and a limit register is forwarded from the PCI to the CardBus Card The R5C841 supports a CardBus Master also so the address forwarding transaction fro
29. of the SD card socket SDEXTCK 07 IN SD External Clock This signal must be connected to GND because the R5C841 does not support SDEXTCK for the SD Card SDPWRO MDIO04 OUT SD Card Power0 Control This signal is provided to control the power supply 3 3V for an SD card SDPWR1 MDIOO05 OUT SD Card Power1 Control This signal is provided to control the power supply 1 8V for an SD card R5C841does not support this signal SDLED MDIO06 SD Card LED Control This signal indicates an access state to the SD card Memory Stick MDIO Pin Memory Stick Control Pin Descriptions Memory Stick Data 3 0 Memory Stick Data signals Normally MSCDATO only MSCCLK MDIO09 Memory Stick Clock Memory Stick Clock signal MSCD MDIOO1 IN Memory Stick Card Detect This signal indicates whether the Memory Stick is inserted to a socket This pin is connected to the INS signal of Memory Stick MSEXTCK MDIOO7 IN Memory Stick External Clock This signal is input to the Memory Stick block This clock supports 0 40MHz If the internal PCICLK is used this signal can be connected to GND MSPWR MDIO04 OUT Memory Stick Power Control This signal is provided to control the power supply for the Memory Stick MSLED MDIOO6 OUT Memory Stick LED Control This signal indicates an access state to the Memory Stick RICOH 2004 1 10 3 18 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick
30. only lower 1byte works when write of address and command data 4 20 Serial ROM Interface The 5 841 can load data for Subsystem ID Subsystem Vendor ID the PCI Interface and some PCI configuration registers default value from the Serial ROM BUS After that the R5C841 can set them to each register automatically e BUS is registered trademark of PHILIPS ELECTRONICS Purchase of Ricoh s 1 C components conveys a license under the Philips patent to use the components of the 1 C system provided the system conforms to the specifications defined by Philips 4 20 1 Outline R5C841 supports 100k mode and 7 bit address and automatically stores the data See Chapter 4 20 3 from the Serial ROM when the first PCI Reset is deasserted after deassertion of the GBRST 4 20 2 User s Setting Connecting the SPKROUT pin to a pull down resistor of 100kQ enables the use of the Serial ROM When the first PCI Reset is deasserted the R5C841 starts to sample SPKROUT pin When SPKROUT pin is connected to a pull down resistor of 100kO the R5C841 attempts to load data through the Serial ROM In this case UDIO3 is reassigned to SCL the clock signal and UDIOA is reassigned to SDA the data signal The SDA and the SCL must be connected to through pull up resistors of 10kQ When the SPKROUT pin is connected to through a pull up resistor of 100kO the R5C841 does not load data through the Serial ROM See
31. start packet The R5C841 supports each DMA controller for each isochronous transmit and isochronous receive Each DMA controller supports 4 different DMA contexts 4 16 3 DMA The R5C841 supports seven types of DMA Each type of DMA has register space and data stream referred to as a DMA context DMA Type Number of Contexts Asynchronous Transmit Request x 1 Response x1 Asynchronous Receive Request 1 Response 1 Isochronous Transmit X4 Isochronous Receive X4 Self ID Receive KI Physical Reguest Physical Response No Context Each asynchronous and isochronous context is composed of buffer descriptor lists called a DMA context program which is stored in main memory The DMA controller finds the necessary data buffers through the DMA context programs The Self ID receive controller is controlled not by the DMA context program but by the two other registers The R5C841 supports the Physical Request DMA and the Physical Response DMA controllers in order to transmit the receive request which is to read and write directly to the bus memory space These controllers are also controlled not by the DMA context program but by the other reserved register RICOH 2004 REv 1 10 4 15 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Card Data Sheet 4 16 4 LINK The Link module sends packets which appear at the transmit FIFO interfaces to the PHY and places correctly addressed packets into the receive FIF
32. works as HWSPND input PCIRST is not accepted as long as is asserted so that VCC_PCI3V can be powered off When Serial IRQ mode is set HWSPND must be asserted after Serial IRQ mode on the chip set has been deasserted When Hardware Suspend mode is off HWSPND must be deasserted before Serial IRQ mode is enabled When a power is on follow the reset sequence shown in the chapter 4 10 in order to confirm the input of PCIRST and PCLK TEST TEST This signal is a test mode pin Usually this pin must be tied low RICOH 2004 1 10 3 16 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 3 3 7 IEEE1394 PHY Interface signals 1 IEEE1394 Cable Interface Pin Descriptions TPAP1 VO TPA Positive Twisted pair cable A positive differential signal terminals TPAPO TPBP1 VO TPB Positive Twisted pair cable B positive differential signal terminals TPBPO TPAN1 VO TPA Negative Twisted pair cable A negative differential signal terminals TPANO TPBN1 TPB Negative Twisted pair cable negative differential signal terminals TPBNO TPBIAS1 TP Bias Twisted pair bias output This pin is compliant with the IEEE1394a 2000 and TPBIASO also monitors Insertion desertion of other cables CPS IN Cable Power Status This pin detects the Cable Power Status See in Spec 4 22 3 for details of CPS 3 3 8 1 1394 Control signals I
33. 1 1 msec 1 0 No Duration Time through 0 1 Test Mode 3 8 5 4 21 4 MS LED xD LED The MS LED and the xD LED signals indicate conditions of the Memory Stick interface and the xD Picture Card interface in the R5C841 This signal is asserted when the R5C841 is on the transmission and the reception Bit 29 and bit 28 of the Config MS Func 3 xD Func 4 F8h register can set the counter s duration bit 29 28 the LED Output Duration 0 0 64 msec default 1 1 1 msec 1 0 No Duration Time through 0 1 Test Mode 3 8 5 RICOH 2004 REv 1 10 4 22 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Data Sheet 4 21 5 LED Output Selection All LED can be output to LEDO LED1 The LED for the 1394 is output by setting Config Func 1 9Eh bit 4 3 to 11b the LED for the SD Card is output by setting Config Func 2 F8h bit 7 6 to 11b the LED for the Memory Stick is output by setting Config Func 3 F8h bit 7 6 to 116 and the LED for the xD Picture Card is output by setting Config Func 4 F8h bit 7 6 to 11b Also the LED for the IEEE1394 is output to LED2 by setting Config Func 0 BOh bit6 to Ob 4 22 1394 Cable Interface The R5C841 builds in 2 ports of 1394 Cable interface that support the transmission speed of 400 200 100Mbps compliant with the IEEE1394a 2000 standard 4 22 1 Cable Interface Circuit ICD Connect Detect TpBias Disable
34. 1 can make each function disable by UDIO3 UDIO4 VPPENO Setting UDIO3 to pull down disables the SD Card interface setting UDIO4 to pull down disables the Memory Stick interface and setting VPPENO to pull down disables the xD Picture Card interface Disabled function cannot detect the corresponding configuration register Master Aborts The function s selection is as follows On use of the Serial ROM set the Serial ROM in order to disable each function because UDIO3 UIDO4 and are set to only pull up Function No VPPENO 2 Pull up Pull up Pull up Enable Enable Enable PCCard Pull down Pull up Pull up Disable Enable Enable PCCard Pull up Pull down Pull up Enable Disable Enable PCCard Pull down Pull down Pull up Disable Disable Enable PCCard Pull up Pull up Pull down Enable Enable Disable PCCard Pull down Pull up Pull down Disable Enable Disable PCCard Pull up Pull down Pull down Enable Disable Disable PCCard Pull down Pull down Pull down Disable Disable Disable PCCard RICOH 2004 REv 1 10 4 26 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Data Sheet 4 24 Internal Regulator The R5C841 has an internal regulator which converts the single 3 3V power into the power for the internal core logic REGEN signal enables disables an internal regulator The following is the r
35. 3V and _ on the suspend mode in spite of the Software the Hardware in case of an internal regulator disabled 4 11 3 Function SD Memory Stick xD Picture Card are acceptable provided SDCCLK and MSCCLK are output provided SDCCLK and MSCCLK are output Only the PCI Configuration Space access is allowed while the power and clock are provided SDCCLK and MSCCLK are stopped compulsorily When the function is brought back to the DO state the reset is automatically performed regardless of the assertion of PCIRST Bridge defines D3cold state is to change from VCC_3V and to the auxiliary power source The R5C841 supports power management events from D3cold with the auxiliary power source The R5C841 can generate PME even in D3cold state without PCI clock if the event source is SD Card Detect Change or Memory Stick Detect Change or xD Picture Card Detect Change in case of an internal regulator disabled 4 12 GPIO UDIO1 2 4 pins work as General Purpose I O pin when GPIO Enable bit of the PC Card Misc Control 4 register A4h bit31 is set to 1 on Serialized IRQ default mode or on UDIO Select mode of the PC Card Misc Control 4 register When GPIO Enable bit is set to 70 GPIO outputs are Hi Z and GPIO Inputs are disabled User can change the characteristics of the GPIO pins to either Input or
36. 841 uses UDIOx pins as LEDO 1 2 See the PC Card Misc Control 4 Config Func 0 A4h register for use these pins The default of the LED signal is Low active But setting the LED Polarity bit Config Func 0 82h bit11 to 1b enables to set the LED signal to high active This bit is common to the PC card the 1394 OHCI the SD Card the Memory Stick and the xD Picture Card The LED signal is asserted at the same time the trigger of its signal is asserted And the internal counter works after the trigger is deasserted In default the LED signal is kept for 64msec after the deassertion of the trigger and is deasserted When the trigger is reasserted in operation of the counter the counter is cleared and restarted to count up at the same time the deassertion of the LED signal See the below chart Counter Reset The LED trigger Counter Start Counter Restart The LED output LED Output Duration J Not Count up The LED Output Duration is selected from among 64msec default 1msec and No Duration time through the trigger The card and the 1394 have the different registers for selecting each other See the following The trigger signals for them also are different The R5C841 uses a counter operating PCLK for the LED Output Duration and therefore a stop request of PCLK by the CLKRUN protocol is refused in operation of the counter When PCLK must be stopped for 64msec on system modify the LED
37. CI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 4 22 2 Transaction of Unused Ports On no use of ports TPBP and are directly connected to AGND and TPAP TPAN and TPBIAS are OPEN After that set Port Disable bit of the 1394 PHY Register The PHY Shadow register in the 1394 Configuration registers space also can set the Port disable bit See the Read Write of the 1394 PHY register Ch 4 22 4 4 22 3 CPS Cable Power State The R5C841 builds in a function monitoring the state of the cable power The CPS pin is connected to the cable power through the external resistor 390kQ 1 and detects a condition that cable power has lowered under the threshold level Normally 7 5V When the four pins cable is used when the CPS function is not used it is possible to select two methods one is the direct connection of the CPS pin with the AVCC and the other is with the register s control of the CPS pin which is set to Open In case of the registers control set CPSDis bit1 and CPSFixVal bit0 on the PHY Power Management Register 98h in the 1394 Configuration Register space to 1b The Serial ROM also can be set these registers Refer to the Serial ROM Chapter 4 20 for details On monitoring the state of Cable Power Cable power supply R5C841 CPS 390kohm 1 6pin connector Out of monitoring the state of Cable Power R5C841 AVCC_PHY3V 4pin connector CPS 4 22 4 Re
38. CLK 33MHz Operating VCC_3V 3 6V MD3V 3 6V VCC PCI3V 3 6V AVCC_ PHY3V 3 6V REGEN 0V VCC_RIN 3 6V 0 or VCC RICOH 2004 Rev 1 10 5 6 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 3 AC Characteristics 5 3 1 PCI Interface signals PCI Clock VCC_ROUT 1 65 1 95V VCC_PCI3V 3 0 3 6V Ta 0 70 C ww Note 212221 Im oeme m Puso wan Duration n Fuso wat Duration va StewRate 3 we ue Stew Rate PICLK Faia Edge e v PCICLK Timing 2 0V 0 5Vcc PCICLK loo aw 0 8V 0 3Vcc 2 0V p to p Min 0 4Vcc p to p Min gt 4 4 5V Signaling 3 3V Signaling PCICLK Timing PCI Reset VCC_ROUT 1 65 1 95V 3 0 3 6 Ta 0 70 C sm uw Now er 222 PCI Reset Timing PCIRST t2b peick PCI Reset Timing RICOH 2004 Rev 1 10 5 7 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet PCI Interface Output Signals VCC_ROUT 1 65 1 95V VCC_PCI3V 3 0 3 6V Ta 0 70 C Parametr mn um _____ AD 31 0 C BE 3 0 PAR FRAME DEVSEL IRDY TRDY STOP PERR SERR CLKRUN Sha
39. EEE1394 Control Pin Descriptions VREF VO Voltage reference Resistance is necessary to connect a capacitance of 0 01uF between this pin and AGND REXT Resistance External It is necessary to connect a resistor 10 1 between this and AGND FILO Filter This pin connects to the PLL Filter It is necessary to connect a capacitance of 0 01uF between this pin and AGND 3 3 9 USB Interface signals USB Interface Pin Descriptions USBDP USB Data Port These signals are differential signals These signals are connected to HOST USBDM USB D D signals PC Card p er Pinwame USB Interface Descriptions USBD IORD Z USB Data Port These signals are differential signals USBD IOWR CPUSB CADR22 IN USB ExpressCard Detect This signal indicates whether the USB ExpressCard is inserted to a socket PERST CDATA2 ExpressCard Reset This signal is a reset signal to ExpressCard RICOH 2004 1 10 3 17 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 3 3 10 Small Card Interface signals SD Card me pee 7 SD Data 3 0 SD Card 4bit data bus signals SD Write Protect This signal indicates the state of SD card s write protect switch This pin is connected to a reserved pin of the SD card socket IN SDCD MDIOOO SD Card Detect This signal indicates whether the SD card is inserted to a socket This pin is connected to a reserved pin
40. EN VPPENO VPPEN1 USBDP USBDM CD1 CDATA4 CDATA11 CDATAS CDATA12 CDATA6 CDATA13 7 CDATA14 CE1 CDATA15 CADR10 CE2 Rev 1 10 OE VS1 CADR11 CADR9 IORD IOWR CADR8 CADR17 CADR13 CADR18 CADR14 CADR19 WE CADR20 RDY IREQ CADR22 CADR21 CADR16 CADR15 CADR23 CADR12 CADR24 CADR7 CADR25 CADR6 VS2 CADR5 RESET CADR4 WAIT CADR3 INPACK CADR2 REG CADR1 BVD2 CADRO BVD1 CDATAO CDATA8 CDATA1 CDATA9 CDATA2 CDATA10 WP IOIS16 CD2 MDIO19 MDIO18 MDIO17 MDIO16 MDIO 15 MDIO14 MDIO13 MDIO12 MDIO11 MDIO10 MDIOO9 MDIOO8 MDIOO7 MDIO06 MDIO05 MDIO04 MDIO03 MDIO02 MDIOO1 MDIOO0 XO FILO VREF TPBPO TPBNO TPBIASO TPAPO TPANO CPS 1 TPBN1 TPBIAS1 TPAP1 TPAN1 REGEN J1 J5 K5 E9 R10 T10 V10 GND W10 L15 M19 L2 C1 D1 E1 C2 D2 E2 E4 E12 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 3 2 Pin Characteristics 16 bit Card Interface CardBus Card Interface Pin Characteristics PinName Di Dir SVtolerant PwrRail Drive Too 3 pes 7 sour sew wo a ene 7 w emm ___ we 7 o woe 7 Fus unos 7
41. HCI On the 1394 OHCI function the R5C841 provides occurred PCI Bus errors and some information to recover the errors to system software via the Context register or the descriptor 2004 REv 1 10 4 4 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Card Data Sheet 4 7 Interrupts The R5C841 supports PCI interrupt signals INTA INTB and INTC as well as ISA interrupt signals IRQx They transmit to the system the Card Status Change Interrupt as insert remove event the Function Interrupt by the PC card the DMA Interrupt and the Device Interrupt defined 1394 and interrupts defined on SD Card Memory Stick xD Picture Card interface INTA is assigned to the PC Card interface INTB is assigned to the 1394 and INTC is assingned to the SD Card Memory Stick xD Picture Card interface Interrupts of the PC Card interface and the 1394 can be reassigned by the INT Select bits bit1 0 of the 1394 Misc Control 2 register and Interrupts of SD Card Memory Stick xD Picture Card interface can be reassigned by the INT Select bits bit26 25 of the SD Misc Control register the MS Misc Control register the xD Misc Control register INT Select INT Select PC Card bit25 SD MS xD Reserved INTC INTB INTA On the PC Card setting the IRQ ISA Enable bit of the Bridge Control register enables the IRQx routing register for PC Card 16 32 On the other
42. ICOH 2004 1 10 3 12 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet wm PCI Bus Interface Pin Descriptions Continued SERR OUT OD SYSTEM ERROR This signal is pure open drain The R5C841 actively drives this output for a single PCI clock when it detects an address parity error on either the primary bus or the secondary bus REQ OUT TS REQUEST This signal indicates to the arbiter that the R5C841 desires use of the bus This is a point to point signal GNT IN GRANT This signal indicates the R5C841that access to the bus has been granted This is a point to point signal GBRST GLOBAL RESET This input is used to initialize registers for control of PME_Context register This should be asserted only once when system power supply is on 3 3 2 System Interrupt signals ne System Interrupt Pin Descriptions INTA OUT OD PCI INTERRUPT REQUEST This signal indicates a programmable interrupt request generated from the PC Card interface This signal is connected to the interrupt line of the PCI bus INTB OUT OD PCI INTERRUPT REQUEST This signal indicates a programmable interrupt request generated from the IEEE 1394 interface This signal is connected to the interrupt line of the PCI bus INTC OUT OD PCI INTERRUPT REQUEST This signal indicates a programmable interrupt request generated from the Memory Stick interface the SD
43. ID 15 0 F8h xD Misc Control 31 0 FCh Key 7 0 1394 OHCI Register 24h Global Unique ID High 31 0 28h Global Unique ID Low 31 0 1394 PHY Register All Registers SD Card Register All Registers Memory Stick Register All Registers xD Picture Card Register All Registers 2 These registers are not initialized by PCIRST when the power state is D3 and PME Enable bit is set to 1 PME Context register PC Card Socket Status Control Register Space 000h Socket Event 3 0 004h Socket Mask 3 0 008h Socket Present State 11 10 5 4 010h Socket Control 6 4 802h Power Control 7 2 804h Card Status Change 3 0 805h Card Status Change interrupt Configuration 3 0 82Fh Misc Control 1 0 PC Card Bridge Config Space DEh Power Management Capabilities 15 EOh Power Management Control Status 15 8 1394 OHCI LINK Config Space DEh Power Management Capabilities 15 EOh Power Management Control Status 15 8 SD Card Config Space 82h Power Management Capabilities 15 84h Power Management Control Status 15 8 Memory Stick Config Space 82h Power Management Capabilities 15 84h Power Management Control Status 15 8 xD Picture Card Config Space 82h Power Management Capabilities 15 84h Power Management Control Status 15 8 3 Excepting the above registers PCI RESET Resistant register PME Context register and the global register all th
44. M Signal RESERVED RFU Put in three state by Host Adapter No connection in PC Card Used for accessing PC Card Pixel Clock to ZV Port AT 17 seme ZV Port Interface Pin Assignments 1 Il indicates signal is input to PC Card indicates signal is output from PC Card Video Data to ZV Port YUV 4 2 2 format 4 14 Subsystem ID Subsystem Vendor ID The R5C841 supports Subsystem ID and Subsystem Vendor ID to meet PC98 99 2001 Design Requirements There are three ways to write into the Subsystem ID and the Subsystem Vendor ID registers from the system through BIOS 1 Write Enable bit Card bit6 in the PC Card Misc Control 1394 bit4 in the 1394 Misc Control 2 SD in the Key Memory Stick bitO in the Key xD Picture Card bitO in the Key control method The BIOS can turn this bit on change the Subsystem IDs and turn it off RICOH 2004 REv 1 10 4 13 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 2 of the Subsystem ID and the Subsystem Vendor ID in PCI user defined space method Card COh C2h 1394 SD MS xD ACh AEh 3 Load the Subsystem IDs from the Serial ROM method Connecting SPKROUT to pull down enables to use the Serial ROM The R5C841 has the Serial ROM interface and load the Subsystem ID and the Subsystem Vendor ID after PCI reset disabled These registers are initialized only by GBRST 4 15 Power Up Down Sequence Follow the sequence when the power se
45. ME is asserted data transfers continue When is deasserted the transaction is in the final data phase CPAR y o CardBus Parity This signal is even parity across CAD 31 0 and CC BE 3 0 All CardBus card agents require parity generation CPAR is stable and valid clock after either CIRDY is asserted on a write transaction or CTRDY is asserted on a read transaction Once CPAR is valid it remains valid until one clock after the completion of CFRAME CardBus Initiator Ready This signal indicates the initiating agent s bus master s ability to complete the current data phase of the transaction CIRDY is used in conjunction with CTRDY A data phase is completed on any clock both CIRDY and CTRDY are sampled asserted During a write CIRDY indicates that valid data is present on CAD 31 0 During a read it indicates the master is prepared to accept data Wait cycles are inserted until both CIRDY and CTRDY are asserted together CardBus Target Ready This signal indicates the 5 selected target s ability to complete the current data phase of the transaction CTRDY is used in conjunction with CIRDY A data phase is completed on any clock both CTRDY and CIRDY are sampled asserted During a read CTRDY indicates that valid data is present on CAD CIRDY CTRDY 31 0 During a write it indicates the target is prepared to accept data Wait cycles are inserted until both CIRDY and CTRDY are asserted
46. MS VO xD xD VO PD MDIO14 VO PD MDIO14 MDIO15 VO PD MDIO15 MDIO16 VO PD MDIO16 MDIO17 VO PD MDIO17 MDIO18 O PD MDIO18 O PD MDIO19 O PD MDIO19 O PD 8mA gt gt gt gt OE RENE NU pol O UE NO ___ p S HEBES NT 2004 1 10 3 6 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 16 bit Card Interface CardBus Card Interface Pin Characteristics bir bir SVtolerant PwrRail Drive wem pue e mw 8 e mem wo e mw wo meom 1 neo 1 e Pin Type Input Pin O Output Pin Input Output Pin I PU Input Pin with Internal Pullup Resister PD Input Pin with Internal Pulldown Resister PU Input Output Pin with Internal Pullup Resister PD Input Output Pin with Internal Pulldown Resister O TS Three State Output Pin O OD Open Drain Output Pin Power Rail AP AVCC 3V M PCI PCI Compliant CB PCMCIA CardBus PC Card Compliant 1394 1394 2000 Compliant Note 1 Pullup is at
47. O The features are as follows Transmits and receives correctly formatted 1394 serial bus packets Generates the appropriate acknowledge for all received asynchronous packets Performs the cycle master function Generates and checks 32 bit CRC Detects missing cycle start packets Interfaces to PHY Receives isochronous packets at all times Supports of asynchronous streams and cycle start packets including a CRC error Ignores asynchronous packets received during the isochronous phase 4 17 SD Card Interface The R5C841 has one port of SD Card interface consists of four serial data lines one serial command line card detection write protection and SD clock 4 17 1 Protocol After the SD Card interface block in the R5C841 is initialized the R5C841 outputs the data through the serial SDCMD signal by the host s command Writing into the SD_CMD register and the SD Card s response to the command is inputted to the SDCMD signal The contents of this card s response are stored into bits 7 0 of the SD_RSP register The SD Card is initialized after the SD Card interface block checked CRC etc After that the data is transmitted between the R5C841 and the SD Card through the data lines When the data is written into the SD memory card the host writes the divided data default 512byte into the SD buffer of SD interface block and the R5C841 transmits the serialized data from the SDDAT 3 0 of SD Interface block Conversely when
48. OWR Low Tsu 2 Hold Time CADR 25 0 REG and 2 1 Thl 10 after IOWR High Thl A OA Programmable IOWR Pulse Duration OWR Low Tpw 20 Tpw ie Programmable Valid Delay CADR 25 0 and REG to 2 1 1Toyo0 ns 1 CDATA 15 0 oe Time CDATA 15 0 before IOWR Low Tsu 2Tcyc 10 Tsu DN E Hold Time CDATA 15 0 after IOWR High Thl 10 Thl Programmable Hold Time IOWR Low after WAIT High 1 0 101516 Low Note1 Tcyc is PCICLK cycle time Typically 30ns Note3 Tsu Tpw be programmed by setting 16 bit Timing 0 register 16 bit Card Write Timing ilc CADR REG X _ gt 4 9 gt CE1 CE2 X y 01516605511 tob gt IOWR t9e CDATA Y 199 t9f were __ 16 bit Card I O Write Timing RICOH 2004 Rev 1 10 5 13 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 3 4 CardBus PC Card Interface signals Clock and Signal Slew Rate VCC_ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta 0 70 C sm wm T unt Now IRSE en Ime _ owetme cok e e Puse wish Duration e 1 71 uo Pose with Duration 7 i ww Stew Rate CA Reng
49. Output by setting either I O control bits on the GPIO register 83Ah or the General Purpose I O 1 register of the Config register space AAh When GPIO Enable bit is set to 1 setting of GPIO is input mode default And it is possible to read the states of their pins through each bit of the GPIO register On Output mode the written states of each bit are output If GPIO functions are not used on Serialized IRQ mode no pull up is required RICOH 2004 REv 1 10 4 12 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 4 13 ZV port Interface The R5C844 has the Bypass type ZV port interface On the 16 bit interface when ZV port Enable bit of either the Misc Control 1 register 82Fh or the PC Card Misc Control 2 register is enabled CADR 25 6 101 16 INPACK SPKR are assigned to ZV port input signal as shown in the below diagram The R5C841 has no on chip buffer for the ZV port interface So if ZV port is enabled the signals for ZV port such as CADR 25 4 will be Hi Z or Input disable and they will be reconfigured for the ZV port interface The R5C841 outputs the control signal for the external buffer which is used to switch sockets so that the buffer control for switching sockets is enabled 16 bit Interface ZV Port Interface ZV Port Comments mmm ___ 0 _ HorzontalSynctozvPon o vetcaswetozvPot Audio MCLK PC
50. PABILITY SENSE 1 VS 2 1 pins are used in conjunction with CD 2 1 to decode card type information 16 bit Card CARD VOLTAGE CAPABILITY SENSE 2 VS 2 1 pins are used in conjunction with CD 2 1 to decode card type information RIGOHE2004 RE 10 3 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 3 3 4 CardBus PC Card Interface signals CardBus PC Card Interface Pin Descriptions CCLK OUT TS CardBus Clock This signal provides timing for all transactions on the PC Card Standard interface and it is an input to every PC Card Standard device All other CardBus PC Card signals except CRST upon assertion CCLKRUN CINT CSTSCHG CAUDIO CCD 2 1 and CVS 2 1 are sampled on the rising edge of CCLK and all timing parameters are defined with respect to this edge CCLKRUN CardBus Clock Run This signal is used by cards to request starting or speeding up s hiz clock CCLK CCLKRUN also indicates the clock status For PC cards CCLKRUN is an open drain output and it is also an input The R5C841 indicates the clock status of the primary bus to the CardBus card CRST OUT TS CardBus Card Reset This signal is used to bring CardBus Card specific registers sequencers and signals to a consistent state Anytime CRST is asserted all CardBus card output signals will be driven to their begin state CAD 31 0 CardBus Address Data These signals are m
51. RICOH COMPANY LTD R5C841 PCI CardBus IEEE1394 SD Card MemoryStick xD ExpressCard Data Sheet REV 1 10 IR RICOH COMPANY LTD REVISION HISTORY REVISION DATE COMMENTS 7 24 03 First Draft described Overview Block Diagram and Pin description only 0 70 9 10 03 Addition of the regulator description Spec 4 and the electrical characteristics Spec 5 0 80 11 6 03 Change from NewCard to ExpressCard Mistakes in writing are corrected 1 00 1 30 04 First Public Release Mistakes in writing are corrected 1 10 5 18 04 Changes in the chart of Global Reset Timing Ch 5 3 6 Deletion of the 2 5V power supply support for the core logic RICON 2004 1 10 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 1 OVERVIEW The R5C841 is a single chip solution offering five PCI functions a PCI bus bridge to a PC Card an IEEE 1394 an SD Card a Memory Stick and an xD Picture Card with an ExpressCard USB Interface Type switch 98 99 2001 compliant 2001 Design Guide compliant Subsystem ID Subsystem Vendor 10 Compliant with ACPI and PCI Bus Power Management 1 1 Support Global Reset Low Power consumption Low operating power consumption due to the improvement of Power Management Software Suspend mode compliant with ACPI Hardware Suspend CLKRUN CCLKRUN support The core logic powered at 1 8V the others powered at 3 3V PCI CardBus 1394 Br
52. TSCHG RI BVD2 SPKR INPACK WP IOIS16 pins RICOH 2004 Rev 1 10 5 2 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 2 4 CardBus PC Card Interface VCC_ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta 0 70 C Parameter me Test Condition note ranen veeswes v feor os v Teor wor mec fess qx ewe 31 Input Leakage Current 0 ua Vin 0 VCC_3V_ 0 VCC_3V Input Leakage Current 0 Pull up o _ Input Pin Capacitance 112 Input Leakage Current Vin VCC_3V Pull down Input Leakage Current 70 Vin 0 Pull up Note 5 Applied for CCLK CCLKRUN CRST CAD 31 0 CC BEZ 3 0 CPAR CFRAME CGNT CINT pins if Card interface is configured as a CardBus Card Socket Note 6 Applied for CIRDY CTRDY CSTOP CDEVSEL CPERR CSERR CREQ CINT CAUDIO pins Note 7 Applied for CSTSCHG pin Note 8 Applied for CCLKRUN pin 5 2 5 PC Card Interface Card Detect Pins and System Interface Pins PC Card Interface Card Detect Pins and System Interface Pins VCC_ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta 0 70 C Parameter Te Unit TostGonaition Not pe T vum Votage aa v 9 Vii inputtowVotege fo
53. The R5C841 provides the parity generation and the parity error detection on both the primary PCI bus and the secondary CardBus Having detected an address parity error the R5C841 asserts SERR and sets the Detected Parity Error bit in the PCI Status register Having detected a data parity error the R5C841 asserts PERR and sets the Detected Parity Error bit in the PCI Status register And also having detected a data parity error the R5C841 passes the bad data and bad parity on to the opposite interface if possible This enables the parity error recovery mechanisms outlines in the PCI Local Bus Specification without special considerations for the presence of a bridge in the path of the transaction 4 6 2 Master Abort Having the occurred master abort at the destination the R5C841 implements one of two transactions One is a transaction that is compatible with ISA to invalidate data Returns all 1 when read and invalidates the data when write The other way is to assert SERR 4 6 3 Target Abort Having the occurred target abort at the destination the R5C841 transmits errors as target abort to the original master as thoroughly as possible But if cannot the R5C841 asserts SERR and transmits errors to the system 4 6 4 CardBus System Error Having the asserted CSERR on the secondary CardBus interface the R5C841 always asserts SERRE on the primary PCI interface and transmits errors to the system 4 6 5 PCI Bus Error concerned with 1394 O
54. a interface 3 0 3 3 3 6 V block block RICOH 2004 Rev 1 10 5 1 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 2 2 PCI Interface For 3 3V signaling 1 65 1 95V 3 0 3 6 Ta 0 70 C Output High Voltage 0 9xVCC_PCI3V i ee lout 500WA VOL Output Low Voltage 2 lout 1500uA Input Leakage Current 10 Vin 0 pem PCI3V Input Pin Capacitance _ Input Pin Capacitance _ tenes Note 1 Applied for PCICLK CLKRUN PCIRST AD 31 0 C BE 3 0 FRAME IRDY TRDY STOP DEVSEL IDSEL PERR SERR REQ GNT INTA INTB INTC pins 5 2 3 16 bit PC Card Interface For 3 3V signaling VCC_ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta 0 70 C symbot Parameter Typ Max __ Unt TestGonditon T __ MN wr 20 55 a vu foron pa 99 vom 24 v meam 2 vom output kia Vote 24 288 E IIL1 Input Leakage Current Vin 0 Pull up cn Note 2 Applied for CADR 25 0 15 0 2 1 IORZ OE WE WAIT if Card interface is configured as a 16 bit Card Socket Note 3 Applied for RESET pin Note 4 Applied for RDY IREQ BVD1 S
55. ad Write of 1394 PHY Registers The R5C841 builds in the 1394 PHY registers compliant with IEEE 1394 1995 and IEEE1394a 2000 standard Refer to the 1394PHY Registers for details Access to these registers is enabled by the PHY Control register of the 1394 OHCI Registers and offsetting 31 11 bits of the 1394 OHCI Register Base Address 10h in the 1394 Configuration register space enables access to the PHY Control register OECh The data of 1394 PHY register is the little endian description On access of the PHY Control register the R5C841 converts the data from a little endian to a bit endian So the data is dealt only in a row without the bit number of data PHY Register 0 1112 5 6 7 PHY Control Daa 0 23222120 16 2 19 2004 REv 1 10 4 24 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Card Data Sheet For example when 53h is written in wrData of the PHY Control register bit 6 4 1 and 0 are set to 717 53h is written in the PHY Register as they bit 1 3 6 and 7 are set to 1 Access to Contender bit Power class field and Disable bit for PortO Port1 in the 1394 PHY register is enabled through the PHY Shadow register 99h in the 1394 configuration register space Refer to the PHY Shadow register in the Registers Description for details 4 22 5 Clock Circuit The PHY block of the R5C841 requires 24 576MHz of clock frequency
56. alities under relevant laws or regulations before exporting or otherwise taking out of your country the products or the technical information described herein 4 The technical information described in this Data Sheet shows typical characteristics of and example application circuits for the products The release of such information is not to be construed as a warranty of or a grant of license under Ricoh s or any third party s intellectual property rights or any other rights 5 The products listed in this Data Sheet are intended and designed for use as general electronic components in standard applications office equipment computer equipment measuring instruments consumer electronic products amusement equipment etc Those customers intending to use a product in an application requiring extreme quality and reliability for example in a highly specific application where the failure or miss operation of the product could result in human injury or death aircraft spacevehicle nuclear reactor control system traffic control system automotive and transportation equipment combustion equipment safety devices life support system etc should first contact us 6 We are making our continuous effort to improve the quality and reliability of our products but semiconductor products are likely to fail with certain probability In order prevent any injury to persons or damages to property resulting from such failure customers should be careful en
57. and only PME can be asserted Event Source Card Detect Change R5C841 Ready Busy change card Battery Warning card Ring Indicate Card Status Change card 1394 LINKON R5C841 SD Card Detect Change R5C841 Memory Stick Detect Change R5C841 xD Picture Card Detect Change R5C841 4 11 1 Function on PC Card The maximum powered state All PCI transactions are acceptable CardBus CLK is output CardBus CLK is stopped by the protocol of CLKRUN Only the PCI Configuration Space access is allowed while the power and clock are provided CardBus CLK is stopped compulsorily If CardBus card is inserted CardBus RESET is asserted at the same time this state is set When the function is brought back to the DO state the reset is automatically performed regardless of the assertion of PCIRST PCI interface is disabled when reset CardBus interface is reset by the assertion of CRST on CardBus card PCI CardBus Bridge defines D3cold state is to change from VCC_ROUT 3V and to the auxiliary power source The R5C841 supports power management events from D3cold with the auxiliary power source The R5C841 can generate PME even in D3cold state without PCI clock if the event source is Card Detect Change or Ring Indicate in case of an internal regulator disabled RICOH 2004 REv 1 10 4 10 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Card Data Sheet On the software suspend mode the interface si
58. ard Sas Change UOIOOSINTAR Dd aoea 7 m cewemeowcwmeeunoesmTM Dem o e SSS m SPKROUTDeAy Note1 Tcyc is PCICLK cycle time Typically 30ns System Signals Timing 456 STSCHG RI t5b t5c gt Card Status Change IREQ CINT IRQ3 15 Y INTA RI_OUT SPKR CAUDIO t5e tbe SPKROUT System Signals Timing RICOH 2004 Rev 1 10 5 9 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 3 3 16 bit PC Card Interface signals Memory Read VCC_ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta 0 70 C Syms Parameter ______ Unt CADR 25 0 REG CE 2 1 Time CADR 25 0 REG and CE Tsu 20 2 1 before OE Low Tsu ae RM Hold Time CADR 25 0 REG and CE Thl 10 2 1 after OE High Thl ire Programmable Pulse Duration OE Low Tpw 20 1 2 Tpw 3 31Tcyc Programmable CDATA 15 0 ________ ea Hots Tine OFF 1 ps vate Dey _ 9 Note1 Tcyc is PCICLK cycle time Typically 30ns Note2 Tsu Tpw can be programmed by setting 16 bit Memory Timing register 16 bit Card Memory Read Timing PONS ce ee RA
59. ccess is selected when this signal and common memory access is selected when this signal is high READY 16 bit Card READY BUSY or INTERRUPT REQUEST This signal has two different IREQ functions READY BUSY input on the memory PC card and IREQ input on the I O card 16 bit WRITE PROTECT CARD IS 16 BIT PORT This signal has two different 101516 functions Write Protect Switch input the memory 101516 input on the card RESET OUT TS 16 bit Card CARD RESET WAIT p 16 bit Card BUS CYCLE WAIT BVD1 16 bit Card BATTERY VOLTAGE DETECT 1 or STATUS CHANGE This signal has STSCHGZ three different functions The battery voltage detect input 1 on the memory PC card and Card Status Change Ring Indicate input on the I O card BVD2 16 bit Card BATTERY VOLTAGE DETECT 2 or DIGITAL AUDIO or LED INPUT This SPKR signal has three different functions The battery voltage detect input 2 on the memory LED card and SPEAKER input or LED input on the I O card INPACK EX 16 bit Card INPUT ACKNOWLEDGE 16 bit Card CARD DETECT 1 CD 2 1 pins are used to detect the card insertion CD 2 1 pins are used in conjunction with VS 2 1 to decode card type information 16 bit Card CARD DETECT 2 CD 2 1 pins are used to detect the card insertion CD 2 1 pins are used in conjunction with VS 2 1 to decode card type information 16 bit Card CARD VOLTAGE CA
60. ction On D2 and D3 states the PHY can be set to any one of the following low power consumption by Software Doze Mode Sleep Mode Select Condition All of Ports status is set to Disconnected Disabled or Suspended Resume Time less than 200ns less than 10ms Doze Mode Stopping clock of the PHY digital block and getting the Cable Interface s power down enables the low power consumption Sleep Mode In addition to the low power consumption by Doze mode getting power down of PLL and the oscillator enables the lower power consumption than on Doze mode Setting D2PhyPM bit or D3PhyPM bit on the PHY Power Management register the 1394 OHCI LINK Configuration register addr 98h enables a selection of Doze mode or Sleep mode On Doze mode or Sleep mode LinkOn event enables to resume from the power saving mode automatically and PME is asserted Each power saving modes cannot be set without the above selected conditions even if the R5C841 is set to D2 state or D3 state If the above Ports conditions are not satisfied the R5C841 transacts as the Repeater PHY In this time setting D2ForcePM bit or D3ForcePM bit to 1b enables to ignore above conditions and to set Doze mode or Sleep mode automatically But it is disabled LinkOn event to resume from the power consumption mode automatically and to assert PME Writing into Power State bits enables to return to DO state In addition don t the power supply of VCC_RIN VCC_ROUT VCC_3V VCC_MD
61. e 7 we Stew Rate lv os vw ws Stew Rate o ve CCLK Timing and CardBus Signals Slew Rate t10a gt t10c t10b gt CCLK 0 475Vcc Other CardBus Signals 0 325Vcc t10g t10f gt 4 CCLK Timing and CardBus Slew Rate Card Reset VCC_ROUT 1 65 1 95V 3 3 0 3 6 Ta 0 70 C _ Win T unt Now ita Paa Owain s um Seu f CardBus Reset Timing t11a CRST t11b aon LS LS NN CardBus Reset Timing RICOH 2004 Rev 1 10 5 14 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet Card Output VCC_ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta 0 70 C Syme Paramotor une CAD 31 0 CC BE 3 0 CPAR CFRAME CDEVSEL CIRDY CTRDY CSTOP CPERR CSERR CCLKRUN CGNT t12a Valid delay time from CCLK Min CL 0 pF Max CL 30 t12b Enable Time Hi Z to active delay from CCLK CardBus Interface Output Signals Timing 0 4Vcc CCLK eM uu t12a Min gt OUTPUT 0 475Vcc J 0 325Vcc lt t12a Max t12b OUTPUT 0 4Vcc t12c lt gt CardBus Interface Output
62. e 1 Pin Name 2 CE2 MDIOO8 WEZ MDIOO9 CADRO MDIO10 CADR1 MDIO11 CADR2 MDIO12 CADR3 MDIO13 RICOH 2004 REv 1 10 4 28 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 ELECTRICAL CHARACTERISTICS 5 1 Absolute Maximum Rating Ambient Temperature under bias 40 85 Storage Temperature Range 55 125 ee pe ESD1 Human Body Model 320 100 1 5kQ ESD2 Charged Device Model Note 1 Applied for VCC_ROUT Note 2 Applied for VCC_RIN Note 3 The clamping voltage of the trigger pulse power source should be below a value of Vte Note 4 Applied for all of Digital pins Note Stresses above those listed may cause permanent damage to system components These are stress ratings only Functional operation at these or any conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect system reliability 5 2 DC Characteristics 5 2 1 Recommended Operating Conditions for Power Supply oe PCI3V Supply Voltage for PCI interface 3 3V Operation VCC_RIN Supply Voltage for Regulator VCC_RIN Supply Voltage for Core Logic 65 1 8 1 95 VCC_ROUT Disabled regulator 1 8V Operation VCC_3V Supply Voltage for System and 5 j Card Interface Signals VCC MD3V Supply Voltage for Medi
63. e Up by CSTSCHG Support an internal regulator to convert the 3 3V power into the power for the internal core logic Support Zoomed Video Port Bypass type Support PC Card LED 1394 LED SD LED Memory Stick LED and xD Picture Card LED Support BAY function with the PC Card passive adapter Pin Compatible With R5C811 CSP1616 208 R5C821 CSP1616 208 R5C821PA CSP1616 208 R5C851 CSP1616 208 R5C851PA CSP1616 208 Package 208pin CSP size 16x16mm pitch 0 8mm t 1 4mm RICOH 2004 1 10 1 2 2 BLOCK DIAGRAM R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet R5C841 Block Diagram REQ Socket Func 0 _ IDSEL CREO P AD 31 0 PCI CardBus CONTR __ Address Interface CCLKRUNE P PAR PCI Decode FRAME amp Master amp _ CADIST0 y Interface CC BE 3 0 DEVSEL Mapping Target P IRDY gt TRDY 16 bit OFRAMER STOP Interface ECDEVSELH ty PERR CIRDY lt 4 SERR Master COIRDYR y PCICLK PCI to Card CPERR PCIRST CSERR amp gt GBRST 4 RWSPND Mese oe Manage Status amp CVS1 2 Control CSTSCHG EO em oc INTB ADDR DAT Interrupt A CAUDIO 455180905100 8 Buffer Socket 00101 00105 Audio adito Pel eo
64. e registers are initialized by the power state transition from D3 to DO as long as the power state is D3 RICOH 2004 REv 1 10 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Data Sheet Reset Sequence Follow the sequence for initialization when a power is on 1 Supply a power to AVCC_PHY3V and VCC_ROUT in case of an internal regulator disabled Supply a power to Deassert GBRST Deassert HWSPND Deassert PCIRST PCLK has to be supplied for 100usec 33MHz before deasserting PCIRST Qua orm Following Step3 by Step2 has no problem See the timing a detail of the timing shown in Chapter 5 3 6 4 11 Power Management The R5C841 implements two kinds of power management software suspend mode and hardware suspend mode in order to reduce the power consumption on suspend in addition to the adoption of circuit to reduce the power consumption when power on The software suspend mode conforms to the ACPI Advanced Configuration and Power Interface specification and the PCI Bus Power Management Standard The R5C841 as a PCI device implements four power states of DO D1 D2 and D3 Each power state on the PC Card is the following The power management events for the R5C841 and their sources are listed below The PME source supports the Card Detect Change event only When the power state is except DO the interrupt is disabled
65. ecommended circuit diagram Regulator Disable Mode from Regulator 0 01uF 0 1uF O 01uF 10uF 1 8V nb 5 841 0 01 0 01uF 0 47 0 47uF VCC_ROUT X VCC_RIN short REGEN py ORegulator Enable Mode from Regulator 3 3V 0 014 O 1uF 0O 01uF 10uF 0 47uF 0 47uF VCC_RIN R5C841 0 01uF 0 01uF RICOH 2004 REv 1 10 4 27 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 4 25 ExpressCard Interface Using the external USB host interface enables the R5C841 to connect a USB device to a PC Card socket That is inserting an ExpressCard passive adapter into the PC Card socket can support an ExpressCard for the USB interface R5C841 ExpressCard Passive Adapter USB HOST ____ ExpressCard 4 26 BAY Function With the PC Card passive adapter the Small Card the SD Card the Memory Stick the xD Picture Card can be inserted in the PC Card slot To enable this function set 1 in PCl CardBus Bridge Configuration register B7 0 Internal Bay Mode Set PCI CardBus Bridge Configuration register AO 14 to 1 in order to use the External BAY function External Bay Mode You can also set these registers by using Serial ROM use the External Bay Mode you also need to wire the 6 pins of Pin Name 1 to the 6 pins of Pin Name 2 respectively Pin Nam
66. ed at 3 3V The SD Card Interface the Memory Stick interface and the xD Picture Card interface VCC_3V and are powered at 3 3V 2004 REv 1 10 4 7 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Data Sheet 4 10 Reset Event Anytime GBRST is asserted all R5C841 internal state machines are reset and all registers are set to their default values provided that each signals has followed the reset sequence below PCIRST is asserted all registers are set to their default value except the following The default values of each register are described in each register description 1 These registers are initialized only by GBRST not by PCIRST PCI RESET Resistant register PCI CardBus Bridge Config Space 40h Subsystem Vendor ID 15 0 42h Subsystem ID 15 0 80h Bridge Configuration 15 0 82h PC Card Misc Control 15 0 84h 16 bit Interface Control 15 0 88h 16 bit Timing 0 15 0 16 bit Memory Timing 0 15 0 Func Disable Write Key 15 0 AOh PC Card Misc Control 2 15 0 A2h PC Card Misc Control 3 15 0 A4h PC Card Misc Control 4 31 0 BOh PC Card Misc Control 5 31 0 B4h PC Card Misc Control 6 23 0 B7h Function Disable 7 0 B8h Serial ROM Control 31 0 COh Writable Subsystem Vendor ID 15 0 C2h Writable Subsystem ID 15 0 1394 OHCI LINK Config Space 2Ch Subsystem Vendor ID 15 0 2Eh Subsystem ID 15 0
67. gnals on the PC Card keep to the following levels when the card is inserted CardBus CCLK low CPAR low CAD high or low CCBE high or low CRST low CGNT high Pull up high Pull down low 16 bit CDATA hi z CADR low Other pins keep the level before the software suspend mode In addition to the Operating system directed power management like ACPI the R5C841 can control to stop or slow the clock by supporting CLKRUN CCLKRUN protocol Therefore it is possible to reduce the power consumption The state of the card interface signals is the same as the software suspend mode The hardware suspend mode is enabled when HWSPND is asserted Once HWSPND is asserted all PCI bus interface signals are disabled and can be powered off If PCIRST is asserted the internal registers of the R5C841 hold the data as long as ROUT 3V are in case of an internal regulator disabled 4 11 2 Function on 1394 OHCI LINK PME can be generated by PME EN after setting PME STS Ack tardy is returned on accesses from the 1394 The PCI configuration space the 1394 OHCI register and the GUID register are preserved Functional interrupts are masked Unmasked interrupts can be generated by PME EN after setting PME STS All transmit contexts must be inactive before it attempts to place the R5C841 into the D1 power state IEEE1394 bus manager shall not be placed into D1 Placing the
68. high impedance state The negation of PCIRST requires no bounds AD 31 0 ADDRESS AND DATA Address and Data are multiplexed on the same PCI pins C BE 3 0 BUS COMMAND AND BYTE ENABLES Bus Command and Byte Enables multiplexed on the same PCI pins During the address phase of transaction C BE 3 0 define the bus command During the data phase C BE 3 0 are used as Byte Enables The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data PAR PARITY Parity is even parity across AD 31 0 3 0 PAR is stable and valid one clock after the address phase For data phases PAR is stable and valid one clock after either IRDY is asserted on a write transaction or TRDY is asserted on a read transaction The master drives PAR for address and write data phases the target drives PAR for read data phases FRAME CYCLE FRAME This signal is driven by the current master to indicate the beginning s hiz and duration of an access is asserted to indicate a bus transaction is beginning While FRAME is asserted data transfers continue When FRAME is deasserted the transaction is in the final data phase or has complete TRDY y o TARGET READY This signal indicates the initialing agent s ability to complete the s h z current data phase of the transaction TRDY is used in conjunction with IRDY A data phase is completed on any clock both TRDY and IRDY a
69. idge SD Card Memory Stick xD Picture Card ExpressCard interface 1 slot Card 2 ports of IEEE1394 MDIOxx pins shared by SD Card Memory Stick and xD Picture Providing Ricoh s proprietary driver for Memory Stick xD Picture Card ExpressCard USB Interface Type supported by the Card passive adapter PCI Bus Interface Compliant with PCI Local Bus Specification2 3 The maximum frequency 33MHz PCI Master Target protocol support PCI configuration space for each function 3 3V Interface 5V tolerant CardBus PC card Bridge Compliant with PC Card Standard Release 8 1 Specification The maximum frequency 33MHz Support CardBus Master Target protocol Support Memory Write Posting Read Prefetching Transfer transactions memory read write transaction bi direction read write transaction bi direction Configuration read write transaction PCI 2 programmable memory windows 2 programmable I O windows PC Card 16 Bridge Compliant with Card Standard Release 8 1 16 bit Specification 5 programmable memory windows 2 programmable I O windows Compliant with i82365SL compatible register set ExCA Support Legacy 16 bit mode 3E0 ports RICOH 2004 1 10 1 1 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 1394 Interface Compliant with 1394 1995 Standard Specification and IEEE 1394
70. ime 3 4 Note 1 PCI Clocks Typ 30ns Command Active Time 6 80r18 Note 2 PCI Clocks Typ 30ns Address Hold Time 1 2 Note 3 PCI Clocks Typ 30ns Note1 clocks for 3 3v card attribute memory access Note2 8 PCI clocks for 5v card attribute memory access 18 PCI clocks for 3 3v card attribute memory access Note3 2 clocks for 3 3v card attribute memory access 2004 REv 1 10 4 3 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 4 5 Data Buffers Posting Write Prefetching Read The R5C841 provides data buffers address buffers and command buffers in order to maintain a high speed data transfer between the PCI bus and the CardBus The transaction from the PCI bus to the CardBus allows 8 DWORD buffers of Posting Write Data and Prefetching Read Data Conversely the transaction from the CardBus to the PCI bus allows 12 DWORD buffers of Posting Write Data and Prefetching Read Data Posting of write data is permitted a master to end writing data before a target s end of writing data The transactions that cross the R5C841 in either direction enable a high speed transfer The R5C841 provides a high speed data transfer by PCI burst transfers when Prefetching Read Data or Posting Write Data is implemented on the PCI bus and the 1394 bus Accesses to the SD Card the Memory Stick and the xD Picture Card do not support the PCI burst transfers 4 6 Error Support 4 6 1 Parity Error
71. m the CardBus Card to the PCI or to the other card also is enabled If the address of the transaction started on the CardBus is out of the address range it will be forwarded to the PCI On the 16 bit Card interface the transaction is implemented by two I O windows and five memory windows which are set by the 16 bit Card Status Control register and are compliant with the PCIC The address forwarding transaction is enabled only from PCI to CardBus 4 3 1 ISA Mode The R5C841 supports ISA mode for PCI CardBus Bridge function Setting ISA enable bit of the Bridge Control register enables the ISA mode The ISA mode is applied to the I O transaction of particular address range specified by the I O Base registers and the I O Limit registers which are also in the first 64K Byte of PCI space 0000 0000h 0000 FFFFh By enabled the ISA mode the I O transaction for the first 256 byte of each 1 Kbyte which start address are 0000x000h 0000x400h 0000x800h and 0000 00 are forwarded from PCI to CardBus The last 768 byte is blocked Conversely the I O transaction in the last 768 byte is forwarded from CardBus to PCI 2004 REv 1 10 4 2 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 4 3 2 VGA Support The R5C841 supports accesses to the CardBus interface bridge and the VGA compatible devices that is downstream of the bridge When the VGA Enable bit in the Bridge Control register is set the R5C841
72. ments PC Card Pin using BAY PC CARD PIN 1 68 ASSIGNMENTS CINES E Ae a 2e 9 eee Tt DBE tS ADS uoo Eo 6 ADS AAA AA ORNS CADO _ _ CAD eee Jo es to CAD2 __ 11 a CAD4 XDAE 12 98 1 COREE __ 13 14 4 l 16 READYIREQ 20 At e 5 2 __ __ 22 A7 XDCDAT 23 A68 CADO 6 24 XDCDAT 25 A4 _ 22 30 19 __ 1 in 3Bpu d a eee 33 weloisie CCLKRUN Be D eS 38 2 __ 39 e o 40 4 E EER ae pe io ee 44 1 JORDERFU ee eI 4 SIOWRHREU 2004 1 10 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet seer _ __ ve E 45 a 48
73. n active low tri state signal owned and driven by one and only one agent at a time The agent that drives an s h z pin low must drive it high for at least one clock before letting it float A new agent cannot start driving an s h z signal any sooner than one clock after the previous owner tri state is RICOH 2004 1 10 3 11 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 3 3 1 PCI Local Bus interface signals Dmm tye 71 PCI Bus Interface Pin Descriptions PCICLK PCI CLOCK PCICLK provides timing for all transactions on PCI All other PCI signals are sampled on the rising edge of PCICLK CLKRUN OD PCI CLOCK RUN This signal indicates the status of PCICLK and an open drain output to request the starting or speeding up of PCICLK This pin complies with Mobile specification If CLKRUN is not implemented then this pin should be tied low In this case CardBus clock is controlled by setting of StopClock bit included Socket Control Register This signal has no meaning for the PC Card16 Cards the CardBus Cards that does not support CCLKRUN and not insert Cards to socket During PCI bus reset is asserted this pin placed in a high impedance state And also refer to the chapter 4 21 for the LED output PCIRST PCI RESET This input is used to initialize all registers sequences and signals of the R5C841 to their reset states PCIRST causes the R5C841 to place all output buffers in a
74. o AVCC PHY3V because the only GBRST enables to initialize Cable interface Also sustain the delay time shown in the chapter 5 3 6 on use of GBRST b HWSPND is always set to Low 2004 REv 1 10 4 14 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Card Data Sheet 4 16 1394 OHCI The 1394 OHCI block in the R5C841 employs DMA engines for high performance data transfer host bus interface and FIFO The R5C841 supports two types of data transfer asynchronous and isochronous Prefer to the 1394 OHCI release 1 1 1 0 specifications for settings and procedures of the controller 4 16 1 Asynchronous Functions The R5C841 supports all of transmission and reception defined in 1394 packet formats Transmitted packets are read out of host memory and received packets are written into host memory both using DMA And the R5C841 can be programmed as a bus bridge between the host bus and the 1394 interface by the direct execution of the 1394 read write requests to the host bus memory space 4 16 2 Isochronous Functions The R5C841 includes the cycle master function as defined in the 1394 specification The cycle start packet is transferred at intervals of 8KHz cycle clock This cycle master uses the internal cycle clock When the R5C841 is not the cycle master R5C841 can sustain its internal cycle timer sychronized with the cycle master node by correcting its own cycle timer with the reload value from the cycle
75. ort at I O address 3E0 3E2 in order to maintain the backward compatibility like the Ricoh RF5C396 366 that is the Intel 82365 compatible device 1394 OHCI LINK Register Space The 1394 OHCI LINK registers are 2Kbyte of register compliant with the 1394 OHCI specifications The 1394 OHCI Register Base Address register points to the 2Kbyte memory mapped I O space These registers are used to control OHCI LINK and to set DMA context 1394 PHY Register Space The 1394 PHY registers are compliant with the IEEE1394a 2000 standard specifications These registers are used to set the PHY block ex the value of Gap count and are accessed through the PHY Control register in the 1394 OHCI LINK register space SD Card Control Register Space The SD Card Control registers compliant with the SD Host Controller Standard specification are 256byte of register assigned to control the SD card These registers are used to set for access to the SD card to give commands and to read write data These are placed in the memory mapped space by the SD Card Register Base Address register 2004 REv 1 10 4 1 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Data Sheet 4 1 8 Memory Stick Control Register Space The Memory Stick Control registers are 256byte of register assigned to control the Memory Stick These registers are used to set for access to the Memory Stick to give commands and to read write data These are placed
76. ough to incorporate safety measures in their design such as redundancy feature fire containment feature and fail safe feature We do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products Anti radiation design is not implemented in the products described in this Data Sheet Please contact Ricoh sales representatives should you have any questions or comments concerning the products or the technical information IRI GG Oe2004 REv 1 10 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet RICOH Company Ltd Electronic Devices Company Head Office 13 1 Himemurocho Ikeda shi Osaka 563 8501 JAPAN Phone 81 72 748 6262 Fax 81 72 753 2120 m Yokohama Office 3 2 3 Shinyokohama Kouhoku ku Yokohama shi Kanagawa 222 8530 JAPAN Phone 81 45 477 1703 Fax 81 45 477 1694 RICOH CORPORATION Electronic Devices Division Cupertino Office 4 Results Way Cupertino CA 95014 USA Phone 408 346 4463 1601 2004 REv 1 10
77. positively decodes and forwards accesses to VGA frame buffer addresses and accesses to VGA registers from PCI to CardBus interface The address range is as follows Memory address to OBFFFFh I O address AD 9 0 3BOh to 3BBh 3COh to 3DFh inclusive of ISA address aliases AD 15 10 are not decoded And also the R5C841 can forward only write transaction to the VGA Palette register of the following ranges Palette address AD 9 0 3C6h 3C8h and 3C9h Inclusive of ISA address aliases AD 15 10 are not decoded 4 4 16 bit Card Interface Timing Control The R5C841 generates the timing of address data and command for the 16 bit Card interface Each timing is set in a timer granularity of PCI clock as shown below When 16 bit I O enhanced Timing or 16 bit Memory Enhanced Timing bit in each socket control register space is cleared the default timing is selected regardless of the I O Win 0 1 Enhanced Timing bit or Memory Enhanced Timing bit Default timing is selected when the value smaller than the minimum value is set 16 bit Card Signal Timing Example LL CADR REG Address Setup Time Address Hold Time Command Active Time gt OE WE Y lOW IORZ CDATA Uso Paramor We Command 3 6 Focos AA Memory Read Write Address Setup T
78. quence is ON OFF the power sequence is ON 1 Supply to RIN and VCC ROUT 2 Supply to VCC_3V VCC_MD3V and AVCC PHY3V 3 Supply to the power sequence is OFF 1 Stop supplying to 2 Stop supplying to MD3V and AVCC PHY3V 3 Stop supplying to VCC_RIN in case of an internal regulator disabled On the power sequence is on sustain to timing of Global Reset Chapter 5 3 6 in regards to the control of HWSPND and GBRST GBRST must be specially asserted on the power supply to because the only GBRST enables to initialize the Cable interface block The rising of VCC_PCI3V should be within HWSPND asserted time When the power sequence is off the special limit for Delay Time is none The R5C841 can operate the PHY as Repeater Follow the power sequence when the R5C841 operates PHY as Repeater without providing On the power sequence is ON 1 Supply to RIN and ROUT 2 Supply to MD3V and AVCC PHY3V the power sequence is OFF 1 Stop supplying to and AVCC PHY3V 2 Stop supplying to RIN and ROUT in case of an internal regulator disabled In this case also the special limit for delay time is none on the power sequence is off Note the following a Asserting GBRST enables to supply power t
79. rdBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet ExpressCard 21 2 22 A7 8 ____ 23 A6 22 25 CAD 25 4 2 ___ 26 A3 CAD23 ____ 27 4 28 A1 05 29 A0 X CAD6 30 00 CAD7 31 oba f 33 WP OISTOR CCLKRUN 37 Dii CAD2 38 Da 44 39 3 CADO 9 ____ RU 41 015 42 ___ 4 46 7 6 as AA 48 9 49 0 y O 50 21 55 vee vee po 54 55 A24 7 56 aai 58 RESET 4 59 ___ CSERR 60 INPACKHRFU CREQR 61 62 SPKR BVD2 CAUDO 63 STSCHGHBVD1_ CSTSCHO 64 DB __ 65 CADO 66 010 1 68 GND QGND O RICOH 0200 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet Small Card Pin Assign
80. re sampled asserted During a read TRDY and IRDY are sampled asserted During a read TRDY indicates that valid data is present on AD 31 0 During a write it indicates the target is prepared to accept data Wait cycles are inserted both IRDY and TRDY are asserted together IRDY y o INITIATOR READY This signal indicates the initiating agent s ability to complete the s h z current data phase of the transaction IRDY is used in conjunction with TRDY A data phase is completed on any clock both TRDY and IRDY are sampled asserted During a write IRDY indicates that valid data is present on AD 31 0 During a read it indicates the target is prepared to accept data Wait cycles are inserted both IRDY and TRDY are asserted together STOP STOP This signal indicates the current target is requesting the master to stop the s hiz current transaction IDSEL INITIALIZATION DEVICE SELECT This signal is used as chips select during configuration read and write transactions DEVSEL DEVICE SELECT When actively driven indicates the driving device has decoded its s h z address as the target of the current access As an input DEVSEL indicates whether any device on the bus has been selected PERR PARITY ERROR This signal is only for the reporting of data parity errors during s h z transactions except a Special Cycle The R5C841 drives this output active low if it detects a data parity error during a write phase R
81. red Signal Valid delay time from PCICLK 2 11 ns Min CL 0 pF Max CL 50 pF 10 pF 3 3v Point to Point Signal Valid delay time from PCICLK Min CL 0 pF Max CL 50 pF 10 pF 3 3v PCI Output Signals Timing 1 5V 0 4Vcc PCICLK A 52991508180 t3d ptp OUTPUT Shared or ptp 1 5V 0 285Vcc Rise Edge 0 615Vcc Fall Edge OUTPUT t3c A v 5 0V Signaling 3 3V Signaling PCI Output Signals Timing PCI Interface Input Signals ROUT 1 65 1 95V VCC_PCI3V 3 0 3 6V Ta 0 70 C Wax um Now NE AD 31 0 C BE 3 0 PAR FRAME DEVSEL IRDY TRDY STOP IDSEL PERR SERR CLKRUN Setup Time Shared Signal Valid before PCICLK 7 __ on 4 Hold Time Shared Signal Hold Time after PCICLKHigh 0 t4c Setup Time Point to Point Signal Valid before PCICLK 10 ns PCI Input Signals Timing 4 5V 0 4Vcc ln t4a Shared t4b PCICLK INPUT 1 5V 0 4Vcc 5 0V Signaling 3 3V Signaling PCI Input Signals Timing RICOH 2004 Rev 1 10 5 8 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 3 2 System Interface signals System Interface Signals AC Characteristics VCC_ROUT 1 65 1 95V VCC_PCI3V 3 0 3 6V VCC_3V 3 0 3 6V Ta 0 70 C Parametr wa um os 02 RL OUT UDIOO 5 INTA m memommey J G
82. rent seoz speed Sora 25 UMEN mem fers Tesh Vole v Tobi OuputVorage 1665 205 v Sd Note 13 Applied for TPAPO 1 TPANO 1 pins Note 14 Applied for TPBPO 1 TPBNO 1 pins Note 15 Applied for TPBIASO 1 pins Note 16 Applied for CPS pin 5 2 7 UDIOO 5 pins For PCI 3 3V signaling ROUT 1 65 1 95V VCC_3V 3 0 3 6V Ta 0 70 C symbol Parameter mn max Unit Test condition Note von Ouputrighvotass __ 24 v Outputtowvotase em __ _7 Hoz Hrzouputteatege ten ua vouro vooay m v fe Du mueve os v Duc weewen Note 17 Applied for UDIOO 5 pins Note 18 Applied for UDIOO 4 pins RICOH 2004 Rev 1 10 5 4 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 5 2 8 SD Card Interface VCC_ROUT 1 65 1 95V VCC_MD3V 3 0 3 6V Ta 0 70 C Parameter typ Tuoi Test condition note VIH Input High Voltage 0 625x VCC_MD3V V 19 VCC_MD3V 0 3 VIL Input Low Voltage 0 3 0 25 V 19 VCC_MD3V Output High Voltage 0 75x lout 100LA 3V 19 20 MD3V Output Low Voltage p t25xvcc ITEM lout 1000AQ3V 19 20 Input Leakage Vin 0 Current Pull up 102 HI Z Output Leakage 10 uA Vout 0
83. s Card Interface Pin Characteristics PinName Dir PinName Dir SVtolerant PwrRail Drive ___ o __ _ 1 owe ____ omo o owe ____ wo _ ex o ow 7 o oos 7 ew o oom ____ wo ma Dow o ao ow ____ Lowe o ow oom 7 ama _ ___ o oo 7 9 1 o cw f wm LE oom o ceme 7 ama a wwe ______ jew em om wen oom oss cu 7 mw oen 7 o ____ 7 ama 1 E ERE DI jM UN RE o s ee o ow Co Gf wx ____ ev ____ ser oem oes 7 am _ Ew po joe Eee eem emm CADR1 CAD25 BVD2 SPKR PU CAUDIO PU
84. tached when PC Card Interface is configured as a CardBus Interface Mode 2 Pullup or Pulldown is configured according to the type of a card inserted 2004 1 10 3 7 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet Small Card Pin Assignments Pin Media SD Card Memory Stick xD Picture Card 1 XDCDOR ZS mon 7 2 1 4 mooo sow CCX 6 SDPWR xwa 8 mpoo MSEXCK 9 ms 15 XDCDAM 16 17 _ 18 XDODAT 19 1 20 XDAE ExpressCard Pin Assignments Card Pin PC CARD PIN 1 68 ASSIGNMENTS Pen ExpressCard 5 3 CAD eC 3 D CADi ____ 4 SCA __ ____ 5 06 CAS 6 7 8 Ai capo o 1 CADI2 __ ____ 11 4 12 48 13 CPAR 4 14 4 15 X 16 READY IREQH 18 19 6 cak 20 A15 2004 1 10 R5C841 PCI Ca
85. the data is read from the SD memory card the SD Card writes the divided data default 512byte into the SDDAT 3 0 of SD interface block after initialization of the SD Card by the command response signal 4 18 Memory Stick Interface The R5C841 has one port of Memory Stick interface consists of four serial data lines one bus state line card detection and MS clock 4 18 1 Protocol The Memory Stick interface block accesses to the Memory Stick registers and the Page Buffer by the Transfer Protocol Command TPC in compliance with the host The R5C841 checks transmission of data between the Page Buffer in the Memory Stick and the Flash Memory and a status after accepting INT signal of the Memory Stick After that the R5C841 starts to read write erase the data 4 19 xD Picture Card Interface The R5C841 has one port of xD Picture Card interface consists of eight serial data lines seven control signals and card detection RICOH 2004 REv 1 10 4 16 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD Express Card Data Sheet 4 19 1 Protocol The R5C841 accesses to the xD Picture Card through the 32 bit Data port register Writing to the Data port register can transfer address command and data to the xD Picture Card The data transfer to the xD Picture Card enables in units of 8 bit 16 bit or 32 bit On the 16 bit or 32 bit access R5C841 can access to the xD Picture Card by increments of 8 bit unit automatically Note that
86. together CSTOP y o CardBus Stop This signal indicates the current target is requesting the master to stop S h z the current transaction CDEVSEL y o CardBus Device Select This signal indicates the driving device has decoded its s h z address as the target of the current access when actively driven As an input CDEVSEL indicates whether any device on the bus has been selected CREQ CardBus Request This signal indicates to the arbiter that this agent desires use of the bus Every master has its own CREQ RICOH 2004 1 10 3 15 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet we O CardBus PC Card Interface Pin Descriptions Continued CGNT OUT CardBus Grant This signal indicates to the agent that access to the bus has been granted Every master has its own CGNT CPERR CardBus Parity Error This signal is only for the reporting of data parity errors during all S h z CardBus Card transactions except a Special Cycle An agent cannot report a CPERR until it has claimed the access by asserting CDEVSEL and completed a data phase CSERR CardBus System Error This signal is for reporting address parity errors data parity errors on the Special Cycle command any other system error where the result could be catastrophic CINT CardBus Interrupt Request This signal is an input signal from CardBus card It is level sensitive and asserted low negative true using
87. ues of 5V 3 3V and combination of them at the socket interface Card type can be known by reading the Socket Present State register Card Type CD2 CD1 VS2 VS1 Voltage I6bit PC Card T6bit PC Card SV and 33V X XV 16 PC Card ground connect to open connectto LV CardBus 3 3V CVS1 CCD1 PC Card 16bit Card 3 3 and connect to ground connect to ground LV CardBus 3 3 and CVS2 CCD2 PC Card connect to ground ground connect to LV CardBus 3 3 and CVS1 CCD2 PC Card X XV 16bit PC Card connect to ground connect to open LV CardBus CVS2 CCD2 PC Card ground connect to connect to open LV CardBus X XV and Y YV CVS2 CCD1 PC Card connect to ground open connect to LV CardBus CVS1 CCD2 PC Card ground connect to ground connect to Reserved CVS1 CCD1 ground connect to connect to ground Reserved CVS2 CCD1 connect to connect to connect to open ExpressCard CVS2 CVS2 CCD1 Small Card BAY CCD2 4 9 Mixed Voltage Operation The R5C841 has 5 independent power rails The power for Card VCC_3V and VCC PCI3V is powered at 3 3V The R5C841 can support either 3 3V the PCI and the PC Card as so the R5C841 s interface has the structure of 5V tolerant and VCC_ROUT are powered at 1 8V when an internal regulator disabled and VCC_RIN is powered at 3 3V when an internal regulator enabled The 1394 interface AVCC_PHY3V is power
88. ultiplexed on the same CardBus card pins A bus transaction consists of an address phase followed by one or more data phases CardBus card supports both read and write bursts CAD 31 0 contains a physical address 32 bits For I O this is a byte address for configuration and memory itis a DWORD address During data phases CAD 7 0 contains the east significant byte LSB and CAD 31 24 contains the most significant byte MSB Write data is stable and valid when CIRDY is asserted and read data is stable and valid when CTRDY is asserted Data is transferred during those clocks where both CIRDY and CTRDY are asserted CC BE 3 0 y o CardBus Command Bye Enables These signals are multiplexed on the same CardBus card pins During the address phase of a transaction CC BE 3 0 define the bus command During the data phase CC BE 3 0 are used as Byte Enables The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data CC BE 0 applies to byte 0 LSB and CC BE 3 applies to byte 3 MSB the current data phase CPAR has the same timing as CAD 31 0 but delayed by one clock The master drives CPAR for address and write data phases the target drives CPAR for read data phases CardBus Cycle Frame This signal is driven by the current master to indicate the beginning and duration a transaction is asserted to indicate that a bus transaction is beginning While CFRA
89. unctions for the PC Card socket the PCI IEEE1394 bridge function the SD Card interface the Memory Stick interface and the xD Picture Card interface Logically the R5C841 looks to the primary PCI as a separate secondary bus residing in a single device The PC Card the IEEE 1394 the SD Card the Memory Stick and the xD Picture Card have their own register spaces PCI Configuration Register Space The PCI Configuration registers are used to control the basic operations as settings and status control of the PCI device Each function has 256 byte of configuration space CardBus 32 bit Card Control Register Space The CardBus Card Control registers are used to manage status changed events remote wakeup events and status information about the PC Card in the socket These registers are used for PC Card 32 as well as PC Card 16 The PC Card Control Register Base Address register points to the 4 Kbyte memory mapped space that contains both the PC 32 and PC Card 16 Status and Control registers Socket Status Control Registers for Card 32 are placed in the lower 2Kbyte of the 4Kbyte and start at offset 000h 16 bit Card Control Register Space The Socket Status Control Registers for the PC Card 16 are placed in the upper 2Kbyte of the 4Kbyte pointed by the PC Card Control Register Base Address register and start at offset 800h 16 bit Legacy Port Legacy mode allows all 16 bit Card Control registers to be accessed through the index data p
90. xD ExpressCard Data Sheet xD Picture Card RN xD Picture CardData 7 0 xD Picture Card Data bus signals IN xD Picture Card Detect These signals indicate a detection of the xD Picture Card when two signals are set to Low by insertion of xD Picture Card XDWP MDIOO05 OUT xD Picture Card Write Protect This signal indicates the state of xD Picture Card s write protect This pin is connected to the WP signal of the xD Picture Card XDPWR MDIO04 OUT xD Picture Card Power Control This signal is provided to control the power supply for the xD Picture Card xD Picture R B xD Picture Ready Busy signal When this signal is low xD Picture Card is busy XDLED MDIOO6 OUT xD Picture Card LED Control This signal indicates an access state to the xD Picture Card XDWE MDIOO8 xD Picture Card Write Enable xD Picture Card Write Enable signal XDCE MDIO02 xD Picture Card Enable xD Picture Card Enable signal XDRE MDIO09 xD Picture Card Read Enable xD Picture Card Read Enable signal RICOH 2004 1 10 3 19 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 3 3 11 Power and GND signals memes tye Power Pin Descriptions REGEN Regulator Enable This pin controls an internal regulator Setting this pin to Low enables the internal regulator and setting this pin to High disables it PCI VCC Power Suppl
91. y pins for the PCI interface signals This pin can be powered at 3 3V VCC_3V PWR_ 3V VCC This supply pin is connected to 3 3V This pin must not be off on the suspend mode because of the power supply for PME and GBRST This pin supplies for a socket of the PC Card Controller also Media VCC Power Supply pins for the Media interface signals This pin can be powered at 3 3V VCC RIN Regulator Input Power supply input pins for an internal regulator This pin is connected to 3 3V when an internal regulator is enabled and to the same power as that of VCC_ROUT 1 8V when the regulator is disabled VCC ROUT Regulator Output Power supply output pins for an internal regulator and power supply pins for the internal core logic This pin is powered as an output from an internal regulator and as an input to the core logic when an internal regulator enabled and connected to 1 8V as input to the core logic when the regulator disabled Add bypass condensers between this pin and GND 1394 PHY Power supply for PHY analog block This pin can be powered at 3 3 Thig pin must not be off on the suspend mode because of the power supply for Cable interface block Digital GND Analog GND RICOH 2004 1 10 3 20 R5C841 PCI CardBus IEEE 1394 SD Card Memory Stick xD ExpressCard Data Sheet 4 FUNCTIONAL DESCRIPTION 4 1 Device Configuration The R5C841 supports PCl CardBus Bridge Interface f

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