Philips SAA7345 User's Manual
Contents
1. switching threshold voltage falling Vhys hysteresis voltage Repu input pull up resistance OV Ci input capacitance tiw reset pulse width a V 0 2Vbo V V 50 KQ ee PORE 1 us PORE only Digital outputs CL16 and CLA LOW level output voltage lot 1mA VoL VoH HIGH level output voltage loH 1 mA CL load capacitance tr output rise time 0 Pn e 3 C 20 pF note 1 tf output fall time Digital outputs V4 and V5 LOW level output voltage C 20 pF note 1 Vpp 4 5 to 5 5 V lot 10mA Vpp 3 4 to 5 5 V lot 5mA HIGH level output voltage Vpp 4 5 to 5 5 V lou 10mA Vpp2 3 4 V to 5 5 V Vpp 1 load capacitance output rise time 0 V 5 V V 5 V V pF ns ns V V V V pF ns output fall time Open drain output CFLG 4 DD 0 15 15 1 0 1 0 DD DD 0 15 15 C 20 pF note 1 C 20 pF note 1 ns VoL LOW level output voltage LOW level output current 50 pF lot L f C load capacitance t output fall time C 20 pF note 1 30 ns Open drain outputs KILL and V3 VoL LOW level output voltage lo 2 1 mA 0 0 4 V 50 CL load capacitance t output fall time C 20 pF note 1 1998 Feb 16 15 27 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 SYMBOL PARAMETER CONDITIONS 3 state outputs MISC SCLK WCLK DAT2. DPLL m 1 2Vpp 22nF ref 100 uA VSSA Veg JE ISLICE 2 D 100 RE Yop MGA368 1 Socii VSSA 100 uA Fig 3 Data slicer showing typical application components 1998 Feb 16 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 OTHER SUBCODE CHANNELS Write operation sequence Data of the other subcode channels Q to W may be read RAB is held LOW by the microcontroller to hold the via the V4 pin if the versatile pins interface register SAA7345 DA pin at high impedance address 1101 is set to XX01 Microcontroller data is clocked into the internal shift The format is similar to RS232 The subcode sync word is register on the LOW to HIGH clock transition CL formed by a pause of 200 us minimum Each subcode byte e Data D 3 0 is latched into the appropriate control starts with a logic 1 followed by 7 bits Q to W The gap register address bits A 3 0 on the LOW to HIGH between bytes is variable between 11 3 us and 90 us transition of RAB with CL HIGH The subcode data is also available in the EBU output e If more data is clocked into SAA7345 before the DOBM in a similar format LOW to HIGH transition of RAB then only the last 8 bits are used Microcontroller interface If less data is clocked into SAA7345 unpredictable operation will result If the LOW to HIGH transition of RAB occurs with CL LOW the command will be disregarded The SAA7345 has a 3
3. Xx x x x lt no interpolations at least one 1 sample interpolation FEE x a XIXI lt 1 Kx oj oj x Xx XI lt 1 lt x X oJ o XxX X X X Xx Xx x Xx x lt 4 o ABSOLUTE TIME SYNC The first flag bit F1 is the absolute time sync signal It is the FIFO passed subcode sync and relates the position of the subcode sync to the audio data DAC output The flag may be used for special purposes such as synchronization of different players FLAGS AT EBU OUTPUT The CFLG flags are available on bit 4 of the EBU data format when bit 3 of the EBU output control register address 1010 is set to logic 1 1998 Feb 16 at least one hold and no interpolations at least one hold and one 1 sample interpolation Double speed mode Double speed mode is programmed via the Speed control register address 1011 It is possible to program double speed independent of clock frequency but optimum performance is achieved with a 33 8688 MHz crystal or a ceramic resonator 25 Philips Semiconductors CMOS digital decoding IC with RAM for Product specification SAA7345 Compact Disc LIMITING VALUES In accordance with the Absolute Maximum Rating System IEC 134 SYMBOL PARAMETER CONDITIONS MIN MAX UNIT supply voltage 6 5 V maximum input voltage output voltage 46 5 V output current continuous operating ambient temperature 40 485 C storage temperature 55 electrostatic h
4. from digital servo XXXO0 input may be read via status register address 0010 data X101 V2 4 input input may be read via status register address 0010 data X110 V3 26 output 1100 XXOX kill output for right channel X01X output logic 0 X11X output logic 1 V4 25 output 1101 0000 4 line motor drive using V4 and V5 XX01 Q to W subcode output XX10 output logic 0 XX11 output logic 1 V5 24 output 1101 01XX de emphasis output active HIGH 10XX output logic 0 11XX output logic 1 1998 Feb 16 24 Philips Semiconductors CMOS digital decoding IC with RAM for Compact Disc Flags Output CFLG open drain output Product specification SAA7345 A 1 bit flag signal is available at the CFLG pin This signal shows the status of the error corrector and interpolator and is updated every frame 7 35 kHz gt us ka CFLG Table 11 Meaning of flag bits n N F7 n n A 45 4 us MGA370 Fig 22 Flags output timing gt x lt ig o MEANING no absolute time sync absolute time sync C1 frame contained no errors E C1 frame contained 1 error C1 frame contained 2 errors C1 frame non correctable C2 frame contained no errors C2 frame contained 1 error C2 frame contained 2 errors C2 frame non correctable A i o o X X X Xx Xx Xx x x Xx x lt o X X X X Xx x
5. 37 Kohnan 2 chome Minato ku TOKYO 108 Tel 81 3 3740 5130 Fax 81 3 3740 5077 Korea Philips House 260 199 Itaewon dong Yongsan ku SEOUL Tel 82 2 709 1412 Fax 82 2 709 1415 Malaysia No 76 Jalan Universiti 46200 PETALING JAYA SELANGOR Tel 60 3 750 5214 Fax 60 3 757 4880 Mexico 5900 Gateway East Suite 200 EL PASO TEXAS 79905 Tel 49 5 800 234 7381 Middle East see Italy For all other countries apply to Philips Semiconductors International Marketing amp Sales Communications Building BE p P O Box 218 5600 MD EINDHOVEN The Netherlands Fax 31 40 27 24825 Philips Electronics N V 1998 a worldwide company Netherlands Postbus 90050 5600 PB EINDHOVEN Bldg VB Tel 31 40 27 82785 Fax 31 40 27 88399 New Zealand 2 Wagener Place C P O Box 1041 AUCKLAND Tel 64 9 849 4160 Fax 64 9 849 7811 Norway Box 1 Manglerud 0612 OSLO Tel 47 22 74 8000 Fax 47 22 74 8341 Philippines Philips Semiconductors Philippines Inc 106 Valero St Salcedo Village P O Box 2108 MCC MAKATI Metro MANILA Tel 63 2 816 6380 Fax 63 2 817 3474 Poland UI Lukiska 10 PL 04 123 WARSZAWA Tel 48 22 612 2831 Fax 48 22 612 2327 Portugal see Spain Romania see Italy Russia Philips Russia Ul Usatcheva 35A 119048 MOSCOW Tel 7 095 755 6918 Fax 7 095 755 6919 Singapore Lorong 1 Toa Payoh SINGAPORE 1231 Tel 65 350 2538 Fax 65 251 6500 Slovakia see Austria Sl
6. current feedback output from data slicer ISLICE HFIN HFREF IREF VDDA comparator signal input comparator common mode input 10 reference current pin nominally Va Vpp 11 analog supply voltage note 1 12 13 14 15 analog ground note 1 CRIN CROUT Vpp1 crystal resonator input crystal resonator output digital supply to input and output buffers note 1 16 digital ground to input and output buffers note 1 17 16 9344 MHz system clock output 18 general purpose DAC output 3 state 19 serial data output 3 state 20 word clock output 3 state SCLK 21 serial bit clock output 3 state MOTO1 22 motor output 1 versatile 3 state MOTO2 23 motor output 2 versatile 3 state 24 versatile output pin CL16 MISC DATA WCLK V4 25 versatile output pin V versatile output pin open drain 3 26 KILL 27 kill output programmable open drain PORE power on reset enable input active LOW CLA 29 4 2336 MHz microcontroller clock output CL 31 interface clock input line RAB 32 interface R W and acknowledge input CFLG 33 correction flag output open drain ii Cc n c 34 to 42 no internal connection Vppo 44 digital supply voltage to internal logic note 1 Note 1 All supply pins must be connected to the same external power supply 1998 Feb 16 4 Philips Semiconductors CMOS digital decoding IC with RAM for Compact Disc 1998 Feb 16 CL11 DOBM V1
7. line microcontroller interface which is compatible with the digital servo IC TDA1301 WRITING DATA TO SAA7345 The SAA7345 has thirteen 4 bit programmable configuration registers as shown in Table 2 These can be written to via the microcontroller interface using the protocol shown in Fig 5 200 us 11 3 11 3 us min min m us s 90 us max gt TIES MGA369 Fig 4 Subcode format and timing at V4 pin RAB microcontroller i a i i a microcontroller DA microcontroller AS D1 X DO DA SAA7345 Ar high impedance MGA379 1 Fig 5 Microcontroller WRITE timing 1998 Feb 16 7 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 WRITING DATA TO SAA7345 REPEAT MODE The same command can be repeated several times e g for fade function by applying extra RAB pulses as shown in Fig 6 RAB microcontroller o EEE e 7 8 microcontroller DA microcontroller A3 D1 DO DA SAA7345 high impedance MGA380 1 Note that CL must stay HIGH between RAB pulses Fig 6 Microcontroller WRITE timing repeat mode READING STATUS INFORMATION FROM SAA7345 There are several internal status signals which can be made available on the DA line Table 1 Table 1 Internal status signals SIGNAL DESCRIPTION SUBQREADY LOW if new subcode word is ready in Q channel register MOTSTART1 HIGH if motor
8. standby 2 CD PAUSE mode note 1 XX11 operating mode Versatile pins interface 1100 XXX1 off track input at V1 XXXO no off track input V1 may be read via status Reset XXOX Kill L at KILL output Kill R at V3 output X01X V3 0 single Kil output Reset X11X V321 single Kill output 1998 Feb 16 13 Philips Semiconductors CMOS digital decoding IC with RAM for Compact Disc REGISTER ADDRESS Product specification SAA7345 FUNCTION INITIAL 1101 Versatile pins interface 4 line motor using V4 V5 Q to W subcode at V4 V4 0 V4 1 de emphasis signal at V5 Note 1 Standby modes CL DA and RAB normal operation a MISC SCLK WCLK DATA CL11 and DOBM 3 state b CRIN CROUT CL16 and CLA normal operation c V1 V2 V3 V4 and V5 normal operation d e Error corrector The error corrector carries outt 2 e 0 error corrections on both C1 32 symbol and C2 28 symbol frames Four symbols are used from each frame as parity symbols The strategy t 2 e 0 means that the error corrector can correct two erroneous symbols per frame and detect all erroneous frames The error corrector also contains a flag controller Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good C1 generates output flags which are read after de interleaving by C2 to help in the generation of C2 output flags The C2 output f
9. v2 TEST2 TEST1 ISLICE HFIN HFREF IREF Pins 34 to 42 inclusive have no internal connection VpDA SAA7345 Ro Se ee euo 62e g a8 a gt Offs gt 9 O Fig 2 Pin configuration MISC DATA WCLK SCLK MOTO1 Product specification SAA7345 CFLG RAB CL DA CLA PORE KILL v3 V4 V5 MOTO2 MGA359 1 Product specification Philips Semiconductors CMOS digital decoding IC with RAM for Compact Disc FUNCTIONAL DESCRIPTION Demodulator FRAME SYNC PROTECTION This circuit will detect the frame synchronization signals Two synchronization counters are used in the SAA7345 1 The coincidence counter which is used to detect the coincidence of successive syncs It generates a Sync coincidence signal if 2 syncs are 588 1 EFM clocks apart 2 The main counter is used to partition the EFM signal into 17 bit words This counter is reset when a A Sync coincidence is generated b A sync is found within 6 EFM clocks of its expected position The Sync coincidence signal is also used to generate the Lock signal which will go active HIGH when 1 Sync coincidence is found It will reset to LOW when during 61 consecutive frames no Sync coincidence is found This Lock signal is accessed via the status signal when the status control register address 0010 is set to X100 See section on Microcontroller interface Data Slicer and Clock Regenerator The SAA7345 has an integrated slic
10. 0 data X000 The signal will reduced to zero in up to 128 steps depending on the current position of the fade control taking a maximum of 3 ms Attenuation 12 dB is activated by sending the Attenuate command to the fade control register data X01X Attenuation and mute are cancelled by sending the Full Scale command to the fade control register data X001 It will take 3 ms to ramp the output from mute to the full scale level Fade The audio output level is determined by the value of the internal fade counter counter x maximum level Level e The counter is preset to 128 by the Full Scale command if no oversampling is required e The counter is preset to 120 0 5 dB scaling by the Full Scale command if either 2fs or 4f oversampling is programmed in the DAC output register address 001 1 e The counter is preset to 32 by the Attenuate command e The counter is preset to 0 by the Mute command 1998 Feb 16 To control the fade counter in a continuous way the step up and step down commands are available fade control register data X101 and X100 They will increment or decrement the counter by 1 for each register write operation e When issuing more than 1 step up or step down command in sequence the write repeat mode may be used see Fig 6 A pause of at least 22 us is necessary between any two Step up or step down commands When a step up command is given when the fade counter is alre
11. A and CL11 Vor _ tOWievel ouiputvotage ozim p pa V 1 HIGH level output voltage lou 1 mA Vpp 0 4 output rise time C 20 pF note 1 3 state leakage current Vi 0 to Vpp 3 state outputs MOTO1 MOTO2 and DOBM VoL LOW level output voltage Vpp 4 5 to 5 5 V loL 10 mA Vpp 3 4 to 5 5 V loL 5 mA HIGH level output voltage Vpp 4 5 to 5 5 V loH 10 mA Vpp 3 4 to 5 5 V loH 5 mA CL load capacitance 50 e eter fr ty output fall time C 20 pF note 1 10 3 state leakage current Vi 0 to Vpp 10 Digital input output DA si LOW level input voltage HIGH level input voltage 3 state leakage current Vi 0 to Vpp 10 Senan LOW level output voltage lo 1 mA load capacitance e earem aaa output fall time C 20 OF note 1 Sere oscillator input CRIN external clock Om mutual conductance at start up output resistance at start up input capacitance input leakage current Crystal oscillator output CROUT see Fig 26 fal crystal frequency feedback capacitance output capacitance 1998 Feb 16 28 Philips Semiconductors CMOS digital decoding IC with RAM for Compact Disc SYMBOL PARAMETER Product specification SAA7345 CONDITIONS I2S timing CLOCK OUTPUT SCLK see Fig 23 output clock period sample rate fs sample rate 2f sample rate 4f clock HIG
12. C deactivation during digital silence Double speed mode Compact Disc Read Only Memory CD ROM modes A single speed only version is available SAA7345GP SS QUICK REFERENCE DATA SYMBOL PARAMETER supply voltage supply current 22 crystal frequency 16 9344 or 33 8688 operating ambient temperature storage temperature ORDERING INFORMATION TYPE PACKAGE NUMBER DESCRIPTION VERSION SAA7345GP plastic quad flat package 44 leads lead length 2 35 mm body SOT205 1 14x 14x 2 2 mm 1998 Feb 16 2 Philips Semiconductors CMOS digital decoding IC with RAM for Product specification Compact Disc BLOCK DIAGRAM VppA VssA Vppi Vssi VDD2 Vss2 HFIN MOTO MOTOR HEBEF CONTROL MOTO2 ISLICE IREF a TEST 8 GAG TEST2 a N CRIN AUDIO CROUT PROCESSOR CLt1 SAA7345 CLA DOBM CL16 Q CHANNEL CRC CHECK SCLK CL Q CHANNEL PEAK REGISTER pETECT 1 WCLK DA i DATA RAB KILL MISC PORE 27 V1 v2 V3 V4 V5 KILL MGA371 2 Fig 1 Block diagram 1998 Feb 16 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for AA734 Compact Disc n m PINNING SYMBOL PIN DESCRIPTION 11 2896 or 5 6448 MHz clock output 3 state divide by 3 bi phase mark output externally buffered 3 state versatile input pin versatile input pin test input this pin should be tied LOW test input this pin should be tied LOW
13. H time clock LOW time sample rate fs sample rate 2f sample rate 4f sample rate fs sample rate 2f sample rate 4f set up time sample rate fs sample rate 2f sample rate 4f hold time CLOCK OUTPUT SCLK see Fig 23 sample rate fs sample rate 2f 48 sample rate 4f 24 output clock period clock HIGH time sample rate fs sample rate 2f 118 1 ns sample rate 4f 59 1 ns sample rate fs 83 sample rate 2f sample rate 4f clock LOW time sample rate fs 83 sample rate 4f 21 set up time hold time sample rate fs 48 sample rate 2f 24 sample rate 4f 12 sample rate fs 48 sample rate 2f sample rate 4f 1998 Feb 16 29 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 SYMBOL PARAMETER CONDITIONS Microcontroller interface timing see Figs 24 and 25 INPUTS CL AND RAB input LOW time single speed double speed 260 double speed 260 rise time single speed fall time double speed delay time RAB to DA valid delay time RAB to DA high impedance READ MODE propagation delay CL to DA single speed 700 double speed 340 WRITE MODE tsuD set up time DA to CL single speed note 2 double speed note 2 340 double speed double speed 140 delay ti
14. Hz lt 0 03 dB Table 4 Digital filter stopband characteristics STOPBAND ATTENUATION 24 kHz gt 25 dB 24 to 27 kHz 2 38 dB 27 to 35 kHz gt 40 dB 35 to 64 kHz 2 50 dB 64 to 68 kHz gt 31dB 68 kHz gt 35 dB 69 to 88 kHz gt 40 dB MGA385 20 magnitude dB 20 40 ES ZIN pon 0 10 20 30 40 50 frequency kHz Fig 12 Digital filter characteristics CONCEALMENT A 1 sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected The erroneous sample is replaced by a level midway between the preceding and following samples Left and right channels have independent interpolators If more than one consecutive non correctable sample is found the last good sample is held A 1 sample linear interpolation is then performed before the next good sample see Fig 13 1998 Feb 16 15 Philips Semiconductors CMOS digital decoding IC with RAM for Compact Disc Interpolation OK Error OK Error Product specification SAA7345 Interpolation Error Error OK OK MGA372 Fig 13 Concealment mechanism MuTE ATTENUATION AND FADE A digital level controller is present on the SAA7345 which performs the functions of soft mute attenuation and fade Mute and Attenuation Soft mute is activated by sending the Mute command to the fade control register address 000
15. INTEGRATED CIRCUITS DATA SHEET SAAT7345 CMOS digital decoding IC with RAM for Compact Disc Product specification 1998 Feb 16 Supersedes data of 1996 Jan 09 File under Integrated Circuits ICO1 Philips PHILIPS Semiconductors DH LI p Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc FEATURES GENERAL DESCRIPTION Integrated data slicer and clock regenerator The SAA7345 incorporates the CD signal processing Digital Phase Locked Loop PLL functions of decoding and digital filtering The device is equipped with on board SRAM and includes additional features to reduce the processing required in the analog domain Demodulator and Eight to Fourteen Modulation EFM decoding Subcoding microcontroller serial interface 3 Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Error correction and concealment functions Compact Disc application Embedded Static Random Access Memory SRAM for de interleave and First In First Out FIFO FIFO overflow concealment for rotational shock resistance Integrated programmable motor speed control Digital audio interface European Broadcasting Union EBU 2 to 4 times oversampling integrated digital filter Audio data peak level detection Versatile audio data serial interface Digital de emphasis filter Kill interface for Digital to Analog Converter DA
16. OTO2 Accelerate Brake MGA366 Fig 17 Motor 2 line PWM mode timing K NE J Vss MGA365 2 Fig 18 Motor 2 line PWM mode application diagram 1998 Feb 16 21 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 PWM MODE 4 LINE Using two extra outputs from the Versatile Pins Interface it is possible to use the SAA7345 with a 4 input motor bridge Figure 19 shows the timing and Fig 20 a typical application diagram trep 45 us ina Fi tdead 2 240 ns MOTO1 l MOTO2 l Va LLL v5 an tovi 240 ns MGA367 1 Accelerate Brake Fig 19 Motor 4 line PWM mode timing cd The n 10Q 100 nF MOTO1 D J MOTO2 Vss MGA364 2 Fig 20 Motor 4 line PWM mode application diagram CDV MODE In the CDV motor mode the FIFO position will be put in pulse width modulated form on the MOTO1 pin carrier frequency 300 Hz and the PLL frequency signal will be put in pulse density modulated form on the MOTO2 pin carrier frequency 4 23 MHz The integrated motor servo is disabled in this mode Remark The PWM signal on MOTO1 corresponds to a total memory space of 20 frames therefore the nominal FIFO position half full will result in a PWM ou
17. SION IEC JEDEC EIAJ PROJECTION SOT205 1 133E01A E 97 08 01 ISSUE DATE 1998 Feb 16 34 Philips Semiconductors CMOS digital decoding IC with RAM for Compact Disc SOLDERING Introduction There is no soldering method that is ideal for all IC packages Wave soldering is often preferred when through hole and surface mounted components are mixed on one printed circuit board However wave soldering is not always suitable for surface mounted ICs or for printed circuits with high population densities In these situations reflow soldering is often used This text gives a very brief insight to a complex technology A more in depth account of soldering ICs can be found in our IC Package Databook order code 9398 652 90011 Reflow soldering Reflow soldering techniques are suitable for all QFP packages The choice of heating method may be influenced by larger plastic QFP packages 44 leads or more If infrared or vapour phase heating is used and the large packages are not absolutely dry less than 0 1 moisture content by weight vaporization of the small amount of moisture in them can cause cracking of the plastic body For more information refer to the Drypack chapter in our Quality Reference Handbook order code 9397 750 00192 Reflow soldering requires solder paste a suspension of fine solder particles flux and binding agent to be applied to the printed circuit board by
18. ady at its full scale value the counter will not increment DAC Interface The SAA7345 is compatible with a wide range of Digital to Analog Converters Eleven formats are supported and are shown in Table 5 All formats are MSB first f is 44 1 kHz in single speed mode and 88 2 kHz in double speed mode Philips Semiconductors CMOS digital decoding IC with RAM for Product specification SAA7345 Compact Disc Table 5 DAC interface formats DAC CONTROL SAMPLE MODE REGISTER DATA FREQUENCY BITS SCLK MHz FORMAT INTERPOLATION 1010 f 2 1168 x n CD ROM I2S 1011 2 1168 xn CD ROM EIAJ O S fs 1110 fs S 0110 f 000X 4 2 1168 xn EIAJ 18 bits 8 4672 x n EIAJ 16 bits 010X 4 110X 4 o 1111 a f f f f f S S S 0011 2f 2fs f 16 16 18 18 16 18 1 4 2336 x n 8 4672 x n EIAJ 18 bits isse mers am m 4 2336 x n EIAJ 16 bits emen fence m 2 1168 x n Philips 12S 16 bits y y y y y y y no o es es es es es es es es es Philips 1 S 18 bits Note 1 n disc speed 2 EIAJ is the abbreviation for Electronic Industries Associated of Japan 1998 Feb 16 17 9I G84 8661 8L SCLK DATA LEFT CHANNEL DATA WCLK NORMAL POLARITY WCLK I MISC LSB VALID MSB VALID LSB VALID MSB VALID CD ROM MODE ONLY MGA383 Fig 14 Philips 1 S data for
19. andling 2000 2000 V electrostatic handling 200 Notes 1 All Vpp and Vss connections must be made externally to the same power supply 2 Equivalent to discharging a 100 pF capacitor via a 1 5 kO series resistor with a rise time of 15 ns 3 Equivalent to discharging a 200 pF capacitor via a 2 5 uH series inductor CHARACTERISTICS Vpp 3 4 to 5 5 V Vss 0 V Tamb 40 to 85 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Supply supply voltage 5 0 5 5 V Vpp Ipp supply current Analog Front End Vpp z 4 5 to 5 5 V comparator inputs HFIN and HFREF folk clock frequency 22 3 4 Vpp 5 V 3 50 mA 35 MHz Vin switching thresholds Analog Front End Vpp 3 4 to 5 5 V comparator inputs HFIN and HFREF folk clock frequency 8 n 1 2 Vpp 0 4 V 20 MHz Vipt Digital inputs CL and RAB HFIN input voltage level 8 E 1 0 V 0 3Vpp V Vpp 0 3 V Viu LOW level input voltage 0 3 Vin HIGH level input voltage 0 7Vpp IL input leakage current Vi 0 to Vpp 10 C input capacitance 1998 Feb 16 26 10 uA 10 pF Philips Semiconductors CMOS digital decoding IC with RAM for Compact Disc SYMBOL PARAMETER Product specification SAA7345 CONDITIONS Digital inputs PORE V1 and V2 Vihr switching threshold voltage rising Vint E E mw v
20. e level comparator which is clocked by the crystal frequency clock The slice level is controlled by an internal current source applied to an external capacitor under the control of the digital phase locked loop DPLL SAA7345 Regeneration of the bit clock is achieved with an internal fully digital PLL No external components are required and the bit clock is not output The PLL has two microcontroller control registers addresses 1000 and 1001 for bandwidth and equalization For certain applications an off track input is necessary If this flag is HIGH the SAA7345 will assume that the servo is following on the wrong track and will flag all incoming HF data as incorrect The off track is input via the V1 pin when the versatile pins interface register address 1100 bit 0 is set to logic 1 EFM demodulation The 14 bit EFM data and subcode words are decoded into 8 bit symbols Subcode data processing Q CHANNEL PROCESSING The 96 bit Q channel word is accumulated in an internal buffer Sixteen bits are used to perform a Cyclic Redundancy Check CRC If the data is good the SUBQREADY I signal will go LOW SUBQREADY can be read via the status signal when the status control register address 0010 is set to X000 normal reset condition Good Q channel data may be read via the microcontroller interface crystal clock HF 2 2 kQ HFIN V input IHH 1 2 2 nF 47 pF HFREF 250
21. e to limiting values for extended periods may affect device reliability Application information Where application information is given it is advisory and does not form part of the specification LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale 1998 Feb 16 36 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 NOTES 1998 Feb 16 37 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 NOTES 1998 Feb 16 38 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 NOTES 1998 Feb 16 39 Philips Semiconductors Argentina see South America Australia 34 Waterloo Road NORTH RYDE NSW 2113 Tel 61 2 9805 4455 Fax 61 2 9805 4466 Austria Computerstr 6 A 1101 WIEN P O Box 213 Tel 43 160 1010 Fax 43 160 101 1210 Belarus Hotel Minsk Business Center Bld 3 r 1211 Volodarski Str 6 220050 MINSK Tel 375 172 200 733 Fax 375 172 200 773 Belgium see The Netherlands Brazil see So
22. ead operation e SAA7345 will output consecutive subcode bits after each HIGH to LOW transition of CL e When enough subcode has been read 1 to 96 bits stop reading by pulling RAB LOW RAB microcontroller o apps E microcontroller Ir dq CRC pa saarsas ox fara XaaX Xaez asian m STATUS MN MGA382 1 Fig 8 SAA7345 Q channel subcode READ timing PEAK DETECTOR OUTPUT In place of the CRC bits bits 81 to 96 the peak detector information is added to the Q channel data The peak information corresponds to the highest audio level absolute value and is measured on positive peaks Only the most significant 8 bits of the peak level are given in unsigned notation Bits 81 to 88 contain the LEFT peak value bit 88 MSB and bits 89 to 96 contain the RIGHT channel bit 96 MSB Value is reset after reading Q channel data 1998 Feb 16 9 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc BEHAVIOUR OF THE SUBQREADY I SIGNAL SHARING THE MICROCONTROLLER INTERFACE When the CRC of the Q channel word is good and no When the RAB pin is held LOW by the microcontroller it is subcode is being read the SUBQREADY I signal willreact permitted to put any signal on the DA and CL lines as shown in Fig 9 SAA7345 will set output DA to high impedance Under this circumstance these lines may be used for another purpose e g TDA1301 microcontroller int
23. el control bits 0 to 3 bit 2 is logic 1 when copy permitted bit 3 is logic 1 when recording has pre emphasis Reserved mode 8to 15 Category code always zero CD bit 8 logic 1 all other bits logic 0 28 to 29 Clock accuracy set by EBU control register 00 Level Il 01 Level III 16 to 27 and 30 to 191 Remaining KILL circuit The KILL circuit detects digital silence by testing for an all zero or all ones data word in the left or right channel before the digital filter The output is switched active LOW when silence has been detected for at least 200 ms Two modes are available selected by the versatile pins register address 1100 1 PIN KILL MODE Active LOW signal on KILL pin when digital silence has been detected on both LEFT and RIGHT channels for 200 ms 2 PIN KILL MODE Independent digital silence detection for left and right channels The KILL pin is active LOW when digital silence has been detected in the LEFT channel for 200 ms and V3 is active LOW when digital silence has been detected in the RIGHT channel for 200 ms When MUTE is active then the KILL output is forced LOW Spindle motor control The spindle motor speed is controlled by a fully integrated digital servo Address information from the internal 8 frame FIFO and disc speed information are used to calculate the motor control output signals 1998 Feb 16 always zero Several output modes are supported 1 Pu
24. enuate X001 Full Scale X100 Step Down X101 Step Up Motor mode 0001 X000 Motor off mode Reset X001 Motor brake mode 1 X010 Motor brake mode 2 X011 Motor start mode 1 X100 Motor start mode 2 X101 Motor jump mode X111 Motor play mode X110 Motor jump mode 1 1XXX anti windup active OXXX anti windup off Reset Status control 0010 X000 status SUBQREADY Reset X001 status MOTSTART1 X010 status MOTSTART2 X011 status MOTSTOP X100 status PLL Lock X101 status V1 X110 status V2 X111 status MOTOR OV OXXX L channel first at DAC WCLK normal Reset 1XXX R channel first at DAC WCLK inverted 1998 Feb 16 11 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for AA734 Compact Disc a REGISTER ADDRESS FUNCTION INITIAL DAC output 0011 12S CD ROM mode EIAJ CD ROM mode 12S 4f mode 12S 2f mode 12S f mode EIAJ 16 bit 4f EIAJ 16 bit 2f EIAJ 16 bit fs EIAJ 18 bit 4f EIAJ 18 bit 2f EIAJ 18 bit fs Motor gain Motor gain G 3 2 Motor gain G 4 0 Motor gain G 6 4 Motor gain G 8 0 Motor gain G 12 8 Motor gain G 16 0 Motor gain G 25 6 Motor gain G 32 0 Motor bandwidth Motor f4 0 5 Hz Motor f4 0 7 Hz Motor f4 1 4 Hz Motor f4 2 8 Hz Motor f3 0 85 Hz Motor f3 1 71 Hz Motor f3 3 42 Hz Motor output configuration Motor power ma
25. erface Data and Clock line see Fig 11 When the CRC is good and subcode is being read the timing in Fig 10 applies If t4 SUBQREADY I LOW to end of subcode read is below 2 6 ms then t 13 1 ms i e the microcontroller can read all subcode frames if it completes the read operation within 2 6 ms after subcode ready If this criterion is not met it is only possible to guarantee that t3 will be below 26 2 ms approximately If subcode frames with failed CRCs are present the te and tg times will be increased by 13 1 ms for each defective subcode frame RAB microcontroller CL microcontroller l et high DA SAA7345 CRC OK CRC OK impedance 10 8 ms 15 4 ms 2 3 ms READ start allowed Fig 9 SUBQREADY I timing when no subcode is read MGA373 1 RAB microcontroller CL j M i it microcontroller LI L DA SAA7345 aXe Kos MGA374 1 Fig 10 SUBQREADY I timing when subcode is being read 1998 Feb 16 10 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 SAA7345 Vo O MICROCONTROLLER O O MGA361 1 Fig 11 SAA7345 microcontroller interface application diagram Table 2 Command registers The INITIAL column shows the power on reset state REGISTER ADDRESS DATA FUNCTION INITIAL Fade and Attenuation 0000 X000 Mute Reset X01 X Att
26. is turning at 75 or more of nominal speed MOTSTART2 HIGH if motor is turning at 50 or more of nominal speed MOTSTOP HIGH if motor is turning at 12 or less of nominal speed PLL Lock HIGH if Sync coincidence signals are found V2 Follows input on V2 pin The status signal to be output is selected by status control register address 0010 The timing for reading the status signal is shown in Fig 7 Status read operation sequence e Write appropriate data to register 0010 to select required status signal e With RAB LOW set CL LOW e Set RAB HIGH this will instruct the SAA7345 to output status signal on DA 1998 Feb 16 8 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 RAB a a microcontroller CL o LLL microcontroller DA microcontroller high impedance DA SAA7345 STATUS MGA381 1 Fig 7 SAA7345 status READ timing READING Q CHANNEL SUBCODE FROM SAA7345 To read Q channel subcode from SAA7345 the SUBQREADY I signal should be selected as status signal The subcode read timing is shown in Fig 8 Read subcode operation sequence e Monitor SUBQREADY I status signal When this signal is LOW and up to 2 3 ms after its LOW to HIGH transition it is permitted to read subcode e Set CL LOW SAA7345 will output first subcode bit Q1 e After subcode read starts the microcontroller may take as long as it wants to terminate r
27. lags are used by the interpolator for concealment of non correctable errors They are also output via the EBU signal DOBM and the MISC output with 12S for CD ROM applications The flags output pin CFLG provides information on the state of all error correction and concealment flags 1998 Feb 16 MOTO and MOTO2 in standby 2 CD PAUSE normal operation MOTO and MOTO2 in standby 1 CD STOP held LOW in PWM mode 3 state in PDM mode Audio functions DE EMPHASIS AND PHASE LINEARITY When de emphasis is detected in the Q channel subcode the digital filter automatically includes a de emphasis filter section When de emphasis is not required a phase compensation filter section controls the phase linearity of the digital oversampling filter to x 1 within the band 0 to 16 kHz DIGITAL OVERSAMPLING FILTER The SAA7345 contains a 2 to 4 times oversampling filter The filter specification of the 4 x oversampling filter is given in Table 2 and shown in Fig 12 These attenuations do not include the sample and hold at the DAC output or the DAC post filter When using the oversampling filter the output level is scaled 0 5 dB down to avoid overflow on full scale sinewave inputs 0 to 20 kHz Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 Table 3 Digital filter passband characteristics PASSBAND ATTENUATION 0 to 19 kHz lt 0 001 dB 19 to 20 k
28. lation flags when bit 3 of EBU control register is set to logic 1 Audio sample 8 to 27 first 4 bits not used always zero User data 29 used for subcode data Q to W control bits and category code 31 Parity bit even parity for bits 4 to 30 SYNC AUDIO SAMPLE The sync word is formed by violation of the biphase rule Left and right samples are transmitted alternately and therefore does not contain any data Its length is equivalent to 4 data bits The three different sync patterns VALIDITY FLAG Incl are thie GOlONI GO SIDON Audio samples are flagged bit 28 logic 1 if an error has Sync B been detected but was non correctable This flag remains Start of a block 384 words word contains left the same even if data is taken after concealment sample e Sync M USER DATA Word contains left sample no block start Subcode bits Q to W from the subcode section are e Sync W transmitted via the user data bit This data is asynchronous MUS with the block rate Word contains right sample 1998 Feb 16 19 Philips Semiconductors CMOS digital decoding IC with RAM for Compact Disc CHANNEL STATUS Product specification SAA7345 The channel status bit is the same for left and right words Therefore a block of 384 words contains 192 channel status bits The category code is always CD The bit assignment is shown in Table 8 Table 8 EBU channel status Control FUNCTION copy of CRC checked Q chann
29. lse Density 2 line true complement output 1 MHz sample frequency 2 PWM output 2 line 22 05 kHz modulation frequency 3 PWM output 4 line 22 05 kHz modulation frequency 4 CDV motor mode The modes are selected via the motor output configuration register address 0110 PuLsE DENSITY MODE In the Pulse Density mode the motor output pin MOTO1 is the pulse density modulated motor output signal A 5096 duty cycle corresponds with the motor not actuated higher duty cycles mean acceleration lower mean braking In this mode the MOTO2 signal is the inverse of the MOTO signal Both signals change state only on the edges of a 1 MHz internal clock signal Possible application diagrams are shown in Fig 16 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc MOTO1 a c MOTO2 10 nF i i3 o rt ih 10 nF T T SAA7345 yoa YSS Vss DD 22 KQ 22 KQ MOTO lt il Vss 22 KQ 10 nF T 22 KQ eL Vss YSS aka C Vpp MGA363 1 Fig 16 Motor pulse density application diagrams PWM MODE 2 LINE In the PWM mode the motor acceleration signal is put in pulse width modulation form on the MOTO 1 output and the motor braking signal is pulse width modulated on the MOTO 2 output Figure 17 shows the timing and Fig 18 a typical application diagram trep 45 us aa EE ldead 2 240 ns MOTO1 l M
30. mat 16 bit word length shown sek JUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUULI pata I To 17 IIIIIIIIIIILILILIILIIIo 9 17 TT TT TTT LEFT CHANNEL DATA wek o MISC MGA384 Fig 15 EIAJ data format 18 bit word length shown osi Pedwo JO NYH YIM 2 Buipooep erDip SOND GVELVVS SJojonpuooruleg sdi iud uoneouioeds 1onpoug Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 EBU interface The biphase mark digital output signal at pin DOBM is in accordance with the format defined by the IEC 958 specification Three different modes can be selected via the EBU output control register address 1010 Table 6 EBU output modes EBU CONTROL REGISTER DATA EBU OUTPUT AT DOBM PIN EBU VALIDITY FLAG BIT 28 XX11 DOBM pin held LOW XX00 data taken before concealment mute and fade HIGH if data is non correctable concealment flag XX10 data taken after concealment mute and fade HIGH if data is non correctable concealment flag FORMAT The digital audio output consists of 32 bit words subframes transmitted in biphase mark code two transitions for a logic 1 and one transition for a logic 0 Words are transmitted in blocks of 384 see Table 7 Table 7 EBU word format WORD BITS FUNCTION Sync 0 to 3 Auxiliary 4to7 not used normally zero Error flags 4 CFLG error and interpo
31. me DA high impedance MR to RAB 1 Timing reference voltage levels are 0 8 V and Vpp 0 8 V Notes 2 Negative set up time means that data may change after clock transition clock period tey MGA376 1 Fig 23 I S timing 1998 Feb 16 30 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 RAB CL DA SAA7345 high impedance MGA377 1 Fig 24 Microcontroller timing READ mode RAB CL DA microcontroller high impedance MGA378 1 Fig 25 Microcontroller timing WRITE mode 1998 Feb 16 31 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 APPLICATION INFORMATION CRIN 33 8688 MHz 3 3 8rd overtone ul CRYSTAL CROUT 1nF 10pF VDDA VSSA CRIN 16 9344 MHz CRYSTAL CROUT 33 pF VDDA VSSA t CRIN 33 8688 CERAMIC 100 GENERATOR r kQ CROUT z 5pF VDDA VSSA Fig 26 Application circuits for crystal oscillator 1998 Feb 16 32 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for i SAA7345 Compact Disc V C12 ds 47uF c3 C13 dai 63 V 100 nF clock output aa to DOBM transfo
32. ode 1 Start mode 2 Stop mode 1 and Stop If FIFO overflow occurs during Play mode e g as a result mode 2 a fixed positive or negative voltage is applied to of motor shock the FIFO will be automatically reset the motor This voltage can be programmed as a to 5096 and the audio interpolator is activated to minimize percentage of the maximum possible voltage via the motor the effect of data loss output configuration register address 0110 to limit current drain during start and stop The following power limits are possible e 100 of maximum no power limit e 75 of maximum e 50 of maximum e 37 of maximum LOOP CHARACTERISTICS The gain and cross over frequencies of the motor control loop can be programmed via the motor gain and bandwidth registers addresses 0100 and 0101 The possible parameter values are as follows Gain 3 2 4 0 6 4 8 0 12 8 16 26 6 or 32 Cross over frequency f4 0 5 0 7 1 4 or 2 8 Hz Cross over frequency f3 0 85 1 71 or 3 42 Hz 1998 Feb 16 23 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 MGAS62 2 Fig 21 Motor servo mode diagram Versatile pins interface The SAA7345 has five pins that can be reconfigured for different applications as shown in Table 10 Table 10 Versatile pins CONTROL CONTROL SYMBOL REGISTER REGISTER FUNCTION ADDRESS DATA V1 3 input 1100 XXX1 off track input
33. ovenia see Italy South Africa S A PHILIPS Pty Ltd 195 215 Main Road Martindale 2092 JOHANNESBURG P O Box 7430 Johannesburg 2000 Tel 27 11 470 5911 Fax 27 11 470 5494 South America Al Vicente Pinzon 173 eth floor 04547 130 SAO PAULO SP Brazil Tel 55 11 821 2333 Fax 55 11 821 2382 Spain Balmes 22 08007 BARCELONA Tel 34 3 301 6312 Fax 34 3 301 4107 Sweden Kottbygatan 7 Akalla S 16485 STOCKHOLM Tel 46 8 632 2000 Fax 46 8 632 2745 Switzerland Allmendstrasse 140 CH 8027 Z RICH Tel 41 1 488 2686 Fax 41 1 488 3263 Taiwan Philips Semiconductors 6F No 96 Chien Kuo N Rd Sec 1 TAIPEI Taiwan Tel 886 2 2134 2865 Fax 886 2 2134 2874 Thailand PHILIPS ELECTRONICS THAILAND Ltd 209 2 Sanpavuth Bangna Road Prakanong BANGKOK 10260 Tel 66 2 745 4090 Fax 66 2 398 0793 Turkey Talatpasa Cad No 5 80640 G LTEPE ISTANBLL Tel 90 212 279 2770 Fax 90 212 282 6707 Ukraine PHILIPS UKRAINE 4 Patrice Lumumba str Building B Floor 7 252042 KIEV Tel 380 44 264 2776 Fax 380 44 268 0461 United Kingdom Philips Semiconductors Ltd 276 Bath Road Hayes MIDDLESEX UB3 5BX Tel 44 181 730 5000 Fax 44 181 754 8421 United States 811 East Arques Avenue SUNNYVALE CA 94088 3409 Tel 1 800 234 7381 Uruguay see South America Vietnam see Singapore Yugoslavia PHILIPS Trg N Pasica 5 v 11000 BEOGRAD Tel 381 11 625 344 Fax 381 11 635 777 Internet ht
34. ration of package immersion in solder is 10 seconds if cooled to less than 150 C within 6 seconds Typical dwell time is 4 seconds at 250 C A mildly activated flux will eliminate the need for removal of corrosive residues in most applications Repairing soldered joints Fix the component by first soldering two diagonally opposite end leads Use only a low voltage soldering iron less than 24 V applied to the flat part of the lead Contact time must be limited to 10 seconds at up to 300 C When using a dedicated tool all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development Preliminary specification This data sheet contains preliminary data supplementary data may be published later Product specification This data sheet contains final product specifications Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposur
35. rmer micro controller interface TEST2 TEST1 SAA7345 ISLICE R2 HFIN 22 kQ C2 47 pF HFREF 1k t 1 4 MOTOR I C4 C3 l X6 2 2 KQ 100 nF 22 nF 1 INTERFACE HFIN l I Ci V i 2 2 nF n Viz 7 R4 Vpp 220 pp ad c11 7 uF c3 C7 100 gt toDAC 63 V 100 nF nF X9 7z 7 16 MHz Hi a clock output 2 MGA375 1 1 Diagram is for a 5 V application For 3 4 V applications an additional resistor of 150 kQ should be added between IREF pin 10 and ground 2 For crystal oscillator circuit see Fig 26 Fig 27 Typical SAA7345 application diagram 1998 Feb 16 33 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc PACKAGE OUTLINE QFP44 plastic quad flat package 44 leads lead length 2 35 mm body 14 x 14 x 2 2 mm SOT205 1 detail X DIMENSIONS mm are the original dimensions A max UNIT Ai A2 A3 bp c 2 3 mm 2 60 21 0 25 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VER
36. screen printing stencilling or pressure syringe dispensing before package placement Several methods exist for reflowing for example infrared convection heating in a conveyor type oven Throughput times preheating soldering and cooling vary between 50 and 300 seconds depending on heating method Typical reflow peak temperatures range from 215 to 250 C Wave soldering Wave soldering is not recommended for QFP packages This is because of the likelihood of solder bridging due to closely spaced leads and the possibility of incomplete solder penetration in multi lead devices CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch e equal or less than 0 5 mm 1998 Feb 16 Product specification SAA7345 If wave soldering cannot be avoided for QFP packages with a pitch e larger than 0 5 mm the following conditions must be observed A double wave a turbulent wave with high upward pressure followed by a smooth laminar wave soldering technique should be used The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners During placement and before soldering the package must be fixed with a droplet of adhesive The adhesive can be applied by screen printing pin transfer or syringe dispensing The package can be soldered after the adhesive is cured Maximum permissible solder temperature is 260 C and maximum du
37. tp www semiconductors philips com SCA57 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Printed in The Netherlands 545102 00 05 pp40 Philips Semiconductors Date of release 1998 Feb 16 Document order number 9397 750 03314 Let make things better S PHILIPS
38. tput of 60 1998 Feb 16 22 Philips Semiconductors Product specification CMOS digital decoding IC with RAM for Compact Disc SAA7345 OPERATION MODES The motor servo has the operation modes as shown in Table 9 and is controlled by the motor mode register address 0001 Table 9 Operation modes MODE DESCRIPTION Start mode 1 Disc is accelerated by applying a positive voltage to the spindle motor No decisions are involved and the PLL is reset No disc speed information is available for the microcontroller Start mode 2 The disc is accelerated as in Start mode 1 however the PLL will monitor the disc speed When the disc reaches 75 of its nominal speed the controller will switch to Jump mode The motor status signals are valid register 0010 Jump mode Motor servo enabled but FIFO kept reset at 5096 The audio is muted but it is possible to read the subcode Jump mode 1 Similar to Jump mode but motor integrator is kept at zero Used for long jumps Play mode FIFO released after resetting to 50 Audio mute released Stop mode 1 Disc is braked by applying a negative voltage to the motor No decisions are involved Stop mode2 The disc is braked as in Stop mode 1 but the PLL will monitor the disc speed As soon as the disc reaches 12 of its nominal speed the MOTSTOP status signal will go HIGH and switch the motor servo to off mode Off mode Motor not steered POWER LIMIT FIFO OVERFLOW In Start m
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40. ximum 37 Motor power maximum 50 Motor power maximum 75 Motor power maximum 100 MOTO1 MOTOZ2 pins 3 state Motor Pulse Width Modulation PWM mode Motor Pulse Density Modulation PDM mode Motor Compact Disc Video CDV mode 1998 Feb 16 12 Philips Semiconductors CMOS digital decoding IC with RAM for Compact Disc Product specification SAA7345 REGISTER ADDRESS FUNCTION INITIAL Internal BW Low pass Hz BW Hz PLL loop filter bandwidth 1000 0000 1640 525 8400 0001 3279 263 16800 0010 6560 131 33600 0100 1640 1050 8400 0101 3279 525 16800 0110 6560 263 33600 1000 1640 2101 8400 1001 3279 1050 16800 Reset 1010 6560 525 33600 1100 1640 4200 8400 1101 3279 2101 16800 1110 6560 1050 33600 PLL loop filter equalization 1001 0001 PLL30 ns over equalization 0010 PLL 15nsover equalization 0011 PLL nominal equalization Reset 0100 PLL 15 ns under equalization 0101 PLL 30 ns under equalization EBU output EBU data before concealment EBU data after concealment and fade EBU off output LOW Level Il clock accuracy 1000 x 10 9 Level III clock accuracy 1000 x 10 9 Flags in EBU off Flags in EBU on Speed control 1011 1XXX double speed mode OXXX single speed mode Reset XOXX 33 869 MHz crystal present Reset X1XX 16 934 MHz crystal present XX00 standby 1 CD STOP mode note 1 Reset XX10
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