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Philips UDA1325 User's Manual

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1. DIMENSIONS mm are the original dimensions A A4 A UNIT max min max b by 1 3 mm 5 08 0 51 4 0 08 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION SOT270 1 Es Q 95 02 04 ISSUE DATE 1999 May 10 47 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 GFP64 plastic quad flat package 64 leads lead length 1 95 mm body 14 x 20 x 2 8 mm SOT319 2 detail X DIMENSIONS mm are the original dimensions A max UNIT Ay A2 A3 bp c mm 3 20 0 25 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION SOT319 2 E Rp ISSUE DATE 1999 May 10 48 Philips Semiconductors Universal Serial Bus USB CODEC SOLDERING Introduction This text gives a very brief insightto a complex technology A more in depth account of soldering ICs can be found in our Data Han
2. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT All digital I Os Viio DC input output voltage range 0 5 VppE V lo output current Temperature values o Tj junction temperature 0 C Tstg storage temperature 55 150 C Tamb operating ambient temperature 0 25 70 C Electrostatic handling Ves electrostatic handling note 1 3000 3000 V note 2 300 300 V Notes 1 Equivalent to discharging a 100 pF capacitor through a 1 5 kO series resistor 2 Equivalent to discharging a 200 pF capacitor through a 2 5 uH series conductor THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rih a thermal resistance from junction to ambient UDA1325PS in free air 48 KAN UDA1325H in free air 48 KAN RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER VppE supply voltage periphery I O Vpp supply voltage core 3 0 3 3 3 6 V VI DC input voltage range for D and D 0 0 Vpp V for VINL and VINR 0 5Vpp V for digital I Os 0 0 VppDE V 1999 May 10 37 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 DC CHARACTERISTICS Vppe 5 0 V Vpp 3 3 V Tamb 25 C fos 48 MHz fs 44 1 kHz unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT digital supply voltage periphery 4 75 5 0 b 25 V digital supply voltage core 3 0 analog supply voltage 1 3 0 3 3 3 6 analog
3. 0 1 4 6 Controlling the playback features of the ADAC The exchange of control information between the microcontroller and the ADAC is accomplished through a serial hardware interface comprising the following pins L3 DATA microcontroller interface data line L3 MODE microcontroller interface mode line L3 CLK microcontroller interface clock line See also the description of Port 3 of the 80C51 microcontroller Information transfer through the microcontroller bus is organized in accordance with the so called L3 format in which two different modes of operation can be distinguished address mode and data transfer mode The address mode is required to select a device communicating via the L3 bus and to define the destination registers for the data transfer mode Data transfer for the UDA1325 can only be in one direction from microcontroller to ADAC to program its sound processing features and other functional features ADDRESS MODE The address mode is used to select a device in this case the ADAC for subsequent data transfer and to define the destination registers The address mode is characterized by L3 MODE being LOW and a burst of 8 pulses on L3 CLK accompanied by 8 data bits on L3 DATA Data bits 0 and 1 indicate the type of the subsequent data transfer as shown in Table 6 1999 May 10 13 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 Table 6 Selection of data transfer type
4. Audio recording channel One isochronous input endpoint Supports multiple audio data formats 8 16 and 24 bits Twelve selectable sample rates 4 8 16 or 32 kHz 5 5125 11 025 22 05 or 44 1 kHz 6 12 24 or 48 kHz via analog PLL APLL Selectable sample rate between 5 to 55 kHz via a second oscillator optional One slave 20 bit I2S digital stereo recording input I2S and LSB justified serial formats Programmable Gain Amplifier for left and right channel Low total harmonic distortion typical 85 dB High signal to noise ratio typical 90 dB One stereo Line Microphone input USB endpoints 2 control endpoints 2 interrupt endpoints 1 isochronous data sink endpoint 1 isochronous data source endpoint Document references USB Specification USB Device Class Definition for Audio Devices Device Class Definition for Human Interface Devices HID USB HID Usage Table USB Common Class Specification Philips Semiconductors Universal Serial Bus USB CODEC APPLICATIONS e USB monitors e USB speakers e USB microphones e USB headsets USB telephone answering machines e USB links in consumer audio devices GENERAL DESCRIPTION The UDA1325 is a single chip stereo USB codec incorporating bitstream converters designed for implementation in USB compliant audio peripherals and multimedia audio applications It contains a USB interface an embedded microcontroller an Analog to Digital Interfa
5. PSEN DA SAMPLE ws AUDIO FEATURE PS BUS FREQUENCY BCK INTERFACE GENERATOR EA ALE VINL DECIMATOR FILTER PROCESSING DSP UPSAMPLE FILTERS NZ VARIABLE HOLD REGISTER NZ VINR UDA1325 VRN VRP 3rd ORDER NOISE SHAPER LEFT DAC P2 0 to P2 7 14 16 18 20 T 22 23 29 30 DDI Vss VSSE VDDE VDDO Vsso VDDA1 VSSA1 VDDA2 VssA2 17 19 SCL MICRO 18 SDA CONTROLLER TEST CONTROL BLOCK 25 34 VOUTL 28 37 VOUTR 40 81 n c Vref AD Vref DA The pin numbers given in parenthesis refer to the SDIP42 version Fig 1 Block diagram QFP64 package REFERENCE VOLTAGE sd MGM108 1999 May 10 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 PINNING PIN PIN SYMBOL QFP64 SDIP42 yo DESCRIPTION GP3 WSO 1 5 IO general purpose pin 3 or word select output GP4 BCKO 6 general purpose pin 4 or bit clock output 2 O P0 5 3 IO Port 0 5 of the microcontroller SHTCB 4 7 shift clock of the test control block active HIGH O Port 0 6 of the microcontroller O negative data line of the differential data bus conforms to the USB standard Port 0 7 of the microcontroller positive data line of the differential data bus conforms to the USB standard digital supply voltage for core digital ground for core Vsse
6. The Analog to Digital Interface ADIF The ADIF is used for sampling an analog input signal from a microphone or line input and sending the audio samples to the USB interface The ADIF consists of a stereo Programmable Gain Amplifier PGA a stereo Analog to Digital Converter ADC and Decimation Filters DFs The sample freguency of the ADC is determined by the ADC clock see Section The clock source of the analog to digital interface The user can also select a digital serial input instead of an analog input In this event the sample freguency is determined by the continuous WS clock with a range between 5 to 55 kHz Digital serial input is possible with four formats I2S bus 16 18 or 20 bits LSB justified Programmable Gain Amplifier circuit PGA This circuit can be used for a microphone or line input The input audio signals can be amplified by seven different gains 3 dB 0 dB 3 dB 9 dB 15 dB 21 dB and 27 dB The gain settings are given in Table 17 The Analog to Digital Converter ADC The stereo ADC of the UDA1325 consists of two 3rd order Sigma Delta modulators They have a modified Ritchie coder architecture in a differential switched capacitor implementation The oversampling ratio is 128 Both ADCs can be switched off in power saving mode left and right separate The ADC clock is generated by the analog PLL or the ADC oscillator The Decimation Filter DF The decimator filter converts the audio
7. other endpoints 40h endpoint index Set endpoint status control OUT read 1 byte read 1 byte control IN other endpoints 40h endpoint index write 1 byte write 1 byte Read buffer selected endpoint FOh Write buffer selected endpoint Acknowledge setup selected endpoint write 1 byte read n bytes write n bytes Clear buffer selected endpoint Validate buffer selected endpoint none none none General commands Read current frame number F5h read 1 or 2 bytes 1999 May 10 30 Philips Semiconductors Universal Serial Bus USB CODEC COMMAND DESCRIPTIONS Command procedure This chapter describes the commands that can be used by the microcontroller to control the USB processor There are three basic types of commands e nitialization commands e Data flow commands e General commands A command is represented by an 8 bit code It can be followed by one or more data write cycles or one or more read cycles or a combination The PSIE MMU READY output connected to Port 3 4 of the microcontroller indicates that the previous action command write data read or data write has completed A new action can only be initiated if PSIE MMU READY is TRUE The data is valid from the moment PSIE MMU READY becomes TRUE The PSIE contains a number of interrupt registers one for each endpoint Every time a transition occurs the interrupt flag for the involved endpoint is set The PSIE MMU INT connect
8. GPO BCKI BCKI digital input WSI GESIWSI 15 playback GP1 DI DI 18 BCK BOK 6 digital input ws NS 59 recording DA DA 57 Tc R48 V Xi Li USB 1 5kQ 1 1 8 2 2 7 6 8 18 6 I 4 4 5 n 8 UDA1325H C16 C18 C17 220 C15 10nF 22pF 22 pF 50V 63V 63V 10nF gt 50 V m VINR m analog 47 uF 16 V input yn recording VINL He 47 uF 16 V L5 C44 1 xTAL2b 3 1 5 pH ix 10 nF 63 v T gt M C38 12 pF 63 V X1 E 48 MHz c37 l XTAL1b IF 25 12 pF 63 V XTAL2a 53 ADC XTAL o XTAL1a 54 os L C6 18pF 18 pF T 50 V Le V L8 A ext V en BLM32A07 A L7 Tc BLM32A07 L6 L3 VD ext mee Vp BLM32A07 C47 4 C46 4 C45 100 nF ZE100uF 100 pF asv T 16v T aev R25 GND io d MGM760 ES Vp Fig 8 Application diagram UDA1325H continued in Fig 9 1999 May 10 44 Philips Semiconductors Universal Serial Bus USB CODEC Preliminary specification UDA1325 50 14 16 18 20 22 23 81 48 UDA1325H 21 19 40 41 37 34 D2 EEPM27128 Vp 100 nF 50 V Vp M 3 internal ROM 2 1 1 external ROM I C bus P0 0 Q7 A0 P0 1 Q6 A1 4 P0 2 Q5 A2 4 P0 3
9. BIT1 BITO DATA TRANSFER TYPE audio feature registers volume left volume right bass and treble not used 1 control registers 1 1 not used Data bits 7 to 2 represent a 6 bit device address with bit 7 being the MSB and bit 2 the LSB The address of the ADAC is 000101 bits 7 to 2 In the event that the ADAC receives a different address it will deselect its microcontroller interface logic DATA TRANSFER MODE The selection preformed in the address mode remains active during subsequent data transfers until the ADAC receives a new address command The data transfer mode is characterized by L3 MODE being HIGH and a burst of 8 pulses on L3 CLK accompanied by 8 data bits All transfers are bitwise i e they are based on groups of 8 bits Data will be stored in the ADAC after the eight bit of a byte has been received The principle of a multibyte transfer is illustrated in the figure below thalt ha L3MODE L3CLOCK address data byte 1 data byte 2 address MGD018 PROGRAMMING THE SOUND PROCESSING AND OTHER FEATURES The sound processing and other feature values are stored in independent registers The first selection of the registers is achieved by the choice of data transfer type This is performed in the address mode bits 1 and 0 see Table 6 The second selection is performed by bit 7 and or bit 6 of the data byte depending of the selected data transfer type Data tra
10. 1 vector OOOBh Timer 0 interrupt Source 2 vector 0013h external interrupt 1 INT1_N Source 3 vector 001Bh Timer 1 interrupt Source 4 vector 0023h UART interrupt not present Source 5 vector 002Bh Timer 2 interrupt not present Source 6 vector 0033h IC interrupt INTERRUPT ENABLE REGISTER IE Each interrupt source can be individually enabled or disabled by setting or clearing a bit in IE This register also contains a global interrupt enable bit EA which can be cleared to disable all interrupts at once 76 5 4 3 2 1 0 Power On Value EXO vector 0003h ETO vector 000Bh EX1 vector 0013h EM ln 001Bh n ETS n a E vector 0033h Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 Internal registers Table 17 PGA gain registers ADDRESS REGISTER COMMENTS BIT VALUE 0800h PGA gain register reserved 7 PGA input selection 6 0 do not change it PGA gain right channel 5 4 and 3 000 3 dB 001 2 0 dB 010 2 3 dB 011 9 dB 100 15 dB 101 2 21 dB 110 2 27 dB 111 2 27 dB PGA gain left channel 2 1 and 0 000 3dB 001 0 dB 0102 3dB 011 9dB 100 15 dB 101 2 21 dB 110 27 dB 111 2 27 dB Table 18 ADIF control registers ADDRESS REGISTER COMMENTS BIT VALUE 0801h ADIF control register reserved 7 number of bits per audio sample 6 and 5 00 reserved to be transmitted to the host 01 8 bits audio samples 10 16 bi
11. 11 12 digital ground for I O pads VpDE 12 13 digital supply voltage for I O pads GP1 DI 13 14 general purpose pin 1 or data input P2 0 14 Port 2 0 of the microcontroller GP5 WSI 15 15 general purpose pin 5 or word select input P2 1 16 Port 2 1 of the microcontroller GPO BCKI 17 16 general purpose pin 0 or bit clock input P2 2 18 Port 2 2 of the microcontroller SCL 19 17 serial clock line I2C bus P2 3 20 1 0 Port 2 3 of the microcontroller P2 4 22 Port 2 4 of the microcontroller P2 5 23 IO Port 2 5 of the microcontroller Vssx 24 19 crystal oscillator ground 48 MHz XTAL1b 25 20 crystal input analog 48 MHz XTAL2b 26 21 crystal output analog 48 MHz CLK 27 48 MHz clock output signal Vppx 28 supply crystal oscillator 48 MHz P2 6 29 Port 2 6 of the microcontroller P2 7 30 Port 2 7 of the microcontroller PSEN 31 program store enable active LOW 32 33 34 25 O voltage output left channel TC 35 26 test control input active HIGH 37 28 VOUTR O voltage output right channel supply voltage for operational amplifier operational amplifier ground 1999 May 10 6 Philips Semiconductors Universal Serial Bus USB CODEC SYMBOL VDDA1 PIN SDIP42 Preliminary specification UDA1325 DESCRIPTION analog supply voltage 1 VssA1 analog ground 1 Vref DA Vref AD reference voltage output DAC reference voltage output ADC
12. 3905 Finland Sinikalliontie 3 FIN 02630 ESPOO Tel 358 9 615 800 Fax 358 9 6158 0920 France 51 Rue Carnot BP317 92156 SURESNES Cedex Tel 33 1 4099 6161 Fax 33 1 4099 6427 Germany HammerbrookstraBe 69 D 20097 HAMBURG Tel 49 40 2353 60 Fax 49 40 2353 6300 Hungary see Austria India Philips INDIA Ltd Band Box Building 2nd floor 254 D Dr Annie Besant Road Worli MUMBAI 400 025 Tel 91 22 493 8541 Fax 91 22 493 0966 Indonesia PT Philips Development Corporation Semiconductors Division Gedung Philips Jl Buncit Raya Kav 99 100 JAKARTA 12510 Tel 62 21 794 0040 ext 2501 Fax 62 21 794 0080 Ireland Newstead Clonskeagh DUBLIN 14 Tel 353 1 7640 000 Fax 353 1 7640 200 Israel RAPAC Electronics 7 Kehilat Saloniki St PO Box 18053 TEL AVIV 61180 Tel 972 3 645 0444 Fax 972 3 649 1007 Italy PHILIPS SEMICONDUCTORS Piazza IV Novembre 3 20124 MILANO Tel 39 02 67 52 2531 Fax 39 02 67 52 2557 Japan Philips Bldg 13 37 Kohnan 2 chome Minato ku TOKYO 108 8507 Tel 81 3 3740 5130 Fax 81 3 3740 5077 Korea Philips House 260 199 Itaewon dong Yongsan ku SEOUL Tel 82 2 709 1412 Fax 82 2 709 1415 Malaysia No 76 Jalan Universiti 46200 PETALING JAYA SELANGOR Tel 60 3 750 5214 Fax 60 3 757 4880 Mexico 5900 Gateway East Suite 200 EL PASO TEXAS 79905 Tel 49 5 800 234 7381 Fax 49 5 800 943 0087 Middle East see Italy For all other countries apply to Phil
13. CODEC UDA1325 GUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Supplies VpDE supply voltage periphery 4 75 Vos supplyvolage core e9 IDD tot total supply current Ipp tot ps total supply current in power saving note 1 mode Dynamic performance DAC THD Ny S total harmonic distortion plus fs 44 1 kHz RL 5 ko noise to signal ratio fi 1 kHz 0 dB fi 1 kHz 60 dB signal to noise ratio at bipolar zero A weighted at code 0000H o FS rms full scale output voltage Vpp2 3 3 V 0 66 V RMS value Dynamic performance PGA and ADC THD N S total harmonic distortion plus f 44 1 kHz noise to signal ratio PGA gain 0 dB fi 1 kHz 0 dB Vi 1 0 V RMS fi 1 kHz 60 dB signal to noise ratio Viz 0 0 V General characteristics E laen Tamb operating ambient temperature 0 25 Note 1 Exclusive the IDDE current which depends on the components connected to the I O pins 1999 May 10 4 Philips Semiconductors Universal Serial Bus USB CODEC BLOCK DIAGRAM Preliminary specification UDA1325 XTAL2b GP2 DO 25 20 26 21 2 52 39 53 4 55 42 CLK 27 24 19 OSC 48 MHz OSC ADC D PO 7 to P0 0 ANALOG FRONT END TIMING ANALOG PLL D 7 ZI 62 60 58 56 GP3 WSO GP4 BCKO GP1 DI DIGITAL I O GPO BCKI A A AAAA GP5 WSI
14. O option the UDA1325 device acts as a master controlling the BCKO and WSO signals Using the 6 pin digital I O option GP2 GP3 and GP4 are output pins master and GPO GP1 and GP5 are input pins slave The period of the WSO signal is determined by the number of samples in the 1 ms frame of the USB This implies that the WSO signal does not have a constant time period but is jittery The characteristic timing of the I2S bus signals is illustrated in Figs 5 and 6 LEFT ws BCK DATA MGK003 Fig 5 Timing of digital I O input signals 1999 May 10 21 OL ACW 6664 cc DATA MSB B2 X B3 X B4 Xs B6 y YewYXtsBy O wse B2 X B3 X B4 B5 8o _______ XB19 XLSB L MGK002 LSB JUSTIFIED FORMAT 20 BITS Fig 6 Input formats 23002 gsn sng jeues jesuenum Sce NVan SJojonpuooruleg sdijiyd uoneoiioeds Aieuiuiieid Philips Semiconductors Universal Serial Bus USB CODEC PORT DEFINITION 80C51 Port 1 Table 13 Port 1 of the 80C51 microcontroller 8 BIT PORT 1 Preliminary specification UDA1325 FUNCTION LOW HIGH COMMENT ADAC_ error no error error GP1 Port 3 Table 14 Port 3 of the 80C51 microcontroller general purpose pins 8 BIT PORT 3 BIT LOW no error FUNCTION ASR_ error HIGH error COMMENT PSIE MMU SUSPEND no suspend suspend suspend input from USB interface during normal operation or input from
15. Q4 A3 Q P0 4 pi Ss m PoS i 74HCT373D 2 P0 6 Qi A6 P0 7 Qo A7 Vcc A8 ALE Vp C24 I 100 nF A9 50 V A10 GND A11 P2 0 A12 P2 1 A13 P2 2 AW OE P2 3 CE P24 mE PGM P2 5 EN Vpp PSEN 7 EA R28 p L R20 4 7kQ Vp 1 TQ Vi la a iV 100 nF PTC D A D4 di J3 SCL 3 PCF85116 3 6 R38 R39 SDA 5 10ko 10ka SDA 1 SCL Vref DA 2 Vref AD C29 4 C4 100nF 47 uF C28 C31 Iw dar Je 16 V Jev sw 2 7 VOUTR JE 47 uF 16 V saos output playback VOUTL En 47 uF 16 V GP4 BCKO GP3 WSO BOKO digtal WSO output GP2 DO DO playback MGM761 Fig 9 Application diagram UDA1325H continued from Fig 8 1999 May 10 45 OL ACW 6661 9v Bo GPO BCKI digital input WSI GESINS playback GP1 DI DI ci BCK digital input ws we recording DA DA c VusB x4 L1 R48 ya j 8 1 5kQ c d 7 R7 D 8 3 6 I 220 4 4 5 R16 D C16 C18 C17 220 C15 10nF 22 pF 22 pF LLL 50V 63V 63V 10 nF 2 7 7 50 V us VINR 2 34 analog 47 uF 16 V input eo recording VINL 47 uF 16 V L5 C44 1 xTA2b 3 ll 1 5 uH 10 nF 63 V V C38 12 pF 63 V X1 E 48 MHz C37 T XTAL1b d 12 pF 63 V XTAL2a le ADC XTAL o XTAL1a o i C5 res 18 pF 18 pF Im V je V VA VA VA VA R35 R27 R10 R8 c34 1Q ca io c L192 cu i19 d 1k N iH y IH y ll 47 uF 47 uF 47 uF 1
16. S 16485 STOCKHOLM Tel 46 8 5985 2000 Fax 46 8 5985 2745 Switzerland Allmendstrasse 140 CH 8027 ZURICH Tel 41 1 488 2741 Fax 41 1 488 3263 Taiwan Philips Semiconductors 6F No 96 Chien Kuo N Rd Sec 1 TAIPEI Taiwan Tel 886 2 2134 2886 Fax 886 2 2134 2874 Thailand PHILIPS ELECTRONICS THAILAND Ltd 209 2 Sanpavuth Bangna Road Prakanong BANGKOK 10260 Tel 66 2 745 4090 Fax 66 2 398 0793 Turkey Yukari Dudullu Org San Blg 2 Cad Nr 28 81260 Umraniye ISTANBUL Tel 90 216 522 1500 Fax 90 216 522 1813 Ukraine PHILIPS UKRAINE 4 Patrice Lumumba str Building B Floor 7 252042 KIEV Tel 380 44 264 2776 Fax 380 44 268 0461 United Kingdom Philips Semiconductors Ltd 276 Bath Road Hayes MIDDLESEX UB3 5BX Tel 44 181 730 5000 Fax 44 181 754 8421 United States 811 East Arques Avenue SUNNYVALE CA 94088 3409 Tel 1 800 234 7381 Fax 1 800 943 0087 Uruguay see South America Vietnam see Singapore Yugoslavia PHILIPS Trg N Pasica 5 v 11000 BEOGRAD Tel 381 11 62 5344 Fax 381 11 63 5777 Internet http www semiconductors philips com SCA64 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any guotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by t
17. VDDA2 VINL analog supply voltage 2 input signal left channel PGA VssA2 n c 44 45 analog ground 2 not connected n c VINR 46 47 not connected input signal right channel PGA EA VRN 48 49 external access active LOW negative reference input voltage ADC ALE address latch enable active HIGH positive reference input voltage ADC ae supply voltage for crystal oscillator and analog PLL XTAL2a XTAL1a 53 54 40 41 O crystal output analog ADC crystal input analog ADC VssA3 P0 0 55 56 crystal oscillator and analog PLL ground Port 0 0 of the microcontroller DA PO 1 57 58 data Input digital Port 0 1 of the microcontroller WS PO 2 59 60 word select Input digital Port 0 2 of the microcontroller BCK P0 3 61 bit clock Input digital Port 0 3 of the microcontroller GP2 DO general purpose pin 2 or data output P0 4 1999 May 10 Port 0 4 of the microcontroller Philips Semiconductors Universal Serial Bus USB CODEC GP3 WSO GP4 BCKO Preliminary specification UDA1325 63 GP2 DO 55 VssA3 54 XTAL1a 53 XTAL2a 52 VDDA3 x o aW o 62 P0 3 61 BCK 60 P0 2 59 WS 58 P0 1 57 DA 56 P0 0 VRP ALE VRN EA VINR n c n c VSSA2 VINL VDDA2 Vref AD Vref DA VSSA1 VDDA1 VOUTR RTCB TC VOUTL Vsso MGL349 P2 3 SDA P
18. Vssa1 The RC time can be calculated using R 25000 Q and C Cret During 20 ms after Power on reset becomes HIGH the UDA1325 has to initiate the internal registers During this initialisation the user should prevent indicating the connected status to the USB host This can be done by forcing the DP line LOW i e via one of the GP pins Power Management The total current drawn from the USB supply for i e bus powered operation of the UDA1325 application must be less than 500 uA in suspend mode In order to reach that low current target the total power dissipation of the UDA1325 can be reduced by disabling all internal clocks and switching off all internal analog modules Important note In order to make use of power reduction Power down mode and be able to restart after power down a number of precautions must be taken 1999 May 10 28 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 AT INITIALISATION TIME Bit 7of the power control register mux ctrl suspend must be set to 1 in order to connect the CLK ON of the USB processor with P3 1 of the microcontroller Bit 6 of the power control register mux ctrl int1 must be set to 0 in order to connect the PSIE MMU INT output pin of the USB processor with P3 3 INT1 N of the microcontroller Bit 7of the I O selection register must be set to 1 in order to enable the power on control of the 48 MHz crystal oscillator automatic
19. data from 128f down to 1fs with a word width of 8 16 or 24 bits This data can be transmitted over the USB as mono or stereo in 1 2 or 3 bytes sample The decimator filters are clocked by the ADC clock Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 The clock source of the analog to digital interface The clock source of the ADIF is the analog PLL or the ADC oscillator The preferred clock source can be selected The ADC clock used for the ADC and decimation filters is obtained by dividing the clock signal coming from the analog PLL or from the ADC oscillator by a factor O Using the analog PLL the user can select 3 basic APLL clock freguencies see Table 1 By connecting the appropriate crystal the user can choose any clock signal between 8 192 and 14 08 MHz via the ADC oscillator Table 1 The analog PLL clock output frequencies APLL CLOCK CODE TAND FREQUENCY MHz 11 2896 8 1920 10 12 2880 11 11 2896 The dividing factor Q can be selected via the microcontroller With this dividing factor Q the user can select a range of ADC clock signals allowing several different sample frequencies see Table 2 Table 2 ADC clock frequencies and sample frequencies based upon using the APLL as a clock source APLL CLOCK FREQUENCY MHz DIVIDE FACTOR G ADC CLOCK FREQUENCY MHz SAMPLE FREQUENCY kHz 8 1920 4 096 32 2 048 16 1 024 8 0 512 not supported 4 not supp
20. input resistance at VINL and VINR of the PGA Filter stream DAC Vref DA reference voltage DAC 0 5VppA2 12 5 Vo cM Ro vour common mode output voltage output resistance at VOUTL and VOUTR Q Rot Cow output load resistance output load capacitance pF Notes 1 This value depends strongly on the application The specified value is the typical value obtained using the application diagram as illustrated in Fig 8 1999 May 10 At start up of the OSCAD oscillator At start up of the OSC48 oscillator Exclusive the IDDE current which depends on the components connected to the I O pins 39 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 AC CHARACTERISTICS Vppe 5 0 V Vppi 3 3 V Tamb 25 C fos 48 MHz fs 44 1 kHz unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Driver characteristics D and D full speed mode audio sample output freguency rise time C 50 pF fall time C 50 pF rise fall time matching trt Ver output signal crossover voltage Rovarive driver output resistance steady state drive Data source timings D and D full speed mode fits audio sample input frequency 5 55 fis D full speed data rate 11 97 12 00 12 03 Mbits s lip frame interval 1 0000 1 0005 ms tut aiff source differential jitter to next 0 0 43 5 ns transition source differentia
21. restart circuit GPO INTO N PSIE MMU INT INT1 N general purpose pin interrupt input from USB interface during normal operation or input from restart circuit PSIE MMU READY L3 MODE 3 7 L3 CLK L3 DATA 1999 May 10 23 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 MEMORY AND REGISTER SPACE 80C51 RESET ADDRESS REGISTER Overview registers VALUE Table 15 Register location and recommended values Port registers after Power on reset PO FFh RESET FFh ADDRESS REGISTER VALUE BER 0800h PGA gain 09 FFh ADIF control Ic ae SIO1 registers clock shop settings S1CON reset control and APLL settings S1STA 1002h IO selection register ES S1DAT 1003h power control DBh S1ADR 2000h ASR settings 4000h data register PSIE Interrupts 4001h command register PSIE Table 16 Special function register location RESET ADDRESS REGISTER VALUE CPU registers 81h SP Ca 99 83h DPH Ls 9 EOh ACC me Interrupt registers A8h IE 00h Timer 0 and Timer 1 registers 88h TO1CON 00h 8Ah TOL 00h 8Ch TOh 00h PCON registers 87h PCON 00h 1999 May 10 24 The UDA1325 supports up to five of maximal 7 interrupt sources Each interrupt source corresponds to an interrupt vector in the CPU program memory address space Source 0 vector 0003h external interrupt O INTO_N Source
22. supply voltage 2 3 0 analog supply voltage 3 3 0 3 3 3 6 operational amplifier supply voltage 3 0 crystal oscillator supply voltage 3 0 3 3 3 6 digital supply current periphery digital supply current core 39 0 analog supply current 1 ee je analog supply current 2 8 0 analog supply current 3 0 9 9 0 2 operational amplifier supply current 3 0 crystal oscillator supply current 1 2 total power dissipation 200 total power dissipation in power saving mode s D and D static DC input voltage static DC output voltage HIGH R_ 15 kQ connected to GND static DC output voltage LOW R 1 5 kQ connected to Vpp lio high impedance data line output leakage current Vi diff differential input sensitivity VcMddiff differential common mode range single ended receiver threshold voltage CiN transceiver input capacitance pin to GND Digital input pins Vi LOW level input voltage HIGH level input voltage input leakage current input capacitance 1999 May 10 38 Philips Semicon ductors Universal Serial Bus USB CODEC SYMBOL PARAMETER CONDITIONS Preliminary specification UDA1325 PGA and ADC Vref AD reference voltage PGA and ADC Vref ADC pos Vref ADC neg positive reference voltage of the ADC negative reference voltage of the ADC 0 0 Vi PGA Ri PGA DC input voltage VINL and VINR of the PGA DC
23. 00 nF p 16 V 16 V 16 V 63 V C38 C21 C19 1H Il IH R20 19 100 nF 100 nF 100 nF 63 V 63 V 63 V Vssa1 VDDA1 VSSA2 VDDA2 VssAs VDDA3 VRN VRP VoD 30 29 35 33 42 39 37 38 ai PTC D 16 pe 7 so 3 PCF85116 3 6 15 SDA R38 R39 2 10ko 10ka 14 1g SDA E e 3 MES PC bus 2 ji Vref DA A 2 32 Vref AD I C29 s a cai 100 n 47 C28 C81 IN 100nF 2247 uF 63V 16V Jev INL zz a C35 VOUTR 28 9 47 uF 16 V dadia output layback C48 P VOUTL UDA1325PS 25 t 47 uF 16 V 36 34 Ffamwso OO aua 5 Wso output 4 GP2DO DO playback 21 27 BTCB 20 26 HE 7 SHTCB 40 41 11 10 12 13 19 22 L8 Vss VDDI VssE VDDE Tues ysgo Vssx YDDX VA ext VA C25 C26 C33 C28 BLM32A07 L7 100 nF 100 nF 100 nF 100 nF c 63 V L2 63 MITT 63 V 63 V L13 BLM32A07 o BLM32A07 BLM32A07 on cig t BLM32A07 L6 24 VD ext Vp E 1H y il 3 IF BLM32A07 100 nF 100 nF P le 100 nF s C47 _ C46 C45 e3 v R7 e3v R25 ie V R43 63 V pn 100 uF Zc100uF 100 pF 63M io 63V io 19 6v asv T aev GND Vc Vp VA c MGS271 Fig 10 Application diagram UDA1325PS 23002 gsn sng jeues esJeAiuf Sce van SJojonpuooruleg sdijiyd uoneoiioeds Aieuiuiieid Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 PACKAGE OUTLINES SDIP42 plastic shrink dual in line package 42 leads 600 mil SOT270 1 7 seating plane
24. 11 Treble settings TREBLE dB FLATSET MIN SET MAX SET TR4 TR3 TR2 TR1 TRO ojo o o ojo o oio o o eo ojo ojoio o o 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 TT 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 _ Bass control For the playback channel bass can be regulated in three audio modes minimum flat and maximum mode In flat mode the audio is not influenced In minimum mode the bass range is from 0 to approximately 14 dB in steps of 1 5 dB In maximum mode the bass range is from 0 to approximately 24 dB in steps of 2 dB The programmable bass filters are implemented digitally and have a fixed corner frequency of 100 Hz for the minimum mode and 75 Hz for the maximum mode Because of the exceptional amount of programmable gain bass should be used with adequate prior attenuation using volume control 1999 May 10 18 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 Table 12 Bass boost settings BASS dB FLAT SET MIN SET MAX SET NIN AJA 8 4 4 8 11 3 10 2 13 3 10 2 13 3 11 9 15 2 13 7 17 3 13 7 19 2 13 7 21 2 13 7 23 2 13 7 23 2 aw oa NIN o N Cc N o 1 1 3 3 5 5 7 7 9 9 7 7 6 6 4 4 4 4 4 4 o co De emphasis De emphasis is contr
25. 2 4 P2 5 Vssx CLK P2 6 P2 7 PSEN o a a gt XTAL1b XTAL2b VDDX Fig 2 Pin configuration QFP64 package 1999 May 10 Philips Semiconductors Universal Serial Bus USB CODEC GP5 WSI GPO BCKI SDA Vssx XTAL1b XTAL2b MGM106 VSSA3 XTAL1a XTAL2a VDDA3 VRP VRN VINR VSSA2 VINL VDDA2 Vref AD Vref DA VSSA1 VDDA1 VOUTR RTCB TC VOUTL Vsso Vppo VDDX Fig 3 Pin configuration SDIP42 package 1999 May 10 Preliminary specification UDA1325 FUNCTIONAL DESCRIPTION The Universal Serial Bus USB Data and power is transferred via the USB over a 4 wire cable The signalling occurs over two wires and point to point segments The signals on each segment are differentially driven into a cable of 90 O intrinsic impedance The differential receiver features input sensitivity of at least 200 mV and sufficient common mode rejection The analog front end The analog front end is an on chip generic USB transceiver It is designed to allow voltage levels up to Vpp from standard or programmable logic to interface with the physical layer of the USB It is capable of receiving and transmitting serial data at full speed 12 Mbits s The USB processor The USB processor forms the interface between the analog front end the ADIF the ADAC and the microcontroller The USB processor consists of A bit clock recovery circuit The Philips Serial Interface Engine PSIE e The M
26. Ci xTAL1a output resistance parasitic input capacitance XTAL1a 12 8 4 5 22 1 30 2 1 1 2 3 Ci xTAL2a parasitic input capacitance XTAL2a 4 1 4 6 lstart Oscillator 2 f start up current or ADC clock 3 7 13 0 fosc 5 oscillator frequency duty cycle 14 08 g Ci xTAL1b transconductance parasitic input capacitance XTAL1b m Ro output resistance mm Ci xTAL2b parasitic input capacitance XTAL2b lstart start up current 2 4 5 4 5 7 4 6 5 0 1999 May 10 41 Philips Semiconductors Universal Serial Bus USB CODEC SYMBOL PARAMETER CONDITIONS Preliminary specification UDA1325 MIN TYP MAX UNIT Analog PLL for ADC clock folk PLL PLL clock frequency 8 1920 11 2896 MHz tstrt PO Power on res duty factor start up time after power on et 12 2880 tsu PO PGA and ADC VitFSy rms Ci PGA power on set up time full scale input voltage RMS value input capacitance of the PGA PGA gain 3 dB PGA gain 0 dB PGA gain 3 dB PGA gain 9 dB PGA gain 15 dB PGA gain 21 dB PGA gain 27 dB THD N S total harmonic distortion plus noise to signal ratio fs 44 1 kHz at input signal of 1 kHz PGA gain 0 dB note 4 Vi 0 dB 1 0 V RMS Vi 60 dB signal to noise ratio crosstalk between channels Vi20 0V PGA gain 0 dB s
27. ERING Reflow soldering requires solder paste a suspension of fine solder particles flux and binding agent to be applied to the printed circuit board by screen printing stencilling or pressure syringe dispensing before package placement Several methods exist for reflowing for example infrared convection heating in a conveyor type oven Throughput times preheating soldering and cooling vary between 100 and 200 seconds depending on heating method 1999 May 10 Preliminary specification UDA1325 Typical reflow peak temperatures range from 215 to 250 C The top surface temperature of the packages should preferable be kept below 230 C WAVE SOLDERING Conventional single wave soldering is not recommended for surface mount devices SMDs or printed circuit boards with a high component density as solder bridging and non wetting can present major problems To overcome these problems the double wave soldering method was specifically developed If wave soldering is used the following conditions must be observed for optimal results Use a double wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave For packages with leads on two sides and a pitch e larger than or equal to 1 27 mm the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed circuit board smaller than 1 27 mm the footprint longitudinal axis
28. INTEGRATED CIRCUITS DATA SHEET ICD eg UNIVERSAL SERIAL BUS UDA1325 Universal Serial Bus USB CODEC Preliminary specification 1999 May 10 File under Integrated Circuits ICO1 Philips PHILIPS Semiconductors D ia l L Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 ICD egg UNIVERSAL SERIAL BUS FEATURES General High Quality USB compliant Audio HID device Supports 12 Mbits s serial data transmission Fully USB Plug and Play operation Supports Bus powered and Self powered operation 3 3 V power supply Low power consumption with optional efficient power control On chip clock oscillator only an external crystal is required Audio playback channel One isochronous output endpoint e Supports multiple audio data formats 8 16 and 24 bits e Adaptive sample frequency support from 5 to 55 kHz One master 20 bit 12S digital stereo playback output I2S and LSB justified serial formats One slave 20 bit I2S digital stereo playback input I2S and LSB justified serial formats Selectable volume control for left and right channel Soft mute control Digital bass and treble tone control Selectable on chip digital de emphasis Low total harmonic distortion typical 90 dB High signal to noise ratio typical 95 dB One stereo Line output 1999 May 10
29. PT REGISTER Command F4h Data read 1 byte The read interrupt register command returns the value of the interrupt register Every time a packet is received or transmitted an interrupt will be generated and a flag specific to the physical endpoint will be set in the interrupt register Reading the status of the endpoint will clear the flag 1999 May 10 Preliminary specification UDA1325 An interrupt is also generated after a bus reset When the interrupt register consists of all zeros and an interrupt was generated there was a bus reset The interrupt is cleared when the interrupt register is read 76 5 4 3 2 1 0 Power On Value Control OUT Control IN Endpoint 1 OUT Endpoint 1 IN Endpoint 2 IN Endpoint 3 IN Endpoint 4 OUT Endpoint 5 IN SELECT ENDPOINT Command 00h endpoint index Data optional read 1 byte The select endpoint command initializes an internal pointer to the start of the selected buffer Optionally this command can be followed by a data read Bit 0 is low if the buffer is empty and high if the buffer is full There is one command for every endpoint X X X X X X x o Power On Value Full Empty Reserved GET ENDPOINT STATUS Command 40h endpoint index Data read 1 byte The get endpoint status command is followed by one data read that returns the status of the last transaction of the selected endpoint This command also resets the corresponding interrupt flag in the interrupt reg
30. able suitable HLOFP HSQFP HSOP HTSSOP SMS not suitable 9 suitable PLCC SO SOJ suitable suitable LOFP QFP TQFP not recommended suitable SSOP TSSOP VSO not recommended 9 suitable Notes 1 All surface mount SMD packages are moisture sensitive Depending upon the moisture content the maximum temperature with respect to time and body size of the package there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them the so called popcorn effect For details refer to the Drypack information in the Data Handbook IC26 Integrated Circuit Packages Section Packing Methods 2 For SDIP packages the longitudinal axis must be parallel to the transport direction of the printed circuit board 3 These packages are not suitable for wave soldering as a solder joint between the printed circuit board and heatsink at bottom version can not be achieved and as solder may stick to the heatsink on top version 4 lf wave soldering is considered then the package must be placed at a 45 angle to the solder wave direction The package footprint must incorporate solder thieves downstream and at the side corners 5 Wave soldering is only suitable for LOFP QFP and TQFP packages with a pitch e equal to or larger than 0 8 mm it is definitely not suitable for packages with a pitch e equal to or smaller than 0 65 mm 6 Wave soldering is only suitable for SSOP and TSSOP pac
31. ally by the microcontroller IN NORMAL OPERATION MODE In normal operation working mode a suspend can be initiated by the falling edge of the CLK ON output signal of the USB processor This falling edge comes about 2 ms after the rising edge of the PSIE MMU SUSPEND output signal of the USB processor At this moment several actions should be taken by the microcontroller All analog modules of the UDA1325 must be switched off this can be done by setting bits 5 to O of the power control register to 1 and bit 0 of the clock shop register to 1 Bit 6 of the power control register mux ctrl int1 must be set to 1 in order to awake from power down by the CLK ON signal of the USB processor Put all GP pins in the high or low state depending of how they are used in the UDA1325 application Put the microcontroller in Power down mode This can be done via the PCON register of the microcontroller This results in an automatically switching off the 48 MHz crystal oscillator and with that all internal clocks if they are enabled On the rising edge of the CLK ON output signal the 48 MHz crystal oscillator will be switched on automatically and with that all internal clocks if they are enabled At the same time a counter starts counting for 2048 clock cycles 170 us This time is necessary for stabilising the 48 MHz clock of the 48 MHz crystal oscillator When the counter reaches its end value after 2048 cycles a rising edge will be de
32. ample frequency 128f OL digital output level PGA gain 0 dB 2 0 dBFS Vi 1 V RMS 1999 May 10 42 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 SYMBOL PARAMETER CONDITIONS Filter stream resolution full scale output voltage RMS value supply voltage ripple rejection at fripple 1 kHz Vppa and Vppo Vripple p p 0 1 V channel unbalance maximum volume Oct crosstalk between channels R_ 5 kQ THD N S total harmonic distortion plus fs 44 1 kHz noise to signal ratio RL 5 kQ note 5 at input signal of 1 kHz 0 dB at input signal of 1 kHz 60 dB S N signal to noise ratio at bipolar zero A weighting at code 0000H Notes 1 Strongly depends on the external decoupling capacitor connected to Vret DA 2 Crerin uF 3 Although a level of 1 414 V RMS would be required to optimal drive the ADC in this gain setting this level can not be used Due to the 3 3 V supply voltage input signals of 1 17 V RMS and higher will result in clipping 4 Measured with the APLL as ADC clock source 5 Measured with I2S bus input as digital source 1999 May 10 43 Philips Semiconductors Universal Serial Bus USB CODEC APPLICATION INFORMATION Preliminary specification UDA1325 VA R27 10 VppAi Vssa2 VpDA2
33. ce ADIF and an Asynchronous Digital to Analog Converter ADAC The USB interface consists of an analog front end and a USB processor The analog front end transforms the differential USB data into a digital data stream The USB processor buffers the incoming and outgoing data from the analog front end and handles all low level USB protocols The USB processor selects the relevant data from the universal serial bus performs an extensive error detection and separates control information and audio information The control information is made accessible to the microcontroller At playback the audio information becomes available at the digital IS output of the digital I O module or is fed directly to the ADAC At recording the audio information is delivered by the ADIF or by the digital 12S input of the I S bus interface ORDERING INFORMATION TYPE NUMBER Preliminary specification UDA1325 All I2S inputs and 1 S outputs support standard 2S bus format and the LSB justified serial data format with word lengths of 16 18 and 20 bits Via the digital I O module with its IS input and output an external DSP can be used for adding extra sound processing features for the audio playback channel The microcontroller is responsible for handling the high level USB protocols translating the incoming control requests and managing the user interface via general purpose pins and an l2C bus The ADAC enables the wide and continuous range of p
34. crocontroller needs to re enable these commands by the acknowledge setup command This ensures that the last SETUP packet stays in the buffer and no packet can be sent back to the host until the microcontroller has 1999 May 10 Preliminary specification UDA1325 acknowledged explicitly that it has seen the SETUP packet If the microcontroller is reading the data from a SETUP packet and a new SETUP packet arrives the device must accept this new SETUP packet So the data currently being read by the microcontroller is overwritten with the new packet On the arrival of the new packet the commands validate buffer and clear buffer are disabled If the microcontroller has finished reading the data from the buffer it will try to clear the buffer The device will ignore this command so the new SETUP packet in the buffer is not cleared The microcontroller will now detect the interrupt of the new SETUP packet and will start reading the new data in the buffer A SETUP token can be followed by an IN token After the SETUP token the microcontroller will start filling the IN buffer A SETUP token will clear the IN buffer This avoids the following problem after a SETUP token the microcontroller fills the IN buffer If the SETUP token is followed by a SETUP token and shortly followed by an IN token the device will send the contents of the IN buffer to the host The IN buffer was filled after the first SETUP token That is why after a SETUP
35. cted by the SIO1 hardware the SI bit is set when a serial interrupt is requested and the STO bit is cleared when a STOP condition is present on the I2C bus The STO bit is also cleared when ENS1 0 Reset initializes S1CON to 00h 76 5 4 3 2 1 0 o o o o o o o o Power On Value CRO CR1 AA S STO STA ENS1 CR2 i CR2 1 AND O THE CLOCK RATE BITS These three bits determine the serial clock frequency when SIO1 is in a master mode The various serial rates are shown in Table 28 Table 28 Serial clock rates SCL line I C BIT FREQUENCY kHz 0 0 1 1 0 0 lo oj io o o as 3 9 501 When the CR bits are 111 the maximum bit rate for the data transfer will be derived from the Timer 1 overflow rate divided by 2 i e every time the Timer 1 overflows the SCL signal will toggle OL ACW 6661 9 SDA t HD STA gt sp SCL gt ket HD STA gt e gt gt ke tSU STO he P S t HD DAT THIGH tsuDAT SU STA g P MBC611 Du zd Fig 7 Definition of timing of the I2C bus SJojonpuooruleg sdijiyd 23002 gsn sng jeues resJeAiuf Sce van uoneoiioeds Aieuiuiieid Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 LIMITING VALUES In accordance with the Absolute Maximum Rating System IEC 134
36. dbook IC26 Integrated Circuit Packages document order number 9398 652 90011 There is no soldering method that is ideal for all IC packages Wave soldering is often preferred when through hole and surface mount components are mixed on one printed circuit board However wave soldering is not always suitable for surface mount ICs or for printed circuit boards with high population densities In these situations reflow soldering is often used Through hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE The maximum permissible temperature of the solder is 260 C solder at this temperature must not be in contact with the joints for more than 5 seconds The total contact time of successive solder waves must not exceed 5 seconds The device may be mounted up to the seating plane but the temperature of the plastic body must not exceed the specified maximum storage temperature T stg max If the printed circuit board has been pre heated forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit MANUAL SOLDERING Apply the soldering iron 24 V or less to the lead s of the package either below the seating plane or not more than 2 mm above it If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds If the bit temperature is between 300 and 400 C contact may be up to 5 seconds Surface mount packages REFLOW SOLD
37. ed to Port 3 3 is an OR function of all interrupt registers Initialization commands Initialization commands are used during the enumeration process of the USB network They are used to set the USB assigned address enable endpoints and select the configuration of the device SET ADDRESS ENABLE Command DOh Data write 1 byte The set address enable command is used to set the USB assigned address and enable the function The device always powers up disabled and should be enabled after a bus reset 76 5 4 3 2 1 0 o o 0 0 O O 0 o Power On Value Address Enable 1999 May 10 Preliminary specification UDA1325 Table 24 BIT DESCRIPTION Address the value written becomes the device address Enable a 1 enables this function READ ADDRESS ENABLE Command DOh Data read 1 byte The read address enable command is used to read the USB assigned address and the enable bit of the device The format of the data phase is the same as for the set address enable command SET ENDPOINT ENABLE Command D8h Data write 1 byte The set endpoint enable command is used to set the enable bits for the non default endpoints 7 6 5 4 3 2 1 0o X X X X X X x o Power On Value Enable Reserved If the enable bit is 1 the non default endpoints are enabled if 0 the non default endpoints are disabled The function then only responds to the default control endpoint After bus reset
38. emory Management Unit MMU e The Audio Sample Redistribution ASR module Bit clock recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream using four times over sampling principle It is able to track jitter and frequency drift specified by the USB specification Philips Serial Interface Engine PSIE The Philips SIE implements the full USB protocol layer It translates the electrical USB signals into data bytes and control signals Depending upon the USB device address and the USB endpoint address the USB data is directed to the correct endpoint buffer The data transfer could be of bulk isochronous control or interrupt type The functions of the PSIE include synchronization pattern recognition parallel serial conversion bit stuffing de stuffing CRC checking generation PID verification generation address recognition and handshake evaluation generation The amount of bytes packet on all endpoints is limited by the PSIE hardware to 8 bytes packet except for both isochronous endpoints 336 bytes packet Philips Semiconductors Universal Serial Bus USB CODEC Memory Management Unit MMU and integrated RAM The MMU and integrated RAM handle the temporary data storage of all USB packets that are received or sent over the bus The MMU and integrated RAM handle the differences between data rate of the USB and the application allowing the microcontroller to read and write USB pack
39. ets at its own speed The audio data is transferred via an isochronous data sink endpoint or source endpoint and is stored directly into the RAM Consequently no handshaking mechanism is used Audio Sample Redistribution ASR The ASR reads the audio samples from the MMU and integrated RAM and distributes these samples equidistant over a 1 ms frame period The distributed audio samples are translated by the digital I O module to standard I S bus format or 16 18 or 20 bits LSB justified IS bus format The ASR generates the bit clock output BCKO and the Word Select Output signal WSO of the IS output The 80C51 microcontroller The microcontroller receives the control information selected from the USB by the USB processor It can be used for handling the high level USB protocols and the user interfaces The microcontroller does not handle the audio stream The major task of the software process that is mapped upon the microcontroller is to control the differentmodules of the UDA1325 in such a way that it behaves as a USB device The embedded 80C51 microcontroller is compatible with the 80C51 family of microcontrollers described in the 80C51 family single chip 8 bit microcontrollers of Data Handbook IC20 which should be read in conjunction with this data sheet The internal ROM size is 12 kbyte The internal RAM size is 256 byte A Watchdog Timer is not integrated 1999 May 10 10 Preliminary specification UDA1325
40. he SFG controls the timing signals for the asynchronous digital to analog conversion By means of a digital PLL the SFG automatically recovers the applied sampling frequency and generates the accurate timing signals for the audio feature processing DSP and the upsampling filters The lock time of the digital PLL can be chosen see Table 8 While the digital PLL is not in lock the ADAC is muted As soon as the digital PLL is in lock the mute is released as described in Section Soft mute control First In First Out FIFO registers The FIFO registers are used to store the audio samples temporarily coming from the USB processor or from the digital I O input The use of a FIFO in conjunction with the SFG is necessary to remove all jitter present on the incoming audio signal The sound processing DSP A DSP processes the sound features The control and mapping of the sound features is explained in Section Controlling the playback features of the ADAC Depending on the sampling rate fs the DSP knows four frequency domains in which the treble and bass are regulated The domain is chosen automatically 1999 May 10 12 Preliminary specification UDA1325 Table4 Frequency domains for audio processing by the DSP DOMAIN SAMPLE FREQUENCY kHz 5 to 12 12 to 25 25 to 40 40 to 55 The upsampling filters and variable hold function After the audio feature processing DSP two upsampling filters and a variable h
41. he publisher for any conseguence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Printed in The Netherlands 545002 750 01 pp52 Philips Semiconductors Date of release 1999 May 10 Document order number 9397 750 02805 Led make things betta S PHILIPS
42. iconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 Table 8 ADAC general control registers REGISTER BIT DESCRIPTION VALUE COMMENT Control register 0 0 reset ADAC 0 not reset 1 reset 1 soft mute control 0 not muted 1 mutes 2 synchronous asynchronous 0 asynchronous select 0 1 synchronous 3 channel manipulation O L gt L R gt R 1 L gt R R gt L 4 de emphasis 0 de emphasis off 1 de emphasis on 6 and 5 audio mode 00 flat mode 01 2 min mode 10 2 min mode 11 2 max mode 7 selecting bit 0 Control register 1 1 and O serial I2S bus input format 00 I2S bus 01 16 bit LSB justified 10 18 bit LSB justified 11 20 bit LSB justified 3 and 2 digital PLL mode 00 adaptive select 00 01 fix state 1 10 fix state 2 11 fix state 3 4 digital PLL lock mode 0 adaptive select 1 1 fixed 6 and 5 digital PLL lock speed 00 lock after 512 samples select 00 01 lock after 2048 samples 10 lock after 4096 samples 11 lock after 16348 samples 7 selecting bit 1 Soft mute control When the mute bit 1 of control register 0 is active for the playback channel the value of the sample is decreased smoothly to zero following a raised cosine curve There are 32 coefficients used to step down the value of the data each one being used 32 times before stepping to the next This amounts to a mute transition of 23 ms at f 44 1 kHz Whe
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45. ister and clears the status indicating that it was read There is one command for every endpoint olololo o o olo Power On Value L Data Receive Transmit Error Code Setup Packet Data 0 1 Packet Previous Status not Read Philips Semiconductors Universal Serial Bus USB CODEC Table 26 Error codes ERROR CODE RESULT 0000 no error 0001 PID encoding error bits 7 to 4 in the PID token are not the inversion of bits 3 to O 0010 PID unknown PID encoding is valid but PID does not exist 0011 unexpected packet packet is not of the type expected token data or acknowledge or SETUP token received on non control endpoint 0100 token CRC error 0110 time out error 1000 unexpected end of packet 1001 sent or received NAK 1010 sent stall a token was received but the endpoint was stalled 1011 overflow error the received data packet was larger then the buffer size of the selected endpoint 1100 sent empty packet ISO only 1101 bitstuff error 1110 error in sync 1111 wrong data PID Table 27 BIT DESCRIPTION Data receive transmit a 1 indicates data has been received or transmitted successfully Error code see Table 26 Setup packet a 1 indicates the last received packet had a SETUP token this will always read 0 for IN buffers Data 0 1 packet a 1 indicates the last received packet had a DATA 1 PID Previou
46. kages with a pitch e equal to or larger than 0 65 mm it is definitely not suitable for packages with a pitch e equal to or smaller than 0 5 mm 1999 May 10 50 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development Preliminary specification This data sheet contains preliminary data supplementary data may be published later Product specification This data sheet contains final product specifications Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Where application information is given it is advisory and does not form part of the specification LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips customers using or selling these products for use in such applicat
47. l Serial Bus USB CODEC The data in the buffer are organized as follows Byte 0 transfer successful number of data bytes MSB Byte 1 number of data bytes LSB Byte 2 data byte 0 Byte 3 data byte 1 Byte 4 data byte 2 Byte 5 data byte 3 Byte 6 data byte 4 Byte 7 data byte 5 Byte 8 data byte 6 Byte 9 data byte 7 Bytes 0 and 1 indicate the number of bytes in the buffer Byte 0 is the Most Significant Byte MSB Byte 1 is the Least Significant Byte LSB Only bits 1 and O of byte 0 are used in the number of bytes indication Bit 7 of byte 0 indicates if the transaction was successful bit 7 is 1 if the transaction was successful Bits 6 to 2 of byte 0 are reserved WRITE BUFFER Command FOh Data write n bytes max 10 The write buffer command is followed by a number of data writes which load the endpoint buffer After each write the internal buffer pointer is incremented by 1 The buffer pointer is not resetto the buffer start by the write buffer command This means that writing a buffer can be interrupted by any other command except for select endpoint The data must be organized in the same way as described in the read buffer command Bits 7 to 2 of byte 0 are reserved and must be filled with zeros ACKNOWLEDGE SETUP Command F1h Data none The arrival of a SETUP packet flushes the IN buffer and disables the validate buffer and clear buffer commands for both IN and OUT endpoints The mi
48. l jitter for paired transitions tw EOP source end of packet width tEOP diff differential to end of packet transition skew receiver data jitter tolerance to next transition receiver data jitter tolerance for paired transitions tEOPR1 end of packet width at receiver must reject as end of packet tEoPR2 end of packet width at receiver must accept as end of packet Serial input output data timing System clock frequency word selection input frequency rise time fall time tBCK H bit clock HIGH time bit clock LOW time data set up time data hold time word selection set up time word selection hold time 1999 May 10 40 Philips Semiconductors Universal Serial Bus USB CODEC SYMBOL PARAMETER CONDITIONS Preliminary specification UDA1325 SDA and SCL lines for 100 kHz I C devices scL SCL clock frequency bus free time between a STOP and START condition tLow hold time repeated START condition LOW period of the SCL clock tHIGH HIGH period of the SCL clock set up time for a repeated START condition tuD DAT set up time for STOP condition data hold time tsu DAT data set up time rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line Oscillator 1 system clock fosc oscillator frequency 5 9 duty factor transconductance m Ro
49. layback sampling frequencies By means of a Sample Frequency Generator SFG the ADAC is able to reconstruct the average sample frequency from the incoming audio samples The ADAC also performs the playback sound processing The ADAC consists of a FIFO an unique audio feature processing DSP the SFG digital filters a variable hold register a Noise Shaper NS and a Filter Stream DAC FSDAC with line output drivers The audio information is applied to the ADAC via the USB processor or via the digital I S input of the digital I O module The ADIF consists of an Programmable Gain Amplifier PGA an Analog to Digital Converter ADC and a Decimator Filter DF An Analog Phase LockLoop APLL or oscillator is used for creating the clock signal of the ADIF The clock freguency for the ADIF can be controlled via the microcontroller Several clock freguencies are possible for sampling the analog input signal at different sampling rates The wide dynamic range of the bitstream conversion technigue used in the UDA1325 for both the playback and recording channel guarantees a high audio sound guality PACKAGE NAME DESCRIPTION VERSION UDA1325PS SDIP42 plastic shrink dual in line package 42 leads 600 mil SOT270 1 UDA1325H GFP64 plastic quad flat package 64 leads lead length 1 95 mm SOT319 2 body 14 x 20 x 2 8 mm 1999 May 10 3 Philips Semiconductors Preliminary specification Universal Serial Bus USB
50. must be parallel to the transport direction of the printed circuit board The footprint must incorporate solder thieves at the downstream end For packages with leads on four sides the footprint must be placed at a 45 angle to the transport direction of the printed circuit board The footprint must incorporate solder thieves downstream and at the side corners During placement and before soldering the package must be fixed with a droplet of adhesive The adhesive can be applied by screen printing pin transfer or syringe dispensing The package can be soldered after the adhesive is cured Typical dwell time is 4 seconds at 250 C A mildly activated flux will eliminate the need for removal of corrosive residues in most applications MANUAL SOLDERING Fix the component by first soldering two diagonally opposite end leads Use a low voltage 24 V or less soldering iron applied to the flat part of the lead Contact time must be limited to 10 seconds at up to 300 C When using a dedicated tool all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 Suitability of IC packages for wave reflow and dipping soldering methods SOLDERING METHOD MOUNTING PACKAGE REFLOW DIPPING Through hole mount DBS DIP HDIP SDIP SIL suitable suitable Surface mount BGA SQFP not suit
51. n the mute is released the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in reversed order The mute on the master channel is synchronized to the sample clock so that operation always takes place on complete samples 1999 May 10 16 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 Volume control The volume of the UDA1325 can be controlled from 0 dB down to 60 dB in steps of 1 dB Below 60 dB the audio signal is muted e dB The setting of 0 dB is always referenced to the maximum available volume setting Independant volume control of the left and right channel is possible balance control Table9 Volume settings right playback channel 1999 May 10 17 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 Treble control For the playback channel treble can be regulated in three audio modes minimum flat and maximum mode In flat mode the audio is not influenced In minimum and maximum mode the treble range is from 0 to 6 dB in steps of 2 dB The programmable treble filter is implemented digitally and has a fixed corner freguency of 3000 Hz for the minimum mode and 1500 Hz for the maximum mode Because of the exceptional amount of programmable gain treble should be used with adeguate prior attenuation using volume control Table
52. nsfer type audio feature registers When the data transfer type audio feature registers is selected 4 audio feature registers can be selected depending on bits 7 and 6 of the data byte see Table 7 1999 May 10 14 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 Table 7 ADAC audio feature registers BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO REGISTER VRO volume right L volume left DATA_TRANSFER_TYPE VLO BBO bass TRO treble The sequence for controlling the ADAC audio feature registers via the L3 bus is given in the figure below DEVICE ADDRESS 5 L3 MODE LOW L3 DATA 0 0 1 bit 0 0 1 0 0 0 bit 7 LEFT VOLUME TREBLE REGISTER RIGHT VOLUME BASS ADDRESS L3 MODE HIGH L3 DATA X X X X X X X X bit 0 bit 7 L3 CLK Data transfer type control registers zr des apres E epe da SEAT MGS270 When the data transfer type control registers is selected 2 general control registers can be selected depending on bit 7 of the data byte see Table 7 The sequence for controlling the ADAC control registers via the L3 bus is given in the figure below DATA TRANSFER TYPE DEVICE ADDRESS 5 L3 MODE LOW L3 DATA 0 1 1 0 1 0 0 0 bit 0 bit 7 REGISTER DATA OF THE CONTROL REGISTER ADDRESS L3 MODE HIGH L3_DATA X X x x x x x x bit 0 bit 7 L3_CLK 1999 May 10 MGS269 15 Philips Sem
53. old function increase the oversampling rate to 128f The noise shaper A 3rd order noise shaper converts the oversampled data to a noise shaped bitstream for the FSDAC The in band quantization noise is shifted to frequencies well above the audio band The Filter Stream DAC FSDAC The FSDAC is a semi digital reconstruction filter that converts the 1 bit data stream of the noise shaper to an analog output voltage The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier In this way very high signal to noise performance and low clock jitter sensitivity is achieved A post filter is not needed because of the inherent filter function of the DAC On board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 USB ENDPOINT DESCRIPTION The UDA1325 has following six endpoints e USB control endpoint 0 e USB control endpoint 1 e USB status interrupt endpoint 1 e USB status interrupt endpoint 2 sochronous data sink endpoint sochronous data source endpoint Table 5 Endpoint description ENDPOINT ENDPOINT MAX PACKET NUMBER INDEX ENDPOINT TYPE DIRECTION SIZE BYTES control default control interrupt in interrupt in isochronous out out isochronous in in CONTROLLING THE PLAYBACK FEATURES
54. olled by bit 4 of control register 0 The de emphasis filter can be switched on or off The digital de emphasis filter is dimensioned to produce the de emphasis frequency characteristics for the sample rate 44 1 kHz De emphasis is synchronized to the sample clock so that operation always takes place on complete samples 1999 May 10 19 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 Filter characteristics playback channel The overall filter characteristic of the UDA1325 in flat mode is given in Fig 4 de emphasis off The overall filter characteristic of the UDA1325 includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC fs 44 1 kHz MGM110 0 20 volume dB 40 100 120 140 160 0 f KHz Fig 4 Overall filter characteristics of the UDA1325 1999 May 10 20 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 DSP extension port for enhanced playback audio processing An external DSP can be used for adding extra sound processing features via the I S inputs and outputs of the digital I O module The UDA1325 supports the standard l2S bus data protocol and the LSB justified serial data input format with word lengths of 16 18 and 20 bits Using the 4 pin digital I
55. orted 5 6448 44 1 2 8224 22 05 1 4112 11 025 0 7056 5 5125 6 144 48 1 536 12 0 768 6 11 2896 12 2880 A P CO BY PO CO BY PO Table 3 ADC clock frequencies and sample frequencies based upon using the OSCAD as a clock source OSCAD CLOCK FREQUENCY MHz DIVIDE FACTOR Q ADC CLOCK FREQUENCY MHz SAMPLE FREQUENCY kHz fosc ae foso 2O foso 256Q Notes 1 The oscillator frequency and therefore the crystal of OSCAD must be between 8 192 and 14 08 MHz 2 The Q factor can be 1 2 4 or 8 3 Sample frequencies below 5 kHz and above 55 kHz are not supported 1999 May 10 11 Philips Semiconductors Universal Serial Bus USB CODEC The Asynchronous Digital to Analog Converter ADAC The ADAC receives audio data from the USB processor or from the digital O bus The ADAC is able to reconstruct the sample clock from the rate at which the audio samples arrive and handles the audio sound processing After the processing the audio signal is upsampled noise shaped and converted to analog output voltages capable of driving a line output The ADAC consists of e A Sample Frequency Generator SFG e FIFO registers e An audio feature processing DSP Two digital upsampling filters and a variable hold register A digital Noise Shaper NS A Filter Stream DAC FSDAC with integrated filter and line output drivers The Sample Frequency Generator SFG T
56. rface 2 0 reset off 1 reset on reset ADIF 1 0 reset off 1 reset on reserved 0 X 1999 May 10 26 Philips Semiconductors Universal Serial Bus USB CODEC Table 21 I O selection register Preliminary specification UDA1325 ADDRESS REGISTER I O selection register COMMENTS microcontroller control on 48 MHz oscillator 0 UPC control disabled 48 MHz oscillator is enabled 1 UPC control enabled audio format GP4 I O if BITO 1 GP3 I O if BITO 1 00 4 pins 12S 01 6 pins 12S 10 3 pins 12S only input 11 3 pins 12S only input 0 output 1 input GP2 I O if BITO 1 GP1 I O if BITO 1 0 output 1 input GP4 to GP1 function 0 I S usage 1 general purpose usage Table 22 Power control register ADDRESS REGISTER COMMENTS VALUE 1003h power control register analog modules 1999 May 10 suspend input selection for P3 1 of the microcontroller interrupt input selection for P3 3 INT1_N of the microcontroller power APLL power FSDAC 0 suspend from USB interface connected to P3 1 during normal operation 1 suspend from restart circuit connected to P3 1 e g after power down 0 interrupt from USB interface connected to P3 3 during normal operation 1 interrupt from restart circuit connected to P3 3 e g after power down 0 power on 1 power off 0 power on 1 power off power ADC left po
57. s status not read a 1 indicates a second event occurred before the previous status was read 1999 May 10 33 Preliminary specification UDA1325 SET ENDPOINT STATUS Command 40h endpoint index Data write 1 byte This command is used to stall or unstall an endpoint Only the least significant bit has a meaning When the stalled bit is equal to 1 the endpoint is stalled when equal to 0 the endpoint is unstalled There is one command for every endpoint A stalled control endpoint is automatically unstalled when it receives a SETUP token regardless of the contents of the packet If the endpoint should stay in stalled state the microcontroller should restall it When a stalled endpoint is unstalled it is also re initialized This means that its buffer is flushed and the next DATA PID that will be sent or expected depending on the direction of the endpoint is DATAO 7 6 5 4 3 2 1 0 X X X X X X x0 Power On Value Stalled Reserved READ BUFFER Command FOh Data read n bytes max 10 The read buffer command is followed by a number of data reads which returns the contents of the selected endpoint data buffer After each read the internal buffer pointer is incremented by 1 The buffer pointer is not reset to the buffer start by the read buffer command This means that reading a buffer can be interrupted by any other command except for select endpoint Philips Semiconductors Universa
58. tected on the P3 3 INT1_N of the microcontroller At this moment following actions should be taken by the microcontroller The Power down mode of the microcontroller must be switched off Re initialise all GP pins All analog modules of the UDA1325 must be switched on this can be done by setting bits 5 to O of the power control register to O and bit 0 of the clock shop register to 0 Bit 6 of the power control register mux ctrl int1 must be set to 0 in order to connect the PSIE MMU INT output pin of the USB processor again with P3 3 INT1_N of the microcontroller The UDA1325 is now back in its normal operation mode and can be put back in power reduction mode by the falling edge of the CLK_ON signal of the USB processor 1999 May 10 29 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 COMMAND SUMMARY COMMAND NAME RECIPIENT CODING DATA PHASE Initialization commands Set address enable device Read address enable device Set endpoint enable device write 1 byte read 1 byte Read endpoint enable device Set mode device write 1 byte read 1 byte write 1 byte Data flow commands Read interrupt register device Select endpoint control OUT read 1 byte read 1 byte optional control IN other endpoints 00h endpoint index read 1 byte optional read 1 byte optional Get endpoint status control OUT 40h control IN 41h read 1 byte
59. the enable bit is set to O READ ENDPOINT ENABLE Command D8h Data read 1 byte The read endpoint enable command is used to read the enable bit for the non default endpoints of the function The format of the data phase is the same as for the set endpoint enable command SET MODE Command F3h Data write 1 byte Philips Semiconductors Universal Serial Bus USB CODEC Reset value Bus Reset IsoOut Isoln IntlsoOut Intlsoln ErrorbebugMode AlwaysPLLClock Reserved Reserved Reset value gives the value of the bits after Power on reset Bus reset a F indicates that the value of the bit is not changed during a bus reset a T indicates that during a bus reset the bit is reset to its reset value Table 25 BIT DESCRIPTION IsoOut ISO out endpoint can be used Isoln ISO in endpoint can be used IntlsoOut allow interrupt from ISO out endpoint Intlsoln allow interrupt from ISO in endpoint Setting chip in debug mode ErrorbebugMode AlwaysPLLClock the PLL clock must keep on running Data flow commands Data flow commands are used to manage the data transmission between the USB endpoints and the host Much of the data flow is initiated via the interrupt to the microcontroller The microcontroller uses these commands to access the endpoint buffers and determine whether the endpoint buffers have valid data READ INTERRU
60. token the IN buffer is cleared If the microcontroller is still filling the buffer when the second SETUP token arrives the SETUP token will clear the IN buffer If the microcontroller has filled the IN buffer it will validate the buffer So clearing the IN buffer on receiving a SETUP token is not enough If a SETUP token is received the device will also disable the validate buffer command for the IN buffer If the microcontroller needs to fill the buffer after a SETUP token the command acknowledge setup command must be sent to enable the validate buffer command CLEAR BUFFER Command F2h Data none When a packet is received completely an internal endpoint buffer full flag is set All subsequent packets will be refused by returning a NACK to the host When the microcontroller has read the data it should free the buffer by the clear buffer command When the buffer is cleared new packets will be accepted Philips Semiconductors Universal Serial Bus USB CODEC VALIDATE BUFFER Command FAh Data none When the microcontroller has written data into an IN buffer it should set the buffer full flag by the validate buffer command This indicates that the data in the buffer are valid and can be sent to the host when the next IN token is received General commands READ CURRENT FRAME NUMBER Command F5h Data read 1 or 2 bytes This command is followed by one or two data reads and returns the frame number of the last s
61. ts audio samples 11 24 bits audio samples mono stereo selection 4 0 mono selection audio input recording 3 0 digital serial audio input selection high pass filter of 2 0 high pass filter off I2S bus input serial input format 1 and 0 00 I S bus recording channel 01 16 bit LSB justified 10 18 bit LSB justified 11 20 bit LSB justified 1999 May 10 25 Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 Table 19 Clock shop register ADDRESS REGISTER COMMENTS BIT VALUE clock shop settings selection ADC clock source divide factor O clock ADAC 6 and 5 0 ADC clock from APLL 1 ADC clock from OSCAD 00 ADC clock divided by 1 01 ADC clock divided by 2 10 ADC clock divided by 4 11 ADC clock divided by 8 0 enable 1 disable clock 48 MHz internal clock recovered by PSIE ADC clock 0 enable 1 disable 0 enable 1 disable 0 enable 1 disable OSCAD oscillator Table 20 Reset control and APLL register 0 power on 1 power off ADDRESS REGISTER COMMENTS BIT VALUE 1001h reset control and APLL fcode 1 and 0 7 and6 00 256 x 44 1 kHz settings clock frequency selection APLL 01 256 x 32 kHz 10 2 256 x 48 kHz 11 256 x 44 1 kHz reserved 5 X reset ADAC 4 0 reset off 1 reset on reset MMU 3 0 reset off 1 reset on reset digital I O inte
62. uccessfully received SOF The frame number is eleven bits wide The frame number is returned least significant byte first In case the user is only interested in the lower 8 bits of the frame number only the first byte needs to be read I C MASTER SLAVE INTERFACE The 12C module implements a master slave I2C bus interface with integrated shift register shift timing generation and slave address recognition It is compliant to the l2C bus specification IC20 Jan92 I C standard mode 100 kHz SCL and fast mode 400 kHz are supported Low speed mode and extended 10 bit addressing are unsupported Characteristics of the I2C bus The I C bus is for 2 way 2 line communication between different ICs or modules The two lines are a serial data line SDA and a Serial Clock Line SCL Both lines must be connected to Vppe via a pull up resistor The timing definition of the IZC bus is given in Fig 7 Programmer s view For a detailed description of the I C bus protocol refer to Philips Integrated Circuits Data Handbook IC20 8XC552 The programmer s view of the 12C library function is with one exception identical to that of the 8XC552 microcontroller Only the bit rate frequency selection in S1CON and the handling of the Timer 1 overflow information deviates to accommodate 400 kHz operation 1999 May 10 35 Preliminary specification UDA1325 S1CON register The CPU can read from and write to this 8 bit SFR Two bits are effe
63. wer ADC right 0 power on 1 power off 0 power on 1 power off power PGA left 0 power on 1 power off power PGA right 27 0 power on 1 power off Philips Semiconductors Preliminary specification Universal Serial Bus USB CODEC UDA1325 Table 23 ASR control register ADDRESS REGISTER ASR control register COMMENTS robust word clock 0 off not recommended 1 on recommended serial I2S bus output format 6 and 5 00 I S bus digital I O interface 01 16 bit LSB justified 10 18 bit LSB justified 11 20 bit LSB justified 0 mono phase inversal off phase inversion on right mono 4 output 1 mono phase inversal on 00 reserved 01 8 bit audio 10 16 bit audio 11 24 bit audio 0 mono bits per sample modi 3 and 2 mono or stereo operation 1 1 stereo ASR register start up mode 0 stop e g at alternate setting with bandwidth equal to zero 1 go START UP BEHAVIOUR AND POWER MANAGEMENT Start up of the UDA1325 After power on of Vppa1 an internal Power on reset signal becomes HIGH after a certain RC time This RC time is created by using the internal resistor 2 x 50 kQ divider for creating the reference voltage for the FSDAC in combination with the capacitor connected externally to the Vrerpa pin The FSDAC and the internal resistor divider are supplied by VppA1 and

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