Omega Vehicle Security DAQ-16 User's Manual
Contents
1. Y OMEGA ENGINEERING INC Data Acquisition Adapter for 16 bit ISA compatible machines Users Manual INTERFACE CARDS FOR PERSONAL COMPUTERS OMEGA ENGINEERING INC TEL 203 359 1660 One Omega Drive FAX 203 359 7700 P O Box 4047 Toll free 1 800 826 6342 Stamford CT 06907 4047 E mail das omega com http www dasieee com WARRANTY DISCLAIMER OMEGA ENGINEERING INC warrants this unit to be free of defects in materials and workmanship for a period of 13 months from the date of purchase OMEGA warranty adds an additional one 1 month grace period to the normal one 1 year product warranty to cover shipping and handling time This ensures that OMEGA S customers receive maximum coverage on each product If the unit should malfunction it must be returned to the factory for evaluation OMEGA s Customer Service Department will issue an Authorized Return AR number immediately upon phone or written reguest Upon examination by OMEGA if the unit is found to be defective it will be repaired or replaced at no charge OMEGA s warranty does not apply to defects resulting from any action of the purchaser including but not limited to mishandling improper interfacing operation outside design limits improper repair or unauthorized modification This WARRANTY is VOID if the unit shows evidence of having been tampered with or shows evidence of being damaged as a result of excessive corrosion or current heat moisture or vibration2. channels are to be used each channel must be jumpered to a different number i e channel 1 is jumpered to DRO 5 DACK 5 and channel 2 is jumpered to DRO 7 DACK 7 DAO 16 Users Manual 21 2 8 Interrupts The DAQ 16 is capable of generating an interrupt from one of four sources 1 End of conversion signal 2 DMA terminal count 3 Multi function timer output 4 External interrupt input The interrupt source is software selected through the DAQ 16 control word register The interrupt level is selected using the jumpers J10 and J11 as shown in Figure 2 11 IRQ10 O o o RR g Factory default IRQ 5 Figure 2 11 Jumpers J10 and J11 Configuration 2 8 1 External Interrupt The external interrupt is a TTL compatible input from the D 62 connector An interrupt request is generated on a high to low transition of this input DAQ 16 Users Manual 22 3 External Connections The DAO 16 is eguipped with a high density 62 pin connector as shown in Figure 3 1 2 CH1 3 4 CH2 O 6 CH4 O 8 CH5 10 CH7 O 12 AOUTO 14 DOUTO 6 6 DOUT3 5 18 EXT TRIG O 20 DIN1 22 CHO 24 CH1 OnO 26 CH3 28 CH4 O 30 CH6 32 CH7 O 34 AOUT1 36 DOUT1 GG 38 EXT INT G 40 DIN3 42 DINO OPEO 43 CHO 45 CH2 47 CH3 O 49 CH5 51 CH6 53 VREFO 55 VREF1 a 57 DOUT2 59 EXT CLK O 61 DIN2 Figure 3 1 62 Pin Connector
3. N D o 2 e wD S o ug Y o oD 6D 5 N e gt S o o a q N 6D S a gt o a o a o Me E O Z z S YN ov O rU N H o Q z gt me rU o J Q o YN op 8 o YN amp op o gt FO O im S D E o op o gt 2 o A z D E A E o No E oO o z py a un oD 6D S H o 6D o gt A SS lt o Ke rU o o o x o o S 11 DAQ 16 Users Manual The final stage of the A D converter circuit is the A D converter IC The converter must be configured for unipolar or bipolar input voltages and for binary or 2 s complement data conversion These options are selected using jumper J5 as shown in Figure 2 3 below Unipolar J5 4 5 6 SIDO ODO L 2 3 Lid 3 Binary 2 s complement Figure 2 3 Jumper J5 Configuration To simplify the following discussions a new variable Vmax is introduced Vmax is defined as the maximum input voltage amplitude and is egual to the A D range selected by jumper J6 divided by the amplifier gain defined by jumper J7 In eguation form A D range When configured for unipolar operation the input voltage may range from 0 volts analog ground to Vmax volts as defined above When configured for bipolar operation the input voltage may range from Vmax volts to Vmax volts The digit
4. control the sampling rate directly the frequency of the external clock input may be varied from DC to 100 KHz as long as the width of the low and high portions of the clock are a minimum of 1 us each The A D conversion cycle will begin on each rising edge of the external clock input See Figure 2 7 1 usec min 1 usec min 10 usec min Figure 2 7 Sampling Rate External Clock Pulses DAQ 16 Users Manual 19 When the multi function timer is used as a pre divider the freguency of the external clock input may be varied from DC to 10 MHz as long as the high portion of the clock is at least 30ns and the low portion is at least 50ns Except for the first period the sampling rate of the DAO 16 will be the external clock freguency divided by the count value written to the multi function timer Since one clock pulse is reguired to load the initial count value into the timer the first sampling interval will be one clock cycle longer than the rest The valid range of count values for the multi function timer is 2 lt count lt 65 595 but the resulting sampling rate must be less than 100KHz to assure proper operation of the A D converter circuitry See Figure 2 8 30 nsec min 50 nsec min 100 nsec y min Figure 2 8 Pre Divider External Clock Pulses 2 6 Trigger Selection The DAQ 16 is capable of accepting an internal software trigger or an external hardware trigger The trigger selection and trigger leve
5. improper specification misapplication misuse or other operating conditions outside of OMEGA s control Components which wear are not warranted including but not limited to contact points fuses and triacs OMEGA is pleased to offer suggestions on the use of its various products However OMEGA neither assumes responsibility for any omissions or errors nor assumes liability for any damages that result from the use of its products in accordance with information provided from OMEGA either verbal or written OMEGA warrants only that the parts manufactured by it will be as specified and free of defects OMEGA MAKES NO OTHER WARRANTIES OR REPRESENTATIONS OF ANY KIND WHATSOEVER EXPRESSED OR IMPLIED EXCEPT THAT OF TITLE AND ALL IMPLIED WARRANTIES INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED LIMITATION OF LIABILITY The remedies of purchaser set forth herein are exclusive and the total liability of OMEGA with respect to this order whether based on contract warranty negligence indemnification strict liability or otherwise shall not exceed the purchase price of the component upon which liability is based In no event shall OMEGA be liable for conseguential incidental or special damages CONDITIONS Equipment sold by OMEGA is not intended to be used nor shall it be used 1 as a Basic Component under 10 CFR 21 NRC used in or with any nuclear installation or activity medical applicatio
6. 5 Clock Rate Register low word ei G ES 27 4 1 6 Clock Rate Register high word a 5 Se xe Au Mee we ke Me RA a 27 4 1 7 Multi Function Timer Register ss 34 242 inca GDG dnd DG GO UG 27 4 1 8 8254 Control Word Status Register ou soi RE YN YY Y nh 27 4 2 Programming the 8254 Counter Timer Y ie 28 DAO 16 Users Manual 6 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 8 Figure 2 9 Figure 2 10 Figure 2 11 Figure 3 1 Table 2 1 Table 2 2 Table 2 3 Table 4 1 List of Figures and Tables Jumper T Configuration eu NN SA E ASA 11 Jumper J6 Configuration rata RA ARA AR RA AG G BOE 11 Jumper J5 Configuration vd A E GN a ss 12 Jumper J3 Configuration rai RN ER NY eter wae es 14 I O Base Address Selection cc cece cee cece eee uu eens 16 Jumper J2 Configuration ee AE ore ee eae ore he as Gore ee FO ES 17 Sampling Rate External Clock Pulses 5 23b i wu ae hu Sed oe EU dyw AG ae UO 19 Pre Divider External Clock Pulses gt R iA 04590 TAR DOG YDD FOA 20 Jumper J1 Configuration est pot poes tas a E 20 Jumpers J8 and J9 Configuration YY FF EF Yu uu 21 Jumpers J10 and J11 Configuration esis eau ie S aS GYN Eee NAU 22 62 Pi Connector Diaeran ci ele uate arw te bro WING weet ae wh lel eat a lnk ee 23 A D Converter Configurations dur a Stara a Tw e 10 A D Conversion Format Examples Y YY FFF Fu Hd 13 Jumper J4 Configuration astas das 15
7. DAG RIG Address Map masr esau ara GWD YR EE R GDG UD 25 DAO 16 Users Manual 7 1 Introduction The DAO 16 is a high speed data acguisition adapter for IBM AT compatible machines offering eight differential analog input channels with 16 bit resolution two analog output channels with 12 bit resolution and four digital input output lines Other features of the DAO 16 include Analog to Digital Converter e 100 KHz maximum sampling rate Bipolar input ranges of 2 5 5 and 10 volts Unipolar input ranges of 0 to 2 5 0 to 5 and 0 to 10 volts Selectable gain of 1 10 and 100 Two DMA channels for continuous acquisition Internal or external clock and trigger Digital to Analog Converters Two independent analog output channels Output ranges of 0 to 5 volts and 5 volts Internal or external voltage reference Other Features Interrupt on one of four sources including an external interrupt input High density D 62 connector for reduced noise 1 1 Installation 1 Configure the DAQ 16 utilizing the instructions in Chapter 2 Circuit Board Description and Configuration 2 Ensure that power is not applied to the computer system 3 Remove the cover according to the instructions provided by the system manufacturer 4 Insert the DAC 16 into any vacant ISA expansion slot The board is secured to the slot by installing the Option Retaining Bracket ORB screw 5 Replace the system cover pe
8. DAO 16 uses 16 consecutive I O address locations in the range 0 to OFFFFH Two six position switches SW1 and SW2 are used to select the base address SW1 controls address lines A15 A10 and SW2 controls A9 A4 Address lines A3 AO are used internally by the DAO 16 to select which register to access When selecting a base address for the DAO 16 an address selection switch in the OFF position corresponds to an address bit of 1 while a switch in the ON position corresponds to an address bit of 0 The base address of the DAO 16 must be set on a 16 byte boundary meaning A3 A0 are 0 The address of the DAO 16 as shipped from the factory is 0300H This setting and other examples are shown in the Figure 2 5 L T 1 Xxxx Hex 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Examplel Base I O Address 0300H 1011 1100 D 1101 01 1110 El 1111 A 0 1 4 3 mmgow boo c oAu ADN O 1 4 Example 2 Base I O Address 6ADOH Figure 2 5 I O Base Address Selection DAO 16 Users Manual 16 2
9. Diagram Analog Ground 1 3 5 7 9 11 13 44 46 48 50 52 54 Digital Ground 15 17 19 21 37 39 41 56 58 60 62 DAO 16 Users Manual CHO0 CH0 CH7 CH7 Analog inputs to the analog to digital converter Amplitude and polarity depend upon jumper settings The input resistance of these lines is 1 5K ohms typical AOUTO AOUT1 Analog outputs from the digital to analog converters Polarity and maximum amplitude depend on the jumper settings and voltage references Output resistance of the analog outputs is typically 70 ohms VREFO VREF1 External voltage references for the digital to analog converters Input range is O to 5 5 volts with a no load input resistance of 7 5K ohms EXT CLK EXT TRG EXT INT External clock trigger and interrupt inputs respectively Inputs are TTL compatible DOUTO DOUT1 DOUT2 DOUT3 TIL compatible digital output lines DINO DIN1 DIN2 DIN3 TTL compatible input lines DAO 16 Users Manual 24 4 Register Description and Programming The DAO 16 uses 16 consecutive I O address locations in the range 0 to FFFFH The card utilizes these addresses for the registers listed in Table 4 1 indicates registers located in 8254 counter Base 0 1 Read Write 16 bit Control Word Register Base 2 3 Write only 16 bit Start Conversion Register 16 bit A D Data Register Read only Base 4 5 Write only 16 bit D A Channel 0 Register Base 6 7 Write only 1
10. 3344 E mail nl omega com Czech Republic ul Rude armady 1868 733 01 Karvina Hraniee Tel 42 69 6311899 FAX 42 69 6311114 Toll Free 0800 1 66342 E mail czech omega com France 9 rue Denis Papin 78190 Trappes Tel 33 130 621 400 Toll Free in France 0800 4 06342 E mail france omega com Germany Austria Daimlerstrasse 26 D 75392 Deckenpfronn Germany Tel 49 07056 3017 Toll Free in Germany 0130 11 21 66 E mail germany omega com DAQ 16 Users Manual United Kingdom One Omega Drive River Bend Technology Drive ISO 9002 Certified Northbank Irlam Manchester M44 5EX England Tel 44 161 777 6611 FAX 44 161 777 6622 Toll Free in England 0800 488 488 E mail info omega co uk It is the policy of OMEGA to comply with all worldwide safety and EMC EMI regulations that apply OMEGA is constantly pursuing certification of it s products to the European New Approach Directives OMEGA will add the CE mark to every appropriate device upon certification The information contained in this document is believed to be correct but OMEGA Engineering Inc accepts no liability for any errors it contains and reserves the right to alter specifications without notice WARNING These products are not designed for use in and should not be used for patient connected applications DAQ 16 Users Manual 4 Declaration of Conformity Manufacturer s Name Omega Engineering Inc Manufacturer s Address One Omega Driv
11. 5 Clock Selection The DAO 16 is equipped with a programmable clock circuit to produce data sampling rates independent from the clock rate of the host computer An onboard 8254 programmable interval timer with a 10 MHz clock input and either two or three cascaded 16 bit timers provides the sampling rate This enables the sampling rate to be adjusted from 10 us between samples to almost a year between samples in as small as 100ns increments The DAO 16 s sampling rate can also be generated from an external clock input This external clock can be connected directly to the A D converter or through a 16 bit pre divider the multi function timer Samples are taken on the low to high transition of the clock WARNING For the DAO 16 the maximum data sampling rate is 10 us This restricts clock freguency to a maximum of 100 KHz Sampling rates in excess of 100 KHz may result in erratic operation and unpredictable results The clock source internal or external clock is software selectable through the DAO 16 s control word register The configuration of the clock source itself is controlled by jumper block J2 as shown in Figure 2 6 indicates factory default Internal Timer 2 timers cascaded connect 1 2 6 7 3 timers cascaded connect 2 6 7 8 External Timer w o pre divider connect 1 2 3 4 with pre divider connect 2 3 4 8 Figure 2 6 Jumper J2 Configuration DAO 16 Users Manual 17 2 5 1 Internal Clock
12. 6 bit D A Channel 1 Register Base 8 Read Write 8 bit Digital Input Output Register Base 9 A B Reserved Base C Read Write 8 bit Clock Rate Register low Base D Read Write 8 bit Clock Rate Register high Base E Read Write 8 bit Multi function Timer Register Base F Read Write 8 bit 8254 Control Word Status Register Table 4 1 DAQ 16 Address Map 4 1 Register Description 411 Control Word Register The control word register defines and controls many of the DAO 16 s data conversion functions This register is 16 bit read write Write D15 INT2 D14 INTI D13 INTO D12 DMAEN D11 DMACT D10 LEVEL D9 TRIG D8 CLK Read INT2 INT1 INTO DMAEN DMACH LEVEL TRIG CLK Write Read D7 RUN RUN D6 0 EOC D5 0 VALID D4 0 0 D3 0 0 D2 CHSL2 CHSL2 D1 CHSL1 CHSL1 DO CHSLO CHSLO INT2 INT1 and INTO control the DAO 16 interrupt source INT2 hhh o INT1 ee OO oO INTO DESCRIPTION 0 Interrupt disabled 0 Interrupt timer 2 1 Interrupt on terminal count 0 External interrupt 1 Interrupt on end of conversion DAQ 16 Users Manual 25 DMAEN enables disables DMA When set logic 1 DMA transfers are enabled DMACT enables the multi channel DMA capability of the DAQ 16 When set logic 1 a terminal count on the active DMA channel causes DMA transfers to begin on the stand by channel When cleared logic 0 DMA transfers halt when the ter
13. HSL1 CHSLO select the multiplexer channel for the analog input signal CHSL2 CHSL1 CHSLO MUX channel 0 0 0 channel 0 0 0 1 chamnel 1 0 1 0 channel 2 0 1 1 channel 3 1 0 0 channel 4 1 0 1 channel 5 1 1 0 channel 6 1 1 1 channel 7 DAO 16 Users Manual 26 4 1 2 Start of Conversion Register The start of conversion register is 16 bit write only and performs two functions 1 When configured for internal triggering writing a 0 to this register generates the software trigger starting the data conversion process 2 Writing a 0 to this register at any time resets the VALID bit in the control word register This allows the VALID bit to be reset at any time during the conversion process or before the event of an external trigger 4 1 3 DACO Register An output to this register causes the lower twelve bits of data to be converted to an analog output on D A converter channel 0 The four most significant bits of data are ignored This register is 16 bit write only 4 1 4 DACI Register An output to this register causes the lower twelve bits of data to be converted to an analog output on D A converter channel 1 The four most significant bits of data are ignored This register is 16 bit write only The remaining four registers are contained in an 8254 counter timer 4 15 Clock Rate Register low word The low word of the clock divider is contained in counter 0 of an 8254 counter timer The output of this counter is cascad
14. Sampling rates for theinternal clock can be calculated using the following eguation t 100ns N1 N2 or f 10MHz N1 N2 where N1 is the low 16 bits of the clock divider and N2 is the high 16 bits of the clock divider The following criteria must be met when selecting values for N1 and N2 2 lt N1 lt 65 535 2 lt N2 lt 65 35 N1 N2 gt 100 Using the equations above the minimum and maximum data sampling rates for the internal clock can be calculated Maximum sampling rate Minimum Sampling Rate N1 2 N2 50 N1 65535 N2 65535 t 100 x 10 2 50 t 100 x 10 65535 65535 t 100 x 10 100 t 100 x 10 4 295 x 10 t 10 us t 429 5 sec f 10x 10 2 50 f 10 x 106 65535 65535 f 10x10 100 f 10 x 10 4 295 x 10 f 100 Khz f 2 328 mHz If extremely slow data sampling rates are needed the third 8254 timer the multi function timer can be cascaded with the other two to produce a 48 bit clock divider The sampling rates are then calculated as follows t 100ns N1 N2 N3 or f 10MHz N1 N2 N3 where N1 is the low 16 bits of the clock divider N2 is the intermediate 16 bits of the clock divider and N3 is the high 16 bits of the divider The following criteria must be met when selecting values for N1 N2 and N3 2 lt N1 lt 65 535 2 lt N2 lt 65 535 2 lt N3 lt 65 535 N1 N2 N3 gt 100 DAQ 16 Users Manual 18 When configured for a 48 bit divider t
15. al code generated for any specific voltage is dependent upon the operating mode unipolar or bipolar and the data conversion format binary or 2 s complement Binary conversion will result in unsigned integers ranging from 0 to 65 535 while 2 s complement conversion will produce signed integers ranging from 32 768 to 32 767 Table 2 2 lists A D conversion format examples Unipolar entries marked n a are not applicable because the voltage is outside of the unipolar voltage range DAO 16 Users Manual 12 Voltage Binary Binary 2 s Complement 2 s Complement unipolar bipolar unipolar bipolar Vmax n a 0 n a 32 768 Vmax 2 n a 416 384 n a 16 384 0 0 32 768 32 768 0 Vmax 2 32 768 49 152 0 16 384 Vmax 65 935 65 535 32 767 32 767 Table 2 2 A D Conversion Format Examples In order to calculate the actual input voltage from the digital code provided by the DAQ 16 the user must know the configuration used to acquire the data Given this information the input voltage can be calculated using the equations below Unipolar binary CODE input E DE Vmax Bipolar binary _ CODE 1 input CODE 1 2 Vmax Unipolar 2 s complement CODE 1 input CODE 4 Vmax Bipolar 2 s complement LODE 2 Vmax input 65 536 DAO 16 Users Manual 13 2 2 Digital to Analog Converters The digital to analog D A section of the DAO 16 consists o
16. ddress 0EH output 00H to base_address OEH Example Program the value 0100H into the multi function timer register output B4H to base_address 0FH output 00H to base_address OEH output 01H to base_address OEH DAQ 16 Users Manual 29 DAO 16 Users Manual Version 2 20 January 28 1999 Part No 940 0032 220
17. e Stamford CT 06907 0047 Application of Council Directive 89 336 EEC Standards to which Conformity is Declared EN50081 2 EN55022 EN60555 2 EN60555 3 EN50082 1 IEC 801 2 IEC 801 3 amp IEC 801 4 Type of Equipment Information Technology Equipment Equipment Class Light Industrial Equipment Product Name ISA Data Acquisition Card Model Number DAO 16 DAO 16 Users Manual Table of Contents 1 Introduction db ye o ASAS Fyd a yd ydd AN hy 8 ETA AO gae cg a A A DA AD AD ADAR 8 1 2 DAQ I6 Specifications uu O WYLAN aa GOR UD 9 2 Circuit Board Description and Configuration 2 1 Analog to Digital Converter tada cua Y y 10 2 2 Digital to Analog Converters ue i da 14 2 3 Digital Input Output een tenes 15 2 4 Base Address AA E E EA GAN GAD AA 16 2 5 Clock Selection A A A NY GN YU YD A 17 2 Oe internal Glock di IR RARA ARAN a a 18 PS AB Externa 0 k rotan IR A O 19 26 Trigger selechon se oeste eE Y NN GR y Gw 20 27 Direct Memory ACCESS sI e A E 21 Pe NA A A II TAE E e 22 2 01 External Inteirupb soi a misni O A 22 3 External Connections 93 4 Register Description and Programming A Aol Register Description uu GW dn YD CEFNOG 25 4 1 1 Control Word Register uaes Dr AAA aa 25 4 1 2 Start of Conversion Register A NR A AR ROGER REN 27 4 1 3 DACORegister sarees Y NW aE Re Vat WAN Y FN Y Reh ESA 27 iL DACT IRGC IG LCE ys dada dra RR WYR e wich De dre ad 27 4 1
18. ed into the input of counter 1 to produce a 32 bit timer Mode 2 must be selected for counter 0 with a minimum count of 2 This register is 8 bit read write 4 1 6 Clock Rate Register high word The high word of the clock divider is contained in counter 1 of the 8254 counter timer Mode 2 must be selected for counter 1 with a minimum count of 2 This register is 8 bit read write 4 1 7 _ Multi Function Timer Register The multi function timer is implemented using counter 2 of the 8254 counter timer Mode 2 must be selected for this timer with a minimum count of 2 This register is 8 bit read write 4 1 8 8254 Control Word Status Register This register is used to program the mode and report the status of the 8254 counter timer This register is 8 bit read write DAO 16 Users Manual 27 42 Programming the 8254 Counter Timer This section provides programming information for the 8254 counter timer as implemented on the DAO 16 For more details on the 8254 consult the Intel Micro Processor and Peripheral Handbook To program any of the counters contained in the 8254 counter timer three steps are required 1 Write the configuration byte to the 8254 mode select status register This byte sets the operating mode of the selected counter 2 Write the least significant byte of the count value to the selected counter register 3 Write the most significant byte of the count value to the selected counter register The followin
19. f two independent 12 bit multiplying D A converters and two independent two stage output amplifiers Digital data output to the D A converter by the CPU is converted to an analog voltage by the D A converter amplified by the output amplifiers and becomes output to the 62 pin connector at CN1 The D A converters used on the DAO 16 are 12 bit resolution converters Of the 16 bits written to the D A only the 12 least significant bits DO D11 are used for the conversion The 4 most significant bits D12 D15 are ignored The DAO 16 implements multiplying D A converters which makes the analog output proportional to a reference voltage applied to the D A Under normal circumstances the reference voltage should be applied from the internal 5V reference source An external reference voltage may also be supplied to the D A This input from the D 62 connector should not exceed 5 volts and has a typical input impedance of 7 5Kohms The D A reference voltage source is selected using jumper J3 as illustrated in Figure 2 4 D A channel 0 reference Internal Source gt m External Source 5 J3 1 Internal Source gt lt External Source D A channel 1 reference Figure 2 4 Jumper J3 Configuration The D A converter channels may also be operated in unipolar mode 0 to 5 volts or bipolar mode 5 to 5 volts The output mode is selected using jumper J4 as shown in Figure 2 5 In addition a ga
20. g examples illustrate the programming sequence for each of the counters in the 8254 The variable base_address is the base address of the DAQ 16 as defined by the address selection switches Counter 0 Clock rate register low word operating mode 2 minimum count value 2 configuration byte 0 0 1 1 0 1 0 0 34H Example Program the value 2675H into the low word of the clock rate register output 34H to base address OFH output 75H to base address OCH output 26H to base address OCH Example Program the value 0008H into the low word of the clock rate register output 34H to base_address 0FH output 08H to base_address OCH output 00H to base_address OCH DAO 16 Users Manual 28 Counter 1 Clock rate register high word operating mode 2 minimum count value 2 configuration byte 0 1 1 1 0 1 0 0 74H Example Program the value 13A4H into the high word of the clock rate register output 74H to base_address 0FH output A4H to base_address ODH output 13H to base_address 0DH Example Program the value FFFFH into the high word of the clock rate register output 74H to base_address 0FH output FFH to base_address 0DH output FFH to base_address 0DH Counter 2 Multi function timer register operating mode 2 minimum count value 2 configuration byte 1 0 1 1 0 1 0 0 B4H Example Program the value 000AH into the multi function timer register output B4H to base_address OFH output 0AH to base_a
21. he first sampling period will be slightly longer than the others because the first clock period is reguired to load the initial value of the multi function timer The following eguation calculates the additional time of the first period tadd 100ns N1 E N2 To minimize the amount of additional time required for the first sample select clock dividers such that N1 and N2 are as small as possible and N3 is as large as possible Using the equations above the minimum and maximum data sampling rates and the amount of additional time required for the first sample can be calculated Maximum sampling rate Minimum sampling rate N1 2 N2 2 N3 25 N1 65535 N2 65535 N3 65535 t 100 x 10 2 2 25 t 100 x 10 65535 65535 65535 t 100 x 10 100 t 100 x 10 2 815 x 10 t 10us t 28 146 x 10 sec f 10x 10 2 2 25 t 325 days 18 hours 23 minutes 29 sec f 10x10 100 f 10 x 10 65535 65535 65535 f 100 Khz f 10 x 106 2 815 x 1014 f 35 529 nHz taaa 100 x 10 9 2 2 tada 100 x 10 65535 65535 tada 100 x 10 4 tada 100 x 107 9 4 295 x 10 taaa 400 ns tada 429 5 sec 2 5 2 External Clock The external clock input to the DAQ 16 is a TTL level 0 5 volt signal This input may be used to control the sampling rate directly or it may be fed through a pre divider the multi function timer with the timer output controlling the A D sampling rate When used to
22. in selection jumper is provided to select an output gain of 1 or 2 When using an external voltage reference this gain can be used to amplify the D A output for small reference voltages WARNING When the internal voltage reference is used the D A gain MUST be set to the gain 1 position DAQ 16 Users Manual 14 5 6 7 8 OOO OO090 12 3 4 Channel 0 select gt La Channel 1 gain Channel 0 gain gt lt Channel 1 select Figure 2 5 Jumper J4 Configuration Table 2 3 lists configuration options for jumper J4 Channel 0 Channel 1 Bipolar connect 1 5 connect 3 7 Unipolar open 1 5 open 3 7 Gain 1 connect 2 6 connect 4 8 Gain 2 open 2 6 open 4 8 Table 2 3 Jumper J4 Configuration When configured for unipolar operation the output voltage can be calculated from the equation Ae Var CODE gain For bipolar operation the eguation becomes CODE Aout 2048 dE V ref gain 2 3 Digital Input Output The DAQ 16 offers four bits of digital output and four bits of digital input for control monitoring of external digital devices The four digital output lines are LS TTL compatible and will initialize low 0 volts on power up The four digital inputs are also LS TTL compatible There is no termination provided on the digital input lines and a read of an unused digital input will result in an indeterminate value DAQ 16 Users Manual 15 2 4 Base Address The
23. l bits in the DAQ 16 control word register select the trigger source and level Upon reset the trigger selection and trigger level bits default to the internal software trigger When the internal trigger is used an output to the start of conversion register will trigger the DAQ 16 to begin sampling the input For triggering off an external event the DAQ 16 accepts a level sensitive TTL compatible trigger input from the D 62 connector The trigger level bit in the DAQ 16 control word register determines which TTL level is used to trigger the A D converter to begin sampling When an internal clock source is used a delay of not more than 225ns will occur between the trigger and the first data sample When an external clock is used the delay will be dependent on the frequency and duty cycle of the clock input If these delays are unacceptable the clock and trigger circuitry can be bypassed and a start of conversion pulse can be input directly into the A D circuitry with a maximum delay of 25ns If the user controls the start of conversion pulse directly the sample will be taken on the low to high transition of the pulse the pulse must have a duration of at least 10 us and the duty cycle must be between 5 and 80 percent Jumper J1 shown in Figure 2 9 configures start of conversion control Start of Conversion indicates factory default DAO 16 controlled connect 1 2 User controlled connect 2 3 Figure 2 9 Jumper J1 Config
24. minal count is reached on the active channel DMACH indicates which of the DAO 16 s DMA channels is currently active to transfer data Logic 0 indicates DMA channel 0 logic 1 indicates DMA channel 1 LEVEL selects the edge of the external trigger input When set logic 1 A D conversions will begin on the falling edge of the external trigger input When cleared logic 0 conversions will begin on the rising edge of the external trigger IMPORTANT LEVEL must be logic 0 when internal triggering is used TRIG selects between internal and external triggers When set logic 1 the external trigger is selected CLK selects between internal and external clock sources When set logic 1 the external clock source is selected RUN when set logic 1 the A D converter is placed in the run mode and will begin converting data when a trigger is received RUN may be cleared at any time by writing a 0 to it When using DMA transfers RUN is automatically cleared when a terminal count is received with DMACT set to 0 EOC when set indicates an end of conversion has taken place and the data is available in the A D converter data register VALID when set logic 1 indicates at least one data sample was lost because it was read by the computer before the next sample was converted The data was lost because the sampling rate was too fast for the computer to acquire data VALID is reset by writing to the start conversion register CHSL2 C
25. n or used on humans Should any Product s be used in or with any nuclear installation or activity medical application used on humans or misused in any way OMEGA assumes no responsibility as set forth in our basic WARRANTY DISCLAIMER language and additionally purchaser will indemnify OMEGA and hold OMEGA harmless from any liability or damage whatsoever arising out of the use of the Product s in such a manner RETURN REOUESTS INOUIRIES Direct all warranty and repair reguests inguiries to the OMEGA Customer Service Department BEFORE RETURNING ANY PRODUCT S TO OMEGA PURCHASER MUST OBTAIN AN AUTHORIZED RETURN AR NUMBER FROM OMEGA S CUSTOMER SERVICE DEPARTMENT IN ORDER TO AVOID PROCESSING DELAYS THE ASSIGNED NUMBER SHOULD THEN BE MARKED ON THE OUISIDE OF THE RETURN PACKAGE AND ON ANY CORRESPONDENCE THE PURCHASER IS RESPONSIBLE FOR SHIPPING CHARGES FREIGHT INSURANCE AND PROPER PACKAGING TO PREVENT BREAKAGE IN TRANSIT FOR WARRANTY RETURNS please have the following information available BEFORE contacting OMEGA 1 P O Number under which the product was purchased 2 Model and serial number of the product under warranty and 3 Repair instructions and or specific problems relative to the product FOR NON WARRANTY REPAIRS consult OMEGA for current repair charges Have the following information available BEFORE contacting OMEGA 1 P O Number to cover the cost of the repair 2 Model and serial number of the product and 3 Re
26. ng time 0 5 us settling time 3 5 us The amplifier stage of the A D converter circuit performs two functions 1 amplifies low level input signals and 2 converts this input signal into a voltage range acceptable to the A D converter The amplifier circuit is controlled by jumpers J6 and J7 Table 2 1 below shows the recommended jumper settings for various input voltage ranges indicates factory settings Maximum Input Voltage Amplifier J7 A D Range J6 Unipolar Bipolar 10 10 1 3 4 10v 2 3 5 6 5 5 1 3 4 5v 1 2 4 5 2 5 2 5 1 3 4 2 5 v 2 3 4 5 1 1 10 2 4 10 v 2 3 5 6 0 5 0 5 10 2 4 5v 1 2 4 5 0 25 20 25 10 2 4 2 5v 2 3 4 5 0 1 1 100 1 3 10v 2 3 5 6 0 05 0 05 100 1 3 5v 1 2 4 5 0 025 0 025 100 1 3 2 5 v 2 3 4 5 Table 2 1 A D Converter Configurations DAQ 16 Users Manual 10 Figures 2 1 and 2 2 show the configuration options for jumpers J7 and J6 Y N O O NNS SS SS SS SS N Y N SN NS NS NS IS O O co SS RSS RSS SS ce NN O 2 5 volt range RSQ 5 volt range Figure 2 1 Jumper J7 Configuration 10 volt range Figure 2 2 Jumper J6 Configuration o o S oO E q D 6D o gt ea pleno yml 2 gn S o o Y o N Ea o
27. pair instructions relative to the product OMEGA s policy is to make running changes not model changes whenever an improvement is possible This affords our customers the latest in technology and engineering OMEGA is a registered trademark of OMEGA ENGINEERING INC O Copyright 1999 OMEGA ENGINEERING INC All rights reserved This document may not be copied photocopied reproduced translated or reduced to any electronic medium or machine readable form in whole or in part without prior written consent of OMEGA ENGINEERING INC DAO 16 Users Manual 2 OMEGAnet On line Service Internet e mail http Www omega com info omega com Servicing North America USA One Omega Drive Box 4047 E mail info omega com ISO 9001 Certified Stamford CT 06907 0047 Tel 203 359 1660 FAX 203 359 7700 Canada 976 Bergar E mail info omega com Laval Quebec H7L 5A1 Tel 514 856 6928 FAX 514 856 6886 For immediate technical or application assistance USA and Canada Sales Service 1 800 826 6342 1 800 TC OMEGA Customer Service 1 800 622 2378 1 800 622 BEST M Engineering Service 1 800 872 9436 1 800 USA WHEN M TELEX 996404 EASYLINK 62968934 CABLE OMEGA Mexico and Latin America Tel 001 800 826 6342 FAX 001 203 359 7807 En Espanol 001 203 359 7803 E mail espanol omega com Servicing Europe Benelux Postbus 8034 1180 LA Amstelveen The Netherlands Tel 31 20 6418405 Toll Free in Benelux 0800 099
28. r manufacturer instructions DAQ 16 Users Manual 8 1 2 DAO 16 Specifications Bus Interface ISA 16 bit I O Address Range 0000H FFFFH Interrupt Levels IRQ 2 3 4 5 6 7 10 11 12 14 15 DMA Levels Power Requirements 5 volts 5 volts 1069 0 mA 12 volts 374 9 mA 491 4mA I t Typical Current I ms Maximum Statisical Current DAQ 16 Users Manual 2 Circuit Board Description and Configuration The base address of the DAO 16 is selected using switches SW1 and SW2 The operating mode of the DAO 16 is controlled by jumpers J1 through J7 while DMA and interrupt selections are set with jumpers J8 through J11 Connections to external equipment are made through the high density 62 pin connector CN1 2 1 Analog to Digital Converter The analog to digital A D section of the DAO 16 accepts up to 8 differential inputs from the D 62 connector These inputs pass through a dual 8 to 1 multiplexer circuit which selects the channel to be converted The selected input is then amplified and presented to the A D converter to be digitized The digital output of the A D is latched into a buffer to be read by the computer The multiplexer circuit selects one of the 8 differential channels to be input to the A D converter The channel is software selected through the DAO 16 s control word register The typical characteristics of the multiplexer circuit are input resistance 1 5 Kohm switchi
29. uration DAQ 16 Users Manual 20 2 7 Direct Memory Access Direct Memory Access DMA transfers provide a way of transferring data from the DAO 16 s A D converter into the computer s memory without using the Central Processing Unit CPU DMA capability enables other system software to be executed while data is being input from the DAO 16 The DAO 16 actually implements two DMA channels The advantage of having two DMA channels is that one channel can be transferring data while the second channel is being programmed When the first channel is finished the second channel will automatically take over and continue the data transfer The first channel can then be re programmed while the second channel is transferring data In this way the DAO 16 can acguire data continuously until terminated by the user The DAO 16 supports 16 bit DMA transfers on channels 5 6 and 7 The DMA channel s are selected by jumpers J8 and J9 as shown in Figure 2 10 DMA Channel 1 DMA Channel 2 J8 0600000 JO 000000 000000 000000 DRQ7 gt DR07 gt DACK7 gt DACK7 gt DR06 gt DRQ gt DACK6 gt ___ DACK6 gt gt DRO5 DRO5 DACK5 DACK5 Figure 2 10 Jumpers J8 and J9 Configuration WARNING To properly implement the DMA capability the DRO and DACK of each DMA channel must be jumpered to the same number i e DRO 5 DACK 5 If both DMA
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