Omega Engineering PCI-DIO96 User's Manual
Contents
1. PINS 51 TO 100 N SIGNAL CONDITIONING OR 50 PIN SCREW TERMINAL BOARD Figure 3 2 Cable C100FF xx Configuration Port AG D 2 PortA4D 4 PottA2D 6 8 PortB6D 10 DIO PortB4D 12 DIO Group 3 Port BOD 16 Group 3 PortC6D 18 Port CAD 20 20 22 COD 24 C 26 4 C 28 Port A2C 30 DIO ort 36 Group 2 B2 C 38 DIO ort PortC6 42 Group 2 4 44 2 46 48 Ground 50 2nd of 2 50 Pin Connectors From board pins 51 to 100 1st connector is pin 1 to 1 etc DIO Groups 0 and 1 Pins 51 100 of 100 Pin Conn 99 Port Port A Port Port B U gt 75777 O00000000000000000000000000000U7UUCOCOUOUCOCOUOCOCOCOCOUOU Port B UU Port UU Port O SNOROO XO ANO v o Ei gt Port Port U o a gt Port Port 000 U Port B ARAIONOANWAUON UUUU 4444 Port UU 00 QU Port C Port C Port Port C Port C Port C Port C 5 100 GND Figure 3 3 Pin Translation Pins 51 to 100 Signals 3 3 SIGNAL CONNECTION CONSIDERATIONS All the digital inputs on the PCI DIO96 are 8255 CMOS TTL Th2. PCI BUS 5V 32 BIT 33MHZ Figure 1 1 PCI DIO96 Block Diagram 2 INSTALLATION PCI DIO96 boards completely plug and play There switches or jumpers on the board All board addresses are set by your computer s plug and play software InstaCal is the installation calibration and test software supplied with your data acquisition IO hardware Refer to the Extended Software Installation Manual to install InstaCal If you need it there is some on line help in the InstaCal program Owners of the Universal Library should read the manual and examine the example programs prior to attempting any programming tasks 3 CONNECTIONS 3 1 CABLES AND SCREW TERMINAL BOARDS The board has a 100 pin high density Robinson Nugent male connector Figure 3 1 CI100FF x cable is used to split the 100 I O lines into two 50 wire cables One connector has pins 1 to 50 the other has 51 to 100 The two I O connectors can be connected directly to two screw terminal boards such as the 50 CIO TERM100 5 50 or SCB 50 See Figures 3 2 and 3 3 for configuration and pin out 3 2 CONNECTOR DIAGRAM The PCI DIO96 I O connector is a 100 pin type connector accessible from the rear of the PC at the expansion backplate See Figure 3 1 below for the board pin out PotA7B 116 Port A7 D PotA6B 2 e Port A6 D PotA5B 3 e Port A5 D PotA4B 4 Port A4 D PotA3B 5 PotA2B
3. This register is used to configure the Group 0 ports as either input or output and configures the operating mode to mode 0 1 or 2 The following describes configuration for mode 0 See the Intel or Harris 8255 data sheets for information on other modes of operation 8255 MODE 0 CONFIGURATION 1 Output Ports In mode 0 configuration 82C55 ports can be configured as outputs holding the data written to them For example to set all three ports A B amp C of Group 0 to output mode write the value 80 hex to BADR3 3 refer to Table 5 3 below The user is then able to read the current state of the output port by simply reading the address corresponding to that port 2 Input Ports In mode 0 configuration the 82C55 ports can be configured as inputs reading the state of the inputs lines For example to set all of the ports of Group 0 to the input mode write the value 9B hex to BADR3 3 12 Table 5 3 DIO Port Configurations Per Group Programming Codes Values D4 D3 D1 DO Hex Dec A B CU CL 0 0 0 0 80 128 OUT OUT OUT OUT 0 0 0 1 81 129 OUT OUT OUT IN 0 0 1 0 82 130 OUT IN OUT OUT 0 0 1 1 83 131 OUT IN OUT IN 0 1 0 0 88 136 OUT OUT IN OUT 0 1 0 1 89 137 OUT OUT IN IN 0 1 1 0 8 138 OUT IN IN OUT 0 1 1 1 8 139 OUT IN IN IN 1 0 0 0 90 144 IN OUT OUT OUT 1 0 0 1 91 145 IN OUT OUT IN 1 0 1 0 92 146
4. 5 Group Port B Data Group Port B Data BADR3 6 Group Port C Data Group Port C Data BADR3 7 Group Configure Group 1 Configure BADR3 8 Group 2 Port A Data Group 2 Port A Data BADR3 9 Group 2 Port B Data Group 2 Port B Data BADR3 A Group 2 Port C Data Group 2 Port C Data BADR3 B Group 2 Configure Group 2 Configure BADR3 C Group 3 Port A Data Group 3 Port A Data BADR3 D Group 3 Port B Data Group 3 Port B Data BADR3 E Group 3 Port C Data Group 3 Port C Data BADR3 Group 3 Configure Group 3 Configure BADR3 10h Counter Counter BADR3 11h Counter 2 Counter 2 BADR3 12h N A N A BADR3 13h Counter Configuration Counter Configure BADR3 14h Interrupt Control 1 Interrupt Control 1 BADR3 15h Interrupt Control 2 Interrupt Control 2 The 82C55 may be programmed to operate in Input Ouput mode 0 Strobed Input Ouput mode 1 or Bi Directional Bus mode 2 The following information describes mode 0 operation Users needing information regarding other modes of operation should refer to an Intel or Intersil 82C55 data sheet Upon power up an 82C55 is reset and defaults to the input mode No further programming is needed to use the 24 lines of an 82C55 as TTL inputs 5 4 1 Group 0 8255 Configuration amp Data GROUP 0 PORT A DATA BADR3 0 READ WRITE GROUP 0 PORT DATA BADR3 1 READ WRITE GROUP 0 PORT C DATA BADR3 2 READ WRITE GROUP 0 CONFIGURE BADR3 3 READ WRITE
5. 6 Port A2 D PotA1B 7 Port A1 D PotA0B 8 Port AO D PortB7B 9 Port B7 D PortB6B 10 e Port B6 D PotB5B 11 e Port 5 D 12 e PortB4D DIO DIO PortB3B 13 e Port B3 D Group 3 Group 1 Port B2B 14 e Port B2 D PotB1B 15 e Port B1 D 16 e Port BO D PotC7B 17 e Port C7 D PotC6B 18 ee Port C6 D PotC5B 19 ee Port C5 D PortC4B 20 Port C4 D PotC3B21 ee Port C3 D PortC2B 22 ee Port C2 D PortC1B 23 ee Port C1 D LPort COB 24 e e Port CO D Port A7 A 25 e e Port A7 C 26 e e Port A6 C PortA5A 27 Port A5 C PotA4A28 ee Port A4 C PotA3A29 ee Port A3 C PotA2A30 ee Port A2 C PortA1A 311606 Port A1 C Port A0 A 32 Port A0 C Port B7 A 33 e Port B7 C PotB6A 34 e Port B6 C 5 35 e Port B5 C nu o PotB4A 36 e Port B4 DIO 37 Port B3 Group 2 2 38 e 2 PortB1A 39 Port B1 40 e Port BO 41 e Port C7 Port C6A 42 e Port C6 C PortC5A 43 e Port C5 C 44 e Port C4 45 e Port C3 C Port C2A 46 e Port C2 C PortC1A 47 e Port C1 LPortCOA 48 e Port CO C 5V 49 e 5V GND 50 e GND Figure 3 1 PCI DIO96 100 Pin Connector Pin Out 100 PIN I O CABLE PAM S C100FF xx CONNECTOR PINS 1 TO 50 SIGNAL NET CONDITIONING or 50 PIN SCREW TERMINAL BOARD
6. IN IN OUT OUT 1 0 1 1 93 147 IN IN OUT IN 1 1 0 0 98 152 IN OUT IN OUT 1 1 0 1 99 153 IN OUT IN IN 1 1 1 0 9 154 IN IN IN OUT 1 1 1 1 9B 155 IN IN IN IN Notes CU is PORT C upper nibble CL is PORT C lower nibble 5 4 2 Group 1 8255 Configuration amp Data GROUP 1 PORT A DATA BADR3 4 READ WRITE GROUP 1 PORT B DATA BADR3 5 READ WRITE GROUP 1 PORT C DATA BADR3 6 READ WRITE GROUP 1 CONFIGURE BADR3 7 READ WRITE 5 4 3 Group 2 8255 Configuration amp Data GROUP 2 PORT A DATA BADR3 8 READ WRITE GROUP 2 PORT B DATA BADR3 9 READ WRITE GROUP 2 PORT C DATA BADR3 A hex READ WRITE GROUP 2 CONFIGURE BADR3 B hex READ WRITE 5 4 44 Group 3 8255 Configuration amp Data GROUP 3 PORT A DATA BADR3 C hex READ WRITE eS Co m ps 14 GROUP 3 PORT DATA BADR3 D hex READ WRITE GROUP 3 PORT C DATA BADR3 E hex READ WRITE GROUP 3 CONFIGURE BADR3 F hex READ WRITE 5 4 5 8254 Configuration amp Data COUNTER 1 DATA BADR3 10 hex READ WRITE E o a 9 or 82 54 counters 1 2 have been configured in hardware to produce 32 bit counter for use in interrupt generation This register provides access to the lower
7. configuration is shown in Figure 3 4 below The 24 bits of digital I O on PCI DIO96 connector pins 1 24 base address 0 through 3 control the first relay board The 24 bits on pins 25 50 will control the second relay SSR board on the daisy chain and so on up to 100 pins C100FF X Cable N CIO ERB24 OUT IN CIO ERB24 S SSR RACK24 or SSR RACK24 IN CIO ERB24 OUT IN CIO ERB24 our 5 SSR RACK24 or SSR RACK24 Figure 3 4 Relay Rack Cabling 4 SOFTWARE We highly recommend that users take advantage of our Universal Library package s easy to use programming interfaces However if you are an experienced programmer and wish to read and write directly to the board we have provided a detailed register map in the next chapter 4 1 UNIVERSAL LIBRARY The Universal Library provides complete access to the PCI DIO96 functions from a range of programming languages If you are planning to write programs or would like to run the example programs for Visual Basic or any other language please turn now to the Universal Library manual 4 2 PACKAGED APPLICATION PROGRAMS Most packaged application programs such as SoftWIRE DAS Wizard and HP VEE have drivers for the PCI DIO96 If the package you own does not appear to have drivers for the boards please fax or e mail the package name and the revision number from the install disks We will research the package f
8. 16 data bits Since the interface to the 82C54 is only 8 bits wide write counter data in two bytes low byte first followed by the high byte COUNTER 2 DATA BADR3 11 hex READ WRITE The 82C54 counters 1 and 2 have been configured in hardware to produce 32 bit counter for use in interrupt generation This register provides access to the upper 16 data bits Since the interface to the 82C54 is only 8 bits wide write counter data in two bytes low byte first followed by the high byte 15 COUNTER CONFIGURATION BADR3 13 hex READ WRITE This register is used to set the operating modes of each of the 82C54 s counters Configure the counters by writing mode information to the Configure register followed by the count information written to the specific counter data registers Refer to the Celeritous 82C54 data sheets for more detailed information 5 4 6 8255 Interrupt Source Configure BADR3 14 hex DIRQ1 When this bit is set the 8255 in Group 3 will generate an interrupt on INTRB if INTEN in BASE 15 hex is also set DIRQO When this bit is set the 8255 in Group 3 will generate an interrupt on INTRA if INTEN in BASE 15 hex is also set When this bit is set the 8255 in Group 2 will generate an interrupt on INTRB if INTEN in BASE 15 hex is also set CIRQO When this bit is set the 8255 in Group 2 will generate an interrupt INTRA if INTEN in BASE 15 hex is also set When thi
9. ORS 20 7 2 TIL TO SOLID STATE RELAYS 21 7 3 VOLTAGE DIVIDERS This page is blank 1 INTRODUCTION PCI DIO96 is 96 bit line digital I O board The board provides the 96 bits in four 24 bit groups Each group provides an 8 bit port A and port B as well as an 8 bit port C that can be split into independent 4 bit port C HI and a 4 bit port C LO See Figure 1 1 below On power up and reset all I O bits are set to input mode If you are using the board to control items that must be OFF on reset you will need to install pull down resistors Provisions have been made on the board to allow users to quickly and easily install SIP resistor networks in either pull up or pull down configurations DIO Group 3 7 0 lt gt Port A 7 0 lt Port B Control 7 0 3 Port C 82 55 PCI DIO96 Block Diagram DIO Group 7 0 lt gt Port A 7 0 lt PortB 7 0 lt Port C 82655 CONTROLLER FPGA and LOGIC DIO Group 1 7 0 lt gt Port A CONTROL BUS Control 7 0 lt gt Port B Registers oim me 7 0 lt Port COUNTERS 82C55 82C54 Decode Status DIO Group 0 7 0 lt gt Port A 5 7 0 lt gt PortB 2 7 0 lt gt Port 82055 Boot PCI EEPROM CONTROLLER BADR3 PLX 9052
10. PCI DIO96 DIGITAL INPUT OUTPUT User s Manual Revision 2 November 2000 TABLE OF CONTENTS 1 INTRODUCTION 1 2 INSTALLATION a nee iced poe Ante 2 3 O CONNECTIONS ERAN RR RES 2 3 1 CABLES AND SCREW TERMINAL BOARDS 2 3 2 CONNECTOR DIAGRAM 3 3 3 SIGNAL CONNECTION CONSIDERATIONS 6 3 4 24 amp SSR RACK24 CONNECTIONS 7 ZSOPRIWARE e ooo P ERO estu quce ees 8 4 1 UNIVERSAL LIBRARY 8 4 2 PACKAGED APPLICATION PROGRAMS 8 5 REGIS FER MAPS een UG oe o etate dt 9 Delt BADR 9 BADR D a ee et TH M 9 5 2 1 INTCSR Configure Los cesis ente TES 9 SO BAR 10 eec vivat t Dit 11 5 4 1 Group 0 8255 Configuration amp Data 11 5 4 2 Group 1 8255 Configuration amp Data 13 5 4 3 Group 2 8255 Configuration amp Data 14 5 4 4 Group 3 8255 Configuration amp Data 14 5 4 5 8254 Configuration amp Data 15 5 4 6 8255 Interrupt Source Configure 16 5 4 7 Counter Interrupt Source Configure 17 6 SPECIFICATIONS 18 7 ELECTRONICS AND INTERFACING 20 7 1 PULL UP amp PULL DOWN RESIST
11. any variation in the voltage drop for the circuit as a whole will have a proportional variation in all the voltage drops in the circuit In a voltage divider the voltage 1 vi across one of the resistors in a circuit is proportional to voltage across the total resistance Signal 4 Input 2 Volt in the circuit Figure 7 2 v2 des Est R2 Vout When designing a voltage divider choose two resistors with Signal gt proper proportions relative to the SIMPLE VOLTAGE DIVIDER Vin R1 R2 full scale of the digital input and Vout R2 the maximum signal voltage The formula for voltage attenuation is Figure 7 2 Voltage Divider The variable Attenuation is the Attenuation 1 2 proportional difference between the R2 signal voltage max and the full scale of the analog input For example if the signal varies 2 10K 10K between 0 and 10 volts and you wish to 10K measure that with a PCI DIO96 board 22 with a full scale range of 0 to 5 volts the Attenuation is 2 1 or just 2 For a given attenuation pick a handy R1 A 1 R2 resistor and call it R2 then use this formula to calculate R1 Digital inputs can readily use voltage dividers For example if you wish to measure a digital signal that is at 0 volts when off and 24 volts when on you cannot connect that directly to the PCI DIO96 digital inputs The voltage must be dro
12. ctromagnetic field requirements for industrial process measurements and control equipment IEC 801 4 Electrically fast transients for industrial process measurement and control equipment Carl Haapaoja Director of Quality Assurance OMEGA Engineering Inc One OMEGA Drive Stamford CT 06801 800 872 9436 Fax 203 359 7700 E mail info omega com www omega com
13. e PCI DIO96 output signals are 8255 CMOS OMEGA Engineering Inc offers a wide variety of digital signal conditioning products that provide an ideal interface between high voltage and or high current signals and the PCI DIO96 If you need control or monitor non TTL level signals with your board please refer to our catalog or our web site for the following products CIO ERB series electromechanical relay output boards CIO SERB series 10A electromechanical relay output boards SSR RACK series solid state relay I O module racks A description of digital interfacing is in the Interface Electronics section IMPORTANT NOTE The 82 55 digital I O chip initializes all ports as inputs power up and reset A TTL input is a high impedance input If you connect another TTL input device to the 82C55 it could be turned ON or OFF every time the 82C55 is reset Remember the 82 55 is reset to the INPUT mode There are positions for pull up and pull down resistor packs on your PCI DIO96 board To implement these please refer to section 7 1 3 4 24 amp SSR RACK24 CONNECTIONS PCI DIO96 boards provide digital I O in two major groups of 48 bits each 96 total but each side of the C100FF xx cable provides 48 bits However many popular relay and SSR boards provide only 24 bits of I O The CIO ERB24 and SSR RACK24 each implements a connector scheme where all 96 bits of the PCI DIO96 board may be used to control relays and or SSRs This
14. itched on whenever the computer is powered on or reset To prevent unwanted switching and to drive all outputs to a known state after power on or reset pull all pins either high or low through a 2 2 K resistor 7 1 PULL UP amp PULL DOWN RESISTORS Whenever the board is powered on or reset the control register is set to a known state That state is all ports go to the input state The nature of the input means it will typically float high However depending on the drive requirements of the device you are driving they may float up or down Which way they float is dependent on the characteristics of the circuit and the electrical environment and may be unpredictable This is why it often appears that the board outputs have gone high after power up The result is that the controlled device gets turned on That is why you need pull up down resistors Shown in Figure 7 1 is 82C55 digital 82655 output with a pull up resistor attached 2 2K AQ The pull up resistor provides a reference Controlled to 5V The value of 2 2K ohms requires Device only 2 3 mA of drive current If the board is reset and enters high impedance input the line is pulled high At that point both the board AND the device being controlled will sense a high signal Figure 7 1 Pull up Resistor 20 If the board is in output mode the board has enough power to override the pull up down resistor s high signal and drive the line to 0 volts If the
15. nstalled Dual footprint allows pull up or pull down configuration Counter Section Counter type Configuration Counter 1 Counter 2 Counter 3 Nor used 18 Interrupts The interrupt control registers function with the four 82C55 devices and the 82C54 counter timer to provide interrupt sources Interrupt sources 1 82C55 in Mode 1 or Mode 2 Interrupt configuration First Port CO First Port C3 Second Port CO Second Port C3 Third Port CO Third Port C3 Fourth Port CO Fourth Port C3 Note Any interrupt source above can be individually enabled 2 82C54 Counter e Counter 1 OUT e Counter 2 OUT Note Counters 1 and 2 interrupts are exclusive Only one counter can be enabled as an interrupt source at any given time Crystal Oscillator Environmental Operating temperature range 0 to 70 C Storage temperature range 40 to 70 C 0 to 95 non condensing Mechanical PCI short card 136 0mm L x 100 6mm W x11 00mm H 7 ELECTRONICS AND INTERFACING This brief introduction to the electronics most often needed by digital I O board users covers a few key concepts IMPORTANT NOTE WHENEVER AN 82C55 IS POWERED ON OR RESET ALL PINS ARE SET TO HIGH IMPEDANCE INPUT FOLLOWING STANDARD TTL FUNCTIONALITY THESE INPUTS WILL TYPICALLY FLOAT HIGH AND MAY HAVE ENOUGH DRIVE CURRENT TO TURN ON EXTERNAL DEVICES The implications of this is that if you have output devices such as solid state relays they may be sw
16. o tie input lines and unconnected lines will not affect the performance of connected lines Just make sure that you mask out any unconnected bits in software 7 2 TTL TO SOLID STATE RELAYS Many applications require digital outputs to switch AC and DC voltage motors on and off or to monitor AC and DC voltages These AC and high DC voltages cannot be controlled or read directly by the TTL digital lines of a PCI DIO96 Solid State Relays such as those available from OMEGA Engineering Inc allow control and monitoring of AC and high DC voltages and provide up to 4000VAC isolation Solid State Relays SSRs are the recommended method of interfacing to AC and high DC signals 21 The most convenient way to use solid state relays and a PCI DIO96 board is to use a Solid State Relay Rack An SSR Rack is a circuit board with input buffer amplifiers that are powerful enough to switch the SSRs The buffer amplifiers and SSRs are socketed The standard buffer amplifiers are inverting types meaning that a low input from a DIO 82C55 outputs a high to the SSR which turns it on closes the SSR output If desired non inverting amplifiers can be specified 7 3 VOLTAGE DIVIDERS If you wish to measure a signal that varies over a range greater than the input range of a digital input use a voltage divider to drop the voltage of the input signal to the level the digital input can measure Ohm s law states Voltage Current Resistance Thus
17. or you and advise how to utilize the PCI DIO96 boards with the driver available Some application drivers are included with the Universal Library package but not with the application package If you have purchased an application package directly from the software vendor you may need to purchase our Universal Library and drivers Please contact us for more information on this topic 5 REGISTER MAPS The PCI Controller a PLX 9052 has four configuration control and status registers Table 5 1 They are described in the following section Table 5 1 I O Region Register Operations Region Function Operations BADRO PCI memory mapped configuration 32 bit double word registers BADRI PCI I O mapped config registers 32 bit double word BADR2 N A N A BADR3 Digital I O registers 8 bit byte 5 1 BADRO BADRO is reserved for the PLX 9052 configuration registers There is no reason to access this region of I O space 5 2 BADRI BADR is a 32 bit register for control and configuration of interrupts 5 21 INTCSR Configure BADRI 4C hex 32 15 14 13 12 11 10 9 8 X X X ISAMD X INTCLR X LEVEL EDGE READ WRITE 7 6 5 4 3 2 1 0 X PCINT X X X INT INTPOL INTE Note For applications requiring edge triggered interrupts LEVEL EDGE bit 8 1 the user must configure the INTPOL bit for active high polarity bit 1 1 The INTCSR Interrupt Con
18. output circuit asserts a high signal the pull up resistor guaranties that the line goes to 5 V Of course a pull down resistor accomplishes the same task except that the line is pulled low when the board is reset The board has enough power to drive the line high The PCI DIO96 series boards are equipped with positions for pull up down resistors Single Inline Packages SIPs The positions marked PORT A B and C are located adjacent to the I O connectors A 2 2K 8 resistor SIP is made of eight 2 2K resistors all connected with one side to a single common point the other side of each to a pin protruding from the SIP The common line to which all resistors are connected also protrudes from the SIP The common line is marked with a dot and is at one end of the SIP The SIP may be installed as pull up or pull down At each location PORT A B amp C on the PCI DIO96 series boards there are 10 holes in a line One end of the line is 5V the other end is GND They are marked HI and LO respectively The eight holes in the middle are connected to the eight lines of a port 1 through 4 A B or C A resistor value of 2 2K is recommended Use other values only if you have calculated the necessity of doing so UNCONNECTED INPUTS FLOAT Keep in mind that unconnected inputs float typically but not reliably high If you are using the PCI DIO96 board for input and have unconnected inputs ignore the data from those lines You do not have t
19. pped to 5 volts max when on The Attenuation is 24 5 or 4 8 Use the equation above to find an appropriate if R2 is IK Remember that a TTL input is on when the input voltage is greater than 2 5 volts IMPORTANT NOTE The resistors R1 and R2 are going to dissipate all the power in the divider circuit according to the equation Current Voltage Resistance The higher the value of the resistance RI R2 the less power dissipated by the divider circuit Here is a simple rule For attenuation of 5 1 or less no resistor should be 10K For attenuation of greater than 5 1 no resistor should be 1K 23 For Your Notes 24 For Your Notes 25 For Your Notes 26 EC Declaration of Conformity PCI DIO96 Digital I O board Part Number Description to which this declaration relates meets the essential requirements is in conformity with and CE marking has been applied according to the relevant EC Directives listed below using the relevant section of the following EC standards and other normative documents EU EMC Directive 89 336 EEC Essential requirements relating to electromagnetic compatibility EU 55022 Class B Limits and methods of measurements of radio interference characteristics of information technology equipment EN 50082 1 EC generic immunity requirements IEC 801 2 Electrostatic discharge requirements for industrial process measurement and control equipment 801 3 ele
20. s bit is set the 8255 in Group 1 will generate an interrupt on INTRB if INTEN in BASE 15 hex is also set BIRQO When this bit is set the 8255 in Group 1 will generate an interrupt on INTRA if INTEN in BASE 15 hex is also set When this bit is set the 8255 in Group 0 will generate an interrupt on INTRB if INTEN in BASE 15 hex is also set AIRQO When this bit is set the 8255 in Group 0 will generate an interrupt on INTRA if INTEN in BASE 15 hex is also set 16 5 47 Counter Interrupt Source Configure BADR3 15 hex READ WRITE ee Enables or disabled interrupts 1 enabled 0 disabled CTRIR Enables or disables the counters as an interrupt source 1 counters may generate interrupts 0 counters cannot generate interrupts CTRI Controls whether counter 2 is the interrupt source or counter 1 is the interrupt source When 1 is set to 1 the interrupt source is counter 2 and counter 1 acts as prescaler for counter 2 When is set to 0 the interrupt source is counter 1 Counter 3 is not used 17 6 SPECIFICATIONS Power Consumption 5V Digital Input Output Digital Type Four 82C55 Number of I O 62 Configuration 82655 e 2banks of 8 and 2 banks of 4 or e 3banks of 8 or 2 banks of 8 with handshake Output High 3 0 volts min 2 5mA Output Low Input High Input Low Power up reset state Pull Up Pull Down Resistors User i
21. trol Status Register controls the interrupt features of the PL X 9052 controller As with all of the PLX 9052 registers it is 32 bits in length Since the rest of the register have specific control functions those bits must be masked off in order to access the specific interrupt control functions listed below INTE Interrupt enable local 0 disabled 1 enabled default INTPOL Interrupt polarity 0 active low default 1 active high INT Interrupt status 0 interrupt not active 1 interrupt active PCINT PCI interrupt enable 0 disabled default 1 enabled LEVEL EDGE Interrupt trigger control 0 level triggered mode default 1 edge triggered mode INTCLR Interrupt clear edge triggered mode only 0 N A 1 clear interrupt ISAMD ISA mode enable control must be set to 1 0 2 ISA mode disabled 1 ISA mode enabled default 5 3 BADR2 2 is not used 10 5 4 BADR3 BADR3 is 8 bit data bus for reading writing and control of the individual 82655 chips and the 82C54 Refer to Table 5 2 for register offsets Table 5 2 BADR3 Registers REGISTER READ FUNCTION WRITE FUNCTION BADR3 0 Group 0 Port A Data Group 0 Port A Data BADR3 1 Group 0 Port B Data Group 0 Port B Data BADR3 2 Group 0 Port C Data Group 0 Port Data BADR3 3 Group 0 Configure Group 0 Configure BADR3 4 Group Port A Data Group Port A Data BADR3
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