Home

NXP Semiconductors ISP1562 User's Manual

1. 8L JO vL 33V DVAUX oU JP1 2UXgi M21PG221SN1 DVAUX DS gy Rai iis Y MS 1 LIL HEADER 3 FB 10 1 I 3300 E Gir C48 cio Jo C25 C70 C67 All capacitors should be 0 1 uF inF 94 uF 1nF o uF 470pF 47 uF 6 3 V AVAUX placed as close as possible DVAUX BLM18PG121SN1 to the corresponding ferrite Should be placed Should be placed nana as close as as close as 3 3V DV AV FB6 E ES possible to pin 95 possible to pin 67 C20 C21 C22 ces C28 C24 To AUX AUX C26 C50 c71 DV DVAUX vin 0 1 uF T 1 nF AN 47 uF 6 3 V AUX i 0 1 uF 0 1 uF 0 1 uF 47 pF alela DVAUX Lcos R28 asee Aal SENS T 0 1 uF 51 kQ I f pep ER SELM 121 4 89 SES 290000 SX XXX R29 R30 hs SL 12 o KK 665 8Booooo LIT 2335 51ko 51 kQ s s m dd BEE BSSS8S 200 2355 gt 4 09 ADO 82 Apo EOS 2222 AMB 93 o AMBi ADi 8i gt 7 99 AMB2 91 n ADI BII api gt gt L200 AMB2 R36 R37 AD2 80 AMB3 59 AD 2 AMBS es 02 Joo UZA 3 3 V AD 78 AD n 64 1 8 AD 77 ADIS GRN1 5 O GRN1 WA A0 vcc e Abs 75 ADIG GRN2 50 O GRN2 ADS 71 AD yi GANG L610 GRN Ai NC WP ADI 69 apo ADi0 68 OC N 4 96 OOl oc1 3 8 ADI 66 ABO 002 405 OC2 OC2 A3 SCL ADI 65 ADH2 OC3 N le 112 OC3f 5 ocas DVAUx ADi 2 ADHS OCA N e 14 OC4 Ocas 4 5 1 1 ADI4 6 AD 14 iw GND SDA C27 AD15 60 ADH5 PWE1 NLL SZ PWEI pwery I Im AD16 7 106 PWE2 0 1 uF AD 16 PWE2 N 106 PWE2R PWE2 o AT24C01A 2 7 ji R25 R26 PA
2. STOP DEVSEL gt DEVSEL TRDY gt TRDY IRDY gt IRDY FRAME gt FRAME IDSEL 8 GNT REO fp 2 REQ gt REQ 4 INTA INTA gt INTA U1 9 Z9S LdSI Buisn 13 depe Od 1S04 gsn peeds iH e Buiufiseg OSOOLNV SJ0jonpuoolul9S dXN v 0S001NV 9jou uoneorddy Z00c 19qui9AON 70 Ady Bi 12V TRST Al B2 TCK 42v LE Be OMe TS 7M EY TDI B5 45V 45V AS INTA INTA B6 45V INTA le Er 2 INTA Be NIB INTC As Be INTD 5V e 3 Bio PRSNT 1 RESERVED a5q 3 gano B11 RESERVED VIO tar PRSNT2 RESERVED 3 3 VAUX Bia 3V3 AUX A14 B15 RESERVED mer A15 RST PCICLK B15 Gnd RST gt RST PCICLK POEIK D Bl6 CLK Vio AE basis 9 GNT GNT REQ GND GNT gt GNT REQH REQ 9 Bis GND GND A18 PME PER AD31 Bap VIO PME M S AD30 PME AD29 Bo AD31 AD30 AP Boo AD29 3V3 A22 AD28 AD27 1 Be3 GND AD28 A33 AD26 AD25 B24 AD27 AD26 rer B25 AD25 GND A25 AD24 casa 9 C BES Bo6 SS AD24 A26 IDSEL C BES 4 SESS BSS e C BES IDSEL 257 3 gt IDSEL Bog AD23 avs iSe IDSEL MWA AD21 T_B29_ GND AD22 A
3. 77 3 3 V 9 29S LdSI Duisn 1e1depe 5d 1S04 ASN peeds iH e Durubiseg OSOOLNV SJOJONPUOSIWIS dXN 1007 42qQUIAAON L t0 9H ajou uoneoriddy 8LJ0 9I v 0S001NV pamasa siuBu Iv 2002 N 8 dXN O Vv DVAUX R13 ESD1 560 Q zs n R3 R4 WA DI 5 2 R 10 kQ li kQ u3 A LED a i PWE1 PWE1 4 Eng OUTB E E Val IP 4220CZ6 R1 5V Standby oci 4 OC 4 3 _ FLGB S Lo T0 ko GND S C4 i055 L0 D DM py 0 1 uF C3 45 VBUS FB1 TT1 0 1 uF 48220 uF 10 V T1 nF 3 EA IS uF BLM41PG600SN1 tlen d DPI ppt Oc2 Totu R2 2 IN 5 ober ow T ndi C38 C42 2 C54 FB2 6 SHIELD R17 R18 PWE2 10 kQ 8 C37 TT2 fea a SHIELD PWE2 gt ENA OUTA 0 01 uF 47 uF 10 V 1nF 22uF 10V 1 DOCS 15 kQ 15 kQ MIC2526 E 8 BLM18PG121SN1 Dent ESD2 R5 R7 S H1 H1 4 3 m 10 kQ 10 kQ 45V 5 2 E HA R14 1 IP 4220CZ6 DvAUX 560 Q I VBUS m C7 ZiC56 044 D DM2 Do 0 1 yF 220 uF
4. 10 V T1 nF DP2 5 VBUS laden P T DP2 SHIELD FB3 HIELD R19 R20 139 l C5 E l C59 lI C40 Los C60 o ems 15kQ 15kQ 47 uF 10V T7 0 1 100 pF 47 uF 10V 1aF T T m T u I p T iti Te m 100 pF eration USB i Vv DVAUX R15 ESD3 5600 is E R6 R8 X D3 5 2 10kQ 10kQ y2 WA LED a PWES PWES I 4 ENB amp ouTBL H veus T OC3 OC3 lt ia od FLGB 7 Cii C57 C61 D DM3 gt DM3 3 qu Loto 0 1 WF 48220 hE 10V 771 nF O49 uF Rio 6 Teak 4 up D DPS DP3 n GND OC4 lt OC4 Ze 2 FLGB m FB4 FEM SHIELD R2 R22 PWE4 TO ko 1 8 SHIELD PWE4 t gt ENA OUTBI Hrm CONS 15 kQ 15kQ MIC2526 e BLM18PG121SN1 CON ESD4 R12 Rii VS m a 3 mm 10 kQ 10 kQ 5 2 E 6 1 H R16 1 IP 4220CZ6 DvAUX 5600 I VBUS AT C12 a C58 062 D 10M Dm4 l uF fI 220uF 10V T1 nF DP4 balan far Pes Optional FB5 amp SHIELD R23 R24 ptional FB8 aga 15kQ 15kQ J1 BLM31PG121SN1 5 V_Standby Bracket holes IBLM18PG121SN1 Nene gt rh m SB2 m h 2 os Locs ices swi sw2 33 E T uF T 0 1 nF 100 uF 10V SOCKET SOCKET FB9 BLM31PG121SN1 Fig 8 ISP1563 eval board schematic port power control and ESD protection 9 c9S LdSI Duisn saydepe 5d 1504 gsn peeds iH e Durubiseg OSOOLNV SIOJONPUOSIWIIS dXN NXP Semiconductors AN10050 Designing a Hi Speed USB host PCI adapter using ISP1562 63 6 Legal information 6 1 Definitions Draft The document is a draft version only The content is still under internal review and subj
5. 5 V power supply Therefore PCI Vaux is not useful in the case of a standard PCI add on card implementation for a system wake up from S3coid It is however a very useful feature for onboard and mobile application designs because it allows additional considerable power savings and also wakes up the system by using a USB device The system wake up from S394 generated from a USB device for example USB mouse or USB keyboard connected to the ISP1562 3 host controller must be supported in system s BIOS hardware a continuous 45 V must be supplied to Vaus and operating system drivers To be able to test the remote wake up especially from those power management states in which the 5 V power source on PCI is not present for example S301 a special connector J1 is added for an external 45 V source Any external independent power NXP B V 2007 All rights reserved Application note Rev 04 1 November 2007 4 of 18 NXP Semiconductors AN1 0050 AN10050 4 Designing a Hi Speed USB host PCI adapter using ISP1562 63 supply that provides 5 V 5 96 9 2 A stabilized can be used For example a standard hub power supply Note the distribution of pull up resistors in the recommended schematics For example to achieve correct functionality it is recommended that you connect the pull up resistors placed on the PWEn N and OCn_N input signals of the power switch for example MIC2026 to DVayx NET maintaining a good condition
6. 2 G AN10050 BUS Designing a Hi Speed USB host PCI adapter using the ISP1562 ISP1563 Rev 04 1 November 2007 Application note Document information Info Content Keywords isp1562 isp1563 usb universal serial bus host pci adapter Abstract This document contains a description of the ISP1562 3 application schematics and the PCB design recommendations founded by Philips NXP Semiconductors AN1 0050 Designing a Hi Speed USB host PCI adapter using ISP1562 63 Revision history Rev Date Description 04 20071101 Fourth revision Corrected typo in Section 4 it is 2 5 inches 0 1 inch not 1 inch Last line of Section 3 4 03 20061212 Third revision Updated Fig 6 02 20060707 Second revision Updated Section 5 01 20051004 First release Contact information For additional information please visit http Avww nxp com For sales office addresses please send an email to salesaddresses nxp com AN10050 4 NXP B V 2007 All rights reserved Application note Rev 04 1 November 2007 2 of 18 NXP Semiconductors AN1 0050 Designing a Hi Speed USB host PCI adapter using ISP1562 63 1 Introduction The ISP1562 and the ISP1563 are Hi Speed Universal Serial Bus USB host controllers HCs that can be directly connected to a standard 32 bit 33 MHz PCI bus For the rest of this document they will be known as ISP1562 3 The ISP1562 3 complies with PCI
7. 3 3 V dedicated power source which is present on the PCI connector pin A14 even when PCI Vcc 3 3 V is off This enables the ISP1562 3 PME signal to be asserted and activates the wake up logic of the motherboard even if the rest of the system is powered down for example in S3 gg system standby mode This is applicable mainly to onboard desktop or mobile designs but not applicable to PCI add on cards because the PCI 5 V used for Vgus is also off during S3cod The ISP1562 3 may use PCI Vaux to power its four internal transceivers connected to the ISP1562 3 VppA aux analog and also the clock circuitry port router root hub and Power Management Event PME logic connected to the ISP1562 3 Vccyo Aux digital For details on implementation of the PCB design see Section 4 The power management capabilities enabled by using PCI Vaux allow system designers to meet the governmental energy regulations that are becoming increasingly essential worldwide Energy Star USA 30 W standby White Swan Europe 5 W standby Blue Angel Europe 5 W standby This document provides a description of the application schematics and the PCB design recommendations 2 ISP1562 3 initialization The following sequence is required during the ISP 1562 3 initialization for correct functionality 1 Register HcRhDescriptorA 902h This means that bit PSM 1b 2 Register HcControl 680h This means that bits HCFS 1 0 10b operational mode
8. AN10050 4 NXP B V 2007 All rights reserved Application note Rev 04 1 November 2007 3 of 18 NXP Semiconductors AN1 0050 Designing a Hi Speed USB host PCI adapter using ISP1562 63 3 Register HcRhStatus 18000h This implies that bit LPSC 1b port powered Microsoft Windows 2000 Windows XP and Linux drivers normally use this sequence The order of the steps may however be reversed in Windows CE default drivers so changes are required for normal functionality 3 Description of the application schematics AN10050 4 3 1 The schematics see Section 5 contain a complete implementation of the ISP1562 3 and allow testing of all its features in different types of design PCI add on card onboard design in standard desktop or mobile solution In the case of a standard PCI add on card design some simplifications to the schematics can be done as described here Some features will not be normally used in a standard PCI add on card For example The legacy support wake up from S3 no external 5 V input for Vsus and the alternative 48 MHz clock input All these alternatives however are included in the schematics and are described in this document Distribution of power sources and power management support As shown in the schematics see Section 5 a simple solution by using one jumper JP1 may be adopted to choose between PCI Vcc 3 3 V or PCI Vaux 3 3 V as the main power source for the ISP1562 3 Power
9. Ad ajou uoneorddy 8L JO CL Y 0S00INV penesei siuBu Iy 2002 N 8 dXN GO abr DVAUX R20 ESD1 560 Q 3 R11 R12 WA DI 5 E Mii M ID in PWE1 PWEN ENB amp OUTB 2 4 Veus oct OC1 R9 ELGER 5V_Standby A Bs L3 1 Loss oe GND HE T o C42 Mao 043 gt DM1 0 1 uF 5VBUS FB8 TT1 T70 1 pF 8220 uF 10 V n bao I HF BLM41PG600SN1 c 4 4 DPI DPI OC24 OiyF R10 2 IN Pv 5 GND QUA wees T Tm T eat c1 bo Lota T2 re 3 SHIELD R24 R25 PWE2 ENA amp OUTA 0 01 uF M7 uE 10V 1 nF Teo pF 10V oom CONI 15kQ 15 ko MIC2526 LED BLM18PG121SN1 oe ESD2 R13 R14 YS ns 715 T ll 10 kQ 10 ko SU 5 2 E p R21 1 IP 4220CZ6 DvAUX 5600 I VBUS C44 C56 O45 DM2 DM At 0 1 uFAI 220 uF 10 V T 1 nF DR DP2 5VBUS 44 ano te tS FB5 SHIELD R26 R27 v 04 uF Tia bumispar2tsni CON2 s ic 47 WF 1 0 1 uF T7100 pF uF 10V ui p 7 ja USB2 77 17 Optional FB9 J BLM31PG121SN1 5 V_Standby Bracketholes nid x 2 L C11 C12 C13 swi sw2 UT ais wean lis uF TO nF T 100 wr 10V SOCKET SOCKET FB10 BLM31PG121SN1 Fig 4 ISP1562 eval board schematic port power control and ESD protection 9 Z9S1 dSI Duisn sa depe Dd 150u g
10. of these signals even when 43 3 V and 5 V are off The fault flag pins OCn N of MIC2026 are open drain and require the presence of pull up resistors A 100 nF capacitor is used on each OCn N signal to prevent false fault conditions CLKRUN is implemented in the ISP1562 on pin 42 and in the ISP1563 on pin 52 This signal is targeted mainly for mobile system designs CLKRUN is an I O pin It is used by the system to safely turn off the PCI CLK for power saving with acknowledgment from the ISP1562 3 according to a predefined protocol In the case of the PCI adapter card design CLKRUN must always be LOW because it is not present in the PCI connector CLKRUN may directly be connected to GND For details on CLKRUN function refer to PCI Mobile Design Guide Version 1 1 3 2 Input clock applies only to the ISP1563 You can use either of the following as clock input e A 12 MHz crystal the default recommended solution for best ElectroMagnetic Interference EMI results e A48 MHz oscillator this may be a useful alternative typically in the case of on motherboard design Both solutions for the input clock are shown in the schematics To use a 48 MHz clock as input connect the clock signal to the ISP1563 pin 86 XTAL1 pin 87 XTAL2 can be left open and pin 121 SEL48M must be pulled up as shown in the schematics In an add on card configuration normally the 12 MHz crystal is used In such a case oscillators OSC2 and R4
11. source PCI Vaux 3 3 V is introduced in PCI Local Bus Specification Revision 2 2 It allows powering an add on card and generation of the PME signal even if the system is in a deep power management state and PCI Vcc is off An alternative solution to using a jumper may be a simple circuit containing a pair of MOSFET transistors that allows to detect the presence of PCI Vaux 3 3 V and automatic selection of the input voltage Selection of PCI Voc 43 3 V must be the default position of jumper JP1 in the case of a standard add on card design The other possible position of JP1 selects PCI Vayx 3 3 V for complete Power Management tests including S3 in the case of on motherboard or notebook Note that pins 3 77 98 and 100 of the ISP1562 and pins 6 12 and 95 of the ISP1563 are connected to the PCB Vccwo Aux power plane and pins 86 and 93 of the ISP1562 and pins 104 111 120 and 128 of the ISP1563 are connected to the PCB Vppa Aux power plane Each of these planes is separated from PCI Vaux by its own set of inductors and decoupling capacitors Although most of the motherboards provide the PCI Vaur power source in all system power management modes including S301 the PCI 5 V power supply is simultaneously interrupted with PCI Voc 43 3 V In certain standby modes S3 the devices connected to USB ports will not be powered once the 5 V power is removed because the Vgus voltage present on USB connectors is normally derived from the PCI
12. 0 C27 em epus 94 wr o1uF o ur o wr T nt DVAUX L C21 f Qi p rh 1 2 43 3V DVAUX I E C9 R4 R5 4 0 1 WF I 47 kQ 47 kQ 77 1 4 R2 2 4 R3 R6 02 00 00 3 77 17 4 HF AT24C01A 2 7 3 3 V C49 mim oso in T tne Ty tne Ty L ost cs Lose Loss L ca L cas Lose fol neun ue T All capacitors T be placed as close as possible to the corresponding power pins Fig 2 ISP1562 eval board schematic 0 1 uF AD 31 0 C BEO C BE1 C BE2 C BE3 tink TOIT UTI ISP1562 73 58 43 N AUX1V18 AUX1V18 REG1V18 REG1V18 REG1V18 ISP1562ESP AVAUX as close as possible to the corresponding ferrite bead DVAUX AVAUX BLM18PG121SN1 LYYY das C29 i C19 C61 n uF T 1 nF I 47 uF 6 3V 78 OC1 oci 87__OC2 CoA 79 PWE1 gt PWE1 88 PWE2 gt PWED 83 DM1 DM1 90 DM2 gt DM 85 DP1 92 DP2 oni FB3 is optional Can be directly tied to ground di R7 FB3 go 12kQ 1 BLMI8PG121SN1 C624 22 pF N osc 1 12 MHz T C63 p 22 pF E Pues 99 PME PCICLK K Z PCICLK si PCICLK RST le 5 RST RST PAR 47 PAR PAR SERR 4 422 SERRE gt SERR PERR 44 PERR gt PERR 1ko CLKRUN ae aS STOP
13. 17 6 1 Definitio EE UAE AAA 17 6 2 Disclaimer red tems 17 6 3 Trademarks sse 17 T CO o eceeeet erase onec rea enti rra eesaEs 18 founded by Please be aware that important notices concerning this document and the product s described herein have been included in the section Legal information NXP B V 2007 All rights reserved For more information please visit http www nxp com For sales office addresses email to salesaddresses nxp com Date of release 1 November 2007 Document identifier AN10050 4
14. 29 AD20 ADIS Bap AD21 AD20 RA30 B31 AD19 GND A31 7 AD18 pe i E ju AD18 A32 AD16 C BE2 B33_ ADIZ AD16 A35 C BE2 lt p34 C BE2 3V3 A34 1 9 FRAME IRDY C BE2 9 IRDY t Bus GND FRAME lengo gt FRAME IRDY B36 IRDY GND A38 1 9 TRDY TRDY eet DEVSEL 9 DEVSEL B37 e se TRDY AST gt TRDY gt GND IA STOP TOP 38 GND STOP A8 1 STOPE __ stopy PERR amp 9 PERR Bao LOCK 3v3 AO PERR lt 4 EM PERR RESERVED A SERR 3V3 RESERVED SERRE ou ae B42 SEHR GND 42 4 PAR B43 A43 PAR C BE1 2 C BE1 T B44 3V3 _ PAR na ADIS PAR C BE1 lt ADIA B45 gt C BEi AD15 Aie Bas AD14 3v3 aie AD13 AD12 1 Ba7 GND AD13 747 ADI AD10 pig ADi AD11 rr B49 Most GND A49 ADS 9 GND M66EN AD9 3 C BEOR Abe B52 ADS O BEO 42 2 C BEO __ C BEO 1 B54 ADI AS A54 1 7 AD6 iL B55 AD5 AD4 AS AD4 3 B56 AD3 cno A55 Hes 4 B57 GND AD2 37 AD1 B58 ADI ADO ADO B59 MO X VIO Keo AD 31 0 ACK64 REQ64 B61 5V S ABT T B62 45v 15V A62 ii I 45V E CIBUS T I f C48 C52 C46 C14 C54 C53 47 uF 10 V J 47 uF 10V T nF F 0 1 uF 7 nF S uF n t C47 C15 C64 C16 C58 C57 nF T uF 100 pF T uF pes FPES T 43 3V Fig 3 ISP1562 eval board schematic PCI edge connector pamasa sjuBu Iy 2002 NAKO 8LJO LL SJOJONPUODIWISS dXN 9 Z9S1 dSI Duisn 1e1depe 5d 1504 GSN peeds H e Hulubisaq OSOOLNV 100Z 19quioAON t0
15. 5 are not necessary Also pin 121 SEL48M must directly be connected to GND Another possibility is using a 12 MHz clock as an input In this case the 12 MHz clock signal is directly connected to the ISP1563 pin 86 XTAL1 This is similar to the case in which the 48 MHz clock is used however the ISP1563 pin 121 must still be connected to GND 3 3 Selecting the number of ports applies only to the ISP1563 The selection of the number of ports 2 or 4 is done using the SEL2PORTS signal ISP1563 pin 5 It must be pulled to LOW that is connected to GND for normal use of all four ports If SEL2PORTS is HIGH only two ports that is port 1 and port 2 are enabled one port from each OHCI will be used in this case for performance improvement Details regarding the power consumption and possible power savings in a two port configuration can be found in the ISP1563 data sheet 3 4 Subsystem vendor ID and subsystem device ID The ISP1562 8 allows loading of the Subsystem Vendor ID VID and the Subsystem Device ID DID for both EHCI and OHCI from an external EEPROM Loading of these values in the configuration registers of the ISP1562 3 will occur only if a value of 15h is found in byte 7 of the EEPROM The necessary signals I C bus clock and I C bus data NXP B V 2007 All rights reserved Application note Rev 04 1 November 2007 5 of 18 NXP Semiconductors AN1 0050 AN10050 4 Designing a Hi Speed USB host PCI adapter
16. A22 82 ND AD28 h45 AD26 AD27 B23 AD27 AD26 A24 ape AD25 AD25 GND A35 T IDSEL B25 3v3 AD24 AG IDSEL crBEs Q C BES B26 ces IDSEL 557 SIDSEL CIBESH AD2S vn Boiss ava AZ 4 AD22 B28 GND AD22 R59 AD20 AD21 B29 AD21 AD20 A30 ADIS B30 AD19 GND A AD18 ml 3V3 AD18 A32 AD16 17 AD17 AD16 A33 EE B93 CBE 3V3 A34 t QFRAME FRAME amp FRAME CIBE2 4 C BE2 g IRDY B35 GND FRAME A35 9 TROV TRDY IRDY 9 IRDY GND A3c gt TRDY IRDY L B36 3V3 TRDY A37 op DEVSEL DEVSEL 837 DEVSEL GND 537 1 9 sroPs STOP gt STOP DEVSEL B38 GND STOP M A39 i 839 OCK 3V3 mo PERR amp 9 PERR B40 PERR RESERVED A PERR lt 3V3 RESERVED A45 SERRY Q SERR B42 SERA GND 442 9 PAR PAR PPS SES C BE1 Bar 3V3 PAR Aaa ADI5 P C BE1 _ 9 B45 C BEi ADIS A45 Apis C BE1 AD14 AD14 3V3 77 A46 1L B46 GND AD13 A47 AD11 AD12 B47 AD12 AD11 A48 ADS B48 AD10 GND ADIO A49 END B49 M66EN AD9 3 TEL As 2 C BEO CIBEO _ C BEO AD8 B52 aps C BEO A53 AD7 B53 AD7 3V3 AB AD6 B54 3V3 ADe oe AD4 B55 AD5 AD4 ADS B56 Apa GND A6 AD2 B57 GND AD2 ABB ADO AD1 B58 ADI ADO 35 B59 vio vo LM B60 ACK64 REQ64 mRei B61 5V 5V A62 1 B62 5v 45V i l CIBUS C41 C75 F 10V Leis l C14 Loz Rm 47 uF 10 V J 47 pi T nF T 0 1 uF in nF F uF C15 C63 C16 C65 C66 one I uF 100 pF l uF e ISP1563 eval board schematic PCI edge connector
17. DIT 231 Ap 7 PWE3 N 113 PWES pwe3 a nr 47 kQ 47kQ Abia 41 anjis PWE4 N 115 PWE4 y pwegy YADI 40 adha 1 Ud AD20 39 Ap 20 DM 101 DM yp AO vec AD21 38 AD 21 DM2 4 108 DM2 DM2 i T AD22 37 ADI22 DM3 a 17 DMS song e AN R34 R35 R46 y Ab2s 36 AD 23 DM4 e 25 DM4 DM4 m uid y 02 0a 00 AD25 31 Apis DP1 103 DPI pp 3 L AD26 30 ADIS DP2 S110 DP2 Dp FB7isoptional I 3 SCL ATE AD27 25 ADI27 ISP1563 DP3 4 L15 D53 M DP3 Can bedirectly T VAD 241 pog DP4le 127 DPA DPA tied to ground 92 GND SDA 2530 25 pe prer 99 R44 12 kQ 196 g AD 30 FB7 DVAUX notto be implemented o AT24C01A 2 7 GNDA _98 moan E BLM18PG121SN1 o ABUS R38 86 C73 4 22 pF c C BEO CIBEO 72 gt ciBEs o XTALI Ji E OSC2 48MHz 09 15 C74 C28 o AVAUX C BE1 CIBET 58 b CBEgH 87 J 6 1 pel C BE2 RE 45 gt C BE 2 AAA osct R5 94 2 2 uF 10 VI UJ mka C32 Lcs Lcs L C35 C BES lt C BE 3 12 MHz T num U 8 7 5 0 1 uF 70 1 uF 7770 1 WF 0 1 uF INTA 4 INTA 14 INTAR Il p E 330 o REQ REQ 19 REQ DVAUX o GNT GNIS 185 RKO Q IDSEL DSE 34 SEL ml FRAME FRAMER 463 OSE inci LS IRQ1 R31 R32 v IRDY IRDY 27 ins 4 IRQ12 51 ko Sika JP Oo TRDY TRDY 48 IRQ12 Oo DEVSEL DEVSELE29 j TROU nouri A200UT S 4 gt STOP amp STOPS 51 SEL E 8 KBIRQi BA 52 STOP KBIRQ1 5 a PERRE d CLKRUN MUIRQI2 SMF 7 8 D SERR lt PERRI R39 R40 HEADER4X2 ped
18. EMI or the ESD tests because these may affect the signaling quality Nevertheless it is recommended that you include the necessary footprints for common mode chokes and ESD protection components on the PCB as safeguards The footprints must be placed as close as possible to the USB connector Special attention must be given when placing additional components on the DP and DM lines and routing recommendations must be followed Both Vppa_aux analog and Vecivo _aux digital are derived from the PCI Vaux voltage found on pin A14 of the PCI connector Vcc yo Aux can directly be connected to PCI Vaux VppA aux iS separated from PCI Vaux by an inductor and each of Vcc yo Aux and Vppa Aux uses its own decoupling capacitors The design must ensure that the Vppa Aux and Vccio Aux power planes are isolated from the main PCI 3 3 V power plane This is achieved by creating two separate power planes that do not come in contact with the PCI 3 3 V power plane The decoupling capacitors must be placed as close as possible to the ISP1562 3 A good choice is the four corners of the IC because these areas will not normally be occupied by traces or other components according to the ISP1562 3 pinout For good EMI testing results it is recommended that you provide a good path from the USB connector shell to the chassis ground The USB connector shell must be connected to an isolated ground plane For more information refer to the Intel document The USB 2 0
19. Local Bus Specification Rev 2 2 and PCI Bus Power Management Interface Specification Rev 1 1 No additional logic is required to implement a complete Hi Speed USB host controller solution on Peripheral Component Interconnect PCI Adapter cards based on the ISP1562 3 implement three functions function 0 and function 1 for OHCI1 and OHCI2 and function 2 for EHCI According to PC Local Bus Specification each physical PCI device may incorporate one to eight separate functions logical devices Each function contains its own memory mapped individually addressable configuration space of 256 bytes containing configuration registers The configuration registers of the ISP1562 3 are used by the system s BIOS and the operating system to detect the presence of the respective functions that is Vendor ID VID and Product ID PID to determine the necessary resource requirements that is memory and I O space interrupt lines and so on and for specific capabilities A set of on chip operational registers is also defined for each of the three host controllers implemented in the ISP1562 3 The respective host controller device driver interacts with these registers to implement the USB functionality and the legacy support A detailed description of configuration registers and operational registers can be found in the ISP1562 and ISP1563 data sheets The ISP1562 3 implements two internal power wells Vpp and Vppx to benefit from the PCI Vaux
20. PAR PAR 5 R27 02 02 9 All capacitors should be placed as close as possible RST RST SEL2PORTS t ae DVAUX to the corresponding power pins PCICLK t 1 PCICLK R43 E DVAUX M c bod MES aaa X ae lt i EN LZ ud TT esagses 20520 5333 3333 m Gur 3 C51 C29 C30 a FE TF TAFT ne TT od wr 0 1 ur TRO wr poe es AA Us ae pe EIA sro loo SERE eere eere Should be placed as close as a possible to pin 12 m 9 Fig 6 ISP1563 eval board schematic ISP1563 N o Co SJ0jonpuoolul9S dXN OSOOLNV 1007 J9qui9AON L t0 Ad ajou uoneoriddy 8LJOGL v OSOOLNV pamasa sjybi lv 2002 NAKO AD 31 0 Fig 7 45V Ad BS 45V 45V AS Q INTAF INT INTA B6 45V INTA 37 B7 INTB INTC s B8 INTD 45V Ag 1 Bo PRSNT1 RESERVED a7o GND BIO RESERVED vio A 3 PRSNT2 RESERVED 3 3 VAUX N B14 ava AUX Al4 RST Bis RESERVED Ber AIS t gt RST PCICLK _ PCICLK Big GND Vio 38 Bus dai GNT GNT PCICLK 4 B17 GNT 21 and A18 PME PME REQ QREO 818 REQ GND Ai9 PME REQ B19 VIO PME M 450 AD30 AD31 B20 AD31 AD30 AST AD28 B21 3V3 AD29 AD29
21. Platform Design Guideline Rev 1 0 AN10050 4 NXP B V 2007 All rights reserved Application note Rev 04 1 November 2007 8 of 18 NXP Semiconductors AN10050 Designing a Hi Speed USB host PCI adapter using ISP1562 63 Fig 1 PCI CONNECTOR ISP1562 ES1 AD 31 9 PCICLK AD 31 0 PCICLK USB PORTS RST IDSEL RST IDSEL GNT GNT C BEO C BE1 C BE2 C BEO C BE1 C BE2 C BE3 INTA C BE3 REQ FRAME FRAME TRDY IRDY DEVSEL STOP PERR TRDY IRDY DEVSEL STOP PERR ISP1562 eval board schematic top level interfaces POWER CONTROL AN10050_4 NXP B V 2007 All rights reserved Application note Rev 04 1 November 2007 9 of 18 200Z J9qui9AON t0 9H 9jou uoneorddy 8LJO 0L v 0S001NV pamasa sjuBu Iy 2002 NO DVAUX C20 C17 C22 C18 0 1 pF L 0 001 uF 0 1 pF L eT 5 Should be placed Should be placed as close as as close as possible to pin 98 possible to pin 55 DVAUX mbu C38 T 0 001 uF Ay OT BE Should be placed as close as possible to pin 3 JP1 3 3 VAUX DV D3 LED 3b BLM21PG221SN1 AUX 7 RI FB T t T E 1P m ceo o59 330 Q HEADER 3 0 1 uF T 470 pF 1247 uF 6 3 V All capacitors should be placed io ib pm C3
22. al traces 50 mils between the DP and DM traces and clock or high speed periodic signal traces 20 mils between two pairs of the DP and DM traces Avoid creating stubs to connect the 15 kQ pull down resistors or to test points If a stub is unavoidable in the design no stub must be greater than 80 mils Route all the DP and DM lines on one layer Do not change layers avoid using vias even to avoid crossing a plane split It is better to place a non split plane under high speed USB signals ground layer or power layer It is recommended that you place a ground layer beneath the DP and DM lines NXP B V 2007 All rights reserved Application note Rev 04 1 November 2007 7 of 18 NXP Semiconductors AN1 0050 5 Schematics Designing a Hi Speed USB host PCI adapter using ISP1562 63 The maximum allowed length of the DP and DM lines for onboard solutions or trace cable length for a front panel solution is 18 inches A decoupling capacitor must be placed on Vgus as close as possible to each USB connector A value of about 150 uF 10 V is recommended on each port The common mode choke used if really necessary on the DP and DM lines must be placed as close as possible to the USB connector and must have Zoom 80 100 MHz and Zaift 300 2 100 MHz The common mode choke as well as the ElectroStatic Discharge ESD protection components will be used only if necessary in case the design does not pass
23. ect to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability tor the consequences of use of such information 6 2 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof AN10050 4 Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft Space or life support equipment nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclu
24. ent protection not measuring the current through the transistor NXP B V 2007 All rights reserved Application note Rev 04 1 November 2007 6 of 18 NXP Semiconductors AN1 0050 Designing a Hi Speed USB host PCI adapter using ISP1562 63 4 PCB design recommendations AN10050 4 Some important recommendations for a successful PCB design applicable to both adapter card and motherboard design solutions are as follows Typically a solution using four layers PCB signal 1 GND Vcc signal 2 is sufficient for proper routing allowing you to obtain good functionality and meeting all compliance tests requirements Start your design by placing the ISP1562 3 chip the major components and routing of the high speed DP and DM traces and clock traces Also a complete clean solution for routing the power and GND split planes must be defined before you start routing the rest of the signals The trace length for all PCI signals except the PCI clock signal to the PCI connector must be limited to a maximum of 1 5 inches The length of the PCI clock signal from the PCI bus connector to the ISP1562 3 must be 2 5 inches 0 1 inch in length and must be routed to only one load It must usually be snaked Ensure that all corners of this trace are rounded Do not use 90 sharp corners Route the high speed USB differential pairs over continuous GND or power planes Avoid crossing anti etch areas and any breaks in the int
25. ernal planes plane splits The minimum recommended distance to a plane split is 25 mils You must also avoid placing a series of via holes near the DP and DM lines because these will create break areas in the GND plane below This is because of the clearance imposed by the manufacturing process around any via holes to an internal plane Try to keep the length of the DP and DM traces equal The maximum trace length mismatch between high speed USB signal pairs must not be greater than 70 mils Maintain parallelism between USB differential signals with the trace spacing needed to achieve 90 differential impedance To achieve the required impedance of the pair traces it is recommended that you use 8 mils traces and keep the distance between the DP and DM traces at 8 mils These values may vary depending on the actual PCB parameters Avoid corners when routing the differential pairs DP and DM Any 90 direction change of traces must be accomplished with two 45 turns or by using an arc of an imaginary circle tangent to the DP and DM lines Avoid routing the USB differential pairs near I O connectors signal headers crystals oscillators magnetic devices and power connectors Maintain the maximum possible distance between high speed USB differential pairs high speed or low speed clock and non periodic signals The minimum recommended distances are as follows 20 mils between the DP and DM traces and low speed non periodic sign
26. signaled by an external power switching device can be an overcurrent or a thermal shutdown The port power switching integrated devices commonly implement a delay of 1 ms to 3 ms to prevent false OC N reporting because of inrush currents when plugging a USB device Once a fault condition is received it will be detected by the operating system and the respective device driver will disable the port power switch by programming the Port Power PP bit in the PORTSC register This device driver is the OHCI driver in the case of an Original USB device to create the fault condition or the EHCI driver in the case of a Hi Speed USB device to create the overcurrent condition This is according to the USB port allocation at the moment when the OC signal was asserted A possible alternative is to use a resettable fuse on each port This has the advantage of simplicity It however does not inform the operating system of the fault condition and therefore no message is generated to inform the user The resettable fuse will continue to protect the port by switching on or off as long as the overcurrent condition persists A possible enhancement of this scheme is connecting Vaus to the OCn N input of the ISP1562 3 to detect the OCn N condition the first time Vgus is cut off a LOW level will appear on the OCn N pin Using only an external PMOS transistor for overcurrent protection is not possible because the ISP1562 3 does not implement the analog overcurr
27. sion and or use is for the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification 6 3 Trademarks Notice All referenced brands product names service names and trademarks are property of their respective owners C bus logo is a trademark of NXP B V NXP B V 2007 All rights reserved Application note Rev 04 1 November 2007 17 of 18 NXP Semiconductors AN10050 Designing a Hi Speed USB host PCI adapter using ISP1562 63 7 Contents 1 Introduction erre rne 3 2 ISP1562 3 initialization 3 3 Description of the application schematics 4 3 1 Distribution of power sources and power management support eessssseese 4 3 2 Input clock applies only to the ISP1563 5 3 8 Selecting the number of ports applies only to the ISP1563 sssssssseseseeeeeenennnnee nnns 5 3 4 Subsystem vendor ID and subsystem device ID 5 3 5 Legacy support applies only to the ISP1563 6 3 6 Overcurrent protection 6 4 PCB design recommendations 7 5 Schemalics rine rnnt 8 6 Legal information eere
28. sn peeds iH e Buiufiseq OSOOLNV SJ0jonpuoolul9S dXN NXP Semiconductors AN10050 AN10050 4 Designing a Hi Speed USB host PCI adapter using ISP1562 63 PCI PCICONN SCH Fig 5 C BEO C BE1 C BE2 C BE3 TRDY IDSEL PME GNT RST INTA PCICLK REQ STOP FRAME DEVSEL PERR SERR IRDY PAR AD 31 0 ISP1563 eval board schematic top level interfaces ISP1563 ES1 ISP1563 ES1 8CH C BEO C BE1 C BE2 C BE3 TRDY DSEL PME GNT RST NTA PCICLK REQ STOP FRAME DEVSEL PERR SERR IRDY PAR AD 31 0 POWER_SWITCH POWER_SWITCH SCH NXP B V 2007 All rights reserved Application note Rev 04 1 November 2007 13 of 18 v OSOOINY ajou uoneoijddy 200Z 19qUJ9AON t0 H pamasa sjuBu Iy 2002 Aa dXN O
29. using ISP1562 63 are defined on pins 96 SCL and 97 SDA of the ISP1562 and pins 122 SCL and 123 SDA of the ISP1563 respectively When not in use these signals must be connected to ground using a pull down resistor typically 10 kQ 3 5 Legacy support applies only to the ISP1563 Legacy signals IRQ1 IRQ12 A200UT KBIRQ1 MUIRQ12 and SMI are not normally used on a PCI add on card design In this case the MUIRQ12 and KBIRQ1 input signals must be connected to GND The other signals that are mentioned in this category that are outputs can be left open Details on legacy signals and a block diagram showing correct connection of these signals in the case of onboard design can be found in SP1563 Eval Board User Manual UM10066 3 6 Overcurrent protection The ISP1562 3 implements the digital overcurrent protection scheme The recommended solution to implement an external overcurrent protection is a standard power switch with integrated overcurrent detection such as e M3526 and MIC2526 2 ports or e LM3544 4 ports The overcurrent protection logic of the ISP1562 3 uses the following two pins for each USB port e PWEn N It is used to enable or disable the respective external port power switch For example MIC2526 and LM3526 e OCn_N It is an input on which a fault condition on the respective USB port is signaled to the ISP1562 3 by the external port power switching device The fault condition that is usually

NXP Semiconductors ISP1562 User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents