NXP Semiconductors CBT3126 User's Manual
Contents
1. 0 2 5 5mm ee E A AE a R scale DIMENSIONS inch dimensions are derived from the original mm dimensions UNIT Ein Ay A2 A3 bp c D E e He L Lp Q v w y z 6 wen a7s 935 148 oas 942 995 49 27 2 vos 38 G2 oes oa or 2 neres 6 0010 2857 oor 0018 faaroo nao 016 aos 2284 oom 2088 ooze aor oor omoa 008 Note 1 Plastic or metal protrusions of 0 15 mm 0 006 inch maximum per side are not included VERSION coe ueMTA PROJECTION SSUE DATE SOT109 1 076E07 MS 012 E pra Fig 8 Package outline SOT109 1 S016 NXP B V 2008 All rights reserved CBT3126_2 Product data sheet Rev 02 23 October 2008 8 of 15 NXP Semiconductors CBT31 26 Quad FET bus switch SSOP16 plastic shrink small outline package 16 leads body width 5 3 mm SOT338 1 duje je L detail X DIMENSIONS mm are the original dimensions UNIT A A2 Ag bp Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC JEITA PROJECTION SOT338 1 MO 150 E46 agian ISSU2. 0 15 0 05 0 95 0 80 0 30 0 19 0 2 0 1 5 1 4 5 4 9 4 3 Notes 1 Plastic or metal protrusions of 2 Plastic interlead protrusions o 0 15 mm maximum per side are not included 0 25 mm maximum per side are not included OUTLINE VERSION REFERENCES EUROPEAN IEC JEDEC JEITA PROJECTION ISSUE DATE SOT403 1 MO 153 Et 03 02 18 Fig 11 Package outline SOT403 1 TSSOP16 CBT3126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 11 of 15 NXP Semiconductors CBT31 26 Quad FET bus switch DHVQFN16 plastic dual in line compatible thermal enhanced very thin quad flat package no leads 16 terminals body 2 5 x 3 5 x 0 85 mm SOT763 1 JE detail X terminal 1 index area terminal 1 index area DIMENSIONS mm are the original dimensions AM 1 o UNIT nax 1 b c D Dh E Eh 0 05 0 30 36 215 26 1 15 mm 1 9 00 018 34 1 85 24 0 85 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC JEITA
3. 15 founded by Quad FET bus switch Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2008 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 23 October 2008 Document identifier CBT3126_2
4. PROJECTION SOT763 1 esd MO 241 sE E fae ISSUE DATE Fig 12 Package outline SOT763 1 DHVQFN16 CBT3126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 12 of 15 NXP Semiconductors CBT31 26 Quad FET bus switch 14 Abbreviations Table 10 Abbreviations Acronym Description CDM Charged Device Model ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor Transistor Logic 15 Revision history Table 11 Revision history Document ID Release date Data sheet status Change notice Supersedes CBT3126 2 20081023 Product data sheet CBT3126_1 Modifications e The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors e Legal texts have been adapted to the new company name where appropriate e Table 4 Limiting values Piot added e Section 10 Dynamic characteristics tqis value updated CBT3126_1 20011212 Product data sheet CBT3126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 13 of 15 NXP Semiconductors CBT3126 16 Legal information 16 1 Data sheet status Quad FET bus switch Document status I2 Product status Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This docum
5. or warranty that such applications will be suitable for the specified use without further testing or modification Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 may cause permanent damage to the device Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied Exposure to limiting values for extended periods may affect device reliability Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms including those pertaining to warranty intellectual property rights infringement and limitation of liability unless explicitly otherwise agreed to in writing by NXP Semiconductors In case of any inconsistency or conflict between information in this document and such terms and conditions the latter will prevail No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights 16 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owner
6. 126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 3 of 15 NXP Semiconductors CBT3126 7 Limiting values Table 4 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Quad FET bus switch Symbol Parameter Conditions Min Max Unit Voc supply voltage 0 5 7 0 V Vi input voltage 0l 0 5 7 0 V loc supply current continuous current through each Vcc or GND pin 128 mA lik input clamping current V lt 0OV 50 3 mA Tstg storage temperature 65 150 C Prot total power dissipation Tamb 40 C to 125 C 2 S014 package BI 500 mW SSOP14 and SSOP16 package 4 500 mW TSSOP14 package 4 500 mW 1 The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed 2 The package thermal impedance is calculated from JESD51 7 3 For SO14 package Piot derates linearly with 8 mW K above 70 C 4 For SSOP14 SSOP16 and TSSOP14 packages Piot derates linearly with 5 5 mW K above 70 C 8 Recommended operating conditions Table 5 Operating conditions All unused control inputs of the device must be held at Vcc or GND to ensure proper device operation Symbol Parameter Conditions Min Max Unit Voc supply voltage 4 5 5 5 V Vin HIGH level input voltage 2 0 s V Vit LOW level input voltage 0 8 V Tamb ambient temperature operating in free air 40 85 C 9 Static characte
7. 85 C TSSOP 14 plastic thin shrink small outline package 14 leads SOT402 1 body width 4 4 mm 1 Also known as QSOP16 4 Functional diagram 2 3 10E 1A LE 1B i 1A 1B 1E D 20E 2A 5 7 2B 2A 2B 202 D 30E 3a 2 8 3B 3A 3B aoe gt ave eT 4A 4B z 40E 001aaj023 001aaj024 Pin numbers are for the 14 pin packages Fig 1 Logic symbol Fig 2 Logic diagram CBT3126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 2 of 15 NXP Semiconductors CBT3126 5 Pinning information 5 1 Pinning Quad FET bus switch GND CBT3126 001 aaj025 Voc 40E 4A 4B 30E 3A 3B CBT3126 001aaj026 Vcc 40E 4A 4B 30E 3A 3B n c Fig 3 Pin configuration SOT108 1 S014 SOT337 4 Fig 4 Pin configuration SOT519 1 SSOP16 SSOP14 and SOT402 1 TSSOP14 5 2 Pin description Table 2 Pin description Symbol Pin SOT108 1 SOT337 4 Pin SOT519 1 Description and SOT402 1 10E to 40E 1 4 10 13 2 5 12 15 output enable input 1A to 4A 2 5 9 12 3 6 11 14 A input output 1B to 4B 3 6 8 11 4 7 10 13 B output input GND 7 8 ground 0 V Voc 14 16 positive supply voltage n c 1 9 not connected 6 Functional description Table 3 Function selection H HIGH voltage level L LOW voltage level Inputs Switch nOE L H nA to nB disconnected nA to nB connected CBT3
8. CBT3126 Quad FET bus switch Rev 02 23 October 2008 Product data sheet 1 General description The CBT3126 is a quadruple FET bus switch features independent line switches Each switch is disabled when the associated Output Enable OE input is LOW The CBT3126 is characterized for operation from 40 C to 85 C 2 Features Standard 126 type pinout Multiple package options 5 Q switch connection between two ports TTL compatible input levels Minimal propagation delay through the switch Latch up protection exceeds 500 mA per JEDEC standard JESD78 class II level A ESD protection HBM JESD22 A114E exceeds 2000 V MM JESD22 A115 A exceeds 200 V CDM JESD22 C101C exceeds 1000 V E Specified from 40 C to 85 C 3 Ordering information Table 1 Ordering information Type number Temperature range Package Name Description Version CBT3126D 40 C to 85 C S014 plastic small outline package 14 leads SOT108 1 body width 3 9 mm CBT3126DB 40 C to 85 C SSOP14 plastic shrink small outline package 14 leads SOT337 1 body width 5 3 mm founded by Philips NXP Semiconductors CBT31 26 Quad FET bus switch Table 1 Ordering information continued Type number Temperature range Package Name Description Version CBT3126DS 40 C to 85 C SSOP 161 plastic shrink small outline package 16 leads SOT519 1 body width 3 9 mm lead pitch 0 635 mm CBT3126PW 40 C to
9. E DATE Fig 9 Package outline SOT338 1 SSOP16 CBT3126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 9 of 15 NXP Semiconductors CBT31 26 Quad FET bus switch SSOP16 plastic shrink small outline package 16 leads body width 3 9 mm lead pitch 0 635 mm SOT519 1 detail X DIMENSIONS mm are the original dimensions A UNIT nax Ar Az As bp 1 73 Note 1 Plastic or metal protrusions of 0 2 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC JEITA PROJECTION ISSUE DATE acd E 03 02 18 Fig 10 Package outline SOT519 1 SSOP16 CBT3126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 10 of 15 NXP Semiconductors CBT3126 Quad FET bus switch TSSOP16 plastic thin shrink small outline package 16 leads body width 4 4 mm SOT403 1 DIMENSIONS mm are the original dimensions e __ detail X UNIT A1 A2 A3 bp c pM 2 mm
10. age output levels that occur with the output load Fig 6 Enable and disable times Table 8 Measurement points Input Output Vu Vu Vx Vy 1 5V 1 5V VoL 0 3 V Vou 0 3 V CBT3126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 6 of 15 NXP Semiconductors CBT31 26 Quad FET bus switch 12 Test information Vi negative pulse OV Vi positive pulse 001aae331 Test data is given in Table 9 Definitions for test circuit R Load resistance C Load capacitance including jig and probe capacitance Ry Termination resistance should be equal to the output impedance Z of the pulse generator Vext External voltage for measuring switching times Fig 7 Test circuit for measuring switching times Table 9 Test data Supply voltage Input Load VEXT Vec Vi tr t CL RL teu tPHL tpLz tPzL tpyz tPzH 4 5 Vto 5 5 V GND to 3 0 V lt 2 5 ns 50 pF 500 Q open 7 0 V open CBT3126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 7 of 15 CBT3126 NXP Semiconductors Quad FET bus switch 13 Package outline 016 plastic small outline package 16 leads body width 3 9 mm SOT109 1 D xX 4 ae He t a f A As A f lt La Lp f a gt detail X
11. ent contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 16 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the
12. ristics Table 6 Static characteristics Tamb 40 C to 85 C Symbol Parameter Conditions Min Typ Max Unit Vik input clamping voltage Voc 4 5 V l 18 mA 7 z 1 2 V Vpass pass voltage Vi Voc 5 0 V lo 100 uA 3 8 V l input leakage current Vec 5 5 V Vi GND or 5 5 V 1 uA loc supply current Voc 5 5 V lo 0 mA uA Vi Vcc or GND Alce additional supply current control pins per input Bl 2 5 mA Vec 5 5 V one input at 3 4 V other inputs at Vcc or GND Ci input capacitance control pins VV 3 V or0 V 1 7 pF Cio off off state input output capacitance Vo 3 V or 0 V OE Vec 3 4 pF CBT3126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 40f 15 NXP Semiconductors CBT31 26 Quad FET bus switch Table 6 Static characteristics continued Tamb 40 C to 85 C Symbol Parameter Conditions Min Typ Max Unit Ron ON resistance Vec 4 0 V 3 Vi 2 4V l 15mA p 16 22 Q Voc 4 5 V Vi 0 V l 64 mA 5 7 Q Vi 0 V l 30 mA 5 7 Q Vi 2 4 V I 15 mA 10 15 Q 1 All typical values are measured at Vcc 5 V Tamb 25 C 2 This is the increase in supply current for each input that is at the specified TTL voltage level rather than Vcc or GND 3 Measured by the voltage drop between the A and the B terminals at the indicated current through the switch ON resistance is determined by the lowest voltage of the
13. s For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com CBT3126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 14 of 15 NXP Semiconductors CBT3126 18 Contents ONoanaa kh wN Nha i b mb b i d O oa rh whNndD O 16 1 16 2 16 3 16 4 17 18 General description 020ee0ees 1 FeatureS 0c e cece ee eee eens 1 Ordering information 0006 1 Functional diagram 00 cece eens 2 Pinning information 00 eee eee 3 PINNING s2cnesteels beeen eed awa eee 3 Pin description 0 0000 3 Functional description 00 0000s 3 Limiting values 0 0 0 eee eee eee 4 Recommended operating conditions 4 Static characteristics 0 0006 4 Dynamic characteristics 00005 5 AC waveforms 002 e eee eee eee 5 Test information 2 00 c eee eee eee 7 Package outline 0 0 eee eee 8 Abbreviations 000 e eee eee eee 13 Revision history 00ee eee eee 13 Legal information 00 eeeeeeee 14 Data sheet status 0 14 Definitions 020000 200 eee 14 Disclaimers 20000000 eee eee 14 Trademarks nuaa nananana 14 Contact information 0 02006 14 CONEIS isis cee tee wie ce ete x erecta
14. short data sheet the full data sheet shall prevail 16 3 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or 17 Contact information malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation
15. two A or B terminals 10 Dynamic characteristics Table 7 Dynamic characteristics Tamb 40 C to 85 C Voc 4 5 V to 5 5 V for test circuit see Figure 7 Symbol Parameter Conditions Min Max Unit toa propagation delay nA to nB or nB to nA see Figure 5 plz 0 25 ns ten enable time OE to nA or nB see Figure 6 2 1 6 4 5 ns tdis disable time OE to nA or nB see Figure 6 2l 1 0 5 4 ns 1 This parameter is warranted but not production tested The propagation delay is based on the RC time constant of the typical ON resistance of the switch and a load capacitance when driven by an ideal voltage source zero output impedance 2 tp and tpp are the same as tpa tpz_ and tpzy are the same as ten tpLz and tpyz are the same as tais 11 AC waveforms VoH output VoL 001aai367 Measurement points are given in Table 8 VoL and Vox are typical voltage output levels that occur with the output load Fig 5 The input nA nB to output nB nA propagation delay times CBT3126_2 NXP B V 2008 All rights reserved Product data sheet Rev 02 23 October 2008 5 of 15 NXP Semiconductors CBT31 26 Quad FET bus switch Vi nOE input VM GND Voc output LOW to OFF OFF to LOW VoL VoH output HIGH to OFF OFF to HIGH GND switch switch switch enabled disabled enabled 001aaj027 Measurement points are given in Table 8 VoL and Vox are typical volt
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