Nvidia TEGRA DG-04927-001_V01 User's Manual
Contents
1. per Board User Guide nVIDIA 4 9 4 Strapping Pins Straps must be stable from the rising edge of SYS RESET N until 12 5us afterward Figure 26 Power on Strapping Connections pepe VDDIO NAND Recovery Circuit in USB Section FORCE RECOVERY N JTAG ARM proa JTAG ARMO RAM CODES RAM CODE2 T RAM CODE1 1 RAM CODEO 1 BOOT SELECT CODE3 1 BOOT SELECT CODE2 1 BOOT SELECT CODE1 1 BOOT SELECT CODED mm Qjisvaav f Ew Table 14 Power on Strapping Breakdown Strap Options Strap Pins Description USB RECOVERY GMI_OE_N 0 USB Recovery Mode 1 Boot from secondary device JTAG_ARM 1 0 GMI_CLK GMI_ADV_N 00 Serial JTAG chain MPCORE and AVP RAM CODE 3 0 GMI_AD 7 4 SW uses to determine which BCT table to use for DRAM NAND timing BOOT SELECT CODE 3 0 GMI_AD 15 12 Selects Boot device depends on how Boot fuses are burned 1 v0 Advance Information Subject to Change 37 NVIDIA CONFIDENTIAL nVIDIA 5 0 THERMAL er Board User Guide 5 1 Major Component Thermal Specifications Most of the major components used in Tegra 200 series Developer Board are listed in Table 39 along with the temperature range they are able to operate across Note The specifications noted in Table 16 may change and other versions with wider or narrower temperature ranges may be available from the manufacturers An2. HELE ES sontes ean DDR2 Ed E x E c um BE RRER ccr ERRRE VAREF DORZ Hj VAEF DORZ Hj 7 y Advance Information Subject to Change 22 NVIDIA CONFIDENTIAL e NVIDIA Table 7 DDR Pinout Signal Pin Signal Pin DDR A0 A20 DDR DMO F19 DDR Ai C24 DDR DMi E15 DDR A2 D20 DDR DM2 G23 DDR A3 B20 DDR_DM3 D9 DDR_A4 F26 DDR_DQO F20 DDR_AS C26 DDR DQl E18 DDR A6 C27 DDR DQ2 D18 DDR A7 F28 DDR_DQ3 F18 DDR_A8 A26 DDR_DQ4 F17 DDR A9 A23 DDR DQS E21 DDR A10 D23 DDR DQ6 D21 DDR Ali C20 DDR DQ7 F21 DDR_A12 cis DDR DQ8 E17 DDR A13 E28 DDR DQ9 D15 DDR_A14 C28 DDR DQiO F16 DDR_CLK E26 DDR DQii E14 DDR_CLK_N E27 DDR DQi2 F13 DDR CAS N H26 DDR_DQ13 D16 DDR_CKEO A21 DDR DQi4 D12 DDR_CKE1 C21 DDR DQIS D13 DDR_CSO_N E25 DDR DQ16 F23 DDR CSl N C23 DDR DQ17 F25 DDR BAO B26 DDR DQi8 H22 DDR BAL A24 DDR DQi9 G25 DDR BA2 B24 DDR DQ20 F22 DDR QUSEO G15 DDR_DQ21 D24 DDR_QUSE1 G17 DDR DQ22 H24 DDR QUSE2 A18 DDR_DQ23 E23 DDR_QUSE3 B18 DDR_DQ24 F9 DDR_RAS_N B23 DDR_DQ25 F12 DDR_WE_N F27 DDR DQ26 E12 DDR DQSOP E20 DDR DQ27 E9 DDR DQSON D19 DDR_DQ28 F10 DDR DQSip F15 DDR_DQ29 G8 DDR DQSIN F14 DDR_DQ30 F11 DDR_DQS2p F24 DDR DQ3i G9 DDR_DQS2N E24
3. USER GUIDE Tegra 200 Series Developer Board Advance Information Subject to Change NVIDIA CONFIDENTIAL January 2010 DG 04927 001 v01 Document Change History Version Date Description voi JAN 22 2010 Initial Release Advance Information Subject to Change NVIDIA CONFIDENTIAL 1 G Tegra 200 Series Developer Board User Guide nVIDIA Table of Contents 2 1 Feature List 2 2 NVIDIAG Tegra 250 2 3 System DRAM 2 4 Boot Device 2 5 LCD Interface 2 6 External Display Support 2 7 Audio 2 8 USB 2 9 Storage 2 10 Camera optional 2 11 Wireless 2 12 User Interface 2 13 Miscellaneous 2 14 Power 3 0 SATELLITE BOARD HEADERS 3 1 Satellite Board Headers 3 2 I2C Map 4 0 CONNECTION EXAMPLES 4 1 Power 4 1 1 Major Components 4 1 2 Power Supplies 4 1 8 Power Sequencing 4 1 4 Bypass Capacitor Recommendations 4 1 5 Unused Interface Power Rails 4 1 6 Unused Power Management Signals 4 2 Clocks 4 2 1 32 768KHz Clock 4 2 2 Oscillator Clock 4 3 DRAM Memory Configurations 4 3 1 Four 8 bit DDR2 devices 4 3 2 Eight 8 bit DDR2 devices 4 3 3 Unused Pins 4 4 NAND 4 5 USB 4 5 1 Force Recovery 001 v01 Advance Information Subject to Change NVIDIA CONFIDENTIAL 1 Tegra 200 Series Developer Board User Guide nVIDIA
4. AVDD_CAM 285V Signal Pin Signal Pin CSI CLKAN AH26 CSI D2AP AG23 CSI CLKAP AG26 CSI CLKBN AB20 CSI D1AN AD20 CSI CLKBP AC20 CSI D1AP AE20 CSI D1BN AH24 CSI D2AN AH23 CSI D1BP AG24 4 7 1 Unused Pins Any unused signal lines can be left unconnected If neither DSI nor CSI are implemented the AVDD DSI CSI power rail all data clock lines and the DSI CSI RUP DSI CSI RND pins should be left unconnected DG 04927 001 v01 Advance Information Subject to Change NVIDIA CONFIDENTIAL 31 3 Tegra 200 Series Developer Board User Guide AVIDIA 4 8 SD SDIO MMC The Tegra 250 has four SD MMC controllers capable of supporting a variety of devices and protocols including SD Memory SDIO eSD MMC and eMMC SD eSD SDIO can support up to 4 bits and at Standard or High Speed MMC eMMC supports 4 or 8 bit devices Standard or High Speed 4 8 1 SD MMC Card Connections The SD MMC socket uses the controller mapped to the SDIO2 controller pins on the VI interface domain Figure 20 Tegra 200 Series Developer Board Reference design 4 bit SD MMC Card Socket Connection Example VDDIO VI GPIO PI5 SDIO CD N GPIO PH1 SDIO WP DG 04927 001 v01 Advance Information Subject to Change 32 NVIDIA CONFIDENTIAL G Tegra 200 Series Developer Board User Guide NVIDIA 4 8 2 eMMC Device Connections The SD MMC interface can support a
5. Figure 4 Example Satellite Board Block Diagram Tegra 200 Series Developer Board E1162 Additional Functionality ONKEY Button PWR I2C PROG HDR se con CON Tx Rx RTS CTS LID_Status Switch Eh RF On Off Switch Bi ForceRecovery m Touchpad DG 04927 001_v01 Advance Information Subject to Change 12 NVIDIA CONFIDENTIAL gt AVIDIA 3 1 Satellite Board Headers All the interface connections between a satellite board and the Tegra 200 Series Developer Board are through two sets of Samtec FTS series 50 pin Micro Strips connectors Table 2 Satellite Connectors Pinout Dir_ Pin Signal Name Signal Name Pin Dir Dir Pin Signal Name Signal Name Pins Dir In 1 KB COL7 EC_KSO17 2 Out Out 1 LED_WPAN VDD CELL RMT 2 In In 3 KB COL6 EC KSO16 4 Out Out 3 LED WLAN UART4 TXD 4 Out In 5 KB COLS EC KSO15 6 Out Out 5 LED WWAN VDDIO NAND MB 6 Out In 7 KB COL4 EC KSO14 8 Out In 7 W DISABLE UART4_RXD 8 In In 9 KB COL3 EC KS013 10 Out Out 9 LED_WIFI_BT UART4_CTS 10 In In 1 KB COL2 EC_KSO12 12 Out Out 11 LED_CH
6. nVIDIA Figure 24 Debug Interface Connection vbblo sys vpplo sys O ott Tegra DEBUG CONNECTOR iv ge bbc RESET N iv iv L iv TRON Unused Pins If JTAG is not implemented then JTAG RTCK and JTAG TDO can be left unconnected The JTAG TDI and JTAG TMS pins still need to be pulled up and JTAG_TRST_N and JTAG TCK must be pulled down The rail the JTAG pins reside on VDDIO_SYS must be powered for any mode including Deep Sleep 4 9 3 EFUSE The Tegra 250 design must provide a way to supply a 3 3V power source to the FUSE SRC pin This can be accomplished using one of the following mechanisms Test point to connect external 3 3V supply 3 3V Output of on board LDO controlled by the Tegra 250 GPIO 3 3V Output of PMU controlled by PWR I2C from the Tegra 250 Permanently connected to always on 3 3V supply The power source must provide a nominal voltage of 3 3V and be able to supply a minimum of 100mA When not powered a 10K Q pull down resistor each on FUSE SRC is required A 0 1uf bypass capacitor is also recommended on FUSE SRC The KFUSE SRC pin must be pulled down with a 10KQ resistor only Figure 25 EFUSE Connections asy Supply for VPP_FUSE only needed when burning Fuses DG 04927 001_v01 Advance Information Subject to Change 36 NVIDIA CONFIDENTIAL Tega 200
7. 4 6 Display 4 6 1 LCD Displays 4 6 2 HDMI 4 6 3 VGA CRT Out 4 7 Camera 31 4 7 1 Unused Pins 4 8 SD SDIO MNC 4 8 1 SD MMC Card Connections 4 8 2 eMMC Device Connections 4 8 3 SDIO Device Connections 4 8 4 Unused Pins 4 9 Miscellaneous 4 9 1 Thermal Diode Temperature Sensor 4 9 2 Debug Interfaces 4 9 3 EFUSE 4 9 4 Strapping Pins 5 0 THERMAL 5 1 Major Component Thermal Specifications 5 2 Thermal Considerations for Components DG 04927 001 v01 Advance Information Subject to Change 4 NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide nVIDIA 1 0 INTRODUCTION The Smartbook Development System is an example of a development platform built around the Tegra 200 Series Developer Board This example provides a starting point for continued development it outlines a fairly typical Smartbook configuration based on the NVIDIA Tegra 250 Computer on a Chip This document Provides recommendations and integration guidelines for engineers to follow when designing a Smartbook or similar product that is optimized for high performance and low power consumption Details a generic Smartbook Development System development system consists of the NVIDIA Tegra 200 Series Developer Kit plus a satellite board containing most of the user input devices and some features for test and development can be used for evaluati
8. DDR DQS3p D10 DDR DQS3N E11 4 3 3 Unused Pins Any unused signal pins can be left unconnected 001_v0 Advance Information Subject to Change 23 NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide nVIDIA 4 4 NAND The Tegra 250 GMI interface supports a broad range of devices including a variety of NAND devices and configurations Works with SLC and MLC devices Supports up to 8 devices with up to 8 chip selects Figure 11 Single 8 bit NAND Connection Example VDDIO NAND NAND ALE NAND CLE NAND CEO N NAND CE1 N 4 5 USB The Tegra 250 has three available USB controllers Controllers 1 and 3 come out on the USB PHYs on the USB1 and USB3 pins Controller 42 can be used for either ULPI or HSIC only one at a time Controller 1 This USB controller is routed to an integrated PHY USB1 and supports low full and high speed mode Both Host and Device modes are supported VBUS and Device ID are available to support Type A B or A B connector types USB1 is required for Recovery mode and must be configurable as a USB Device when the Force Recovery strap on pin GMI OE N is held low In this case USB1 is connected to a host typically for flashing images at the factory or possibly in the field Controller 2 Controller 2 can be used for either ULPI or HSIC Only one can be used in a design ULPI is a 12 pin I F used to connect to compatible external USB PHYs bas
9. Reset and Force Recovery Buttons Lid Open Close slider switch UARTA 4 pin UART brought to RS232 DB9 serial connector intended for software test and debug Adds a coin cell battery for uninterrupted Real Time Clock operation when the developer board is powered off Advance Information Subject to Change 6 NVIDIA CONFIDENTIAL nVIDIA Figure 2 Tegra 200 Series Developer Board Top View Tegra 200 Series Developer Board User Guide VGA Conn J12 LCD 37 ACIDC pud g EP EOM a Jack ua DES Ey Far v Camera pt J15 ml A D PCIE niaje y lt b WEE ie ae Mini use BN 7 Vg BE oa Card 0 wa H 27 o SIMCard LE 119 718 SD MMC Oo 35 L ppm PCIE or i Mini o Card 1 T Tegra T20 27 Jack J4 U4 E a EH eet ffs USB Host Zag Port J25 Dual USB LE VA E igen wm Host Ports E I pP d Coo 6 i bc lai Ls t B e B f l z Jo MMC VCORE J20 Headphn Debug 2 us Internal L Jack 1 Conn Dover SD MMC Y 110 126 Mic Jack Walla 2 n i Q va Y E Lu WE du Oh ForceRec Heset Satellite Right Mic pkr Button But
10. TO THE MATERIALS AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Information furnished is believed to be accurate and reliable However NVIDIA Corporation assumes no responsibility for the consequences of use of such information or for any infringement of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of NVIDIA Corporation Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied NVIDIA Corporation products are not authorized for use as critical components in life support devices or systems without express written approval of NVIDIA Corporation Macrovision Compliance Statement NVIDIA Products that are Macrovision enabled can only be sold or distributed to buyers with a valid and existing authorization from Macrovision to purchase and incorporate the device into buyer s products Macrovision copy protection technology is protected by U S patent numbers 5 583 936 6 516 132 6 836 549 and 7 050 698 and other intellectual property rights The use of Macrovision s copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay per view uses only unless otherwise authorized in writing by Macrovision Reverse engin
11. 26 SD MMC socket is a combination 8 bit MMC and 4 bit SD MMC socket intended to be for internal storage most likely an eMMC module Although this device is in a socket it is not meant to be used as removable storage in a real design 3 3V is supplied to the socket There is also a 2 pin header J5 to supply a core rail at 2 85V This header is used when the eMMC module is installed in this socket SD MMC Socket 2 J5 The J5 SD MMC Socket is a removable storage is a standard 4 bit SD MMC socket This would normally be located to allow SD MMC SDIO cards to be inserted and removed by the user 3 3V is supplied to this socket 2 10 Camera optional A socket for a camera module is provided on the Tegra 200 Series Developer Board J9 2 11 Wireless Bluetooth and Wifi The Tegra 200 Series Developer Board integrates a MuRata BT WF Module using the CSR BC6 and Atheros AR6002 controllers The Bluetooth 2 0 transceiver sends and receives on a 2 4GHz line including Enhanced Data Rates EDR up to 3Mbps and scatter net support USB and Dual UART Ports with rates up to 3MBaud are supported It operates at full speed Bluetooth operation with full piconet support and co exists with 802 11 The CSR device will act as a serial peripheral when connected to the Tegra 250 via a serial port This interface as with WiFi below will be implemented on a substrate typically LTCC supplied by MuRata containing all components required for operation to minimize
12. ARGE UART4_RTS 12 Out In 13 KB COL EC KSO11 14 Out Out 13 LED POWER NOCONNECT 14 In 15 KB COLO EC KSO10 16 Out Out 15 ED SCROLL LOCK FORCE ACOK 16 In Out 17 KB ROW15 EC KsO9 18 Out Out 17 LED CAPS LOCK VDDIO SYS MB 18 Out Out 19 KB ROW14 EC KsO8 20 Out Out 19 LED NUM LOCK PWR I2C SCL 20 Bi Out 21 KB ROW13 EC_KSO7 22 Out 21 GND PWR I2C SDA 22 Bi Out 23 KB ROW12 EC_KSO6 24 Out In 23 SPDIF IN VDD 3V3 MB 24 Out Out 25 KB_ROW11 EC KsO5 26 Out Out 25 SPDIF OUT VDD 3V3 MB 26 Out Out 27 KB_ROW10 EC_KSO4 28 Out 27 GND GND 28 Out 29 KB ROW9 EC KSO3 30 Out Out 29 IR TXD PS2 TS CLOCK 30 Bi Out 31 KB ROWS EC KsO2 32 Out In 31 IR_RXD PS2_TS_DATA 32 Bi Out 33 KB ROW7 EC_KSO1 34 Out In 33 LID OPEN GND 34 Out 35 KB ROW6 EC KsO0 36 Out Out 35 VDD 5V0 MB CAM I2C SDA 36 Bi Out 37 KB ROWS EC KSI7 38 In Out 37 VDD 5V0 MB CAM I2C SCL 38 Bi Out 39 KB ROW4 EC KSI6 40 In In 39 TP IRQ GND 40 Out 4 KB ROW3 EC_KSIS 42 In In 41 TS_IRQ PS2_TP_CLOCK 42 Bi Out 43 KB_ROW2 EC_KSI4 44 In 43 NO CONNECT PS2_TP_DATA 44 Bi Out 45 KB_ROW1 EC_KSI3 46 In In 45 ONKEY LED HEARTBEAT 46 Out Out 47 KB ROWO EC_KSI2 48 In In 47 FORCE RECOVERY SYS RESET B 48 Out In 49 EC KSIO EC KSI1 50 In In 49 RESET VDD 3V3 EC MB 50 Out 001 v0 Advance Information Subject to Change NVIDIA CONFIDENTIAL gt AVIDIA 3 2 12C Map
13. D_DE u23 LCD D6 Y26 LCD D16 v27 LCD_HSYNC AD27 LCD D7 Y27 LCD D17 v26 LcD_PeLK v28 LCD D amp v28 LCD Di8 AB25 LCD Di3 u28 LCD VSYNC AD26 Advance Information Subject to Change 28 NVIDIA CONFIDENTIAL 3 Tegra 200 Series Developer Board User Guide nVIDIA 4 6 2 HDMI HDMI RSET on the Tegra 250 is tied to ground through a 1KQ 1 resistor DDC SCL SDA pins are 5V tolerant no level shifter required 12C pull ups connect to 5V supply HP DET drives HDMI INT interrupt pin on the Tegra 250 Also 5V tolerant no level shifter required Figure 17 HDMI Connection Example WbohHDMI amp VDDIO HDMI ipii DOG BLOX 120580098 120R 100M HDMI DOG DATA angie ow HOMJ INT ES we pcr io 200pf 35v 100KQ M8 as DDGICEG_GND e DDG DATA eic DDC CLOCK 15 C vopio Lco pum oe RSRVO 944 ESD CEC 013 Protection CK 2 Ss CK mr 91 MO D es Do sue o S g Dor D1 6 DI SHIELD Die D2 KAT D2 SHIELD D2 CjAvbD HDMI PLL 1 8V Cjavon_Homi 3v 777 SHIELD GND Table 11 HDMI Pinout Signal Pin Signal Pin HDMI_TXCN AF17 HDMI TXDIN AC18 HDMI_TXCP AG17 HDMI_TXD1P AD18 HDMI_TXDON AE16 HDMI TXD2N AHIB HDMI_TXDOP AE17 HDMI TXD2P AGIB 4 6 2 1 Unused Pins Any unused s
14. KEY VDD 2V2 S x Signals e 5 g E z 3 2 E Enabled 32KHz Ramp Time System Clock External Source or XTAL Iv Oscillator Ramp Time 1 woo ve 18V DOIDG TPSS1 116 VaREF DDR2 03V DOIDC TPSS 16 7 AVDO USS ruse PLL 83V PHULDOS NGORE MMC 25V PMU LDOS vop DDR RX 285V PMU DOS VOD 33 83V DCDC TPS51220A vo CPU 10V PMU SMI SYS RESET N PMU AVDD VDAC 2 85V PMU LDOS ADD HDMI 53V PMU LDOT or ADD HOM PLL 18V PMU L008 TES VDDIO PEX CLK 53V PMU LDOO 0 Misc V 33V 80V Backlight GPIO ADD DSL CSI 12V LDO TPST2012 1 VbD 1V05 05V DCIDC TPS62290 VDD 3V3 VDDIO NAND 3V3 VDDIO SDIO VDDIO VI VDD iV amp VDDIO NAND 1V8 VDDIO LCD VDDIO BB VDDIO AUDIO VDDIO UART VDDIO DDR VDD 1V05 AVDD PLLE AVDD PEX AVDD PEX PLL VDD PEX Note 1 VDD RTC VDD CORE Critical PLLs AVDD OSC VDDIO_SYS VDDIO DDR VDDIO_NAND 32 768KHz and System clocks required before SYS RESET N goes high 2 Recommended Power down sequence is reverse of Power up DG 04927 001 v0 Advance Information Subject to Change 18 NVIDIA CONFIDENTIAL nVIDIA 4 1 4 Bypass Capacitor Recommendations Table 5 lists the basic recommendations for bypass capacitors near the Tegra 250 In general one 0 1uf per power pin or group for cores is de
15. LDO4PG AVDD USB AVDD USB PLL 33 33 PMU LDO3 PMU SM2 3 7V Internal Trigger VDD DDR RX 28 28 PMU LDO9 PMU SM2 3 7V Internal Trigger VDDIO NAND if 3 3V VDDIO_SDIO VDDIO_VI 182833 33 TPSS1220 DC DC EN_VDD_3V3 Output of SR AVDD VDAC 27 33 285 PMU LDO6 PMU SM2 3 7V AVDD_HOMI 33 33 PMU LDO7 PMU SM2 3 7V AVDD_HOMI_PLL 18 25 18 PMU LDOB PMU SM2 3 7V VDDIO_PEX_CLK 33 33 PMU LDOO PMU SM2 3 7V AVDD DSI CSI 12 12 TPS72012 LDO2 EN VDD 1V2 PMU GPIO AVDD PCIE AVDD_PEX AVDD PEX PLL VDD PEX 1 05 105 TPS62290 DC DC EN_VDD_1V05 PMU GPIO VCORE MMC 27 38 285 PMU LDOS Note 1 This includes pins AVDD_PLLA_C_P powers PLLA PLLC and PLLP AVDD_PLLM AVDD_PLLU powers PLLU and PLLD and AVDD_PLLX If PCIE not supported in a design AVDD_PCIE should be left unpowered as the leakage is significant 2 Supplies must meet maximum rate requirement in AP20 EMT of 165mV us 0 Advance Information Subject to Change 17 NVIDIA CONFIDENTIAL G Tegra 200 Series Developer Board User Guide NVIDIA 4 1 3 Power Sequencing The Power solution including the PMU and any external supplies logic must be able to meet the Tegra 250 power sequence requirements These requirements are detailed in the Tegra 200 Series datasheet Electrical Mechanical and Thermal Specifications Figure 7 shows the sequence used for the Smartbook Development System Figure 7 Power up Sequence Example ll ON
16. NAND on board nternal SD MMC socket supports eMMC module Baseband USB based PCle Mini Card Modules USIM Card Connector Display LVDS Bridge TI SN75LVDS83B HDMI Type A connector Slim 15 pin VGA Connector Wolfson WM8903L Codec Stereo Headphones External and Internal Mics Left Right Speaker Amps Imaging Dual lane MIPI CSI connection for camera module Wireless Murata WiFi and Bluetooth module Bluetooth CSR BC6 802 11b g WiFi Atheros 6002 Tegra 200 Series Developer Board User Guide SD SDIO and HSMMC Standard SD SDIO MMC socket USB and Ethernet SMSC LAN 9514 USB Hub and Ethernet S8USB Type A Host ports USB for PCIE MiniCard Slot 2 Ethernet RJ 45 Jack SMSC USB3315 ULPI PHY USB for PCIE MiniCard Slot 1 USB Mini Type B connector for Recovery Mode Buttons Switches Power On Reset and Force Recovery Buttons Miscellaneous Devices EC SMSC MEC1308 Temperature Sensor ADT7461AARMZ RL7 Power PMIC TI TPS658621AZGUR Battery Charge Controller TI BQ24745RHDR Main system regulators 8 3V 5V 1 8V and 1 05V Other lower power regulators 83V standby 1 2V and 1 5V Debug Test Features 22 pin Debug Connector JTAG UART and SPI Tegra Debug Module optional This is an optional module that may have been shipped with your Tegra 200 Series Developer Board depending on the version of the development kit that was ordered Power
17. The I2C interface can be used to connect a touch screen touch pad and other devices There are two options for the Touch devices I2C versions of these devices recommended interface to the Tegra 250 while PS 2 versions connect to the EC controller Table 3 Tegra 200 Series Developer Board I2C Map Contrir Tegra 250 Slave addr I2C3 CAM I2C SCL SDA la MEC1308 I2C Master 0x45 Main Board I2C3 CAM I2C SCL SDA Touchpad 0x28 Remote Location I2C3 CAM I2C SCL SDA Touchscreen TBD Remote Location I2C1 GEN1 I2C SCL SDA Camera 0x36 Main Board I2C1 GEN1 I2C SCL SDA Autofocus DAC Ox0C Main Board y Pack is Master or Slave Ici GEN1 I2C SCU SDA 3V Option for SMB to Battery Pack addr OxOB Main Board I2C1 GEN1_I2C_SCL SDA Option for SMB to Charger 0x09 Main Board I2C2 DDC SCL SDA Mini VGA or HDMI Display 0x30 0x50 0x52 Main Board PWR I2C PWR I2C SCL SDA TI TPS658621 PMU 0x34 Main Board I2Ci WM8903 Audio Codec Ox1A Main Board PWR_I2C ID EEPROM 0x50 Main Board PWR I2C ID EEPROM 0x51 Remote Location PWR_I2C Temperature Sensor Ox4C Main Board Figure 5 12C Diagram TOUCHPAD iso sarao com CEA CAM pc Qva TOUCHSCREEN 27 sc meisos AM EC SDA SCL Ec sub VDDIO vi
18. USB controllers Controllers 1 and 3 come out on the USB PHYs on the USB1 and USB3 pins Controller 2 can be used for either ULPI or HSIC only one at a time All three USB controllers are used on the Tegra 200 Series Developer Board Controller 1 USB1 PHY is required for Recovery mode and so is brought out to a USB Mini B connector J3 USB1 is configured as a device to allow connection to a host PC typically for flashing images at the factory or possibly in the field Controller 2 USB2 provides a ULPI interface on the Tegra 200 Series Developer Board and connects to an external USB3315 ULPI PHY The PHY then connects to PCle Mini Card 0 J27 which is intended for a 3G baseband module Controller 3 USB3 PHY is routed to an SMSC LAN9514 USB Hub and Ethernet controller This controller provides one Ethernet interface and four USB Host ports The Tegra 200 Series Developer Board routes the Ethernet signals to a standard RJ 45 jack Three Advance Information Subject to Change NVIDIA CONFIDENTIAL lt a G Tegra 200 Series Developer Board User Guide nVIDIA of the USB ports are brought to standard Type A connectors J6 Dual host port connector and J25 Single host port The forth USB is routed to PCle Mini Card 1 J28 2 9 Storage There are two SD MMC sockets on the Tegra 200 Series Developer Board Both sockets support High Speed operation 52MHz for MMC 50MHz for SD SDIO SD MMC Socket 1 J26 The J
19. cam 1ac sve SANLI20_SPA SCL G sve T SMB sve SlaveGVo 7h47 400KHz Um e Is Ov Re eme Axa E io 5 5 AUTOFOCUS DAC e e ov zma 2 2 vobi UART GEN tacgnve GEILE SOASCL 1v8 LIC INET HOC 4008 2 E TN T T Bc sub Qvo AP SMBQ ava Master or m cen pc eso p SEB Slave EC 33V 7h08_100KH2 E Sree Charger BQ24745 2 SMB 12C_1 8V_7h0S_100KHz Pumpe Zane Sensor amtasi av aav ue EC 3V ThAG AH max coec e903 EUR CTWA 400682 max aisoz GAT mD como 1p gEPROM 2400025 Satellite VDDIO SYSPWR 120 1va NR EC SDASCL 1V8 PAR EQ To EC 18 7f61 4 XKhz max TM 195650623 L BS 718 orea 400KHe max p _prpRoM 24n9025 Harmony Ec 18V 7060 A00Knz max sum von ODIO NAND GEN2 Joc sva SENZIZC_SDASCL Q Svo CAE VoDIO VGA Homi PU DDC DC SDA SCL 1V8 5V Tolerant DDC EC Qv prd VDDIO LCD DDC I2c 1v PDC EC 9 Uc TAG SN TTGOSQ52 AUOKHz max 001 v0 Advance Information Subject to Change NVIDIA CONFIDENTIAL nVIDIA 4 0 CONNECTION EXAMPLES Tegra 200 Series Developer Board User Guide 4 1 Power Figure 6 Tegra 250 Power Connection Example PWR 2C SCL PWR I2C SDA CORE PWR REQ CPU PWR REQ SYS RESETN iE aT DDIO PEX CLK IVDD dV PCIe MiniCard DG 04927 001 v01 Advance Information Subject to Change 15 NVIDIA CONFIDENTIAL KI Tegra 200 Series Developer Board User Guide nVIDIA 4 1 1 Major Components 4 1 1 1 PMU Th
20. displays One of the displays can be an LCD while the other an HDMI display standard NTSC PAL TV or CRT Alternately a number of dual LCD combinations are supported An 18 bit interface to an external LVDS Transmitter to connect to common Smartbook panels is described Other interface options are possible The example assumes an SPWG 18BPP single channel LVDS panel interface Figure 15 Single Channel LVDS Signal Mapping Previous Dat H Current Data LVDS CLKOUTPN X H X X i LVDS YOPM X RIX RON K Go LVDS Y1P M B1 LVDS_Y2P M DE De DG 0 Advance Information Subject to Change 27 NVIDIA CONFIDENTIAL G Tegra 200 Series Developer Board User Guide nVIDIA Figure 16 Example LVDS Connections LVDS Transmitter LCD PCLK CLKIN YOM LCD VSYNC Dos Yor LCD HSYNC D24 LCD DE D26 YIM vie LCD D 16 12 DIA LCD DI7 D6 YM LCD DIS 6 E Di9 7 E LCD D 11 L D I4 12 LCD po Dis CLKOUTM LCD D S I P D22 18 CLKOUTP CLKSEL SHTDN 120R 100MHz PLLVCC vDD LVDS PLLGND 120R 100MHz LVDSGND LVDSVCC GND vec VDDIO LCD toyee Q vboio Lco Table 10 LVDS Pinout Signal Pin Signal Pin Signal Pin LCD DO AA26 LCD D9 v25 LCD_D19 AA23 LCD Di AC26 LCD D10 AA28 LCD D20 AB23 LCD D2 AC27 LCD Dii AA27 LCD D21 AA22 LCD D3 lAC28 LCD Di2 u25 LCD_D22 v25 LCD D4 AD25 LCD Di4 u27 LCD_D23 AC22 LCD D5 AD28 LCD D15 u26 LC
21. e Tegra 200 Series Developer Board includes a multi channel power management unit for embedded processors TI TPS658621 Feature List Host Interface 12C Control I F Core CPU power request signals 82 768KHz Clock Reset input Reset output RTCLDO 1 0V 1 2V nominal voltage range with 25mV steps Separate LDO for RTC domain allowing Deep Sleep mode support the Tegra 250 lowest power mode Switch RTC domain automatically back to 1 2V when wake up event detected w CORE PWR REQ CORE switcher 1 0V 1 2V nominal voltage range with 25mV steps CORE and RTC domains must track each other within 170mV Tracking can be ensured in software Optimized DVS handled by NVIDIA BSP DVFS architecture Turned off if CORE PWR REQ is de asserted on at 1 2V when CORE PWR REQ asserted CPU switcher 0 85 1 0V nominal voltage range with 25mV steps Optimized DVS handled by NVIDIA BSP DVFS architecture Turned off if CPU_PWR_REQ is de asserted on at 1 0V when CPU_PWR_REQ asserted PLLLDO Use 1 1V LDO Very good line regulation ensured using DC DC switcher as LDO source STDBY input Standby mode Only the minimum rails are kept powered RTC and SYSTEM domains DDR2 in self refresh The Tegra 250 indicates Standby mode by de asserting CORE PWR REQ polarity programmable 4 1 1 2 Battery Charge Controller The Tegra 200 Series Developer Board includes a battery charger with input current detect compa
22. eband or other compatible devices An example of the ULPI interface being used to connect to an SMSC USB3315 ULPI to USB PHY is shown in the ULPI section HSIC is a 2 pin I F for high speed chip to chip communications to compatible external PHYs hubs basebands etc Controller 3 Controller 3 can be routed to a second integrated USB PHY USB3 or to the IC USB interface Only one of these functions can be used in a design USB3 also supports low full and high speed modes and can be configured as Host or Device VBUS and Device ID are provided on this interface Typically in a Smartbook design USB3 would be used as a Host to interface to a Type A host port or more likely a USB Hub An example of USB3 interfacing to an SMSC LAN9514 USB Hub and Ethernet controller is provided in section 3 7 The IC USB interface is used to connect to compatible SIM Cards DG 04927 001 v01 Advance Information Subject to Change 24 NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide nVIDIA 4 5 1 Force Recovery The Tegra 250 requires USB1 to be available as a Device for Force Recovery mode which is used to download new firmware This is shown in Figure 12 where a USB Mini B connector is available to connect to a Host system Force Recovery mode is entered by keeping the FORCE RECOVERY pin low when the system is first powered up until SYS RESET N goes high This is accomplished by pressing the momentary push button shown during powe
23. eering or disassembly is prohibited Trademarks NVIDIA the NVIDIA logo and Tegra are trademarks or registered trademarks of NVIDIA Corporation in the U S and other countries Other company and product names may be trademarks of the respective companies with which they are associated Copyright 2010 NVIDIA Corporation All rights reserved ia com NVI DIA NVIDIA Corporation 2701 San Tomas Expressway Santa Clara CA 95050 www nvi
24. es see http focus ti com lit ds symlink tps2052 pdf 135 mQ Power Distribution Switch TI TPS2051 for a detailed description and list of device features see http focus ti com lit ds symlink tps2051 pdf Advance Information Subject to Change 16 NVIDIA CONFIDENTIAL er Board User Guide G Tegra 200 Si NVIDIA 4 1 2 Power Supplies The Tegra 250 has 29 power rails 3 cores 14 analog and 12 digital I O Depending on system design many of the rails can share a power supply and some are not needed for all designs The example shown in Table 4 is based on the Smartbook Development System design and should be representative of these types of designs This table mainly lists the supplies required by the Tegra 250 Others are required to support some of the peripherals typically seen in a Smartbook Table 4 Tegra 250 Power Supply Allocation Example Power Rails Supported ae Power Supply Enable Voltages V Series DB VDD_RTC 10 12 Upto 1 2 PMU LDO2 PMU SM2 3 7V Internal Trigger VDD CORE 10 12 Upto 12 PMU SMO CORE PWR REQ Internal Trigger VDD CPU 09 109 Up to 10 PMU SMO CPU PWR REQ Internal Trigger AVDD PLix 11 11 PMU LDO1 PMU SM2 3 7V Internal Trigger VDDIO SYS AVDD_OSC 18 18 PMU LDO4 PMU SM2 3 7V Internal Trigger VDDIO_LCD VDDIO_BB VDDIO_AUDIO VDDIO_UART 1 8 2 8 3 3 EN VDD 1V8 VDDIO DDR 18 ru TPS51116 DC DC GG Vppro sys PMU
25. i controller The connection example in Figure 22 is from the Smartbook Development System This shows a Wi Fi BT module interfacing to the Tegra 250 SDIO1 UART3 and DAP4 interfaces as well as several GPIO pins for control Only the signals between the Tegra 250 and the module are shown Figure 22 Tegra 250 SDIO WiFi Connection Example WiFi SDIO CLK SbIO CMD SDIO DATO SDIO DATI SDIO DAT2 SDIO DATS WLAN SYS RST WLAN PWD BT UART RX 4 8 4 Unused Pins Any unused data pins can be left unconnected If the HSMMC or SD SDIO interfaces will not be supported at all then any unused signal pin can be left unconnected or configured for another function or GPIO If none of the signals are used on one of the digital power domains except VDDIO_DDR and VDDIO_SYS which must be powered for normal operation then the associated power rail can be left unconnected or tied to GND DG 04927 001_v01 Advance Information Subject to Change 34 NVIDIA CONFIDENTIAL 3 Tegra 200 Series Developer Board User Guide nVIDIA 4 9 Miscellaneous 4 9 1 Thermal Diode Temperature Sensor Figure 23 Thermal Diode Connection Example av T5 EN up eee wy qp hen Tegra E z 1000p w oo voDIo svs aw TEMP ALERT N Pin LCD DOO GPIO_PNE miii MM om de 2 Table 13 Thermal Diode Pinout Signal Pin THERMD N E6 THERMD_P F7 4 9 2 Debug Interfaces An op
26. ignal lines can be left unconnected If HDMI is not implemented AVDD HDMI HDMI PLL rails and all signal pins can be left unconnected DG 04927 001 v01 Advance Information Subject to Change 29 NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide NVIDIA 4 6 3 VGA CRT Out Figure 18 VGA Output Connection Example emi emi SEH cpt sone oor 09r or otur T Suelo ion VnAC ese vopio Lco VoDIO GA aoe aa zangoz fesses lm Jer zangoa OS PRA ZARON PRA 4 6 3 1 Unused Pins Any unused VDAC pins VDAC_R VDAC_G VDAC_B can be left unconnected If the TV CRT Output function will not be supported AVDD_VDAC VDAC_R G B VDAC_RSET and VDAC_VREF should be left unconnected DG 04927 001_v01 Advance Information Subject to Change 30 NVIDIA CONFIDENTIAL nVIDIA 4 7 Camera Tegra 200 Series Developer Board User Guide The Tegra 200 Series Developer Board supports a dual lane MIPI CSI connection The Smartbook Development System uses an OmniVision Camera module Figure 19 Tegra 200 Series Developer Board CSI Camera Connections Table 12 CSI Pinout VDDIO Vi VDDIO CAM E A vono cam VDDIO UART C voD psi csi VCORE CAM 1 5 O 120R 100MHz VDD AF 3 VDDIO_CAM 1 8V
27. l datasheet CPCB is PCB capacitance trace via pad etc cl Advance Information Subject to Change NVIDIA CONFIDENTIAL G Tegra 200 Series Developer Board User Guide NVIDIA 4 3 DRAM Memory Configurations Tegra 250 supports standard DDR2 SDRAM Up to 1GB total memory two chip selects and two Clock Enables are supported A full 8 device configurations using x8 DDR2 devices is shown A 4 device configuration is possible and is a subset of the 8 device configuration Only Rank 0 would be used in this case 4 3 1 Four 8 bit DDR2 devices Four Devices are routed in parallel to form single 32 bit memory Rank 1 Chip Select 1 Clock Enable CLK Address BA RAS CAS WR CKEO CSO and ODTO are routed to all devices 4 loads DQ 31 0 DQS 3 0 DQM 3 0 are routed to one device each 1 load 4 3 2 Eight 8 bit DDR2 devices Two Ranks of four devices each form two 32 bit memory Ranks 2 Chip Selects 2 Clock Enables CLK Address BA RAS CAS WR and ODTO are routed to all devices 8 loads CKE 1 0 and CSO 1 0 N are routed to 4 devices each 4 loads DQ 31 0 DQS 3 0 DOM 3 0 are routed to 2 devices each 2 loads Figure 10 Eight 8 bit DDR2 Configuration Ranko Rank1 E m Q uem ien pes E a En pore pore WEN 8 WEN e EECCCEE ore k E ES k Z pel k mme
28. lock The Tegra 200 Series Developer Board utilizes a 12MHz crystal connected to the Tegra 250 XTAL IN XTAL OUT pins to generate the reference clock internally A reference circuit is shown in Figure 9 Table 6 contains the requirements for the crystal used the value of the parallel bias resistor and information to calculate the values of the two external load capacitors C and C 2 shown in the circuit DG 04927 001 v01 Advance Information Subject to Change 20 NVIDIA CONFIDENTIAL e nVIDIA Figure 9 Crystal Connection Example Table 6 Crystal and Circuit Requirements Tegra XTAL OUT Tegra 200 Series Deve er Board User Guide Symbol Parameter Min Typ Max Unit Fe Parallel resonance crystal Frequency 12 MHz Fro Frequency Tolerance 50 ppm amp Load Capacitance for crystal parallel resonance 5 7 10 pf DL Crystal Drive Level 300 uw Raus External Bias Resistor 2 Ma ESR Equivalent Series Resistance 80 Q Note FP FTOL CL and DL are found in the Xtal Datasheet ESR RM 1 C0 CL 2 where RM Motional Resistance CO Shunt Capacitance from Xtal datasheet Datasheets may specify ESR directly consult manufacturer if unclear whether ESR or RM are specified Load capacitor values C x can be found with formula C C xCi2 Cu Ci2 Coce Or since Cu and Cazare typically of equal value C Cix 2 Crce or Crx Ci Cece x 2 Load capacitance Xta
29. neration Dark Orange Significant contributor to heat generation The Green coded devices may be significantly affected by temperature Typically these have more analog circuitry and may not perform as well hot such as the Camera Module The other highlighted parts contribute additional heat to the system which can be problematic to deal with in an enclosed mobile device ES Advance Information Subject to Change NVIDIA CONFIDENTIAL eo Tegra 200 Series Developer Board User Guide nVIDIA Figure 27 Top View Heat Generating and Thermal Sensitive Components Inductor Fe 3 3V L3 hk WS 50V L2 Inductor Swi 1 8V L4 Bm DG 04927 001 v01 Advance Information Subject to Change 39 NVIDIA CONFIDENTIAL G Tegra 200 Series Developer Board User Guide nVIDIA The Tegra 200 Series Developer Board does not represent an actual layout for use in a Smartbook design It does show the various components typically found in a Smartbook and aids in describing some useful thermal guidelines Keep hotter or more sensitive components from being in close proximity to each other This may include keeping them from being directly op
30. ntrolled by PM3 PWMO on SDIO3 DAT3 SDIO block Backlight power provided from VDD VBAT battery or AC DC adapter and enabled by the Tegra 250 GPIO on LCD CS1 N LVDS Transmitter shutdown enabled by Tegra 250 GPIO on pin LCD PWRO 2 6 External Display Support A standard HDMI Type A connector J18 is provided and supports up to 1080p60Hz operation The Tegra 200 Series Developer Board supports Hot Plug Detect by routing the HP DET line on the HDMI connector to the Tegra 250 HDMI INT N interrupt pin The DDC interface is shared between HDMI and the VGA interface so only one of these displays can be connected at a time A standard 15 pin VGA connector J12 is also provided and supports resolutions up to 1600x1200 The Tegra 200 Series Developer Board also supports detection of a VGA device connection This uses the Tegra 250 pin SPI2 SCK on the Audio block 2 7 Audio The Tegra 200 Series Developer Board integrates the Wolfson Microelectronics WM8903 Ultra Low Power CODEC for Portable Audio Applications The Tegra 250 DAP1 interface supporting I2S protocol communicates audio data to from the CODEC GEN1_I2C is used for CODEC configuration The audio subsystem features Leftand Right amplified speaker output via two Wolfson WM9001 amplifiers Headers for connecting Left J11 Right J21 speakers Stereo headphone jack J1 Both internal Microphone J8 and external microphone jack J2 2 8 USB The Tegra 250 has three available
31. on and or software development Figure 1 Example Smartbook Development System Block Diagram Tegra 250 To Pephenis E Togra 2 ais hot Fom PMU VDDIO AUDIO po 18V VDDIG OSC 18V EE contos VoDIO sys aM voio sys nternal Mio aM torai Bank Senay r3 J a rave ricB Tata Sors Grau kec 1e gt K r SMSC MEC1308 3 Mg Embedsed voDIO_ DOR 8 volo Vi Bw VDDIO_NAND GM AVDD USB ere jS USB Mini B oy FAP connector VODIO UART am 7 z 10 100 ridge UEUPIGCLA Lcpmem Ememet VDDIO Lco am HWSYNC HUB amp AVDD USE ETH DDC EV Tol gt G3 SMSC LAN9514 AVDD VDAG G3 AVDD HDMI 6M AVOD HOMLPLL Lad 00 PCHEYAP2OPEX 2 0 VDDIO PEX 105 amp 33V vooo vi G35 PCHE AP20PEX 1 VODIC RUDIO 24MH VDDIO UART 18V Ed SMS m o ERES AVDGDSI vovio BB 5 CSI 12V am gt vDo SYS NODI UART x VODIO_UART E HART 2S DARN GPIOS VBDIG AUDIO 8 UAR APM GPS DG 04927 001 v01 Advance Information Subject to Change 5 NVIDIA CONFIDENTIAL nVIDIA 2 0 DEVELOPER BOARD OVERVIEW 2 1 Feature List Applications Processor NVIDIA Tegra 250 23x23mm 0 8mm pitch DRAM and Flash Memory 8 128Mx8 DDR2 333MHz TPS51116RGET DDR2 Buck Regulator Hynix 8 bit
32. posite each other on each side of the PCB The exception is the DDR2 devices which need to be located opposite each other in an 8 device design for signal integrity reasons Provide airflow to help remove trapped heat for either side of the PCB where hot components are located Possibly providing extra room x y and z around hot components to help with airflow Use some type of metal heat spreader to help dissipate some of the heat from especially hot components This could be an additional piece of metal or having the case bottom of PCB or keyboard plate top of PCB contact the hotter components Figure 29 Considerations for resolving for thermal hot spots Optional metal plate possibly part of keypad assy to act as heat spreader This would contact major heat generating components on PCB top to improve heat dissapation Metal Chasis Space under critical hotter components on PCB Bottom and unblocked airflow paths Possibly vent holes in PCB to allow trapped heat out of confined areas Chassis risers could also provide heat spreader function for hot components on bottom of PCB DG 04927 001 v01 Advance Information Subject to Change 40 NVIDIA CONFIDENTIAL Notice ALL NVIDIA DESIGN SPECIFICATIONS REFERENCE BOARDS FILES DRAWINGS DIAGNOSTICS LISTS AND OTHER DOCUMENTS TOGETHER AND SEPARATELY MATERIALS ARE BEING PROVIDED AS IS NVIDIA MAKES NO WARRANTIES EXPRESSED IMPLIED STATUTORY OR OTHERWISE WITH RESPECT
33. ption If any of these pins are not used either as their primary function or as a GPIO if available they can be left unconnected DG 04927 001 v01 Advance Information Subject to Change NVIDIA CONFIDENTIAL j G Tegra 200 Series Developer Board User Guide AVIDIA 4 2 Clocks The Tegra 250 has a large number of internal functional blocks supporting a broad range of interfaces Each of these has its own clocking requirements The RTC Real Time Clock and PMC Power Management Controller require a 32 768KHz clock to be provided externally In addition a higher frequency reference clock OSC is required This can come from a crystal or an external source and feeds several integrated PLLs that provide a variety of clocking options for the core and I O blocks The Tegra 250 clocking scheme is shown in Figure 8 Figure 8 Tegra 250 Clocking Block Diagram Clock sources for internal core amp UF blocks Ti 120R 100MHz AVDD_OSC avp AVDD PLLA P C AVDD PLLX AVDD PLLM AVDD PLLU also powers PLLD Hr 105v D AVDD PLLE Gus PLL S PLL LF 4 2 1 32 768KHz Clock The 32 768KHz clock is provided externally by the PMU This clock is input on the CLK 32K IN pin which is referenced to the VDDIO SYS rail See the Tegra 200 Series Datasheet Electrical Mechanical and Thermal Specifications for details on the requirements for this clock 4 2 2 Oscillator C
34. r on Figure 12 Force Recovery Connections VDDIO NAND ForceRecovery Button SORGIDOMHZ ES TTA pe ol BH USB Type Mini B 4 5 2 ULPI The Tegra 250 optionally supports ULPI UMTI Low Pin Interface as an option to connect to external USB PHYs or other compatible devices 12 bit interface including ULPI_CLK ULPI DIR ULPI_NXT ULPI_STP and ULPI_DAT 7 0 Operates from 60 MHz clock 8 bit SDR data interface 4 bit DDR data I F not supported Figure 13 shows the Tegra 250 interfacing with an external ULPI USB PHY The USB PHY can be used to interface to a compatible Baseband a USB Hub etc Figure 13 Example ULPI connection to External SMSC USB3317 USB PHY SMSC USB3315 ULPI PHY ULPI DIR S sis ULPI NXT DG 04927 001 v01 Advance Information Subject to Change 25 NVIDIA CONFIDENTIAL nVIDIA Tegra 200 Series Developer Board User Guide Table 8 ULPI Pinout Signal Pin Signal Pin ULPI_CLK M2 ULPI_DATA2 N4 ULPI_DIR M3 ULPI_DATA3 B ULPL_NXT ML ULPI_DATA4 14 ULPI STP P3 ULPI DATAS 16 ULPI DATAO P4 ULPI DATAG P5 ULPI_DATAL P6 ULPI_DATA7 N6 4 5 3 PCle The remaining two downstream USB interfaces on the Tegra 200 Series Developer Board are each routed to one of the Mini PCle connectors shown One use for Mini PCle is to support compatible Baseband mod
35. rator and charge enable pin TI bq24745 For a detailed description and list of device features see http focus ti com lit ds symlink bq24745 pdf 4 1 1 3 Battery Pack Not Included The Tegra 200 Series Developer Board can be used with a 3 cell 381P Lithium ion battery pack that has a nominal voltage of 10 8 volts and a total capacity of 2200mAh The 3S1P is ideal for applications that can operate on lower voltages 4 1 1 4 External Switchers LDOs Power Switches The Tegra 200 Series Developer Board includes the following components Notebook System Power Controller Tl TPS51220 a dual synchronous buck regulator controller with 2 LDOs For a detailed description and list of device features see http focus ti com lit ds symlink tps51220 pdf DDR2 Memory Power Supply TI TPS51116 provides a power supply for the DDR2memory system For a detailed description and list of device features see http focus ti com lit ds symlink tps51 116 pdf 350mA Low Dropout Linear Regulator Tl TPS72012 for a detailed description and list of device features see http focus ti com lit ds symlink tps7 2012 pdf Step Down Converter TI TPS62290 synchronous step down dc dc converter optimized for battery powered portable devices For a detailed description and list of device features see http focus ti com lit ds symlink tps62290 pdf 135 mQ Dual Power Distribution Switch TI TPS2052 for a detailed description and list of device featur
36. rocessing Acceleration with ISP MPEG 4 H264 JPEG Encoder Note For more information on Tegra 250 refer to the Tegra 200 Series Datasheet Electrical Mechanical and Thermal Specifications and the Design Guide 2 3 System DRAM The Tegra 200 Series Developer Board has 8 DDR2 128M x 8 devices for 1GB total system DRAM The DDR2 will operate up to 333MHz for a peak bandwidth of 2 7GB s The memory is arranged as one or two 32 bit Ranks Each Rank uses a different Chip Select and Clock Enable For low power operation with memory retention self refresh is supported 2 4 Boot Device A 4Gb 512MB Hynix HY27UF084G2BTPCB 8 bit NAND is available for use as the boot device In addition an internal 4 bit SD 8 bit MMC socket J26 is provided to support other flash memories 0 Advance Information Subject to Change 8 NVIDIA CONFIDENTIAL q G Tegra 200 Series Developer Board User Guide NVIDIA 2 5 LCD Interface The Smartbook Development System routes an 18 bit parallel RGB interface from the Tegra 250 to a Texas Instruments SN75LVDS83B LVDS Transmitter which goes to an LVDS panel connector J7 The connector is a Foxconn GS13307 11230 TF The controls available for the panel and backlight include Panel power provided by main 3 3V Buck regulator and enabled by the Tegra 250 GPIO on LCD PWR2 EN VDD PNL Backlight enable controlled by the Tegra 250 GPIO on pin SDIO3 DAT2 SDIO block Backlight PWM co
37. s to PWR I2C Programmable over under temperature limits Debug Options The Tegra 200 Series Developer Board provides development debugging interfaces including JTAG UART and Ethernet The Tegra Debug Module E1173 interfaces to the Tegra 200 Series Developer Board using the expansion headers This board provides AUART interface through a RS232 DB9 serial connector intended for software test and debug Remote POWER RESET and FORCE RECOVERY buttons A Adds a coin cell battery for uninterrupted Real Time Clock operation when the developer board is powered off 2 14 Power Power Source Battery 3 Cell Li lon 24WHr 11 1V Nominal AC DC Adapter TopMagnetics HK HW30 A15 15 30W 100V 240V operation Battery Charge Controller Texas Instruments BQ24745RHDR PMU Texas Instruments TPS658621AZGUR Dedicated DC DCs Main system 3 3V and 5V rails Texas Instruments TPS51220ARTVT Main system 1 8V Texas Instruments TPS51116RGER PCle 1 05V for the Tegra 250 Texas Instruments TPS62290DRVR External LDOs 12V Texas Instruments TPS72012YZUT 1 5V Texas Instruments TPS74201RGWR Advance Information Subject to Change 11 NVIDIA CONFIDENTIAL 3 Tegra 200 Series Developer Board User Guide nVIDIA 3 0 SATELLITE BOARD HEADERS Two dual row 50 pin expansion headers enable the ability to connect a satellite board to the Tegra 200 Series Developer Board and are used to extend developer board functionality
38. sirable These should be placed as close as possible to the respective power pins In addition for the higher power higher frequency I O rails one or more 4 7uf bulk capacitor is recommended and should be placed in the general area of the power and interface pins Table 5 Power Supply Capacitor Recommendations for Tegra 250 Supplies Tegra 200 Series Developer Board User Guide Power Rail 0 1uF Bypass 4 TuF Bulk Power Rail 0 1uF Bypass 4 TuF Bulk Capacitors Capacitors Capacitors Capacitors Cores VDD CORE 3 2 VDD_CPU 3 VDD_RTC 1 Note 1 AVDD PLLA 4 1 5 Unused Interface Power Rails C AVDD_PLLM AVDD_PLLU AVDD PLLX The example also assumes that all the interfaces are to be used If a design does not use any functions on one or more of the interface blocks the associated power rail does not need to be powered For the correct handling of each of the rails in this case check the Unused Pin section under for the interface in this document Generally unused digital power rails can be left unconnected or tied to ground while unused analog rails should be left unconnected 4 1 6 Unused Power Management Signals A few of the signals related to power management may not be required in some designs This includes SYS CLK REQ and CLK 32K OUT If not required these pins can be configured as GPIOs instead CORE PWR REQ may also not be needed in all designs but this pin does not have a GPIO o
39. tional debug connector providing access to several debugging interfaces can be added to a design possibly in the early stages and removed for production One option is the Debug connector shown in Figure 24 This connector is used with the E1137 Combo Debug Board This board interfaces to the Tegra 200 Series Developer Board Debug connector J10 using a flex cable The Combo board provides RS 232 interface on a DB 9 connector which uses UART1 on the Tegra 250 Standard 20 pin 0 1 JTAG header Can be used with standard ARM software development debugging hardware Provides low level access to the CPUs and AVP Ethernet RJ 45 jack by means of a SPI Ethernet controller using the Tegra 250 SP11 interface Note that in the circuit in Figure 24 there is an optional resistor on JTAG TRST N For normal JTAG operation this resistor should not be present The JTAG_TRST_N pin on the Tegra 250 selects whether the JTAG interface is to be used for communicating with the Tegra 250 CPU complex or for Test Scan purposes When JTAG TRST Nis pulled low the JTAG interface is enabled for access to the CPU complex When high it is in Test Scan mode When used in the normal operating mode to access the internal CPUs in order to reset the Tegra 250 JTAG block a reset command is used rather than toggling the JTAG TRST N pin DG 04927 001 v01 Advance Information Subject to Change 35 NVIDIA CONFIDENTIAL 3 Tegra 200 Series Developer Board User Guide
40. ton Button Headers on 08 it 8 S2 3 WHEE Figure 3 Tegra 200 Series Developer Board Bottom View wis On T yal E jF DEDE Us ae Ty iur Ad e Hub LVDS Trans OK Switch DG 04927 001 v01 Advance Information Subject to Change NVIDIA CONFIDENTIAL per Board Use nVIDIA 2 2 NVIDIA Tegra 250 The NVIDIA Tegra 250 computer on a chip is suited for handheld and mobile applications It s primary purpose is to control all system peripherals and provide computing power Table 1 Features Available Used on Tegra 200 Series Developer Board CPU Dual core ARM Cortex A9 MPCore processor External Memory Support 32 bit 333MHz DDR2 SDRAM to 1GB 2chip selects Advanced Power Management Dynamic voltage and frequency scaling Multiple clock and power domains Independent gating of power domains 2D 3D acceleration Integrated Open GLES 2 0 3D core Connectivity and Expansion SPI Qty 1 I2C Qty 3 UART Qty 2 I2S PCM Qty 2 ULPI HS USB 2 0 HS Qty 3 SDIO Qty 3 Storage Internal 4 bit SD 8 bit MMC o eMMC compatible module available External 4 bit MMC SD Multimedia Support Dual Display Integrated LCD external 18 bit LVDS LCD HDMI to 1080p and VGA Camera CSI Pre Post P
41. tuning and testing An external antenna for 2 4GHz available off the shelf is also required The 802 11b g transceiver sends and receives on a 2 4GHz line at 54Mbps max It provides full QoS for 802 11e and security support 802 11i and co exists with the Bluetooth device The interface of choice is SDIO This interface will be implemented on a LTCC substrate supplied by MuRata and soldered down to our board to minimize tuning and testing An external antenna supporting both Bluetooth and WiFi for 2 4GHz available off the shelf is required and available from a variety of suppliers PCle Mini Card 3G Modem support and more The Tegra 200 Series Developer Board provides two PCle Mini Card slots Both slots support PCle operation as well as USB 2 0 High Speed Slot 0 J27 also routes to a UIM SIM socket J19 and is intended to support compatible 3G Modem modules PCle Mini Card slot 1 J28 could be used for other peripherals such as Solid State drives or a different WiFi solution Note Contact NVIDIA for list of certified PCI express peripherals Advance Information Subject to Change 10 NVIDIA CONFIDENTIAL G Tegra 200 Series Developer Board User Guide NVIDIA 2 12 User Interface Attach your USB keyboard and mouse to any of the available USB Type A Host ports J6 J25 2 13 Miscellaneous Temperature Sensor On Semiconductor Model ADT7461AARMZ_RL7 0 25 C resolution 1 C accuracy remote channel used Interface
42. ules currently using the USB interface portion of Mini PCle A SIM socket is provided off one of the PCle Mini Card connectors for this purpose Other peripherals such as Solid State drives or Wi Fi may also take advantage of the high performance PCle interfaces on the PCle Mini Card connectors Contact NVIDIA for a list of certified PCI express peripherals Figure 14 Example LAN9514 USB Ethernet Hub and Dual Mini PCle Connectors DG 04927 00 33v Tegra Optional 2 PCle MiniCard PEX WAKEN USB DN USB DP PEXRSTON AP SMB SDA AP SMB SCL THT PEX RSTI N sav VDDIO UART AP SMB SCL AP SMB SDA 4 v0t Advance Information Subject to Change NVIDIA CONFIDENTIAL USB DN USB DP rerum 26 e nVIDIA Table 9 PCle Pinout oper Board User Gui Signal Pin Signal Pin PEX CLK OUTI N ACA PEX L1 TXN AC2 PEX CLK OUTI P AD4 PEX_L1_TXP ACL PEX_CLK_OUT2_N Y4 PEX_L2_RXN v4 PEX_CLK_OUT2_P Y5 PEX_L2_RXP v3 PEX_LO_RXN AAS PEX_L2_TXN AAL PEX_LO_RXP AM PEX L2 TXP AA2 PEX LO TXN ADL PEX_L3_RXN v6 PEX LO TXP AD2 PEX L3 RXP vs PEX L1 RXN AA7 PEX_L3_TXN Y3 PEX_L1_RXP AAG PEX_L3_TXP Ya 4 6 Display LCD Displays HDMI VGA CRT SDTV HDTV Out 4 6 1 LCD Displays The Tegra 250 supports a broad range of interfaces for connecting to LCD displays Two separate display controllers can drive up to two
43. variety of flash memory devices The Tegra 200 Series Developer Board uses a combination 4 bit SD MMC and 8 bit MMC socket to support either standard SD MMC cards or proprietary modules with eMMC embedded MMC or other compatible devices for storage and possibly boot options One available module that can be used with this socket supports eMMC The example in Figure 21 shows a connection example that will work with the eMMC module as both the boot and mass storage device Figure 21 Tegra 200 Series Developer Board Reference design 4 8 bit Captive SD MMC Card Socket Connection Example VDDIO_NAND iii HSMMC DATA HSMMC DATS HSMMC DATZ HSMMC DATS HSMMC CMD HSMMC CLK HSMMC_DATO HSMMC DATT HSMMC DATS HSMMG_DAT7 The Tegra 200 Series Developer Board uses this socket to as an internal means to support assorted boolistorage devices including eMMC This header is included to provide a core supply to an IMC module Not needed if MMC or other device directly on board Chant cor 2051 GPIO PH2 HSMMC CD N GPIO FH3 HSMMC WP sav DG 04927 001_v01 Advance Information Subject to Change 33 NVIDIA CONFIDENTIAL Tegra 200 Series Developer Board User Guide AVIDIA 4 8 3 SDIO Device Connections An SDIO controller is often used to interface to medium bandwidth peripherals such as a Wi F
44. y design using these components must ensure each of these devices do not exceed the maximum temperature This may require careful board and mechanical design practices to accommodate various contributors to heat generation Table 15 Major Component Thermal Specifications Device Definition Min Max Units Notes Overall System Operating temperature ambient 0 50 oc 1 Tegra 250 Operating Case Temperature 25 85 oc Hynix HY5PS1G831CLFP DDR2 Operating Case Temperature 30 85 oc Hynix HY27UF084G2B TPCB NAND Operating Case Temperature 0 70 so Wolfson WM8903 Audio Codec Operating Case Temperature 40 85 c TI TPS658621AZGUR PMU Operating Case temperature 40 85 c SMSC MEC1308 Embedded Controller Operating Case Temperature 0 70 c SMSC LAN9514 USB Hub and Ethernet Operating Case Temperature 0 70 c SMSC USB3315 ULPI Phy Operating Case Temperature 40 85 3c TI SN75LVDS83B LVDS Transmitter Operating Case Temperature 10 70 3 Note 1 Design specific Rating shown is typical for many mobile computing designs 5 2 Thermal Considerations for Components Figure 27 and Figure 28 show the top and bottom of the Tegra 200 Series Developer Board The components that either generate heat or may be very sensitive to temperature are highlighted with different colors Green Adversely sensitive to heat Yellow Mild contributor to heat generation LtOrange Medium contributor to heat ge
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