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Motorola MC9S12C-Family User's Manual

1. Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 CAN Motorola Scalable CAN MSCAN Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 RXFRM LEAST CSWAI SHOE TIME WUPE SLPRQ INITRQ CANE CLKSRC LOOPB LISTEN 0 WUPM SLP QUIA SJW1 SJWO BRP5 BRP4 BRP3 BRP2 BRP1 BRPO SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 WUPIF CSCIF RSTAT1 RSTATO TSTAT1 TSTATO OVRIE RXF WUPIE CSCIE RSTATE1 RSTATEO TSTATE1 TSTATEO OVRIE RXFIE 9 s TXE2 TXE1 TXEO TXEIE2 TXEIE1 TXEIEO 2 g 0 ABTRQ2 ABTRQ1 ABTRQO 0 0 0 0 0 ABTAK2 ABTAK1 ABTAKO 0 2 0 TX2 TX1 TXO 0 0 DAMI IDAMO 0 IDHIT2 IDHIT1 IDHITO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45 Device User Guide 9512C128DGV1 D V01 05 0140 017F CAN Motorola Scalable CAN MSCAN Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SOME CANRXERR naag RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERRO 014F CANTXERR ka TXERR7 TXERRe TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERRO 0150 CANIDARO Read 0153 CANIDAR3 Write 0154 CANIDMRO Read 0157 CANIDMR3 Write 0158 CANIDAR4 Read 015B CANIDAR7 Write 015C CANIDMR4 Read 015F CANIDMR7 Write AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO AC7 ACE
2. 00 0055 96 B3 OUIDURLOAdS pa 52 cio DA Eod AU ea meek hee Rp a ete d 96 B 3 1 RESISUIVO QS p E AA PK Ja ean AA deeds 96 B 3 2 Capacitive Loads duas asd ee Sante dia bd ER AA 97 BA ATO Characi ristics nte bad BEDA AA eens soda DRE RS 99 B 4 1 ATD Operating Characteristics In 5V Range a 99 B 4 2 ATD Operating Characteristics In 3 3V Range a 99 B 4 3 Factors influencing accuracy bose vk Amex SM EC kaa pA xs 100 B 4 4 ATO accuracy DV Rang wb toes eee ia 102 B 4 5 ATD accuracy 3 3V Range 2c cece eee es 102 B5 NWM Flash and EEPROM scsi iit esa north Er o rts 105 B 5 1 A Me UTE MEER NUR 105 B 5 2 NVM Tellablliy t costas tr RE ri tae a 106 6 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 B6 Reset Osoillator and Puke ente t nel aae bct redox cfe ta e KA ka Tenuta 109 B 6 1 co jts LA E LE ETE 109 B 6 2 SCN AO eu aos etii ia NADA ts aio Dy dar dps Ody Ros o ed AN 110 B 6 3 Phase Locked LOON sS oni E A ee aa haan am abay Ur pde UR 111 BE MOSOAN U ese duni Ed n E aged a APA 117 Ba SEI co corsa cd rr a PE bon E Deed C que ed 119 Appendix C Electrical Specifications Cs Master Mod cud NA ERES PR E RE ate a 119 Cue Slave Mode uade ee ork Se oil Bua e SE Rd err bb 121 C3 tExtemal BUS TIMING c ss n iocus ceste oat hr AA a E aE 123 C 3 1 General Mixed Bus TIMING s 254 200x KEEP TABA RA PER RE RUE RET 123 Appendix D Package Information Dd Renca aren e voL pede
3. Table of Contents Section 1 Introduction a aKo n 23 Wee RA 23 1 3 Modes of Operations 2E ae sies SU oe e Ib baal Cao bA BAOG by REM ATA SB s AE UR 25 BA bo BE LG Sus 50578 eo avc Apt A aue es usted 27 1 5 Device Memory Map cs ee ees e P EN ee ga RM nds 28 1 6 Detailed Register Map Ecs desto Eee PRO Y np DOLI a ee eRe eee epp 33 1 7 Rant ASSIGnMei sensed eh ees xe ex erede de eee WERE grid ere bet UR IRAN 50 Section 2 Signal Description 2 1 Device PINOUT Los o ds nerd d deduci EE e el Ead oi Eit aee eed E ad tee 52 2a gh Properties SUMA screen eee tee A A EDI 55 2 2 1 Pin Initialization for 48 amp 52 Pin LQFP bond out versions 56 2 3 Detailed Signal Descriptions soria ae mm e A 57 2 3 1 EXTAL XTAL Oscillator PINS Gs ed ARKA se GRECE X RR ETE CC RO a 57 2 3 2 RESET External R set Pin 2 2221002 nebhet tiae daua ia APRERRERSS 57 2 3 3 TESTA VPP TES Pag gaina ha robo Da E E aa i a Wear bct gc 57 2 3 4 XFO PLL Loop Filter PN astra ei mhi sese da aai EIE aiie a ar 57 2 3 5 BKGD TAGHI MODC Background Debug Tag High amp Mode Pin 58 2 3 6 PA 7 0 ADDR 15 8 DATA 15 8 Port A I O Pins 58 2 3 7 PB 7 0 ADDR 7 0 DATA 7 0 Port B I O Pins aa 58 2 3 8 PE7 NOACC XCLKS Port E VO Pin7 a 58 2 3 9 PE6 MODB IPIPE1 Port E V O Pin6 eee 60 2 3 10 PES MODA IPIPE0 Port E VO PINS aiu See daa tcs cis 60 2 3
4. The following constraints exist to obtain full scale full range results VSSA VRL lt VIN VRH lt VDDA This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to If the input level goes outside of this range it will effectively be clipped Table B 3 ATD Operating Characteristics Conditions are shown in Table A 4 unless otherwise noted Supply Voltage 5V 1096 lt Vppa lt 5V 10 Rating Symbol Min Max Reference Potential VRL VSSA VDDA 2 VRH VDDA 2 VDDA Differential Reference Voltage VRH VRL 4 75 5 25 ATD Clock Frequency f 0 5 2 0 ATDCLK ATD 10 Bit Conversion Period Clock Cycles NcoNv10 28 Conv Time at 2 0MHz ATD Clock farpcik Tconvio 14 ATD 8 Bit Conversion Period Clock Cycles Nconvio 26 Conv Time at 2 0MHz ATD Clock farpcik TeoNv1o 13 us Cycles us Reference Supply current 0 375 1 Full accuracy is not guaranteed when differential voltage is less than 4 75V 2 The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks Recovery Time VppA 5 0 Volts B 4 2 ATD Operating Characteristics In 3 3V Range The Table B 3 shows conditions under which the ATD operates The following constraints exist to obtain full scale full range results VssA VRL lt Vin Vry Vppa This constraint exists since the sample buffer amplifier ca
5. 1 deviation from target frequency 2 fosc 4MHZ fgus 25MHz equivalent fyco 50MHz REFDV 03 SYNR 018 Cs 4 7nF Cp 470pF Rs 10KQ AR MOTOROLA 115 Device User Guide 9512C128DGV1 D V01 05 116 M MOTOROLA Device User Guide 9512C128DGV1 D V01 05 B 7 MSCAN Table B 13 MSCAN Wake up Pulse Characteristics Conditions are shown in Table A 4 unless otherwise noted P MSCAN Wake up dominant pulse pass AR MOTOROLA 117 Device User Guide 9512C128DGV1 D V01 05 118 M MOTOROLA Device User Guide 9512C128DGV1 D V01 05 B 8 SPI Appendix C Electrical Specifications This section provides electrical parametrics and ratings for the SPI In Table C 1 the measurement conditions are listed Table C 1 Measurement Conditions Description Value Unit Drive mode full drive mode L it C oad capacitance C gap 50 pF on all outputs Thresholds for delay 20 80 VDDX V measurement points C 1 Master Mode In Figure C 1 the timing diagram for master mode with transmission format CPHA 0 is depicted ss OUTPUT POL O MA 2 OUTPUT 4 CPOL 1 OUTPUT D MISO INPUT 7 MOSI OUTPUT Y MSB OUT BIT6 1 LSB OUT N 1 if configured as an output 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB Figure C 1 SPI Master Timing CPHA 0 In Figure C 2 the t
6. I Bit I Bit Reserved CANRIER RXFIE CANTIER TXEIE 2 0 B2 BO FF90 to FFAF FF8E FF8F FF8C FF8D PWM Emergency Shutdown I Bit Port P VREG LVI I Bit I Bit PIEP PIEP7 0 PWMSDN PWMIE CTRLO LVIE 8E 8C 8A FF8A FF8B FF80 to FF89 NOTES 1 Not available on MC9S12GC Family members 5 3 Resets Reserved Resets are a subset of the interrupts featured inTable 5 1 The different sources capable of generating a system reset are summarized in Table 5 2 When a reset occurs MCU registers and control bits are AR MOTOROLA 69 Device User Guide 9512C128DGV1 D V01 05 changed to known start up states Refer to the respective module Block User Guides for register reset states 5 3 1 Reset Summary Table Table 5 2 Reset Summary Reset Priority Source Vector Power on Reset 1 CRG Module SFFFE SFFFF Low Voltage Reset SFFFE SFFFF Clock Monitor Reset 2 CRG Module SFFFC SFFFD COP Watchdog Reset SFFFA SFFFB 5 3 2 Effects of Reset When a reset occurs MCU registers and control bits are changed to known start up states Refer to the respective module Block User Guides for register reset states Refer to the HCS12 Multiplexed External Bus Interface MEBI Block Guide for mode dependent pin configuration of port A B and E out of reset Refer to the PIM Block User Guide for reset configurations of all peripheral module ports Refer to Figure 1 2
7. See PLL specification chapter PLL loop filter capacitor Colpitts mode only if recommended by DC cutoff capacitor quartz manufacturer PLL loop filter resistor See PLL Specification chapter PLL loop filter resistor Pierce mode only PLL loop filter resistor NOTES 1 In 48LQFP and 52LQFP package versions VDD2 is not available Thus 470nF must be connected to VDD1 AR MOTOROLA 73 Device User Guide 9512C128DGV1 D V01 05 Note Oscillator in Colpitts mode Figure 8 1 Recommended PCB Layout 48 LQFP 74 AR MOTOROLA AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 NOTE Oscillator in Colpitts mode Figure 8 2 Recommended PCB Layout 52 LQFP 75 Device User Guide 9512C128DGV1 D V01 05 NOTE Oscillator in Colpitts mode Figure 8 3 Recommended PCB Layout 80 QFP 76 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Figure 8 4 Recommended PCB Layout for 48 LQFP Pierce Oscillator AR MOTOROLA 77 Device User Guide 9512C128DGV1 D V01 05 lt O O o g VSSX VSSA M C3 VDDA VDD1 C1 VSS1 VSSR O a e R2 VDDR Q1 O o O O co M dl te VDDPLL R1 Figure 8 5 Recommended PCB Layout for 52 LQFP Pierce Oscillator 78 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Figure 8 6 Recommended PCB Layout for 80QFP Pierce Oscillator Section 9 Clock Reset Generat
8. VDDX VSSX PMO RXCAN PM1 TXCAN PM2 MISO PM3 SS PP6 KWP6 ROMCTL PM4 MOSI PM5 SCK PJ6 KWJ6 68 HH PJ7IKWJ7 MC9S12C Family MC9S12GC Family 19 a a 2 E a 15 tc a a lt o mm co cn Lu a a A rc EE aag Om tc tcc aas 295 IAN MODB IPIPE1 PE6 MODAI IPIPE0 PE5 TEST VPP LSTRB TAGLO PE3 R W PE2 IRQ PE1 Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52 but not the 48 Pin Package XIRQ PEO VRH VDDA PADO7 A PADO6 A PADOS A PADO4 A PADOS A PADO2 A PADO1 ANO1 PADOO A VSS2 VDD2 PA7 ADDR15 DATA15 PAG ADDR14 DATA14 PA5 ADDR13 DATA13 PA4 ADDR12 DATA12 PA3 ADDR11 DATA11 PA2 ADDR10 DATA10 PA1 ADDR9 DATA9 PAO ADDR8 DATAS Figure 2 1 Pin Assignments in 80 QFP for MC9S12C Family AR MOTOROLA PW3 KWP3 PP3 PWO IOCO PTO PW1 10C1 PT1 PW2 10C2 PT2 PW3 10C3 PT3 VDD1 VSS1 PW4 10C4 PT4 lOC5 PT5 lOC6 PT6 lOC7 PT7 MODC BKGD PB4 Figure 2 2 Pin assignments in 52 LQFP for MC9S12C Family AR MOTOROLA PP4 KWP4 PW4 PP5 KWP5 PW5 VDDX VSSX PMO RXCAN PM1 TXCAN PM2 MISO PM3 SS PM4 MOSI PM5 SCK PS1 TXD PSO RXD Device User Guide 9512C128DGV1 D V01 05 MC9S12C Family MC9S12GC Family r t r Of 4 cote T E C O o n o pag S lt gt ul ae 09 e x gt let e c t 30 gt gt o ui x XTAL TEST VPP IRQ PE1 XIRQ PEO VRH VDDA PADO7 ANO
9. 0 018 0 030 F G 0 65 BSC 0 026 BSC J 007 0 20 0 003 0 008 K 0 50 REF 0 020 REF R1 S 12 00 BSC 0 472 BSC S1 6 00 BSC 0 236 BSC u 009 0 16 0 004 0 006 V vi 6 00 BSC 0 236 BSC Ww 0 20 REF 0 008 REF Z 1 00 REF 0 039 REF e 09 72 oe 70 01 09 0 En 29 REF 129 RE 03 129 REF 129 REF Figure D 2 52 pin LQFP Mechanical Dimensions case no 848D 03 AR MOTOROLA 129 Device User Guide 9512C128DGV1 D V01 05 D 4 48 pin LQFP package NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y 14 5M 1994 DETAIL Y 1 CONTROLLING DIMENSION MILLIMETER 2 DATUM PLANE AB IS LOCATED AT BOTTOM P te OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE 3 DATUMST U ANDZ TO BE DETERMINED AT DATUM PLANE AB 4 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC 5 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 250 PER SIDE DIMENSIONS A ANDB DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB 6 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 4X ic paper AE AE 0 350 7 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0 0076 8 AEXACT SHAPE OF EACH CORNER IS PTIONAL MILLIMET
10. C 85 C 52LQFP 25MHz Final GC64 using GC64 die MC9S12GC64CFU25 TBD 40 C 85 C 80QFP 25MHz Final GC64 using GC64 die MC9S12GC64PVFA25 OLO9S 40 C 105 C 48LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PVPB25 OLO9S 40 C 105 C 52LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PVFU25 OLO9S 40 C 105 C 80QFP 25MHz Preliminary GC64 using C128 die MC9S12GC64VFA25 TBD 40 C 105 C 48LQFP 25MHz Final GC64 using GC64 die MC9S12GC64VPB25 TBD 40 0 105 C 52LQFP 25MHz Final GC64 using GC64 die MC9S12GC64VFU25 TBD 40 C 105 C 80QFP 25MHz Final GC64 using GC64 die MC9S12GC64PMFA25 OLO9S 40 0 125 C 48LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PMPB25 OLO9S 40 C 125 C 52LQFP 25MHz Preliminary GC64 using C128 die MC9512GC64PMFU25 OLO9S 40 C 125 C 80QFP 25MHz Preliminary GC64 using C128 die MC9S12GC64MFA25 TBD 40 125 C 48LQFP 25MHz Final GC64 using GC64 die MC9S12GC64MPB25 TBD 40 C 125 C 52LQFP 25MHz Final GC64 using GC64 die MC9512GC64MFU25 TBD 40 C 125 C 80QFP 25MHz Final GC64 using GC64 die MC9S12GC32PCFA25 1L45J 40 C 85 C 48LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PCPB25 1L45J 40 C 85 C 52LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PCFU25 1L45J 40 C 85 C 80QFP 25MHz Preliminary GC32 using C32 die MC9S12GC32CFA25 TBD 40 C 85 C 48LQFP 25MHz Final GC32 using GC32 die MC9S12GC32CPB25 TBD 40 C 85 C 52LQFP 25MHz Final GC32 using GC32 die
11. CRI CRO FORBYP Read 0 0 0 0 0030 ESTONG Wag ATIBYP COPBYP PLLBYP FCM gouge CTOTL Read TCTL7 TCTLe TCTLS TCTL TCLTS TCTL2 TOTLI TCTLO TESTONLY Write Read 0 0 0 0 0 0 0 0 MR ARMCOR pis SBT 6 5 4 3 2 1 Bit 0 0040 006F TIM Timer 16 Bit 8 Channels Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0040 TIOS A los7 lose loss IOS4 los3 10s2 lost loso Read 0 0 0 0 0 0 0 0 0041 CFORC Write FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOCO 0042 OC7M hes OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7MO 0043 OC7D ber OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7Di OC7DO Read Bit 15 14 13 12 11 10 9 Bit 8 0044 TONT N Ato Read Bit 7 6 5 4 3 2 1 Bit 0 0045 TONT O y an 0046 TSCR1 bie TEN TSWAI TSFRZ TFFCA i o 0047 TTOV Ha Tov7 Tove tovs TOV4 TOV3 Tove tovi TOVO 0048 TCTL1 bt om7 OL7 ome o om5 o5 om OL4 Read 0049 TCTL yael OM3 OL3 OM OL OM1 OL1 OMO OLO 004A TCTL3 hek EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 004B TCTL4 WE EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDGOB EDGOA 004C TIE Naa C71 C6l Cs Cal cal cal cil col 004D TSCR2 NG TOI D TCRE PR2 PRI PRO Read SOME TFLG1 Wo OE C6F C5F C4F C3F C2F CIF COF Read 0 0 0 0 0 0 0 004F TFLG2 Qto TOF 38 AR MOTOROLA Address 0050 0051 0052 0053 0054 0055 0056 0057 0058
12. MC9S12C32VPB16 1L45J 40 C 105 C 52LQFP 16MHz C32 die MC9S12C32VFU16 1L45J 40 C 105 C 80QFP 16MHz C32 die MC9S12C32MFA16 1L45J 40 C 125 C 48LQFP 16MHz C32 die MC9S12C32MPB16 1L45J 40 C 125 C 52LQFP 16MHz C32 die MC9S12C32MFU16 1L45J 40 C 125 C 80QFP 16MHz C32 die MC9S12C32CFA25 1L45J 40 C 85 C 48LQFP 25MHz C32 die MC9512C32CPB25 1L45J 40 C 85 C 52LQFP 25MHz C32 die MC9S12C32CFU25 1L45J 40 C 85 C 80QFP 25MHz C32 die MC9S12C32VFA25 1L45J 40 C 105 C 48LQFP 25MHz C32 die MC9S12C32VPB25 1L45J 40 C 105 C 52LQFP 25MHz C32 die MC9512C32VFU25 1L45J 40 C 105 C 80QFP 25MHz C32 die MC9S12C32MFA25 1L45J 40 C 125 C 48LQFP 25MHz C32 die MC9S12C32MPB25 1L45J 40 C 125 C 52LQFP 25MHz C32 die MC9S12C32MFU25 1L45J 40 C 125 C 80QFP 25MHz C32 die Table 0 4 MC9S12GC Family Part Number Coding Part Number pe Temp Package Speed Description MC9S12GC128PCFA25 OLO9S 40 C 85 C 48LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PCPB25 OLO9S 40 C 85 C 52LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PCFU25 OLO9S 40 C 85 C 80QFP 25MHz Preliminary GC128 using C128 die MC9S12GC128CFA25 TBD 40 C 85 C 48LQFP 25MHz Final GC128 using GC 128 die MC9S12GC128CPB25 TBD 40 C 85 C 52LQFP 25MHz Final GC128 using GC128 die MC9S12GC128CFU25 TBD 40 C 85 C 80QFP 25MHz Final GC128 using GC128 die MC9S12GC128PVFA25 OLO9S 40 C 105 C 48LQFP
13. PIX3 PIX PIX1 PIXO Read O 0 0 0 0 0 0 0 0031 Reserved y mE r 0032 0033 MEBI map 3 of 3 HCS12 Multiplexed External Bus Interface p p Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit Bit 1 Bit 0 s0032 PoRTK Read gu 6 5 4 3 2 1 Bit 0 Write 0053 DpRK Read gi 6 5 4 3 2 1 Bit 0 Write NOTES 1 Only applicable in special emulation only bond outs for emulation of extended memory map 0034 003F CRG Clock and Reset Generator Address Name Bit 7 Bit 6 Bit5 Bit 4 Bit3 Bit Bit 1 Bit 0 0034 SYNR Acie SYN5 SYM SYN3 SYN2 SYN1 SYNO 0035 REFDV Md 0 O REFDV3 REFDV2 REFDV1 REFDVO soe CIFiG Read TOUT7 Tours TOUTS Tours Tours TOUT2 TOUTI TOUTO TESTONLY Write 0037 CRGFLG bos RTIF PROF FOCI LOBE LIA US ce E SUM 0038 cRGNT O REG are LOCKIE SCMIE Write 0039 CLKSEL baa PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI Read 0 009A PLLOTL Ato CME PLLON AUTO aca PRE PCE SCME AR MOTOROLA 37 Device User Guide 9512C128DGV1 D V01 05 0034 003F CRG Clock and Reset Generator Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80038 RTICTL e O eres RTR5 RTR4 RTR3 RTR2 RTRI RTRO 003C COPCTL dnd WCOP RSBCK E J CR2
14. Refer to manufacturer s data Figure 2 6 Pierce Oscillator Connections PE7 0 EXTAL CMOS COMPATIBLE EXTERNAL OSCILLATOR VDDPLL Level MCU XTAL not connected Figure 2 7 External Clock Connections PE7 0 59 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 2 3 9 PE6 MODB IPIPE1 Port E I O Pin 6 PE6 is a general purpose input or output pin It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODB bit at the rising edge of RESET This pin is shared with the instruction queue tracking signal IPIPE1 This pin is an input with a pull down device which is only active when RESET is low PE 6 is not available in the 48 52 pin package versions 2 3 10 PE5 MODA IPIPEO Port E I O Pin 5 PES is a general purpose input or output pin It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODA bit at the rising edge of RESET This pin is shared with the instruction queue tracking signal IPIPEO This pin is an input with a pull down device which is only active when RESET is low This pin is not available in the 48 52 pin package versions 2 3 11 PE4 ECLK Port E I O Pin 4 E Clock Output ECLK is the output connection for the internal bus clock It is used to demultiplex the address and data in expanded modes and is used as a timing reference ECLK frequency is equal to 1 2 the crystal frequency out of reset The
15. case no 841B 128 52 pin LQFP Mechanical Dimensions case no 848D 03 129 Device User Guide 9512C128DGV1 D V01 05 Figure D 3 48 pin LQFP Mechanical Dimensions case no 932 03 ISSUE F Figure 19 1 Pin Assignments in 112 pin LQFP a 131 Figure 19 2 112 pin LQFP mechanical dimensions case no 987 80 pin QFP Mechanical Di mensions case no 841B 133 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 List of Tables Table 0 2 MC9S12C Family Package Option Summary eenaa 15 Table 0 1 List of MC9S12C and MC9S12GC Family members 15 Table 0 3 MC9S12C Family Part Number Coding 002200 eee eee 16 Table 0 4 MC9S12GC Family Part Number Coding a 19 Table 0 5 Document References eee 21 Table 1 1 Device Register Map Overview esee 28 0000 000FMEBI map 1 of 3 HCS12 Multiplexed External Bus Interface 34 0010 0014 MMC map 1 of 4 HCS12 Module Mapping Control 34 0018 0018 Miscellaneous Peripherals Device User Guide 35 0019 0019 VREG3V3 Voltage Regulator 35 0015 0016 INT map 1 of 2 HCS12 Interrupt 35 0017 0017MMC map 2 of 4 HCS12 Module Mapping Control 35 001A 001B Miscellaneous Peripherals Device User Guide 35 001C 001D MMC map 3 of 4 HCS12 Module Mapping Control 36 Device User Guide 36 001E 001E MEBI map 2 of 3 HCS12 Multiplexed External Bus Interface 36 001F 001F IN
16. s J LUI he D M DETAIL C 9 0200 fc as D SECTION B B DATUM VIEW ROTATED 90 a 0 0410 SEATING PLANE M po NOTES MILLIMETERS 7 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 DIM MIN MAX 2 CONTROL LING DIMENSION MILLIMETER A 1390 14 10 3 DATUM PLANE H IS LOCATED AT BOTTOM OF B 1390 1410 LEAD AND IS COINCIDENT WITH THE U LEAD WHERE THE LEAD EXITS THE PLASTIC C 215 245 BODY AT THE BOTTOM OF THE PARTING LINE D 022 0 38 4 DATUMS A B AND D TO BE E 200 240 T DETERMINED AT DATUM PLANE H F 022 1033 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE C G 0 65BSC DATUM H 6 DIMENSIONS A AND B DO NOT INCLUDE H 0 25 PLANE R MOLD PROTRUSION ALLOWABLE J 918 023 PROTRUSIONS 025 PER SIDE DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH K 0 65 095 AND ARE DETERMINED AT DATUM PLANE H L 12 35 REF 7 DIMENSION D DOES NOT INCLUDE DAMBAR MI 50 100 PROTRUSION ALLOWABLE DAMBAR N 17 PROTRUSION SHALL BE 0 08 TOTAL IN 013 0 K EXCESS OF THE D DIMENSION AT MAXIMUM P 0325Bsc Q MATERIAL CONDITION DAMBAR CANNOT al o 7 w BE LOCATED ON THE LOWER RADIUS OR R 013 030 HE FOOT X S 1695 17 45 T 013 DETAIL C U o v 1695 1745 w 035 045 X 1 6 REF Figure D 1 80 pin QFP Mechanical Dimensions case no 841B 128
17. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 lb 2 9 Bit 7 6 5 4 3 Bit 2 2 0 0 0 NOACCE PIPOE NECLK LSTRE RDWE MODC MODB MODA O VIS Q EMK EME PUPKE g PUPEE i i PUPBE PUPAE RDPK 0 i RDPE RDPB RDPA 0 0 0 0 0 0 0 ESTA 0 0 0 0 0 0 0 0 MMC map 1 of 4 HCS12 Module Mapping Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAM15 RAM14 RAM13 RAM12 RAM11 i RAMHAL y REG14 REG13 REG12 REG11 i i Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AR MOTOROLA 0010 0014 Address Name 0012 INITEE 0013 MISC 0014 Reserved 0015 0016 Address Name 0015 ITCR 0016 ITEST 0017 0017 Address 0017 Name Reserved 0018 0018 Address Name 0018 Reserved 0019 0019 Address Name 800199 VREGCTRL 001A 001B Address Name 001A PARTIDH 001B PARTIDL AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 MMC map 1 of 4 HCS12 Module Mapping Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read Geis EEMA REIS SEED EE a me LL EON Write kaa i i 0 EXSTR1 EXSTRO ROMHM ROMON Read 0 0 0 0 0 0 0 0 Write INT map 1 of 2 HCS12 Interrupt Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read 0 0 0 wRINT ADRS ADR2 ADRI ADRO Write Read 3C INTE INTC INTA INT8 INT6 INT4 INT2 INTO Wr
18. 0059 005A 005B 005C 005D 005E 005F 0060 0061 0062 0063 0064 0065 0066 0067 AR MOTOROLA Name TCO hi TCO lo TC1 hi TC1 lo TC2 hi TC2 lo TC3 hi TC3 lo TC4 hi TC4 lo TC5 hi TC5 lo TC6 hi TC6 lo TC7 hi TC7 lo PACTL PAFLG PACNT hi PACNT lo Reserved Reserved Reserved Reserved Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Device User Guide 9512C128DGV1 D V01 05 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 0 PAEN PAMOD PEDGE CLK1 CLKO PAOVI PAI o PAOVF PAIF Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0
19. 25MHz Preliminary GC128 using C128 die MC9S12GC128PVPB25 OLO9S 40 0 105 C 52LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PVFU25 OLO9S 40 C 105 C 80QFP 25MHz Preliminary GC128 using C128 die MC9S12GC128VFA25 TBD 40 C 105 C 48LQFP 25MHz Final GC128 using GC128 die MC9S12GC128VPB25 TBD 40 0 105 C 52LQFP 25MHz Final GC128 using GC128 die MC9S12GC128VFU25 TBD 40 0 105 C 80QFP 25MHz Final GC128 using GC128 die MC9S12GC128PMFA25 OLO9S 40 0 125 C 48LQFP 25MHz Preliminary GC128 using C128 die MC9512GC128PMPB25 OLO9S 40 C 125 C 52LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PMFU25 OLO9S 40 C 125 C 80QFP 25MHz Preliminary GC128 using C128 die MC9S12GC128MFA25 TBD 40 C 125 C 48LQFP 25MHz Final GC128 using GC128 die MC9S12GC128MPB25 TBD 40 C 125 C 52LQFP 25MHz Final GC128 using GC128 die MC9S12GC128MFU25 TBD 40 C 125 C 80QFP 25MHz Final GC128 using GC128 die MC9S12GC64PCFA25 OLO9S 40 C 85 C 48LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PCPB25 OLO9S 40 C 85 C 52LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PCFU25 OLO9S 40 C 85 C 80QFP 25MHz Preliminary GC64 using C128 die AR MOTOROLA 19 Device User Guide 9512C128DGV1 D V01 05 Part Number pia Temp Package Speed Description MC9S12GC64CFA25 TBD 40 C 85 C 48LQFP 25MHz Final GC64 using GC64 die MC9S12GC64CPB25 TBD 40
20. 4 034 03F Clock and Reset Generator CRG 12 040 06F Standard Timer Module16 bit 8 channels TIM 48 070 07F Reserved 16 080 09F Analog to Digital Convert ATD 32 0A0 0C7 Reserved 40 0C8 0CF Serial Communications Interface SCI 8 0DO 0D7 Reserved 8 0D8 0DF Serial Peripheral Interface SPI 8 SOEO 0FF Pulse Width Modulator 8 bit 6 channels PWM 32 100 10F Flash Control Register 16 110 13F Reserved 48 140 17F Motorola Scalable CAN MSCAN 64 180 23F Reserved 192 240 27F Port Integration Module PIM 64 280 3FF Reserved 384 NOTES 1 External memory paging is not supported on this device 6 1 1 PPAGE 2 Not available on MC9S12GC Family Devices AR MOTOROLA 0000 0400 3000 4000 8000 C000 FF00 FFFF EN KO x lt VECTORS NORMAL SINGLE CHIP Device User Guide 9512C128DGV1 D V01 05 0000 1K Register Space PAGE MAP 03FF Mappable to any 2K Boundary 0000 16K Fixed Flash EEPROM FFF uc 3D 3000 4K Bytes RAM 3FFF Mappable to any 4K Boundary 4000 16K Fixed Flash EEPROM 3E 16K Page Window 8 16K Flash EEPROM Pages PPAGE 16K Fixed Flash EEPROM 3F BDM If Active EXPANDED SPECIAL SINGLE CHIP The figure shows a useful map which is not the map out of reset After reset the map is 30000 SURE Register Space 0000 OFFF 4K RAM only 3K visible 0400 0FFF Flash Erase
21. 90 48MHz V The phase detector relationship is given by Kg lion Ky 316 7Hz 0 ich is the current in tracking mode The loop bandwidth f should be chosen to fulfill the Gardner s stability criteria by at least a factor of 10 typical values are 50 G 0 9 ensures a good transient response 2 Gel at 1 fref a AAA fo 43 96 0 9 10 2 eene fc 25kHz 112 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 And finally the frequency relationship is defined as fvco ref 2 synr 1 50 With the above values the resistance can be calculated The example is shown for a loop bandwidth f 10kHz mento R K 2 1 50 10kHz 316 7Hz Q0 29 9kOz 10kQ o The capacitance C can now be calculated as 2 2206 2500516 5 19nF 4 7nF ue UT Ru ev The capacitance C should be chosen in the range of C 20 C C 10 C 470pF B 6 3 2 Jitter Information The basic functionality of the PLL is shown in Figure B 3 With each transition of the clock femp the deviation from the reference clock f is measured and input voltage to the VCO is adjusted accordingly The adjustment is done continuously with no abrupt changes in the clock output frequency Noise voltage temperature and other factors cause slight variations in the control loop resulting in a clock jitter This jitter affects the real minimum and maximum clock periods as illustrated in Figure B 4 113 AR MOTOROLA Device
22. AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO 0160 canpxe Pead FOREGROUND RECEIVE BUFFER see Table 1 2 016F Write 0170 cantxrg Reed FOREGROUND TRANSMIT BUFFER see Table 1 2 017F Write NOTES 1 Not available on the MC9S12GC Family members Those memory locations should not be accessed Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Extended ID Read ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 xxx0 Standard ID Read ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 CANxRIDRO Write Extended ID Read ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 xxx1 Standard ID Read ID2 ID1 IDO RTR IDE 0 CANxRIDR1 Write Extended ID Read ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 xxx2 Standard ID Read CANxRIDR2 Write Extended ID Read ID6 ID5 ID4 ID3 ID2 ID1 IDO RTR xxx3 Standard ID Read CANxRIDR3 Write xxx4 CANxRDSRO Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO xxxB CANxRDSR7 Write oxC CANRxDLR eae DLC3 DLC2 DLC1 DLCO Write Read xxxD Reserved ite oxE CANXRTSRH ps TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 xxxF CANXRTSRL o TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSRO Extended ID Read CANXTIDRO Write Standard ID Read Write ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 xx10 ID10 ID9 ID8 ID7 ID6
23. AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 D 3 52 pin LQFP package 4X SERRO 4X 13 TIPS 3x VIEW Y E SEATING PLANE VIEW AA 0 25 0 010 GAGE PLANE VIEW AA Z SED PLATING F BASE METAL IR Cd RE 0 13 0 005 T LMO NO NOTES do em SECTION AB AB ROTATED 90 CLOCKWISE MENSIONING AND TOLERANCING PER ANSI 14 5M 1982 ROLLING DIMENSION MILLIMETER UM PLANE H IS LOCATED AT BOTTOM OF D ANDIS COINCIDENT WITH THE LEAD WHERE LEAD EXITS THE PLASTIC BODY AT THE OTTOM OF THE PARTING LINE UMS L M AND N TO BE DETERMINED AT ATUM PLANE H MENSIONS S AND V TO BE DETERMINED AT ING PLANE T MENSIONS A AND B DO NOT INCLUDE MOLD ROTRUSION ALLOWABLE PROTRUSION IS 0 25 010 PER SIDE DIMENSIONS A AND B DO CLUDE MOLD MISMATCH AND ARE ETERMINED AT DATUM PLANE H MENSION D DOES NOT INCLUDE DAMBAR ROTRUSION DAMBAR PROTRUSION SHALL NOT AUSE THE LEAD WIDTH TO EXCEED 0 46 0 018 NIMUM SPACE BETWEEN PROTRUSION AND DJACENT LEAD OR PROTRUSION 0 07 0 003 ImM2352 m2 32 3 pelo fofo fofo fd Am zo ovg r MILLIMETERS INCHES DIM MIN MAX MIN MAX A 10 00 BSC 0 394 BSC At B 10 00 BSC 0 394 BSC B1 5 00 BSC 0 197 BSC C 1 0 067 C1 0 002 0 008 c2 130 150 0 051 0 059 D 0 20 040 0 008 0 016 E 045 075
24. C96 using C96 die MC9S12C96CPB25 TBD 40 C 85 C 52LQFP 25MHz Final C96 using C96 die MC9S12C96CFU25 TBD 40 C 85 C 80QFP 25MHz Final C96 using C96 die MC9S12C96PVFA25 OLO9S 40 C 105 C 48LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PVPB25 OLO9S 40 C 105 C 52LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PVFU25 OLO9S 40 C 105 C 80QFP 25MHz Preliminary C96 using C128 die AR MOTOROLA 17 Device User Guide 9512C128DGV1 D V01 05 Mask Part Number set Temp Package Speed Description MC9S12C96VFA25 TBD 40 C 105 C 48LQFP 25MHz Final C96 using C96 die MC9S12C96VPB25 TBD 40 C 105 C 52LQFP 25MHz Final C96 using C96 die MC9S12C96VFU25 TBD 40 C 105 C 80QFP 25MHz Final C96 using C96 die MC9S12C96PMFA25 OLO9S 40 C 125 C 48LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PMPB25 OLO9S 40 C 125 C 52LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PMFU25 OLO9S 40 C 125 C 80QFP 25MHz Preliminary C96 using C128 die MC9S12C96MFA25 TBD 40 C 125 C 48LQFP 25MHz Final C96 using C96 die MC9S12C96MPB25 TBD 40 C 125 C 52LQFP 25MHz Final C96 using C96 die MC9S12C96MFU25 TBD 40 C 125 C 80QFP 25MHz Final C96 using C96 die MC9S12C64PCFA16 OLO9S 40 C 85 C 48LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PCPB16 OLO9S 40 C 85 C 52LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PCFU16 OLO9S 40 C 85 C 8
25. CAEO 0 0 0 CON45 CON23 CON01 PSWAI PFRZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 43 Device User Guide 9512C128DGV1 D V01 05 Address Name Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00F7 PWMPERS Peat pi 6 5 4 3 2 1 Bit 0 Write sore PwMDTYo REC pz 6 5 4 3 2 1 Bito Write soro PWMDIYi Read git7 6 5 4 3 2 1 Bit 0 Write sora PWMDTY2 Read pi 6 5 4 3 2 1 Bit 0 Write sorB PWMDIYa Peet gi 6 5 4 3 2 1 Bito Write sorc PwMDTY4 REG gi 6 5 4 3 2 1 Bit 0 Write sorD PWMDTYs Ped gr 6 5 4 3 2 1 Bit 0 Write Read O 0 0 0 0 0 0 0 00FE Reserved Write Read 0 0 0 0 0 0 0 0 00FF Reserved Write 0100 010F Flash Control Register Address Name Bit7 Bit 6 Bit5 Bit 4 Bit3 Bit 2 Bit 1 Bit o Read FDIVLD eR ERG 0100 FCLKDIV te a PRDIV8 FDIVS FDIV FDIV FDIV2 FDIVI FDIVO m Read KEYENT KEYENO NVS NV4 NV3 Nv2 SEC SECO Write 0102 FTsTmop Reed q 0 0 WRALL LO y Write 90103
26. E I O pin and pipe status Mode ECLK PUCR Dep Port E I O pin bus clock output Mode sia VDDX PUCR Port E I O pin R W in expanded modes VDDX Port E input external interrupt pin LSTRB PUCR Port E I O pin low strobe tag signal low XIRQ ADDR 15 1 DATA 15 1 gt ADDR 10 9 PA 2 11 DATA 10 9 VDDX Port E input non maskable interrupt pin PA 7 3 VDDX Disabled Port A I O pin amp multiplexed address data VDDX PUCR Disabled Port A I O pin amp multiplexed address data ADDR 7 5 DATA 7 5 ADDR 4 DATA 4 ADDR 3 0 DATA 3 0 PB 7 5 PUCR Disabled Port B I O pin amp multiplexed address data PB 4 PUCR Disabled Port B I O pin amp multiplexed address data PB 3 0 PUCR Disabled Port B I O pin amp multiplexed address data PAD 7 0 AN 7 0 EE PP 7 KWP 7 VDDX RS Disabled Port P I O Pins and keypad wake up ROMCTL VDDX PERP Disabled Port P I O Pins keypad wake up and ROMON PPSP enable Disabled Port AD I O pins and ATD inputs PA 0 5 rid Es VDDX PUCR Disabled Port A I O pin amp multiplexed address data PP 5 KWP 5 VDDX Mabi Disabled Port P I O Pin keypad wake up PW5 output PERP PP 4 3 KWP 4 3 PW 4 3 VDDX PPSP Disabled Port P I O Pin keypad wake up PWM output AR MOTOROLA 55 Device User Guide 9512C128DGV1 D V01 05 Internal Pull Pin Name Pin Name Pin Name Power Resistor Function 1
27. ECLK pin is initially configured as ECLK output with stretch in all expanded modes The E clock output function depends upon the settings of the NECLK bit in the PEAR register the IVIS bit in the MODE register and the ESTR bit in the EBICTL register All clocks including the E clock are halted when the MCU is in STOP mode It is possible to configure the MCU to interface to slow external memory ECLK can be stretched for such accesses Reference the MISC register EXSTR 1 0 bits for more information In normal expanded narrow mode the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system Alternatively PE4 can be used as a general purpose input or output pin 2 3 12 PE3 LSTRB Port E I O Pin 3 Low Byte Strobe LSTRB In all modes this pin can be used as a general purpose I O and is an input with an active pull up out of reset If the strobe function is required it should be enabled by setting the LSTRE bit in the PEAR register This signal is used in write operations Therefore external low byte writes will not be possible until this function is enabled This pin is also used as TAGLO in Special Expanded modes and is multiplexed with the LSTRB function This pin is not available in the 48 52 pin package versions 2 3 13 PE2 RW Port E I O Pin 2 Read Write In all modes this pin can be used as a general purpose I O and is an input with an active
28. FFOO VECTORS FED NORMAL EXPANDED SPECIAL SINGLE CHIP SINGLE CHIP The figure shows a useful map which is not the map out of reset After reset the map is 30000 SOFE Register Space 0800 0FFF 2K RAM Flash Erase Sector Size is 512 Bytes Figure 1 6 MC9S12GC16 User Configurable Memory Map 1 6 Detailed Register Map The detailed register map of the MC9S12C Family is listed in address order below AR MOTOROLA 33 Device User Guide 9512C128DGV1 D V01 05 0000 000F Address 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved 0010 0014 Address 0010 0011 Address 34 Name INITRM INITRG Name Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MEBI map 1 of 3 HCS12 Multiplexed External Bus Interface Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0
29. ID5 ID4 ID3 46 AR MOTOROLA Address Name Extended ID CANxTIDR1 SO Standard ID Extended ID CANxTIDR2 PIE Standard ID Extended ID CANxTIDR3 pota Standard ID xx14 CANXTDSRO xx1B CANxTDSR7 xx1C CANXTDLR xx1D CONxTTBPR xx1E CANXxTTSRH xx1F CANXTTSRL 0180 023F 0180 023F Reserved 0240 027F Device User Guide 9512C128DGV1 D V01 05 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read Write ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 Read Write ID2 ID1 IDO RTR IDE 0 Read Write ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 Read Write Read Write IDE ID5 ID4 ID3 ID2 ID1 IDO RTR Read Write Read Write DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Read Write DLC3 DLC2 DLC1 DLCO Head Brio7 PRIO6 PRIO5 PRIO4 Write PRIO3 PRIO2 PRIO1 PRIOO Read TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 Write Read TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSRO Write Reserved PIM Port Interface Module 0240 PTT ce P117 ptte PTI5 PTT4 PTT3 PTT2 pm PTO oe Read PTIT7 Prite PTIT priv PTITS PTIT2 Primi PTITO Write 0242 DDRT ae DDRT7 DDRT7 DDRT5 DDRT4 DDRT
30. IRQEN FFFO SFFF1 SFFEE SFFEF Real Time Interrupt Standard Timer channel 0 CRGINT RTIE TIE COl SFFEC SFFED Standard Timer channel 1 TIE C11 SFFEA SFFEB FFE8 FFE9 Standard Timer channel 2 Standard Timer channel 3 TIE C21 TIE C3I FFE6 FFE7 Standard Timer channel 4 FFE4 SFFE5 FFE2 FFE3 Standard Timer channel 5 Standard Timer channel 6 TIE C5I TIE Cel TIE C41 SFFEO SFFE1 Standard Timer channel 7 TIE C71 SFFDE SFFDF FFDC FFDD Standard Timer overflow Pulse accumulator A overflow TMSK TOI PACTL PAOVI FFDA FFDB Pulse accumulator input edge PACTL PAI FFD8 FFD9 FFD6 FFD7 SPI I Bit Reserved SPICR1 SPIE SPTIE SCICR2 TIE TCIE RIE ILIE FFD4 FFD5 FFD2 FFD3 FFDO FFD1 ATD Port J I Bit Reserved I Bit ATDCTL2 ASCIE PIEP PIEP7 6 FFCE FFCF FFCC FFCD Reserved SECA SFFCB Reserved FFC8 FFC9 FFC6 FFC7 FFC4 SFFC5 CRG Self Clock Mode I Bit CRG PLL lock I Bit Reserved PLLCR LOCKIE PLLCR SCMIE C6 C4 FFBA to SFFC3 FFB8 FFB9 FFB6 FFB7 CAN wake up I Bit I Bit CANRIER CSCIE OVRIE FFB4 FFB5 FLASH CAN errors 1 I Bit FCNFG CCIE CBEIE CANRIER WUPIE B8 B6 B4 FFB2 FFB3 FFBO FFB1 CAN receive CAN transmit
31. Interface module Section 14 Serial Peripheral Interface SPI Block Description Consult the SPI Block User Guide for information about the Serial Peripheral Interface module 80 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Consult the SPI Block User Guide for information about the Synchronous Serial Communications Interface module Section 15 Flash Block Description Consult the FTS16K Block User Guide for information about the Flash module for the MC9S12GC16 Consult the FTS32K Block User Guide for information about the Flash module for the MC9S12C32 or MC9S12GC32 Consult the FTS64K Block User Guide for information about the Flash module for the MC9S12C64 or MC9S12GC64 Consult the FTS96K Block User Guide for information about the Flash module for the MC9S12C96 Consult the FTS128K Block User Guide for information about the Flash module for the MC9S 12C128or MC9S12GC128 Section 16 RAM Block Description This module supports single cycle misaligned word accesses without wait states The MC912GC16 features a single 1K byte RAM module The MC9S12C32 and MC9S12GC32 feature a 2K byte RAM module The MC9S12C64 MC9S12GC64 MC9S12C96 MC9S12C128 and MC9S12GC128 versions feature a 4K byte RAM module Section 17 Pulse Width Modulator PWM Block Description Consult the PWM 8B6C Block User Guide for information about the Pulse Width Modulator Module Section 18 MSCAN Block Description Consult the MSCAN Bloc
32. Minimum bus frequency specification increased to 0 25MHz 00 06 01 00 21 MAY 03 15 JUL 03 21 MAY 03 15 JULOS Parameter classification added to Appendix Table C 2 IOH changed to 4mA for 3V range LVR level defined for C32 Run IDD changed for C32 Block guide reference table updated Added PCB layout guide for Pierce oscillator configuration IOL parameter updated in 3 3V range 01 01 01 02 01 03 12 AUG 03 20 NOV 03 27 NOV 03 12 AUG 03 20 NOV 03 27 NOV 03 Updated PARTID listing due to C128 ECO revision Changed DOC number and CPU DOC reference number Included separate C32 LVI levels Changed PortM pull up reset state to enabled Added References to the CAN less GC Family No major revision number increment since silicon functionality is not changed Added VDDX connection in PCB layout figures 8 1 to 8 6 Added Part ID for 2L45J mask set to Part ID table 01 04 27 JAN 04 27 JAN 04 Table A 4 VDD VDDPLL min when supplied externally now 2 35V Reference S12FTS128K1 in Preface was S12FTS128K Reference to CPU Guide corrected to Version2 01 05 11 FEB 04 11 FEB 04 Corrected flash sector sizes for C Family devices with 564K Flash Corrected Preface Table 0 1 16K part listing to GC16 without CAN Added PPAGE specifications to memory map diagrams Added flash timing parameters for 1024 byte sector size AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05
33. S12MEBIV3 D HCS12 Interrupt INT Block Guide Vol S12INTV1 D Analog To Digital Converter 10 Bit 8 Channel ATD_10B8C Block Guide V02 S12ATD10B8CV2 D Clock and Reset Generator CRG Block Guide V04 S12CRGV4 D Serial Communications Interface SCI Block Guide V02 S12SCIV2 D Serial Peripheral Interface SPI Block Guide Vos S12SPIV3 D Motorola Scalable CAN MSCAN Block Guide V02 S12MSCANV2 D Pulse Width Modulator 8 bit 6 channel PWM 8B6C Block Guide V01 S12PWM8B6V1 D Timer 16 bit 8 channel TIM_16B8C Block Guide Vol S12TIM16B8CV1 D Voltage Regulator VREG Block Guide V02 S12VREG3V3V2 D Oscillator OSC Block Guide V02 S120SCV2 D Port Integration Module PIM 9C32 Block Guide V01 S12C32PIMV1 D 32Kbyte Flash EEPROM FTS32K Block Guide Vol S12FTS32KV1 D 64Kbyte Flash EEPROM FTS64K Block Guide Vol S12FTS64KV1 D 128Kbyte Flash EEPROM FTS128K1 Block Guide Vol S12FTS128K1V1 D NOTES 1 For the GC16 refer to the 16K flash for the C32 and GC32 refer to the 32K flash for the C64 and GC64 the 64K flash for the C96 the 96K flash and C128 the 128K flash document 2 Not available on the GC Family members Terminology Acronyms and Abbreviations New or invented terms symbols and notations AR MOTOROLA 21 Device User Guide 9512C128DGV1 D V01 05 22 M MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Section 1 Introduction 1 1 Overview The MC9S12C Family and the MC9S12GC Family is a 48 52 80 pin Fl
34. SPI Slave Timing CPHA 0 In Figure C 4 the timing diagram for slave mode with transmission format CPHA 1 is depicted AR MOTOROLA 121 Device User Guide 9512C128DGV1 D V01 05 SS INPUT SCK CPOL 0 INPUT SCK CPOL 1 INPUT gt 68 MISO see OUTPUT note M SLAVE MSB OUT BIS pl SLAVE LSBOUT Ro 5 MOSI INPUT MSB IN NOTE Not defined Figure C 4 SPI Slave Timing CPHA 1 In Table C 3 the timing characteristics for slave mode are listed Table C 3 SPI Slave Mode Timing Characteristics Characteristic Symbol Unit SCK Frequency fsck DC 1 4 fous SCK Period lsck 4 oo tbus Enable Lead Time 1 1 Enable Lag Time Clock SCK High or Low Time Data Setup Time Inputs tsu Data Hold Time Inputs thi Slave Access Time time to data active Slave MISO Disable Time Data Valid after SCK Edge Data Valid after SS fall Eo E EM e Data Hold Time Outputs tho 12 D Rise and Fall Time Inputs tri 8 ns 13 D Rise and Fall Time Outputs tro 8 ns NOTES 1 tbus added due to internal synchronization delay 122 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 C 3 External Bus Timing A timing diagram of the external multiplexed bus is illustrated in Figure C 5 with the actual timing values shown on table Table C 4 All major bus signals are included in the diagram While both
35. Symbol Min Typical Max Unit ENE Input Voltages VVDDR A 2 97 5 5 V Regulator Current Reduced Power Mode Shutdown Mode Output Voltage Core Full Performance Mode Low Voltage Interrupt Assert Level C32 GC32 Assert Level C64 C96 C128 GC64 GC128 Deassert Level C32 GC32 Deassert Level C64 C96 C128 GC64 GC128 Low Voltage Reset Assert Level C32 GC32 Assert Level C64 C96 C128 GC64 GC128 Low Voltage Reset Deassert Level Power on Reset 7 C Assert Level VPORA 0 97 V Deassert Level VporD 2 05 V NOTES 1 Monitors Vppa active only in Full Performance Mode Indicates I O amp ADC performance degradation due to low supply voltage 2 Monitors Vpp active only in Full Performance Mode MCU is monitored by the POR in RPM see Figure B 1 3 Monitors Vpp Active in all modes NOTE The electrical characteristics given in this section are preliminary and should be used as a guide only Values in this section cannot be guaranteed by Motorola and are subject to change without notice AR MOTOROLA 95 Device User Guide 9512C128DGV1 D V01 05 B 2 Chip Power up and LVI LVR graphical explanation Voltage regulator sub modules LVI low voltage interrupt POR power on reset and LVR low voltage reset handle chip power up or drops of the supply voltage Their function is described in Figure B 1 Figure B 1 Voltage Regulator Chip Power up and Voltage Drops not sca
36. This 2 5V voltage is generated by the internal voltage regulator Table 2 2 MC9S12C Family Power and Ground Connection Summary Nominal ARI Mnemonic Voltage Description VDD1 25v Internal power and ground generated by internal regulator These also VDD2 allow an external source to supply the core VDD VSS voltages and bypass VSS1 the internal voltage regulator vss2 ov In the 48 and 52 LQFP packages VDD2 and VSS2 are not available VDDR 5 0 V External power and ground supply to internal voltage regulator VSSR OV VDDX 5 0 V Ext d d htec xternal power and ground su o pin drivers VSSX OV baa al VDDA 5 0 V Operating voltage and ground for the analog to digital converters and the reference for the internal voltage regulator allows the supply voltage to the VSSA OV A D to be bypassed independently VRH 5 0V Reference voltage low for the ATD converter VRL OV In the 48 and 52 LQFP packages VRL is bonded to VSSA VDDPLL 2 5V Provides operating voltage and ground for the Phased Locked Loop This fT allows the supply voltage to the PLL to be bypassed independently VSSPLL 0v Internal power and ground generated by internal regulator NOTE AIl VSS pins must be connected together in the application Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requir
37. VSS2 are the supply pins for the digital logic VDDPLL VSSPLL supply the oscillator and the PLL AR MOTOROLA 83 Device User Guide 9512C128DGV1 D V01 05 VSS1 and VSS2 are internally connected by metal VDDI and VDD2 are internally connected by metal VDDA VDDX VDDR as well as VSSA VSSX VSSR are connected by anti parallel diodes for ESD protection NOTE Inthe following context VDDS is used for either VDDA VDDR and VDDX VSS5 is used for either VSSA VSSR and VSSX unless otherwise noted IDDS denotes the sum of the currents flowing into the VDDA VDDX and VDDR pins VDD is used for VDD1 VDD2 and VDDPLL VSS is used for VSSI VSS2 and VSSPLL IDD is used for the sum of the currents flowing into VDDI and VDD2 A 1 3 Pins There are four groups of functional pins A 1 3 1 5V I O pins Those I O pins have a nominal level of 5V This class of pins is comprised of all port I O pins the analog inputs BKGD pin and the RESET inputs The internal structure of all those pins is identical however some of the functionality may be disabled E g pull up and pull down resistors may be disabled permanently A 1 3 2 Analog Reference This class is made up by the two VRH and VRL pins In 48 and 52 pin package versions the VRL pad is bonded to the VSSA pin A 1 3 3 Oscillator The pins XFC EXTAL XTAL dedicated to the oscillator have a nominal 2 5V level They are supplied by VDDPLL A 1 3 4 TEST This pin is used for production
38. WOMM2 WOMM WOMMO Read O 0 0 0 0 0 0 0 0257 Reserved Write 0258 PTP je PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTPi PIPO o bat Read PTIP7 PTIPG PTIPS pripa PTIP3 PTIP2 PTIPi PTIPO Write 025A DDRP a DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRPO 025B RDRP he RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRPO 025C PERP Nak PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERPO 025D PPSP bn PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSSO 025E PIEP his PIEP7 PIEP6 PIEPS PIEP4 PIEP3 PIEP2 PIEP1 PIEPO 025F PIFP Ne PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFPO Read O 0 0 0 0 0 0 0 0260 Reserved Write 48 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Read O 0 0 0 0 0 0 0 0261 Reserved Write Read 0 0 0 0 0 0 0 0 0262 Reserved Write Read 0 0 0 0 0 0 0 0 50263 Reserved Write Read O 0 0 0 0 0 0 0 0264 Reserved Write Read O 0 0 0 0 0 0 0 0265 Reserved Write Read O 0 0 0 0 0 0 0 0266 Reserved Write Read 0 0 0 0 0 0 0 0 0267 Reserved Write 0268 PTJ Read pr PTUs 0 0 0 Write bas Siri Read PTU7 PTU6 0 0 0 0 0 0 Write 026A Dor Read apy ppm Write 026B RDRJ Read RDRJ7 RDRJ6 2 ki Write 026C PERJ Read PERJ7 PERJ6 Write seb Ppsy adi pps ppgjg LO Write 026E PIEJ Rea
39. code would defeat the purpose of security At the same time the user may also wish to put a back door in the user s program An example 66 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters 4 3 1 Securing the Microcontroller Once the user has programmed the FLASH the part can be secured by programming the security bits located in the FLASH module These non volatile bits will keep the part secured through resetting the part and through powering down the part The security byte resides in a portion of the Flash array Check the Flash Block User Guide for more details on the security configuration 4 3 2 Operation of the Secured Microcontroller 4 3 2 1 Normal Single Chip Mode This will be the most common usage of the secured part Everything will appear the same as if the part was not secured with the exception of BDM operation The BDM operation will be blocked 4 3 2 2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller This is accomplished by resetting directly into expanded mode The internal FLASH will be disabled BDM operations will be blocked 4 3 3 Unsecuring the Microcontroller In order to unsecure the microcontroller the internal FLASH must be erased This can be done through an external program in expanded mode or via a sequence o
40. endo 109 Table B 11 Oscillator Characteristics llle 111 Table B 12 PEE ODSFacterislieS soo ota uti Gat de dei sb tice utar AA 115 Table B 13 MSCAN Wake up Pulse CharacteristiCS o o ooooooo o 117 Table C 1 Measurement Conditions 0 0 0 00 cee ees 119 12 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Table C 2 SPI Master Mode Timing Characteristics a 120 Table C 3 SPI Slave Mode Timing Characteristics oooooooooooo 122 Table C 4 Expanded Bus Timing Characteristics 5V Range 124 Table C 5 Expanded Bus Timing Characteristics 3 3V Range 125 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 14 M MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Preface The Device User Guide provides information about the MC9S12C Family as well the MC9S12GC Family devices made up of standard HCS12 blocks and the HCS12 processor core This document is part of the customer documentation A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block User Guides of the implemented modules In an effort to reduce redundancy all module specific information is located only in the respective Block User Guide If applicable special implementation details of the module are given in the block description sections of this document The C Family and the GC Family offer an extensive ra
41. ns 12 D Write data delay time toow 15 ns 13 D Write data hold time tbHW 2 ns 14 D Write data setup time PWey tppw tosw eed ll c ns 15 D Address access time tacca 29 ns 16 D Ehigh access time PWe tpsR tacce 15 ns 17 D Read write delay time tRwD 14 ns 18 D Read write valid time to E rise PWE trwp trwv EE ERN ns 19 D Read write hold time trawH 2 ns 20 D Low strobe delay time tisp 14 ns 21 D Low strobe valid time to E rise PWE t sp ti sv a ns 22 D Low strobe hold time ti su 2 ns 23 D NOACC strobe delay time tNOD 14 ns 24 D NOACC valid time to E rise PWe t sp tNov 16 ns 25 D NOACC hold time tNoH 2 ns 26 D IPIPO 1 0 delay time tPop 2 14 ns 27 D IPIPO 1 0 valid time to E rise PWE tpop trov 16 ns 28 D IPIPO 1 0 delay time tp1D ERES ns 29 D IPIPO 1 0 valid time to E fall tpiv 11 ns NOTES 1 Affected by clock stretch add N x toyo where N 0 1 2 or 3 depending on the number of clock stretches 125 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 126 M MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Appendix D Package Information D 1 General This section provides the physical dimensions of the MC9S12C Family and MC9S12GC Family packages 48LQFP 52LQFP 80QFP 127 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 D 2 80 pin QFP package DETAIL A 0 20 c ABO DO 110 05 A B 0200 H AB OPO mM WY
42. pull up out of reset If the read write function is required it should be enabled by setting the RDWE bit in the PEAR register External writes will not be possible until enabled This pin is not available in the 48 52 pin package versions 60 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 2 3 14 PE1 IRQ Port E input Pin 1 Maskable Interrupt Pin The IRQ input provides a means of applying asynchronous interrupt requests to the MCU Fither falling edge sensitive triggering or level sensitive triggering is program selectable INTCR register IRQ is always enabled and configured to level sensitive triggering out of reset It can be disabled by clearing IRQEN bit INTCR register When the MCU is reset the IRQ function is masked in the condition code register This pin is always an input and can always be read There is an active pull up on this pin while in reset and immediately out of reset The pull up can be turned off by clearing PUPEE in the PUCR register 2 3 15 PEO XIRQ Port E input Pin 0 Non Maskable Interrupt Pin The XIRQ input provides a means of requesting a non maskable interrupt after reset initialization During reset the X bit in the condition code register CCR is set and any interrupt is masked until MCU software enables it Because the XIRQ input is level sensitive it can be connected to a multiple source wired OR network This pin is always an input and can always be read There is an active pull
43. to Figure 1 5 footnotes for locations of the memories depending on the operating mode after reset The RAM array is not automatically initialized out of reset NOTE For devices assembled in 48 pin or 52 pin LQFP packages all non bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs Refer to Table 2 1 for affected pins Section 6 HCS12 Core Block Description Consult the individual block guides for information about the HCS12 core modules i e central processing unit CPU interrupt module INT module mapping control module MMC multiplexed external bus interface MEBI debug12 module DBG12 and background debug mode module BDM Where the CPU12 Reference Manual refers to cycles this is equivalent to device bus clock periods 6 1 Device specific information 6 1 1 PPAGE External paging is not supported on these devices In order to access the 16K flash blocks in the address range 8000 SBFFF the PPAGE register must be loaded with the corresponding value for this range Refer to Table 6 1 for device specific page mapping 70 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 For all devices Flash Page 3F is visible in the C000 SFFFF range if ROMON is set For all devices ecept 9S12GC16 Page 3E is also visible in the 4000 7FFF range if ROMHM is cleared and ROMON is set For all devices apart from MC9S12C32 Flash Page 3D is visible in the 0000 3FFF range if
44. wave pulse width low ns External square wave pulse width high ns 5 6 7 8 9 External square wave rise time ns a o External square wave fall time ns 1 Input Capacitance EXTAL XTAL pins pF 1 Cin DC Operating Bias in Colpitts Configuration V E on EXTAL Pin EIAS Y NOTES 1 Depending on the crystal a damping series resistor might be necessary 2 fos 4MHz C 22pF 3 Maximum value is for extreme cases using high Q low frequency crystals 4 XCLKS 0 during reset B 6 3 Phase Locked Loop The oscillator provides the reference clock for the PLL The PLL s Voltage Controlled Oscillator VCO is also the system clock source in self clock mode B 6 3 1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics AR MOTOROLA 111 Device User Guide 9512C128DGV1 D V01 05 p VDDPLL Cs R XFC Pin Phase VCO fosc 1 fref fvco refdv 1 Detector femp Loop Divider Figure B 3 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for Kj f and i from Table B 12 The grey boxes show the calculation for fyco 50MHz and f ef 1MHz E g these frequencies are used for fosc 4MHz and a 25MHz bus clock The VCO Gain at the desired VCO frequency is approximated by fi feo 60 50 K 1V 100m Ky K e 100 e
45. 0 Write Read 0 0 0 0 0 0 0 Write SC Read 0 0 0 0 0 0 0 0 Write AR MOTOROLA 0080 009F Address 008B 008C 008D 008E 008F 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F Name ATDSTAT1 Reserved ATDDIEN Reserved PORTADO ATDDROH ATDDROL ATDDR1H ATDDR1L ATDDR2H ATDDR2L ATDDR3H ATDDR3L ATDDR4H ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L ATDDR7H ATDDR7L 00A0 00C7 00A0 00C7 AR MOTOROLA Reserved Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Device User Guide 9512C128DGV1 D V01 05 ATD Analog to Digital Converter 10 Bit 8 Channel Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCFO 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit7 6 5 4 3 2 1 BIT 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bi
46. 0 0 0 0 00DC Reserved Write SS a wc mi cZZ i ooDD sppR R20 gy 6 5 4 3 2 1 Bito Write Read 0 0 0 0 0 0 0 0 00DE Reserved Write Read O 0 0 0 0 0 0 0 S00DF Reserved y m g M a 42 AR MOTOROLA 00E0 Address 00E0 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8 00E9 00EA 00EB 00EC 00ED 00EE 00EF 00F0 00F1 00F2 00F3 00F4 00F5 00F6 AR MOTOROLA 00FF Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC PWMSCLA PWMSCLB PWMSCNTA PWMSCNTB PWMCNTO PWMCNT1 PWMCNT2 PWMCNT3 PWMCNT4 PWMCNT5 PWMPERO PWMPER1 PWMPER2 PWMPER3 PWMPER4 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write PWM Pulse Width Modulator Device User Guide 9512C128DGV1 D V01 05 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWME5 PWME4 PWME3 PWME2 PWME1 PWMEO PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOLO i PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLKO 3 PCKB2 PCKB1 PCKBO 0 PCKA2 PCKA1 PCKAO k CAE5 CAE4 CAE3 CAE2 CAE1
47. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39 Device User Guide 9512C128DGV1 D V01 05 Address 0068 0069 006A 006B 006C 006D 006E 006F Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0070 007F 0070 007F Reserved 0080 009F Address 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 008A 40 Name ATDCTLO ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTATO Reserved ATDTESTO ATDTEST1 Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Reserved writ AAA ent Read 0 do lodo lolol 0 ATD Analog to Digital Converter 10 Bit 8 Channel Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bito Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Mes ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE LASCF ioa eed dis USO S4C S2C S1C FIFO FRZ1 FRZO Write Read we SRES8 SMP1 SMPO PRS4 PRS3 PRS2 PRS PRSO Read pM DSGN SCAN MULT CC CB CA Write Read SCF 0 ETORF FIFOR 0 CC2 CC1 cco Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0
48. 0QFP 16MHz Preliminary C64 using C128 die MC9S12C64CFA16 TBD 40 C 85 C 48LQFP 16MHz Final C64 using C64 die MC9512C64CPB16 TBD 40 C 85 C 52LQFP 16MHz Final C64 using C64 die MC9S12C64CFU16 TBD 40 C 85 C 80QFP 16MHz Final C64 using C64 die MC9S12C64PVFA16 OLO9S 40 C 105 C 48LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PVPB16 OLO9S 40 0 105 C 52LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PVFU16 OLO9S 40 C 105 C 80QFP 16MHz Preliminary C64 using C128 die MC9512C64VFA16 TBD 40 C 105 C 48LQFP 16MHz Final C64 using C64 die MC9512C64VPB16 TBD 40 C 105 C 52LQFP 16MHz Final C64 using C64 die MC9512C64VFU16 TBD 40 C 105 C 80QFP 16MHz Final C64 using C64 die MC9S12C64PMFA16 OLO9S 40 C 125 C 48LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PMPB16 OLO9S 40 C 125 C 52LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PMFU16 OLO9S 40 C 125 C 80QFP 16MHz Preliminary C64 using C128 die MC9512C64MFA16 TBD 40 C 125 C 48LQFP 16MHz Final C64 using C64 die MC9S12C64MPB16 TBD 40 C 125 C 52LQFP 16MHz Final C64 using C64 die MC9512C64MFU16 TBD 40 C 125 C 80QFP 16MHz Final C64 using C64 die MC9S12C64PCFA25 OLO9S 40 C 85 C 48LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PCPB25 OLO9S 40 C 85 C 52LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PCFU25 OLO9S 40 C 85 C 80QFP 25MHz PreliminaryC64 using C128 die MC9512C64CFA25 TBD 40 C 85 C 48LQFP 25MHz Final C64 using C64 die MC95
49. 11 X PE4 ECLK Port E I O Pin 4 E Clock Output aa 60 2 3 12 PES LSTRB Port E I O Pin 3 Low Byte Strobe LSTRB 60 2 3 13 PE2 R W Port E I O Pin 2 Read Write ooooocoooooo o 60 2 3 14 PE1 IRQ Port E input Pin 1 Maskable Interrupt Pin 61 2 3 15 PEO XIRQ Port E input Pin 0 Non Maskable Interrupt Pin 61 2 3 16 PAD 7 0 AN 7 0 Port AD I O Pins 7 0 leeren 61 2 17 PP 7 KWP 7 Port P HO Pin wada xS ORE ERA ares ae RGR REX S 61 2 3 18 PP 6 KWP 6 ROMCTL Port P I O Pin 6 o o ooooooooo 61 2 3 19 PP 5 0 KWP 5 0 PW 5 0 Port P I O Pins 5 0 62 AR MOTOROLA 3 Device User Guide 9512C128DGV1 D V01 05 2 3 20 2 3 21 2 3 22 2 3 23 2 3 24 2 3 25 2 3 26 2 3 27 2 3 28 2 3 29 2 3 30 2 3 31 2 4 2 4 1 2 4 2 63 2 4 3 2 4 4 2 4 5 2 4 6 PJ 7 6 KWJ 7 6 Port J I O Pins 7 6 aa 62 PM5 S0 Port M VO PING aici eee es a ere is 62 PM4 MOSI Port M l OPin4 0 0 IIR 62 PM3 SS Port M I O PIN Quse PAGDAAN nahh Y a AN Side s 62 PM2 MISO Port M I O PIN s rece tx RU ees GG ded NG adi 62 PMT TXCAN Port M VO PING lt ust 3n S dS HORE S ANT eae 62 PMO T RXCAN Port MIKO PIO ve ad ore ade A Er S 62 PS 3 2 Port S IO Pins 9 2 raider 63 PS eT XO Pot S O PII T osse oue hap a th et E ee pt dtes 63 P
50. 12C64CPB25 TBD 40 C 85 C 52LQFP 25MHz Final C64 using C64 die MC9S12C64CFU25 TBD 40 C 85 C 80QFP 25MHz Final C64 using C64 die MC9S12C64PVFA25 OLO9S 40 C 105 C 48LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PVPB25 OLO9S 40 0 105 C 52LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PVFU25 OLO9S 40 C 105 C 80QFP 25MHz Preliminary C64 using C128 die MC9512C64VFA25 TBD 40 C 105 C 48LQFP 25MHz Final C64 using C64 die MC9512C64VPB25 TBD 40 C 105 C 52LQFP 25MHz Final C64 using C64 die MC9512C64VFU25 TBD 40 C 105 C 80QFP 25MHz Final C64 using C64 die MC9S12C64PMFA25 OLO9S 40 C 125 C 48LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PMPB25 OLO9S 40 C 125 C 52LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PMFU25 OLO9S 40 C 125 C 80QFP 25MHz Preliminary C64 using C128 die MC9512C64MFA25 TBD 40 C 125 C 48LQFP 25MHz Final C64 using C64 die MC9512C64MPB25 TBD 40 C 125 C 52LQFP 25MHz Final C64 using C64 die 18 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Part Number pisan Temp Package Speed Description MC9S12C64MFU25 TBD 40 C 125 C 80QFP 25MHz Final C64 using C64 die MC9S12C32CFA16 1L45J 40 C 85 C 48LQFP 16MHz C32 die MC9S12C32CPB16 1L45J 40 C 85 C 52LQFP 16MHz C32 die MC9512C32CFU16 1L45J 40 C 85 C 80QFP 16MHz C32 die MC9S12C32VFA16 1L45J 40 C 105 C 48LQFP 16MHz C32 die
51. 15 P Port P J Interrupt Input Pulse filtered tpiGN 3 us 16 P Port P J Interrupt Input Pulse passed tpvaL 10 us NOTES 1 Maximum leakage current occurs at maximum operating temperature Current decreases by approximately one half for each 8 C to 12 C in the temperature range from 50 C to 125 C 2 Refer to Section A 1 4 Current Injection for more details 3 Parameter only applies in STOP or Pseudo STOP mode 90 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Table A 7 3 3V I O Characteristics Conditions are VDDX 3 3V 10 Termperature from 40 C to 140 C unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Input High Voltage Vi 0 65 Vpps V T Input High Voltage Vin 5 VDD5 0 3 V 2 P Input Low Voltage VL 0 35 Vppg V T Input Low Voltage Vi VSS5 0 3 V 3 C Input Hysteresis Viiys 250 mV Input Leakage Current pins in high ohmic input 4 P mode I 1 E 1 uA Vin Vops orV i SS5 Output High Voltage pins in output mode V i C Partial Drive loH 0 75mA oH Vpps 04 V Output High Voltage pins in output mode V zx E P Full Drive loy 4mA oH Vpps 0 4 V Output Low Voltage pins in output mode Partial Drive loj 0 9mA Output Low Voltage pins in output mode Full Drive loj 4 75mA Internal Pull Up Device Current 3 P tested at V Max IPUL i 60 uA Internal Pull Up Device C
52. 2 Pin assignments in 52 LQFP for MC9S12C Family 53 Pin Assignments in 48 LQFP for MC9S12C Family 54 PLL Loop Filter Connections emo RS ECT A nx ei 57 Colpitts Oscillator Connections PE721 s os wee tied eee ERE Deda 59 Pierce Oscillator Connections PE720 cee eee eee eee 59 External Clock Connections PE720 0c eee eee ee eee 59 Clock CONMECHONG Ha uu EE RA donum Pk ee Er elt Ae eee 65 Recommended PCB Layout 48 LQFP aa 74 Recommended PCB Layout 52 LQFP 2022200000 75 Recommended PCB Layout 80 QFP aa 76 Recommended PCB Layout for 48 LQFP Pierce Oscillator 77 Recommended PCB Layout for 52 LQFP Pierce Oscillator 78 Recommended PCB Layout for 80QFP Pierce Oscillator 79 Voltage Regulator Chip Power up and Voltage Drops not scaled 96 ATD Accuracy Definitions e ute oe E eR ERE SO a GNG 104 Basic PLL functional diagram 252 5e DERE EG ias abe nees 112 Jitter DONS o o etre toas Warde reus eee E QU e tu c AAA 114 Maximum bus clock jitter approximation lille 114 SPI Master Timing CPHASO oca Ree a sr nd 119 SPI Master Timing CPHA 1 eos x ve ic nee Se ee ee REPE 120 SPI Slave Timing CPHA 0 0 0 2020 eee 121 SPI Slave Timing CPHA 1 raesent ied oe ape ea ee Rote 122 General External Bus Timing eee eee eee 123 80 pin QFP Mechanical Dimensions
53. 3 DDRT2 DDRT1 DDRTO 0243 RDRT dies RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRTO 0244 PERT We PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERTi PERTO 0245 PPST han PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPSTi PPSTO Read O 0 0 0 0 0 0 0 0246 Reserved Write Read 0 0 0 0247 MODRR Write EN MODRR4 MODRR3 MODRR2 MODRR1 MODRRO 0248 PTS Read 0 0 0 0 pres prs2 ptst PTSO Write 47 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 T ma Read O 0 0 0 PTIS3 PTIS2 PTIS1 PTISO Write 024A DDRS a u DDRS3 DDRS2 DDRS1 DDRSO 024B RDRS a 0 2 RDRS3 RDRS2 RDRS1 RDRSO 024C PERS PN M L PERS3 PERS2 PERS PERSO 024D PPSS a PPSS3 PPSS2 PPSS1 PPSSO 004E WOMS hen i 0 womss WOMS2 woms1 WOMSO Read 0 0 0 0 0 0 0 0 024F Reserved MAE ERES EE E RE ET ESSES 0250 PTM aT PTM5 PTM4 PTM3 PTM2 PTMI PTMO si ER Read 0 0 PTIMS Prima PTIM3 PTIM2 PTIMi PTIMO Write Read 0 0 0252 DDRM io DDRMS DDRM4 DDRMS DDRM2 DDRM DDRMO Read 0 0 0253 ADAM qp ADAMS RDRM4 RDRMS RDRM2 ADAM ADAMO Read 0 0 0254 PERM e PERM5 PERM4 PERM3 PERM2 PERM1 PERMO Read 0 0 0255 PPSM Write epu PPSMS PPSM4 PPSM3 PPSM2 PPSMI PPSMO Read 0 0 0256 WOMM 7 WOMMS WOMM4 WOMMS
54. 4 Temp Options 52LQFP MC9S12C64 MC9S12C64 80QFP 48LQFP MC9S12C64 MC9S12C32 MC9S12C64 MC9S12C32 52LQFP MC9S12C32 MC9S12C32 80QFP 48LQFP MC9S12C32 MC9S12GC128 MC9S12C32 MC9S12GC128 52LQFP MC9S12GC128 MC9S12GC128 80QFP 48LQFP MC9S12GC128 MC9S12GC128 MC9S12GC128 MC9S12GC64 52LQFP MC9S12GC128 MC9S12GC64 80QFP 48LQFP MC9S12GC128 MC9S12GC32 MC9S12GC64 MC9S12GC32 52LQFP MC9S12GC32 MC9S12GC32 80QFP 48LQFP MC9S12GC32 MC9S12GC16 MC9S12GC32 MC9S12GC16 52LQFP MC9S12GC16 MC9S12GC16 80QFP NOTES 1 Maskset dependent errata can be accessed at MC9S12GC16 MC9S12GC16 http e www motorola com wbapp sps site prod_summary jsp 2 C Th 85 C f 25MHz V Ta 105 C f 25MHz M Taz 125 C f 25MHz 3 All C Family derivatives feature 1 CAN 1 SCI 1 SPI an 8 channel A D a 6 channel PWM and an 8 channel timer The GC Family members do not have the CAN module 4 I O is the sum of ports capable to act as digital input or output MC9S12 C32 P C FU 25 Temperature Options C 40 C to 85 C Speed Option V 40 C to 105 C Package Option MA A e EO Tem Package Options Temperature Option FU 80QFP PB 52LQFP Preliminary Option FA 48LOFP T Device Title Controller Family Speed Options 25 25MHz bus 16 16MHz bus Figure 0 1 Order Part number Coding Table 0 3 MC9S12C Fami
55. 48LQFP Port A 7 1 Port B 7 5 Port B 3 0 PortE 6 5 3 2 Port P 7 6 PortP 4 0 Port J 7 6 PortS 3 2 52LQFP Port A 7 3 Port B 7 5 Port B 3 0 PortE 6 5 3 2 Port P 7 6 PortP 2 0 Port J 7 6 PortS 3 2 56 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 2 3 Detailed Signal Descriptions 2 3 1 EXTAL XTAL Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins On reset all the device clocks are derived from the EXTAL input frequency XTAL is the crystal output 2 3 2 RESET External Reset Pin RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known start up state It also acts as an open drain output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 32 ECLK cycles after the low drive is released Upon detection of any reset an internal circuit drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal processing 2 3 3 TEST VPP Test Pin This pin is reserved for test and must be tied to VSS in all applications 2 3 4 XFC PLL Loop Filter Pin Dedicated pin used to create the PLL loop filter See CRG BUG for more detailed information PLL loop filter Pleas
56. 7 PADO6 AN06 PAD0O5 AN05 PAD04 AN04 PADOS ANOS3 PADOZ ANO2 PADO1 ANO1 PADOO ANOO PA2 PA1 PAO Signals shown in Bold italic are not available on the 48 Pin Package 53 Device User Guide 9512C128DGV1 D V01 05 LO Zz E C 0 D x a xx png osx x ox Ek Z0 Z2 o CU 00 S 2 N Oo TO c c o DA DD Z2 gt Z Z ND HN DM a gt SOO O OO O O Os PWO IOCO PTO i VRH PW1 IOC1 PT1 2 VDDA PWA IOC2 PT2 43 PADO7 ANO7 PWS IOC3 PT3 4 PADO6 ANO6 VDD1 95 PADO5 AN05 VSS1 76 MC9S12C Family PADO4 AN04 PW4 IOC4 PT4 17 MC9512GC Family PADOS ANO3 IOC5 PT5 18 PADO2 ANO2 IOC6 PT6 C19 PADO1 ANO1 IOC7 PT7 PADOO ANOO MODC BKGD PAO PB4 XIRQ PEO E O gt gt a cc Figure 2 3 Pin Assignments in 48 LQFP for MC9S12C Family 54 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 2 2 Signal Properties Summary Table 2 1 Signal Properties Internal Pull Pin Name Pin Name Pin Name Power Resistor Function 1 Function 2 Function 3 Domain Reset CITRE State EXTAL VODPLL EEE NA Oscillator pins XTAL VDDPLL 07 VDDX None None External reset pin Description VDDPLL LE UN PLL loop filter pin EEG VSSX Test pin only BKGD MODC TAGHI VDDX n Background debug mode pin tag signal high SBET O NOACC XCLKS VDDX PUCR Up Port E I O pin access clock select While RESET PE6 IPIPE1 pin is low Down Port E I O pin and pipe status While RESET IPIPEO pin is low Down Port
57. 75 13 16 25 19 5 22 75 26 2925 3286 3289 3292 3295 3299 3302 3305 3309 3312 3315 3318 3321 3324 3328 Vin Figure B 2 ATD Accuracy Definitions mV NOTE Figure B 2 shows only definitions for specification values refer to Table B 6 104 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 B 5 NVM Flash and EEPROM B 5 1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator A minimum oscillator frequency fyymosc is required for performing program or erase operations The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured The Flash program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively The frequency of this clock must be set within the limits specified as fyvmop The minimum program and erase times shown in Table B 8 are calculated for maximum fyymop and maximum fhys The maximum times are calculated for minimum fyymop and a fpus of 2MHz B 5 1 1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency f yymop and can be calculated according to the following formula t 29 1 1 qucd Bg hs SUPE fNVMOP f
58. 8 1L09S 3101 MC9512GC16 TBD TBD MC9S12GC32 TBD TBD MC9S12GC64 TBD TBD MC9S12GC128 TBD TBD NOTES 1 The coding is as follows Bit 15 12 Major family identifier Bit 11 8 Minor family identifier Bit 7 4 Major mask set revision number including FAB transfers Bit 3 0 Minor non full mask set revision The device memory sizes are located in two 8 bit registers MEMSIZ0 and MEMSIZ1 addresses 001C and 001D after reset Table 1 4 shows the read only values of these registers Refer to Module Mapping and Control MMC Block Guide for further details Table 1 4 Memory size registers 50 Device Register name Value MEMSIZO 00 M 12GC1 aaa MEMSIZ1 580 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Table 1 4 Memory size registers Device Register name Value MC9512C32 MC9S12GC32 NEN di i MEMSIZ1 580 MC9S12C64 MC9S12GC64 NEN ii MEMSIZ1 SCO MEMSIZO 01 cl MEMSIZ1 SCO MC9512C128 MC9S12GC128 MEMOS iud MEMSIZ1 SCO AR MOTOROLA 51 Device User Guide 9512C128DGV1 D V01 05 Section 2 Signal Description 2 1 Device Pinout 52 PW3 KWP3 PP3 PW2 KWP2 PP2 PW1 KWP1 PP1 PWO KWPO PPO PWO IOCO PTO PW1 10C1 PT1 PW2 10C2 PT2 PW3 10C3 PT3 PW4 10C4 PT4 lOC5 PT5 10C6 PT6 10C7 PT7 MODC TAGHI BKGD ADDRO DATAO PBO ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4 0 NO 01 Corn PP4 KWP4 PW4 PP5 KWP5 PW5 PP7 KWP7
59. BKP map 1 of 1 HCS12 Debug Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0020 PBO bsa DBGEN ARM TRGSEL BEGIN DBGBRK O CAPMOD 0021 DBGSC read AF BF CF 0 TRG write 0022 DBGTBH read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 write 0023 DBGTBL read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O write 0024 DBGCNT read TBF 0 CNT write sus PBGCOA road PAGSEL EXTCMP write 0096 PBGCCH read iiis 14 13 12 11 10 9 Bit 8 write 0007 PBGCCL read pis 6 5 4 3 2 1 Bit O write DBGC2 read 0028 RETO is BKABEN FULL BDM TAGAB BKCEN TAGC RWCEN RWC 0029 OBONI read BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA RWBEN RWB BKPCT1 write DBGCAX read 002A ps Wie PAGSEL EXTCMP DBGCAH read 002B BEPOH write Bit15 14 13 12 11 10 9 Bit 8 36 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 0020 002F DBG including BKP map 1 of 1 HCS12 Debug Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 gopag DBSUAL tead ges 6 5 4 3 2 1 Bit 0 BKPOL write DBGCBX read 002D BKP1X wilt PAGSEL EXTCMP 002E LOU d Bit 15 14 13 12 11 10 9 Bit 8 DBGCBL read 002F BKP1L write Bit 7 6 5 4 3 2 1 Bit O 0030 0031 MMC map 4 of 4 HCS12 Module Mapping Control Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0030 PPAGE ae PIX5 PIX4
60. DOCUMENT NUMBER 9512C128DGV1 D MC9512C Family Device User Guide V01 05 Covers also MC9S12GC Family Original Release Date 25 JAN 2003 Revised 11 FEBRUARY 2004 Motorola Inc Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify an
61. ERS DIM MIN MAX A 7000BSC Al 3 500 BSC LUZ B 7 000 BSC Bl 3 500 BSC C 1 400 1 600 DETAIL Y D 0 170 0270 E 1 350 1 450 F 0 170 0 230 G 0 500 BSC H 0 050 0 150 J 0 090 0 200 K 0 500 0 700 L oe 7 AC M 129REF AB N 0 090 0 160 P 0250BSC PARAAN R 0 150 0 250 S 9 000Bsc SI 4 500BSC v 9 000 BSC VI 4500BSC W 0 200 REF AA 1 000 REF M BASE METAL mi TOP amp BOTTOM c E E cd D Y 6 ooso amp ac v z H SECTION AE AE H Ww 0 250 GAUGE PLANE L o DETAIL AD L K Figure D 3 48 pin LQFP Mechanical Dimensions case no 932 03 ISSUE F 130 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Appendix E Emulation Information E 1 General In order to emulate the MC9S12C and 9S12GC Family devices external addressing of a 128K memory map is required This is provided in a 112 LQFP package version which includes the 3 necessary extra external address bus signals via PortK This package version is for emulation only and not provided as a general production package PW3 KWP3 PP3 PW2 KWP2 PP2 PW1 KWP1 PP1 PWO KWPO PPO NC XADDR16 PK2 XADDR15 PK1 XADDR14 PK0 IOCO PTO 10C1 PT1 10C2 PT2 NC MODC TAGHI BKGD ADDRO DATAO PBO ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4 AR MOTOROLA 12 C PP4 KWP4 PW4 11 C PP5 KPW5 PWM 95 4 PP6 KWP6 ROMONE 94 NC 00 CO PM5 SCK 99 3 PJ6 KWJ6 98 3
62. FCNFG Naa CBEIE cor kevaco 0 BKSELI BKSELO 80104 FPROT Men FPOPEN NV6 FPHDIS FPHS1 FPHSO FPLDIS FPLS1 FPLSO 0105 FSTAT han cBEF CCF pro ACCERR h BLANK LO 0106 FCMD nd CMDB6 cmpps Y 0 CMDB2 LS cmo Reserved for Read 0 0 0 0 0 0 0 0 10005 Factory Test Write Reserved for Read 0 0 0 0 0 0 0 0 2D Factory Test Write Reserved for Read 0 0 0 0 0 0 0 0 20103 Factory Test Write Reserved for Read 0 0 0 0 0 0 0 0 RONDA Factory Test Write Reserved for Read 0 0 0 0 0 0 0 0 PUB Factory Test Write 44 AR MOTOROLA 0100 010F Address 010C 010D 010E 010F Name Reserved Reserved Reserved Reserved 0110 013F 0110 003F Reserved 0140 017F Address 0140 0141 0142 0143 0144 0145 0146 0147 0148 0149 014A 014B 014C 014D AR MOTOROLA Name CANCTLO CANCTL1 CANBTRO CANBTR1 CANRFLG CANRIER CANTFLG CANTIER CANTARQ CANTAAK CANTBSEL CANIDAC Reserved Reserved Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Flash Control Register Device User Guide 9512C128DGV1 D V01 05
63. FP 16MHz Preliminary C96 using C128 die MC9S12C96CFA16 TBD 40 C 85 C 48LQFP 16MHz Final C96 using C96 die MC9S12C96CPB16 TBD 40 C 85 C 52LQFP 16MHz Final C96 using C96 die MC9S12C96CFU16 TBD 40 C 85 C 80QFP 16MHz Final C96 using C96 die MC9S12C96PVFA16 OLO9S 40 C 105 C 48LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PVPB16 OLO9S 40 0 105 C 52LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PVFU16 OLO9S 40 C 105 C 80QFP 16MHz Preliminary C96 using C128 die MC9S12C96VFA16 TBD 40 C 105 C 48LQFP 16MHz Final C96 using C96 die MC9S12C96VPB16 TBD 40 C 105 C 52LQFP 16MHz Final C96 using C96die MC9S12C96VFU16 TBD 40 C 105 C 80QFP 16MHz Final C96 using C96 die MC9S12C96PMFA16 OLO9S 40 C 125 C 48LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PMPB16 OLO9S 40 C 125 C 52LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PMFU16 OLO9S 40 C 125 C 80QFP 16MHz Preliminary C96 using C128 die MC9S12C96MFA16 TBD 40 C 125 C 48LQFP 16MHz Final C96 using C96 die MC9S12C96MPB16 TBD 40 C 125 C 52LQFP 16MHz Final C96 using C96 die MC9S12C96MFU16 TBD 40 C 125 C 80QFP 16MHz Final C96 using C96 die MC9S12C96PCFA25 OLO9S 40 C 85 C 48LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PCPB25 OLO9S 40 C 85 C 52LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PCFU25 OLO9S 40 C 85 C 80QFP 25MHz Preliminary C96 using C128 die MC9S12C96CFA25 TBD 40 C 85 C 48LQFP 25MHz Final
64. Function 2 Function 3 Domain Description ELZA KWP 2 0 ESSA VDDX POP Disabled Port P I O Pins keypad wake up PWM outputs PJ 7 6 KWJ 7 6 Disabled Port J I O Pins and keypad wake up PM5 SCK Port M I O Pin and SPI SCK signal Port M I O Pin and SPI MOSI signal Port M I O Pin and SPI SS signal PERM Up Port M I O Pin and SPI MISO signal PERM 4 Up Port M I O Pin and CAN transmit signal Port M I O Pin and CAN receive signal PS 3 2 Port S I O Pins PS1 TXD Port S I O Pin and SCI transmit signal RXD Port S I O Pin and SCI receive signal EN PSO PERT f are PT 7 5 IOC 7 5 VDDX PPST Disabled Port T I O Pins shared with timer TIM PERT f T PT 4 0 IOC 4 0 PW 4 0 VDDX PPST Disabled Port T I O Pins shared with timer and PWM NOTES 1 The PortE output buffer enable signal control at reset is determined by the PEAR register and is mode dependent E g in special test mode RDWE LSTRE 1 which enables the PE 3 2 output buffers and disables the pull ups Refer to S12 MEBI user guide for PEAR register details 2 CAN functionality is not available on the MC9S12GC Family members 2 2 1 Pin Initialization for 48 amp 52 Pin LOFP bond out versions Not Bonded Pins If the port pins are not bonded out in the chosen package the user should initialize the registers to be inputs with enabled pull resistance to avoid excess current consumption This applies to the following pins
65. GC16 die MC9S12GC16PVFA25 1L45J 40 C 105 C 48LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PVPB25 1L45J 40 C 105 C 52LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PVFU25 1L45J 40 C 105 C 80QFP 25MHz Preliminary GC16 using C32 die MC9S12GC16VFA25 TBD 40 C 105 C 48LQFP 25MHz Final GC16 using GC16 die MC9S12GC16VPB25 TBD 40 C 105 C 52LQFP 25MHz Final GC16 using GC16 die 20 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Mask Part Number set Temp Package Speed Description MC9S12GC16VFU25 TBD 40 C 105 C 80QFP 25MHz Final GC16 using GC16 die MC9S12GC16PMFA25 1L45J 40 C 125 C 48LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PMPB25 1L45J 40 C 125 C 52LQFP 25MHz Preliminary GC16 using C32 die MC9512GC16PMFU25 1L45J 40 C 125 C 80QFP 25MHz Preliminary GC16 using C32 die MC9S12GC16MFA25 TBD 40 C 125 C 48LQFP 25MHz Final GC16 using GC16 die MC9512GC16MPB25 TBD 40 C 125 C 52LQFP 25MHz Final GC16 using GC16 die MC9S12GC16MFU25 TBD 40 C 125 C 80QFP 25MHz Final GC16 using GC16 die Table 0 5 Document References User Guide Version Document Order Number CPU12 Reference Manual V02 S12CPUV2 D HCS12 Debug DBG Block Guide V01 S12DBGV1 D HCS12 Background Debug BDM Block Guide V04 S12BDMV4 D HCS12 Module Mapping Control MMC Block Guide V04 S12MMCV4 D HCS12 Multiplexed External Bus Interface MEBI Block Guide Vos
66. L pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal Table 4 1 Mode Selection BKGD PE6 PE5 PP6 ROMON nti MODC MODB MODA ROMCTL Bit Mode Description Special Single Chip BDM allowed and ACTIVE BDM is 0 0 0 X allowed in all other modes but a serial command is required to make BDM active 0 1 0 0 1 1 0 Emulation Expanded Narrow BDM allowed 0 1 0 X 0 Special Test Expanded Wide BDM allowed 0 1 0 1 1 1 T Emulation Expanded Wide BDM allowed 1 0 0 X 1 Normal Single Chip BDM allowed 0 0 1 0 1 1 1 Normal Expanded Narrow BDM allowed Peripheral BDM allowed but bus operations would cause 1 1 0 X 1 bus conflicts must not be used 0 0 1 1 1 1 1 Normal Expanded Wide BDM allowed For further explanation on the modes refer to the S12 MEBI block guide Table 4 2 Clock Selection Based on PE7 PE7 XCLKS Description 1 Colpitts Oscillator selected O PereeOscilarexemaldskseeded 4 3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents This feature allows e Protection of the contents of FLASH Operation in single chip mode e Operation from external memory with internal FLASH disabled The user must be reminded that part of the security must lie with the user s code An extreme example would be user s code that dumps the contents of the internal program This
67. MC9S12GC32CFU25 TBD 40 C 85 C 80QFP 25MHz Final GC32 using GC32 die MC9S12GC32PVFA25 1L45J 40 C 105 C 48LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PVPB25 1L45J 40 C 105 C 52LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PVFU25 1L45J 40 C 105 C 80QFP 25MHz Preliminary GC32 using C32 die MC9S12GC32VFA25 TBD 40 C 105 C 48LQFP 25MHz Final GC32 using GC32 die MC9S12GC32VPB25 TBD 40 C 105 C 52LQFP 25MHz Final GC32 using GC32 die MC9S12GC32VFU25 TBD 40 C 105 C 80QFP 25MHz Final GC32 using GC32 die MC9S12GC32PMFA25 1L45J 40 C 125 C 48LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PMPB25 1L45J 40 C 125 C 52LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PMFU25 1L45J 40 C 125 C 80QFP 25MHz Preliminary GC32 using C32 die MC9S12GC32MFA25 TBD 40 C 125 C 48LQFP 25MHz Final GC32 using GC32 die MC9S12GC32MPB25 TBD 40 C 125 C 52LQFP 25MHz Final GC32 using GC32 die MC9S12GC32MFU25 TBD 40 C 125 C 80QFP 25MHz Final GC32 using GC32 die MC9S12GC16PCFA25 1L45J 40 C 85 C 48LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PCPB25 1L45J 40 C 85 C 52LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PCFU25 1L45J 40 C 85 C 80QFP 25MHz Preliminary GC16 using C32 die MC9S12GC16CFA25 TBD 40 C 85 C 48LQFP 25MHz Final GC16 using GC16 die MC9S12GC16CPB25 TBD 40 C 85 C 52LQFP 25MHz Final GC16 using GC16 die MC9S12GC16CFU25 TBD 40 C 85 C 80QFP 25MHz Final GC16 using
68. PE7 NOACC XCLKS Port E I O Pin 7 PE7 is a general purpose input or output pin During MCU expanded modes of operation the NOACC signal when enabled is used to indicate that the current bus cycle is an unused or free cycle This signal will assert when the CPU is not using the bus The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts low power oscillator is used or whether Pierce oscillator external clock circuitry is used The state of this pin is latched at the rising edge of RESET If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator If input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL Since this pin is an input with a pull up device during reset if the pin is left floating the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL 58 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 EXTAL Coc MCU C EC Orystalor ceramic resonator XTAL Co VSSPLL Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC Figure 2 5 Colpitts Oscillator Connections PE7 1 EXTAL t Cj Meu Rg L Crystal or ceramic resonator XTAL E d 2 E VSSPLL Rs can be zero shorted when use with higher frequency crystals
69. PJ7 KWJ7 97 INC 96L INC 93 INC 92 IPS3 91 IPS2 90 I PS1 TXD 89 IPSO RXD 88 INC 87 LaNC 86 CO VSSA 85 CO VRL Fe ah m O quae a aO ee E MC9S12C Family MC9S12GC Family Signals shown in Bold are Figure 19 1 Pin Assignments in 112 pin LQFP O Ai a c N or co si 10 Cd 00 00 O 20 C 00 O O co s Ub LO LO LO moor N CO WwW st F po e ae DQ NT O mamugo9eeguauuunms5suiugdzazugeeeg9emusiutmu aaa Laca dana RRM nao aX a x x e 2000 O ON O ovliljiu ce l Ol O O LLT e uu co Y iS ER EEE ZLLO gt Doce aaa Qaa E Moor oO coo ans B aga SABE fc aoo aALs 5 II Q 4 VRH VDDA NC PADO7 ANO7 NC PADO6 AN06 NC PADOS ANO5 NC PADO4 ANO4 NC PAD03 AN03 NC PAD02 AN02 NC PADO1 ANO1 NC PADOO ANOO VSS2 VDD2 PA7 ADDR15 DATA15 PAG ADDR14 DATA14 PAS ADDR13 DATA13 PA4 ADDR12 DATA12 PAS ADDR1 1 DATA11 PA2 ADDR10 DATA10 PA1 ADDR9 DATA9 PAO ADDR8 DATA8 available only in the 112 Pin Package Pins marked NC are not connected 131 Device User Guide 9512C128DGV1 D V01 05 E 1 1 PK 2 0 XADDR 16 14 PK2 PKO provide the expanded address XADDR 16 14 for the external bus Refer to the S12 Core user guide for detailed information about external address page access Internal Pull Pin Name PinName Power Resistor Function 1 Function2 Domain PK 2 0 XADDR 16 14 VDDX PUPKE Up Port K I O Pins The reset state of DDRK in the S12 CORE is 00 configu
70. ROMON is set Table 6 1 Device Specific Flash PAGE Mapping Device PAGE PAGE visible with PPAGE contents MC9S12GC16 3F 00 01 02 03 04 05 06 07 08 09 36 37 38 39 3A 3B 3C 3D 3E 3F MC9S12C32 3E 00 02 04 06 08 0A 0C 0E 10 12 2C 2E 30 32 34 36 38 3A 3C 3E MC9S12GC32 3F 01 03 05 07 09 0B 0D 0F 11 13 52D 2F 31 33 35 37 39 93B 3D 3F 3C 00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C MC9S12C64 3D 01 05 09 0D 11 915 19 1D 21 25 29 2D 31 35 39 93D MC9S12GC64 3E 02 06 0A 0E 12 16 1A 1 E 22 26 2A 2E 32 36 3A 3E 3F 03 07 0B 0F 13 17 1B 1F 23 27 2B 2F 33 37 3B 3F 3A 00 02 08 0A 10 12 18 1A 20 22 28 2A 30 32 38 3A 3B 01 03 09 0B 1 1 13 19 1B 21 23 29 2B 31 33 39 3B 3C 04 0C 14 1C 24 2C 34 3C MESSI SOS 3D 05 0D 15 1D 25 2D 35 3D 3E 06 0E 16 1E 26 2E 36 3E 3F 07 0F 17 1F 27 2F 37 3F 38 00 08 10 18 20 28 30 38 39 01 09 1 1 19 21 29 31 39 3A 02 0A 12 1A 22 2A 32 3A MC9S12C128 3B 03 0B 13 1B 23 2B 33 3B MC9S12GC128 3C 04 0C 14 1C 24 2C 34 3C 3D 05 0D 15 1D 25 2D 35 3D 3E 06 0E 16 1E 26 2E 36 3E 3F 07 0F 17 1F 27 2F 37 3F 6 1 2 BDM alternate clock The BDM section of S12 Core User Guide reference to alternate clock is equivalent to oscillator clock 6 1 3 Extended A
71. SCAN is not available on the 9812GC Family Members RXCAN PMO TXCAN PM1 PM2 NMN Q Q 10 t o mo Rou t CO O RS i5 OTN O e Ne O00 NOD TON T O PM5 tc C C Cc c c E c E tC CC c C c c c agaqagaaagaga oa aa ad d agaqaqqaagaq AAAOAAAAA qff qqqqIqq AAA Muipeedz SX XR RELIRA T EEE j i Wide Bus lt E lt E lt 33 lt E lt E lt E lt 4 lt Signals shown in Bold are not available on the 52 or 48 Pin Package MORAN TG TO NG BG a Rate Lo Signals shown in Bold Italic are available in the 52 but not the 48 Pin Package Internal Logic 2 5V 1 O Driver 5V VDD1 2 VDDX VSS1 2 VSSX HE l PLL 2 5V A D Converter 5V VRL is bonded internally to VSSA VDDPLL VDDA for 52 and 48 Pin packages VSSPLL i a NT Voltage Regulator 5V amp I O VDDR VSSR ak AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 1 5 Device Memory Map Table 1 1 shows the device register map of the MC9S12C Family after reset The following figures Figure 1 2 Figure 1 2 Figure 1 3 and Figure 1 4 illustrate the full device memory map with flash and RAM 28 Table 1 1 Device Register Map Overview Address Module Size 000 017 CORE Ports A B E Modes Inits Test 24 018 Reserved 1 019 Voltage Regulator VREG 1 01A 01B Device ID register 2 01C 01F CORE MEMSIZ IRQ HPRIO 4 020 02F CORE DBG 16 030 033 CORE PPAGE
72. SQ RXD Por SVO PIN tate esa cons ote ein PLAN PECES 63 PPT Z 5 IOC 7 5 Port T I O Pins 7 5 a ug ce oe oco dos eR DAG Eine 63 PT 4 0 IOC 4 0 PW 4 0 Port T I O Pins 4 0 63 Power SIRIOS a Rp rate eo o i te de NIE NER RE 63 VDDX VSSX Power Ground Pins for I O Drivers 63 VDDR VSSR Power Ground Pins for I O Drivers 8 for Internal Voltage Regulator VDD1 VDD2 VSS1 VSS2 Internal Logic Power Pins 63 VDDA VSSA Power Supply Pins for ATD and VREG 64 VRH VRL ATD Reference Voltage Input Pins 64 VDDPLL VSSPLL Power Supply Pins for PLL a 64 Section 3 System Clock Description Section 4 Modes of Operation 4 1 4 2 4 3 4 3 1 4 3 2 4 3 3 4 4 4 4 1 4 4 2 4 4 3 4 4 4 ONE PE Wet ot aae a SSE vt a NIAN ABO od MA NAG MAG pics A 65 Chip Configuration Summary ssa e eet eves Saks UP dete oe Eden 65 SOS CUNY cocta ou aset Lee Et T repe RON GG DEO TE 66 Securing the Microcontroller sui un ad mE b ESO bs edt ase ress ees 67 Operation of the Secured Microcontroller o oooooooooooooo 67 Unsecuting the Microcontroller paaa apa arestas ETE S Sa ERE 67 erae dtes aha due a ad ka e e O ete PA att KA e kan Ok bledo y E 67 SIOD aa eA IA di 68 Pseudo Stopnia 2 ngs Ace a Pa a a Miedo bab ted DRA beri ud 2 68 LI MEM CP 68 Us lA ae e c D ange LM e Me d e ene deere AG Ba 68 S
73. Sector Size is 1024 Bytes Figure 1 2 MC9S12C128 and MC9S12GC128 User configurable Memory Map AR MOTOROLA 29 Device User Guide 9512C128DGV1 D V01 05 0000 1K Register Space PAGE MAP 0000 S03FF Mappable to any 2K Boundary 0400 0000 16K Fixed Flash EEPROM FFF 3FFF 3D X 3000 4K Bytes RAM 3000 F5 x y PS 4 3FFF Mappable to any 4K Boundary 4000 E 4000 16K Fixed Flash EEPROM 3E 7FFF 8000 gt 8000 16K Page Window 6 16K Flash EEPROM Pages PPAGE BFFF G000 6000 16K Fixed Flash EEPROM 3F FFFF a FF00 BDM EI A mE If Active Free VECTORS J FFFF NORMAL EXPANDED SPECIAL SINGLE CHIP SINGLE CHIP The figure shows a useful map which is not the map out of reset After reset the map is non OFE Register Space 0000 0FFF 4K RAM only 3K visible 0400 SOFFF Flash Erase Sector Size is 1024 Bytes Figure 1 3 MC9512C96 User Configurable Memory Map 30 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 0000 1K Register Space PAGE MAP 0000 S03FF Mappable to any 2K Boundary S0400 0000 16K Fixed Flash EEPROM 3FFF 3000 4K Bytes RAM 93D Z es 3000 gt X y PS 4 3FFF Mappable to any 4K Boundary 4000 E 4000 16K Fixed Flash EEPROM 3E 7FFF 8000 gt 8000 16K Page Window 4 16K Flash EEPROM Pages PPAGE BFFF G000 6000 16K Fixed Flash EEPROM F FFFF ba FF00 BDM E If Active Free
74. T map 2 of 2 HCS12 Interrupt 36 0020 002F DBG including BKP map 1 of 1 HCS12 Debug 36 0030 0031 MMC map 4 of 4 HCS12 Module Mapping Control 37 0032 0033 MEBI map 3 of 3 HCS12 Multiplexed External Bus Interface 37 0034 003F CRG Clock and Reset Generator 37 0040 006F TIM Timer 16 Bit 8 Channels 38 0070 007F Reserved 40 0080 009F ATD Analog to Digital Converter 10 Bit 8 Channel 40 00A0 00C7 Reserved 41 00D0 00D7 Reserved 42 00C8 00CF SCI Asynchronous Serial Interface 42 00D8 00DF SPI Serial Peripheral Interface 42 00E0 00FF PWM Pulse Width Modulator 43 0100 010F Flash Control Register 44 0110 013F Reserved 45 0140 017F CAN Motorola Scalable CAN MSCAN 45 Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout 46 AR MOTOROLA 11 Device User Guide 9512C128DGV1 D V01 05 0180 023F Reserved 47 0240 027F PIM Port Interface Module 47 0280 03FF Reserved space 50 Table 1 3 Assigned Part ID Numbers 22 ere 50 Table 1 4 Memory size registers ees 50 Table 2 1 Signal Propetlles 2255 ANAL E bret eee AUR Erin ee nb RES 55 Table 2 2 MC9S12C Family Power and Ground Connection Summary 64 Table 4el Mode Selecione cendo aaa a BE ee Re 66 Table 4 2 Clock Selection Based on PE7 a 66 Table 5 1 Interrupt Vector Locations iue x EE ut tert ee rU cs 68 Table 5 2 ReSet Sumimaly ipod Bk ee
75. User Guide 9512C128DGV1 D V01 05 Figure B 4 Jitter Definitions The relative deviation of ty iS at its maximum for one clock period and decreases towards zero for larger number of clock periods N Defining the jitter as 4 max ND N t nom N t nom J N mad tmin N For N 100 the following equation is a good fit for the maximum jitter ho XN ij JN J N 1 5 10 20 N Figure B 5 Maximum bus clock jitter approximation 114 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 This is very important to notice with respect to timers serial modules where a pre scaler will eliminate the effect of the jitter to a large extent Table B 12 PLL Characteristics Conditions are shown in Table A 4 unless otherwise noted COI TN Gpmbei him Te Mec uc Dr epo num mu 01 a um 2 VCO locking range fvco 8 50 3 Lock Detector transition from Acquisition to Tracking rel 3 4 mode Lock Detection IALockl 1 5 ED man Cata e Lock Detector transition from Tracking to Acquisition Aung mode PLLON Total Stabilization delay Auto Mode 2 tstab PLLON Acquisition mode stabilization delay tacg PLLON Tracking mode stabilization delay 2 ta Drs Fra pat VO cp a E IO mr Fitting parameter VCO loop frequency Charge pump current acquisition mode lich 38 5 Charge pump current tracking mode ien 3 5 Pla tat 1 Tol 0 13 15 C Jitter fit parameter 22 j2 NOTES
76. VECTORS FFFF NORMAL EXPANDED SPECIAL SINGLE CHIP SINGLE CHIP The figure shows a useful map which is not the map out of reset After reset the map is non OFE Register Space 0000 0FFF 4K RAM only 3K visible 0400 SOFFF Flash Erase Sector Size is 1024 Bytes Figure 1 4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map AR MOTOROLA 31 Device User Guide 9512C128DGV1 D V01 05 0000 1K Register Space PAGE MAP 0000 03FF Mappable to any 2K Boundary um X 3800 2K Bytes RAM 3800 F5 x y PS 4 3FFF Mappable to any 2K Boundary 4000 an 8000 E 8000 16K Page Window 2 16K Flash EEPROM Pages PPAGE BFFF G000 6000 16K Fixed Flash EEPROM F FFFF FF00 BDM E If Active Free VECTORS FFFF NORMAL EXPANDED SPECIAL SINGLE CHIP SINGLE CHIP The figure shows a useful map which is not the map out of reset After reset the map is 30000 SOFE Register Space 0800 0FFF 2K RAM Flash Erase Sector Size is 512 Bytes Figure 1 5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map 32 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 0000 0000 1K Register Space PAGE MAP 03FF Mappable to any 2K Boundary 0400 PN 53800 Z x KA X Na 3800 2K Bytes RAM o 4 SASSSA KX NON 3FFF Mappable to any 2K Boundary 4000 8000 PPAGE C000 16K Fixed Flash EEPROM 3F BDM E If Active
77. a data write and data read cycle are shown only one or the other would occur on a particular bus cycle C 3 1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions The timing parameters shown assume a balanced load across all outputs Figure C 5 General External Bus Timing ECLK PE4 Addr Data read PA PB Addr Data write PA PB PIPOO PIPO1 PE6 5 AR MOTOROLA 123 Device User Guide 9512C128DGV1 D V01 05 Table C 4 Expanded Bus Timing Characteristics BV Range Conditions are 4 75V lt VDDX lt 5 25V Junction Temperature 40 C to 140 C Cj pan 50pF Num C Rating Symbol Min Typ Max Unit 1 P Frequency of operation E clock fo 0 25 0 MHz 2 P Cycle time toye 40 ns 3 D Pulse width E low PWEL 19 ns 4 D Pulse width E high PWen 19 Hs 5 D Address delay time tap 8 ns 6 D Address valid time to E rise PWe tap tav 11 ns 7 D Muxed address hold time tMAH 2 ns 8 D Address hold to data valid taHDS 7 ns 9 D Data hold to address tDHA 2 ns 10 D Read data setup time tpsn 13 ns 11 D Read data hold time tDHR 0 ns 12 D Write data delay time toow 7 ns 13 D Write data hold time tpuw 2 ns 14 D Write data setup time PWe toow tpsw 12 ns 15 D Address access time t tAp tpsg tacca 19 ns 16 D Ehigh access time PWey tpsa tacce 6 ns 17 D Read wr
78. a general purpose input or output pin and also the slave select pin SS for the Serial Peripheral Interface SPI 2 3 24 PM2 MISO Port M I O Pin 2 PM2 is a general purpose input or output pin and also the master input during master mode or slave output during slave mode pin for the Serial Peripheral Interface SPI 2 3 25 PM1 TXCAN Port M I O Pin 1 PMI is a general purpose input or output pin and the transmit pin TXCAN of the CAN module if available 2 3 26 PMO RXCAN Port M I O Pin 0 PMO is a general purpose input or output pin and the receive pin RXCAN of the CAN module if available 62 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 2 3 27 PS 3 2 Port S I O Pins 3 2 PS3 and PS2 are general purpose input or output pins These pins are not available in the 48 52 pin package versions 2 3 28 PS1 TXD Port S I O Pin 1 PS1 is a general purpose input or output pin and the transmit pin TXD of Serial Communication Interface SCD 2 3 29 PS0 RXD Port S I O Pin 0 PS0 is a general purpose input or output pin and the receive pin RXD of Serial Communication Interface SCD 2 3 30 PPT 7 5 IOC 7 5 Port T I O Pins 7 5 PT7 PTS are general purpose input or output pins They can also be configured as the timer system input capture or output compare pins IOC7 IOC5 2 3 31 PT A 0 IOC 4 0 PW 4 0 Port T I O Pins 4 0 PT4 PTO are general purpose input or outp
79. ash based Industrial Automotive network control MCU family Members of the MC9S12C Family and the MC9S12GC Family deliver the power and flexibility of our 16 Bit core CPU12 family to a whole new range of cost and space sensitive general purpose Industrial and Automotive network applications All MC9S12C Family and MC9S12GC Family members are comprised of standard on chip peripherals including a 16 bit central processing unit CPU12 up to 128K bytes of Flash EEPROM up to 4K bytes of RAM an asynchronous serial communications interface SCI a serial peripheral interface SPI an 8 channel 16 bit timer module TIM a 6 channel 8 bit Pulse Width Modulator PWM an 8 channel 10 bit analog to digital converter ADC The MC9S12C Family members also feature a CAN 2 0 A B software compatible module MSCAN12 The MC9S12C Family as well as the MC9S12GC Family has full 16 bit data paths throughout The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements In addition to the I O ports available in each module up to 10 dedicated I O port bits are available with Wake Up capability from STOP or WAIT mode The MC9S12C Family and the MC9S12GC Family devices are available in 48 52 and 80 pin QFP packages with the 80 Pin version pin compatible to the HCS12 A B and D Family derivatives 1 2 Features e 16 bit HCS12 CORE HCS12 CPU i Upward compatible with M68HC1 1 instruction set ii I
80. ator and the clock quality check are started If after a time t907 no valid oscillation is detected the MCU will start using the internal self clock The fastest startup time possible is given by Nypose B 6 1 2 LVR The release level Vy ypg and the assert level Vj yp A are derived from the Vpp Supply They are also valid if the device is powered externally After releasing the LVR reset the oscillator and the clock quality check are started If after a time tco our no valid oscillation is detected the MCU will start using the internal self clock The fastest startup time possible is given by N pose B 6 1 3 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU preventing the CPU from executing code when VDDS is out of specification limits the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set 109 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 B 6 1 4 External Reset When external reset is asserted for a time greater than PWpsry the CRG module generates an internal reset and the CPU starts fetching the reset vector without doing a clock quality check if there was an oscillation before reset B 6 1 5 Stop Recovery Out of STOP the controller can be woken up by an external interrupt A clock quality check as after POR is performed before releasing the clocks to the system B 6 1 6 Pseudo Stop and Wait Recovery The recove
81. chanical AR MOTOROLA Dimensions case no 841B 133 Device User Guide 9512C128DGV1 D V01 05 134 M MOTOROLA Device User Guide End Sheet AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 135 Device User Guide 9512C128DGV1 D V01 05 FINAL PAGE OF 136 PAGES 136 AR MOTOROLA
82. d Ej pjEje e E Write 026F PIFJ Read py PIFJ 0 i Write 0270 PTAD jon PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTADO 0271 PTIAD Read PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIJ7 Write 0272 DDRAD ie DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRADO 0273 RDRAD his RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRADO 0274 PERAD Haha PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERADO 0275 PPSAD je PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSADO 0270 meserved Read O 0 0 0 0 0 0 0 027F Write AR MOTOROLA 49 Device User Guide 9512C128DGV1 D V01 05 0280 03FF Address 0280 2FF 0300 03FF Name Reserved Unimplemented Reserved space Bit 7 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Read 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 Write 1 7 Part ID Assignments The part ID is located in two 8 bit registers PARTIDH and PARTIDL addresses 001A and 001B after reset The read only value is a unique part ID for each revision of the chip Table 1 3 shows the assigned part ID numbers Table 1 3 Assigned Part ID Numbers Device Mask Set Number Part ID MC9512C32 0L45J 3300 MC9512C32 1L45J 3300 MC9512C32 2L45J 3302 MC9S12C64 TBD TBD MC9S12C96 TBD TBD MC9S12C128 OLO9S 3100 MC9S12C12
83. d hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and AN are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer o Motorola Inc 2002 AR MOTOROLA 1 Revision History Device User Guide 9512C128DGV1 D V01 05 Version Number Revision Date Effective Date Author Description of Changes 00 01 00 02 00 03 00 04 00 05 25 JAN 03 07 FEB 03 25 FEB 03 15 APR 03 05 MAY 03 25 JAN 03 07 FEB 03 25 FEB 03 15 APR03 05 MAY 03 Original Version Based on C32 user guide version 01 12 Enhanced PortK description Part number table revision in preface QFP112 Emulation pinout correction Enhanced part number explanation in preface Reduced pseudo STOP current spec for C64 C96 C128 Enhanced PortAD signal description Corrected VDDR description in 2 4 2 Revised pin leakage in electrical parameters SPI timing parameter table correction Output drive high value reduced in 3V range PE 4 2 Pull Up spec out of reset changed 3V Expansion bus timing parameters not tested in production
84. ddress Range Emulation Implications In order to emulate the MC9S12GC or MC9S12C Family devices external addressing of a 128K memory map is required This is provided in a 112 LQFP package version which includes the 3 necessary extra external address bus signals via PortK 2 0 This package version is for emulation only and not provided as a general production package The reset state of DDRK is 00 configuring the pins as inputs The reset state of PUPKE in the PUCR register is 1 enabling the internal PortK pullups In this reset state the pull ups provide a defined state and prevent a floating input thereby preventing unnecessary current flow at the input stage AR MOTOROLA 71 Device User Guide 9512C128DGV1 D V01 05 To prevent unnecessary current flow in production package options the states of DDRK and PUPKE should not be changed by software Section 7 Voltage Regulator VREG Block Description Consult the VREG Block User Guide for information about the dual output linear voltage regulator 7 1 Device specific information The VREG is part of the IPBus domain 7 1 1 VREGEN VREGEN is connected internally to VDDR 7 1 2 VDD1 VDD2 VSS1 VSS2 In the 80 pin QFP package versions both internal VDD and VSS of the 2 5V domain are bonded out on 2 sides of the device as two pin pairs VDD1 VSS1 amp VDD2 VSS2 VDD1 and VDD2 are connected together internally VSS1 and VSS2 are connected together internally The extra
85. e User Guide 9512C128DGV1 D V01 05 Table A 9 Supply Current Characteristics for MC9S12C64 MC9S12C96 MC9S12C128 Conditions are shown in Table A 4 with internal regulator enabled unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Run Supply Current Single Chip Ipps 45 mA Wait Supply current All modules enabled 33 2 Ippw mA DTOTVTOTVOTO VDDR lt 4 9V only RTI enabled VDDR gt 4 9V only RTI enabled Pseudo Stop Current RTI and COP disabled 2 9 40 C 27 C 85 C C Temp Option 100 C 105 C V Temp Option 120 C 125 C M Temp Option 140 C Pseudo Stop Current RTI and COP enabled 3 40 C 27 C 85 C 105 C 125 C NOTES DTOTOTVOTVO Stop Current 9 40 C 27 C 85 C C Temp Option 100 C 105 C V Temp Option 120 C 125 C M Temp Option 140 C 1 STOP current measured in production test at increased junction temperature hence for Temp Option C the test is carried out at 100 C although the Temperature specification is 85 C Similarly for v and M options the temperature used in test lies 15 C above the temperature option specification 2 PLL off 3 At those low power dissipation levels T Ta can be assumed 94 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Appendix B Electrical Specifications B 1 Voltage Regulator Operating Conditions Table B 1 Voltage Regulator Electrical Parameters EE Characteristic
86. e ask your Motorola representative for the interactive application note to compute PLL loop filter elements Any current leakage on this pin must be avoided XFC R ll MCU zs VDDPLL VDDPLL Figure 2 4 PLL Loop Filter Connections AR MOTOROLA 57 Device User Guide 9512C128DGV1 D V01 05 2 3 5 BKGD TAGHI MODC Background Debug Tag High amp Mode Pin The BKGD TAGHI MODC pin is used as a pseudo open drain pin for the background debug communication In MCU expanded modes of operation when instruction tagging is on an input low on this pin during the falling edge of E clock tags the high half of the instruction word being read into the instruction queue It is also used as a MCU operating mode select pin at the rising edge during reset when the state of this pin is latched to the MODC bit 2 3 6 PA 7 0 ADDR 15 8 DATA 15 8 Port A I O Pins PA7 PAO are general purpose input or output pins In MCU expanded modes of operation these pins are used for the multiplexed external address and data bus PA 7 1 pins are not available in the 48 package version PA 7 3 are not available in the 52 pin package version 2 3 7 PB 7 0 ADDR 7 0 DATA 7 0 Port B I O Pins PB7 PBO are general purpose input or output pins In MCU expanded modes of operation these pins are used for the multiplexed external address and data bus PB 7 5 and PB 3 0 pins are not available in the 48 nor 52 pin package version 2 3 8
87. ection 5 Resets and Interrupts AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 5 1 OVETVIGW asno e Dt sp la NAAN oi IR Ae nga pm EE a ate puit Ke eo o anal Ad 68 B2 NOO aah ou Hans od Retos pue A ae ee Se 68 5 2 1 Vector Tales Dee ara naa mg yh MG 5 049 Aster Merida vic edt AD GA robe mad Jo cr A obe 68 Sax TOSS i ecd wa Serio hs DA KAN np BATA BA a aec ctr ro hace s 4 69 5 3 1 Reset Summary Table s xau t kx ope ule RE EE QUEE BANA SE ta 70 5 3 2 Effects O Reset ui cases BAAL AN DEL eo d eade ERE Rei ees 70 Section 6 HCS12 Core Block Description 6 1 Device specific information usas a ped NA ARANGKADA GL E duda IR Re NGA 70 6 1 1 PPAGE ss 2293 eek Peete NAA ANA n a desde dd Ve pede un pt an ris 70 6 1 2 BOM alienate COCK Saara a tait oett e NE NA dot peus st CE iS 71 6 1 3 Extended Address Range Emulation Implicati0nS 71 Section 7 Voltage Regulator VREG Block Description 7 1 Device specific information usn ase toe ethos oli E ERR E han eost d 72 7 1 1 VREGEN a Sn Ma pete ae EE MM E HE 72 7 1 2 VIDT VDD2 VOS VIDA eui io ABA t Eu sb Uo etn SES 72 Section 8 Recommended Printed Circuit Board Layout Section 9 Clock Reset Generator CRG Block Description 9 1 Device specific information s seres pb DERE ad 79 9 1 1 Pis B C DOPO DIU CURT 80 Section 10 Oscillator OSC Block Description Section 11 Timer TIM Block Description Section 12 Analog to Digital Converter ATD Block De
88. ements depend on MCU pin load Section 3 System Clock Description 64 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules Figure 3 1 shows the clock connections from the CRG to all modules Consult the CRG Block User Guide for details on clock generation EXTAL XTAL oscillator clock core clock MSCAN Not on 9512GC VREG Figure 3 1 Clock Connections 1 Section 4 Modes of Operation 4 1 Overview Eight possible modes determine the operating configuration of the MC9S12C Family Each mode has an associated default memory map and external bus configuration controlled by a further pin Three low power modes exist for the device 4 2 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC MODB and MODA pins during reset The MODC MODB and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation The states of the MODC MODB and MODA pins are AR MOTOROLA 65 Device User Guide 9512C128DGV1 D V01 05 latched into these bits on the rising edge of the reset signal The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map ROMON 1 mean the Flash is visible in the memory map The state of the ROMCT
89. f BDM commands Unsecuring is also possible via the Backdoor Key Access Refer to Flash Block Guide for details Once the user has erased the FLASH the part can be reset into special single chip mode This invokes a program that verifies the erasure of the internal FLASH Once this program completes the user can erase and program the FLASH security bits to the unsecured state This is generally done through the BDM but the user could also change to expanded mode by writing the mode bits through the BDM and jumping to an external program again through BDM commands Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state the part will be secured again 4 4 Low Power Modes The microcontroller features three main low power modes Consult the respective Block User Guide for information on the module behavior in Stop Pseudo Stop and Wait Mode An important source of information about the clock system is the Clock and Reset Generator User Guide CRG AR MOTOROLA 67 Device User Guide 9512C128DGV1 D V01 05 4 4 4 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode Wake up from this mode can be done via reset or external interrupts 4 4 2 Pseudo Stop This mode is entered by executing the CPU STOP instruction In this mode the oscillator is still running and the Real Time Interrupt RTT or Watchdog COP sub module can s
90. fferential Nonlinearity Counts 7 8 Bit Integral Nonlinearity Counts NOTES 1 These values include the quantization error which is inherently 1 2 count for any A D converter 102 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 For the following definitions see also Figure B 2 Differential Non Linearity DNL is defined as the difference between two adjacent switching steps Vi Vi 4 1LSB The Integral Non Linearity INL is defined as the sum of all DNLs n V INL n Y DNL 58 n i 1 DNL i 1 AR MOTOROLA 103 Device User Guide 9512C128DGV1 D V01 05 S3FF 3FE 3FD 3FC S3FB S3FA 3F9 3F8 3F7 3F6 3F5 3F4 3F3 10 Bit Resolution DNL 10 Bit Absolute Error Boundary V LSB V il i A M E 8 Bit Absolute Error Boundary m 7 E a XI Y Y B 7 a Pad V 7 r m m m m m FF Es P4 I 1 Fd I Y P VA 2 7 Va 7 L Pag ba gt L zs FE A a bal Y Y Y E Y ye P d joe PA Y Y FD S j pd 2 7 3 4 Q 7 v Pd Dt p F f 7 deal Transfer C cm o eal Transfer Curve ca y m va A gt 2 00 LI 7 E 7 I A 7 KG iV p 7 1 7 INO0 Bit Transfer Curve n Y A Y 7 e d E 7 PA Aba Eu 1 1 A Pag iV 2 3 VA gt 8 Bit Transfer Curve m i E Zi 7 pd p aci L L1 Er e ta si LoL 3 25 6 5 9
91. gital Logic Supply Voltage VDD 0 3 3 0 V 3 PLL Supply Voltage N VppPLL 0 3 V Voltage difference VSSX to VSSR and VSSA E 0 3 V Digital I O Input Voltage i 6 5 V XFC EXTAL XTAL inputs 3 0 V TEST input 10 0 V Instantaneous Maximum Current Single pin limit for all digital I O pins Instantaneous Maximum Current Single pin limit for XFC EXTAL XTAL3 Instantaneous Maximum Current Single pin limit for TEST Operating Temperature Range packaged Operating Temperature Range junction 140 NOTES 1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when the device is powered from an external source 2 All digital I O pins are internally clamped to Vssx and Vppx Vssn and Vppp or Vasa and Vppa 3 These pins are internally clamped to Vggp__ and Vpppi 4 This pin is clamped low to Vggx but not clamped high This pin must be tied low in applications AR MOTOROLA 85 Device User Guide 9512C128DGV1 D V01 05 A 1 6 ESD Protection and Latch up Immunity All ESD testing is in conformity with CDF AEC Q100 Stress test qualification for Automotive Grade Integrated Circuits During the device qualification ESD stresses were performed for the Human Body Model HBM the Machine Model MM and the Charge Device Model A device will be defined as a failure if after exposure to ESD pulses the device no longer meets
92. he state of this pin is latched to the ROMON bit PP6 1 in emulation modes equates to ROMON 0 ROM space externally mapped PP6 0 in expanded modes equates to ROMON 0 ROM space externally mapped M MOTOROLA 61 Device User Guide 9512C128DGV1 D V01 05 2 3 19 PP 5 0 KWP 5 0 PW 5 0 Port P I O Pins 5 0 PP 5 0 are general purpose input or output pins shared with the keypad interrupt function When configured as inputs they can generate interrupts causing the MCU to exit STOP or WAIT mode PP 5 0 are also shared with the PWM output signals PW 5 0 Pins PP 2 0 are only available in the 80 pin package version Pins PP 4 3 are not available in the 48 pin package version 2 3 20 PJ 7 6 KWJ 7 6 Port J I O Pins 7 6 PJ 7 6 are general purpose input or output pins shared with the keypad interrupt function When configured as inputs they can generate interrupts causing the MCU to exit STOP or WAIT mode These pins are not available in the 48 pin package version nor in the 52 pin package version 2 3 24 PM5 SCK Port M I O Pin 5 PMS is a general purpose input or output pin and also the serial clock pin SCK for the Serial Peripheral Interface SPI 2 3 22 PM4 MOSI Port M I O Pin 4 PMA is a general purpose input or output pin and also the master output during master mode or slave input during slave mode pin for the Serial Peripheral Interface SPI 2 3 23 PM3 SS Port M I O Pin 3 PM3 is
93. ib ex ee P DAG te 70 Table 6 1 Device Specific Flash PAGE Mapping a 71 Table 8 1 Recommended External Component Values 00000e0 eee 73 Table A 1 Absolute Maximum Ratings 000 eee ees 85 Table A 2 ESD and Latch up Test Conditions ooooocconcoooonno 86 Table A 3 ESD and Latch Up Protection CharacteristicS o ooooo 86 Table A 4 Operating Conditions 0 0 e cee ees 87 Table A 5 Thermal Package Characteristics 0 0 00 cece eee eee 89 Table A 6 5V I O Characteristics 00 cece eee 90 Table A 7 3 3V V O Characteristics ss aa wos wa Cedere a de sibus 91 Table A 8 Supply Current Characteristics for MCIS12032 oooooomoooo 93 Table A 9 Supply Current Characteristics for MC9S12C64 MC9S12C96 MC9S12C128 94 Table B 1 Voltage Regulator Electrical Parameters cece eaee 95 Table B 2 Voltage Regulator Capacitive LO0adS o oooooooooooo 97 Table B 3 ATD Operating Characteristics 0 0 cece a 99 Table B 4 ATD Operating Characteristics a 100 Table B 5 ATD Electrical Characteristics llle 101 Table B 6 ATD Conversion Performance lesse 102 Table B 7 ATD Conversion Performance lesse 102 Table B 8 NVM Timing Characteristics 00 ees 106 Table B 9 NVM Reliability Characteristics llle 107 Table B 10 Startup Characteristics ss casadas dd ERE Roe ed E rb
94. ide 9512C128DGV1 D V01 05 B 4 4 ATD accuracy 5V Range Table B 6 specifies the ATD conversion performance excluding any errors due to current injection input capacitance and source resistance Table B 6 ATD Conversion Performance Conditions are shown in Table A 4 unless otherwise noted Veer Van Vni 5 12V Resulting to one 8 bit count 20mV and one 10 bit count 5mV ATDCLK 2 0MHz Num C Rating Symbol Min Typ Max Unit 1 P 10 Bit Resolution LSB 5 mV 2 P 10 Bit Differential Nonlinearity DNL 1 1 Counts 3 P 10 Bit Integral Nonlinearity INL 2 2 Counts 4 P 10 Bit Absolute Error AE 2 5 25 Counts 5 P 8 Bit Resolution LSB 20 mV 6 P 8 Bit Differential Nonlinearity DNL 0 5 0 5 Counts 7 P 8 Bit Integral Nonlinearity INL 1 0 10 5 1 0 Counts 8 P 8 Bit Absolute Error AE 1 5 H 1 5 Counts NOTES 1 These values include quantization error which is inherently 1 2 count for any A D converter B 4 5 ATD accuracy 3 3V Range Table B 6 specifies the ATD conversion performance excluding any errors due to current injection input capacitance and source resistance Table B 7 ATD Conversion Performance Conditions are shown in Table A 4 unless otherwise noted Vrer Van Vat 3 328V Resulting to one 8 bit count 13mV and one 10 bit count 3 25mV faTDCLK 2 0MHz Rating 10 Bit Resolution Dr presses A a ene 4 10 Bit Absolute Error 5 8 Bit Resolution mV 6 8 Bit Di
95. iming diagram for master mode with transmission format CPHA 1 is depicted M MOTOROLA 119 Device User Guide 9512C128DGV1 D V01 05 ss OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT MISO INPUT OUTPUT PORTDATA X MASTER MSB OUT MASTER LSB OUT PORT DATA 1 If configured as output 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB Figure C 2 SPI Master Timing CPHA 1 In Table C 2 the timing characteristics for master mode are listed Table C 2 SPI Master Mode Timing Characteristics Max SCK Period lsck 2048 tous Enable Lead Time Enable Lag Time Clock SCK High or Low Time Ul U D D D D Data Setup Time Inputs tsu Data Hold Time Inputs O Data Valid after SCK Edge Data Valid after SS fall CPHA 0 Data Hold Time Outputs 13 Rise and Fall Time Outputs tro 8 ns O UO UO O O 120 AR MOTOROLA C 2 Slave Mode Device User Guide 9512C128DGV1 D V01 05 In Figure C 3 the timing diagram for slave mode with transmission format CPHA 0 is depicted SS INPUT SCK CPOL 0 INPUT cPoL EX INPUT 10 Da MISO see OUTPUT note X lt gt E Ao SLAVE MSB X BIT6 1 KOO let pol 13 O O y SLAVE LSB OUT kag SEE NOTE MOSI INPUT NOTE Not defined Ej xO won TED mm b Figure C 3
96. ite MMC map 2 of 4 HCS12 Module Mapping Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 cy a iss rr TOI a a SUE Write Miscellaneous Peripherals Device User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read 0 0 0 o 0 0 0 0 Write VREG3V3 Voltage Regulator Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Read 0 0 0 0 0 LVDS IME LVIF Write Miscellaneous Peripherals Device User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 Write Read 1D7 ID6 ID5 ID4 ID3 ID2 ID1 IDO Write 35 Device User Guide 9512C128DGV1 D V01 05 001C 001D MMC map 3 of 4 HCS12 Module Mapping Control Device User Guide Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0010 MEMSIZO baa reg sw0 0 eep swi eep sw 0 ram sw2 ram sw1 ram sw 001D MEMSIZ1 Read rom_sw1 rom_sw0 0 0 0 0 pag swi pag_sw0 Write 001E 001E MEBI map 2 of 3 HCS12 Multiplexed External Bus Interface Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 soe INTcR Read por ingen A 0 Write 001F 001F INT map 2 of 2 HCS12 Interrupt Address Name Read 001F HPRIO Write 0020 002F DBG including
97. ite delay time tRwD 7 ns 18 D Read write valid time to E rise PWE tgwp tawv 14 ns 19 D Read write hold time tRwH 2 ns 20 D Low strobe delay time ti sp 7 ns 21 D Low strobe valid time to E rise PWE t sp ti sv 14 ns 22 D Low strobe hold time ti eu 2 ns 23 D NOACC strobe delay time tNOD 7 ns 24 D NOACC valid time to E rise PWg t sp tNov 14 ns 25 D NOACC hold time tNoH 2 ns 26 D IPIPO 1 0 delay time tPop 2 7 ns 27 D IPIPO 1 0 valid time to E rise PWE tpop trov 11 ns 28 D IPIPO 1 0 delay time PWey tp y tp1D 2 25 ns 29 D IPIPO 1 0 valid time to E fall tpiv 11 ns NOTES 1 Affected by clock stretch add N x tyy where N 0 1 2 or 3 depending on the number of clock stretches 124 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Table C 5 Expanded Bus Timing Characteristics 3 3V Range Conditions are VDDX 3 3V 10 Junction Temperature 40 C to 140 C Cj pap 50pF Num C Rating Symbol Min Typ Max Unit 1 D Frequency of operation E clock fo 0 16 0 MHz 2 D Cycle time lcyc 62 5 ns 3 D Pulse width E low PWeL 3 ns 4 D Pulse width E high PWEH 30 ns 5 D Address delay time tap 16 ns 6 D Address valid time to E rise PWE tap tav 16 ns 7 D Muxed address hold time tMAH EXERCERE ns 8 D Address hold to data valid taHDS 7 ns 9 D Data hold to address tDHA 2 ns 10 D Read data setup time tpsR 15 ns 11 D Read data hold time toHr 0
98. k User Guide for information about the Motorola Scalable CAN Module This module is not available on the MC9GC Family Members Section 19 Port Integration Module PIM Block Description AR MOTOROLA 81 Device User Guide 9512C128DGV1 D V01 05 Consult the PIM 9C32 Block User Guide for information about the Port Integration Module for all versions of the MC9DS12GC and MC9S12C Family The MODRR register within the PIM allows for mapping of PWM channels to PortT in the absence of PortP pins for the low pin count packages For the 80QFP package option it is recommended not to use MODRR since this is intended to support PWM channel availability in low pin count packages Note that when mapping PWM channels to PortT in an 80QFP option the associated PWM channels are then mapped to both PortP and PortT 82 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Appendix A Electrical Characteristics A 1 General NOTE The electrical characteristics given in this section are preliminary and should be used as a guide only Values cannot be guaranteed by Motorola and are subject to change without notice NOTE The parts are specified and tested over the 5V and 3 3V ranges For the intermediate range generally the electrical specifications for the 3 3V range apply but the parts are not tested in production test in the intermediate range This supplement contains the most accurate electrical information for the MC9S12C Family microcont
99. led AO AA AA AA E ARAN cn VLVIA Da VLVRD Res E MN A AA KA CO a VpoRD l t LVI 4 LVI enabled LVI disabled due to LVR POR LVR B 3 Output Loads B 3 1 Resistive Loads The on chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external DC loads 96 AR MOTOROLA B 3 2 Capacitive Loads Device User Guide 9512C128DGV1 D V01 05 The capacitive loads are specified in Table B 2 Ceramic capacitors with X7R dielectricum are required Table B 2 Voltage Regulator Capacitive Loads AR MOTOROLA Num Characteristic Symbol Min Typical Max Unit 1 VDD external capacitive load Cppext 400 440 12000 nF 2 VDDPLL external capacitive load 5000 nF 97 Device User Guide 9512C128DGV1 D V01 05 98 M MOTOROLA Device User Guide 9512C128DGV1 D V01 05 B 4 ATD Characteristics This section describes the characteristics of the analog to digital converter VRL is not available as a separate pin in the 48 and 52 pin versions In this case the internal VRL pad is bonded to the VSSA pin The ATD is specified and tested for both the 3 3V and 5V range For ranges between 3 3V and 5V the ATD accuracy is generally the same as in the 3 3V range but is not tested in this range in production test B 4 1 ATD Operating Characteristics In 5V Range The Table B 3 shows conditions under which the ATD operates
100. ly Part Number Coding Part Number Temp Speed Description MC9S12C128CFA16 TBD 40 C 85 C 48LQFP 16MHz C128 die 16 AR MOTOROLA Mask Device User Guide 9512C128DGV1 D V01 05 Part Number set Temp Package Speed Description MC9512C128CPB16 TBD 40 C 85 C 52LQFP 16MHz C128 die MC9S12C128CFU16 TBD 40 C 85 C 80QFP 16MHz C128 die MC9512C128VFA16 TBD 40 C 105 C 48LQFP 16MHz C128 die MC9512C128VPB16 TBD 40 C 105 C 52LQFP 16MHz C128 die MC9512C128VFU16 TBD 40 C 105 C 80QFP 16MHz C128 die MC9512C128MFA16 TBD 40 C 125 C 48LQFP 16MHz C128 die MC9512C128MPB16 TBD 40 C 125 C 52LQFP 16MHz C128 die MC9512C128MFU16 TBD 40 C 125 C 80QFP 16MHz C128 die MC9512C128CFA25 TBD 40 C 85 C 48LQFP 25MHz C128 die MC9512C128CPB25 TBD 40 C 85 C 52LQFP 25MHz C128 die MC9S12C128CFU25 TBD 40 C 85 C 80QFP 25MHz C128 die MC9S12C128VFA25 TBD 40 C 105 C 48LQFP 25MHz C128 die MC9512C128VPB25 TBD 40 C 105 C 52LQFP 25MHz C128 die MC9512C128VFU25 TBD 40 C 105 C 80QFP 25MHz C128 die MC9512C128MFA25 TBD 40 C 125 C 48LQFP 25MHz C128 die MC9512C128MPB25 TBD 40 C 125 C 52LQFP 25MHz C128 die MC9512C128MFU25 TBD 40 C 125 C 80QFP 25MHz C128 die MC9S12C96PCFA16 OLO9S 40 C 85 C 48LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PCPB16 OLO9S 40 C 85 C 52LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PCFU16 OLO9S 40 C 85 C 80Q
101. n not drive 99 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 beyond the power supply levels that it ties to If the input level goes outside of this range it will effectively be clipped Table B 4 ATD Operating Characteristics Conditions are shown in Table A 4 unless otherwise noted Supply Voltage 3 3V 10 lt Vpp4 lt 3 3V 10 e To jara lima e5 20 L ATD 10 Bit Conversion Period y Clock Cycles Nconvio Conv Time at 2 0MHz ATD Clock farpcik Tconvio ATD 8 Bit Conversion Period Clock Cycles Conv Time at 2 0MHz ATD Clock farpcLk NOTES 1 The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks B 4 3 Factors influencing accuracy Three factors source resistance source capacitance and current injection have an influenceon the accuracy of the ATD B 4 3 1 Source Resistance Due to the input pin leakage current as specified in Table A 6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input The maximum source resistance Rg specifies results in an error of less than 1 2 LSB 2 5mV at the maximum leakage current If device or operating conditions are less than worst case or leakage induced error is acceptable larger values of source resistance is allowable B 4 3 2 Source capacitance When sampling an additional internal capacitor is switched to
102. ng Gated Time Accumulation 6 PWM channels Programmable period and duty cycle 8 bit 6 channel or 16 bit 3 channel Separate control for each pulse width and duty cycle Center aligned or left aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Serial interfaces One asynchronous serial communications interface SCI One synchronous serial peripheral interface SPI CRG Clock Reset Generator Module Windowed COP watchdog Real time interrupt Clock monitor AR MOTOROLA 1 3 Device User Guide 9512C128DGV1 D V01 05 Pierce or low current Colpitts oscillator Phase locked loop clock frequency multiplier Limp home mode in absence of external clock Low power 0 5 to 16 MHz crystal oscillator reference clock Operating frequency 32MHz equivalent to 16MHz Bus Speed for single chip 32MHz equivalent to 16MHz Bus Speed in expanded bus modes Option of 98512C Family 50MHz equivalent to 25MHz Bus Speed Al 9S12GC Family Members allow a 50MHz operting frequency Internal 2 5 V Regulator Supports an input voltage range from 2 97V to 5 5V Low power mode capability Includes low voltage reset LVR circuitry Includes low voltage interrupt LVI circuitry 48 Pin LQFP 52 Pin LQFP or 80 Pin QFP package Up to 58 1 0 lines with 5V input and drive capability 80 pin package Up
103. ng to EIA JEDEC Standard 51 2 3 PC Board according to EIA JEDEC Standard 51 7 A 1 9 I O Characteristics This section describes the characteristics of all I O pins All parameters are not always applicable e g not all pins feature pull up down resistances AR MOTOROLA 89 Device User Guide 9512C128DGV1 D V01 05 Table A 6 5V I O Characteristics Conditions are 4 5 VDDX 5 5V Termperature from 40 C to 140 C unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Input High Voltage Vin 0 65 Vpps V T Input High Voltage Vin E VDD5 0 3 V 2 P Input Low Voltage Vi 0 35 Vppg V T Input Low Voltage Vi VSS5 0 3 V Output High Voltage pins in output mode V Partial Drive lop 2MA OH Output High Voltage pins in output mode V Full Drive IOH 10mA SH Output Low Voltage pins in output mode V Partial Drive IOL 2mA 2h Output Low Voltage pins in output mode V Full Drive loL 10mA OL Internal Pull Up Device Current IPUL E tested at Vib Max Internal Pull Up Device Current 10 C tested at V y Min PUH 10 pA Internal Pull Down Device Current n tested at Vin Min PDH 130 LA Internal Pull Down Device Current 12 C tested at V Max PDL 10 7 7 LA 13 D Input Capacitance Cin 7 pF Injection current 14 T Single Pin limit lics 2 5 2 5 mA Total Device Limit Sum of all injected currents licp 25 25
104. nge of package temperature and speed options The members of the GC Family do not feature a CAN module Table 0 1 shows a feature overview of the MC9S12C and MC9S12GC Family members Table 0 2 summarizes the package option and size configuration Table 0 3 lists the part number coding based on the package speed and temperature and preliminary die options for the C Family Table 0 4 lists the part number coding based on the package speed and temperature and preliminary die options for the GC Family Table 0 1 List of MC9S12C and MC9S12GC Family members Device CAN SCI SPI A D PWM Timer M 12C1 128K 4K C9S12C128 1 8ch 6ch 8ch MC9812GC128 96K 4K 8ch 6ch 8ch MC9S12C96 1 RAR ch ch 8h MC9512C64 1 64K 4K 32K 2K 8ch 6ch 8ch 8ch 6ch 8ch MC9S12C32 1 MC9512GC32 8ch 6ch 8ch 16K 1K MC9512GC16 8ch 6ch 8ch 8ch 6ch 8ch a a a Table 0 2 MC9S12C Family Package Option Summary Temp 34 aja 48LQFP MC9S12C128 MC9S12C128 OLO9S M M V C a wae E 128K K 52LQFP MC9S12C128 MC9512C128 0L095 M V C 80QFP MC9S12C128 MC9S12C128 OLO9S M V C Ko 48LQFP MC9S12C96 MC9S12C96 TBD M V M V C pier E 4K Ka MC9S12C96 SS TED M V C 80QFP MC9S12C96 MC9S12C96 M V C AR MOTOROLA 15 Device User Guide 9512C128DGV1 D V01 05 Package 48LQFP MC9S12C64 Part Number MC9S12C6
105. nterrupt stacking and programmer s model identical to M68HC11 111 Instruction queue iv Enhanced indexed addressing MMC memory map and interface INT interrupt control BDM background debug mode DBG12 enhanced debug12 module including breakpoints and change of flow trace buffer MEBI Multiplexed Expansion Bus Interface available only in 80 pin package version e Wake up interrupt inputs Upto 12 port bits available for wake up interrupt function with digital filtering e Memory options 16K or 32KByte Flash EEPROM erasable in 512 byte sectors 64K 96K or 128KByte Flash EEPROM erasable in 1024 byte sectors AR MOTOROLA 28 Device User Guide 9512C128DGV1 D V01 05 24 1K 2K or 4K Byte RAM Analog to Digital Converters One 8 channel module with 10 bit resolution External conversion trigger capability Available on MC9S12C Family One 1M bit per second CAN 2 0 A B software compatible module Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx Tx error and wake up Low pass filter wake up function Loop back for self test operation Timer Module TIM 8 Channel Timer Each Channel Configurable as either Input Capture or Output Compare Simple PWM Mode Modulo Reset of Timer Counter 16 Bit Pulse Accumulator External Event Counti
106. numbers can be given A very good estimate is to take the single chip currents and add the currents due to the external loads 92 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Table A 8 Supply Current Characteristics for MC9S12C32 Conditions are shown in Table A 4 with internal regulator enabled unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Run Supply Current Single Chip Ipps mA Wait Supply current All modules enabled VDDR lt 4 9V only RTI enabled VDDR gt 4 9V only RTI enabled Ippw mA OTU Pseudo Stop Current RTI and COP disabled 9 40 C 27 C 85 C C Temp Option 100 C Ippps 105 C V Temp Option 120 C 125 C M Temp Option 140 C VOVOVOTVO Pseudo Stop Current RTI and COP enabled 3 40 C 27 C 1 85 C DDPS 105 C 125 C 09090000 Stop Current 9 40 C 10 27 C 20 80 85 C 100 C Temp Option 100 C Ipps MEL SHA 105 C 170 V Temp Option 120 C 300 1400 125 C 350 M Temp Option 140 C 520 4000 TOUTUDOVUVUO VO NOTES 1 STOP current measured in production test at increased junction temperature hence for Temp Option C the test is carried out at 100 C although the Temperature specification is 85 C Similarly for v and M options the temperature used in test lies 15 C above the temperature option specification 2 PLL off 3 At those low power dissipation levels Tj Ta can be assumed AR MOTOROLA 93 Devic
107. or CRG Block Description Consult the CRG Block User Guide for information about the Clock and Reset Generator module 9 1 Device specific information The CRG is part of the IPBus domain 79 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the CRG module When the regulator output voltage supply to the internal chip logic falls below a specified threshold the LVR signal from the VREG module causes the CRG module to generate a reset Consult the VREG Block User Guide for voltage level specifications 9 1 1 XCLKS The XCLKS input signal is active low see 2 3 8 PE7 NOACC XCLKS Port E O Pin 7 Section 10 Oscillator OSC Block Description Consult the OSC Block User Guide for information about the Oscillator module Section 11 Timer TIM Block Description Consult the TIM 16B8C Block User Guide for information about the Timer module Section 12 Analog to Digital Converter ATD Block Description 12 1 Device specific information 12 1 1 VRL voltage reference low In the 48 and 52 pin package versions the VRL pad is bonded internally to the VSSA pin Consult the ATD 10B8C Block User Guide for further information about the A D Converter module Section 13 Serial Communications Interface SCI Block Description Consult the SCI Block User Guide for information about the Asynchronous Serial Communications
108. ous B 5 1 2 Row Programming Generally the time to program a consecutive word can be calculated as 1 Po ORL ud Ta NVMOP bus tbwpgm For the C16 GC16 C32 and GC32 device flash arrays where up to 32 words in a row can be programmed consecutively by keeping the command pipeline filled the time to program a whole row is t tbrpgm swpgm 31 tbwpgm For the C64 GC64 C96 C128 and GC128 device flash arrays where up to 64 words in a row can be programmed consecutively by keeping the command pipeline filled the time to program a whole row is tbrpgm tswpgm 63 tbwpgm Row programming is more than 2 times faster than single word programming 105 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 B 5 1 3 Sector Erase Erasing either a 512 byte or 1024 byte Flash sector takes 1 i5 4000 era NvMOP The setup times can be ignored for this operation B 5 1 4 Mass Erase Erasing a NVM block takes 1 t 20000 mass INVMOP This is independent of sector size The setup times can be ignored for this operation Table B 8 NVM Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit o External Oscillator Clock NVMOSC 0 5 501 MHz D Bus frequency for Programming or Erase Operations fNvmBus 1 MHz Operating Frequency Single Word Programming Time Flash Burst Programming consecutive word o Flash Bur
109. pin pair enables systems using the 80 pin package to employ better supply routing and further decoupling Section 8 Recommended Printed Circuit Board Layout The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself The following rules must be observed e Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins C1 C6 e Central point of the ground star should be the VSSR pin e Use low ohmic low inductance connections between VSS1 VSS2 and VSSR e VSSPLL must be directly connected to VSSR e Keep traces of VSSPLL EXTAL and XTAL as short as possible and occupied board area for C7 C8 C11 and QI as small as possible e Do not place other signals or supplies underneath area occupied by C7 C8 C10 and Q1 and the connection area to the MCU e Central power input should be fed in at the VDDA VSSA pins 72 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Table 8 1 Recommended External Component Values Component Purpose Type Value VDD1 filter capapcitor ceramic X7R 220nE 470nF C2 VDD2 filter capacitor 80 QFP only ceramic X7R C3 VDDA filter capacitor ceramic X7R C4 VDDR filter capacitor X7R tantalum C5 VDDPLL filter capacitor ceramic X7R VDDX filter capacitor X7R tantalum OSC load capacitor See PLL specification chapter C8 OSC load capacitor PLL loop filter capacitor
110. ring the pins as inputs Description The reset state of PUPKE in the PUCR register of the S12 CORE is 1 enabling the internal pullup resistors at PortK 2 0 In this reset state the pull up resistors provide a defined state and prevent a floating input thereby preventing unneccesary current consumption at the input stage 132 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 E 2 112 pin LQFP package 4X 28 TIPS Aj 020 T L M n 85 2 o gt a RTEEEEDE e q CEE E 8 00 lt VIEW AB SEATING PLANE 0 25 GAGE PLANE E 6 108X Hu VIEW Y X X L MORN J AA a HAN METAL D SECTION J1 J1 ROTATED 90 COUNTERCLOCKWISE NOTES 1 DIMENSIONING AND TOLERANCING PER SME Y14 5M 1994 MENSIONS IN MILLIMETERS ATUMS L M AND N TO BE DETERMINED AT EATING PLANE DATUM T MENSIONS S AND V TO BE DETERMINED AT EATING PLANE DATUM T MENSIONS A AND B DO NOT INCLUDE OLD PROTRUSION ALLOWABLE ROTRUSION IS 0 25 PER SIDE DIMENSIONS AND B INCLUDE MOLD MISMATCH MENSION D DOES NOT INCLUDE DAMBAR ROTRUSION ALLOWABLE DAMBAR ROTRUSION SHALL NOT CAUSE THE D MENSION TO EXCEED 0 46 2 3 4 Q0 C9 00 C9 C2 22 C OUUO uzco MIN 2 0250REF Figure 19 2 112 pin LQFP mechanical dimensions case no 987 80 pin QFP Me
111. rnal Voltage Regulator disabled Pint loo Vpp DDPLL VDDPLL ppA Y 2 Pio Roson NO l DDA Which is the sum of all output currents on I O ports associated with VDDX and VDDM For RpsoN is valid MOL RDSON T for outputs driven low OL respectively V V RDSON es for outputs driven high 2 Internal voltage regulator enabled Pint DDR DDR IDDA DDA Ippg is the current shown in Table A 8 and not the overall current flowing into VDDR which additionally contains the current flowing into the external loads with output high 2 Pio Roson NO l 88 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 Which is the sum of all output currents on I O ports associated with VDDX and VDDR Table A 5 Thermal Package Characteristics Num C Rating Symbol Min Typ Max Unit ERES Thermal Resistance LQFP48 single layer PCB HH C W 2 T Thermal Resistance LQFP48 double sided PCB with 2 internal planes 3 T Junction to Board LQFP48 T Junction to Case LQFP48 7 T Thermal Resistance LQFP52 double sided PCB with 2 internal planes 8 T Junction to Board LOFP52 C W T Junction to Case LQFP52 17 E Thermal Resistance QFP 80 double sided PCB with 2 internal planes 13 Junction to Board QFP80 C W 14 Junction to Case QFP80 18 C W E HX Junction to Package Top QFP80 wr 4 fow OCW NOTES 1 The values for thermal resistance are achieved by package simulations 2 PC Board accordi
112. rollers available at the time of publication The information should be considered PRELIMINARY and is subject to change This introduction is intended to give an overview on several common topics like power supply current injection etc A 1 1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This classification will be added at a later release of the specification P Those parameters are guaranteed during production testing on each individual device C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations They are regularly verified by production monitors T Those parameters are achieved by design characterization on a small sample size from typical devices All values shown in the typical column are within this category D Those parameters are derived mainly from simulations A 1 2 Power Supply The MC9S12C Family and MC9S12GC Family members utilize several pins to supply power to the I O ports A D converter oscillator and PLL as well as the internal logic The VDDA VSSA pair supplies the A D converter The VDDX VSSX pair supplies the I O pins The VDDR VSSR pair supplies the internal voltage regulator VDDI VSS1 VDD2 and
113. ry from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes The controller can be woken up by internal or external interrupts After tyr the CPU starts fetching the interrupt vector B 6 2 Oscillator The device features an internal Colpitts oscillator By asserting the XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power on STOP or oscillator fail tegour specifies the maximum time before switching to the internal self clock mode in case no proper oscillation is detected The quality monitor also determines the minimum oscillator start up 110 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 time typosc The device features a clock monitor A time out is asserted if the frequency of the incoming clock signal is below the Clock Monitor FailureAssert Frequency femea Table B 11 Oscillator Characteristics Conditions are shown in Table A 4 unless otherwise noted C a Crystal oscillator range Colpitts 3 MHz Crystal oscillator range Pierce 1 4 l MHz Startup Current losc uA 1 Oscillator start up time Colpitts tuposc ms b 2 3 4 Clock Quality check time out tcaouT s Clock Monitor Failure Assert Frequency KHZ External square wave input frequency MHz External square
114. s noted A program erase cycle is specified as two transitions of the cell value from erased programmed erased 1 5 0 5 1 NOTE All values shown in Table B 9 are target values and subject to further extensive characterization Table B 9 NVM Reliability Characteristics IH NEUE ch Retention at an average junction temperature of 1 T 85 C NVMRET Years Javg 7 2 Flash number of Program Erase cycles NFLPE 10 000 Cycles LE are e Ui in Table A 4 unless otherwise noted AR MOTOROLA 107 Device User Guide 9512C128DGV1 D V01 05 108 M MOTOROLA Device User Guide 9512C128DGV1 D V01 05 B 6 Reset Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase Locked Loop PLL B 6 1 Startup Table B 10 summarizes several startup characteristics explained in this section Detailed description of the startup behavior can be found in the Clock and Reset Generator CRG Block User Guide Table B 10 Startup Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating POR release level POR assert level 0 97 4 Startup from Reset Nose 5 Interrupt pulse width IRQ edge sensitive PWiro mode B 6 1 1 POR The release level Vporp and the assert level Vpora are derived from the Vpp Supply They are also valid if the device is powered externally After releasing the POR reset the oscill
115. scription 12 1 Device specific informatlori naaa paaa kama RA GRAN REFER RR ER ERE 80 12 1 1 VRL voltage reference low svi e E aH eae we Oli E eee aes 80 Section 13 Serial Communications Interface SCI Block Description Section 14 Serial Peripheral Interface SPI Block Description Section 15 Flash Block Description M MOTOROLA 5 Device User Guide 9512C128DGV1 D V01 05 Section 16 RAM Block Description Section 17 Pulse Width Modulator PWM Block Description Section 18 MSCAN Block Description Section 19 Port Integration Module PIM Block Description Appendix A Electrical Characteristics WEE aC Wc 83 A 1 1 Parameter Classification c aeta er Sedo rui BA KABAN MERE NA taedas 83 A 1 2 Power OU rat cde ca Rees A Ga haan RO dert UAE uud Res ieu ed 83 A 1 3 PIS sigs te oet Sete AN dd pe v e RET pes Eun but iet teres 84 A 1 4 C rrent MECON PP 84 A 1 5 Absolute Maximum Ralings 2 2 4 6 wats Pode LE TEST RE FERES 85 A 1 6 ESD Protection and Latch up Immunity 0020 eee ee eee 86 A 1 7 Operating ConditonS tas tase tee cede hot e oes AP bess Re aed 86 A 1 8 Power Dissipation and Thermal Characteristics 87 A 1 9 VOCACION AA ce aae e EA EC POE ANN 89 A 1 10 Supply Currents aac hear per en NN ARR S IR ERR RD Ere det diee Rs 92 Appendix B Electrical Specifications B 1 Voltage Regulator Operating Conditions llle 95 B 2 Chip Power up and LVI LVR graphical explanation
116. st Programming Time for 32 Word row torpgm 678 4 1035 53 us Flash Burst Programming Time for 64 Word row torpgm 1331 22 2027 53 us MA 7 Sector Erase Time 8 Mass Erase Time 9 Blank Check Time Flash per block O A 0 Gm Tu NOTES 1 Restrictions for oscillator in crystal mode apply 2 Minimum Programming times are achieved under maximum NVM operating frequency f nymop and maximum bus frequen Cy fbus Maximum Erase and Programming times are achieved under particular combinations of f nymop and bus frequency f bus Refer to formulae in Sections A 3 1 1 A 3 1 4 for guidance Minimum Erase times are achieved under maximum NVM operating frequency f yymop Minimum time if first word in the array is not blank 512 byte sector size Maximum time to complete check on an erased block 512 byte sector size Where toyo is the system bus clock period Minimum time if first word in the array is not blank 1024 byte sector size Maximum time to complete check on an erased block 1024 byte sector size Co SONDA 2 106 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 B 5 2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification constant process monitors and burn in to screen early life failures The failure rates for data retention and program erase cycling are specified at 2ppm defects over lifetime at the operating condition
117. t tu etit ka ai Niles e pde diia 127 D2 80 pin QFP package us xu x ene Rd UE ERRARE Redde eR eR mE 128 D 3 3 52pm E OGEP packages pss Ee pU EPA EUER 129 D 4 48 pin LQFP package io ied aeo rere dto oet qu s Ros etie e E 130 Appendix E Emulation Information Edi General aa St DEEP LUE NELLE ELS S dS a 131 E 1 1 PR 2 017 ADD TO Alas uir NAL An teo pea n bodas et EO arte os 132 E2 il2 pit LOFP package aptas S pu RE PA 133 AR MOTOROLA 7 Device User Guide 9512C128DGV1 D V01 05 8 M MOTOROLA Device User Guide 9512C128DGV1 D V01 05 List of Figures Figure 0 1 Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 Figure 1 6 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 3 1 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 6 Figure B 1 Figure B 2 Figure B 3 Figure B 4 Figure B 5 Figure C 1 Figure C 2 Figure C 3 Figure C 4 Figure C 5 Figure D 1 Figure D 2 AR MOTOROLA Order Part number Coding 9 oe exire o a een E 16 MC9512C Family Block Diagram o 27 MC9S12C128 and MC9S12GC128 User configurable Memory Map 29 MC9S12C96 User Configurable Memory Map lille 30 MC9S12C64 and MC9S12GC64 User Configurable Memory Map 31 MC9S12C32 and MC9S12GC32 User Configurable Memory Map 32 MC9S12GC16 User Configurable Memory Map Lille 33 Pin Assignments in 80 QFP for MC9S12C Family 2 5
118. t15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 41 Device User Guide 9512C128DGV1 D V01 05 00C8 00CF SCI Asynchronous Serial Interface Address Name Bt7 Bite Bits Bit4 Bi3 Bit 2 Bit 1 Bit 0 Read 0 0 0 00C8 SCIBDH Write EE SBR12 SBR11 SBR10 SBR9 SBR8 00C9 SCIBDL Naa SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR SBRO 00CA SCICR1 Nag LOOPS sciswal RSRC M WAKE ILT PE PT Read 008 SCIOR2 yy TIE TCIE RIE ILIE TE RE RWU SBK soco sosa Pest TDRE TC RDRF IDLE OR NF FE PF Write 00CD scismo Read 0 BRK13 TXDIR LY Write oc sopa AG RS rg mc da a Write Read R7 R6 R5 R4 R3 R2 Ri RO GE SD ie T6 T5 T4 T3 T2 Ti TO 00DO 00D7 Reserved 000 penay Peed O 0 0 0 0 0 0 0 00D7 Write 00D8 00DF SPI Serial Peripheral Interface Address Name Bt7 Bite Bt5 Bit4 Bits Bit2 Bit 1 Bit 0 0008 SPICR1 o SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0009 SPICR2 ras Fe MODFEN BIDIROE 2 spigwal sPco 00DA SPIBR e SPPR2 sPPR1 sPPRo LY spr2 spri SPRO soos sogra Read SPIF 0 SPTEF MODF 0 0 0 0 Write Read O 0 0 0
119. tay active Other peripherals are turned off This mode consumes more current than the full STOP mode but the wake up time from this mode is significantly shorter 4 4 3 Wait This mode is entered by executing the CPU WAI instruction In this mode the CPU will not execute instructions The internal CPU signals address and databus will be fully static All peripherals stay active For further power consumption reduction the peripherals can individually turn off their local clocks 4 4 4 Run Although this is not a low power mode unused peripheral modules should not be enabled in order to save power Section 5 Resets and Interrupts 5 1 Overview Consult the Exception Processing section of the CPU12 Reference Manual for information 5 2 Vectors 5 2 1 Vector Table Table 5 1 lists interrupt sources and vectors in default order of priority Table 5 1 Interrupt Vector Locations CCR HPRIO Value Vector Address Interrupt Source Mask Local Enable to Elevate External Reset Power On Reset or Low SFFFE SFFFF Voltage Reset see CRG Flags Register None None to determine reset source SFFFC SFFFD Clock Monitor fail reset None COPCTL CME FCME SFFFA SFFFB COP failure reset None COP rate select FFF8 SFFF9 Unimplemented instruction trap None None 68 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 FFF6 FFF7 FFF4 FFF5 SWI XIRQ None None None FFF2 SFFF3 IRQ INTCR
120. testing only A 1 4 Current Injection Power supply must maintain regulation within operating Vpps or Vpp range during instantaneous and operating maximum current conditions If positive injection current Vi gt V pps is greater than Ipps the injection current may flow out of VDDS and could result in external power supply going out of regulation Insure external VDDS load will shunt current greater than maximum injection current This will be the greatest risk when the MCU is not consuming power e g if no system clock is present or if clock rate is very low which would reduce overall power consumption 84 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 A 1 5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only A functional operation under or outside those maxima is not guaranteed Stress beyond those limits may affect the reliability or cause permanent damage of the device This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either Vgg5 or Vpps Table A 1 Absolute Maximum Ratings Num Rating Symbol Min Max Unit 1 I O Regulator and Analog Supply Voltage Vpps 0 3 6 5 V 2 Di
121. the device specification Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature unless specified otherwise in the device specification Table A 2 ESD and Latch up Test Conditions Model Description Symbol Value Unit Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF suman Body Number of Pulse per pin positive 3 negative 3 Series Resistance R1 0 Ohm Storage Capacitance C 200 pF ace Number of Pulse per pin positive i 3 negative 3 Minimum input voltage limit 2 5 Latch up Maximum input voltage limit 7 5 Table A 3 ESD and Latch Up Protection Characteristics Human Body Model HBM 2000 Machine Model MM VMM 200 Charge Device Model CDM VcpM 500 Latch up Current at 125 C positive negative Latch up Current at 27 C positive negative A 1 7 Operating Conditions This chapter describes the operating conditions of the devices Unless otherwise noted those conditions apply to all the following data 96 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 NOTE Instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature For power dissipation calculations refer to Section A 1 8 Power Dissipation and Thermal Characteristics Table A 4 Operating Conditions Rating Symbol Min Typ Max Unit O Reg
122. the input This can cause a voltage drop due to charge sharing with the external and the pin capacitance For a maximum sampling error of the input voltage ILSB then the external filter capacitor C gt 1024 Cjng Cinn 100 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 B 4 3 3 Current injection There are two cases to consider 1 A current is injected into the channel being converted The channel being stressed has conversion values of 3FF FF in 8 bit mode for analog inputs greater than VRH and 000 for values less than VRL unless the current is higher than specified as disruptive conditions 2 Current is injected into pins in the neighborhood of the channel being converted A portion of this current is picked up by the channel coupling ratio K This additional current impacts the accuracy of the conversion depending on the source resistance The additional input voltage error on the converted channel can be calculated as Vgpp K Rg Iy with Ir being the sum of the currents injected into the two pins adjacent to the converted channel Table B 5 ATD Electrical Characteristics Conditions are shown in Table A 4 unless otherwise noted Pump ef m oma ne owe um T e mae al o 1 mo Total Input Capacitance 2 T Non Sampling CINN 10 Sampling d 15 Coupling Ratio positive current injection e 104 5 C Coupling Ratio negative current injection Kn 102 A A AR MOTOROLA 101 Device User Gu
123. to 2 dedicated 5V input only lines IRQ XIRQ 5V 8 A D converter inputs and 5V I O Development support Single wire background debug mode BDM On chip hardware breakpoints Enhanced DBG12 debug features Modes of Operation User modes Expanded modes are only available in the 80 pin package version Normal and Emulation Operating Modes Normal Single Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Operating Modes AR MOTOROLA 25 Device User Guide 9512C128DGV1 D V01 05 Special Single Chip Mode with active Background Debug Mode Special Test Mode Motorola use only Special Peripheral Mode Motorola use only e Low power modes Stop Mode Pseudo Stop Mode Wait Mode 26 AR MOTOROLA Device User Guide 9512C128DGV1 D V01 05 1 4 Block Diagram Figure 1 1 MC9512C Family Block Diagram VSSX Voltage Regulator 16K 32K 64K 96K 128K Byte Flash VDD1 VSS1 1K 2K 4K Byte RAM BKGD ODC Background Debug12 Module XFC VDDPLL Clock and Timer VSSPLL Reset Module EXTAL Generation COP Watchdog XTAL Module Clock Monitor RESET Periodic Interrupt PEO PE1 PE2 pape System BU a Integration PE3 LSTRB TAGLO Module Module PE4 ECLK SIM PE5 MODA IPIPEO PE6 MODB IPIPE1 PE7 NOACC XCLKS TEST VPP Multiplexed Address Data Bus RXD PSO B a PS2 M
124. ulator and Analog Supply Voltage Vpps 2 97 5 5 5 V Digital Logic Supply Voltage Vpp 2 35 2 5 2 75 V PLL Supply Voltage VppPLL 2 35 2 5 2 75 V Voltage Difference VDDX to VDDA AVDDX 0 1 0 0 1 V Voltage Difference VSSX to VSSR and VSSA Ayssx 0 1 0 0 1 V Oscillator Idee 0 5 16 MHz Bus Frequency feus 0 25 25 MHz Operating Junction Temperature Range Tj 40 140 C NOTES 1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source 2 Some blocks e g ATD conversion and NVMs program erase require higher bus frequencies for proper oper ation A 1 8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related The user must assure that the maximum operating junction temperature is not exceeded The average chip junction temperature Ty in C can be obtained from Ty alt Pp OA Tj Junction Temperature C TA Ambient Temperature C Pp Total Chip Power Dissipation W Oja Package Thermal Resistance C W The total power dissipation can be calculated from Pp PINT RO PINT Chip Internal Power Dissipation W AR MOTOROLA 87 Device User Guide 9512C128DGV1 D V01 05 Two cases with internal voltage regulator enabled and disabled must be considered 1 Inte
125. up on this pin while in reset and immediately out of reset The pull up can be turned off by clearing PUPEE in the PUCR register 2 3 16 PAD 7 0 AN 7 0 Port AD I O Pins 7 0 PAD7 PADO are general purpose I O pins and also analog inputs for the analog to digital converter In order to use a PAD pin as a standard I O the corresponding ATDDIEN register bit must be set These bits are cleared out of reset to configure the PAD pins for A D operation When the A D converter is active in multi channel mode port inputs are scanned and converted irrespective of PortAD configuration Thus PortAD pins that are configured as digital inputs or digital outputs are also converted in the A D conversion sequence 2 3 17 PP 7 KWP 7 Port P I O Pin 7 PP7 is a general purpose input or output pin shared with the keypad interrupt function When configured as an input it can generate interrupts causing the MCU to exit STOP or WAIT mode This pin is not available in the 48 52 pin package versions 2 3 18 PP 6 KWP 6 ROMCTL Port P I O Pin 6 PP6 is a general purpose input or output pin shared with the keypad interrupt function When configured as an input it can generate interrupts causing the MCU to exit STOP or WAIT mode This pin is not available in the 48 52 pin package versions During MCU expanded modes of operation this pin is used to enable the Flash EEPROM memory in the memory map ROMCTL At the rising edge of RESET t
126. urrent 10 C tested at Vj Min PUH 6 g uA Internal Pull Down Device Current 11 P ltested at Vj Min PDH 60 uA Internal Pull Down Device Current 12 C liestedat V Max PDL 6 uA 11 D Input Capacitance Cin 7 pF Injection current 12 T Single Pin limit lics 2 5 2 5 mA Total Device Limit Sum of all injected currents licp 25 25 13 P Port P J Interrupt Input Pulse filtered tPIGN 3 us 14 P Port P J Interrupt Input Pulse passed tpyaL 10 us NOTES 1 Maximum leakage current occurs at maximum operating temperature Current decreases by approximately one half for each 8 C to 12 C in the temperature range from 50 C to 125 C 2 Refer to Section A 1 4 Current Injection for more details 3 Parameter only applies in STOP or Pseudo STOP mode AR MOTOROLA 91 Device User Guide 9512C128DGV1 D V01 05 A 1 10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements A 1 10 1 Measurement Conditions All measurements are without output loads Unless otherwise noted the currents are measured in single chip mode internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator A 1 10 2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address data and control signals as well as on the duty cycle of those signals No generally applicable
127. ut pins They can also be configured as the timer system input capture or output compare pins IOC4 IOCO or as the PWM outputs PW 4 0 2 4 Power Supply Pins 2 4 1 VDDX VSSX Power amp Ground Pins for I O Drivers External power and ground for I O drivers Bypass requirements depend on how heavily the MCU pins are loaded 2 4 2 VDDR VSSR Power amp Ground Pins for I O Drivers amp for Internal Voltage Regulator External power and ground for the internal voltage regulator Connecting VDDR to ground disables the internal voltage regulator 2 4 3 VDD1 VDD2 VSS1 VSS2 Internal Logic Power Pins Power is supplied to the MCU through VDD and VSS This 2 5V supply is derived from the internal voltage regulator There is no static load on those pins allowed The internal voltage regulator is turned off if VDDR is tied to ground AR MOTOROLA 63 Device User Guide 9512C128DGV1 D V01 05 2 4 4 VDDA VSSA Power Supply Pins for ATD and VREG VDDA VSSA are the power supply and ground input pins for the voltage regulator reference and the analog to digital converter 2 4 5 VRH VRL ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter 2 4 6 VDDPLL VSSPLL Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased Locked Loop This allows the supply voltage to the Oscillator and PLL to be bypassed independently

Motorola MC9S12C-Family User's Manual

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