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IBM BDM-610000049 User's Manual

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1. Field Active Keys Selections Main Press Enter to select Access system information such as BIOS version EPLD version and CMOS time and date settings Advanced Press Enter to select Setup advanced cpuModule features PCIPnP Press Enter to select Set PnP and PCI options and control system resources Boot Press Enter to select Set the system boot sequence Security Press Enter to select Setup the supervisor and user access passwords or enable boot sector virus protection Power Press Enter to select Control power management settings including power supply type and system wake functions Thermal Press Enter to select Monitor the cpuModule temperature or activate thermal or fan modes Exit Press Enter to select Save or discard changes and exit the BIOS or load the default BIOS settings Note Future BIOS versions may have slightly different setup menus and options Power On Self Test POST Codes Each POST Code represents a series of events that take place in a system during the POST If the POST fails during a particular POST Code the system will not boot as expected The BIOS uses I O port 80h to store the active POST Code A POST Code board is a tool that is used to display the POST Codes on I O port 80h This is usually accomplished with two 7 segment LEDs Such a board is useful for debugging a system that is unable to boot BDM 610000049 Rev G Chapter 4 Using the cpuModule 57 Booting to Boot Block Flash w
2. ced ere ee te te ERR EU I HACER ee eee 61 multiPort Advanced Digital 1 O Ports aDIO 2 2 0 0 I 62 Digital O Register Sets oma o RISE Mea ERR T Te Ve e edu vu biete Eb S 62 Port 1 Data register is a read write byte direction 64 FEE NOT EV UP DE ME 64 Advanced Digital Interr pts 5 LE rr eA ANN 64 Event Mode 64 MatcliiMode RSS NE eR Pepe RISO PERPE 64 Strob S ELE RR Maas ba ga bok I X YN RR Seno VIDE NOU 65 Wake on aDIQ AREA EPA 65 multiPort Parallel Port hehe hehehe 66 multiPort Floppy etes heure 66 AC 97 Audio DINE eU od at Murs Br A Pas 66 Ethernet 10 100Base T and 66 IDE Controller Configuration 67 Cable Modes Age bh beet AA AE ae Oe ape HR 67 Cabl Detection cocos ROME Rh ids E ME nO 67 Device and Host ccc dahon RR era RR LEN M ERE EON eR o ei e e rra e ebay 67 Host Determination of Cable cee He em emen 67 Device arat deen eer Ren PM REA tas NUMEN Naas 67 Lega
3. Pin Signal Function 1 CPU FAN PWM 5 Volts DC switched 2 GND Ground 54 CMX158886 cpuModule BDM 610000049 Rev G Chapter 4 Using the cpuModule This chapter provides information for users who wish to develop their own applications programs for the CMX158886 cpuModule This chapter includes information on the following topics The RTD Enhanced AMI BIOS page 56 Memory Map page 59 Address Map page 60 Hardware Interrupts page 61 multiPort Advanced Digital Ports aDIO page 62 multiPort Parallel Port Control page 66 multiPort Floppy Drive page 66 AC 97 Audio page 66 Ethernet 10 100Base T and TX page 66 IDE Controller Configuration page 67 Real Time Clock Control page 69 Watchdog Timer Control page 71 Thermal Management page 72 Power Management page 73 Multi Color LED page 76 Reset Status Register page 77 DVMT Mode Select page 79 User EEPROM page 80 Features and Settings That Can Affect Boot Time page 81 System Recovery page 82 Basic Interrupt Information for Programmers page 83 BDM 610000049 Rev G Chapter 4 Using the cpuModule 55 The RTD Enhanced AMI BIOS The RTD Enhanced AMI BIOS is software that interfaces hardware specific features of the cpuModule to an operating system OS Physically the BIOS software is stored in a Flash EPROM on the cpuModule Functions of the BIOS are divided into two parts The first part of t
4. IDAN Pin 10Base T Signal CPU Pin Adapter Pin 1 1 Receive 1 2 2 Reserved 3 3 3 Transmit 5 4 4 Reserved 7 5 5 Ground 9 6 6 Receive 2 7 7 Reserved 4 8 8 Transmit 6 9 Reserved 8 102 CMX158886 cpuModule BDM 610000049 Rev Table74 Audio 9 Pin D Connector female IDAN Pin Signal CPU Pin 5 MIC VREF 1 4 GND 3 3 LINE IN GND 5 2 GND 7 2 GND 9 9 MIC IN 2 8 LINE IN LEFT 4 7 LINE IN RIGHT 6 6 OUTPUT LEFT 8 1 OUTPUT RIGHT 10 BDM 610000049 Rev G Appendix C Dimensions and Pinout 103 IDAN Dimensions and Connectors BRG version only This section describes some of the primary physical differences between the standard dual height IDAN cpuModule and the IDAN cpuModule that comes with a PCI to ISA bridge module BRG version 6 pin mini DIN female 9 pin D male module P N Adam Tech MDE006W module P N Adam Tech DEO9PD mating P N Adam Tech MDP006 mating P N Adam Tech DEO9SD M 1 UDIO MEN NN 74 E 4 FRONT 25 pin D female 9 pin D female module P N Adam Tech DB25SD module P N Adam Tech DEO9SD matingP N Adam Tech DB25PD mating P N Adam Tech DEO9PD 20 pin mini D female 15 pin high density D female module P N 3M 10220 6212VC module P N Adam Tech HDT15SD mating P N 10120 3000VE mating P N Adam Tech HDT15PD LVE USB me 340 le 37 l8 ETHERNET
5. 5V_STDBY 5 V standby Power 2 GND Ground 2 PME Power Management Event input Optional RTC Battery Input CN13 The optional RTC battery input is the connection for an external backup battery This battery is used by the cpuModule when system power is removed in order to preserve the date and time in the real time clock Connecting a battery is only required to maintain time when power is completely removed from the cpuModule A battery is not required for board operation Table36 Optional RTC Battery Input CN13 Pin Signal Function 1 BAT RTC Battery Input 2 GND Ground WARNING This optional RTC battery connector CN13 should be left unconnected if the utility port connector CN5 has a battery connected Fan Power 5 V CN14 If a fan is required to cool the cpuModule it can be wired to CN14 which provides a continuous connection to 5 V and ground Table37 Fan Power 5 V CN14 Pin Signal Function 1 45V 5 Volts DC 2 GND Ground Note To utilize the thermal fan mode feature in the BIOS the fan must be connected to CN15 BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 53 Fan Power Switched CN15 The switched fan power connector CN15 is an optional fan connector which allows the system to power the fan only when the processor temperature reaches high temperatures To utilize this connector refer to the Thermal Management section on page 72 Table38 Fan Power Switched CN15
6. 6 pin mini DIN female module P N Adam Tech MDEO06W 9 pin D male mating P N Adam Tech MDP006 module P N Adam Tech DEO9PD mating P N Adam Tech DEO9SD v cpuModule 1 AUDIO 3 574 RESET 00 2 ZUM _ RT EJ FRONT 25 pin D female module P N Adam Tech DB25SD pin D femal mating P N Adam Tech DB25PD module P N Adam Tech DEO9SD mating P N Adam Tech DEO9PD 20 pin mini D female 15 pin high density D female module P N 3M 10220 6212VC module P N Adam Tech HDT15SD mating P N 3M T d M 2 5 xm module P N Adam Tech DEO9PD mating P N Adam Tech DEO9SD Figure9 IDAN CMX158886 Connectors 1 Heatsink fins not shown in Figure 9 extend 0 75 inches from the sides of the IDAN frame 96 CMX158886 cpuModule BDM 610000049 Rev G External I O Connections BDM 610000049 Rev G Table 65 PS 2 Mouse 6 Pin mini DIN Connector female IDAN Pin Signal Function 1 MDAT Mouse Data 2 Reserved 3 GND Ground 4 5V 5 Volts 5 MCLK Mouse Clock 6 Reserved Table 66 Keyboard 6 Pin mini DIN Connector female IDAN Pin Signal Function 1 KDAT Keyboard Data 2 Reserved 3 GND Ground 4 T5V 5 5 KCLK Keyboard Clock 6 Reserved Appendix C Dimensions and Pinout 97 Table67 COM1 COM2 RS 232 9 Pin D Connector ma
7. 8 COM Ring Indicate in 9 9 10 GND Signal Ground 5 Table26 COMA RS 422 485 and COM B RS 422 485 Pin Signal Function In Out DB 9 1 RXD2 COM Receive Data in 1 2 RXD2 COM B Receive Data in 6 3 RXD1 COM A Receive Data in 2 4 TXD1 COM A Transmit Data out 7 5 TXD1 COM A Transmit Data out 3 6 RXD1 COM A Receive Data in 8 7 TXD2 COM B Transmit Data out 4 8 TXD2 COM B Transmit Data out 9 9 10 GND Signal Ground 5 Chapter 3 Connecting the cpuModule 41 multiPort CNG RTD s exclusive multiPort can be configured as an Advanced Digital I O aDIO a parallel port or a floppy drive Refer to Chapter 4 Using the cpuModule to configure the multiPort multiPort Electrostatic Discharge ESD and Undershoot Protection The multiPort interface provides electrostatic discharge ESD protection allowing the aDIO port parallel port and floppy port circuits to be protected from electrically charged external objects that may come in contact with the cpuModule The ESD protection minimizes susceptibility of the circuitry to ESD from human contact and is rated to withstand up to 2000V with the Human Body Model HBM standardized ESD test The protected circuitry is also rated to protect against up to 1000V with the Charged Device Model CDM standardized ESD test In addition to the ESD protection the circuitry also provides 2V undershoot protection by ensuring tha
8. RTC Without power the RTC will lose the date time information when the system is turned off The RTC also provides an alarm function This may be used to generate an interrupt at a particular time and day This feature is commonly used to wake up the system from Sleep Standby to run a scheduled task defragment the hard drive back up files etc In addition to the date time alarm functions the RTC contains several bytes of battery backed RAM commonly called CMOS memory In a typical desktop PC the CMOS memory is used by the BIOS to store user settings This RTD cpuModule uses onboard flash to store user BIOS settings To preserve compatibility with traditional PCs the RTD Enhanced BIOS also mirrors the user settings from flash in CMOS Therefore the contents of CMOS may be overwritten at boot time and should be treated as read only Accessing the RTC Registers You may access the RTC date time and CMOS memory using the Index and Data Registers located at I O addresses 70h and 71h e Address 70h is the Index register It must be written with the number of the register to read or write Valid values are to 7Fh e Address 71h is the Data register It contains the contents of the register pointed to by the Index To read write an RTC register you must first set the Index register with the register number and then read write the Data register A list of key RTC registers is shown in Table 52 below Table52 Real Time
9. Serial Port 1 CN7 and Serial Port 2 CN8 00 cece cece cece cence eee e me eme 37 Serial Port VART E ete eed NUN RU EG UE UI ASIE RE ERR 37 RS 232 Serial Port Default erre e e 37 RS 422 or RS 485 Serial he hh hh he he meses hehe 38 RS 422 and RS 485 Mode cece cece ener e e ehe mene eh he een 39 Dual Serial Port he e eme 40 multiPort dk arcet TUE 42 multiPort Configured as an Advanced Digital I O aDIO Port 42 multiPort Configured as a Parallel Port I Hee 43 multiPort Configured as a Floppy Drive cece eee eect eee eee 44 USB 2 0 Connector 17 e es e ens 45 Ethernet 10 100Base T and TX Connector 20 47 Audio aeriene wanes FIRES Denia PL dea 48 PC 104 Plus PCI Bus 1 I II eme ehe ehh ns 49 PC 104 Pl s PCI Bus rp rt e bi dant de 50 Address Data i e en eR a E Ere NP E EE Lowe 50 Interface Control PINS MM ex ers een ERG 50 EtrorReporthg OPEM EREMO s se PETER REIR 50 Arbit
10. Supports 480 Mb s high speed 12Mb s full speed and 1 5Mbs low speed peripherals 500 mA Q 5 Vdc provided per port USB Boot capability e UItraDMA 100 66 33 Master Mode PCI EIDE Controller Transfer rate up to 100MB sec using UltraDMA Increased reliability using UltraDMA 66 transfer protocols Support ATAPI compliant devices including DVD drives 48 bit LBA support for hard drives up to 2 2 terabytes e 32 pin ATA IDE Disk Chip Socket Miniature ATA IDE Flash Disk Chip Capacities up to 4GB Natively supported by all major operating systems e Utility port PC AT compatible keyboard port PS 2 Mouse Port Speaker port 0 1W output Hardware Reset input Battery input for Real Time Clock Soft Power Button input e Power I O Access to PCI 104 Bus pins Power ground 12 5 amp 3 3 VDC BIOS e RTD Enhanced AMI BIOS e User configurable using built in Setup program e Nonvolatile storage of CMOS settings without battery e Boot Devices Standard Devices floppy disk hard disk etc ATA IDE Disk Chip 1 Duringthe time of this manual s publication 4GB was the largest available ATA IDE Disk Chip capacity BDM 610000049 Rev Chapter 1 Introduction USB Device Network FailSafe Boot ROM e Surface mount Flash chip that holds ROM DOS e Quick Boot mode 10 CMX158886 cpuModule BDM 610000049 Rev G Block Diagram The next figure shows a simplified block diagram of t
11. 13 provides the pinout of the Flat Panel Video connector CN19 FP VCC is configured for 3 3V by default Contact RTD to have FP VCC configured for 5 V FP VBKLT can be either 5 V or 12 V and can be selected with JP9 See Jumper Settings and Locations on page 86 for more details Table 13 Flat Panel Video Connector CN19 Pin Signal Function In Out 1 YOP LVDS Data 0 out 2 YOM LVDS Data 0 out 3 DDC CLK Panel Detection Clock out 4 GND Ground GND 5 Y1P LVDS Data 1 out 6 YIM LVDS Data 1 out 7 DDC_DATA Panel Detection Data in out 8 GND Ground GND 9 Y2P LVDS Data 2 out 10 Y2M LVDS Data 2 out 11 GND Ground GND 12 GND Ground GND 13 YCP LVDS Clock out 14 YCM LVDS Clock out 15 Y3P LVDS Data 3 out 16 Y3M LVDS Data 3 out 17 GND Ground GND 18 FP Power for flat panel electronics out 19 FP VBKLT Power for flat panel backlight out 20 FP ENABLK Enable for Backlight Power out 1 The DDC signals use a 43 3 V signal level and are not 5 V tolerant 2 When configured for 43 3 V FP VCC is sourced from the auxiliary power connector CN3 or PC 104 Plus connector CN16 Table 14 lists several LVDS panels that were tested with this cpuModule When evaluating a panel to be used with this cpuModule review the specifications of the tested panels to assure compatability Table 14 Tested LVDS Panels Manufacturer Model Number Resolution Color Depth Optrex T 51756D121 FW
12. 485 modes open JP5 2 Install to load the default BIOS settings and boot to Fail Safe for more open information refer to System Recovery page 82 Note that the multi color LED will be red if JP5 is installed JP6 2 Reserved open JP9 3 Select power for flat panel backlight pins 2 3 pins 1 2 12 V pins 2 3 5 V JP11 2 Enable disable 120 series termination to second serial port on CN7 in open RS 422 485 modes JP12 2 Install to support RS 422 485 modes for second serial port on CN7 open JP13 2 Enable disable 120 series termination to second serial port CN8 in open RS 422 485 modes JP14 2 Install to support RS 422 485 modes for second serial port on CN8 open BDM 610000049 Rev G Appendix A Hardware Reference 87 Onboard PCI Devices The CMX158886 cpuModule has several onboard PCI devices all of which are listed in the table below Table 63 Onboard PCI Devices 88 CMX158886 cpuModule Device ID Vendor ID Description 103E 8086 LAN Controller 244E 8086 Hub to PCI Bridge 24C0 8086 PCI to LPC Bridge 24C2 8086 USB UHCI Controller 24C3 8086 SMBus Controller 24C5 8086 AC 97 Audio Controller 24CB 8086 IDE Controller 24CD 8086 USB EHCI Controller 3580 8086 Host Hub 3582 8086 Graphics Device 3584 8086 Main Memory 3585 8086 Configuration Process PCI Slot 1 s PCI Slot 2 PCI Slot 3 PCI Slot 4 BDM 610000049 Rev G Physical Dimensions Figure 8 shows the me
13. 610000049 Rev G Chapter 4 Using the cpuModule 79 User EEPROM A 512kB serial EEPROM Atmel AT93C66 is available on the cpuModule for the user to save nonvolatile parameters on the cpuModule The EEPROM can be accessed by reading and writting to I O address 456h as shown in the following table D7 cs 80 CMX158886 cpuModule D6 SK Bit D7 D6 05 04 03 02 D1 DO Table60 User EEPROM I O Address 456h 05 DI Table 61 Signal CS SK DI DO D4 D3 DO Reserved D2 D1 DO Multi Color LED EEPROM Register Description Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Reserved Multi Color LED Multi Color LED Multi Color LED Read Write Read Write Read Write Read Write Read Only BDM 610000049 Rev G Features and Settings That Can Affect Boot Time The boot time of a system is dependent upon numerous system settings as well as devices attached to a system This section addresses some devices and settings that can increase or decrease a system s boot time Quick Boot The BIOS contains a Quick Boot option that minimizes the boot time of the system Quick Boot eliminates the exhaustive tests that are performed during Power On Self Test POST while maintaining the functionality of the board By enabling the Quick Boot feature your system can achieve 5 second boot times Add On Cards With BIOS Extensions Some add on cards have an integrated BIOS extension
14. A AA 1024x768 18 bit Optrex T 51639D084JU FW A AB 1024 x 768 24 bit BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 33 EIDE Connector CN10 The EIDE connector is a 44 pin 2 mm connector that can connect to a variety of EIDE or IDE devices The connector provides all signals and power needed to use a 2 5 inch form factor laptop hard drive Also the first 40 pins of the connector provide all of the signals needed to interface to a 3 5 inch or 5 inch form factor hard drive CD ROM drive or other EIDE device The larger form factors use a 40 pin 0 1 inch spacing connector so an adapter cable or adapter board is needed to connect to CN10 Table 15 EIDE Connector CN10 1 Signal Pin Signal 1 RESET 2 GND 3 DD7 4 DD8 5 DD6 6 DD9 7 DDS 8 DD10 9 DD4 10 DD11 11 DD3 12 DD12 13 DD2 14 DD13 15 DD1 16 DD14 17 DDO 18 DD15 19 GND 20 N C 21 DMARQ 22 GND 23 DIOW STOP 24 GND 25 DIOR HDMARDY HSTROBE 26 GND 27 IORDY DDMARDY DSTROB 28 GND 29 DMACK 30 GND 31 INTRQ 32 N C 33 DA1 34 PDIAG 35 DAO 36 DA2 37 50 38 CS1 39 DASP 40 GND 41 5 V logic 42 5 V motor 43 GND 44 N C Signals marked with are active low 34 CMX158886 cpuModule BDM 610000049 Rev G ATA IDE Disk Chip Socket U16 The ATA IDE Disk Chip socket is a 32 pin socket that supports 3 3V or 5V miniature ATA IDE flash disk chips The socket allows a true IDE device
15. Exact power consumption depends on the actual application Table 2 lists power consumption for typical configurations and clock speeds Table2 cpuModule Power Consumption Module Speed RAM Power typ Power Max CMX158886PX 1 4 GHz 512 MB 12 7 W 15 2 W CMX158886CX 1 0 GHz 512 MB 10 9 W 12 2 W Operating Conditions Table 3 Operating Conditions Symbol Parameter Test Condition Min Max Vecs 5V Supply Voltage 4 75V 5 25V Vccs 3 3V Supply Voltage 12V Supply Voltage Vcca2 12V Supply Voltage Vecstay 5V Standby Voltage 475 5 25V lccsrgy 5V Standby Current 500mA Ta Ambient Operating Standard 40C 85C Temperature Ts Storage Temperature 40C 85 Rh Humidity Non Condensing 0 9096 MTBF Mean Time Before 23C 110 000 Failure hours 1 The 12V 12V and external 3 3V rails are not used by the cpuModule Any requirements on these signals are driven by other components in the system such as an LVDS Flat Panel or PCI device 2 5V Standby is used to power the board when the main supply is turned off power down modes 53 55 It is not required for board operation Electrical Characteristics The table below lists the Electrical Characteristics of the CMX158886 Operating outside of these parameters may cause permanent damage to the cpuModule 12 CMX158886 cpuModule BDM 610000049 Rev G BDM 610000049 Rev G Table4 Electrical Characteristics Parameter Output Voltage High O
16. Layer e 100Base Tx and 10Base T e Duplex support Easy to Use e Power Features e LED Status e Software configuration e 55 SVGA controller Onboard with 3D Acceleration DirectX amp OpenGL 3D Accelerator Analog SVGA Output LVDS Flat Panel output Resolution up to 2048 x 1536 pixels with 32K colors SVGA XGA SXGA UXGA Upto 16 million colors 64 bit AGP Hardware graphics accelerator 1MB to 64MB of shared DDR high performance memory e Software configurable RS 232 422 485 serial ports 16550 compatible UARTSs for high speed Termination resistors for RS 422 485 serial port connector can be configured as two limited serial ports for a total of four serial ports e multiPort function connector Parallel port SPP PS 2 bi directional EPP amp ECP Advanced Digital I O aDIO 8 CMX158886 cpuModule BDM 610000049 Rev G e 8 bit port programmable as input or output e Eight bit programmable I O with Advanced Digital Interrupt Modes e Event Mode Interrupt generates an interrupt when any input bit changes e Match Mode Interrupt generates an interrupt when input bits match a preset value e External Strobe Mode latches 8 data inputs and generates and interrupt e TwoStrobes can be configured as readable inputs Floppy controller interface e Interfaces with multiPort Floppy Drive and Cable Kit ESD protection e USB 2 0 Universal Serial Bus Ports
17. The most common examples are SCSI controllers and network cards with boot ROMs During POST the BIOS executes the card s extension code This extension code is third party code which is beyond RTD s control The BIOS extension will most likely increase the boot time Exactly how much it increases boot time will depend on the particular card and firmware version VGA Controller VGA controllers have a VGA BIOS that must be initialized during POST It can take some time to initialize the VGA BIOS Exactly how long will depend on the particular VGA controller and BIOS version Hard Drive Type During IDE initialization each IDE device must be probed Some devices take longer to probe 2 5 inch hard drives tend to take longer than 3 5 inch ones because they spin at a lower RPM Monitor Type Some monitors take a while to power on Desktop flat panels are especially slow This does not affect the actual boot time of the CPU However the CPU may boot before the monitor powers on NVRAM Updates System configuration data is stored in the onboard NVRAM When the system configuration changes this information must be updated If an update is necessary it will happen at the end of POST the BIOS will display an Updating NVRAM message The NVRAM update takes a few seconds and increases the boot time Once the NVRAM is updated boot times will return to normal NVRAM updates only happen when the system configuration changes They do not happen
18. USB Connector CN17 Pin Signal Function In Out 1 Supply 5 V USB1 out 2 Supply 5 V to USB2 out 3 DATA1 Bidirectional data line for USB1 in out 4 DATA2 Bidirectional data line for USB2 in out 5 DATA1 Bidirectional data line for USB1 in out 6 DATA2 Bidirectional data line for USB2 in out 7 GND Ground out 8 GND Ground out 9 GND Ground out 10 GND Ground out Chapter 3 Connecting the cpuModule 45 Facing the connector pins the pinout of CN17 is 5 3 1 6 4 2 9 7 10 8 46 CMX158886 cpuModule BDM 610000049 Rev G Ethernet 10 100Base T and TX Connector CN20 The functionality of the Ethernet port is based on the Intel 82562 Fast Ethernet PCI controller Table 31 provides the pinout of the Ethernet connector Table31 Ethernet Connector CN20 RJ 45 Pin 10 PinDILPin Signal Function In Out 3 1 RX Receive in 6 2 RX Receive in 1 5 TX Transmit out 2 6 TX Transmit out 4 3 CT Termination connected to pin 4 5 4 CT Termination connected to pin 3 7 7 CT Termination connected to pin 8 8 8 CT Termination connected to pin 7 9 AGND Ground 10 AGND Ground 9 7 5 3 1 BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 47 Audio CN11 A full featured AC97 compliant audio port is available on CN11 It provides a mono microphone input stereo line level input and a stereo output that can be configured
19. allows the system to turn on at a certain time every day AT vs ATX Power Supplies Both AT and ATX power supplies may be used with the CMX158886 cpuModule however AT power supplies do not provide any standby power to the cpuModule When an AT power supply is used to power the system low power modes that require a standby power to wake the system will not be fully supported ATX power supplies do provide a standby power thus allowing the system to utilize all low power modes supported by the hardware When an ATX supply is used to power the cpuModule lower power modes can be achieved During these low power modes the standby power from the ATX power supply provides power to a small circuit on the CPU which is used to watch for a system wake event ATX Power Supply Signals The auxiliary power connector CN3 provides two ATX style signals 5V Standby and PSON The 45V Standby rail is used to power certain parts of the cpuModule when the main power supply is turned off i e during Suspend to RAM S3 Hibernate S4 or Soft Off 55 power modes The PSON signal is an active low open drain output that signals the power supply to turn on Use of these signals allows the power consumption to drop to below 1W during standby modes and still enable any of the wake events 74 CMX158886 cpuModule BDM 610000049 Rev G Reducing Power Consumption In addition to the CPU s low power modes power consumption can further be reduced by making som
20. by your application program If it is not refreshed before the time out period expires it will cause a hardware reset of the cpuModule The watchdog time out period is typically 1 1 seconds but can vary between 550 ms and 1 65 seconds Because of operating system latency it is recommended that the watchdog be refreshed at half of the period or every 275 ms Before using the Watchdog timer it must be enabled in the BIOS setup utility When it is disabled in the BIOS the watchdog register does not appear in I O space and it will not generate an a reset EN Note Enabling the watchdog timer in the BIOS does not actually arm it The watchdog timer can be armed by accessing I O address 455h as explained below Three functions have been implemented on the cpuModule for controlling watchdog timer control These are The watchdog timer can be enabled by writing a 1 to bit 7 of I O port 0x455 To ensure compatability with future designs you should read the register and only change the bit you need to change e Disarm The watchdog timer is disabled by writing a 0 to bit 7 of I O port 0x455 To ensure compatability with future designs you should read the register and only change the bit you need to change e Refresh The watchdog timer is refreshed by reading from I O port 0x455 After you enable the watchdog timer you must refresh it at least once every 550 ms Table 53 Watchdog Timer Control I O Address 455h D7 06 05 04
21. change the interrupt you wish to use to Reserved Then select the appropriate interrupt mode in the DIO Control register Also verify that the Int Mask bit is cleared in the Wake Control register Advanced Digital Interrupts There are three Advanced Digital Interrupt modes available These three modes are Event Match and Strobe The use of these three modes is to monitor state changes at the aDIO connector Interrupts are enabled by writing to the Digital IRQ Mode field in the DIO Control register Event Mode When this mode is enabled Port 0 is latched into the DIO Compare register at 8 33 MHz The aDIO circuitry includes deglitching logic The deglitching requires pulses on Port 0 to be at least 120 ns in width As long as changes are present longer than that the event is guaranteed to register Pulses as small as 60 ns can register as an event but they must occur between the rising and falling edge of the 8 33 MHz clock To enter Event mode set bits 4 3 of the DIO Control register to 10 Match Mode When this mode is enabled Port 0 is latched into the DIO Compare register at 8 33 MHz The aDIO circuitry includes deglitching logic The deglitching requires pulses on Port 0 to be at least 120 ns in width As long as changes are present longer than that the match is guaranteed to register Pulses as small as 60 ns can register as a match but they must occur between the rising and falling edge of the 8 33 MHz clock To enter Matc
22. designed to be used in embedded computing applications In such environments rotating media like hard disks and floppy disks are not very desirable It is possible to eliminate rotating storage devices by placing your operating system and application software into the cpuModule s ATA IDE Disk Chip socket WARNING Before installing a device in the ATA IDE Disk Chip socket the system must be configured in the correct mode For details on configuring the socket refer to Chapter 4 Using the cpuModule Before installing a device in the ATA IDE Disk Chip socket itis highly recommend to first configure the secondary IDE controller and device mode in the BIOS setup The secondary IDE controller must be enabled in the BIOS to allow read and write access to the device When a device is installed in the socket it will always appear as a master on the cpuModule secondary IDE controller From the BIOS setup screen the user can also configure whether the socket contains a DMA mode or PIO mode device e DMA Mode DMA mode will reduce CPU overhead e Mode When the socket is in PIO mode PIO transfers are supported PIO mode supports write protection 68 CMX158886 cpuModule BDM 610000049 Rev G Real Time Clock Control Overview The cpuModule is equipped with a Real Time Clock RTC which provides system date and time functions When the cpuModule is turned off a battery must be attached to the utility connector to provide power to the
23. difficult Powering through the bus eliminates such problems as voltage drop and lead inductance If using the Auxiliary Power connector to power the system care must be taken to ensure a good power connections The power and ground leads must be twisted together or as close together as possible to reduce lead inductance A separate lead must be used for each of the power pins Both 5V pins must be connected The gauge of wire must be selected taking into account the total power of the system A good rule of thumb is to use wire that can supply twice the power required by the system and do not use less than 18 gauge wire The length of the wire must not exceed 3 ft The power supply solution must be verified by measuring voltage at the Auxiliary Power Connector and verifying that it does not drop below 4 75 V The voltage at the connector should be checked with an oscilloscope while the system is operational WARNING If you connect power incorrectly the module will almost certainly be destroyed Please verify power connections to the module before applying power Table7 Auxiliary Power Connector CN3 Pin Signal Function 1 GND Ground 2 5V 5 Volts DC 3 5V_STDBY 5V Standby ATX 4 12 V 12 Volts DC 5 Reserved Reserved 6 12V 12 Volts DC 7 GND Ground 8 5V 5 Volts DC 9 GND Ground 10 3 3 V See note below 11 PSON Power Supply On ATX 12 3 3 V See note below 1 For more information on the ATX
24. provided it is less than 10ns with the forcing current limited to 200 mA 3 Only required to maintain date and time when power is completely removed from the system Not required for board operation Contact Information RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA Phone 1 814 234 8087 Fax 1 814 234 5218 E mail sales rtd com techsupport rtd com Internet http www rtd com BDM 610000049 Rev G Chapter 1 Introduction 15 16 CMX158886 cpuModule BDM 610000049 Rev G Chapter2 Getting Started For many users the factory configuration of the CMX158886 cpuModule can be used to get a PC 104 system operational You can get your system up and running quickly by following the simple steps described in this chapter which are 1 Before connecting the cpuModule the user must be properly grounded to prevent electrostatic discharge ESD For more information refer to Proper Grounding Techniques on page 24 Connect power Connect the utility harness Connect a keyboard 2 3 4 5 Default BIOS configuration 6 FailSafe Boot ROM 7 Connect monitor to the SVGA connector Refer to the remainder of this chapter for details on each of these steps BDM 610000049 Rev G Chapter 2 Getting Started 17 Connector Locations Figure 3 shows the connectors and the ATA IDE Disk Chip socket of the CMX158886 cpuModule Cont Fan Power CN14 Mngmt PCI Bus CN1
25. silice DIUTIUS 84 Writing an Interrupt Service Routine 15 mI eene 84 Sample Code 84 Appendix Hardware Reference Jumper Settings and Locations sss IH mH see 86 Onboard PCI nnn ene he he he he hehehe hehe ean 88 Physical Dimensions cciac cies cedevks Re re v E E EUR REFECD R S ORNA ERR UE EXE RE ES 89 AppendixB Troubleshooting Common Problems and Solutions eee I ne 92 Troubleshooting a PC 104 Plus System ce cece cence ete ee 93 How to Obtain Technical He hee 94 AppendixC IDAN Dimensions and Pinout IDAN Dimensions and Connectors cece cece enn ehe hehehe 96 External I O Connections eorr datas nese E Ed UR S Meas vr nisu 97 IDAN Dimensions and Connectors version 104 External I O Connections BRG version 105 Appendix D Additional Information Application Notes CU UNO IU LER XLERER UT DS 107 Drivers and Example IH mH hee 107 Interrupt Programming dp 107 Serial Port Programming eem H e He e
26. spuriously They are usually triggered by adding or removing a PCI device from a stack Updates can also be triggered by altering the Plug n Play configuration of the BIOS Boot Device Order The BIOS contains a list of devices to try booting from If you wish to boot to a particular device for example a hard drive make sure that it is first in the boot order This will speed up boot times BDM 610000049 Rev G Chapter 4 Using the cpuModule 81 System Recovery Loading Default BIOS Settings The default BIOS can be restored either by using the Load Defaults option in the BIOS or by installing jumper JP5 see Figure 7 on page 87 In most cases the easiest way to load default settings is by setting them in the BIOS For other unique cases jumper JP5 provides an alternative method of restoring the BIOS settings To restore the default BIOS settings with jumper JP5 follow the procedure below 1 Remove power from the system 2 Install JP5 3 Apply power to the system The cpuModule will then load its default settings Note that the multi color LED will be red if power is applied while JP5 is installed 4 Rebootand press Delete to enter BIOS Setup 5 Savethe BIOS settings and exit allowing the system to boot to the FSBR 6 The next time the system is powered the BIOS Setup will be configured to use the default settings Booting to the Fail Safe Boot ROM FSBR If your system is in configuration that will not allow it to
27. the transaction Both IRDY and TRDY must be asserted to terminate a data cycle IRDY Initiator Ready indicates the master s ability to complete the current data cycle of the transaction STOP Stop indicates the current selected device is requesting the master to stop the current transaction DEVSEL Device Select is driven by the target device when its address is decoded IDSEL 3 0 Initialization Device Select is used as a chip select during configuration LOCK Lock indicates an operation that may require multiple transactions to complete Error Reporting PERR Parity Error is for reporting data parity errors SERR System Error is for reporting address parity errors Arbitration Bus Masters Only 3 0 Request indicates to the arbitrator that this device desires use of the bus GNT 3 0 Grant indicates to the requesting device that access has been granted System CLK Clock provides timing for all transactions on the PCI bus RST Reset is used to bring PCI specific registers to a known state Interrupts INTA Interrupt A is used to request Interrupts INTB Interrupt B is used to request Interrupts only for multi function devices INTC Interrupt C is used to request Interrupts only for multi function devices INTD Interrupt D is used to request Interrupts only for multi function devices 50 CMX158886 cpuModule BDM 610000049 Rev G Power Supplies a
28. this method there is a capacitor on the CBLID pin at the CPU and a pull up at the hard drive The CPU sends a command to the hard drive to drive the CBLID pin low and then release it The CPU then waits a certain amount of time and instructs the hard drive to read the status of the CBLID pin If an 80 conductor cable is attached the CBLID signal is not connected between the CPU and the hard drive and the hard drive will read the signal as a logic high If a 40 conductor cable is attached the CBLID pin is connected between the CPU and the hard drive the capacitor delays the signal from going high and the hard drive reads it as a logic low Host Determination of Cable Type For this method of detection the CPU reads the CPBLID pin which determines if a 40 conductor or 80 conductor cable is connected between the CPU and device An 80 conductor cable has this signal grounded at the CPU end and not connected to the hard drive A 40 conductor cable connects the CBLID signal to the hard drive where it is pulled to a logic high Device Detect For device detect mode the CPU issues a command to the device which tells the CPU the fastest drive speed mode it can use The CPU then sets the transfer mode to the fastest speed supported by the device device will be used regardless of whether a 40 conductor or 80 conductor cable is used If the device speed does not match the cable data corruption and unexpected behaviors may occur This mode shou
29. when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automatically pops the flags CS and IP that were pushed when the interrupt was called Most C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR RTD recommends focusing on the basics such as incrementing a global variable Most operating systems have restrictions on what instructions can be called in your ISR Consult your OS documentation for details on writing your ISR EN Note A complete explanation of interrupt programming is beyond the scope of this manual For more information on interrupts refer to the Appendix Sample Code RTD s drivers provide examples of ISR s and interrupt handling Refer to them as working examples These drivers were shipped with your cpuModule but they can also be downloaded from RTD s website www rtd com 84 CMX158886 cpuModule BDM 610000049 Rev G AppendixA Hardware Reference This appendix provide
30. 0 02 06 Added block diagrams to Appendix to show the dimensions and connectors of the IDAN CMX158886 that includes a PCI to ISA bridge board Added Network Boot bullet to list of board features Removed references to 1 1 GHz Pentium M processor D 11 29 06 Described 43 3 V source for FP VCC and added footnote for DDC signals see Table 13 on page 33 Added section to Chapter 4 DVMT Mode Select page 79 Removed table describing solder jumpers see footnote of Table 62 on page 87 Added height of Mini Fan Heatsink see Physical Dimensions on page 89 Made correction to IDAN SVGA connector pinout table see Table 71 on page 101 Added dimension of heatsink fins on IDAN frames see page 96 and page 104 E 2 23 07 Removed Thermal Throttling Corrected multiPort Floppy setup Removed EEPROM section Updated board name F 1 9 08 Added 1024 MB versions Combined PX and CX manuals Added support for dual serial ports Corrected storage temperatures G 5 21 08 Corrected Table 26 COM A RS 422 485 and COM B RS 422 485 41 Added User EEPROM on page 80 Corrected aDIO Connector in Figure 10 IDAN CMX158886 BRG Connectors 104 Added information for ECC verison ii CMX158886 cpuModule BDM 610000049 Rev G CMX158886 cpuModules www rtd com An 1509001 2000 Company Accessing the Analog World iv CMX158886 cpuModule BDM 610000049 Rev G Table of Contents Chapter 1 Introduction CMX158886 cpuModules sss He Hs me
31. 158886 cpuModule Table70 Panel 20 Pin mini D Connector female IDANPin Signal Name CPU Pin 1 LVDS YAPO 1 2 LVDS DDCPCLK 3 3 LVDS_YAP1 5 4 LVDS_DDCPDATA 7 5 LVDS_YAP2 9 6 GND 11 7 LVDS_CLKAP 13 8 LVDS_YAP3 15 9 GND 17 10 FP_BKLT 19 11 LVDS_YAMO 2 12 GND 4 13 LVDS_YAM1 6 14 GND 8 15 LVDS_YAM2 10 16 GND 12 17 LVDS_CLKAM 14 18 LVDS_YAM3 16 19 FP_VCC 18 20 LVDS_BKLTCTL 20 BDM 610000049 Rev G BDM 610000049 Rev G Table 71 SVGA 15 Pin High Density D Connector female IDAN Pin Signal Function CPU Pin 1 Red Red Analog Output 4 2 Green Green Analog Output 6 3 Blue Blue Analog Output 8 4 Reserved Reserved 5 GND Ground 9 6 GND Ground 9 7 GND Ground 9 8 GND Ground 10 9 45V 5 Volts 7 10 GND Ground 10 11 Reserved Reserved 12 DDC Data Monitor data 5 13 HSYNC Horizontal Sync 2 14 VSYNC Vertical Sync 1 15 DDC CLK Monitor Clock 3 Appendix C Dimensions and Pinout 101 Table 72 USB 9 D Connector male IDAN Pin Signal Function Mode 1 5 V to USB1 output 2 Data USB1 USB1 Data input output 3 Data USB1 USB1 Data input output 4 GND Ground 5 GND Ground 6 5 V to USB2 output 7 Data USB2 USB2 Data input output 8 Data USB2 USB2 Data input output 9 GND Ground Table73 Ethernet 9 Pin D Connector female
32. 6 Audio ideo bed CN11 LVDS Flat Panel CN19 COMI CN7 O 000000000 n 0000000000 w Switched i Fan 99 CENTS CN8 multiPort USB 2 0 CN6 CN17 Ethernet CN20 3 H i Multi H000000000000000 E Function 9553288 gum 5 000000 rd Auxiliary Power Battery ISA Bridge Link CN3 CN13 IDE CN10 CN4 Figure 3 158886 Connector Locations Note Pin 1 of each connector is indicated by a white silk screened square on the top side of the board EN and a square solder pad on the bottom side of the board Pin 1 of the bus connectors match when stacking PC104 Plus or PCI 104 modules 18 CMX158886 cpuModule BDM 610000049 Rev Table5 CMX158886 Basic Connectors Connector Function Size CN3 Auxiliary Power 12 pin CN4 Bridge Link 4 pin CN5 Utility Port 10 pin CN6 multiPort 26 pin CN7 Serial Port 1 COM1 10 pin CN8 Serial Port 2 COM2 10 pin CN10 EIDE Connector 44 pin CN11 Audio Connector 10 pin CN12 External Power Management 3 CN13 RTC Battery Input optional 2 CN14 Fan Power 45V 2 pin CN15 Fan Power switched 2 pin CN16 PC 104 Plus PCI Bus 120 pin CN17 USB 2 0 10 pin CN18 Video SVGA 10 pin CN19 Flat Panel Video LVDS 30 pin CN20 Ethernet 10 pin U16 ATA IDE Disk Chip Socket 32 pin WARNING If you connect power incorrectly the module will almost certainly be damaged or dest
33. 9 SERR GND Reserved PSON PAR 10 GND PERR 3 3 Reserved PME 11 STOP 3 3 V LOCK GND 12 3 3 TRDY GND DEVSEL 13 FRAME GND IRDY 3 3 V 14 GND AD16 3 3 V C BE2 15 AD18 3 3 V AD17 GND 16 AD21 AD20 GND AD19 17 3 3 V AD23 AD22 3 3 V 18 IDSELO GND IDSEL1 IDSEL2 19 AD24 C BE3 VIO IDSEL3 20 GND AD26 AD25 GND 21 AD29 5V AD28 AD27 22 5V AD30 GND AD31 23 REQO GND REQI VIO 24 GND REQ2 5V GNTO 25 GNT1 VIO GNT2 GND 26 5V CLKO GND CLK1 27 CLK2 5V CLK3 GND 28 GND INTD 5V RST 29 12 V INTA INTB INTC 30 12V REQ3 GNT3 GND 1 Signals marked with are active low 2 Optional signals for ATX power management BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 49 PC 104 Plus PCI Bus Signals The following are brief descriptions of the PC 104 Plus PCI bus signals Address and Data AD 31 00 Address and Data are multiplexed A bus transaction consists of an address cycle followed by one or more data cycles C BE 3 0 Bus Command Byte Enables are multiplexed During the address cycle the command is defined During the Data cycle they define the byte enables PAR Parity is even on AD 31 00 and C BE 3 0 and is required Interface Control Pins FRAME Frame is driven by the current master to indicate the start of a transaction and will remain active until the final data cycle TRDY Target Ready indicates the selected devices ability to complete the current data cycle of
34. 9 pin D male 37 pin high density D female module P N Adam Tech DEO9PD module P N Adam Tech HDT37SD mating P N Adam Tech DEO9SD mating P N Adam Tech HDT37PD Figure 10 IDAN CMX158886 BRG Connectors 1 Heatsink fins not shown in Figure 10 extend 0 75 inches from the sides of the IDAN frame 104 CMX158886 cpuModule BDM 610000049 Rev G External I O Connections version only An additional connector is added to the IDAN PCI to ISA bridge configuration to allow additional digital signals to be accessible from outside the IDAN frame The pinout for this connection is shown in the table below Table 75 aDIO 37 Pin D Connector female BRG Pin Function IDAN Pin 1 P1 0 1 2 GND 20 3 P1 1 2 4 GND 21 5 P1 2 3 6 GND 22 7 P1 3 4 8 GND 23 9 P1 4 5 10 GND 24 11 P1 5 6 12 GND 25 13 P1 6 7 14 GND 26 15 P1 7 8 16 GND 27 17 P1 Strobe 9 18 GND 28 19 P2 0 10 20 GND 29 21 P2 1 11 22 GND 30 23 P2 2 12 24 GND 31 25 P2 3 13 26 GND 32 27 P2 4 14 28 GND 33 29 P2 5 15 30 GND 34 31 P2 6 16 32 GND 35 33 P2 7 17 BDM 610000049 Rev G Appendix C IDAN Dimensions and Pinout 105 106 CMX158886 cpuModule BRG Pin Function IDAN Pin 34 GND 36 35 P2 Strobe 18 36 GND 37 37 5 Volts Fused 2A 19 38 GND N C 39 GND N C 40 GND N C BDM 610000049 Rev G Appendix D Additional Information Ap
35. A MultiPort can be configured as a standard EPP ECP parallel port a floppy drive port or an Advanced Digital aDIO port The DDR SDRAM controller on selected models uses Error Correcting Codes ECC to correct single bit memory errors and detect two bit memory errors providing for a more robust memory system SDRAM is soldered directly to the board for high vibration resistance The CMX158886 is also available in a rugged fanless IDAN enclosure Cont Fan Power SVGA CN14 Mngmt PCI Bus CN16 Audio Video CN11 CN18 22000000000000000000000000000000 os 29 000000000000000000000000000000 50000 LVDS Flat 99 Panel _ 09 99 COMI CN19 99 005 CN7 99 oo af Switched x Fan CN15 COM2 oom Hoo CN8 199 goo on 89 rr m see i m oo ultiPort USB 2 0 99 E _ oo CN6 17 gt on TH Ethernet oo CN20 Multi oH 000000000000000 Function a KELLI CN5 o ATA IDE Wi Auxiliary Power Battery ISA Bridge Link CN3 CN13 IDE CN10 CN4 Figure 1 CMX158886 cpuModule top view 2 CMX158886 cpuModule BDM 610000049 Rev G Enhanced Intel SpeedStep PX only Enhanced Intel SpeedStep Technology has revolutionized thermal and power management by giving appli
36. Access D7 D6 D5 D4 D3 D2 D1 DO Strobe 0 Status Strobe 1 Status 0 no strobe 0 no strobe 1 strobe 1 strobe Digital IRQ Mode Multi Function 00 Disabled Register Select Digital IRQ Status 01 strobe Mode Port 1 Direction 00 clear mode 0 no digital interrupt 10 event mode 0 input 01 port 0 direction 1 digital interrupt 11 match mode 1 output 10 mask register 11 compare register Table 48 DIO Control I O Address 453h Write Access D7 D6 05 04 03 02 01 00 Reserved Digital IRQ Mode Multi Function 00 Disabled Register Select 01 strobe Mode Port 1 Direction 00 clear mode _ 10 event mode 0 input 01 port 0 direction 11 match mode 1 output 10 mask register 11 compare register Table 49 Multi Function at Address 452h read write 00 clear X X X X X X X X Oin 1 out 01PortOdirection O 0 no mask 1 mask 10 DIO mask M7 M6 M5 M4 M3 M2 M1 MO read write 11 compare C7 C6 C5 C4 C3 C2 C1 1 Contents based on bits DO D1 of DIO Control Clear Register A read to this register Clears the IRQs and a write to this register sets the DIO Compare DIO Mask DIO Control Port 1 and Port 0 to zeros A write to this register is used to clear the board Port 0 Direction Register Writing a zero to a bit in this register makes the corresponding pin of the aDIO connector an input Writing a one to a bit in this register makes the cor
37. CMX158886 cpuModules User s Manual BDM 610000049 Revision G www rtd com An 1509001 2000 Company Accessing the Analog World CMX158886 cpuModules User s Manual RTD Document Number BDM 610000049 Revision G Copyright 2008 RTD Embedded Technologies Inc All rights reserved Trademarks Advanced Digital I O aDIO a2DIO Autonomous SmartCal cpuModule dspFramework dspModule IDAN HiDAN HiDANplus MIL Value for COTS prices multiPort and PC 104EZ are trademarks and Accessing the Analog World dataModule RTD and the RTD logo are registered trademarks of RTD Embedded Technologies Inc PS 2 PC XT PC AT and IBM are trademarks of International Business Machines Inc MS DOS Windows Windows 95 Windows 98 and Windows NT are trademarks of Microsoft Corporation Linux is a registered trademark of Linus Torvalds ROM DOS is a trademark of Datalight Inc Intel is a registered trademark of Intel Corporation PC 104 is a registered trademark of PC 104 Consortium All other trademarks appearing in this document are the property of their respective owners Contents and specifications within this manual are subject to change without notice Revision History Revision Date Reason for Change A 12 13 06 Initial release B 07 26 06 Added section to Chapter 3 with instructions for installing an ATA IDE Disk Chip Removed the Preliminary tag on the cover sheet Added section describing proper grounding techniques 1
38. Clock Registers Registers Registers Function hex decimal 00h 0 RIC Seconds 02h 2 RTC Minutes 04h 4 RTC Hours 06h 6 RTC Day of Week 07h 7 RTC Day of Month 08h 8 RTC Month 09h 9 RIC Year 10 Status Register e 7 RTC Update Progress Read Only RTC registers should not be accessed when this bit is high e Bits 6 4 Divider for 32 768 KHz input should always 010 e Bits 3 0 Rate select for periodic interrupt BDM 610000049 Rev G Chapter 4 Using the cpuModule 69 Table52 Real Time Clock Registers Registers Registers Function hex decimal OBh 11 RTC Status Register B e Bit7 Inhibit Update When high the RTC is prevented from updating e Bit Periodic Interrupt Enable When high the RTC IRQ will be asserted by the periodic interrupt e Bit5 Alarm Interrupt Enable When high the RTC IRQ will be asserted when the current time matches the alarm time e Bit 4 Update Ended Interrupt Enable When high the RTC IRQ will be asserted every time the RTC updates once per second e Square Wave Enable Not used e Bit 2 Data Mode Sets the data format of the RTC clock calendar registers 0 1 binary This is typically set to BCD mode e Bit 1 Hours Byte Format Sets the hour byte to 12 or 24 hour time 0 12 hour 1224 hour This is typically set to 24 hour mode e Bit 0 Daylight Savings Enable When high the RTC will automat
39. D 38 CMX158886 cpuModule BDM 610000049 Rev G RS 422 and RS 485 Mode Pinout Table 21 provides the serial port connector pinout when RS 422 or RS 485 modes are enabled Table21 Serial Port in RS 422 485 Mode Pin Signal Function In Out DB 9 1 Reserved 1 2 Reserved 6 3 RXD Receive Data in 2 4 TXD Transmit Data out 7 5 TXD Transmit Data out 3 6 RXD Receive Data in 8 7 Reseved 4 8 Reseved 9 9 10 GND Signal Ground out 5 Facing the serial port connector the pinout is software control The transmitters are enabled by manipulating the Request To Send RTS signal of the serial port controller This signal is controlled by writing bit 1 of the Modem Control Register MCR as follows Note When using the serial port in RS 485 mode the serial transmitters are enabled and disabled under e If MCR bit 1 1 then RTS 0 and serial transmitters are disabled e f MCR bit 1 0 then RTS 1 and serial transmitters are enabled Note For more information on the serial port registers including the MCR refer to the Serial Port Programming reference in Appendix D BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 39 Dual Serial Port Modes The serial port connectors can be configured as dual serial ports in the BIOS The mapping between the connectors and COM port numbers is shown in Table 22 The supported combinations of serial port mo
40. D3 D2 Di DO Watchdog Enable Reserved 0 Watchdog timer is disabled and will not generate an interrupt 1 Watchdog Timer is enabled and needs to be refreshed BDM 610000049 Rev G Chapter 4 Using the cpuModule 71 Thermal Management The cpuModule has several thermal features which can be used to monitor and control the board s temperature when extreme operating conditions are prevalent Thermal Monitor The Intel Thermal Monitor is a feature on the CMX158886 that automatically initiates a SpeedStep transition or throttles the CPU when the CPU exceeds its thermal limit The maximum temperature of the processor is defined as the temperature that the Thermal Monitor is activated The thermal limit and duty cycle of the Thermal Monitor cannot be modified EN Note The CPU and PCB temperatures displayed in the BIOS are approximate and should not be used to validate a cooling solution Fan Mode The CPU fan can be controlled by the CPU when connected to the switched fan power connector CN15 Three fan modes are supported which can be toggled in the BIOS setup When the fan is not always on the CPU s power consumption is reduced and the life of the fan is increased e Always On When in this mode the fan is always powered by the CPU e On At70C This mode allows the system to keep the fan turned off until the CPU reaches 70C In this mode the fan will slowly transition between on and off to prevent oscillations This is the bes
41. OS When enabled the multi color LED will blink to indicate an Ethernet connection For more information refer to the Multi Color LED section on page 76 66 CMX158886 cpuModule BDM 610000049 Rev G IDE Controller Configuration The CPU s onboard EIDE connector CN10 supports several different drive speed modes which are BIOS configurable Supported drive modes will depend on whether a 40 conductor or 80 conductor cable is connecting the EIDE device The modes and cable detection schemes described below may be set in the BIOS Setup Similarly the ATA IDE Disk Chip socket U16 is BIOS configurable Cable Modes There are two types of cables that may be used for connecting drives to the EIDE connector 40 conductor cables or 80 conductor cables Depending on the cable used different drive speeds are supported A 40 conductor cable can be used for speeds up to UDMA Mode 2 Ultra ATA 33 In order to use drive speeds faster than UDMA Mode 2 Ultra ATA 33 an 80 conductor cable is required The BIOS can be configured to detect the presence of an 80 conductor cable The 80 conductor cable adds a ground wire between each signal and uses standard 40 pin connectors Cable Detection Every time the cpuModule is powered on or a hardware reset is issued the BIOS will automatically detect the presence of a 80 conductor cable connecting a device to CN10 The user selectable cable detection modes are described below Device and Host Mode For
42. Setup program If you don t press Delete the cpuModule will try to boot from the current settings If you press Delete the cpuModule will enter Setup Once you have configured the cpuModule using Setup save your changes and reboot Note You may miss the initial sign on messages if your monitor takes a while to power on Note By default cpuModules are shipped with Fail Safe Boot ROM enabled When Fail Safe Boot ROM is enabled the system will boot to it exclusively 22 CMX158886 cpuModule BDM 610000049 Rev G Chapter 3 Connecting the cpuModule This chapter provides information on all CMX158886 cpuModule connectors Proper Grounding Techniques page 24 Connector Locations page 24 Auxiliary Power CN3 page 26 Utility Port Connector CN5 page 28 SVGA Video Connector CN18 page 31 LVDS Flat Panel Video Connector CN19 page 33 EIDE Connector CN10 page 34 ATA IDE Disk Chip Socket U16 page 35 Serial Port 1 CN7 and Serial Port 2 CN8 page 37 multiPort CN6 page 42 USB 2 0 Connector CN17 page 45 Ethernet 10 100Base T and TX Connector CN20 page 47 Audio CN11 page 48 PC 104 Plus PCI Bus CN16 page 49 Bridge Link CN4 page 52 External Power Management CN12 page 53 Optional RTC Battery Input CN13 page 53 Fan Power 5 V CN14 page 53 Fan Power Switched 15 page 54 BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 23 Prop
43. ace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to RTD Embedded Technologies All replaced parts and products become the property of RTD Embedded Technologies Before returning any product for repair customers are required to contact the factory for a Return Material Authorization number This limited warranty does not extend to any products which have been damaged as a result of accident misuse abuse such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by RTD Embedded Technologies acts of god or other contingencies beyond the control of RTD Embedded Technologies or as a result of service or modification by anyone other than RTD Embedded Technologies Except as expressly set forth above no other warranties are expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose and RTD Embedded Technologies expressly disclaims all warranties not stated herein All implied warranties including implied warranties for merchantability and fitness for a particular purpose are limited to the duration of this warranty In the event the product is not free from defects as warranted above the purchaser s sole remedy shall be repair or replacement as provided above Under no circumstances will RTD Embedded Technologies b
44. age Low lg 80 mA DDC Input Voltage High DDC Input Voltage Low DDC Supply Current for DDC Electronics Serial Ports RS 232 Output Voltage High 3k Output Voltage Low R 3k Input Voltage High Input Voltage Low x Serial Ports RS 422 485 Differential Output 50 Ohm Differential Output R 2 27 Ohm Common Mode 27 or 50 Output Ohm Differential Input 7V lt Vem lt 7V Threshold Absolute Max Input Voltage multiPort all modes Output Voltage High 74 0 mA Output Voltage Low lg 80 mA Input Voltage High Input Voltage Low Supply current Utility Port Connector CN5 Input RTC Voltage Utility Supply Current Min 3 8 V 0 0 V 2 4 V 0 0 V 2 0 V 0 3 V 5 0 V 10 0 24V 25V 2 0 V 15V 0 0 V 0 3 V 25 V 2 4 V 0 0 V 2 0 V 0 5 V 2 0V External Power Management CN12 PME Input Voltage High Input Voltage Low 2 0 V 0 5 V Max 5 0 V 0 55 V 3 3 V 0 4 V 5 5 V 0 8 V 100 mA 10 0 V 5 0 V 25V 0 8 V 60V 60V 30V 0 3 V 25V 3 3 V 0 4 5 5 V 0 8 V 500 3 6 500 5 5 0 8 V 14 CMX158886 cpuModule 1 Applies to modes up to UltraDMA Mode 4 ATA 66 BDM 610000049 Rev G 2 Maximum DC undershoot below ground must be limited to either 0 5V or 10mA During transitions the device pins may undershoot to 2 0V or overshoot to 7 0V
45. andby power supplies reserved PCI bus reset signal Utility connector push button reset 1 When reset is asserted all resets with a higher reset priority will also be asserted For example if the standby power reset is asserted all other resets will also be asserted 2 The BIOS allows the user to change the function of the utility connector s push button reset Even if the push button is not configured as a reset this bit will always read a 1 asserted when the reset button has been pushed 78 CMX158886 cpuModule BDM 610000049 Rev G DVMT Mode Select The CMX158886 supports Dynamic Video Memory Technology DVMT DVMT allows the CPU to allocate memory to system processing or graphics processing on the fly based on changing processing requirements For example a graphics intensive program will require the operating system to request a larger amount of video memory than one that does not require large amounts of graphics processing For the graphics intensive process DVMT will allocate a larger portion of system memory When the process is complete DVMT will allocate the memory back to the system The CMX158886 supports three user selectable modes including Fixed Mode DVMT Mode and Combo Mode e Fixed Mode A fixed amount of system memory is reserved for video e DVMT Mode Video memory is dynamically allocated as needed e Combo Mode A fixed amount of memory is allocated but more can be claimed as needed BDM
46. as line level or headphone level The output is configured in the BIOS setup utility When used as a headphone output it will drive 32 Ohm speaker at 50mW Table32 Audio Connector CN11 10 Pin DILPin Signal Function In Out 1 MIC VREF 22V Supply to bias out microphones 5mA max 2 MIC_IN Microphone input 1V RMS or in 0 1V RMS 3 GND Signal GND GND 4 LINE_IN_LEFT Line level input for left channel in 1V RMS nominal 5 GND Signal GND GND 6 LINE_IN_RIGHT Line level input for right channel in 1V RMS nominal 7 GND Signal GND GND 8 OUTPUT_LEFT Left channel output Selectable out as line level 1V RMS or headphone 9 GND Signal GND GND 10 OUTPUT RIGHT Left channel output Selectable out as line level 1V RMS or headphone 9 7 5 3 1 OUTPUT RIGHT OUTPUT LEFT LINE IN RIGHT LINE IN LEFT MIC IN 48 CMX158886 cpuModule BDM 610000049 Rev G PC 104 Plus PCI Bus CN16 Connector CN16 carries the signals of the PC 104 Plus PCI bus These signals match definitions of the PCI Local Bus specification Revision 2 1 Table 33 list the pinouts of the PC 104 Plus bus connector Table33 PC 104 Plus Bus Signal Assignments Pin A B D 1 GND Reserved 5V_STDBY 5 ADOO 2 VIO ADO2 ADO01 5 3 05 GND AD04 AD03 4 C BEO AD07 GND ADO06 5 GND ADO09 08 GND 6 AD11 VIO AD10 M66EN 7 AD14 AD13 GND AD12 8 3 3 C BE1 AD15 3 3
47. board Power 5 V 4 System Reset Pin 3 of the multi function connector allows connection of an external push button to manually reset the system The push button should be normally open and connect to ground when pushed Soft Power Button Pin 4 of the multi function connector allows connection of an external push button to send a soft power signal to the system The push button should be normally open and connect to ground when pushed For more information on the modes of the Soft Power Button refer to the Power Management section in Chapter 4 Using the cpuModule BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 29 Battery Pin 9 of the multi function connector is the connection for an external backup battery This battery is used by the cpuModule when system power is removed in order to preserve the date and time in the real time clock Connecting a battery is only required to maintain time when power is completely removed from the cpuModule A battery is not required for board operation WARNING The optional RTC battery input connector CN13 should be left unconnected if the multi function connector CN5 has a battery connected to pin 9 30 CMX158886 cpuModule BDM 610000049 Rev G SVGA Video Connector CN18 Table 11 provides the pinout of the video connector Table 11 SVGA Video Connector CN18 Pin Signal Function In Out 1 VSYNC out 2 HSYNC Horizontal Sync out 3 DDCSCL Monitor Comm
48. boot the Fail Safe Boot ROM is a minimal build of ROM DOS which can be booted to for system debugging To boot to the FSBR follow the instructions below 1 Reboot the system and press Delete to enter BIOS Setup 2 Inthe Boot menu select Bootup Options and change RTD Fail Safe Boot ROM to Enabled 3 Savethe BIOS settings and exit If you are unable to enter the BIOS Setup an alternate method is to use JP5 as described below 1 Remove power from the system 2 Install JP5 This will force the cpuModule to boot using the default BIOS configuration 3 Apply power to the system The cpuModule will then boot to the Fail Safe Boot ROM image Note that the multi color LED will be red if power is applied while JP5 is installed 4 Press the Delete key to enter Setup or allow the cpuModule to boot to Failsafe 82 CMX158886 cpuModule BDM 610000049 Rev G Basic Interrupt Information for Programmers An interrupt is a subroutine called asynchronously by external hardware usually an I O device during the execution of another application The CPU halts execution of its current process by saving the system state and next instruction and then jumps to the interrupt service routine executes it loads the saved system state and saved next instruction and continues execution Interrupts are good for handling infrequent events such as keyboard activity Interrupts on this cpuModule are controlled by two Intel 8259 equivalent interrupt controllers contain
49. cation software greater control over the processor s operating frequency and input voltage Systems can easily manage power consumption dynamically Today s embedded systems are demanding greater performance at equivalent levels of power consumption Legacy hardware support for backplanes board sizes and thermal solutions have forced design teams to place greater emphasis on power and thermal budgets Intel has extended architectural innovation for saving power by implementing new features such as Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology allows the processor performance and power consumption levels to be modified while a system is functioning This is accomplished via application software which changes the processor speed and the processor core voltage while the system is operating A variety of inputs such as system power source processor thermal state or operating system policy are used to determine the proper operating state The software model behind Enhanced Intel SpeedStep Technology has ultimate control over the frequency and voltage transitions This software model is a major step forward over previous implementations of Intel SpeedStep technology Legacy versions of Intel SpeedStep technology required hardware support through the chipset Enhanced Intel SpeedStep Technology has removed the chipset hardware requirement and only requires the support of the voltage regulator processor and operating system Centralizat
50. chanical dimensions of the CMX158886 cpuModule 4 550 IN 115 570 mm 4 050 IN 102 878 mm ae 0 200 IN 5 080 mm 2 988 IN 73 660 mm 0 850 IN 21 598 mm 6 350 mm 1 670 IN 42 418 mm 3 450 IN 87 638 mm 1 675 IN 42 545 mm 3 325 IN 3 775 IN 84 455 mm 95 885 mm 9 325 IN 8 255 mm 9 550 IN 13 970 mm 2 000 IN 50 800 mm Figure8 CMX158886 Physical Dimensions 0 005 inches Heatsink height The mini fan heatsink on the CMX158886 extends 0 6 inches above the top side of the PCB BDM 610000049 Rev G Appendix A Hardware Reference 89 90 CMX158886 cpuModule BDM 610000049 Rev G AppendixB Troubleshooting Many problems you may encounter with operation of your CMX158886 cpuModule are due to common errors This appendix includes the following sections to help you get your system operating properly Common Problems and Solutions page 92 Troubleshooting a PC 104 Plus System page 93 How to Obtain Technical Support page 94 BDM 610000049 Rev G Appendix B Troubleshooting 91 Common Problems and Solutions Table 64 lists some of the common problems you may encounter while using your CMX158886 cpuModule and suggests possible solutions If you are having problems with your cpuModule review this table before contacting RTD Technical Support Problem cpuModule will not boot Table64 Troubleshooting Ca
51. ches UU 21 PCI Bus Expansion Card Power esse ee sere demas K tke rre ret sed Re RE E e 21 5 Volt EET 21 333 en 21 PCIBus Signaling Level o pacsoasuyes wuts be ee EEA encumneeanadinence 21 Booting the CMX158886 cpuModule for the First 22 Chapter 3 Connecting the cpuModule Proper Grounding Techniques nee IH mee ee 24 Connector Locations ER PEU sade tT SNO ESQ C bSE sed UR 24 Auxiliary Power CN3 eiue s obi Rex bebe SS arse Eades 26 Utility Port Connector CNS 0 cc ccc ccc cee cece II eem e eme nan 28 28 Keyboards AEO 29 MOUSE TTE 29 29 BDM 610000049 Rev G DV Soft Power Button dioses Ra ca ac exa PE E Sa ER de 29 Drug 30 SVGA Video Connector 18 cece eee eet esee nme ana 31 LVDS Flat Panel Video Connector 19 cece cece cece ene Innes 33 EIDE Connector 10 ne e I esse EEE EEE EEE EEE ES 34 ATA IDE Disk Chip Socket 016 ene III memes 35 Installing and Configuring the ATA IDE Disk nee 35
52. cy Mode and Native Mode IDE cece ccc cree cnet II Hessen 68 Legacy Mode uoce o ERR RIPE 68 iore poene ERR MAU 68 Configuring the ATA IDE Disk Chip Socket mne 68 Real Time Clock hh he heme hee 69 OVERVIEW Shae aaa GE VUES AN ERREUR ERR ERR Pe aha bad DORE TE QUIE OU TORRE EE 69 Accessing the RIG Registers scc UU v b RR AR UUDEFERURE UE Bob Readme 69 Watchdog Timer Control rp e ede rH ade e RUNE Uy Rire RE dg 71 Thermal Management 2 becca ci Vad hee in DU LEE ned Sadie UNE NS aed he ene PUES 72 Thermal MORItOE tes SSS ees SA Shedd tae ae 72 MOG oodd A Ie BR ead bob IAS Ae eee EE EERE LESTE AN MOUS gt RUS RA 72 Further Temperature cree cnet eme mH emen 72 Power Management vex eerte E plea e doles eae EE dee sen e E E cols 73 Enabling Enhanced Intel SpeedStep Technology PX 73 Advanced Configuration and Power Interface ACPI nn 73 Power B tton coetus tt pot pte RR NE EE UUUBL Ob weeks hea htt bebfe ERE 73 Low Power Wake cece cece cee cee IH He e He eme Hs e esee 73 AT vs ATX Power Supplies 33323 prre EE rre eise FETTE T 74 ATX Power Su
53. de and IRQ multiPort Floppy Drive The multiPort connector can be configured as a floppy drive To utilize the floppy controller the multiPort mode must be first be set to Floppy Drive in the BIOS The complete process for setting up the multiPort as a floppy drive is described below 1 With the system powered off attach a floppy drive with an adapter board to CN6 Power on the system and enter the BIOS setup screen by pressing the delete key as the system boots Set Drive A to 1 44 MB in the Standard CMOS Settings section of BIOS Setup Set the multiPort to Floppy in the BIOS Setup OBS If booting to the floppy drive is required set the first boot device in the boot sequence to floppy drive When the floppy drive is enabled a special cable and adapter board is required For more information about this cable kit refer to the Cable Kits and Accessories section in page 6 AC 97 Audio To use the CPU s onboard audio it must first be enabled in the BIOS Two signaling levels are supported so a line out connection can be used for powered speakers as well as a headphone connection for non powered speakers Once enabled two audio output modes can be selected e Line Out This signaling level should be used for powered speakers e Headphone This signaling level should be used for non powered speakers Ethernet 10 100Base T and TX To use the onboard 10 100 Ethernet controller Ethernet must first be enabled in the BI
54. des are listed in Table 23 which also includes a reference to the corresponding connector pinout For the configurations that have RS 422 or RS 485 on COM B a jumper must be installed Table22 Dual Serial Port Connections Connector COMA COMB CN7 COM 1 COM 3 CN8 COM 2 COM 4 Table 23 Dual Serial Port Modes COMA Pinout JP12 JP14 Reference RS 232 RS 232 Table 24 Not Installed RS 422 RS 232 Table 25 Not Installed RS 422 RS 422 Table 26 CN7 JP12 CN8 JP14 RS 485 RS 232 Table 25 Not Installed RS 485 RS 485 Table 26 CN7 JP12 CN8 JP14 Table24 COMA RS 232 and COM B RS 232 Pin Signal Function In Out DB 9 1 DCD1 COM Data Carrier Detect in 1 2 RXD2 COM B Receive Data in 6 3 RXD1 COM A Receive Data in 2 4 RTS1 COM A Request To Send out 7 5 TXD1 COM A Transmit Data out 3 6 CTS1 COM A Clear To Send in 8 7 TXD2 COM B Transmit Data out 4 8 COM Ring Indicate in 9 9 10 GND Signal Ground 5 40 CMX158886 cpuModule BDM 610000049 Rev G Table25 COM A RS 422 485 and COM B RS 232 BDM 610000049 Rev G Pin Signal Function In Out DB 9 1 DCD1 COM A Data Carrier Detect in 1 2 RXD2 COM B Receive Data in 6 3 RXD1 COM A Receive Data in 2 4 TXD1 COM A Transmit Data out 7 5 TXD1 COM A Transmit Data out 3 6 RXD1 COM A Receive Data in 8 7 TXD2 COM B Transmit Data out 4
55. ding Enhanced Intel SpeedStep Technology PX only Advanced Thermal Management AutoFan Control only runs fan when needed SMBus Temperature Monitor for CPU and board temperature MiniFan Heatsink with Auto Fan control Passive Structural Heatsink amp Heatpipes in IDAN and HiDAN System Configurations Advanced Programmable Interrupt Controller APIC Highresolution 100 MHz APIC timer 24interrupt channels with APIC enabled 15 in legacy PIC mode Advanced Configuration and Power Interface ACPI ACPI 1 0 Compliant Supported power down modes S1 Power On Suspend 53 Suspend to RAM S4 Hibernate and S5 Soft Off Clock Throttling and Clock Stop for CO to Support Wake events include e aDIO Interrupt e Wake on LAN e Real Time Clock COM port Ring e Power Switch etc Network Boot supported by Intel PXE BDM 610000049 Rev Chapter 1 Introduction 7 e Three 3 counter timers Intel 8254 compatible e Seven 7 DMA channels Intel 8237 compatible e 2 compliant Real Time Clock external battery required e Nonvolatile storage of CMOS settings without battery e Watchdog timer e Complete PC compatible Single Board Computer e 97 Audio Support Selectable Headphone or Line level output Line level input Microphone input e Fast Ethernet Ethernet Controller e Intel 82562 Fast Ethernet PCI Controller e Integrated 3KByte Transmit and 3Kbyte Receive FIFOs Physical
56. e modifications to the BIOS setup When the following features are modified the CPU s power consumption will decreases e CPU Speed Setting the processor to its minimum speed in the BIOS will reduce power consumption e Memory Speed Changing the DDR DRAM clock frequency will reduce power consumption however memory performance will also be reduced e Ethernet Can be disabled in the BIOS e Serial Ports Can be disabled in the BIOS e LVDS Flat Panel If an LVDS panel is not connected to the cpuModule while using a VGA monitor setting the BIOS to use only a CRT VGA monitor will reduce power consumption e Mode Set the fan to auto mode so it is used only when the processor reaches high temperatures This option will only effect the fan if it is connected to the switched fan power connector CN15 e Multi Color LED Can be disabled in the BIOS BDM 610000049 Rev G Chapter 4 Using the cpuModule 75 Multi Color LED The CMX158886 has a Multi Color LED located beside the EIDE connector CN10 which can be enabled or disabled in the BIOS setup screen The color of the LED indicates the status of the board as shown in Table 54 Table 54 LED Colors Color Description Green Normal Operation Blue On Board IDE Activity Red cpuModule is in reset Yellow Red Green cpuModule is in Standby White R G B cpuModule is approaching thermal limit Cyan Blue Green Ethernet Link at 10 Mbps Magenta Blue Red Ethernet Link at 100 Mb
57. e liable to the purchaser or any user for any damages including any incidental or consequential damages expenses lost profits lost savings or other damages arising out of the use or inability to use the product Some states do not allow the exclusion or limitation of incidental or consequential damages for consumer products and some states do not allow limitations on how long an implied warranty lasts so the above limitations or exclusions may not apply to you This warranty gives you specific legal rights and you may also have other rights which vary from state to state RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA Website www rtd com BDM 610000049 Rev G Appendix E Limited Warranty 109 110 CMX158886 cpuModule BDM 610000049 Rev G
58. ecting the cpuModule 43 multiPort Configured as a Floppy Drive Controller The multiPort CN6 can be configured to be a floppy drive controller This can be configured in the BIOS Setup under Integrated Peripherals For more information on configuring the multiPort in the BIOS Setup refer to page 66 Table 29 shows the pin assignments to connect a floppy drive to the multiPort Table29 multiPort Connector Floppy Pinout CN6 CN6 Pin Function DB 25 Floppy Drive Pin 1 DSO 1 14 2 DRO 14 2 3 INDEX 2 8 4 HDSEL 15 32 5 TRKO 3 26 6 DIR 16 18 7 WRTPRT 4 28 8 STEP 17 20 9 RDATA 5 30 10 GND 18 11 DSKCHG 6 34 12 GND 19 odd pins 13 7 14 GND 20 odd pins 15 MTRO 8 10 16 GND 21 odd pins 17 9 18 GND 22 odd pins 19 DS1 10 12 20 GND 23 odd pins 21 MTR1 11 16 22 GND 24 odd pins 23 WDATA 12 22 24 GND 25 odd pins 25 WGATE 13 24 26 5 1 Signals marked with are active low 2 These signals must be pulled to 5V with separate 470 Ohm resistors 44 CMX158886 cpuModule BDM 610000049 Rev G USB 2 0 Connector CN17 Two USB 2 0 compliant connectors are available on connector CN17 Table 30 provides the pinout of the USB connector Note For proper operation at USB 2 0 speeds be sure to use a cable that is rated for USB 2 0 such as the cable kit supplied by RTD BDM 610000049 Rev G Table 30
59. ed in the appropriate interrupt mode The Wake Enable bit is then set in the Wake Control Register at 0x454 The CPU can then be placed in a standby mode and the aDIO interrupt will wake the system During system standby a 32kHz clock is used for the aDIO instead of an 8 33 MHz clock Therefore transitions must be at least 30 us in order to trigger a wake event If the aDIO is to be used for a wake event only and not an interrupt the Int Mask bit can be set in the Wake Control Register This will block the interrupt but still allow a wake event to occur The various settings for Wake Enable and Int Mask are shown in Table 51 below Table51 Interrupt and Wake Event Generation WakeEnable Int Mask Function 0 0 Interrupt Only 0 1 No Interrupt or Wake event is generated 1 0 Interrupt and Wake Event 1 1 Wake Event Only BDM 610000049 Rev Chapter 4 Using the cpuModule 65 multiPort Parallel Port Control The parallel port may be operated in SPP output only EPP bidirectional and ECP extended capabilities modes The mode may be selected in the BIOS or by application software To configure the parallel port in the BIOS enter the BIOS and follow the steps below 1 Under the Advanced menu in the BIOS select the I O Device Configuration submenu 2 Setthe multiPort mode to Parallel Port 3 When a new Parallel Port Configuration appears select it and configure the parallel port base address parallel port mo
60. ed on connector CN8 The serial ports are normally configured as PC compatible full duplex RS 232 ports but you may use the BIOS Setup program to reconfigure these ports as half duplex RS 422 or full duplex RS 422 or RS 485 If you reconfigure the ports you must also select the I O address and corresponding interrupt using Setup Table 17 provides the available I O addresses and corresponding interrupts Table 17 Serial Port Settings 1 O Address hex IRQ 03F8 IRQ4 02F8 IRQ3 03E8 IRQ4 02E8 IRQ3 Serial Port UART The serial ports are implemented with a 16550 compatible UART Universal Asynchronous Receiver Transmitter This UART is capable of baud rates up to 115 2 kbaud in 16450 and 16550A compatible mode and includes a 16 byte FIFO Refer to any standard PC AT hardware reference for the register map of the UART For more information about programming UARTS refer to Appendix D RS 232 Serial Port Default The default serial port mode is full duplex RS 232 With this mode enabled the serial port connectors must be connected to RS 232 compatible devices Table 18 provides the serial port connector pinout and shows how to connect to an external DB 25 or DB 9 compatible serial connector Table 18 Serial Port in RS 232 Mode Pin Signal Function In Out DB 25 DB 9 1 DCD Data Carrier Detect in 8 1 2 DSR Data Set Ready in 6 6 3 RXD Receive Data in 3 2 4 RTS Request To Send out 4 y 5 TXD Transmit Data
61. elow 4 75 when hard drive or floppy drive starts add bypass caps insufficient cabling through power connector increase wire gauge to connector power through bus connectors temperature too high add fan processor heatsink or other cooling device s See Thermal Management on page 72 memory address conflict check for two hardware devices e g Ethernet SSD Arcnet PCMCIA trying to use the same memory address check for two software devices e g EMM386 PCMCIA drivers etc trying to use the same memory addresses check for hardware and software devices trying to use the same memory address check for an address range shadowed see Advanced Setup screen while in use by another hardware or software device I O address conflict check for another module trying to use I O addresses reserved for the cpuModule between 010h and 01Fh check for two modules e g dataModules PCMCIA cards Ethernet trying to use the same I O addresses 92 CMX158886 cpuModule BDM 610000049 Rev G Problem keyboard does not work Table64 Troubleshooting cont d Cause keyboard interface damaged by misconnection Solution e check if keyboard LEDs light wrong keyboard type verify keyboard is an AT type or switch to AT mode floppy drive light always on cable misconnected check for floppy drive cable connected backwards two hard drives will not work but one does both drives configured
62. er Grounding Techniques Before removing the CMX158886 from its static bag proper grounding techniques must be used to prevent electrostatic discharge ESD damage to the cpuModule Common grounding procedures include an anti static mat on a workbench which may connect to an anti static wrist strap also known as an ESD wrist strap on the wrist of the technician or engineer Connector Locations Figure 4 shows the connectors and the ATA IDE Disk Chip socket of the CMX158886 cpuModule Cont Fan Power SVGA CN14 Mngmt PCI Bus CN16 Audio Video CN11 CN18 a 888 00000000 1 00000000 00000000 LVDS Flat NISI 99 COM1 cal CN7 E Switched al Fan ne COM2 2 EE CNB o s multiPort USB 2 0 o CN6 CN17 o Ethernet CN20 EN Multi gt 000000000000000 Function Q 53299 5 000900 ATA IDE gu Auxiliary Power Battery ISA Bridge Link CN3 CN13 IDE CN10 CN4 Figure 4 CMX158886 Connector Locations Note Pin 1 of each connector is indicated by a white silk screened square on the top side of the board EN and a square solder pad on the bottom side of the board Pin 1 of the bus connectors match when stacking PC104 Plus or PCI 104 modules 24 CMX158886 cpuModule BDM 610000049 Rev G BDM 610000049 Rev G Table6 CMX158886 Basic Connectors Connector Function S
63. erging the new Dword Memory with ECC enabled requires additional system memory resources This will cause the integrated graphics engine to have less memory bandwidth for access to the graphics frame buffer Because of this the display may flicker at high resolutions when the graphics processor is fully utilized and ECC is enabled ECC memory is supported with internal graphics only aDIO with Wake on aDIO RTD5 exclusive multiPort allows the parallel port to be configured as an Advanced Digital I O aDIO ECP EPP parallel port or a floppy drive aDIO is 16 digital bits configured as 8 bit direction programmable and 8 bit port direction programmable I O giving you any combination of inputs and outputs Match event and strobe interrupt modes mean no more wasting valuable processor time polling digital inputs Interrupts are generated when the 8 bit direction programmable digital inputs match a pattern or on any value change event Bit masking BDM 610000049 Rev G Chapter 1 Introduction 3 allows selecting any subgroup of eight bits The strobe input latches data into the bit programmable port and generates an interrupt Any of the interrupt modes can be used to generate a wake event from any standby powerdown mode 4 CMX158886 cpuModule BDM 610000049 Rev G Ordering Information The CMX158886 cpuModule is available with a 1 4 GHz Pentium M processor or a 1 0 GHz Celeron M processor and 512 or 1024 MB of DDR SDRAM The cpuModule can a
64. for master set one drive for master and the other for slave operation consult drive documentation floppy does not work data error due to drive upside down orient drive properly upright or on side will not boot when video card is removed illegal calls to video controller look for software trying to access nonexistent video controller for video sound or beep commands abnormal video flat panel is enabled disable the flat panel in the BIOS can only use 640 x 480 resolution in Windows flat panel is enabled disable the flat panel in the BIOS video drivers not installed install the video drivers will not boot from PCMCIA hard drive booting from PCMCIA is not supported boot from SSD use autoexec bat to load PCMCIA drivers run application from PCMCIA card COM port will not work in RS 422 or RS 485 modes COM port will not transmit in RS 422 or RS 485 mode not configured for RS 422 485 not enabling transmitters correctly configure serial port in Setup program control RTS bit of Modem Control Register to enable transmitters see Serial Port descriptions date and time not saved when power is off no backup battery connect a backup battery to the multi function connector screen flickers at high resolutions when processor is fully utilized memory with ECC enabled requires additional system memory resources the integrated graphics engine has less mem
65. formation on the serial interrupt signal and the DMA request grand pair refer to Bridge Link CN4 in Chapter 3 Connecting the cpuModule BDM 610000049 Rev G Chapter 4 Using the cpuModule 61 multiPort Advanced Digital I O Ports aDIO Ensure that the BIOS setup has the multiPort set to aDIO mode This board supports 16 bits of TTL CMOS compatible digital I O TTL signaling These I O lines are grouped into two ports Port 0 and Port 1 Port 0 is bit programmable Port 1 is byte programmable Port 0 supports RTD s Advanced Digital Interrupt modes The three modes are strobe match and event Strobe mode generates an interrupt and latches Port 0 when the strobe input transitions from low to high Match mode generates an interrupt when an 8 bit pattern is received in parallel that matches the match mask register Event mode generates an interrupt when a change occurs on any bit In any mode masking can be used to monitor selected lines When the CPU boots all digital lines are programmed as inputs meaning that the digital I O line s initial state is undetermined If the digital I O lines must power up to a known state an external 10 kQ resistor must be added to pull the line high or low The 8 bit control read write registers for the digital I O lines are located from I O address 450h to 454h These registers are written to zero upon power up From 450h to 454h the name of these registers are Port 0 data Port 1 data Multi Functi
66. gabyte is allocated in the system Table41 First Megabyte Memory Map Address hex Description C0000 FFFFFh ROM 256 KB BIOS in Flash EPROM shadowed into DRAM during runtime C0000 EFFFFh Run time user memory space Usually memory between C0000h and CFFFFh is used for the BIOS of add on VGA video cards A0000 BFFFFh Normally used for video RAM as follows EGA VGA 0A0000 0AFFFFh Monochrome 0B0000 0B7FFFh CGA 0B8000 OBFFFFh 00502 9FFFFh DOS reserved memory area 00400 00501h BIOS data area 00000 003FFh Interrupt vector area Memory beyond the first megabyte can be accessed in real mode by using EMS or a similar memory manager See your OS or programming language references for information on memory managers BDM 610000049 Rev G Chapter 4 Using the cpuModule 59 I O Address As with all standard PC 104 boards the I O total I O space is 64k in size However because early processors only addressed 0 address lines SAO SA9 the first 1k is used for legacy I O devices ISA add on modules you install must therefore use I O addresses in the range of 0 1023 decimal or 000 3FF hex The upper I O addresses are used for PCI I O devices and are automatically assigned by the BIOS or operating system at boot time Note lf you add any PC 104 modules or other peripherals to the system you must ensure they do not use EN reserved addresses listed below or malfunctions will occur The exception to this is if the re
67. h contains e Multi function utility harness keyboard socket battery reset speaker e Two serial port cables DIL 10 to DSUB 9 e Parallel port cable DIL 26 to DSUB 25 e TwoIDE cables e monitor cable 011 10 to high density 15 pin DSUB e Power cable 011 12 to wire leads e USB cables 5 pin SIL to USB A e Audio Cable DIL 10 to three Mini Jacks Ethernet cable 011 10 to RJ 45 A floppy drive cable kit P N XK CM49 is also available for connecting to the multiPort This cable kit comes with 3 5 HDD Floppy Drive with a multiPort interface board e floppy cables For additional accessories refer to the RTD website 6 CMX158886 cpuModule BDM 610000049 Rev G Board Features 1 4 GHz Intel Pentium M with thermal throttling 400 MHz source synchronous Front Side Bus Math coprocessor e Supports MMX and SSE2 instructions Internal Cache e 11 32 of instruction and 32KB data L2 2 MB 1 0 GHz Intel Celeron M with thermal throttling 400 MHz source synchronous Front Side Bus Math coprocessor e Supports MMX and SSE2 instructions Internal Cache e 11 32 of instruction and 32KB data L2 512kB 512 or 1024 Mbytes BGA DDR SDRAM Upto 333 MHz Data Rate corrects single bit memory errors and detects 2 bit errors selected models Stackable 120 pin PCI bus 4 Bus master add on cards capable 33V or 5V PCI bus signaling Advanced power management features inclu
68. h mode set bits 4 3 of the DIO Control register to 11 Note Make sure bits 4 3 are set BEFORE writing the DIO Compare register If you do not set them first EN the contents of the DIO Compare register could be lost because the Event mode latches in Port 0 into the DIO Compare register 64 CMX158886 cpuModule BDM 610000049 Rev G CLOCK DIGITAL INPUT IRQ OUT Figure 6 aDIO Match Mode Strobe Mode Another interrupt mode supported by aDIO is Strobe mode This allows the strobe pin of the DIO connector to trigger an interrupt A low to high transition on the strobe pin will cause an interrupt request The request will remain high until the Clear Register is read from Additionally the Compare Register latched in the value at Port 0 when the Strobe pin made a low to high transition No further strobes will be available until a read of the Compare Register is made You must read the Compare Register and then clear interrupts so that the latched value in the compare register is not lost To enter Strobe mode set bits 4 3 of the DIO Control register to 01 Wake on aDIO The aDIO Strobe Match and Event interrupt can be used to generate a wake event This event can wake the CPU from any power down mode including Soft Off S5 Wake from aDIO will work as long at 5V Standby power is applied to the board To use the aDIO to wake the system Wake from aDIO must first be enabled in the BIOS setup utility Then the aDIO is configur
69. he BIOS is known as POST power on self test software and it is active from the time power is applied until an OS boots begins execution POST software performs a series of hardware tests sets up the machine as defined in Setup and begins the boot of the OS The second part of the BIOS is known as the CORE BIOS It is the normal interface between cpuModule hardware and the OS which is in control It is active from the time the OS boots until the cpuModule is turned off The CORE BIOS provides the system with a series of software interrupts to control various hardware devices Configuring the RTD Enhanced AMI BIOS The cpuModule Setup program allows you to customize the cpuModule s configuration Selections made in Setup are stored on the board and are read by the BIOS at power on Entering the BIOS Setup You can run Setup by rebooting the cpuModule and repeatedly pressing the Delete key When you are finished with Setup save your changes and exit The system will automatically reboot Field Selection To move between fields in Setup use the keys listed below Table39 Setup Keys Key Function 2 V Move between fields PgUp PgDn Selects next previous values in fields Enter Go to the submenu for the field Esc To previous menu then to exit menu 56 CMX158886 cpuModule BDM 610000049 Rev G Main Menu Setup Fields The following is a list of Main Menu Setup fields Table 40 Main Menu Setup Fields
70. he CMX158886 cpuModule 855 GME DDR SDRAM NorthBridge 333 MHz SVGA LVDS Flat Panel Intel Processor 2x USB 2 0 ICH 4 South Bridge EIDE AC97 Audio PCI Bus 32 bit 33 MHz 10 100 Ethernet RTD aDIO Watchdog LPC Bus RTD Enhanced BIOS Failsafe Boot ROM 2 x RS 232 422 485 Super Keyboard Mouse Parallel Port Floppy Drive Figure 2 CMX158886 cpuModule Simplified Block Diagram You can easily customize the cpuModule by stacking PCI 104 modules such as video controllers modems LAN controllers or analog and digital data acquisition modules Stacking modules onto the cpuModule avoids expensive installations of backplanes and card cages and preserves the module s compactness The cpuModule uses the RTD Enhanced AMI BIOS Drivers in the BIOS allow booting from floppy disk hard disk ATA IDE Disk Chip or boot block flash thus enabling the system to be used with traditional disk drives or nonmechanical drives Boot from USB devices and network are also supported The cpuModule and BIOS are also compatible with most real time operating systems for PC compatible computers although these may require creation of custom drivers to use the aDIO and watchdog timer BDM 610000049 Rev G Chapter 1 Introduction 11 Specifications Physical Characteristics e Dimensions 117mm L x 97mm W x 15mm 4 6 L x 3 8 W x 0 6 H e Weight Approximately 0 19 Kg 0 40 Ibs Power Consumption
71. he end of interrupt EOI command to the Intel 8259 Each bit in the IMR contains the mask status of an IRQ line bit 0 is for IRQO bit 1 is for IRQ1 and so on If a bit is set 1 then the corresponding IRQ is masked and will not generate an interrupt If a bit is clear 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR is programmed through port 21h EN Note When in APIC mode the PIC is programmed differently and IRQ routing behaves differently For more information refer to the APIC datasheets and specifications provided by Intel PCI Interrupts PCI devices can share interrupts The BIOS or operating system may assign multiple PCI devices to the same IRQ line Any interrupt service routine ISR written for PCI devices must be able to handle shared interrupts Refer to Interrupt Driven PC System Design ISBN 0 929392 50 7 for more information on PCI interrupts Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must clear the interrupt status flag and write an end of interrupt command to the Intel 8259 controller Finally
72. heat sinks and heat pipes for fanless operation RTD modules installed in IDAN frames are called building blocks IDAN building blocks maintain the simple but rugged stacking concept of PC 104 and PC 104 Plus Each RTD module is mounted in its own IDAN frame and all 1 connections are brought to the walls of each frame using standard PC connectors No connections are made from module to module internal to the system other than through the PC 104 and PC 104 Plus bus enabling quick interchangeability and system expansion without hours of rewiring and board redesign The CMX158886 cpuModule can also be purchased as part of a custom built RTD HiDAN or HiDANplus High Reliability Intelligent Data Acquisition Node This appendix provides the dimensions and pinouts of the CMX158886 installed in an IDAN frame Contact RTD for more information on high reliability IDAN HiDAN and HiDANplus PC PCI 104 systems IDAN Adhering to the PC 104 stacking concept IDAN allows you to build a customized system with any combination of RTD modules IDAN Heat Pipes Advanced heat pipe technology maximizes heat transfer to heat sink fins HiDANplus Integrating the modularity of IDAN with the ruggedization of HiDAN HiDANplus enables connectors on all system frames with signals running between frames through a dedicated stack through raceway BDM 610000049 Rev G Appendix C Dimensions and Pinout 95 IDAN Dimensions and Connectors
73. hip with cpuModules contact RTD Technical Support 2 Next apply power to the system and press the delete key repeatedly to enter the BIOS setup screen Once in the BIOS specify the following settings a Enable the cpuModule s secondary IDE channel b Specify the IDE mode of the ATA IDE Disk Chip For more information on the supported IDE modes refer to Configuring the ATA IDE Disk Chip Socket section of this manual on page 68 BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 35 C Savethe settings in the BIOS setup 3 Remove power from the system WARNING The preceding steps should be performed before installing the Disk Chip in the ATA IDE Disk Chip Socket These steps ensure that the system is properly configured for the correct device and supply voltage so neither the Disk Chip or cpuModule are damaged 4 Insert the Disk Chip in the ATA IDE Disk Chip Socket U16 aligning pin 1 with the square solder pad on the board 5 Apply power to the system 6 Re enter the BIOS and set the boot order of the system accordingly ATA IDE Disk Chip Pin 1 indicated by arrow ATA IDE Disk Chip Socket U16 Pin 1 indicated by arrow 1i 4GB Apacer jn 1111 Figure5 158886 before and after ATA IDE Disk Chip Installation 36 CMX158886 cpuModule BDM 610000049 Rev G Serial Port 1 CN7 and Serial Port 2 CN8 Serial Port 1 COM1 is implemented on connector CN7 and Serial Port 2 is implement
74. ically update itself for Daylight Savings Time It is recommended to leave this bit low and let the operating system manage time zones and DST 0Ch 12 RTC Status Register C Read Only e Bit 7 IRQ Flag Indicates that the Real Time Clock IRQ is asserted Goes high whenever one of the enabled interrupt conditions in Register B occurs e Periodic Flag e Bit 5 Alarm Flag e Bit 4 Update Ended Flag e 3 0 Reserved Reading this register will also clear any of set flag IRQ Periodic Alarm Update Ended Note that even if the interrupt source is not enabled in Register B the flags in Register C bits 4 5 and 6 may still be set ODh 13 RTC Status Register D e Bit 7 Valid Time Date always reads 1 e Bit6 Reserved e Bits 5 0 RTC Alarm Day of the Month Altering the contents of any unlisted RTC register may interfere with the operation of your cpuModule The specific uses of the unlisted RTC registers will depend on the BIOS version loaded on the cpuModule Contact RTD s technical support for more information Note RIC registers that are not listed above are used by the BIOS and should be considered Reserved 70 CMX158886 cpuModule BDM 610000049 Rev G Watchdog Timer Control The cpuModule includes a watchdog timer which provides protection against programs hanging or getting stuck in an execution loop where they cannot respond correctly When enabled the watchdog timer must be periodically reset
75. imited Warranty BDM 610000049 Rev G Chapter 1 Introduction 1 CMX158886 cpuModules RTD s CMX158886 cpuModule represents the latest in high performance embedded computing solutions It includes 400 MHz source synchronous Front Side Bus FSB on die 2 MB PX or 512kB CX L2 cache and data pre fetch logic It uses a 333MHz DDR SDRAM controller that can support up to 2 7 G Bytes per second of memory bandwidth All memory chips are soldered directly onto the board The Pentium M PX processor features Enhanced Intel SpeedStep technology which enables real time dynamic switching between multiple voltage and frequency points This results in optimal performance without compromising low power The video interface is provided by an Analog SVGA output and an LVDS flat panel output The two outputs are independent and can display separate images and display timings Maximum resolution is 2048 x 1536 High speed peripheral connections include USB 2 0 with up to 480 Mb sec data throughput An ATA 100 66 33 IDE controller provides a fast connection to the hard drive Network connectivity is provided by an integrated 10 100 Mbps Ethernet controller Other features include two RS 232 422 485 COM ports Parallel Port and AC97 audio RTD has gone the extra mile to include additional advanced features for maximum flexibility These include an ATA IDE Disk Chip socket that allows a true IDE drive to be attached to the board either socketed or soldered
76. ing 13 available interrupt request lines What happens when an interrupt occurs An IRQx pin on the PC 104 bus makes a low to high transition while the corresponding interrupt mask bit is unmasked and the PIC determines that the IRQ has priority that is the PIC interrupts the processor The current code segment CS instruction pointer IP and flags are pushed onto the stack The CPU then reads the 8 bit vector number from the PIC and a new CS and IP are loaded from a vector indicated by the vector number from the interrupt vector table that exists in the lowest 1024 bytes of memory The processor then begins executing instructions located at CS IP When the interrupt service routine is completed the CS IP and flags that were pushed onto the stack are popped from the stack into their appropriate registers and execution resumes from the point where it was interrupted How long does it take to respond to an interrupt A DOS system can respond to an interrupt between 6 and 15 us A Windows system can take a much longer time when a service routine has been installed by a device driver implemented as a DLL from 250 to 1500 us or longer The time the CPU spends in the interrupt depends on the efficiency of the code in the ISR These numbers are general guidelines and will fluctuate depending on operating system and version Minimum time between two IRQ requests is 125 ns per ISA specification Interrupt Request Lines To allow different pe
77. interrupts needed by the cpuModule or malfunctions will occur The CMX158886 cpuModule supports the standard PC interrupts listed in Table 43 Interrupts not in use by hardware on the cpuModule itself are listed as available Similarly if the operating system is using APIC more IRGs will be available Table 43 Hardware Interrupts Used on the CMX158886 cpuModule Interrupt Normal Use 0 Timer 0 1 Keyboard 2 Cascade of IRQ 8 15 3 COM2 4 COMI 5 Available 6 Floppy 7 Printer 8 Real Time Clock 9 Available routed to IRQ 2 10 Available 11 Available 12 Bus Mouse 141 Primary IDE hard disk 15 ATA IDE Disk Chip socket 1 IRQs 14 and 15 may be available if the IDE controller is configured in Native Mode refer to IDE Controller Configuration page 67 Note The cpuModule has onboard PCI devices that will claim IRQ lines In some instances a PCI device EN Will claim an IRQ line that is required by a legacy device To reserve an IRQ for a legacy device refer to the PnP PCI Configuration Setup fields in the BIOS Note A devices hardware interrupt will be available for use if the given device is not present in the system and the device is disabled in Setup For external devices that require Legacy ISA interrupts a serial interrupt signal is available which permits access to the CPU hardware interrupts One pair of Legacy ISA DMA request grant signals are also available For more in
78. ion of the control mechanism and software interface to the processor and reduced hardware overhead has reduced processor core unavailability time to 10 us from the previous generation unavailability of 250 us Thermal Monitor The Intel Thermal Monitor is a feature on the CMX158886 that automatically initiates a SpeedStep transition or throttles the CPU when the CPU exceeds its thermal limit The maximum temperature of the processor is defined as the temperature that the Thermal Monitor is activated The thermal limit and duty cycle of the Thermal Monitor cannot be modified Error Correction Codes Selected Models Only The Graphics and Memory Controller Hub GMCH may be configured in the BIOS setup to operate in an Error Correction Code ECC data integrity mode ECC mode allows multiple bit error detection and single bit error correction The GMCH generate an 8 bit code word for each 64 bit Qword of memory and performs a full Qword write at a time so that an 8 bit code is sent with each write Since the code word covers a full Qword writes of less than a Qword require a read merge write operation Consider a Dword write to memory In this case when in ECC mode GMCH will read the Qword where the addressed Dword will be written merge in the new Dword generate a code covering the new Qword and finally write the entire Qword and code back to memory Any correctable single bit errors detected during the initial Qword read are corrected before m
79. ith Fail Safe Boot ROM EN Note Boards are shipped with Fail Safe Boot ROM enabled When Fail Safe Boot ROM is enabled the system will boot to it exclusively The Fail Safe Boot ROM is a minimal build of ROM DOS located inside a surface mounted Boot Block Flash chip Boot Block Flash is a write protected flash device that contains the BIOS and extra room where the Fail Safe Boot ROM is stored Additionally Fail Safe Boot ROM is an emergency interface accessible by an external computer The ROM DISK contains utilities for remote access to the system s disk drives Due to the size of the flash chip Fail Safe Boot ROM contains an abbreviated selection of the ROM DOS utilities however the complete ROM DOS is contained on a CD shipped with the cpuModule The purpose of the Fail Safe Boot ROM is to make the cpuModule bootable upon receipt The Fail Safe Boot ROM can be used as an indicator of the module s functionality when booting problems arise with another operating system This test can be accomplished by enabling the Fail Safe Boot ROM in the Boot section of the BIOS Setup Utility Enabling this option forces the cpuModule to boot to Fail Safe Boot ROM To boot to the Fail Safe Boot ROM install jumper JP5 and apply power to the system Note lf power is applied to the system while JP5 is installed the multi color LED will turn red 58 CMX158886 cpuModule BDM 610000049 Rev G Memory Map Table 41 shows how memory in the first me
80. ize CN3 Auxiliary Power 12 pin CN4 Bridge Link 4 pin CNS Utility Port 10 pin CN6 multiPort 26 pin CN7 Serial Port 1 COM1 10 pin CN8 Serial Port 2 COM2 10 pin CN10 EIDE Connector 44 pin CN11 Audio Connector 10 pin CN12 External Power Management 3 pin CN13 RTC Battery Input optional 2 CN14 Fan Power 45V 2 pin CN15 Fan Power switched 2 pin CN16 PC 104 Plus PCI Bus 120 pin CN17 USB 2 0 10 pin CN18 Video SVGA 10 pin CN19 Flat Panel Video LVDS 30 pin CN20 Ethernet 10 pin U16 ATA IDE Disk Chip Socket 32 pin Chapter 3 Connecting the cpuModule 25 Auxiliary Power CN3 The Auxiliary Power connector CN3 can be used to supply power to devices that are attached to the cpuModule These devices include hard drive front end boards for data acquisition systems and other devices Power can also be conveyed to the module through the Auxiliary Power connector CN3 The cpuModule only requires 5 VDC and ground for operation however other modules in the system may require 3 3V 12 VDC 12 VDC and 5 Voc In these instances the corresponding pins on the Auxiliary Power Connector CN3 may be used to supply these voltages Note Although it is possible to power the cpuModule through the Auxiliary Power connector the preferred method is to power it through the bus connector from a power supply in the stack The cpuModule can have large current transients during operation which make powering it through wires
81. ld not be selected unless the user knows the cable type and the modes supported by the connected EIDE device WARNING When this cable detection method is enabled the highest transfer speed supported by the BDM 610000049 Rev Chapter 4 Using the cpuModule 67 Legacy Mode and Native Mode IDE The onboard EIDE controller may be configured as a either a Legacy or Native Mode IDE controller in the BIOS Setup However the operating system must support the selected mode for the device to operate correctly The default configuration for the controller is Legacy Mode as this is supported by most operating systems Legacy Mode Legacy mode is the default configuration of the onboard EIDE controller When in this mode the controller will be fixed to use two interrupts IRQs 14 and 15 Similarly the I O address of the controller will be fixed in the system When in Legacy Mode only a primary and secondary channel may be used in the system Native Mode Native Mode allows more flexibility as the system resources used by the IDE controller may be modified When in Native Mode the IDE controller only requires a single IRQ Unlike Legacy Mode this IRQ may be changed by the user or the operating system for better distribution of the system IRQs When IRQs in the system are more evenly distributed interrupt latency is minimized The base address of the controller may also be modified Configuring the ATA IDE Disk Chip Socket The cpuModule was
82. le IDAN Pin Signal Function Mode 1 DCD Data Carrier Detect Input 2 RXD Receive Data Input 3 TXD Transmit Data Output 4 DTR Data Terminal Ready Output 5 GND Ground 6 DSR Data Set Ready Input 7 RTS Request To Send Output 8 CTS Clear To Send Input 9 RI Ring Indicator Input Table68 COM1 COM2 RS 422 485 9 Pin D Connector male 98 CMX158886 cpuModule IDAN Pin Signal Function Mode 1 Reserved 2 RXD Receive Data Input 3 TXD Transmit Data Output 4 Reserved 5 GND Ground 6 Reserved 7 TXD Transmit Data Output 8 RXD Receive Data Input 9 Reserved BDM 610000049 Rev G Table 69 multiPort 25 Pin D Connector female IDAN Pin Port Parallel Port Floppy Port CPU Pin 1 strobe 0 STB 1 2 P1 0 PDO INDEX 3 3 P1 1 PD1 TRKO 5 4 P1 2 PD2 7 5 1 3 9 6 1 4 PD4 DSKCHG 11 7 P1 5 PD5 13 8 P1 6 PD6 15 9 P1 7 PD7 17 10 P0 0 ACK DS1 19 11 P0 1 BSY MTR 21 12 P0 2 PE WDATA 23 13 P0 3 SLCT WGATE 25 14 P0 4 AFD DRO 2 15 P0 5 ERR HDSEL 4 16 P0 6 INIT DIR 6 17 P0 7 SLIN STEP 8 18 strobe 1 GND GND 10 19 GND GND GND 12 20 GND GND GND 14 21 GND GND GND 16 22 GND GND GND 18 23 GND GND GND 20 24 GND GND GND 22 25 GND GND GND 24 BDM 610000049 Rev G Appendix C IDAN Dimensions and Pinout 99 100 CMX
83. lso be purchased as part of an Intelligent Data Acquisition Node IDAN building block which consists of the cpuModule and a milled aluminum IDAN frame The IDAN building block can be used in just about any combination with other IDAN building blocks to create asimple but rugged PC 104 stack Refer to Appendix C IDAN Dimensions and Pinout for more information The CMX158886 cpuModule can also be purchased as part of a custom built RTD HiDAN or HiDANplus High Reliability Intelligent Data Acquisition Node Contact RTD for more information on its high reliability PC PCI 104 systems CMX158886 Model Options The basic cpuModule model options are shown below Refer to the RTD website www rtd com for more detailed ordering information Table1 CMX158886 cpuModule Model Options Part Number Description CMX158886PX1400HR 512 1 4 GHz Pentium M 512MB DDR SDRAM cpuModule CMX158886PX1400HR E512 1 4 GHz Pentium M 512MB DDR SDRAM cpuModule with ECC CMX158886PX1400HR 1024 1 4 GHz Pentium M 1024MB DDR SDRAM cpuModule CMX158886CX1000HR 512 1 0 GHz Celeron M 512MB DDR SDRAM cpuModule CMX158886CX1000HR E512 1 0 GHz Celeron M 512MB DDR SDRAM cpuModule with ECC CMX158886CX1000HR 1024 1 0 GHz Celeron M 1024MB DDR SDRAM cpuModule BDM 610000049 Rev G Chapter 1 Introduction 5 Cable Kits and Accessories For maximum flexibility RTD does not provide cables with the cpuModule You may wish to purchase the CMX158886 cpuModule cable kit P N XK CM65 whic
84. me 107 viii CMX158886 cpuModule BDM 610000049 Rev G PC 104 and PC 104 Plus Specifications AppendixE Limited Warranty BDM 610000049 Rev G X CMX158886 cpuModule BDM 610000049 Rev G Chapter 1 Introduction This manual provides comprehensive hardware and software information for users developing with the CMX158886 PC 104 Plus cpuModule Note Read the specifications beginning on page 12 prior to designing with the cpuModule A This manual is organized as follows Chapter 1 Introduction introduces main features and specifications Chapter 2 Getting Started provides abbreviated instructions to get started quickly Chapter 3 Connecting the cpuModule provides information on connecting the cpuModule to peripherals Chapter 4 Using the cpuModule provides information to develop applications for the cpuModule including general cpuModule information detailed information on storing both applications and system functions and using utility programs AppendixA Hardware Reference lists jumper locations and settings physical dimensions and processor thermal management Appendix B Troubleshooting offers advice on debugging problems with your system AppendixC IDAN Dimensions and Pinout provides connector pinouts for the cpuModule installed in an RTD Intelligent Data Acquisition Node IDAN frame AppendixD Additional Information lists sources and websites to support the cpuModule installation and configuration Appendix E L
85. mes 2 Enhanced Intel SpeedStep PX HH e Hmm emen 3 Thermal MONIO cic esee Ra dee NUS 3 Error Correction Codes Selected Models Only e emnes 3 aDIO with 0 ene hh me hh he hh me he mene here 3 Ordering Information cece cece cence HH Hee he eene 5 CMX158886 Model Options e eene do 5 Cable Kits and Accessories ccc RET RES 6 Bo rd Features ORI EE REESE 7 NO Ses cere cetacean ME 8 BlOS EUM 9 aie EE 11 E TEESE E EEEE E E E 12 Physical tasses ben re re rn esee tee RU RE RERO tbi deb boi 12 x gestisce c EUM 12 Operating Conditions 222 ode e E RR 12 Electrical Characteristics ooo E RE RC DUXI NENNEN CR 12 Contact Information cero osu soe rele pris consc ex ue ba S e EN eK RE 15 Chapter 2 Getting Started Connector Locations eue roh P ERR e PE EU eR PX abbey 18 Connecting the Utility Cable ccc cece cee esee 20 Connecting a Keyboard ioo ied PI Et UD ERRARE 20 Connecting to the PC 104 Plus PCI Bus mese 20 Slot Selection Swit
86. modules make sure an XT bus card will not be placed between two AT bus cards or it will interrupt the AT bus signals 7 Hold the cpuModule by its edges and orient it so the bus connector pins line up with the matching connector on the stack 8 Gently and evenly press the cpuModule onto the PC 104 Plus or PCI 104 stack There are three additional considerations to make when using the PCI bus e Slot selection switches on add in boards CMX158886 cpuModule BDM 610000049 Rev G e PCI bus expansion card power e PCI bus signaling levels Slot Selection Switches Unlike PC 104 cards PC 104 Plus and PCI 104 expansion cards have a slot selection switch or jumpers In total there are 4 PCI cards that can be stacked onto the cpuModule with switch positions 0 through 3 The distance from the CPU determines these switch settings The card closest to the CPU is said to be in slot 0 the next closest slot 1 and so on to the final card as slot 3 Note This requirement means that all PC 104 Plus and PCI 104 cards must be stacked either on the top or the bottom of the CPU not on both sides The slot setting method may vary from manufacturer to manufacturer but the concept is the same The CPU is designed to provide the correct delay to the clock signals to compensate for the bus length The correct switch setting ensures the proper clock delay setting interrupt assignment and bus grant request channel assignment Refer to the expansion b
87. n dynamically This feature can be enabled or disabled in the BIOS When enabled the feature can be set to several different modes which are described below e Maximum Speed The processor speed is set to its maximum operating frequency e Minimum Speed The processor speed is set to its minimum operating frequency e Automatic When set to automatic mode the processor speed is controlled by the operating system Advanced Configuration and Power Interface ACPI The cpuModule supports several different ACPI low power modes including the 1 53 54 and S5 sleeping states The BIOS setup utility provides an option to select between S1 and S3 as the Standby state Sleep modes S4 and S5 are setup by the operating system The cpuModule s ACPI suspend modes are described below e 51 Power on Suspend The S1 low power state consumes the most power of all supported ACPI sleep modes In this mode the CPU stops executing instructions but power to the CPU and RAM is maintained 53 Suspend to RAM Everything in the system is powered off except for the system memory When the system wakes from this mode operating systems allow applications to resume where they left off as the state of the application is preserved in memory e S4 Hibernate When the system enters this state the operating system will save the current state of applications and relevant data to disk thus allowing the system RAM to be powered down e 55 Soft Off The s
88. nd VIO 5 V 5 V supply connected to the PC 104 bus and Auxiliary Power Connector CN3 5 V supplies This is the only power supply that is required for board operation 12 V 12 V supply connected to the PC 104 bus and Auxiliary Power Connector CN3 12 V supplies 12 V 12 V supply connected to the PC 104 bus and Auxiliary Power Connector CN3 12 V supplies 3 3 V The 433 V pins on the PC 104 Plus PCI connector are connected to the Auxiliary Power Connector CN3 by default To supply 3 3V via the onboard 3 3V power supply contact RTD Technical Support VIO This signal is typically the power to the bus drivers on a PCI bus card or used by the clamp diodes on a PCI bus card This is always driven by the cpuModule By default the signaling level is set to 3 3 V For information on configuring VIO for 5 V contact RTD Technical Support ATX Power Management Signals optional If an ATX power supply is connected to the system the following signals listed below may be used to wake the system from low power modes For more information on these signals refer to the Power Management section on page 73 5V_STDBY Some low power modes require that 5 V standby power is applied to the cpuModule during the wake event This signal is an input to the CPU PME Power Management Event input PSON This is an active low open drain output used to turn the power supply on when the system is exiting a low
89. nnector CN5 on page 28 to connect devices to the utility port connector Connecting a Keyboard You may plug a PC AT compatible keyboard directly into the PS 2 connector of the utility harness in the cable kit Note Many keyboards are switchable between PC XT and AT operating modes with the mode usually EN selected by a switch on the back or bottom of the keyboard For correct operation with this cpuModule you must select AT mode Connecting to the PC 104 Plus PCI Bus 20 Other PC 104 Plus or PCI 104 expansion boards may be connected to the cpuModule s PC 104 Plus PCI bus connector To connect expansion modules to the PC 104 Plus bus follow the procedure below to ensure that stacking of the modules does not damage connectors or electronics may damage it If the module does not readily press into place remove it check for bent pins or WARNING Do not force the module onto the stack Wiggling the module or applying too much pressure out of place keying pins and try again 1 Turn off power to the PC 104 Plus or PCI 104 system or stack Select and install stand offs to properly position the cpuModule on the stack Touch a grounded metal part of the rack to discharge any buildup of static electricity Remove the cpuModule from its anti static bag Check that keying pins in the bus connector are properly positioned NW oe M Check the stacking order if a PCI to ISA bridge card is used to connect any PC 104
90. o select the parallel port s address and associated interrupt and choose between its operational modes SPP ECP EPP 1 7 and EPP 1 9 The pinout of the connector enables a ribbon cable to be connected directly to a DB 25 connector thus providing a standard PC compatible port EN Note For correct operation keep the length of the cable connecting the cpuModule and parallel device less than 3 meters 10 feet Table 28 lists the parallel port signals and explains how to connect it to a DB 25 connector to obtain a PC compatible port Table 28 Connector CNG as a Parallel Port CN6 Pin Signal Function In Out DB 25 1 STB Strobe Data out 1 2 AFD Autofeed out 14 3 PDO Printer Data 0 LSB out 2 4 ERR Printer Error in 15 5 PD1 Parallel Data 1 out 3 6 INIT Initialize Printer out 16 7 PD2 Printer Data 2 out 4 8 SLIN Select Printer out 17 9 PD3 Printer Data 3 out 5 10 GND Signal Ground 18 11 PD4 Printer Data 4 out 6 12 GND Signal Ground 19 13 PD5 Printer Data 5 out 7 14 GND Signal Ground 20 15 PD6 Printer Data 6 out 8 16 GND Signal Ground 21 17 PD7 Printer Data 7 MSB out 9 18 GND Signal Ground 22 19 ACK Acknowledge in 10 20 GND Signal Ground 23 21 BSY Busy in 11 22 GND Signal Ground 24 23 PE Paper End in 12 24 GND Signal Ground 25 25 SLCT Ready To Receive in 13 26 5V BDM 610000049 Rev G Chapter 3 Conn
91. oard s manual for the proper settings Each expansion card must be in a different slot PCI Bus Expansion Card Power 5 Volt DC The 5 V power pins on the PC 104 Plus PCI bus are connected directly to the 5 V pins on the auxiliary power connector CN3 pins 2 and 8 3 3 Volt DC The 3 3V pins on the PCI bus can be configured to be supplied from the power connector CN3 or the onboard 3 3V power supply The factory default configuration connects the 3 3 V pins on the PCI bus to the auxiliary power connector CN3 This is to ensure that the cpuModule s onboard 3 3V supply will not supply power to the PC 104 Plus connector while a PC 104 Plus or PCI 104 power supply is already powering the 3 3V pins For more information on configuring the 3 3V pins on the PCI bus contact RTD Technical Support PCI Bus Signaling Levels The PCI bus can operate at 3 3 V or 5 V signaling levels The default PCI bus signaling level is 3 3 V For more information contact RTD Technical Support WARNING You will have to ensure that all your expansion cards can operate together at a single signaling level BDM 610000049 Rev G Chapter 2 Getting Started 21 Booting the CMX158886 cpuModule for the First Time You can now apply power to the cpuModule You will see e greeting message from the VGA BIOS if the VGA BIOS has a sign on message e ThecpuModule BIOS version information e message requesting you press Delete to enter the
92. on DIO Control and Wake Control register EN Note RTD provides drivers that support the aDIO interface on popular operating systems RTD recommends using these drivers instead of accessing the registers directly Digital I O Register Set Table44 Port 0 Data I O Address 450h D7 D6 D5 D4 D3 D2 D1 00 0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 Port 0 Data register is a read write bit direction programmable register A particular bit can be set to input or output A read of an input bit returns the value of port 0 A read of an output bit returns the last value written to Port 0 A write to an output bit sends that value to port 0 Table45 Port 1 Data I O Address 451h D7 D6 D5 D4 D3 D2 D1 DO P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 Port 1 Data register is a read write byte direction programmable register A read on this register when it is programmed to input will read the value at the aDIO connector A write on this register when it is programmed as output will write the value to the aDIO connector A read on this register when it is set to output will read the last value sent to the aDIO connector Table 46 Multi Function I O Address 452h D7 D6 D5 D4 D3 D2 D1 DO The multi function register is a read write register whose contents are set by the DIO Control register See the DIO Control register description for a description of this register 62 CMX158886 cpuModule BDM 610000049 Rev G Table47 DIO Control I O Address 453h Read
93. ory bandwidth for access to the graphics frame buffer disable ECC Troubleshooting a PC 104 Plus System If you have reviewed the preceding table and still cannot isolate the problem with your CMX158886 cpuModule please try the following troubleshooting steps Even if the resulting information does not help you find the problem it will be very helpful if you need to contact technical support 1 Simplify the system Remove items one at a time and see if one particular item seems to cause the problem 2 Swap components Try replacing items in the system one at a time with similar items BDM 610000049 Rev G Appendix B Troubleshooting 93 How to Obtain Technical Support If after following the above steps you still cannot resolve a problem with your CMX158886 cpuModule please gather the following information cpuModule model BIOS version and serial number List of all boards in system List of settings from cpuModule Setup program Printout of autoexec bat and config sys files if applicable Description of problem Circumstances under which problem occurs Then contact RTD Technical Support Phone 814 234 8087 Fax 814 234 5218 E mail techsupportGrtd com 94 CMX158886 cpuModule BDM 610000049 Rev G AppendixC IDAN Dimensions and Pinout cpuModules like all other RTD PC PCI 104 modules can be packaged in Intelligent Data Acquisition Node IDAN frames which are milled aluminum frames with integrated
94. out 2 3 6 CTS Clear To Send in 5 8 7 DTR Data Terminal Ready out 20 4 8 RI Ring Indicate in 22 9 9 10 GND Signal Ground 7 5 BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 37 Facing the serial port s connector pins the pinout is RS 422 or RS 485 Serial Port You may use Setup to configure the serial ports as RS 422 or RS 485 In this case you must connect the serial port to an RS 422 or RS 485 compatible device When using RS 422 or RS 485 mode you can use the serial ports in either half duplex two wire or full duplex four wire configurations For half duplex 2 wire operation you must connect RXD to TXD and connect RXD to TXD Note The cpuModule has a 120 Q termination resistor Termination is usually necessary on all RS 422 EN receivers and at the ends of the RS 485 bus Note lf required the termination resistor can be enabled by closing jumper JP1 for Serial Port 1 COM1 JP2 for Serial Port 2 COM2 JP11 for Serial Port 3 COM3 and JP13 for Serial Port 4 When using full duplex typically in RS 422 mode connect the ports as shown in Table 19 Table 19 Full Duplex Connections Port 1 Port 2 RXD TXD TXD RXD RXD TXD TXD RXD When using half duplex in RS 485 mode connect the ports as shown in Table 20 Table20 Half Duplex RS 485 Mode From To Port 1 TXD Port 1 RXD Port 1 TXD Port 1 RXD Port 1 TXD Port 2 RXD Port 1 RXD Port 2 TX
95. plication Notes RTD offers many application notes that provide assistance with the unique feature set of the CMX158886 cpuModule For the latest application notes refer to the RTD website Drivers and Example Programs To obtain the latest versions of drivers and example programs for this cpuModule refer to the RTD website Interrupt Programming For more information about interrupts and writing interrupt service routines refer to the following book Interrupt Driven PC System Design by Joseph McGivern ISBN 0929392507 Serial Port Programming For more information about programming serial port UARTS consult the following book Serial Communications Developer s Guide by Mark Nielson ISBN 0764545701 PC 104 and PC 104 Plus Specifications A copy of the latest PC 104 and PC 104 Plus specifications can be found on the webpage for the PC 104 Embedded Consortium http www pc104 org BDM 610000049 Rev G Appendix D Additional Information 107 108 CMX158886 cpuModule BDM 610000049 Rev G Limited Warranty RTD Embedded Technologies Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD Embedded Technologies Inc This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period RTD Embedded Technologies will repair or repl
96. power state Note Use of these signals will require board customization For more information contact the RTD BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 51 Bridge Link CN4 The Bridge Link connector allows devices that requires Legacy ISA interrupts to interface with the cpuModule When ISA devices are installed in the system via a PCI to ISA bridge card the Bridge Link connector provides Legacy ISA DMA request signals as well as a serial interrupt signal which permits access to all available system interrupts Multiple devices may utilize the serial interrupt signal SERIRQ which is decoded on the cpuModule Only one device may use the DMA request and grant signal pair Table34 Bridge Link CN4 Pin Signal Function 1 GND Ground 2 DMAREQ Legacy ISA DMA Request 3 SERIRQ Serial Interrupt Request 4 DMAGNT Legacy ISA DMA Grant Facing the connector pins the pinout is 52 CMX158886 cpuModule BDM 610000049 Rev G External Power Management CN 12 An external power management connector CN 12 is available for external devices to wake the system from low power states Some low power modes require that 5 V standby power is applied to the cpuModule during the wake event For more information on power management including a description of the board s supported wake options refer to the Power Management section on page 73 Table35 External Power Management CN12 Pin Signal Function 1
97. pply Signals 2 527 ed ER 74 Reducing Power Consumption He mese eme hse e ese eene 75 Multi Color LED e cL ERR ME EARS eae ae MS 76 Reset Status Register rele naan wien de por D eS Latah RE Polen cole es AE EN ates 77 DVMT Mod Selectie i ver e e rt evt esee p en E ERE Cep Ur S US xd yon tales 79 BDM 610000049 Rev vii User EEPROM C 80 Features and Settings That Can Affect Boot 81 QUICK BOOE eH Bm 81 Add On Cards With BIOS Extensions csse HH eme ese hne 81 Controler Em 81 Hard Drive 22 81 undc 81 Updates MET 81 Boot DeVice Ordeh sca Emm 81 System Recovery re eed ane tied Mew RE ET RE 82 Loading Default BIOS 8 IH me e mesh emen 82 Booting to the Fail Safe Boot ROM ee ens eese 82 Basic Interrupt Information for Programmers ssssssssssssssII ees 83 What happens when an interrupt occurs cece e e He ems mese 83 How long does it take to respond to an interrupt ccc cee teen Ime 83 Interrupt Request eso o ER Re ber repe eee FERNER ERAN bs oon DF URLEDERRER ERI 83 Intel 8259 Programmable Interrupt Controller sees e 84
98. ps Blink Ethernet Activity 1 If power is applied to the cpuModule while jumper JP5 is installed the LED will be red This does not indicate that the board is in reset 2 TheLED will remain White until the system is shut down The LED can also be controlled manually by writing to I O Port 456h as shown in Table 55 and Table 56 Table55 Multi Color LED 1 O Address 456h D7 D6 D5 D4 D3 D2 D1 00 Reserved Reserved Reserved Reserved Reserved Multi Color LED User User User EEPROM EEPROM EEPROM EN Note When writing to I O Port 456h only the lower three bits of the register should be modified Modifying the upper bits will effect the User EEPROM The following table lists the color displayed and the value written Table 56 Manual LED Colors 1 O Port 456h Value Color 0x00 Automatic see Table 54 0x08 Off will reduce system power consumption 0x09 Blue 0x0A Green 0x0B Cyan Green Blue 0x0C Red 0x0D Magenta Red Blue OxOE Yellow Red Green OxOF White Red Green Blue 76 CMX158886 cpuModule BDM 610000049 Rev G Reset Status Register The cpuModule has several different signals on board which can cause a system reset If a reset occurs the reset status register can be used to see which reset or resets have been asserted on the cpuModule The user has the ability to see which resets have been asserted Resets can also be cleared e Examine Resets Reading from I O port 0x457 will indicate if a rese
99. ration Bus Masters Only ee mes ems ne e es nee 50 gu MT 50 Interr pts codec SE dus 50 Power Supplies and rere RP E id rr Y RR exe v EE er ert UNE UE LORD UD MER ones 51 ATX Power Management Signals 51 Bridge Link CN4 52 External Power Management 12 e ee ee sme shes 53 Optional RTC Battery Input 1 eee cece ee III He meme 53 Fan Power 5 V 14 53 Fan Power Switched 15 eee ha ee 54 Chapter 4 Using the cpuModule The RTD Enhanced AMI ERO 56 Configuring the RTD Enhanced AMI BIOS 56 Entering the BIOS meterle rebat d de Toe DURS S D lee RR 56 sers UD 56 Main Menu setup Fields s dare 57 Power On Self Test POST Codes cece cee n ere n eee ee e mesh 57 Booting to Boot Block Flash with Fail Safe Boot ROM II e 58 vi CMX158886 cpuModule BDM 610000049 Rev G Memory Map ehe Oper RE PEBBEERUEEES EF EOM RERCEPERU FEE E NIRE RETE EBENE 59 I O Address eL D 60 Hardware Interrupts
100. responding pin of the aDIO connector an output Mask Register Writing a zero to a bit in this register will not mask off the corresponding bit in the DIO Compare register Writing a one to a bit in this register masks off the corresponding bit in the DIO Compare register When all bits are masked off the aDIOs comparator is disabled This condition means Event and Match mode will not generate an interrupt This register is used by Event and Match modes Compare Register A Read Write register used for Match Mode Bit values in this register that are not masked off are compared against the value on Port 0 A Match or Event causes bit 6 of DIO Control to be set and if the aDIO is in Advanced interrupt mode the Match or Event causes an interrupt BDM 610000049 Rev G Chapter 4 Using the cpuModule 63 Table 50 Wake Control I O Address 451h D7 D6 D5 D4 D3 D2 D1 DO Reserved Int Mask Wake Enable 1 Interruptismasked 1 Interrupt triggers a Wake Event O Interrupt is enabled O Interrupt does not trigger a wake event Port 1 Data register is a read write byte direction Interrupts In order to use an interrupt with aDIO the interrupt must first be selected in the BIOS setup utility under Advanced I O Devices aDIO Configuration aDIO Interrupt The Digital I O can use interrupts 3 5 6 7 10 11 and 12 The interrupt must also be reserved so that is it not assigned to PCI devices To reserve the interrupt enter the BIOS under PCIPnP and
101. ripheral devices to generate interrupts on the same computer the ISA bus has eight different interrupt request IRQ lines On the ISA bus a transition from low to high on one of these lines generates an interrupt request which is handled by the PC s interrupt controller On the PCI bus an interrupt request is level triggered The interrupt controller checks to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is based on the number of the IRQ IRQO has the highest priority IRQ1 is second highest and so on through IRQ7 which has the lowest Many of the IRQs are used by the standard system resources IRQO is used by the system timer IRQ1 is used by the keyboard IRQ3 by 2 IRQ4 by COMI and IRQ6 by the disk drives Therefore it is important to know which IRQ lines are available in your system for use by the cpuModule BDM 610000049 Rev G Chapter 4 Using the cpuModule 83 Intel 8259 Programmable Interrupt Controller The chip responsible for handling interrupt requests in the PC is the Intel 8259 Programmable Interrupt Controller To use interrupts you need to know how to read and set the Intel 82595 interrupt mask register IMR and how to send t
102. royed Such damage is not covered by the RTD warranty Please verify connections to the module before applying power Power is normally supplied to the cpuModule through the PCI bus connectors CN16 If you are placing the cpuModule onto a PC 104 Plus or PCI 104 stack that has a power supply you do not need to make additional connections to supply power If you are using the cpuModule without a PCI 104 or PC 104 Plus stack or with a stack that does not include a power supply refer to Auxiliary Power CN3 on page 26 for more details Some PCI 104 and PC 104 Plus expansion cards may require 3 3V supplied on the PC 104 Plus PCI connector CN16 To learn how to supply this voltage refer to Auxiliary Power CN3 on page 26 and Jumper Settings and Locations on page 86 BDM 610000049 Rev G Chapter 2 Getting Started 19 Connecting the Utility Cable The multi function connector CN5 implements the following interfaces e compatible keyboard e 5 2 mouse port e Speaker port 0 1W output e Hardware Reset input e Battery input for Real Time Clock e Soft Power Button input To use these interfaces you must connect to the utility port connector CN5 The utility harness from the RTD cable kit provides a small speaker two connectors for the keyboard and mouse a push button for resetting the PCI 104 system a soft power button and a lithium battery to provide backup power for the real time clock Refer to Utility Port Co
103. s information on CMX158886 cpuModule hardware including Jumper Settings and Locations page 86 Onboard PCI Devices page 88 Physical Dimensions page 89 BDM 610000049 Rev G Appendix A Hardware Reference 85 Jumper Settings and Locations Many cpuModule options are configured by positioning jumpers Jumpers are labeled on the board as JP followed by a number Some jumpers have three pins allowing three settings e Pins 2 connected indicated as 1 2 e Pins2 connected indicated as 2 3 e pins connected 1 2 3 LI 5 50 Some jumpers have two pins allowing two settings e Pins 2 connected indicated as closed e Pins 2 unconnected indicated as open 1 2 Figure 7 shows the jumper locations that are used to configure the cpuModule Table 62 lists the jumpers and their settings 09000000000 0600000000000 ooo JP9 oooon 00 00000 JP2 JP13 JP14 n 00000n 7 000000 m NOOOOOOOOOOO 00000000000 JP5 JP6 86 CMX158886 cpuModule BDM 610000049 Rev G Figure7 158886 Jumper Locations top side Table62 CMX158886 Jumpers Jumper Pins Function Default JP1 2 Enable disable 120 series termination to COM1 CN7 in RS 422 485 modes open JP2 2 Enable disable 120 series termination to CN8 in RS 422
104. source has been released by the user Table 42 lists I O addresses reserved for the CMX158886 cpuModule Table42 1 O Addresses Reserved for the CMX158886 cpuModule Address Range hex Bytes Device 000 00Fh 16 DMA Controller 010 01Fh 16 Reserved for CPU 020 021h 2 Interrupt Controller 1 022 02Fh 13 Reserved 040 043h 4 Timer 060 064h 5 Keyboard Interface 070 071h 2 Real Time Clock Port 080 08Fh 16 DMA Page Register 0A0 0A1h 2 Interrupt Controller 2 0CO ODFh 32 DMA Controller 2 OFO OFFh 16 Math Coprocessor 100 101h 2 Video Initialization 1F0 1FFh 16 Hard Disk 200 201h 2 Reserved 238 23Bh 4 Bus Mouse 2E8 2EFh 8 Serial Port 2F8 2FFh 8 Serial Port 3E8 3EFh 8 Serial Port 3F0 3F7h 8 Floppy Disk 3F8 3FFh 8 Serial Port 450 454h 4 aDIO 455h 1 Watchdog Timer 456 45F 9 EPLD 1 Ifa floppy or IDE controller is not connected to the system the I O addresses listed will not be occupied 2 Ifa PS 2 mouse is not connected to the system the I O addresses listed will not be occupied 3 Thel O addresses for the serial port are selected in the BIOS Setup utility 4 If aDIO is disabled the I O addresses listed will not be occupied 5 If watchdog timer is disabled the I O addresses listed will not be occupied 60 CMX158886 cpuModule BDM 610000049 Rev G Hardware Interrupts EN Note lf you add any expansion modules or other peripherals to the system you must ensure they do not use
105. style signals 5V Standby and PSON4 refer to the Power Management section in Chapter 4 Using the cpuModule 26 CMX158886 cpuModule BDM 610000049 Rev G Note The 43 3 V pins 10 and 12 on the auxiliary power connector CN3 are connected to the 43 3 V EN pins on the PC 104 Plus bus by default These pins are also configured to supply 3 3V to FP VCC on the LVDS Flat Panel Video connector CN19 Note For more information on configuring the 43 3V pins on the auxiliary power connector CN3 the PCI bus connector CN16 or the LVDS FLat Panel Video connector CN19 contact RTD Technical Support Facing the connector pins the pinout of the Auxiliary Power connector is 11 9 7 5 3 1 em 9 2 _ 12 10 8 6 4 2 BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 27 Utility Port Connector CN5 The utility port connector implements the following functions PC AT compatible keyboard port PS 2 mouse port Speaker port 0 1W output Hardware Reset input Battery input for Real Time Clock Soft Power Button input Table 8 provides the pinout of the multi function connector Table8 Utility Port Connector CN5 Pin Signal Function In Out 1 SPKR Speaker Output open collector out 2 PWR 5 out 3 RESET Manual Push Button Reset in 4 PWRSW Soft Power Button in 5 KBD Keyboard Data in out 6 KBC Keyboard Clock out 7 GND Ground 8 MSC Mouse Clock out 9 BAT RTC Batter
106. t has been asserted If a 1 is read the corresponding reset has been asserted If a 0 is read from the bit the reset has not been asserted e Clear Reset Each reset can be cleared by writing 1 to the selected bit of I O port 0x457 Table 57 Reset Status I O Address 457h Read Access D7 D6 D5 D4 D3 D2 D1 00 Power 5V Non Standby Power Standby Power PCI Reset 1 reset asserted 1 reset asserted 1 reset asserted 1 reset asserted 0 reset 0 reset 0 noreset 0 noreset CPU Core Power Memory Power Reserved Utility Reset 1 reset asserted 1 reset asserted 1 reset asserted 0 no reset 0 no reset 0 no reset Table 58 Reset Status I O Address 457h Write Access D7 D6 DS D4 03 02 D1 00 Power 5V Non Standby Power Standby Power PCI Reset 1 clear reset 1 clear reset 1 clear reset 1 clear reset CPU Core Power Memory Power Reserved Utility Reset 1 clear reset 1 clear reset 1 clear reset BDM 610000049 Rev G Chapter 4 Using the cpuModule 77 1 O Address 457h D7 D6 D5 D4 D3 D2 D1 DO Table 59 Reset Status Description and Priorities Reset Signal Main Power 5V CPU Core Power Non Standby Power Memory Power Standby Power reserved PCI Reset Utility Reset Reset Priority 2 3 4 Description Main input power to cpuModule 5V CPU core powers supply Power supplies that are not for standby power Power to onboard memory banks St
107. t mode for applications that will spend most of the time below OC e Variable The fan will spin slowly until the CPU reaches 60C and then will increase speed Maximum speed is reached when the CPU reaches 75C EN Note lf the CPU fan is connected to the continuous 5 V fan connector CN 14 changing the fan mode options in the BIOS will not affect the fan as it will always be turned on Further Temperature Reduction The cpuModule s temperature is directly related to power consumption Reducing the power consumption of the CPU will have an effect on the CPU s temperature Suggested methods for reducing the power consumption can be found in the Power Management section on page 73 72 CMX158886 cpuModule BDM 610000049 Rev G Power Management The CMX158886 cpuModule supports various powering mechanisms which allow the cpuModule to monitor power consumption and temperature and achieve minimal power consumption states These unique features include Enhanced Intel SpeedStep Technology PX only thermal monitoring and thermal throttling as well as low power modes including ACPI configurations Various wake options are also available to resume normal system power Enabling Enhanced Intel SpeedStep Technology PX only When enabled Enhanced Intel SpeedStep Technology can give application software greater control over the processor s operating frequency and input voltage This allows the system to easily manage power consumptio
108. t the pins remain in the off state when such voltage levels are connected as inputs to the cpuModule For specific electrical characteristics refer to Table 4 on page 13 multiPort Configured as an Advanced Digital 1 O aDIO Port The mulitPort connector CN6 can be configured as an aDIO port aDIO is 16 digital bits configured as 8 bit programmable and 8 bit port programmable I O providing any combination of inputs and outputs Match event and strobe interrupt modes mean no more wasting valuable processor time polling digital inputs Interrupts are generated when the 8 bit programmable digital inputs match a pattern or on any value change event Bit masking allows selecting any subgroup of 8 bits The strobe input latches data into the bit programmable port and generates an interrupt Refer to multiPort Advanced Digital I O Ports aDIO on page 62 for information on programming the multiPort Table27 multiPort aDIO Pinout CN6 Pin Function CN6 Pin Function 1 strobe 0 2 P0 4 3 P1 0 4 P0 5 5 P1 1 6 P0 6 7 P1 2 8 P0 7 9 P1 3 10 strobe 1 11 P1 4 12 GND 13 P1 5 14 GND 15 P1 6 16 GND 17 P1 7 18 GND 19 P0 0 20 GND 21 P0 1 22 GND 23 P0 2 24 GND 25 P0 3 26 5 42 CMX158886 cpuModule BDM 610000049 Rev G multiPort Configured as a Parallel Port The parallel port is available on connector CN6 Make sure the multiPort in the BIOS Setup is configured to parallel port You can use the BIOS Setup t
109. to be attached to the board with either a socketed or soldered connection Such true IDE devices are supported by all major operating systems and do not require special drivers devices that install as a BIOS extension such as the M Systems DiskOnChip If such a device is installed WARNING The ATA IDE Disk Chip socket does not support conventional SSD memory devices or the cpuModule and device will almost certainly be destroyed Table 16 ATA IDE Disk Chip Socket U16 Pin Signal Pin Signal 1 RESET 32 VDD 2 D7 31 D8 3 06 30 09 4 05 29 010 5 04 28 011 6 03 27 012 7 02 26 013 8 01 25 014 9 00 24 015 10 DMARQ WP 23 IOWR 11 IORD 22 DMACK CSEL 12 INTRQ 21 10 16 13 A1 20 PDIAG 14 AO 19 A2 15 CS1FX 18 CS3FX 16 GND 17 DASP 1 Signals marked with are active low 2 The hardware default configuration for VDD is 3 3 V but this pin may also be configured as 5 V For more information contact RTD Technical Support Installing and Configuring the ATA IDE Disk Chip To ensure proper installation and of the ATA IDE Disk Chip follow the following configuration steps Note that the first few steps must be performed before installing the Disk Chip 1 Before installing the ATA IDE Disk Chip in the Disk Chip Socket 016 verify that cpuModule is configured for the correct Disk Chip supply voltage The hardware default configuration is 3 3V To use a 5 V Disk C
110. unications Clock out 4 RED Red Analog Output out 5 DDCSDA Monitor Communications Data bidirectional 6 GREEN Green Analog Output out 7 PWR out 8 BLUE Blue Analog Output out 9 GND out 10 GND out Facing the connector pins of the SVGA Video connector CN18 the pinout is 7 3 1 BDM 610000049 Rev G Chapter 3 Connecting the cpuModule 31 The following table lists the supported video resolutions 32 CMX158886 cpuModule Table 12 SVGA Video Resolutions Resolution Colors Refresh Rates 640 x 480 16 256 64k 16M 60 70 72 75 85 100 120 Hz 720 x 480 256 64k 16M 60 Hz 720x576 256 64k 16M 50 Hz 800 x 600 16 256 64k 16M 60 70 72 75 85 100 120 Hz 960 x 540 256 64k 16M 60 Hz 1024 x 768 256 64k 16M 60 70 75 85 100 120 Hz 1152 x 864 256 64k 16M 60 70 72 75 85 100 Hz 1280 x 720 256 64k 16M 60 75 85 100 Hz 1280 x 768 256 64k 16M 60 75 85 Hz 1280 x 960 256 64k 16M 60 75 85 Hz 1280 x 1024 256 64k 16M 60 70 72 75 85 100 120 Hz 1400 x 1050 256 64k 16M 60 75 85 Hz 1600 x 900 256 64k 16M 60 75 85 100 120 Hz 1600 x 1200 256 64k 16M 60 65 70 72 75 85 100 120 Hz 1856 x 1392 256 64k 16M 60 75 Hz 1920 x 1080 256 64k 16M 50 60 75 85 100 Hz 1920 x 1200 256 64k 16M 60 75 Hz 1920 x 1440 256 64k 16M 60 75 85 Hz 2048 1536 256 G4k 16M 60 75 Hz BDM 610000049 Rev G LVDS Flat Panel Video Connector CN19 Table
111. use no power or wrong polarity Solution check for correct power on the PC 104 Plus PCI bus connector incorrect Setup reboot and press Delete to run Setup defective or misconnected device on bus check for misaligned bus connectors remove other cards from stack cable connected backwards verify all cables are connected correctly SSD installed backwards check for an SSD memory installed in socket backwards cpuModule keeps rebooting problem with power supply reset switch is on watchdog timer is not being serviced quickly enough check for correct power on the PC 104 Plus PCI bus connector check that the reset button is not pushed in verify that the watchdog timer is being refreshed before it times out cpuModule will not boot from particular drive or device device not bootable use sys command on drive or reformat the device using the s switch device not formatted format drive using s switch power not connected to boot drive connect power cable to floppy or hard drive erratic operation excessive bus loading reduce number of modules in stack remove termination components from bus signals remove any power supply bus terminations power supply noise examine power supply output with oscilloscope glitches below 4 75 VDC will trigger a reset add bypass caps power supply limiting examine power supply output with oscilloscope check for voltage drop b
112. utput Voltage Low Input Voltage High Input Voltage Low 3 3V supplied to PCI bus from power connector CN3 Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Test Condition PCI 0 5 mA lo 6 0 mA Bridge Link CN4 0 5 mA lo 6 0 mA Min 2 9 V 0 0 V 1 8 V 0 5 V 2 4 V 0 0 V 2 0 V 0 5 V IDE amp ATA IDE Disk Chip Socket Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Overcurrent Limit Differential Output Voltage Offset Voltage Supply Current for Panel Electronics Supply Current for Backlight Output Voltage High DDC FP ENABLK Output Voltage Low DDC FP ENABLK Input Voltage High DDC Input Voltage Low DDC 76 0 mA lo 60 mA USB Ports Total of both ports on a connector LVDS Port 1 0 mA lg 1 0 mA 2 8V 0 0 V 2 0 V 0 5 V 1 0A 250 mV 1 125 V 2 97 V Max 3 3V 0 55 V 5 5V 0 9 2A 3 3V 0 55 V 5 5 V 0 8 V 3 3 V 0 51 V 5 5 0 8 V 5 0 450 mV 1 375 V 2 2 3 3 V 0 33 V 3 6 V 0 8 V Chapter 1 Introduction 13 Symbol ADIOvcc luriLvec Vin Vi Table4 Electrical Characteristics Parameter Test Condition SVGA Port Output Voltage High lop 32 0 mA HSYNC VSYNC Output Voltage Low lg 32 0 mA HSYNC VSYNC Output Voltage High 74 0 mA DDC Output Volt
113. y Input in 10 MSD Mouse Data in out Facing the connector pins the pinout is Speaker 9 7 5 Le 10 8 6 3 4 SPKR 2 A speaker output is available on pins 1 and 2 of the multi function connector These outputs are controlled by a transistor to supply 0 1 W of power to an external speaker The external speaker should have 8 O impedance and be connected between pins 1 and 2 28 CMX158886 cpuModule BDM 610000049 Rev G Keyboard A PS 2 compatible keyboard can be connected to the multi function connector Usually PC keyboards come with a cable ending with a 5 pin male PS 2 connector Table 9 lists the relationship between the multi function connector pins and a standard PS 2 keyboard connector Table9 Keyboard Connector Pins CN5 Pin Signal Function PS 2 5 KBD Keyboard Data 1 6 KBC Keyboard Clock 5 7 GND Ground 3 2 PWR Keyboard Power 5 V 4 To ensure correct operation check that the keyboard is either an AT compatible keyboard or a switchable XT AT keyboard set to AT mode Switchable keyboards are usually set by a switch on the back or bottom of the keyboard Mouse A PS 2 compatible mouse can be connected to the multi function connector Table 10 lists the relationship between the multi function connector pins and a standard PS 2 mouse connector Table 10 Mouse Connector Pins CN5 Pin Signal Function PS 2 10 MSD Mouse Data 1 8 MSC Mouse Clock 5 7 GND Ground 3 2 PWR Key
114. ystem is in a soft off state and must be rebooted when it wakes Power Button Modes The soft power button input of the utility port connector CN5 can be configured by the operating system as a suspend button transition to S1 or S3 or as soft power button transition to S5 Consult your operating system documentation for information on how to configure it The power button will always cause a transition to S5 if pressed for 4 seconds or longer without interaction from the operating system Low Power Wake Options The cpuModule supports several methods of waking from a low power state Several of these wake options are BIOS configurable and can be accessed directly from the Power menu in the BIOS setup e Resume on Ring While in a low power mode the ring indicator input of either COM port may be used to wake the system BDM 610000049 Rev Chapter 4 Using the cpuModule 73 e Resume aDIO This option allows the system to use aDIO Strobe Match or Event interrupt to generate a wake event This event can wake the CPU from any power down mode including Soft Off S5 For more information refer to the section titled Wake on aDIO on page 65 e Resume on PME When enabled the system can wake when a signal is applied to the External Power Management connector CN12 This includes wake up on onboard LAN controller The PME signal is also available on the PC 104 Plus PCI bus connector e Resume on RTC Alarm The RTC Alarm

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