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Cypress Perform CY7C1354C User's Manual

1. Pin Configurations 100 Pin TQFP Pinout 8 IS 9309 ox 8 gt N S nox f gt 1 Q w lt lt 2255 292 lt lt lt lt re S QN OW N S iO st CO CQ OD CO CN O O O O O O O O O CO CO CO CO OO T O O CO CO O cO 1 NC 1 80 DQcO 2 79 NC 2 79 E1 NC DQcr 3 DQ 3 78 GNC 4 77 O Vona Vova q 4 77 O Vss O 5 76 Vss VssO 5 76 Vss DQ cO 6 75 5 DQb NC 6 75 DQcO 7 74 FI NC 7
2. 1 2 3 4 5 6 7 A VDDQ A A NC 18M A VDDQ NC 576M CE A ADV LD A C Vin A NC D DQ Vss NC Vss DQ E DQ DQ Vss Vss DQ DQ F DQ Vss OE Vss G DQ BW A BW DQ DQ H DQ Vss WE Vss DQ DQ J VDDQ VDD NC Vpp NC Vpp VDDQ K DQ Vss CLK Vss DQ DQ L DQy DQy BW NC BW DQ DQ M VDDQ DQg Vss CEN Vss DQa VDDQ N DO DQ 1 Vss DQ DQ DQ Vss AO Vss DQ R NC 144M A MODE Vpp NC A NC 288M T NC NC 72M A A A NC 36M ZZ U Vppa TMS TDI TCK TDO NC Vppo CY7C1356C 512K x 18 1 2 3 4 5 6 7 8 NC 576M ADV LD A C NCAG A A Vpp A A NC D NC Vss NC Vss DQ Vss CE Vss NC DQ F NC Vss OE Vss DQ G NC DQ BW A Vss NC DQ H DQ NC Vss WE Vss DQ NC J VDDQ VDD NC Vpp NC Vpp K NC Vss CLK Vss NC DQ L Vss NG BW DO NC M VDDQ DQp Vss CEN Vss NC NC Vss Ai Vss DQ NC DAP Vss A0 Vss NC DQ R NC 144M A MODE 288 72 6 ZZ U Voa TMS TDI TCK TDO NC Mond Document 38 05538 Rev G CY7C1354C CY7C1356C Page 4 of 28 Feedback
3. gt CYPRESS CY7C1356C PERFORM Capacitance 6 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max Max Max Unit Cin Input Capacitance TA 25 C f 1 MHz 5 5 5 pF Clock Input Capacitance Vpp 3 3V 2 5 5 5 5 pF Cio Input Output Capacitance 5 7 7 pF Thermal 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max Max Max Unit OJA Thermal Resistance Test conditions follow standard 29 41 34 1 16 8 C W Junction to Ambient test methods and procedures for ing thermal impedance Ojo Thermal Resistance ieee 6 13 14 0 3 0 C W Junction to Case per 5051 AC Test Loads and Waveforms 3 3V I O Test Load 3170 OUTPUT 3 3V ALL INPUT PULSES OUTPUT 90 500 5 pF GND INCLUDING R 3519 lt 1ns gt lt ns 1 5V JIG AND 25V R 16672 OUTPUT R 500 5 pF R 15380 Vy 1 25V INCLUDING ii AND a scope b c Document 38 05538 Rev G Page 18 of 28 Feedback ARE CY7C1354C CYPRESS CY7C1356C PERFORM Switching Characteristics Over the Operating Range 18 19 250 200 166 Parameter Description Min Max Min Max Min Max Unit tower Vcc
4. CY7C1354C EZ CYPRESS CY7C1356C PERFORM Pin Configurations continued 165 Ball FBGA Pinout CY7C1354C 256K x 36 1 2 3 4 5 6 7 8 9 10 11 A 578 CE BW BW CEN ADV LD A A NC B A CE2 BW BW CLK WE OE NC 8M NC DAP NC Vss Vss Vss Vss Vss VDDQ NC D DQ Vss Vss Vss VDD 26 DQ Vpp Vss Vss Vss Vpp DQ F DQ Vpp Vss Vss Vss Vpp G DQ DQ Vpp Vss Vss Vss Vpp Vppo DQ H NC NC NC VDD Vss Vss Vss VoD NG NC ZZ J DQg DQg Vpp Vss Vss Vss Vppa DQ K DQg DQg Vpp Vss Vss Vss Vpp Vppa DQ L DQg DQg Vpp Vss Vss Vss Vpp Vppa DQ M DQg Vss Vss Vss Vppa NC Vppa Vss NC NC NC Vss Vba DOP P NC 144M NC 72M A A TDI A1 TDO A A A NC 288M R MODE NC 36M A A TMS AO TCK A A A A CY7C1356C 512K x 18 1 2 3 4 5 6 7 8 9 10 11 NC 576M BW NC CEN ADV D A A A B NCAG A CE2 NC BW CLK WE OE NC 18M A Vss Vss Vss Vss Vss VDDQ NC D NC DQ Vss Vss Vss Vpp Vss Vss Vss Vpp VDDQ NC DQa F NC DQp Voo Vss Vss Vss Vpp VDDQ NC DQa G
5. 0 05 ME 0 25 MCAB 1 00 75 0 15 119 01 00 3 REF z 1234567 7654321 A _ 8 4 L C OQOOOOQOO E E 0000000 F G OOOOOOO G H 2 QOOQOQOOO H jeep 8 E PC 1 a 1 8 ii N OOOQOOO L M OOOQOOO M N 2 N R QOQOOOOOGO R T vip A eooooee 1 27 0 70 REF a a 12 00 762 8 1 4 40002 S 30 TYP f a 015 4 8 e rnm e n MEE q 51 85115 Et SEATING PLANE d in c Document 38 05538 Rev Page 26 of 28 Feedback gt Cd CY7C1354C CYPRESS CY7C1356C PERFORM Package Diagrams continued 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 BOTTOM VIEW PIN 1 CORNER TOP VIEW 9005M C PIN 1 CORNER 0 25 MEAIB 00 50 7906 165X 30 14 t 2 3 4 5 6 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A Ma B ET 90000900000 B 5 8 D A
6. 84 gt 94 gt gt 8 Partial Write Cycle Description 3 9 Function CY7C1356C Read D Write No Bytes Written Write Byte a DQ Write Byte b DQ and Write Both Bytes Al myr pr pr oie 00 11 w r rrir x g Note 9 Table only lists a partial listing of the byte write combinations Any combination of BW y is valid Appropriate write will be done based on which byte write is active Document 38 05538 Rev G Page 9 of 28 Feedback SES Cypress CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1354C CY7C1356C incorporates a serial boundary scan test access port TAP in the BGA package only The TQFP package does not offer this functionality This part operates in accordance with IEEE Standard 1149 1 1900 but doesn t have the set of functions required for full 1149 1 compliance These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149 1 fully
7. mn m u SM 7 1354 YPRESS CY7C1356C PERFOR 9 Mbit 256K x 36 512K x 18 Pipelined SRAM with NoBL Architecture Features Functional Description Pin compatible and functionally equivalent to ZBT The 7 1354 and CY7C1356C are 3 3V 256K x 36 and 2 512K 18 Synchronous pipelined burst SRAMs with No Bus Supports 250 MHz bus operations with zero wait states Latency logic respectively They are designed to Available speed grades are 250 200 and 166 MHz support unlimited true back to back Read Write operations Internally self timed output buffer control to eliminate with no wait states The CY7C1354C and CY7C1356C are the need to use asynchronous OE equipped with the advanced NoBL logic required to enable EET consecutive Read Write operations with data being trans Fully registered inputs and outputs for pipelined ferred on every clock cycle This feature dramatically improves operation the throughput of data in systems that require frequent Byte Write capability Write Read transitions The CY7C1354C and CY7C1356C are Single 3 3V power supply Vpp pin compatible and functionally equivalent to ZBT devices 3 3V or 2 5V I O power supply All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through Fast clock to output times output registers controlled by the rising e
8. DQP DQPa coco mazma ACTO Cz 2omrm ic PHPO INPUT REGISTER 1 INPUT REGISTER 0 OE 1 READ LOGIC SLEEP CONTROL Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com Cypress Semiconductor Corporation 198 Champion Court San Jose 95134 1709 e 408 943 2600 Document 38 05538 Rev G Revised September 14 2006 Feedback eM 11 H CYPRESS PERFORM CY7C1354C CY7C1356C MODE ADV LD OE 1 READ LOGIC Slee Control Logic Block Diagram CY7C1356C 512K 18 ADV LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE ADDRESS REGISTER 2 MEMORY ARRAY UE mnzmun m wxman amx ACvACO wamnncw ACCO Qz zmm du PAPO m DQs DQPa Selection Guide 250 MHz 200 MHz 166 MHz Unit Maximum Access Time 2 8 3 2 3 5 ns Maximum Operating Current 250 220 180 mA Maximum CMOS Standby Current 40 40 40 mA Document 38 05538 Rev G Page 2 of 28 Feedback CY7C1354C P CYPRESS CY7C1356C PERFORM 1
9. 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14005010 100 81 RRRRRHRRRHRRRRRHRRRER n cr VU I3 E E ES 0 30 0 08 En d F 9 ES 5 5 ES 8 8 ES E 8 S Es ES 065 ES E ES ES ES ES 30 Fo 51 1 HEERHHHHHHHHEHHHEHHEE 31 50 R 0 08 MIN 0 20 0 MIN d STAND OFF d mE e 0 05 MIN H 0 15 MAX GAUGE PLANE i 23 R 0 08 MIN 0 7 0 20 0 60 0 15 0 20 MIN 1 00 REF DETAIL Document 38 05538 Rev G NOTE 1 JEDEC STD REF MS 026 SEATING PLANE 1 40 0 05 A SEE DETAIL A 0 20 MAX 1 60 0 10 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 51 85050 B Page 25 of 28 Feedback RE CY7C1354C CYPRESS CY7C1356C Package Diagrams continued 119 Ball BGA 14 x 22 x 2 4 mm 51 85115
10. 12 3 M4 7 46 N2 M2 4 F4 B8 47 N1 M1 5 B4 48 2 L1 6 G4 A9 49 L1 Ki 7 C3 B10 50 K2 J1 8 B3 A10 51 Not Bonded Not Bonded 9 D6 Cii Preset to 1 Preset to 1 10 H7 E10 52 H1 G2 11 G6 F10 53 G2 Fe 12 E6 G10 54 E2 E2 13 D7 D10 55 D1 D2 14 E7 11 56 H2 G1 15 F6 57 G1 Fi 16 G7 Fit 58 Fe Et 17 H6 59 E1 D1 18 T7 HTI 60 D2 C1 19 K7 J10 61 C2 B2 20 L6 K10 62 A2 A2 21 N6 L10 63 E4 A3 22 P7 M10 64 B2 B3 23 N7 Ji 65 L3 B4 24 M6 Kt 66 G3 4 25 L7 11 67 GS AS 26 K6 M11 68 L5 B5 27 P6 N11 69 B6 A6 28 T4 29 R10 30 C5 P10 81 B5 R9 32 A5 P9 33 C6 R8 34 A6 P8 35 P4 R6 36 N4 P6 37 R6 R4 38 T5 P4 39 T3 R3 40 R2 P3 41 R3 R1 42 P2 Ni 43 1 L2 Page 15 of 28 Feedback 2 CYPRESS PERFORM Boundary Scan Exit Order 512K x 18 Boundary Scan Exit Order 512K x 18 continued CY7C1354C CY7C1356C Bit 4 119 ball ID 165 ball ID Bit 4 119 ball ID 165 ball ID 1 K4 B6 39 T3 R3 2 H4 B7 40 R2 P3 3 M4 A7 41 R3 R1 4 F4 B8 42 Not Bonded Not Bonded 5 B4 8 Preset to 0 Preset to 0 6 G4 9 li Presetto0 Presetto 0 d a 10 44 Not Bonded Not Bonded 8 B3 A10 Preset to 0 Preset to 0 9 T2 11 45 Not Bonded Not Bonded 10 Not Bonded Not Bonded Preset to 0 Preset to
11. 74 O DQc 8 73 E1 DQb 8 73 DQa DQc 9 72 DQb DQb 9 72 DQa yss 10 71 E Vss Vss 10 71 Vss DDAL 11 70 5 2221 11 H DQcH 12 2206 DQb EH 12 O DQc 13 2 DQb H 13 68 V CY7C1354C im M OE CY7C1356C 67 E 66 DD 66 Nc g 16 256K x 36 65 Yop 16 512K x 18 65 Vss 17 64 O ZZ Vss 17 64 O ZZ DQdr 18 63 DQb Lj 18 1 19 62 19 O Vova 20 61 20 61 O Vss 21 60 Vss Vss 21 60 Vss DQdH 22 59 1 DQb o 22 59 DQa DQdr 23 58 DQa DQb 23 5g O DQdrj 24 57 1DQa DQPb 24 57 ONC DQdq 25 56 1 DQa NC 25 56 ONC 55 26 55 Vss Vss o 26 55 H Vss 27 54 Vooad 27 54 DQdr 28 53 NC O 28 53 L1 NC 0991 29 52 O NC o 29 CNC 30 51 NCC 51 FNC 3 9 38 SES SSR LI LI UU LI LT LI LT LT LT LT 5 lt lt lt lt 226 08 8 lt lt lt lt lt lt lt 8 lt lt lt lt 684 lt 4 lt lt lt lt lt lt 9 gt gt gt 99 22 5 22 2 2 Document 38 05538 Rev G Page 3 of 28 Feedback oM CYPRESS PERFORM Pin Configurations continued 119 Ball BGA Pinout CY7C1354C 256K x 36
12. 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1356C 166BGXI CY7C1354C 166BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1356C 166BZI CY7C1354C 166BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 Lead Free CY7C1356C 166BZXI 200 CY7C1354C 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial 7 1356 200 CY7C1354C 200BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1356C 200BGC CY7C1354C 200BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1356C 200BGXC CY7C1354C 200BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1356C 200BZC CY7C1354C 200BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1356C 200BZXC CY7C1354C 200AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1356C 200AXI CY7C1354C 200BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1356C 200BGI CY7C1354C 200BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1356C 200BGXI CY7C1354C 200BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1356C 200BZI CY7C1354C 200BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1356C 200BZXI Document 38 05538 Rev G Page 23 of 28 Feedback ie CY7C1354C 74 CYPRESS CY7C1356C P
13. NC DQ Vss Vss Vss VDDQ NC DQa H NC NC NC Vss Vss Vss Vpop ZZ J DQ NC Vpp Vss Vss Vss Vpp Vppa DQ NC K Vpp Vss Vss Vss Vpp L VDDQ Vpp Vss Vss Vss Vpp Vppa NC M Vppa Vpp Vss Vss Vss Vpp Vppa DQ NC N NC Vss NC NC NC Vss Vooo NC 144M NC 72M A A TDI A1 TDO A A A NC 288M R MODE NC 36M A A TMS AO TCK A A A A Document 38 05538 Rev G Page 5 of 28 Feedback Pin Definitions CY7C1354C CY7C1356C Pin Name Type Pin Description 0 1 Input Address Inputs used to select one of the address locations Sampled at the rising edge of A Synchronous CLK BW BWp Input Byte Write Select Inputs active LOW Qualified with WE to conduct writes to the SRAM BW BWg Synchronous Sampled on the rising edge of CLK BW controls DQ and DQP BW controls DQ and BW controls DQ and DQP BW controls DQg and DQP WE Input Write Enable Input active LOW Sampled on the rising edge of CLK if CEN is active LOW Synchronous This signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input used to advance the on chip address counter or load a new address Synchronous When HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW new address can be load
14. V Output HIGH Voltage 100 pA 3 3V 2 9 V Vppq 2 5V 2 1 V Vout Output LOW Voltage loj 8 0 mA Vppo 3 3V 0 4 V 2 5V 0 4 V Voi2 Output LOW Voltage loj 100 pA Vppo 3 3V 0 2 V Vppq 2 5V 0 2 V Vin Input HIGH Voltage 3 3V 2 0 Vpp 0 3 V Vppo 2 5V 1 7 Vpp 0 3 V ViL Input LOW Voltage Vppo 3 3V 0 3 0 8 V Vppo 2 5V 0 3 0 7 V Ix Input Load Current GND lt Vin lt 5 5 Identification Register Definitions Instruction Field CY7C1354C CY7C1356C Description Revision Number 31 29 000 000 Reserved for version number Cypress Device ID 28 12 131 01011001000100110 01011001000010110 Reserved for future use Cypress JEDEC ID 11 1 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence 0 1 1 Indicate the presence of an ID register Notes 12 All voltages referenced to Vgg GND 13 Bit 24 is 1 in the Register Definitions for both 2 5V and 3 3V versions of this device Document 38 05538 Rev G Page 13 of 28 Feedback CY7C1354C CYPRESS CY7C1356C PERFORM Scan Register Sizes Register Name Bit Size x36 Bit Size x18 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order 119 ball BGA package 69 69 Boundary Scan Order 165 ball FBGA package 69 69 Identification Codes Instruction Code Description EXTE
15. Write operation can be initiated 18 Timing reference level is 1 5V when Vppq 3 3V and is 1 25V when Vppq 2 5V 19 Test conditions shown in a of AC Test Loads unless otherwise noted 20 toyz 2 tgorz and tgopz are specified with AC test conditions shown in b of AC Test Loads Transition is measured 200 mV from steady state voltage 21 At any given voltage and temperature is less than tgo 7 and toy is less than 7 to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 22 This parameter is sampled and not 100 tested Document 38 05538 Rev G Page 19 of 28 Feedback CY7C1354C F CYPRESS CY7C1356C rERFPORM Switching Waveforms Read Write Timingl 24 25 1 2 te 18 4 5 6 7 8 9 10 SE EC CEN 77 gt MD 4 ADDRESS ZAI ZZ NS NIK NS VIN BS VIN XUL gi ae e tas i Data T T Out DQ WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELEC D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6
16. edge of TCK All outputs are driven from the falling edge of TCK Document 38 05538 Rev G CY7C1354C CY7C1356C Test MODE SELECT TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most signif icant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See Tap Controller State Diagram TAP Controller Block Diagram rR 0 Bypass Register gt 2 1 0 Selection de Instruction Register Circuitry Selection 313029 21 0 Ciruitry TDI TDO Identification Register Bou
17. 0 Preset to 0 Preset to 0 46 P2 N1 11 Not Bonded Not Bonded 47 N1 M1 Preset to 0 Preset to 0 48 M2 E EE x 13 06 50 on EN NN ee 15 F6 E11 52 Hi G2 16 G7 11 53 G2 F2 17 H6 G11 54 18 7 H11 55 Di 18 S 10 56 Not Bonded Not Bonded 20 L6 K10 Preset to 0 Preset to 0 21 N6 L10 57 Not Bonded Not Bonded 22 P7 M10 Preset to 0 Preset to 0 23 Not Bonded Not Bonded 58 Not Bonded Not Bonded Preset to 0 Preset to 0 Preset to 0 Preset to 0 24 Not Bonded Not Bonded 59 Not Bonded Not Bonded Preset to 0 Preset to 0 Preset to 0 Preset to 0 25 Not Bonded Not Bonded 60 Not Bonded Not Bonded Preset to 0 Preset to 0 Preset to 0 Preset to 0 26 Not Bonded Not Bonded 61 C2 B2 Preset to 0 Preset to 0 62 A2 A2 27 Not Bonded Not Bonded 63 E4 Preset to 0 Preset to 0 64 B2 B3 28 16 i 65 Not Bonded Not Bonded 29 R10 Preset to 0 Preset to 0 30 C5 P10 66 G3 Not Bonded 31 B5 R9 Preset to 0 32 A5 P9 67 Not Bonded A4 33 C6 R8 Preset to 0 34 A6 P8 35 4 R6 ie Be 36 N4 P6 37 R6 R4 38 T5 P4 Document 38 05538 Rev G Page 16 of 28 Feedback CY7C1354C CE CYPRESS CY7C1356C PERPCXM Maximum Ratings DC Input V
18. Byte Write capability that is described in the Write Cycle Description table Asserting the Write Enable input WE with the selected Byte Write Select BW input will selectively write to only the desired bytes Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed write mechanism has been provided to simplify the Write operations Byte Write capability has been included in order to greatly simplify Read Modify Write sequences which can be reduced to simple Byte Write operations Page 7 of 28 Feedback Because the CY7C1354C and CY7C1356C are common devices data should not be driven into the device while the outputs are active The Output Enable OE can be deasserted HIGH before presenting data to the DQ ang pap DQa p c g DQPa for CY7C1354C and DQ y DQP p for CY7C1356C inputs Doing so will tri state the output drivers As a safety precaution DQ ang DQa p c DQPa p c for CY7C1354C and DQ4jyDQPa4 for CY7C1356C are automatically tri stated during the data portion of a write cycle CY7C1354C CY7C1356C mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE4 CE and CE4 must remain inactive for the duration of after the ZZ input returns LOW Interleaved Burst Ad
19. D A7 D A2 1 4 1 DON T CARE UNDEFINED Notes 23 For this waveform ZZ is tied low 24 When CE is LOW CE is LOW CE is HIGH and CE is LOW When CE is HIGH CE is HIGH or is LOW or is HIGH 25 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Document 38 05538 Rev G Page 20 of 28 Feedback CY7C1354C S76 CYPRESS CY7C1356C Switching Waveforms continued 7 8 9 10 NOP STALL and DESELECT 23 24 26 1 2 3 4 5 6 123 452 1 9 12 mA Ih m uU m uiu m m D CONTINUE DESELECT DESELECT READ Q A5 Data NOP In Out DQ STALL WRITE READ D A4 STALL Q A3 READ WRITE Q A2 D A1 7 M DON T CARE UNDEFINED 26 The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrated CEN being used to create a pause A write is not performed during this cycle Page 21 of 28 Feedback Document 38 05538 Rev G R _ LLL ILL CY7C1354C CYPRESS CYPRESS CY7C1356C Switching Waveforms continued ZZ Mode Timing 28 oe e TA af SUPPLY X ppzz ALL INPUTS m DESELECT or READ Only X Outputs Q High DO
20. ERFORM a Ordering Information continued Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered 250 CY7C1354C 250AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1356C 250AXC CY7C1354C 250BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1356C 250BGC CY7C1354C 250BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1356C 250BGXC CY7C1354C 250BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1356C 250BZC CY7C1354C 250BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1356C 250BZXC CY7C1354C 250AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1356C 250AXI CY7C1354C 250BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1356C 250BGI CY7C1354C 250BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1356C 250BGXI CY7C1354C 250BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1356C 250BZI CY7C1354C 250BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1356C 250BZXI Document 38 05538 Rev G Page 24 of 28 Feedback Package Diagrams CY7C1354C CY7C1356C
21. H input on ADV LD will increment the internal burst counter regardless of the state of chip enables inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 CE and CE are ALL asserted active and 3 the Write signal WE is asserted LOW The address presented to Ag A g is loaded into the Address Register The write signals are latched into the Control Logic block On the subsequent clock rise the data lines are automatically tri stated regardless of the state of the OE input signal This allows the external logic to present the data on DQ ang pap DQa p c g DQPa p c q for CY7C1354C and y DQPa y for CY7C1356C In addition the address for the subsequent access Read Write Deselect is latched into the address register provided the appropriate control signals are asserted On the next clock rise the data presented to DQ ang pap DQa p c g DQPa p c q for CY7C1354C and DQ DQP for CY7C1356C or a subset for byte write operations see Write Cycle Description table for details inputs is latched into the device and the Write is complete The data written during the Write operation is controlled by BW for CY7C1354C and BWa for CY7C1356C signals The CY7C1354C CY7C1356C provides
22. Input Leakage Current GND lt V lt Vppq 5 5 except ZZ and MODE Input Current of MODE Input Vss 30 Input Vpp 5 Input Current of ZZ Input Vss 5 Input Vpp 30 HA loz Output Leakage Current GND lt V lt Output Disabled 5 5 Ipp Vpp Operating Supply Vpp Max 0 mA 4 ns cycle 250 MHz 250 mA f fmax 1 5 ns cycle 200 MHz 220 mA 6 ns cycle 166 MHz 180 mA Ispy Automatic CE Max Vpp Device Deselected 4 ns cycle 250 MHz 130 mA CUORE TTL Inputs 1 or Vin lt f fmax 5 cycle 200 MHz 120 mA 6 ns cycle 166 MHz 110 mA Ispo Automatic CE Max Vpp Device Deselected All speed grades 40 mA Power down Vin 0 3V or Vin gt 0 3V Current CMOS Inputs 0 Automatic CE Max Vpp Device Deselected 4 ns cycle 250 MHz 120 mA 6 ns cycle 166 MHz 100 mA Automatic CE Max Vpp Device Deselected All speed grades 40 mA Power down Vin 2 Vin or Vin lt Vj f 0 Current TTL Inputs Notes 14 Overshoot lt Vpp 1 5V Pulse width less than 2 undershoot Vi AC gt 2V Pulse width less than 2 15 Tpower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time lt Vpp and lt Vpp 16 Tested initially and after any design or process changes that may affect these parameters Document 38 05538 Rev G Page 17 of 28 Feedback
23. N T CARE 27 Device must be deselected when entering ZZ mode See cycle description table for all possible signal conditions to deselect the device 28 I Os in High Z when exiting ZZ sleep mode Document 38 05538 Rev G Page 22 of 28 Feedback P CYPRESS PERFORM Ordering Information CY7C1354C CY7C1356C Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Part and Package Type Range 166 CY7C1354C 166AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1356C 166AXC CY7C1354C 166BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1356C 166BGC CY7C1354C 166BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1356C 166BGXC CY7C1354C 166BZC 51 85180 165 ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm CY7C1356C 166BZC CY7C1354C 166BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1356C 166BZXC CY7C1354C 166AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1356C 166AXI CY7C1354C 166BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1356C 166BGI CY7C1354C 166BGXI 51
24. S Test Mode Select This pin controls the Test Access Port state machine Sampled on the rising edge of TCK Synchronous TCK JTAG Clock Clock input to the JTAG circuitry Vpp Power Supply Power supply inputs to the core of the device VDDQ Power Supply Power supply for the I O circuitry Vss Ground Ground for the device Should be connected to ground of the system Document 38 05538 Rev G Page 6 of 28 Feedback SJ Cypress CYPRESS PERFORM Pin Definitions continued CY7C1354C CY7C1356C Pin Name Type Pin Description NC No connects This pin is not connected to the die NC 18 36 These pins not connected They will be used for expansion to the 18M 36M 72M 144M 72 144 288 288M 576M and 1G densities 576 1G ZZ Input ZZ sleep Input This active HIGH input places the device in a non time critical sleep Asynchronous condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down Functional Overview The CY7C1354C and CY7C1356C are synchronous pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recognized and
25. ST 000 Captures the Input Output ring contents Places the boundary scan register between the TDI and TDO Forces all SRAM outputs to High Z state IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and This operation does not affect SRAM operation SAMPLE Z 010 Captures the Input Output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the Input Output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Placesthe bypass register between TDI and This operation does not affect SRAM operation Document 38 05538 Rev G Page 14 of 28 Feedback NJ CYPRESS PERFORM Boundary Scan Exit Order 256K x 36 Boundary Scan Exit Order 256K 36 continued CY7C1354C CY7C1356C Document 38 05538 Rev G Bit 119 ball ID 165 ball ID Bit 119 ball ID 165 ball ID 1 K4 B6 44 L2 K2 2 H4 B7 45 Ki
26. all internal states are maintained All synchronous operations are qualified with CEN All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise tco is 2 8 ns 250 MHz device Accesses can be initiated by asserting all three Chip Enables CE4 CEs CE3 active at the rising edge of the clock If Clock Enable CEN is active LOW and ADV LD is asserted LOW the address presented to the device will be latched The access can either be a Read or Write operation depending on the status of the Write Enable WE BWia a be used to conduct Byte Write operations Write operations are qualified by the Write Enable WE All Writes are simplified with on chip synchronous self timed Write circuitry Three synchronous Chip Enables CE4 CE3 and an asynchronous Output Enable OE simplify depth expansion All operations Reads Writes and Deselects are pipelined ADV LD should be driven LOW once the device has been deselected in order to load a new address for the next operation Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 and CE ALL asserted active 3 the Write Enable input signal WE is deasserted HIGH and 4 ADV LD is asserted LOW The address presented to the address inputs is latched into the address register and presented to the memory co
27. cle is detected all I Os are tri stated even during Byte Writes Device will power up deselected and the I Os a tri state condition regardless of OE OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle DQs and Tri state when OE is inactive or when the device is deselected and DQs data when OE is active Page 8 of 28 Feedback A Pd CYPRESS PERFORM Truth 2 3 4 5 6 7 8 CY7C1354C CY7C1356C Address Operation Used CE 22 ADV LD W CLK DQ NOP WRITE ABORT Begin Burst None L Tri State WRITE ABORT Continue Burst Next Tri State IGNORE CLOCK EDGE Stall Current SLEEP MODE None XxX X X m Iome H X X x x x i Z x x x x x x x x Q gt lt I m m Tri State Partial Write Cycle Description 91 Function CY7C1354C o o Ww v Read Write No bytes written Write Byte a DQ and Write Byte b DQ and DQP Write Bytes b a Write Byte c DQ DQP Write Bytes c a Write Bytes c b Write Bytes c b a Write Byte d DQg and Write Bytes d a Write Bytes d b Write Bytes d b a Write Bytes d c Write Bytes d c a Write Bytes d c b Write All Bytes
28. compliant TAPs The TAP operates using JEDEC standard 3 3V or 2 5V I O logic levels The CY7C1354C CY7C1356C contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS inter nally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO should be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device TAP Controller State Diagram TEST LOGIC RESET 0 C RUN TEST 1 SELECT 1 SELECT 1 IDLE i DRSCAN IR SCAN 0 0 1 1 CAPTURE DR CAPTURE IR 0 0 3 T SHIFT DR D SHIFTIR 707 10 1 1 1 1 Le EXITLDR Le EXITHR 0 0 Y Y PAUSEDR 707 PAUSE IR D 0D 1 1 0 Y 0 Y EXIT2 DR EXIT2 IR 1 1 Y i d UPDATEDR UPDATER 0 1 0 Y The 0 1 next to each state represents the value of TMS at the rising edge of TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising
29. dge of the clock The 2 8 ns for 250 MHz device clock input is qualified by the Clock Enable CEN signal which when deasserted suspends operation and extends the previous clock cycle Clock Enable CEN pin to suspend operation Synchronous self timed writes Write operations are controlled by the Byte Write Selects Available in lead free 100 Pin TQFP package lead free BW4 BW for CY7C1354C BW BW for CY7C1356C and non lead free 119 Ball BGA package and 165 Ball and a Write Enable WE input All writes are conducted with FBGA package on chip synchronous self timed write circuitry IEEE 1149 1 JTAG Compatible Boundary Scan Three synchronous Chip Enables CE asynchronous Output Enable OE provide for easy bank selection and output tri state control In order to avoid bus ZZ Sleep Mode option and Stop Clock option contention the output drivers are synchronously tri stated during the data portion of a write sequence Burst capability linear or interleaved burst order Logic Block Diagram CY7C1354C 256K x 36 ADDRESS AL REGISTER 0 Di qi BURST go A0 LOGIC MODE C ADV D WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC MEMORY ARRAY BW BWo BW BWa WE WRITE DRIVERS DQs
30. dress Table MODE Floating or Vpp regardless of the state of OE First Second Third Fourth Burst Write Address Address Address Address 2 1 AT AO A1 A0 AT AO The CY7C1354C CY7C1356C has an on chip burst counter 00 01 10 1 that allows the user the ability to supply a single address and 01 00 11 10 conduct up to four WRITE operations without reasserting the address inputs ADV LD must be driven LOW in order to load 10 11 00 01 the initial address as described in the Single Write Access 11 10 01 00 section above When ADV LD is driven HIGH on the subse quent clock rise the chip enables CE4 and CE3 and Linear Burst Address Table MODE GND WE inputs are ignored and the burst counter is incremented First Second Third Fourth The correct BW for CY7C1354C BW for Address Address Address Address CY7C1356C inputs must be driven in each cycle of the burst 1 ALAO 1 A1 A0 write in order to write the correct bytes of data _ 00 01 10 11 Sleep Mode 01 10 11 00 The ZZ input pin is an asynchronous input Asserting ZZ 10 n 00 01 places the SRAM in a power conservation sleep mode Two 11 00 01 10 clock cycles are required to enter into or exit from this sleep ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode
31. ed into the device for an access After being deselected ADV LD should be driven LOW in order to load a new address CLK Input Clock Input Used to capture all synchronous inputs to the device CLK is qualified with CEN Clock CLK is only recognized if CEN is active LOW CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous gt and CE to select deselect the device Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction Synchronous with CE and CE to select deselect the device Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device OE Input Output Enable active LOW Combined with the synchronous logic block inside the device to Asynchronous _ control the direction of the I O pins When LOW the I O pins are allowed to behave as outputs When deasserted HIGH pins are tri stated and act as input data pins OE is masked during the data portion of a Write sequence during the first clock when emerging from a deselected state and when the device has been deselected CEN Input Clock Enable Input active LOW When asserted LOW the clock signal is recognized by the Synchronous SRAM When deasserted HIGH the clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when re
32. g data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the ldentification Register Definitions table TAP Instruction Set Overview Eight different instructio
33. he load TAP AC test Conditions tp te 1 ns Document 38 05538 Rev G Page 12 of 28 Feedback CY7C1354C a CYPRESS CY7C1356C PERPCOKM m 3 3V TAP AC Test Conditions 2 5V TAP AC Test Conditions Input pulse levels Vgg to 3 3V Input pulse levels sse Vgg to 2 5V Input rise and fall 1ns Input rise and fall time 1ns Input timing reference 1 5V Input timing reference 1 25V Output reference 0 1 5V Output reference levels 1 25V Test load termination supply voltage 1 5V Test load termination supply voltage 1 25V 3 3V TAP AC Output Load Equivalent 2 5V TAP AC Output Load Equivalent 1 5V 1 25V 50Q 500 TDO TDO Zo 502 20pF 20 500 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt TA lt 70 Vpp 3 3V 0 165V unless otherwise noted Parameter Description Test Conditions Min Max Unit Vout Output HIGH Voltage 4 0 mA 3 3V 2 4 V 71 0 mA 2 5V 2 0
34. hift DR state the bypass TAP Timing CY7C1354C CY7C1356C register is placed between the TDI and TDO balls The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board Reserved These instructions are not implemented but are reserved for future use Do not use these instructions 1 2 Test Clock TCK tni tTMss tTMsH Test Mode Select yx S fois Test Data In yj V TDI trbov DOX Test Data Out UNDEFINED AC Switching Characteristics Over the Operating Rangel 111 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns 1 TCK Clock Frequency 20 MHz tty TCK Clock HIGH time 20 ns tr TCK Clock LOW time 20 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns ttpox TCK Clock LOW to TDO Invalid 0 ns Set up Times truss TMS Set up to TCK Clock Rise 5 ns trpis TDI Set up to TCK Clock Rise 5 ns tes Capture Set up to TCK Rise 5 ns Hold Times trusH TMS Hold after TCK Clock Rise 5 ns TDI Hold after Clock Rise 5 ns icu Capture Hold after Clock Rise 5 ns Notes 10 tcs and refer to the set up and hold time requirements of latching data from the boundary scan register 11 Test conditions are specified using t
35. mi O OO oO SO D E QQQO O QOO Q0 C O cQ OQ E F Q OOO F 2 g Is i a 8 8 7 1 L 3 8 M Q OO OQ M N N P Qo OQ P R _ _ 0000 O R LAJ A 100 5 00 10 00 13004040 4 4 13003040 5 o154x 3 NOTES 5 E EA SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD N o T 5 PACKAGE WEIGHT 0 4759 1 JEDEC REFERENCE MO 216 DESIGN 4 6 1 F PACKAGE CODE BBOAC 5 SEATING PLANE po c 3 51 85180 A 0 35 0 06 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05538 Rev 27 of 28 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applicatio
36. ndary Scan Register TMS TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH Vpp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the Page 10 of 28 Feedback SES CYPRESS CYPRESS PERFORM TDI and TDO balls as shown in the Tap Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test data path Bypass Register To save time when serially shiftin
37. ns unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback _ M SS d CYPRESS PERFORM Document History Page CY7C1354C CY7C1356C Document Title CY7C1354C CY7C1356C 9 Mbit 256K x 36 512K x 18 Pipelined SRAM with NoBL Architecture Document Number 38 05538 Orig of REV No Issue Date Change Description of Change is 242032 See ECN RKF New data sheet A 278130 See ECN RKF Changed Boundary Scan order to match the B Rev of these devices Changed TQFP pkg to Lead free TQFP in Ordering Information section Added comment of Lead free BG and BZ packages availability B 284431 See ECN VBL Changed ISB1 and ISB3 from DC Characteristic table as follows ISB1 225 mA gt 130 mA 200 MHz 120 mA 167 MHz 110 mA ISB3 225 MHz 120 mA 200 MHz gt 110 mA 167 MHz gt 100 mA Add BG and BZ pkg lead free part numbers to ordering info section C 320834 See ECN PCI Changed 225 MHz
38. ns are possible with the three bit instruction register All combinations are listed in the Instruction Codes table Three of these instructions are listed as RESERVED and should not be used The other five instruc tions are described in detail below The TAP controller used in this SRAM is not fully compliant to the 1149 1 convention because some of the mandatory 1149 1 instructions are not fully implemented The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I O buffers The SRAM does not implement the 1149 1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE PRELOAD rather it performs a capture of the I O ring when these instructions are executed Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted Document 38 05538 Rev G CY7C1354C CY7C1356C through the instruction register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST EXTEST is a mandatory 1149 1 instruction which is to be executed whenever the instruction register is loaded with all Os EXTEST is not implemented in this SRAM TAP controller and therefore this device is not compliant to 1149 1 The TAP controller does recognize an all 0 instruction When an EXTEST instructi
39. oltage 0 5V to Vpp 0 5V LAbavawhich fie aeui fe maybe dmpsired For aserauides Current into Outputs LOW eene 20 mA lines not tested Static Discharge gt 2001V Storage Temperature 65 to 150 C parE SID ee Meiha amta Ambient Temperature with Latch up gt 200 Power 55 to 125 C Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 4 6V Ambient Supply Voltage on Vppq Relative to GND 0 5V to Vpp Range Temperature Vpp VDDQ DC to Outputs in Tri State 0 5V to 0 5V Commercial 0 C to 70 C 3 3 5 10 2 5V 5 Industrial 40 C to 85 C to Vpp Electrical Characteristics Over the Operating Rangel 151 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ Supply Voltage for 3 3V I O 3 135 V for 2 5V I O 2 375 2 625 V Output HIGH Voltage 3 3V I O 4 0 mA 2 4 V for 2 5V I O 1 0 mA 2 0 V VoL Output LOW Voltage 3 3V I O loj 8 0 mA 0 4 V for 2 5V I O 1 0 mA 0 4 V Vin Input HIGH Voltage for 3 3V I O 2 0 0 3V V for 2 5V I O 1 7 Vpp 0 3V V Vi Input LOW Voltagel 3 3V 0 3 0 8 V for 2 5V I O 0 3 0 7 V Ix
40. on is loaded into the instruction register the SRAM responds as if a SAMPLE PRELOAD instruction has been loaded There is one difference between the two instructions Unlike the SAMPLE PRELOAD instruction EXTEST places the SRAM outputs in a High Z state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state It also places all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and output pins is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capt
41. quired Bidirectional Data I O lines As inputs they feed into on chip data register that is triggered Synchronous by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by addresses during the previous clock rise of the Read cycle The direction of the pins is controlled by OE and the internal control logic When OE is asserted LOW the pins can behave as outputs When HIGH DQ DQ y are placed in a tri state condition The outputs are automat ically tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE Bidirectional Data Parity I O lines Functionally these signals are identical to DQ q During Synchronous write sequences is controlled by BW is controlled by BWp is controlled by BW and DQP is controlled by BW MODE Input Strap Pin Mode Input Selects the burst order of the device Tied HIGH selects the interleaved burst order Pulled LOW selects the linear burst order MODE should not change states during operation When left floating MODE will default HIGH to an interleaved burst order TDO JTAG serial Serial data out to the JTAG circuit Delivers data on the negative edge of TCK output Synchronous TDI JTAG serial input Serial data In to the JTAG circuit Sampled on the rising edge of Synchronous TM
42. re and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2 8 ns 250 MHz device provided OE is active LOW After the first clock of the read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW in order for the device to drive out the requested data During the second clock a subsequent operation Read Write Deselect can be initiated Deselecting the device is also pipelined Therefore when the SRAM is deselected at clock rise by one of the chip enable signals its output will tri state following the next clock rise Document 38 05538 Rev G Burst Read Accesses The CY7C1354C and CY7C1356C have an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be driven LOW in order to load a new address into the SRAM as described in the Single Read Access section above The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both burst counters use AO and A1 in the burst sequence and will wrap around when incremented suffi ciently A HIG
43. standby current ZZ gt 0 2V 50 mA tzzs Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzznEC ZZ recovery time ZZ lt 0 2V 2tcvc ns tzzi ZZ active to sleep current This parameter is sampled 2tcvc ns trzzI ZZ Inactive to exit sleep current This parameter is sampled 0 ns Truth Table 3 4 5 6 7 8 Address Operation Used ZZ ADV LD WE BWx OE CEN CLK DQ Deselect Cycle None HL L X X X L L H Tri State Continue Deselect Cycle None XIL H X X X L L H Tri State Read Cycle Begin Burst External L L L H X L L L H Data Out Q Read Cycle Continue Burst Next XIL H X X L L L H Data Out Q NOP Dummy Read Begin Burst External L L H X H L L H Tri State Dummy Read Continue Burst Next XIL H X X H L L H Tri State Write Cycle Begin Burst External L L L L L X L L H Data In D Write Cycle Continue Burst Next XIL H X L X L L H Data In D Notes 2 X Don t Care H Logic HIGH L Logic LOW CE stands for ALL Chip Enables active BWx L signifies at least one Byte Write Select is active BWx Valid signifies that the desired Byte Write Selects are asserted see Write Cycle Description table for details The DQ and pins are controlled by the current cycle and the OE signal CEN H inserts wait states Document 38 05538 Rev Write is defined by WE and BWy See Write Cycle Description table for details When a write cy
44. to 250 MHz Address expansion pins balls in the pinouts for all packages are modified as per JEDEC standard Unshaded frequencies of 250 200 166 MHz in AC DC Tables and Selection Guide Changed 0 4 and jc for TQFP Package from 25 and 9 C W to 29 41 and 6 13 C W respectively Changed and for BGA Package from 25 and 6 C W to 34 1 and 14 0 C W respectively Changed 0 4 and jc for FBGA Package from 27 and 6 C W to 16 8 and 3 0 C W respectively Modified VoL test conditions Added Lead Free product information Updated Ordering Information Table Changed from Preliminary to Final D 351895 See ECN PCI Changed lag from 35 to 40 mA Updated Ordering Information Table E 377095 See ECN PCI Modified test condition in notes 15 from VDDQ lt to VDDQ lt Vpp 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed three state to tri state Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table G 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on Relative to GND Changed try tr from 25 ns to 20 ns and from 5 ns to 10 ns TAP AC Switching Characteristics table Updated the Ordering Information table Document 38 05538 Re
45. typical to the First Access Read or Write 1 1 1 ms Clock Clock Cycle Time 4 0 5 6 ns Maximum Operating Frequency 250 200 166 MHz tcu Clock HIGH 1 8 2 0 2 4 ns Clock LOW 1 8 2 0 2 4 ns teov OE LOW to Output Valid 2 8 3 2 3 5 ns 2 Clock to 1 2120 21 22 1 25 1 5 1 5 ns Output Times tco Data Output Valid after CLK Rise 2 8 3 2 3 5 ns teov OE LOW to Output Valid 2 8 3 2 3 5 ns Data Output Hold after CLK Rise 1 25 1 5 1 5 ns 2 Clock to 2120 21 22 125 28 1 5 32 1 5 3 5 ns 2 Clock to 1 2120 21 22 1 25 1 5 1 5 ns tEouz OE HIGH to Output 2120 21 22 2 8 3 2 3 5 ns tEoLz OE LOW to Output 21 22 0 0 0 ns Set up Times tas Address Set up before CLK Rise 1 4 1 5 1 5 ns tps Data Input Set up before CLK Rise 1 4 1 5 1 5 ns tcENS CEN Set up before CLK Rise 1 4 1 5 1 5 ns twes WE BW Set up before CLK Rise 1 4 1 5 1 5 ns tats ADV LD Set up before CLK Rise 1 4 1 5 1 5 ns tcEes Chip Select Set up 1 4 1 5 1 5 ns Hold Times Address Hold after CLK Rise 0 4 0 5 0 5 ns 1 Data Input Hold after CLK Rise 0 4 0 5 0 5 ns tcENH CEN Hold after CLK Rise 0 4 0 5 0 5 ns twEH WE BW Hold after CLK Rise 0 4 0 5 0 5 ns ADV LD Hold after CLK Rise 0 4 0 5 0 5 ns Chip Select Hold after CLK Rise 0 4 0 5 0 5 ns Notes 17 This part has a voltage regulator internally is the time power needs to be supplied above Vpp minimum initially before a Read or
46. ure DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture set up plus hold times tcs and tcu The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins Page 11 of 28 Feedback PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a S
47. v G Page 28 of 28 Feedback

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