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Cypress CY7C68013A User's Manual

1. 4 0 8 e0 000000 m E F 4 F E 0000 000 G H H Y 0 50 B 3 50 r 5 004010 p 5 004010 A p 104 SIDE VIEW oo s 0 4 REFERENCE JEDEC MO 195C MI I PACKAGE WEIGHT 0 02 grams FC SEATING PLANE 8 001 03901 B No Q S 5 13 PCB Layout Recommendations Follow these recommendations to ensure reliable high perfor m Bypass and flyback caps on VBus near connector are recom mance 24 mended m Four layer impedance controlled boards are required to m DPLUS and DMINUS trace lengths should be kept to within 2 maintain signal quality mm of each other in length with preferred length of 20 to 30 mm m Specify impedance targets ask your board vendor what they can achieve m Maintain a solid ground plane under the DPLUS and DMINUS traces Do not allow the plane to split under these traces m Do not place vias on the DPLUS or DMINUS trace routing m Isolate the DPLUS and DMINUS traces from all other signal Connections between the USB connector shell and signal traces by no less than 10 mm grou
2. denotes CY7C68015A CY7C68016A pinout denotes programmable polarity 2 U U U U U v v J YeatesRnogs lt n TI m lt zo mz S U Q N uo como R c o o co B PB B B e Ne A 4 Ol NI A 6 1 42 2 41 3 40 4 39 5 CY7C68013A CY7C68014A 38 6 amp 37 CY7C68015A CY7C68016A 7 36 8 56 pin QFN 35 9 34 10 T C327 12 13 30 14 29 amHseBNSSSEBNSNS nn U U 70 U 70 UU U 0 lt Qo DD D Z G Z gt O gt PP ese D O D n m m m mm TI 000 O m O A O N RESET GND PA7 FLAGD SLCS PA6 PKTEND PA5 FIFOADR1 PA4 FIFOADRO PA3 WU2 PA2 SLOE PA1 INT1 33 PAO INTO VCC 31 CTL2 FLAGC CTL1 FLAGB CTLO FLAGA Page 19 of 62 Feedback We CY7C68013A CY7C68014A 97 CYPRESS CY7C68015A CY7C68016A PERFORM Figure 11 CY7C68013A 56 pin VFBGA Pin Assignment Top View Document 38 08032 Rev L Page 20 of 62 Feedback CYPRESS PERFORM CY7C68013A CY7C68014A CY7C68015A CY7C68016A 4 1 CY7C68013A 15A Pin Descriptions The FX2LP Pin Descriptions follows 9 Table 11 FX2LP Pin Descriptions 100 56 56 VF
3. OLV CLKOUT VCC GND RDY0 SLRD RDY1 SLWR RDY2 RDY3 RDY4 RDY5 T2 IFCLK RESERVED BKPT EA SCL SDA OE N3Sd 65 Or ev vv UM 9INI SAd 1 10 44 4104 204 9 X3c1 93d LNOel eAd 8HQavdid9 73 CY7C68013A CY7C68014A 128 pin TQFP 54 19 904 984 104 284 QNO 55 QNO Sv 9r Lv 8r 6r 08 LS os S vs 55 95 29 89 1 011 134 101001 034 6S 91 LL 14 60 4 0104 204 La ea 09 e6da rad PDO FD8 192 WAKEUP VCG RESET CTL5 A3 A2 A1 A0 GND 93 PA7 FLAGD SLCS 22 PA6 PKTEND 2 PA5 FIFOADR1 1 99 PA4 FIFOADR0 PA3 WU2 PA2 SLOE PA1 INT1 PAO INTO VCC GND PC7 GPIFADR7 PC6 GPIFADR6 PC5 GPIFADR5 PC4 GPIFADR4 2761 PC3 GPIFADR3 2751 PC2 GPIFADR2 7 PC1 GPIFADR1 PCO GPIFADRO CTL2 FLAGC CTL1 FLAGB CTLO FLAGA VCC CTL4 87 261 GND
4. tFAH tora FIFOADR t ED tswr twnH gt tow WRH SLWR sLcs Dor EE FLAGS E isrp FDH tros tsrp N N 1 N 2 CD PKTEND The Figure 31 shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchro nizing clock The diagram illustrates a single write followed by burst write of 3 bytes and committing all 4 bytes as a short packet using the PKTEND pin m Att 0 the FIFO address is stable and the signal SLCS is asserted SLCS may be tied low in some applications Note that has a minimum of 25 ns This means when IFCLK is running at 48 MHz the FIFO address setup time is more than one IFCLK cycle m Att 1 the external master peripheral must outputs the data value onto the data bus with a minimum set up time of before the rising edge of IFCLK m Att 2 SLWR is asserted The SLWR must meet the setup time of tswp time from asserting the SLWR signal to the rising edge of IFCLK and maintain a minimum hold time of typ time from the IFCLK edge to the deassertion of the SL WR signal If the SLCS signal is used it must be asserted with SLWR or before SL WR is asserted SLCS and SLWR signals must both be asserted to start a valid write condition m While the SLWR is asserted data is written to the FIFO and on the rising edge o
5. E604 1 FIFORESETITTI Restore FIFOS to default NAKALL 0 0 0 2 1 W state 605 1 Breakpoint Control 0 0 0 0 BREAK BPPULSE 0 00000000 rrrrbbbr E606 1 BPADDRH Breakpoint Address H A15 A14 A13 A12 A11 A10 A9 A8 RW E607 1 BPADDRL Breakpoint Address L 7 A5 A4 A3 A2 A1 RW 608 1 UART230 230 Kbaud internally 0 0 0 0 0 0 230UART1 230UARTO 00000000 rrrrrrbb generated ref clock E609 1 FIFOPINPOLARl Slave FIFO Interface pins 0 0 PKTEND SLOE SLRD SLWR EF FF 00000000 rrbbbbbb polarity E60A 1 REVID Chip Revision rv7 rv5 rv4 rv3 rv2 rvi rv0 00000001 E60B 1 REVCTLITU Chip Revision Control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb UDMA E60C GPIFHOLDAMOUNT MSTB Hold Time 0 0 0 0 0 0 HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb for UDMA 3 reserved ENDPOINT CONFIGURATION E610 EP1OUTCFG Endpoint 1 OUT VALID 0 TYPE1 0 0 0 0 10100000 brbbrrrr Configuration E611 EP1INCFG Endpoint 1 IN VALID 0 TYPE1 TYPEO 0 0 0 0 10100000 brbbrrrr Configuration E612 1 EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPEO SIZE 0 BUF1 BUFO 10100010 bbbbbrbb E613 EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPEO 0 0 0 0 10100000 bbbbrrrr E614 EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPEO SIZE 0 BUF1 BUFO 11100010 bbbbbrbb E615 1 EP8CFG Endpoint 8
6. TQFP Type Default Description 10 9 10 3 20 Power N A Analog VCC Connect this pin to 3 3V power source This signal provides power to the analog section of the chip 17 16 14 7 1D AVCC Power N A Analog VCC Connect this pin to 3 3V power source This signal provides power to the analog section of the chip 13 12 13 6 2F AGND Ground N A Analog Ground Connectto ground with as short a path as possible 20 19 17 10 1 AGND Ground Analog Ground Connectto ground with as short a path as possible 19 18 16 9 1E DMINUS IO Z 2 USB D Signal Connect to the USB D signal 18 17 15 8 2 DPLUS 10 7 2 USB D Signal Connect to the USB D signal 94 A0 Output L 8051 Address Bus This bus is driven at all times 95 A1 Output L When the 8051 is addressing internal RAM it reflects the internal address 96 A2 Output L 97 A3 Output L 117 A4 Output L 118 A5 Output L 119 A6 Output L 120 A7 Output L 126 A8 Output L 127 A9 Output L 128 A10 Output L 21 11 Output L 22 A12 Output L 23 A13 Output L 24 A14 Output L 25 A15 Output L 59 D0 IO Z Z 8051 Data Bus This bidirectional bus is high 60 Di 10 7 7 impedance when inactive input for bus reads and output for bus writes The data bus is used for external 61 D2 10 2 Z 8051 program and data memory The data bus is active 62 D3 10 2 7 only for external bus accesses
7. FLAGS k Table 28 Slave FIFO Asynchronous Packet End Strobe 23 Parameter Description Min Max Unit tPEpwi PKTEND Pulse Width LOW 50 ns tpwpwh PKTEND Pulse Width HIGH 50 ns PKTEND to FLAGS Output Propagation Delay 115 ns Document 38 08032 Rev L Page 47 of 62 Feedback CY7C68013A CY7C68014A CY7C68015A CY7C68016A W CYPRESS PERFORM 10 13 Slave FIFO Output Enable Figure 25 Slave FIFO Output Enable Timing 20 SLOE DATA Table 29 Slave FIFO Output Enable Parameters Parameter Description Min Max Unit toEon SLOE Assert to FIFO DATA Output 10 5 ns loEoff SLOE Deassert to FIFO DATA Hold 10 5 ns 10 14 Slave FIFO Address to Flags Data Figure 26 Slave FIFO Address to Flags Data Timing Diagram 20 FIFOADR 1 0 Y txFLG FLAGS 3 txFD DATA ON Table 30 Slave Address to Flags Data Parameters Parameter Description Min Max Unit txrLG FIFOADR 1 0 to FLAGS Output Propagation Delay 10 7 ns txFD FIFOADR 1 0 to FIFODATA Output Propagation Delay 14 3 ns Page 48 of 62 Feedback Document 38 08032 Rev L CY7C68013A CY7C68014A CY7C68015A CY7C68016A T
8. 19 29 59 v9 denotes programmable polarity Document 38 08032 Rev L Page 16 of 62 Feedback CY7C68013A CY7C68014A LL aee s CYPRESS CY7C68015A CY7C68016A PERFORM Figure 8 CY7C68013A CY7C68014A 100 pin TQFP Pin Assignment OQQ UUUUQUUUUUUUU ZUU T c rFzoggooczmmmmrmmmmos5codco O Zou9gBouioggstkov oogom 2 un nmn lt 9999 ma Ggoo 999 Q G 8 gt cc 5 Ad 1 VCC PDO FD8 80 2 GND WAKEUP 79 3 RDYO SLRD VCC 78 4 RDY1 SLWR RESET 77 5 RDY2 CTL5 76 6 RDY3 GND 75 7 RDY4 PA7 FLAGD SLCS 74 8 RDY5 PA6 PKTEND 73 9 AVCG PA5 FIFOADR1 72 10 XTALOUT PA4 FIFOADRO 71 11 XTALIN PA3 WU2 70 12 AGND PA2 SLOE 69 13 NC PA1 INT1 68 14 NC PAO INTO 15 NC CY7C68013A CY7C68014A VCC 55 16 AVCC 100 GND 5 17 DPLUS PC7 GPIFADR7 64 18 DMINUS PC6 GPIFADR6 63 19 AGND PC5 GPIFADR5 62 20 VCC PC4 GPIFADR4 61 21 GND PC3 GPIFADR3 60 22 INT4 PC2 GPIFADR2 59 23 TO PC1 GPIFADR1 58 24 1 PCO GPIFADRO 57 25 T2 CTL2 FLAGC 26 IFCLK CTL1 FLAGB 55 27 RESERVED CTLO FLAGA 54 28 VCC 53 29
9. ata XXXXXXXX 16 bit mode only E6F1 XGPIFSGLDATLX Read Write GPIF Data L amp D7 D6 D5 D4 D3 D2 D1 DO RW trigger transaction 6 2 XGPIFSGLDATL Read GPIF Data L 07 D6 D5 D4 D3 D2 D1 DO R NOX transaction trigger E6F3 1 GPIFREADYCFG Internal RDY Sync Async INTRDY SAS TCXRDYS 0 0 0 0 0 00000000 bbbrrrrr RDY pin states 6 4 GPIFREADYSTAT Ready Status 0 0 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 00xxxxxx R E6F5 GPIFABORT Abort GPIF Waveforms x x x x x x W E6F6 2 reserved ENDPOINT BUFFERS E740 64 EPOBUF EPO IN OUT buffer D7 D6 D5 D4 D3 D2 D1 DO RW E780 64 EP10UTBUF EP1 OUT buffer D7 D6 D5 D4 D3 D2 D1 DO RW E7C0 64 EP1INBUF EP1 IN buffer D7 D6 D5 D4 D3 D2 D1 DO RW E800 2048 RW F000 1024 EP2FIFOBUF 512 1024 byte EP 2 slave D7 D6 D5 D4 D3 D2 00 RW FIFO IN OUT F400 512 EP4FIFOBUF 512 byte 4 slave FIFO D7 D6 D5 D4 D3 D2 D1 DO XXXXXXXX RW buffer IN or OUT F600 512 reserved F800 1024 EP6FIFOBUF 512 1024 byte 6 slave D7 D6 D5 D4 D3 D2 D1 DO RW FIFO buffer IN or OUT 00 512 EP8FIFOBUF 512byte EP 8 slave FIFO D7 D6 05 04 03 02 D1 DO RW buffer IN or OUT 00 512 reserved Document 38 08032 Rev
10. Table 18 GPIF Synchronous Signals Parameters with Internally Sourced IFCLK2 21 Parameter Description Min Max Unit tlECLK IFCLK Period 20 83 ns lsRY RDYy to Clock Setup Time 8 9 ns Clock to RDYx 0 ns tsap GPIF Data to Clock Setup Time 9 2 ns GPIF Data Hold Time 0 ns tsaa Clock to GPIF Address Propagation Delay 7 5 ns txap Clock to GPIF Data Output Propagation Delay 11 ns Clock to CTL Output Propagation Delay 6 7 ns Table 19 GPIF Synchronous Signals Parameters with Externally Sourced IFCLKP Parameter Description Min Max Unit IFCLK Period 20 83 200 ns tsRy RDYx to Clock Setup Time 2 9 ns tRYH Clock to RDYx 3 7 ns GPIF Data to Clock Setup Time 3 2 ns tpaH GPIF Data Hold Time 4 5 ns tsa Clock to GPIF Address Propagation Delay 11 5 ns Clock to GPIF Data Output Propagation Delay 15 ns Clock to Output Propagation Delay 10 7 ns Notes 20 Dashed lines denote signals with programmable polarity 21 GPIF asynchronous RDY signals have a minimum Setup time of 50 ns when using internal 48 MHz IFCLK 22 IFCLK must not exceed 48 MHz Document 38 08032 Rev L Page 42 of 62 Feedback lt _ SJ CYPRESS PERFORM 10 7 Slave FIFO Synchronous Read Figure 18 Slave FIFO Synchronous Read Timing Diagram CY7C68013A CY7C68014A CY7C68015A CY7C68016A DATA
11. 0 3010 012 zi Li 0 500020 0 60 0 024 SEATING PLANE 0 50 0 020 6 45 0 254 6 55 0 258 NOTES 1 HATCH AREA IS SOLDERABLE EXPOSED METAL 2 REFERENCE JEDEC MO 220 3 PACKAGE WEIGHT 0 162g 4 ALL DIMENSIONS ARE IN MM MIN MAX 5 PACKAGE CODE PART DESCRIPTION LF56 STANDARD SUBCON PUNCH TYPE PKG with 6 1 x 6 1 EPAD LY56 PB FREE 51 85144 0 Document 38 08032 Rev L Page 56 of 62 Feedback CY7C68013A CY7C68014A CY7C68015A CY7C68016A JC Ypnrss PERFORM Package Diagrams continued Figure 37 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm A100RA 51 85050 16 00 0 20 14 00 0 10 1 40 0 05 100 81 1 80 0 30 0 08 V eo eo 4 8 8 N e 0 65 12 1 DETAIL 8 Eg 31 50 0 20 MAX 1 60 R 0 08 MIN 0 20 MAX 0 MIN 2 SEATING PLANE STAND OFF 0 55 5 0 05 MIN 0 15 GAUGE PLANE 1 JEDEC STD REF 5 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH Y S008 HN MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 E ODD MAN BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 51 85050 B
12. RW Note 13 SFRs not part of the standard 8051 architecture 14 If no EEPROM is detected by the SIE then the default is 00000000 Document 38 08032 Rev L Page 34 of 62 Feedback 1 253 gt Y CYPRESS PERFORM Table 12 FX2LP Register Summary continued CY7C68013A CY7C68014A CY7C68015A CY7C68016A Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 50 Default 1 Data L w Trigger 07 D6 D5 D4 D3 D2 D1 D0 RW 1 GPIFSGLDATL GPIF Data L w No TriggeD7 D6 05 04 03 02 D1 DO co 1 Serial Port 1 Control bit SMO 1 SM1 1 SM2 1 REN 1 TB8 1 RB8 1 TI 1 RI 1 00000000 RW addressable 1 Serial 1 Data Buffer 07 06 05 04 03 02 01 00 00000000 2 16 reserved C8 T2CON Timer Counter 2 Control TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 00000000 bit addressable C9 reserved CA RCAP2L Capture for Timer 2 07 D6 D5 D4 D3 D2 D1 DO 00000000 to reload up counter CB 1 2 Capture for Timer 2 au 07 06 05 04 03 02 01 DO 00000000 RW to reload up counter CC TL2 Timer 2 reload L D7 D6 D5 04 03 02 01 DO 00000000 RW CD TH2 Timer 2 reload H D15 D14 D13 D12 D11 D10 D9 D8 00
13. E6C8 FLOWEQOCTL CTL Pin States in CTLOE3 CTLOE2 CTLOE1 CTLOEO CTL3 CTL2 CTL1 CTLO 00000000 Flowstate CTL4 when Logic 0 E6C9 FLOWEQ1CTL CTL Pin States in Flow CTLOE3 CTL0E2 CTLOE1 CTLOEO CTL3 CTL2 CTL1 CTLO 00000000 state when Logic 1 CTL5 CTL4 6 FLOWHOLDOFF Holdoff Configuration HOPERIOD3 HOPERIOD2HOPERIOD 1 HOPERIOD HOSTATE HOCTL2 HOCTL1 HOCTLO 00010010 0 Document 38 08032 Rev L Page 32 of 62 Feedback CY7C68013A CY7C68014A W CYPRESS CY7C68015A CY7C68016A PERFORM Table 12 FX2LP Register Summary continued Hex Size Description b7 56 b5 b4 b3 b2 b1 50 Default 55 6 1 FLOWSTB Strobe SLAVE RDYASYNC CTLTOGL SUSTAIN 0 MSTB2 MSTB1 MSTB0 00100000 onfiguration 6 011 FLOWSTBEDGE Flowstate Rising Falling 0 0 0 0 0 0 FALLING RISING 00000001 rrrrrrbb Edge Configuration E6CD 1 FLOWSTBPERIOD Master Strobe Half Period D7 D6 05 04 03 02 D1 DO 00000010RW E6CE 1 GPIFTCB3I GFIF Transaction Count 1 TC30 TC29 TC28 TC27 TC26 TC25 TC24 00000000 E6CF 1 GPIFTCB2I GPIF Transaction Count TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16 00000000 RW Byte 2 E6DO 1 GPIFTCB1IT GPIF Transaction Count 15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 00000000 1 E6D1 1 GPIF Transaction Count TC7 TC6 TC5 TC4 TC2 TC1 TCO 00000001 RW Byte 0 2
14. bit addressable A9 1 reserved 1 2468 Enapoint 2 4 6 8 status EP8F EP8E EP6F EP6E EP4F EP4E EP2F EP2E 01011010R ags AB R524FIFOFLGS Endpoint 2 4 slave FIFO 0 EP4PF EP4EF EP4FF 0 EP2PF EP2EF EP2FF 00100010R status flags AC 1 RB68FIFOFLGS Endpoint 6 8 slave FIFO 0 EP8PF EP8EF EP8FF 0 EP6PF EP6EF EP6FF 011001101 status flags AD 2 reserved AF 1 Autopointer 182 setup 0 0 0 0 APTR2INC APTR1INC 00000110 BO IODIT3 Port D bit addressable D7 D6 D5 D4 D3 D2 D 00 RW 1 1 Port E D7 D6 D5 D4 D3 D2 D D0 RW NOT bit addressable B2 OEA Port A Output Enable D7 D6 05 04 03 02 00 00000000 B3 1 Port B Output Enable D7 D6 05 04 03 02 DO 00000000 4 1 1 Port Output Enable D7 D6 D5 D4 D3 D2 01 00 00000000 5 1 Port D Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 B6 OEE Port E Output Enable D7 D6 05 04 03 02 00 00000000 B7 reserved B8 IP nterrupt Priority bit ad 1 PS1 PT2 PSO PT1 PX1 PTO 10000000 dressable B9 reserved BA 1 Endpoint 0 amp 1 Status 0 0 0 0 0 EP1INBSY FPIOUTBS EPOBSY 00000000 R BB GPiFTRIGUS 11 Endpoint 2 4 6 8 GPIF DONE 0 0 0 0 RW EP1 EPO 10000xxx brrrrbbb slave FIFO Trigger BC reserved BD GPIFSGLDATH SI Data 16 bit mode D15 014 013 012 011 010 09 08
15. CYPRESS PERFORM 10 15 Slave FIFO Synchronous Address Figure 27 Slave FIFO Synchronous Address Timing Diagram 2 IFCLK SLCS FIFOADR 1 0 1 1 isrA Table 31 Slave FIFO Synchronous Address Parameters 21 Parameter Description Min Max Unit tlECLK Interface Clock Period 20 83 200 ns FIFOADR 1 0 to Clock Setup Time 25 ns Clock to FIFOADR 1 0 Time 10 ns 10 16 Slave FIFO Asynchronous Address Figure 28 Slave FIFO Asynchronous Address Timing Diagram SLCS FIFOADR 1 0 x 1 NEN tran SLRD SLWR PKTEND Table 32 Slave FIFO Asynchronous Address Parameters Parameter Description Min Max Unit FIFOADR 1 0 to SLRD SLWR PKTEND Setup Time 10 ns RD WR PKTEND to FIFOADR 1 0 Hold Time 10 ns Document 38 08032 Rev L Page 49 of 62 Feedback 10 17 Sequence Diagram 10 17 1 Single and Burst Synchronous Read Example Figure 29 Slave FIFO Synchronous Read Sequence and Timing Diagram tiFcLK CY7C68013A CY7C68014A CY7C68015A CY7C68016A 20 amp n Po Y 15 t tsFA t j FAH FAH FIFOADR SLRD sLcs FLAGS DATA SLOE Figure 30 Slave FIFO Synchronous Sequence of Events Diagram AIFCLK AIFCLK IFCLK AIFCLK IFCLK AIFCL
16. 1 INTO PA0 INT0 IFCLK INT14 PA1 INT1 PA1 INT1 PA1 CLKOUT PA2 PA2 lt SLOE WU2 PA3 WU2 PA3 WU2 PA3 DPLUS 4 4 lt FIFOADRO DMINUS lt FIFOADR1 4 7 7 PA7 FLAGD SLCS CTL3 gt CTL4 gt 15 lt RDY2 lt RDY3 lt RDY4 100 lt RDY5 PORTC7 GPIFADR7 PORTC6 GPIFADR6 PORTC5 GPIFADR5 uuum PORTC2 GPIFADR2 4 PORTC1 GPIFADR1 PORTCO GPIFADRO TE EM PE7 GPIFADR8 PE6 T2EX T2 6 Ti amp PE4 RxD1OUT TO lt _ PE3 RxDOOUT 2 200 PE1 T1OUT PEO TOOUT WR D7 58 9 06 OE a B po A15 A14 00 A13 A12 gt A10 128 A9 A8 A7 A p EA A3 A2 A0 Page 15 of 62 Feedback s 2 CY7C68013A CY7C68014A CYPRESS PERFORM CY7C68015A CY7C68016A Figure 7 CY7C68013A CY7C68014A 128 pin TQFP Pin Assignment 821 181 A HIE 03 Go N
17. programmable 0 4 GPIF gt to ASIC DSP or bus 16 DYE standards such as 0 4 Smart RAM 5 6 ATAPI EPP etc USB lt Integrated 1 1 2 0 full speed and Engine Up to 96 MBytes igh p to ytes s high speed 4kB 816 burst rate XCVR FIFO Enhanced USB core Simplifies 8051 code 1 1 Features CY7C68013A 14A only m CY7C68014A Ideal for battery powered applications Suspend current 100 uA typ m CY7C68013A Ideal for non battery powered applications Suspend current 300 uA typ m Available in five lead free packages with up to 40 GPIOs 128 pin TQFP 40 GPIOs 100 pin TQFP 40 GPIOs 56 pin QFN 24 GPIOS 56 SSOP 24 GPIOS and 56 pin VF 24 GPIOs 1 2 Features CY7C68015A 16A only m CY7C68016A Ideal for battery powered applications Suspend current 100 uA typ m CY7C68015A Ideal for non battery powered applications Suspend current 300 uA typ m Available in lead free 56 pin QFN package 26 GPIOs 2 more GPIOs than CY7C68013A 14A enabling additional features in same footprint Cypress Semiconductor Corporation s Cypress s EZ USB FX2LP CY7C68013A 14A is a low power version of the EZ USB FX2 CY7C68013 which is a highly integrated low power USB 2 0 microcontroller By integrating the USB 2 0 trans ceiver serial interface engine SIE enhanced 8051 microcon troller and a programmable peripheral
18. 1 24 MHz tay tpsu 106 ns tacc1 48 MHz tay tps 43 ns Document 38 08032 Rev L Page 38 of 62 Feedback CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A PERFORM 10 3 Data Memory Read Figure 13 Data Memory Read Timing Diagram teL Stretch 0 CLKOUT 7 tav tav 15 0 tsTBL 5 RD tscsL CS tsoEL OE 19 tosu 1 lt lt ton data in D 7 0 Stretch 1 CLKOUT 71 A 15 0 RD tpsu 19 pit lt ton Br Table 16 Data Memory Read Parameters Parameter Description Min Typ Max Unit Notes tcL 1 CLKOUT Frequency 20 83 ns 48 MHz 41 66 ns 24 MHz 83 2 ns 12 MHz tay Delay from Clock to Valid Address 10 7 ns tsTBL Clock to RD LOW 11 ns tsTBH Clock to RD HIGH 11 ns Clock to CS LOW 13 ns teoEL Clock to OE LOW 11 1 ns tpsu Data Setup to Clock 9 6 ns toy Data Hold Time 0 ns When using the AUTPOPTR1 or AUTOPTR2 to address external memory the address of AUTOPTR1 is only active while either RD or WR are active The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for
19. 0 20 MIN 1 00 REF DETAIL Document 38 08032 Rev L Page 57 of 62 Feedback CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A PERFORM Package Diagrams continued Figure 38 128 Lead Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm A128 51 85101 1 1 40 0 05 16 00 0 20 14 00 0 10 128 F 0 22 0 05 20 00 0 10 e 8 I N N SEE DETAIL A 0 50 TYP 0 20 MAX 1 60 MAX R 0 08 MIN 0 20 MIN g S STAND OFE SEATING PLANE 0 0 05 MIN NOTE 1 0 15 1 JEDEC STD REF MS 026 GAUGE PLANE 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH qp i MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE R 0 08 MIN BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 20 MAX 3 DIMENSIONS IN MILLIMETERS 51 85101 C 0 60 0 15 H 020 MIN 1 00 REF DETAIL Document 38 08032 Rev L Page 58 of 62 Feedback E CY7C68013A CY7C68014A UJ CYPRESS CY7C68015A CY7C68016A Package Diagrams continued Figure 39 56 VFBGA 5 x 5 x 1 0 mm 0 50 Pitch 0 30 Ball BZ56 001 03901 TOP VIEW BOTTOM VIEW 005 M C Y 5 CORNER PIN A1 CORNER 60 30 0 05 56 12345668 87654321
20. 4 a nene 0 5V to VCC 0 5V Power DISSIDAIIO M63 ER 300 mW Static Discharge Voltage 2 gt 2000V Max Output Current per IO pott 10 mA Max Output Current all five IO ports 128 and 100 pin 50 mA 7 Operating Conditions Ambient Temperature Under Bias Commesrcial neret 0 C to 70 C Ambient Temperature Under Bias 40 to 105 S pply 3 00V to 3 60V Ground oV Fosc Oscillator or Crystal en nnns 24 MHz 100 ppm Parallel Resonant 8 Thermal Characteristics The following table displays the thermal characteristics of various packages Table 13 Thermal Characteristics T D 7 Junction to Case Case to Ambient unction to Ambient Temperature Package Ambient Temperature Temperature Temperature Jc 0 C W C W C W 56 SSOP 70 24 4 23 3 47 7 100 TQFP 70 11 9 34 0 45 9 128 TQFP 70 15 5 27 7 43 2 56 QFN 70 10 6 14 6 25 2 56 VFBGA 70 30 9 27 7 58 6 The Junction Temperature can be calculated using the followin
21. SLOE toron lt gt toEort 204 Table 20 Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLKP Parameter Description Min Max Unit IFCLK Period 20 83 ns SLRD to Clock Setup Time 18 7 ns Clock to SLRD Hold Time 0 ns loEon SLOE Turn on to FIFO Data Valid 10 5 ns toEott SLOE Turn off to FIFO Data Hold 10 5 ns txFLG Clock to FLAGS Output Propagation Delay 9 5 ns Clock to FIFO Data Output Propagation Delay 11 ns Table 21 Slave FIFO Synchronous Read Parameters with Externally Sourced Parameter Description Min Max Unit IFCLK Period 20 83 200 ns SLRD to Setup Time 12 7 ns Clock to SLRD Hold Time 3 7 ns loEon SLOE Turn on to FIFO Data Valid 10 5 ns toEot SLOE Turn off to FIFO Data Hold 10 5 ns txFLG Clock to FLAGS Output Propagation Delay 13 5 ns txFD Clock to FIFO Data Output Propagation Delay 15 ns Document 38 08032 Rev L Page 43 of 62 Feedback 10 8 Slave FIFO Asynchronous Read Figure 19 Slave FIFO Asynchronous Read Timing Diagram CY7C68013A CY7C68014A CY7C68015A CY7C68016A tRDpwh SLRD 4 i RDpwl gt txFLG FLAGS P N Li SLOE N Table 22 Slave FIFO A
22. 10 pF 0 0 15 Isusp Suspend Current Connected 300 380081 uA CY7C68014 CY7C68016 Disconnected 100 150091 Suspend Current Connected 0 5 1 216 CY7C68013 CY7C68015 Disconnected 0 3 1 0176 mA lec Supply Current 8051 running connected to USB HS 50 85 mA 8051 running connected to USB FS 35 65 mA TRESET Reset Time after Valid Power VCC min 3 0V 5 0 ms Pin Reset after powered on 200 us Page 37 of 62 Feedback a CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A PERFORM 10 2 Program Memory Read Figure 12 Program Memory Read Timing Diagram teL a CLKOUT 71 Ln tav tav 15 0 lt gt PSEN 18 t D 7 0 tacci pH data in OE gt CS N Table 15 Program Memory Read Parameters Parameter Description Min Typ Max Unit Notes tcL 1 CLKOUT Frequency 20 83 ns 48 MHz 41 66 ns 24 MHz 83 2 ns 12 MHz tay Delay from Clock to Valid Address 0 10 7 ns tsTBL Clock to PSEN Low 0 8 ns tsTBH Clock to PSEN High 0 8 ns tsoEL Clock to OE Low 11 1 ns Clock to CS Low 13 ns tpsu Data Setup to Clock 9 6 ns toy Data Hold Time 0 ns Notes 17 CLKOUT is shown with positive polarity 18 tacc1 is computed from the above parameters as follows
23. Multiplexed pin whose function is selected by the following bits IFCONFIG 1 0 PB1 is a bidirectional IO port pin FD 1 is the bidirectional FIFO GPIF data bus 46 36 27 20 4 2 FD 2 IO Z PB2 Multiplexed pin whose function is selected by the following bits IFCONFIG 1 0 2 is a bidirectional IO port pin FD 2 is the bidirectional FIFO GPIF data bus 47 37 28 21 4G FD 3 IO Z PB3 Multiplexed pin whose function is selected by the following bits IFCONFIG 1 0 PB3 is a bidirectional IO port pin FD 3 is the bidirectional FIFO GPIF data bus 54 44 29 22 5H PB4 or FD 4 IO Z PB4 Multiplexed pin whose function is selected by the following bits IFCONFIG 1 0 4 is a bidirectional IO port pin FD 4 is the bidirectional FIFO GPIF data bus Document 38 08032 Rev L Page 23 of 62 Feedback gt CYPRESS PERFORM CY7C68013A CY7C68014A CY7C68015A CY7C68016A Table 11 FX2LP Pin Descriptions continued 100 56 56 VF TOFP TQFP Default Description 55 45 30 23 5G 5 10 7 Multiplexed whose function is selected by the FD 5 PB5 following bits IFCONFIG 1 0 PB5 is a bidirectional IO port pin FD 5 is the bidirectional FIFO GPIF data
24. to populate RAM data memory Data here RD WR RD WR strobes are not active 0000 Data Code SUDPTR USB upload download 1 C interface boot access 3 11 Register Addresses 4 KBytes EP2 EP8 buffers 8 x 512 F000 EFFF 2 KBytes RESERVED E800 E7FF 7 64 Bytes EP1IN E7BF E780 64 Bytes 1 E77F E740 64 Bytes EPO IN OUT E7SF E700 64 Bytes RESERVED 8051 Addressable Registers 512 E500 4 E480 Reserved 128 47 128 bytes GPIF Waveforms 400 Reserved 512 200 1 512 bytes 8051 xdata RAM E000 Document 38 08032 Rev L Page 9 of 62 Feedback EE xS CYPRESS PERFORM 3 12 Endpoint RAM 3 12 1 Size m 3x 64 bytes m 8 x 512 bytes Endpoints 0 and 1 Endpoints 2 4 6 8 3 12 2 Organization m EPO m Bidirectional endpoint zero 64 byte buffer m EP1IN 1 m 64 byte buffers bulk or interrupt m EP2 4 6 8 m Eight 512 byte buffers bulk interrupt or isochronous EP4 and EP8 can be double buffered EP2 and 6 can be either double triple or quad buffered For high speed endpoint configuration options see Figure 5 CY7C68013A CY7C68014A CY7C68015A CY7C68016A 3 12 3 Setup Data Buffer A separate 8 byte buffer at OxE6B8 O0xE6BF holds the setup data from a CONTROL transfer 3 12 4 Endpoint Configurations High speed Mode Endpoints 0 and 1 are the same for every config
25. 58 RD WR 128 package adds the 8051 address and data buses plus control signals Note that two of the required signals RD and WR8 are present in the 100 pin version In the 100 pin and 128 pin versions an 8051 control bit can be set to pulse the RD and WR pins when the 8051 reads from writes to PORTC This feature is enabled by setting PORTCSTB bit in CPUCS register Section 10 5 displays the timing diagram of the read and write strobing function on accessing PORTC Page 14 of 62 Feedback CYPRESS PERFORM Document 38 08032 Rev L Figure 6 Signal CY7C68013A CY7C68014A CY7C68015A CY7C68016A Port GPIF Master Slave FIFO PD7 FD 15 FD 15 PD6 e FD 14 lt FD 14 PD5 e FD 13 FD 13 PD4 FD 12 lt gt FD 12 FD 11 FD 11 PD2 FD 10 lt gt FD 10 PD1 FD 9 lt gt FD 9 PDO 9 FD 8 FD 8 7 FD 7 PB6 FD 6 e FD 6 lt gt FD 5 FD 5 ALOLT PB4 gt FD 4 lt gt 4 BE ETE 9 FD 3 lt FD 3 WAKELP PB2 FD 2 lt gt FD 2 PB1 FD 1 lt gt FD 1 SCL 56 lt gt FD 0 lt gt FD 0 SDA RDY0 lt SLRD Res ete Eds RDY1 SLWR PEO replaces IFCLK d amp PE1 replaces CLKOUT CTLO gt FLAGA CY7C68015AA46A CTL1 gt FLAGB 0 CTL2 1
26. WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 08032 Rev L Revised February 8 2008 Page 62 of 62 Purchase of C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an system provided that the system conforms to the 2 Standard Specification as defined by Philips EZ USB FX2LP EZ USB FX2 and ReNumeration are trademarks and EZ USB is a registered trademark of Cypress Semiconductor Corporation All product and company names mentioned in this document are the trademarks of their respective holders Feedback
27. m Four programmable BULK INTERRUPT ISOCHRONOUS m Integrated 2 controller runs at 100 or 400 kHz endpoints m Four integrated FIFOs Integrated glue logic and FIFOs lower system cost Automatic conversion to and from 16 bit buses Master or slave operation m 8 bit or 16 bit external data interface Uses external clock or asynchronous strobes Easy interface to ASIC and DSP ICs m Available in Commercial and Industrial temperature grade all packages except VFBGA Buffering options double triple and quad m Additional programmable BULK INTERRUPT 64 byte endpoint m Smart Media Standard ECC generation Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document 38 08032 Rev L Revised February 8 2008 Feedback CYPRESS PERFORM Logic Block Diagram High performance micro CY7C68013A CY7C68014A CY7C68015A CY7C68016A 24 MHz using standard tools Ext with lower power options FX2LP amp c T 5 a E 10 5 vec x20 8051 PLL 12 24 48 MHz 69 1 four clocks cycle E Additional 10s 24 Abundant IO 1 5k E including two USARTS connected for u ADDR 9 ble IF
28. which is based on the stretch value Note 19 1 and t are computed from the above parameters as follows MHZ tay tpsu 106 ns tacce 48 MHz 3 toL tav E tpsu 43 5 tacca 24 MHz 5 tcL tay tpsu 190 ns tacc3 48 MHz 5 tay tpsu 86 ns Document 38 08032 Rev L Page 39 of 62 Feedback CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A PERFORM 10 4 Data Memory Write Figure 14 Data Memory Write Timing Diagram teL oo CLKOUT t PES AV tsTBL lt tsTBH tav A 15 0 A WR T t toFF1 D 7 0 data out teL Stretch 1 CLKOUT tav A 15 0 WR CS t 1 D 7 0 data out Table 17 Data Memory Write Parameters Parameter Description Min Max Unit Notes tay Delay from Clock to Valid Address 0 10 7 ns Clock to WR Pulse LOW 0 11 2 ns tsTBH Clock to WR Pulse HIGH 0 11 2 ns Clock to CS Pulse LOW 13 0 ns loN1 Clock to Data Turn on 0 13 1 ns torri Clock to Data Hold Time 13 1 ns When using the AUTPOPTR1 AUTOPTR2 to address external memory the address of 1 is only active while either RD or WR are active The address of AU
29. 0 0 10 9 8 00000 RW E691 EP2BCLTITI Endpoint 2 Byte Count L BC7 SKIP BC6 5 BC4 BC3 BC2 BC1 BC0 IRW E692 2 reserved E694 EP4BCH Endpoint 4 Byte Count H 0 0 0 0 0 0 9 BC8 000000xx RW E695 1 EP4BCLITTI Endpoint 4 Byte Count L BC7 SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 IRW E696 2 reserved E698 EP6BCH Endpoint 6 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 00000xxx RW E699 6 Endpoint 6 Byte Count L 7 5 6 5 4 BC3 BC2 1 RW E69A 2 reserved E69C 1 8 Endpoint 8 Byte Count H 0 0 0 0 0 0 BC9 BC8 000000xx RW Page 31 of 62 Feedback CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A PERFORM Table 12 FX2LP Register Summary continued Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 50 Default E69D 1 EP8BCLTTTI Endpoint 8 Byte Count L BC7 SKIP BC6 BC5 BC4 BC3 BC2 BC1 BCO RW 2 reserved E6A0 1 5 0 Control 0 0 0 0 0 BUSY STALL 10000000 bbbbbbrb atus E6A1 1 5 Endpoint 1 OUT Control 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb and Status E6A2 EP1INCS Endpoint 1 IN Control and 0 0 0 0
30. 0 0 0 4K 24LC32 0 0 1 8K 24LC64 0 0 1 16K 24LC128 0 0 1 Table 9 Part Number Conversion Table CY7C68013A CY7C68014A CY7C68015A CY7C68016A 3 18 2 PC Interface Boot Load Access At power on reset the 2 interface boot loader loads the VID PID DID configuration bytes and up to 16 KBytes of program data The available RAM spaces are 16 KBytes from 0x0000 0x3FFF and 512 bytes from 0xE000 0xE1FF The 8051 is in reset interface boot loads only occur after power on reset 3 18 3 Interface General Purpose Access The 8051 can control peripherals connected to the bus using the and I2DAT registers FX2LP provides 2 master control only it is never an 12 slave 3 19 Compatible with Previous Generation EZ USB FX2 The EZ USB FX2LP is form fit and with minor exceptions functionally compatible with its predecessor the EZ USB 2 This makes for an easy transition for designers wanting to upgrade their systems from the FX2 to the FX2LP The pinout and package selection are identical and a vast majority of firmware previously developed for the FX2 functions in the FX2LP For designers migrating from the FX2 to the FX2LP a change in the bill of material and review of the memory allocation due to increased internal memory is required For more information about migrating from EZ USB FX2 to EZ USB FX2LP see the application note titled Migrating from EZ USB FX2 to EZ USB FX2LP av
31. 0 0 BUSY STALL 00000000 bbbbbbrb Status E6A3 EP2CS Endpoint 2 Control and 0 NPAK2 NPAK1 NPAKO FULL EMPTY 0 STALL 00101000 rrrrrrrb Status E6A4 EP4CS Endpoint 4 Control 0 0 NPAK1 NPAKO FULL EMPTY 0 STALL 00101000 rrrrrrrb Status E6A5 EP6CS ae 6 Control and 10 NPAK2 NPAK1 FULL EMPTY 0 STALL 00000100 rrrrrrrb atus E6A6 EP8CS Endpoint 8 Control and 0 0 NPAK1 NPAKO FULL EMPTY 0 STALL 00000100 rrrrrrrb Status E6A7 EP2FIFOFLGS Endpoint 2 slave 0 0 0 0 0 PF EF FF 00000010R Flags E6A8 EP4FIFOFLGS Endpoint 4 slave FIFO 0 0 0 0 0 PF EF 00000010 Flags E6A9 EP6FIFOFLGS Endpoint 6 slave 0 0 0 0 0 PF EF FF 00000110 Flags EP8FIFOFLGS Endpoint 8 slave 0 0 0 0 0 00000110 Flags E6AB EP2FIFOBCH Endpoint 2 slave FIFO 0 0 0 BC12 BC11 BC10 BC9 BC8 00000000 R total byte count H E6AC EP2FIFOBCL Endpoint 2 slave FIFO 7 BC6 BC5 BC4 BC3 BC2 BC1 BCO 00000000 R total byte count L E6AD EP4FIFOBCH Endpoint 4 slave FIFO 0 0 0 0 0 BC10 BC9 BC8 00000000 R total byte count H E6AE EP4FIFOBCL Endpoint 4 slave 7 BC6 5 BC3 BC2 BC1 BCO 00000000 R total byte count L E6AF EP6FIFOBCH Endpoint 6 slave FIFO 0 0 0 0 BC11 BC10 BC9 BC8 00000000 R total byte count H E6BO EP6FIFOBCL Endpoint 6 slave FIFO 7 BC6 5 BC4 BC3 BC2 BC1 BCO 00000000 R total byte count L E6B1 1 EP8FIFOBCH Endpoint 8 slave FIFO 0 0 0 0 0 BC10 BC9 BC8 00000000 R total byte count H
32. 0 PFC9 IN PKTS 2 00001000 bbbbbrbb ES Programmable Flag H OUT PFC8 635 1 EPeFIFOPFLITTI Endpoint 6 slave 7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFCO 00000000 RW H S Programmable Flag L E635 1 EPeFIFOPFLTTI Endpoint 6 slave FIFO IN PKTS 1 IN PKTS 0 PFC5 PFC4 2 1 00000000 RW F Programmable Flag L OUT PFC7 OUT PFC6 636 1 Endpoint 8 slave DECIS PKTSTAT 0 PKTS 1 JIN 0 0 0 8 00001000 bbrbbrrb 5 Programmable Flag OUT PFC10 OUT PFC9 636 1 Endpoint 8 slave FIFO DECIS PKTSTAT 0 OUT PFC10 OUT PFC9 0 0 PFC8 00001000 bbrbbrrb ES Programmable Flag H E637 1 EP8FIFOPFLITTI Endpoint 8 slave 7 PFC6 PFC5 4 PFC2 PFC1 PFCO 00000000 RW H S Programmable Flag L E637 1 8 Endpoint 8 slave IN PKTS 1 JIN PKTS 0 PFC5 2 1 00000000 Programmable Flag L OUT PFC7 OUT PFC6 8 reserved E640 1 EP2ISOINPKTS 2 if ISO IN Packets AADJ 0 0 0 INPPF1 INPPF0 00000001 brrrrrob per frame 1 3 E641 1 EP4ISOINPKTS EP4 if ISO IN Packets AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrrr per frame 1 3 E642 1 EP6ISOINPKTS EP6 if ISO IN Packets AADJ 0 0 0 0 0 INPPF1 INPPFO 00000001 brrrrrbb per frame 1 3 E643 1 EP8ISOINPKTS EP8 if ISO IN Packets AADJ 0 0 0 0 0 INPPF1 INPPFO
33. 2 of 62 Feedback 2 Applications m Portable video recorder m MPEG TV conversion m DSL modems m ATA interface m Memory card readers m Legacy conversion devices m Cameras m Scanners m Home PNA m Wireless LAN m MP3 players m Networking The Reference Designs section of the Cypress web site provides additional tools for typical USB 2 0 applications Each reference design comes complete with firmware source and object code schematics and documentation Visit the Cypress web site for more information 3 Functional Overview 3 1 USB Signaling Speed FX2LP operates at two of the three rates defined in the USB Specification Revision 2 0 dated April 27 2000 m Full speed with a signaling bit rate of 12 Mbps m High speed with a signaling bit rate of 480 Mbps FX2LP does not support the low speed signaling mode of 1 5 Mbps 3 2 8051 Microprocessor The 8051 microprocessor embedded in the FX2LP family has 256 bytes of register RAM an expanded interrupt system three timer counters and two USARTs 3 2 1 8051 Clock Frequency FX2LP has an on chip oscillator circuit that uses an external 24 MHz 100 ppm crystal with the following characteristics m Parallel resonant m Fundamental mode m 500 uW drive level m 12 pF 5 tolerance load capacitors An on chip PLL multiplies the 24 MHz oscillator up to 480 MHz as required by the transceiver PHY and internal counters divide it down for use as the 8051
34. 3 9 Reset and Wakeup on page 6 for more details External Access This pin determines where the 8051 fetches code between addresses 0x0000 and Ox3FFF 0 the 8051 fetches this code from its internal RAM IF 1 the 8051 fetches this code from external memory 12 5 XTALIN Input N A Crystal Input Connect this signal to a 24 MHz parallel resonant fundamental mode crystal and load capacitor to GND It is also correct to drive XTALIN with an external 24 MHz square wave derived from another clock source When driving from an external source the driving signal should be a 3 3V square wave 10 2 XTALOUT Output N A Crystal Output Connect this signal to a 24 MHz parallel resonant fundamental mode crystal and load capacitor to GND an external clock is used to drive XTALIN leave this pin open Port A 100 2B CLKOUT on CY7C68013A and CY7C68014A PE1 on CY7C68015A and CY7C68016A O Z 12 MHz CLKOUT 12 24 or 48 MHz clock phase locked to the 24 MHz input clock The 8051 defaults to 12 MHz operation The 8051 may three state this output by setting CPUCS 1 1 PE1 is a bidirectional IO port pin 82 83 67 68 40 33 41 34 8G eG PAO or INT0 PA1 or INT1 IO Z IO Z PA0 PA1 Multiplexed pin whose function is selected by 0 bidirectional IO port INTO is the active LOW 8051 INT
35. 3 Nine GPIF Address OUT Signals Nine GPIF address lines are available in the 100 pin and 128 pin packages GPIFADR 8 0 The GPIF address lines enable indexing through up to a 512 byte block of RAM If more address lines are needed IO port pins are used 3 14 4 Long Transfer Mode In the master mode the 8051 appropriately sets GPIF trans action count registers GPIFTCB3 GPIFTCB2 GPIFTCB1 or GPIFTCBO for unattended transfers of up to 29 transactions The GPIF automatically throttles data flow to prevent under or overflow until the full number of requested transactions complete The GPIF decrements the value in these registers to represent the current status of the transaction Notes CY7C68013A CY7C68014A CY7C68015A CY7C68016A 3 15 ECC Generation The EZ USB can calculate ECCs Error Correcting Codes on data that passes across its GPIF or Slave FIFO interfaces There are two ECC configurations Two each calculated over 256 bytes SmartMedia Standard and one ECC calculated over 512 bytes The ECC can correct any one bit error or detect any two bit error 3 15 1 ECC Implementation The two ECC configurations are selected by the bit 0 Two 3 byte ECCs each calculated over a 256 byte block of data This configuration conforms to the SmartMedia Standard Write any value to ECCRESET then pass data across the GPIF or Slave FIFO interface The ECC for the first 256 bytes of data is calcul
36. Busses Ideal for battery powered applications CY7C68014A 128AXC 128 TQFP Lead Free 16K 40 16 8 bit CY7C68014A 100AXC 100 TQFP Lead Free 16K 40 CY7C68014A 56PVXC 56 SSOP Lead Free 16K 24 CY7C68014A 56LFXC 56 QFN Lead Free 16K 24 CY7C68014A 56BAXC 56 VFBGA Lead Free 16K 24 CY7C68016A 56LFXC 56 QFN Lead Free 16K 26 Ideal for non battery powered applications CY7C68013A 128AXC 128 TQFP Lead Free 16K 40 16 8 bit CY7C68013A 128AXI 128 TQFP Lead Free Industrial 16K 40 16 8 bit CY7C68013A 100AXC 100 TQFP Lead Free 16K 40 7 68013 100 100 TQFP Lead Free Industrial 16 40 CY7C68013A 56PVXC 56 SSOP Lead Free 16K 24 7 68013 56 56 SSOP Lead Free Industrial 16K 24 CY7C68013A 56LFXC 56 QFN Lead Free 16K 24 CY7C68013A 56LFXI 56 QFN Lead Free Industrial 16K 24 CY7C68015A 56LFXC 56 QFN Lead Free 16K 26 CY7C68013A 56BAXC 56 VFBGA Lead Free 16K 24 Development Tool Kit CY3684 EZ USB FX2LP Development Kit Reference Design Kit CY4611B USB 2 0 to ATA ATAPI Reference Design using EZ USB FX2LP Document 38 08032 Rev L Page 54 of 62 Feedback CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A PERFORM 12 Package Diagrams The FX2LP is available in five packages m 56 pin SSOP m 56 QFN m 100 TQFP m 128 pin TQFP m 56 ball VFBGA Package Diag
37. CTL3 is a GPIF control output 67 52 CTL4 Output H CTL4 is a GPIF control output 98 76 CTL5 Output H CTL5 is a GPIF control output 32 26 20 13 2G IFCLK on IO Z 2 Interface Clock used for synchronously clocking data CY7C68013A into or out of the slave FIFOs IFCLK also serves as a and timing reference for all slave FIFO control signals and CY7C68014A GPIF When internal clocking is used IFCONFIG 7 1 the IFCLK pin can be configured to output 30 48 MHz by bits IFCONFIG 5 and IFCONFIG 6 IFCLK may be inverted whether internally or externally sourced by setting the bit IFCONFIG 4 1 PEO on 10 2 PEO is a bidirectional IO port pin CY7C68015A and CY7C68016A 28 22 INT4 Input N A INT4isthe 8051 INT4 interrupt request input signal The INT4 pin is edge sensitive active HIGH 106 84 INT5 Input N A INT5 is the 8051 INT5 interrupt request input signal The INT5 pin is edge sensitive active LOW 31 25 T2 Input N A T2 is the active HIGH T2 input signal to 8051 Timer2 which provides the input to Timer2 when C T2 1 When C T2 0 Timer2 does not use this pin 30 24 T1 Input N A 1 active HIGH T1 signal for 8051 Timer1 which provides the input to Timer1 when C T1 is 1 When C T1 is 0 Timer1 does not use this bit 29 23 TO Input N A TOisthe active HIGH TO signal for 8051 0 which provides the input to TimerO when C TO is 1 When C TO is 0 TimerO does not use this bit 53 43 RXD1 Input N A RXDhlis an act
38. E6B2 EP8FIFOBCL Endpoint 8 slave 7 BC6 BC5 BC4 BC3 BC2 BC1 BCO 00000000 R total byte count L E6B3 SUDPTRH Setup Data Pointer high A15 14 13 12 11 10 AQ 8 RW address byte E6B4 SUDPTRL Setup Data Pointer low 4 7 5 4 2 1 0 0 bbbbbbbr dress byte E6B5 SUDPTRCTL Setup Data Pointer Auto 0 0 0 0 0 0 0 SDPAUTO 00000001 Mode 2 reserved E6B8 8 SET UPDAT 8 bytes of setup data D7 D6 D5 D4 D3 D2 D1 DO SET UPDAT O bmRequestType SET UPDAT 1 bmRequest SET UPDAT 2 3 wVal ue SET UPDAT 4 5 wind ex SET UPDAT 6 7 wLength GPIF 6 0 GPIFWFSELECT Waveform Selector SINGLEWR 1 SINGLEWRO SINGLERD1 SINGLERDO FIFOWR1 FIFOWRO FIFORD1 FIFORDO 11100100 E6C1 GPIFIDLECS GPIF Done GPIF IDLE DONE 0 0 0 0 0 0 IDLEDRV 10000000 drive mode 1 GPIFIDLECTL Inactive Bus CTL states 0 0 CTL4 CTL3 CTL2 CTL1 CTLO 11111111 RW 6 3 GPIFCTLCFG CTL Drive Type TRICTL 0 CTL5 CTL4 CTL3 CTL2 CTL1 CTLO 00000000 E6C4 GPIF Address 0 0 0 0 0 0 0 GPIFA8 00000000 RW 6 5 GPIFADRLUI GPIF Address L GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFAO 00000000 FLOWSTATE E6C6 1 FLOWSTATE Flowstate Enable and FSE 0 0 0 0 FS2 FS FSO 00000000 brrrrbbb Selector E6C7 FLOWLOGIC Flowstate Logic LFUNC1 LFUNCO TERMA2 1 TERMAO 2 00000000
39. EEPROM contents into internal RAM 0 2 If no EEPROM is detected FX2LP enumerates using internally stored descriptors The default ID values for FX2LP are VID PID DID 0x04B4 0 8613 where xxx Chip 21 Table 2 Default ID Values for 21 Default VID PID DID Vendor ID 0x04B4 Cypress Semiconductor Product ID 0x8613 EZ USB FX2LP Device release OxAnnn Depends on chip revision nnn chip revision where first silicon 001 3 6 ReNumeration Because the FX2LP s configuration is soft one chip can take on the identities of multiple distinct USB devices When first plugged into USB the FX2LP enumerates automati cally and downloads firmware and USB descriptor tables over the USB cable Next the FX2LP enumerates again this time as a device defined by the downloaded information This patented two step process called ReNumeration happens instantly when the device is plugged in without a hint that the initial download step has occurred Note x 8x 9x Ax Bx Cx Dx Ex Fx 0 IOA IOB IOC IOD SCON1 PSW ACC B 1 SP EXIF INT2CLR IOE SBUF1 2 DPLO MPAGE INT4CLR OEA 3 DPHO OEB 4 DPL1 OEC 5 DPH1 OED 6 DPS OEE 7 PCON 8 TCON SCONO IE IP T2CON EICON EIE EIP 9 TMOD SBUFO A TLO AUTOPTRH1 EP2468STAT EPO1STAT RCAP2L B TL1 AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H C THO reserved EP68FIFOFLGS TL2 D TH1 AUTOPTRH2 GPIFSGLDATH TH2 E CKCON AUTOPTRL2 GPIFSGLDATLX F
40. PC6 or 10 2 Multiplexed whose function is selected by GPIFADR6 PC6 IPORTCCFG 6 PC6 is a bidirectional IO port pin GPIFADR6 is a GPIF address output pin 79 64 PC7 or IO Z Multiplexed whose function is selected by GPIFADR7 PC7 IPORTCCFG 7 is a bidirectional IO port pin GPIFADR7 is a GPIF address output pin PORT D 102 80 52 45 8A PDOor 10 2 Multiplexed whose function is selected by the FD 8 PDO IFCONFIG 1 0 and EPxFIFOCFG 0 wordwide bits FD 8 is the bidirectional FIFO GPIF data bus 103 81 53 46 PD1 or 10 2 Multiplexed whose function is selected the FD 9 PD1 IFCONFIG 1 0 and EPxFIFOCFG 0 wordwide bits FD 9 is the bidirectional FIFO GPIF data bus Document 38 08032 Rev L Page 24 of 62 Feedback CY7C68013A CY7C68014A CY7C68015A CY7C68016A Table 11 FX2LP Pin Descriptions continued 100 TQFP TQFP 56 SSOP 56 QFN 56 VF BGA Name Type Default Description 82 54 47 6B PD2 or FD 10 10 2 2 Multiplexed whose function is selected by the IFCONFIG 1 0 and EPxFIFOCFG 0 wordwide bits FD 10 is the bidirectional FIFO GPIF data bus 55 48 6A or FD 11 10 2 Multiplexed whose function is selected by the IFCONFIG 1 0 and EPxFIFOCFG 0 wordwide bits FD 11 is the bidirectional FIFO GPIF data bus 122 56 49 50 3B
41. SCL CTL4 52 30 SDA CTL3 51 20 70 70 20 70 70 252051021222 dE denotes programmable polarity Document 38 08032 Rev L Page 17 of 62 Feedback CYPRESS PERFORM Figure 9 CY7C68013A CY7C68014A 56 pin SSOP Pin Assignment Document 38 08032 Rev L CY7C68013A CY7C68014A CY7C68015A CY7C68016A CY7C68013A CY7C68014A 56 pin SSOP PD5 FD13 PD4 FD12 PD6 FD14 PD3 FD11 PD7 FD15 PD2 FD10 GND PD1 FD9 CLKOUT PDO FD8 VCC WAKEUP GND VCC RDY0 SLRD RESET RDY1 SLWR GND AVCC PA7 FLAGD SLCS XTALOUT PA6 PKTEND XTALIN PA5 FIFOADR1 AGND PA4 FIFOADRO AVCC PA3 WU2 DPLUS PA2 SLOE DMINUS PA1 INT1 AGND PAO INTO VCC VCC GND CTL2 FLAGC IFCLK CTL1 FLAGB RESERVED CTLO FLAGA SCL GND SDA VCC VCC GND PBO FDO PB7 FD7 PB1 FD1 PB6 FD6 PB2 FD2 PB5 FD5 PB3 FD3 PB4 FD4 denotes programmable polarity Page 18 of 62 Feedback CYPRESS PERFORM CY7C68013A CY7C68014A CY7C68015A CY7C68016A Figure 10 CY7C68013A 14A 15A 16A 56 pin QFN Pin Assignment RDYO SLRD RDY1 SLWR AVCC XTALOUT XTALIN AGND AVCC DPLUS DMINUS AGND VCC GND IFCLK PEO RESERVED Document 38 08032 Rev L
42. assertion there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte word packet Additional timing requirements exists when the FIFO is configured to operate in auto mode and it is desired to send two packets a full packet full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register committed automatically followed by a short one byte or word packet committed manually using the PKTEND pin In this case the external master must ensure to assert the PKTEND pin at least one clock cycle after the rising edge that caused the last byte or word that needs to be clocked into the previous auto committed packet the packet with the number of bytes equal to what is set in the AUTOINLEN register Refer to Figure 23 for further details on this timing Page 51 of 62 Feedback CY7C68013A CY7C68014A CY7C68015A CY7C68016A CYPRESS PERFORM 10 17 3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 32 Slave FIFO Asynchronous Read Sequence and Timing Diagram t SFA FIFOADR 1 ED tRDpwi tropwh T 0 tRDpwi tRDpwh SLRD SLCS DATA SLOE Figure 33 Slave FIFO Asynchronous Read Sequence of Events Diagram SLOEY
43. blocks between two domains the USB SIE domain and the 8051 IO Unit domain This switching is done virtually instan taneously giving essentially zero transfer time between USB FIFOS and Slave FIFOS Because they are physically the same memory no bytes are actually transferred between buffers At any given time some RAM blocks are filling emptying with USB data under SIE control while other RAM blocks are available to the 8051 the IO control unit or both The RAM blocks operate as single port in the USB domain and dual port in the Notes 4 0 means not implemented 5 2x means double buffered 805140 domain The blocks can be configured as single double triple or quad buffered as previously shown The IO control unit implements either an internal master M for master or external master S for Slave interface In Master M mode the GPIF internally controls FIFOADR 1 0 to select a FIFO The RDY pins two in the 56 pin package six in the 100 pin and 128 pin packages can be used as flag inputs from an external FIFO or other logic if desired The GPIF can be run from either an internally derived clock or externally supplied clock IFCLK at a rate that transfers data up to 96 Megabytes s 48 MHz IFCLK with 16 bit interface In Slave S mode the FX2LP accepts either an internally derived clock or externally supplied clock IFCLK max frequency 48 MHz and SLCS SLRD SLWR SLOE PKTEND signals from external lo
44. bulk 64 int 64 int ep2 0 64 bulk out 2x 64 int out 2 64 iso out 2x ep4 0 64 bulk out 2x 64 bulk out 2x 64 bulk out 2x 0 64bulkin 2x 64 int in 2x 64 iso in 2x ep8 0 64 bulk in 2x 64 bulk in 2x 64 bulk in 2x 3 12 6 Default High Speed Alternate Settings Table 7 Default High Speed Alternate Settings 5 Alternate Setting 0 1 2 3 64 64 64 64 eplout 0 512 64 int 64 int eptin 0 512 64 int 64 int ep2 0 512 bulk out 2x 512 int out 2x 512 iso out 2x ep4 0 512 bulk out 2x 512 bulk out 2x 512 bulk out 2x 0 512 bulk 2 512 int in 2 512 iso in 2x ep8 0 512 bulk in 2x 512 bulk in 2x 512 bulk in 2x 3 13 External FIFO Interface 3 13 1 Architecture The FX2LP slave FIFO architecture has eight 512 byte blocks in the endpoint RAM that directly serve as FIFO memories and are controlled by FIFO control signals such as IFCLK 51 54 SLRD SLWR SLOE PKTEND and flags In operation some of the eight RAM blocks fill or empty from the SIE while the others are connected to the IO transfer logic The transfer logic takes two forms the GPIF for internally generated control signals and the slave FIFO interface for externally controlled transfers 3 13 2 Master Slave Control Signals The FX2LP endpoint FIFOS are implemented as eight physically distinct 256x16 RAM blocks The 8051 SIE can switch any of the RAM
45. bus 56 46 31 24 PB6 or 10 7 Multiplexed whose function is selected by the FD 6 PB6 following bits IFCONFIG 1 0 PB6 is a bidirectional IO port pin FD 6 is the bidirectional FIFO GPIF data bus 57 47 32 25 PB7 or 10 7 Multiplexed whose function is selected by the FD 7 PB7 following bits IFCONFIG 1 0 PB7 is a bidirectional IO port pin FD 7 is the bidirectional FIFO GPIF data bus PORT C 72 57 PCO or IO Z Multiplexed whose function is selected by GPIFADRO PCO PORTCCFG O PCO is a bidirectional IO port pin GPIFADRO is a GPIF address output pin 73 58 PC1 or 10 2 Multiplexed whose function is selected GPIFADR1 PC1 IPORTCCFG 1 PC1 is a bidirectional IO port pin GPIFADR1 is GPIF address output pin 74 59 2 or IO Z Multiplexed whose function is selected by GPIFADR2 PC2 IPORTCCFG 2 PC2 is a bidirectional IO port pin GPIFADR2 is GPIF address output pin 75 60 PC3 or IO Z Multiplexed whose function is selected by GPIFADR3 PC3 IPORTCCFG 3 is a bidirectional IO port pin GPIFADRS3 is a GPIF address output pin 76 61 PC4 or 10 2 Multiplexed whose function is selected GPIFADR4 PC4 IPORTCCFG 4 PC4 is a bidirectional IO port pin GPIFADRA is a GPIF address output pin 77 62 PC5 or IO Z Multiplexed whose function is selected by GPIFADR5 PC5 PORTCCFG 5 PC5 is a bidirectional IO port pin GPIFADRS5 is a GPIF address output pin 78 63
46. interface in a single chip Document 38 08032 Rev L Soft Configuration Easy firmware changes FIFO and endpoint memory master or slave operation USE Cypress has created a cost effective solution that provides superior time to market advantages with low power to enable bus powered applications The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second the maximum allowable USB 2 0 bandwidth while still using a low cost 8051 microcon troller in a package as small as a 56 VFBGA 5mm x 5mm Because it incorporates the USB 2 0 transceiver the FX2LP is more economical providing a smaller footprint solution than USB 2 0 SIE or external transceiver implementations With EZ USB FX2LP the Cypress Smart SIE handles most of the USB 1 1 and 2 0 protocol in hardware freeing the embedded microcontroller for application specific functions and decreasing development time to ensure USB compatibility The General Programmable Interface GPIF and Master Slave Endpoint FIFO 8 bit or 16 bit data bus provides an easy and glueless interface to popular interfaces such as ATA UTOPIA EPP PCMCIA and most DSP processors The FX2LP draws less current than the FX2 7 68013 has double the on chip code data RAM and is fit form and function compatible with the 56 100 and 128 pin FX2 Five packages are defined for the family 56VFBGA 56 SSOP 56 QFN 100 TQFP and 128 TQFP Page
47. reserved 00000000 reserved reserved E6D2 1 EP2GPIFFLGSELl Endpoint 2 GPIF Flag 0 0 0 0 0 0 FS1 FSO 00000000 RW select E6D3 1 EP2GPIFPFSTOP Endpoint 2 GPIF stop 0 0 0 0 0 0 0 FIFO2FLAG 00000000 RW transaction on prog flag EP2GPIFTRIGI Endpoint 2 GPIF Trigger 3 reserved reserve W reserved E6DA 1 EPAGPIFFLGSELTT 2 4 GPIF Flag 0 0 0 0 0 0 FS1 FSO 00000000 RW selec E6DB 1 EP4GPIFPFSTOP Endpoint 4 GPIF stop 0 0 0 0 0 0 0 FIFO4FLAG 00000000 transaction on GPIF Flag 1 EP4GPIFTRIGI Endpoint 4 GPIF Trigger x W 3 reserved U l reserved E6E2 EP6GPIFFLGSEL Endpoint 6 GPIF Flag 0 0 0 0 0 0 51 50 00000000 RW selec 1 EPeGPIFPFSTOP Endpoint 6 GPIF stop 0 0 0 0 0 0 0 FIFO6FLAG 00000000 transaction on prog flag 6 4 EP6GPIFTRIGI Endpoint 6 GPIF Trigger x W 3 reserved reserve reserved E6EA EP8GPIFFLGSELTTI Endpoin 8GPIF Flag 0 0 0 0 0 0 FS1 0 00000000 select E6EB EP8GPIFPFSTOP 8 GPIF stop 0 0 0 0 0 0 0 FIFO8FLAG 00000000 transaction on prog flag E6ECH EP8GPIFTRIGI Endpoint 8 GPIF Trigger x x x x x x x x W 3 reserved
48. the SLCS is used it must be asserted with SLWR or before SLWR is asserted m At t 2 data must be present on the bus tsrp before the deasserting edge of SLWR m Att 3 deasserting SL WR causes the data to be written from the data bus to the FIFO and then increments the FIFO pointer Document 38 08032 Rev L The FIFO flag is also updated after tyr from the deasserting edge of SLWR The same sequence of events are shown for a burst write and is indicated by the timing marks of T 0 through 5 Note In the burst write mode after SLWR is deasserted the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO The FIFO pointer is post incre mented In Figure 34 after the four bytes are written to the FIFO and SLWR is deasserted the short 4 byte packet can be committed to the host using the PKTEND The external device should be designed to not assert SLWR and the PKTEND signal at the same time It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse width The FIFOADDR lines have to held constant during the PKTEND assertion Page 53 of 62 Feedback cypress PERFORM 11 Ordering Information Table 33 Ordering Information CY7C68013A CY7C68014A CY7C68015A CY7C68016A 8051 Address Ordering Code Package Type Size Prog 10
49. 000000 RW 2 reserved 0 1 PSW Program Status Word bit CY AC F0 RS1 RS0 F1 P 00000000 RW addressable Di 7 reserved 08 1 External Interrupt Control SMOD1 1 ERESI RESI INT6 0 0 0 01000000 D9 7 reserved EO 1 bit address D7 06 05 04 03 02 01 00 00000000 able 1 7 reserved E8 1 EIEN External Interrupt En 1 1 1 EX6 EX5 4 EUSB 11100000 able s E9 7 reserved FO 1 B B bit addressable D7 D6 D5 D4 D3 D2 D1 D0 00000000 1 T reserved F8 1 1 External Interrupt Priority 1 1 1 5 4 PUSB 11100000 RW Control F9 7 reserved Document 38 08032 Rev L all bits read only W all bits write only r read only bit w write only bit b both read write bit Page 35 of 62 Feedback CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A 6 Absolute Maximum Ratings Storage 30010 3 0 ERRORES 65 C to 150 Ambient Temperature with Power Supplied Commercial enne nnns 0 C to 70 Ambient Temperature with Power Supplied Industrial nennen 40 C to 105 Supply Voltage to Ground Potential 0 5V to 4 0V 5 25 DC Voltage Applied to Outputs High Z State
50. 00000001 brrrrrrr per frame 1 3 E644 4 reserved E648 1 INPKTENDI Force IN Packet End Skip 0 0 0 2 1 W E649 7 Force OUT Packet End Skip 0 0 0 2 1 W INTERRUPTS E650 1 2 Endpoint 2 slave FIFO 0 0 0 0 EDGEPF 00000000 RW Flag Interrupt Enable E651 1 2 27 Endpoint2slave FIFO 0 0 0 0 0 00000000 rrrrrbbb Flag Interrupt Reques E652 1 EP4FIFOIETT Endpoint 4 slave FIFO 0 0 0 0 EDGEPF EF FF 00000000 RW Flag Interrupt Enable E653 1 27 Endpoint 4 slave FIFO 0 0 0 0 0 PF EF FF 00000000 rrrrrbbb Flag Interrupt Reques E654 4 EP6FIFOIEL Endpoint 6 slave FIFO 0 0 0 0 EDGEPF EF FF 00000000 RW Flag Interrupt Enable E655 1 EP6FIFOIRQU 27 Endpoint 6 slave FIFO 0 0 0 0 0 PF EF FF 00000000 rrrrrbbb Flag Interrupt Reques 656 1 Endpoint 8 slave FIFO 0 0 0 0 EDGEPF 00000000 Interrupt Enable E657 1 27 8 slave FIFO 0 0 0 0 0 00000000 rrrrrbbb Flag Interrupt Reques E658 1 IBNIE N BULK NAK Interrupt 0 0 EP8 EP6 4 2 1 00000000 Enable E659 1 IBNIRQI TZI N BULK NAK interrupt 0 0 EP8 EP6 4 2 1 00 rrbbbbbb Request E65A11 NAKIE Endpoint Ping NAK IBN 8 EP6 E
51. 3 10 3 External Code Memory EA 1 The bottom 16 KBytes of program memory is external and therefore the bottom 16 KBytes of internal RAM is accessible only as a data memory Page 7 of 62 Feedback Inside FX2LP CY7C68013A CY7C68014A CY7C68015A CY7C68016A Figure 3 Internal Code Memory EA 0 Outside FX2LP FFFF E200 7 5 KBytes USB regs and 4K FIFO buffers RD WR ETFF E000 3FFF 0000 SUDPTR USB upload download 1 C interface boot access Document 38 08032 Rev L 0 5 KBytes RAM Data RD WR OK to populate data memory here RD WR strobes are not active 40 KBytes External Data Memory RD WR 48 KBytes External Code Memory PSEN 16 KBytes RAM Code and Data Ok to populate OK to populate data memory program here RD WR memory here PSEN RD WR strobes are not PSEN strobe active is not active Data Code Page 8 of 62 Feedback CY7C68013A CY7C68014A CY7C68015A CY7C68016A Figure 4 External Code Memory EA 1 Inside FX2LP Outside FX2LP FFFF 7 5 KBytes USB regs and OK to populate 4K FIFO buffers data memory RD WR here RD WR E200 strobes are not ETFF 0 5 KBytes RAM active E000 Data RD WR 40 KBytes External Data 64 KBytes Memory External RD WR Code Memory PSEN 16 KBytes
52. 3A PD4 or FD 12 PD5 or FD 13 10 2 10 2 PD4 5 Multiplexed whose function is selected the IFCONFIG 1 0 and EPxFIFOCFG 0 wordwide bits FD 12 is the bidirectional FIFO GPIF data bus Multiplexed pin whose function is selected by the IFCONFIG 1 0 EPxFIFOCFG 0 wordwide bits FD 13 is the bidirectional FIFO GPIF data bus 51 3C PD6 or FD 14 10 2 PD6 Multiplexed pin whose function is selected by the IFCONFIG 1 0 and EPxFIFOCFG 0 wordwide bits FD 14 is the bidirectional FIFO GPIF data bus 124 98 52 2A PD7 or FD 15 10 7 PD7 Multiplexed pin whose function is selected by the IFCONFIG 1 0 and EPxFIFOCFG 0 wordwide bits FD 15 is the bidirectional FIFO GPIF data bus Port E 108 109 86 87 PEO or TOOUT PE1 or T1OUT 10 2 10 2 PE1 Multiplexed pin whose function is selected by the 0 bit PEO is a bidirectional IO port pin TOOUT is an active HIGH signal from 8051 Timer counterO TOOUT outputs a high level for one CLKOUT clock cycle when 0 overflows If TimerO is operated in Mode 3 two separate timer counters TOOUT is active when the low byte timer counter overflows Multiplexed pin whose function is selected by the PORTECFG 1 bit PE1 is a bidirectional IO port pin T1OUT is an active HIGH signal from 8051 Timer counter1 T1OUT outputs a high
53. 4 5G EP8PING EP8 OUT was Pinged and it NAK d 25 60 ERRLIMIT Bus errors exceeded the programmed limit 26 64 27 68 reserved 28 6 reserved 29 70 EP2ISOERR ISO EP2 OUT PID sequence error 30 74 EP4ISOERR ISO EP4 OUT PID sequence error 31 78 EP6ISOERR ISO EP6 OUT PID sequence error 32 7 EP8ISOERR ISO EP8 OUT PID sequence error If Autovectoring is enabled AV2EN 1 in the INTSET UP 3 8 3 FIFO GPIF Interrupt INT4 register the FX2LP substitutes its INT2VEC byte Therefore if the high byte page of a jump table address is preloaded at the location 0x0044 the automatically inserted INT2VEC byte at 0x0045 directs the jump to the correct address out of the 27 addresses within the page Document 38 08032 Rev L Just as the USB Interrupt is shared among 27 individual USB interrupt sources the FIFO GPIF interrupt is shared among 14 individual FIFO GPIF sources The FIFO GPIF Interrupt like the USB Interrupt can employ autovectoring Table 4 shows the priority and INT4VEC values for the 14 FIFO GPIF interrupt sources Feedback Table 4 Individual FIFO GPIF Interrupt Sources CY7C68013A CY7C68014A CY7C68015A CY7C68016A Priority INT4VEC Value Source Notes 1 80 EP2PF Endpoint 2 Programmable Flag 2 84 EP4PF Endpoint 4 Programmable Flag 3 88 EP6PF Endpoint 6 Programmable Flag 4 8C EP8PF Endpoint 8 Programmable Flag 5 90 EP2EF Endpoint 2 Empty Fl
54. 6 RDY3 Input N A RDY3 is a GPIF input signal 8 7 RDY4 Input N A RDY4 is a GPIF input signal 9 8 RDY5 Input N A RDY5 is a GPIF input signal 69 54 36 29 7H CTLO or O Z H Multiplexed pin whose function is selected by the FLAGA following bits IFCONFIG 1 0 CTLO is a GPIF control output FLAGA is a programmable slave FIFO output status flag signal Defaults to programmable for the FIFO selected by the FIFOADR 1 0 pins Document 38 08032 Rev L Page 26 of 62 Feedback gt gt CYPRESS PERFORM Table 11 FX2LP Pin Descriptions continued CY7C68013A CY7C68014A CY7C68015A CY7C68016A 100 56 56 VF Document 38 08032 Rev L 56 I TQFP TQFP SSOP BGA Name Type Default Description 70 55 37 30 7G CTL1 or O Z H Multiplexed pin whose function is selected by the FLAGB following bits IFCONFIG 1 0 CTL1 is a GPIF control output FLAGB is a programmable slave FIFO output status flag signal Defaults to FULL for the FIFO selected by the FIFOADR 1 0 pins 71 56 38 31 8H CTL2 or O Z H Multiplexed pin whose function is selected by the FLAGC following bits IFCONFIG 1 0 CTL2 is a GPIF control output FLAGC is a programmable slave FIFO output status flag signal Defaults to EMPTY for the FIFO selected by the FIFOADR 1 0 pins 66 51 CTL3 O Z H
55. 60 of 62 Feedback CY7C68013A CY7C68014A CY7C68015A CY7C68016A Description of Change PERFORM Document Title CY7C68013A CY7C68014A CY7C68015A CY7C68016A EZ USB FX2LP USB Microcontroller Document History Page High Speed USB Peripheral Controller Document Number 38 08032 Issue Orig of REV NO Date Change 124316 03 17 03 VCS New data sheet 128461 09 02 03 VCS PN CY7C68015A throughout data sheet Modified Figure 1 to add block and fix errors Removed word compatible where associated with 2 Corrected grammar and formatting in various locations Updated Sections 3 2 1 3 9 3 11 Table 9 Section 5 0 Added Sections 3 15 3 18 4 3 20 Modified Figure 5 for clarity Updated Figure 36 to match current spec revision 130335 10 09 03 KKV Restored PRELIMINARY to header had been removed in error from rev 131673 02 12 04 KKU Section 8 1 changed certified to compliant Table 14 added parameter Vi x and Vy Added Sequence diagrams Section 9 16 Updated Ordering information with lead free parts Updated Registry Summary Section 3 12 4 example changed to column 8 from column 9 Updated Figure 14 memory write timing Diagram Updated section 3 9 reset Updated section 3 15 ECC Generation 230713 SeeECN KKU Changed Lead free Marketing part numbers in Table 33 as per spe
56. 8032 Rev L If the SLCS signal is used it must be asserted before SLRD is asserted The SLCS and SLRD signals must both be asserted to start a valid read condition m The FIFO pointer is updated on the rising edge of the IFCLK while SLRD is asserted This starts the propagation of data from the newly addressed location to the data bus After a propagation delay of tx p measured from the rising edge of IFCLK the new data value is present N is the first data value read from the FIFO To have data on the FIFO data bus SLOE MUST also be asserted The same sequence of events are shown for a burst read and are marked with the time indicators of T 0 through 5 Note For the burst mode the SLRD and SLOE are left asserted during the entire duration of the read In the burst read mode when SLOE is asserted data indexed by the FIFO pointer is on the data bus During the first read cycle on the rising edge of the clock the FIFO pointer is updated and increments to point to address N 1 For each subsequent rising edge of IFCLK while the SLRD is asserted the FIFO pointer is incremented and the next data value is placed on the data bus Page 50 of 62 Feedback CYPRESS PERFORM 10 17 2 Single and Burst Synchronous Write CY7C68013A CY7C68014A CY7C68015A CY7C68016A Figure 31 Slave FIFO Synchronous Write Sequence and Timing 20
57. CLK Period 20 83 200 ns tswr SLWR to Clock Setup Time 12 1 ns twRH Clock to SLWR Hold Time 3 6 ns FIFO Data to Clock Setup Time 3 2 ns teDH Clock to FIFO Data Hold Time 4 5 ns Clock to FLAGS Output Propagation Time 13 5 ns Document 38 08032 Rev L Page 45 of 62 Feedback lt _ CYPRESS PERFORM 10 10 Slave FIFO Asynchronous Write Table 25 Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK Figure 21 Slave FIFO Asynchronous Write Timing Diagram twRpwh SLWR twrpwi CY7C68013A CY7C68014A CY7C68015A CY7C68016A 20 gt tFDH DATA gt FLAGS txrp Parameter Description Min Max Unit SLWR Pulse LOW 50 ns twRowh SLWR Pulse HIGH 70 ns SLWR to FIFO DATA Setup Time 10 ns FIFO DATA to SLWR Hold Time 10 ns SLWR to FLAGS Output Propagation Delay 70 ns 10 11 Slave FIFO Synchronous Packet End Strobe Figure 22 Slave FIFO Synchronous Packet End Strobe Timing 0 IFCLK E SPE Aedes A i FLAGS b txFLG Table 26 Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced 211 Parameter Description Min Max Unit IFCLK Per
58. Configuration VALID DIR TYPE1 TYPEO 0 0 0 0 11100000 bbbbrrrr 2 reserved E618 EP2FIFOCFGI Endpoint 2 slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN O WORDWIDE 00000101 rbbbbbrb configuration E619 1 EP4FIFOCFG Endpoint 4 slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN O WORDWIDE 00000101 rbbbbbrb configuration E61A 1 EP6FIFOCFGI Endpoint 6 slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN O WORDWIDE 00000101 rbbbbbrb configuration E61B EP8FIFOCFGI Endpoint 8 slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN O WORDWIDE 00000101 rbbbbbrb configuration E61C 4 reserved E620 EP2AUTOINLENHU Endpoint 2 AUTOIN 0 0 0 0 0 PL10 PL9 PL8 0000001 0 rrrrrbbb Packet Length H E621 EP2AUTOINLENLT Endpoint 2 AUTOIN PL7 PL6 15 PL4 PL3 PL2 PL1 PLO 00000000 RW Packet Length L E622 EP4AUTOINLENH UT Endpoint 4 AUTOIN 0 0 0 0 0 0 PL9 PL8 0000001 O rrrrrrbb Packet Length H E623 1 EPA4AUTOINLENLT T Endpoint 4 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO 00000000 RW Packet Length L E624 EP6AUTOINLENH Endpoint 6 AUTOIN 0 0 0 0 0 PL10 PLO PL8 0000001 Ojrrrrrbbb Packet Length H E625 EP6AUTOINLENLI J Endpoint 6 AUTOIN PL7 PL6 15 PL4 PL3 PL2 PL1 PLO 00000000 Packet Length L E626 EP8AUTOINLENHI T Endpoint 8 AUTOIN 0 0 0 0 0 0 PL9 PL8 0000001 0 rrrrrrbb Packet Length H E627 1 EP8AUTOINLENLT T Endpoint 8 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO 00000000 RW Packet Length L E628 ECCCFG ECC Configuration 0 0 0 0 0 0 0 ECCM 00000000 r
59. D7 D6 D5 04 03 02 DO 00000000 RW 8C THO Timer 0 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 8D TH1 Timer 1 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW 8E 1 CKCONISI Clock Control x x T2M TiM TOM MD2 MD1 MDO 00000001 RW 8F reserved 90 1 Port B bit addressable 07 D6 05 04 03 02 DO RW 91 EXIFUSI External Interrupt Flag s 4 USBNT 1 0 0 0 00001000 RW 92 1 Upper Addr Byte of MOVX A15 14 13 12 11 10 AQ A8 00000000 using R0 R1 93 5 reserved 98 1 SCON0 Serial Port 0 Control SM0_0 SM1_0 5 2 0 REN 0 TB8 0 RB8 0 TI 0 RI 0 00000000 bit addressable 99 SBUF0 Serial Port 0 Data Buffer 07 D6 D5 D4 D3 D2 D1 D0 00000000 RW 9A 1 AUTOPTRH10 3 Autopointer 1 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW 1 Autopointer 1 Address L 7 A6 A5 A4 A3 A2 Al AO 00000000 RW 9C reserved 9D 1 21731 Autopointer 2 Address 15 14 13 12 11 10 9 00000000 9E 1 AUTOPTRL2ISI Autopointer 2 Address L 7 A6 A5 A4 A3 A2 A1 AO 00000000 RW 9F 1 reserved AO lochs Port C bit addressable D7 D6 D5 D4 D3 D2 D1 RW 1 1 INT CLRISI Interrupt 2 clear x x x W 2 1 INTACLR I Interrupt 4 clear x x x x W 5 reserved A8 1 Interrupt Enable EA ES1 2 0 1 1 00000000
60. ISOEP2 0 0 0 ERRLIMIT 00000000 RW nables E663 5 2 E Interrupt ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 0000000x bbbbrrrb equests E664 ERRCNTLIM Error counter and KEC3 EC2 EC1 ECO LIMIT3 LIMIT2 LIMIT1 LIMITO 0100 rrrrbbbb Imt E665 1 CLRERRCNT Clear Error Counter EC3 0 x x x x x x x x W E666 NT2IVEC nterrupt 2 USB 0 124 123 12 2 12 1 12 0 0 0 00000000 Autovector E667 NT4IVEC nterrupt 4 slave FIFO amp 1 0 l4V3 14 2 l4V1 l4V0 0 0 10000000 R GPIF Autovector E668 NTSET UP nterrupt 2 amp 4 setup 0 0 0 0 AV2EN 0 INT4SRC AV4EN 00000000 E669 7 reserved NPUT OUTPUT E670 PORTACFG O PORTA Alternate FLAGD SLCS 0 0 0 0 INT1 INTO 00000000 Configuration E671 PORTCCFG E Alternate GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 ontiguration E672 PORTECFG PORTE Alternate GPIFA8 amp T2EX INT6 RXD1OUT RXDOOUT T2OUT 100 TOOUT 00000000 RW Configuration E673 4 reserved E677 1 reserved E678 ZCS 2C Bus START STOP LASTRD 101 1 BERR ACK DONE 000xx000 bbbrrrrr Control amp Status E679 2DAT 97 46 45 d4 d3 d2 91 90 IRW ata E67A PCTL 2 Bus 0 0 0 0 0 0 STOPIE 400KHZ 00000000 Control E67B XAUTODAT1 Autoptr1 MOVX access 07 D6 D5 D4 D3 D2 D1 D0 RW when APTREN 1 67 XAUTODAT2 Autoptr2 MOVX access D7 D6 D5 D4 D3 D2 D1 00 RW when APTREN 1 UDMA E67D UDMACRCH UDMA CRC M
61. K AIFCLK IFCLK IFCLK IFCLK FIFO POINTER N gt gt N 1 gt N 1 gt N 1 gt N 2 7 9 N 3 gt N 4 gt 4 gt 4 51 SLRDY SLOE SLRD SLOE FIFO DATA BUS Not Driven Driven gt 1 Driven gt 1 gt 2 gt N 3 gt N 4 gt 4 Driven Figure 29 shows the timing relationship of the SLAVE FIFO signals during a synchronous FIFO read using IFCLK as the synchronizing clock The diagram illustrates a single read followed by a burst read m Att 0 the FIFO address is stable and the signal SLCS is asserted SLCS may be tied low in some applications Note that tsa has a minimum of 25 ns This means when IFCLK is running at 48 MHz the FIFO address setup time is more than one IFCLK cycle m Att 1 SLOE is asserted SLOE is an output enable only whose sole function is to drive the data bus The data that is driven on the bus is the data that the internal FIFO pointer is currently pointing to In this example it is the first data value in the FIFO Note the data is pre fetched and is driven on the bus when SLOE is asserted m Att 2 SLRD is asserted SLRD must meet the setup time of tenp time from asserting the SLRD signal to the rising edge of the IFCLK and maintain a minimum hold time of time from the IFCLK edge to the deassertion of the SLRD signal Document 38 0
62. L 33 of 62 Feedback 1 4 2 CYPR PE TP ESS ORM Table 12 FX2LP Register Summary continued CY7C68013A CY7C68014A CY7C68015A CY7C68016A Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 50 Default 2 Configuration 0 DISCON 0 0 0 0 0 400KHZ Special Function Registers SFRs 80 OATS Port A bit addressable D7 D6 D5 D4 D3 D2 D1 DO RW 81 1 SP Stack Pointer D7 D6 05 04 03 02 01 DO 00000111 RW 82 1 DPLO Data Pointer 0 L 7 5 4 2 1 AO 00000000 RW 83 Data Pointer 0 15 14 13 12 11 10 AQ 8 00000000 84 DPL1U3 Data Pointer 1 L A7 A6 A5 A4 A3 A2 A1 00000000 RW 85 1 1 Data Pointer 1 H A15 A14 13 12 11 10 9 A8 00000000 RW 86 91737 Data Pointer 0 1 select 10 0 0 0 0 0 0 SEL 00000000 87 Power Control SMOD0 x 1 1 x x x IDLE 00110000 88 TCON Timer Counter Control TF1 TR1 TFO TRO IE1 IT1 ITO 00000000 RW bit addressable 89 TMOD HUE ed Mode GATE CT M1 MO GATE CT M MO 00000000 ontro 8A TLO Timer 0 reload L D7 D6 D5 04 03 02 D1 DO 00000000 RW 8B TL1 Timer 1 reload L
63. Masc CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A EZ USB FX2LP USB Microcontroller High Speed USB Peripheral Controller 1 Features CY7C68013A 14A 15A 16A m GPIF General Programmable Interface p Enables direct connection to most parallel interfaces m USB 2 0 USB IF high speed certified TID 40460272 Programmable waveform descriptors and configuration reg isters to define waveforms Supports multiple Ready RDY inputs and Control CTL out puts m Single chip integrated USB 2 0 transceiver smart SIE and enhanced 8051 microprocessor m Fit form and function compatible with the FX2 i m Integrated industry standard enhanced 8051 Pin compatible 48 MHz 24 MHz 12 MHz CPU operation Object code compatible I Four clocks per instruction cycle Functionally compatible FX2LP is a superset a Two USARTS m Ultra Low power more than 85 mA any mode Three counter timers Ideal for bus and battery powered applications Expanded interrupt system Two data pointers m Software 8051 code runs from Internal RAM which is downloaded USB m 3 3 operation with 5V tolerant inputs a Internal RAM which is loaded from EEPROM m Vectored USB interrupts and GPIF FIFO interrupts External memory device 128 pin package m Separate data buffers for the Setup and Data portions of m 16 KBytes of on chip Code Data RAM CONTROL transfer
64. NC N A N A Connect This pin must be left open Document 38 08032 Rev L Page 28 of 62 Feedback CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A PERFORM 5 Register Summary FX2LP register bit definitions are described in the FX2LP TRM in greater detail Table 12 FX2LP Register Summary Hex Size Name Description b7 b6 b5 b4 b3 b2 61 50 Default GPIF Waveform Memories E400 128 IWAVEDATA GPIF Waveform 07 06 05 04 03 02 01 DO RW Descriptor 0 1 2 3 data 480 128 reserved GENERAL CONFIGURATION E50D GPCR2 General Purpose Configu4reserved reserved reserved FULL SPEE reserved reserved reserved reserved 00000000 R ration Register 2 D ONLY E600 1 CPUCS CPU Control amp Status 0 0 PORTCSTB CLKSPD1 CLKSPDO CLKINV CLKOE 8051RES 00000010 rbbbbbr E601 1 IFCONFIG nterface Configuration IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFGO 10000000 Ports GPIF slave FIFOs E602 1 Slave FIFO FLAGA FLAGB3 FLAGB2 FLAGB1 FLAGBO FLAGA3 FLAGA2 FLAGA1 FLAGAO 00000000 FLAGB Pin Configuration 603 1 Slave FIFO FLAGC FLAGD3 FLAGD2 FLAGD1 FLAGDO FLAGC3 FLAGC2 FLAGC1 FLAGCO 00000000 FLAGD Pin Configuration
65. O interrupt input signal which is either edge triggered ITO 1 or level triggered ITO 0 Multiplexed pin whose function is selected by PORTACFG 1 PA1 is a bidirectional IO port pin INT1 is the active LOW 8051 interrupt input signal which is either edge triggered IT1 1 or level triggered IT1 0 84 69 42 35 8F 2 or SLOE or IO Z PA2 Multiplexed pin whose function is selected by two bits IFCONFIG 1 0 PA2 is a bidirectional IO port pin SLOE is an input only output enable with program mable polarity FIFOPINPOLAR 4 for the slave FIFOs connected to FD 7 0 or FD 15 0 Document 38 08032 Rev L Page 22 of 62 Feedback gt CYPRESS PERFORM Table 11 FX2LP Pin Descriptions continued CY7C68013A CY7C68014A CY7C68015A CY7C68016A 128 100 56 56 VF 56 55 QFN BGA Default Description 85 70 43 36 or WU2 IO Z Multiplexed pin whose function is selected by WAKEUP 7 and OEA 3 is a bidirectional IO port pin WU2 is an alternate source for USB Wakeup enabled by WU2EN bit WAKEUP 1 and polarity set by WU2POL WAKEUP 4 If the 8051 is in suspend and WU2EN 1 a transition on this pin starts up the oscil lator and interrupts the 8051 to enable it to exit the suspend mode Asserting this pin inhibits
66. P registers under control of a mode bit AUTOPTRSET UP 0 Using the external FX2LP autopointer access at OxE67B OxE67C enables the autopointer to access all internal and external RAM to the part Also the autopointers can point to any FX2LP register or endpoint buffer space When autopointer access to external memory is enabled location OXE67B and OxE67C in XDATA and code space cannot be used 7 To use the ECC logic the GPIF or Slave FIFO interface must be configured for byte wide operation 8 After the data has been downloaded from the host a loader can execute from internal RAM to transfer downloaded data to external memory Document 38 08032 Rev L Page 12 of 62 Feedback 3 18 12 Controller FX2LP has one 2 port that is driven by two internal controllers one that automatically operates at boot time to load VID PID DID and configuration information and another that the 8051 uses when running to control external 1 C devices I C port operates in master mode only 3 18 1 Port Pins The pins SCL and SDA must have external 2 2 pull up resistors even if no EEPROM is connected to the FX2LP External EEPROM device address pins must be configured properly See Table 8 for configuring the device address pins Table 8 Strap Boot EEPROM Address Lines to These Values Bytes Example EEPROM A2 Al 16 241 128 24LC01 0 0 0 256 241 02
67. P4 EP2 1 0 00000000 nterrupt Enable 65 1 NAKIRQU I Endpoint Ping NAK IBN EP8 EP6 4 2 1 0 bbbbbbrb nterrupt Request 65 1 USBIE USB Int Enables 0 HSGRANT URES SUSP SUTOK SOF SUDAV 00000000 RW Note 12 The register can only be reset it cannot be set Document 38 08032 Rev L Page 30 of 62 CY7C68013A CY7C68014A CY7C68015A CY7C68016A Feedback 1 4 gt 55 PERFORM Table 12 FX2LP Register Summary continued CY7C68013A CY7C68014A CY7C68015A CY7C68016A Document 38 08032 Rev L Hex Size Name Description b7 56 b5 b4 b3 b2 b1 50 Default 55 E65D USBIRQI2 USB Interrupt Requests 0 EPOACK HSGRANT URES SUSP SUTOK SOF SUDAV Oxxxxxxx rbbbbbbb E65E 1 EPIE Endpoint Interrupt EP8 EP6 EP4 EP2 EP1OUT EP1IN EPOOUT EPOIN 00000000 RW nables E65F 1 2 Interrupt EP8 EP6 EP4 EP2 EP1OUT EP1IN EPOOUT EPOIN 0 RW equests E660 GPIFIEUTI GPIF Interrupt Enable 0 0 0 0 0 0 GPIFWF GPIFDONE 00000000 E661 GPIFIRQU GPIF Interrupt Request 0 0 0 0 0 0 GPIFWF GPIFDONE 000000xx RW E662 1 USBERRIE Eum Interrupt ISOEP8 ISOEP6 ISOEP4
68. SB CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8 01001010 RW E67E CRC 158 CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 10111010 RW E67F 1 EE UDMA CRC Qualifier QENABLE 0 0 0 QSTATE QSIGNAL2 QSIGNAL1 QSIGNALO 00000000 brrrbbbb USB CONTROL E680 1 USBCS USB Control amp Status HSM 0 0 DISCON NOSYNSOF RENUM SIGRSUME x0000000 rrrrbbbb E681 1 SUSPEND Put chip into suspend x x x x x x x W E682 1 WAKEUPCS Wakeup Control amp Status WU2 WU WU2POL WUPOL 0 DPEN WU2EN WUEN xx000101 bbbbrbbb E683 1 TOGCTL Toggle Control Q S R IO EP3 EP2 EP1 EPO x0000000 rrrbbbbb E684 1 USB Frame count 0 0 0 0 0 FC10 FC9 FC8 00000 685 1 USBFRAMEL USB Frame count L FC7 FC6 FC5 FC4 FC3 FC2 FC1 FCO xxxxxxxx E686 1 MICROFRAME Microframe count 0 7 0 0 0 0 0 MF2 MF1 MFO 00000 R E687 1 FNADDR USB Function address 10 FA6 FA5 FA4 FA3 FA2 FA1 E688 2 reserved ENDPOINTS E68A Endpoint 0 Byte Count 15 BC14 BC13 BC12 BC11 BC10 9 8 IRW 68 Endpoint 0 Byte Count L 7 5 BC4 BC3 BC2 BC1 BCO RW E68C reserved E68D EP1OUTBC 1 OUT 0 BC6 5 BC4 BC3 BC2 BC1 BCO IRW oun E68E reserved E68F 1 EP1INBC Endpoint 1 IN Byte Count 0 BC6 BC5 BC4 BC3 BC2 BC1 BCO Oxxxxxxx IRW E690 1 2 Endpoint 2 Byte Count 0 0 0
69. SLRD y SLRD f SLOE SLOE y SLRDy SLRD SLRDy SLRD SLOE FIFO POINTER N gt gt gt N 1 gt 1 1 gt N 2 gt 2 gt N 3 gt N 3 FIFO DATA BUS Not Driven Driven X gt N gt gt Driven N gt 1 gt N 1 gt 2 gt N 2 1 Driven Figure 32 shows the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read It shows a single read followed by a burst read m Att 0 the FIFO address is stable and the SLCS signal is asserted m Att 1 is asserted This results in the data bus being driven The data that is driven on to the bus is previous data it data that was in the FIFO from a prior read cycle m Att 2 SLRD is asserted The SLRD must meet the minimum active pulse of tappwi and minimum de active pulse width of tRppwh SLCS is used then SLCS must be asserted before BD is asserted The SLCS and SLRD signals must both be SL asserted to start a valid read condition Document 38 08032 Rev L m The data that is driven after asserting SLRD is the updated data from the FIFO This data is valid after a propagation delay of txFp from the activating edge of SLRD In Figure 32 data N is the first valid data read from the FIFO For data to appear on the data bus during the read cycle SLRD is asserted SLOE must be in an asserted state SL RD SLOE can also be tied together The same sequence of eve
70. TOPTR2 is active throughout the cycle and meets the above address valid time for which is based on the stretch value Document 38 08032 Rev L Page 40 of 62 Feedback Nr wt CYPRESS PERFORM 10 5 PORTC Strobe Feature Timings The RD and WR are present in the 100 pin version and the 128 pin package In these 100 pin and 128 pin versions an 8051 control bit can be set to pulse the RD and WR pins when the 8051 reads from or writes to PORTC This feature is enabled by setting PORTCSTB bit in CPUCS register The RD and WRi strobes are asserted for two CLKOUT cycles when PORTO is accessed The WR strobe is asserted two clock cycles after PORTC is updated and is active for two clock cycles after that as shown in Figure 15 As for read the value of PORTC three clock cycles before the assertion of RD is the value that the 8051 reads in The RD is pulsed for 2 clock cycles after 3 clock cycles from the point when the 8051 has performed a read function on PORTC CY7C68013A CY7C68014A CY7C68015A CY7C68016A The RD signal prompts the external logic to prepare the next data byte Nothing gets sampled internally on assertion of the RD signal itself it is just a prefetch type signal to get the next data byte prepared So using it with that in mind easily meets the setup time to the next read The purpose of this pulsing of RD is to allow the external peripheral to know that the 8051 is d
71. The bus SCL and SDA pins must be pulled up even if an EEPROM is not connected Otherwise this detection method does not work properly Document 38 08032 Rev L Page 4 of 62 Feedback CYPRESS PERFORM FX2LP jump instruction is encoded follows Table 3 INT2 USB Interrupts CY7C68013A CY7C68014A CY7C68015A CY7C68016A USB INTERRUPT TABLE FOR INT2 Priority INT2VEC Value Source Notes 1 00 SUDAV Setup Data Available 2 04 SOF Start of Frame or microframe 3 08 SUTOK Setup Token Received 4 0C SUSPEND USB Suspend request 5 10 USB RESET Bus reset 6 14 HISPEED Entered high speed operation 7 18 EPOACK FX2LP ACK d the CONTROL Handshake 8 1C reserved 9 20 EPO IN EPO IN ready to be loaded with data 10 24 EPO OUT EPO OUT has USB data 11 28 EP1 IN EP1 IN ready to be loaded with data 12 20 EP1 OUT EP1 OUT has USB data 13 30 EP2 IN buffer available OUT buffer has data 14 34 EP4 IN buffer available OUT buffer has data 15 38 EP6 IN buffer available OUT buffer has data 16 3C EP8 IN buffer available OUT buffer has data 17 40 IBN IN Bulk NAK any IN endpoint 18 44 reserved 19 48 EPOPING EPO OUT was Pinged and it NAK d 20 4 EP1PING EP1 OUT was Pinged and it NAK d 21 50 EP2PING EP2 OUT was Pinged and it NAK d 22 54 EP4PING EP4 OUT was Pinged and it NAK d 23 58 EP6PING EP6 OUT was Pinged and it NAK d 2
72. UT PFC11 OUT PFC10 E630 2 Endpoint 2 slave DECIS PKTSTAT OUT PFC12 OUT PFC11 10 0 PFC9 IN PKTS 2 10001000 bbbbbrbb ES Programmable Flag H OUT PFC8 E631 EP2FIFOPFLITTI Endpoint 2 slave PFC7 PFC6 PFC5 4 2 1 PFCO 00000000 RW H S Programmable Flag L E631 1 EP2FIFOPFLI T Endpoint 2 slave FIFO IN PKTS 1 IN PKTS 0 PFC5 PFC4 2 1 00000000 RW F S Programmable Flag L OUT PFC7 OUT PFC6 E632 1 Endpoint 4 slave DECIS PKTSTAT 10 PKTS 1 JIN 0 0 0 8 10001000 bbrbbrrb 5 Programmable Flag OUT PFC10 OUT PFC9 E632 1 Endpoint 4 slave DECIS PKTSTAT 0 OUT PFC10 9 0 0 8 10001000 bbrbbrrb ES Programmable Flag H E633 1 EP4FIFOPFLITTI Endpoint 4 slave 7 PFC6 PFC5 4 PFC2 PFC1 PFCO 00000000 RW H S Programmable Flag L E633 1 4 Endpoint 4 slave 1 IN PKTS 0 PFC5 PFC4 2 1 00000000 Programmable Flag L OUT PFC7 OUT PFC6 E634 1 EPeFIFOPFHITI Endpoint 6 slave DECIS PKTSTAT IN PKTS 2 IN PKTS 1 IN PKTS 0 0 PFC9 PFC8 00001000 bbbbbrbb H S Programmable Flag H OUT PFC12 OUT PFC11 OUT PFC10 E634 1 EPeFIFOPFHIT Endpoint 6 slave FIFO DECIS PKTSTAT OUT PFC12 OUT PFC11 OUT PFC10
73. ag 6 94 EP4EF Endpoint 4 Empty Flag 7 98 EP6EF Endpoint 6 Empty Flag 8 9C EP8EF Endpoint 8 Empty Flag 9 AO EP2FF Endpoint 2 Full Flag 10 A4 EP4FF Endpoint 4 Full Flag 11 A8 EP6FF Endpoint 6 Full Flag 12 AC EP8FF Endpoint 8 Full Flag 13 BO GPIFDONE GPIF Operation Complete 14 B4 GPIFWF GPIF Waveform If Autovectoring is enabled AVAEN 1 in the INTSET UP register the FX 2LP substitutes its INTAVEC byte Therefore if the high byte page of a jump table address is preloaded at location 0x0054 the automatically inserted INTAVEC byte at 0x0055 directs the jump to the correct address out of the 14 addresses within the page When the ISR occurs the FX2LP pushes the program counter onto its stack then jumps to address 0x0053 where it expects to find a jump instruction to the ISR Interrupt service routine 3 9 Reset and Wakeup 3 9 1 Heset Pin The input RESET resets the FX2LP when asserted This pin has hysteresis and is active LOW When a crystal is used with Note the CY7C680xxA the reset period must allow for the stabilization of the crystal and the PLL This reset period must be approxi mately 5 ms after VCC reaches 3 0V If the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 after VCC has reached 3 0 8 Figure 2 on page 7 shows a power on reset condition and a reset applied during operation A power on reset is defined as the time reset that is asserted while power is being a
74. ailable in the Cypress web site Part Number Part Number Package Description CY7C68013 56PVC CY7C68013A 56PVXC or CY7C68014A 56PVXC 56 SSOP CY7C68013 56PVCT CY7C68013A 56PVXCT or 7 68014 56 56 SSOP Tape and Reel CY7C68013 56LFC CY7C68013A 56LFXC or CY7C68014A 56LFXC 56 QFN CY7C68013 100AC CY7C68013A 100AXC or CY7C68014A 100AXC 100 TQFP CY7C68013 128AC 7 68013 128 or CY7C68014A 128AXC 128 TQFP Note 9 This EEPROM does not have address pins Document 38 08032 Rev L Page 13 of 62 Feedback CYPRESS PERFORM 3 20 CY7C68013A 14A and CY7C68015A 16A Differences CY7C68013A is identical to CY7C68014A in form fit and functionality CY7C68015A is identical to CY7C68016A in form fit and functionality CY7C68014A and CY7C68016A have a lower suspend current than CY7C68013A and CY7C68015A respectively and are ideal for power sensitive battery applica tions CY7C68015A and CY7C68016A are available in 56 pin QFN package only Two additional GPIO signals are available on the CY7C68015A and CY7C68016A to provide more flexibility when neither IFCLK or CLKOUT are needed in the 56 pin package USB developers wanting to convert their FX2 56 pin application to a bus powered system directly benefit from these additional signals The two GPIOs give developers the signals they need for the power control circuitry of their bus powered ap
75. and is driven LOW 63 D4 10 2 86 05 10 7 2 87 06 10 7 2 88 07 10 7 2 39 PSEN Output H Program Store Enable This active LOW signal indicates an 8051 code fetch from external memory It is active for program memory fetches from 0x4000 0xFFFF when the EA pin is LOW or from 0x0000 0xFFFF when the EA pin is HIGH Note 10 Unused inputs must not be left floating Tie either HIGH or LOW as appropriate Outputs should only be pulled up or down to ensure signals at power up and in no pins should be driven while the device is powered down standby Note also tha Document 38 08032 Rev L Page 21 of 62 Feedback TZ gt CYPRESS PERFORM CY7C68013A CY7C68014A CY7C68015A CY7C68016A Table 11 FX2LP Pin Descriptions continued 100 TQFP 56 56 SSOP QFN 56 VF BGA Name Type Default Description 28 49 42 8B BKPT RESET EA Output Input Input L N A N A Breakpoint This pin goes active HIGH when the 8051 address bus matches the BPADDRH L registers and breakpoints are enabled in the BREAKPT register BPEN 1 If the BPPULSE bit in the BREAKPT register is HIGH this signal pulses HIGH for eight 12 24 48 MHz clocks If the BPPULSE bit is LOW the signal remains HIGH until the 8051 clears the BREAK bit by writing 1 to it in the BREAKPT register Active LOW Reset Resets the entire chip See section
76. ated and stored in ECC1 The ECC for the next 256 bytes is stored in ECC2 After the second ECC is calculated the values in the ECCx registers do not change until ECCRESET is written again even if more data is subsequently passed across the interface ECCM 1 One 3 byte ECC calculated over a 512 byte block of data Write any value to ECCRESET then pass data across the GPIF or Slave FIFO interface The ECC for the first 512 bytes of data is calculated and stored in ECC1 ECC2 is unused After the ECC is calculated the values in ECC1 do not change even if more data is subsequently passed across the interface till ECCRESET is written again 3 16 USB Uploads and Downloads The core has the ability to directly edit the data contents of the internal 16 KByte RAM and of the internal 512 byte scratch pad RAM via a vendor specific command This capability is normally used when soft downloading user code and is available only to and from internal RAM only when the 8051 is held in reset The available RAM spaces are 16 KBytes from 0x0000 0x3FFF code data 512 bytes from OxE000 0xE1FF scratch pad data 18 3 17 Autopointer Access FX2LP provides two identical autopointers They are similar to the internal 8051 data pointers but with an additional feature they can optionally increment after every memory access This capability is available to and from both internal and external RAM The autopointers are available in external FX2L
77. c change 28 00054 242398 See ECN TMD Minor Change data sheet posted to the web 271169 SeeECN MON Added USB IF Test ID number Added USB 2 0 logo Added values for Isusp Icc Power Dissipation Vih x Vil x Changed VCC from 10 to 5 Changed E Pad size to 4 3 mm x 5 0 mm Changed PKTEND to FLAGS output propagation delay asynchronous interface in Table 28 from a max value of 70 ns to 115 ns G 316313 See ECN MON Removed CY7C68013A 56PVXCT part availability Added parts ideal for battery powered applications CY7C68014A CY7C68016A Provided additional timing restrictions and requirement about the use of PKETEND pin to commit a short one byte word packet subsequent to committing a packet automatically when in auto mode Added Min Vcc Ramp Up time 0 to 3 3v 338901 See ECN MON Added information about the AUTOPTR1 AUTOPTR2 address timing with regards to data memory read write timing diagram Removed TBD for Min value of Clock to FIFO Data Output Propagation Delay tx p for Slave FIFO Synchronous Read Changed Table 33 to include part CY7C68016A 56LFXC in the part listed for battery powered applications Added register GPCR2 in register summary 371097 See ECN MON Added timing for strobing RD WRi signals when using PortC strobe feature Section 10 5 J 397239 MON Removed XTALINSRC register from register summary Changed Vcc margins to 10 Added 56 pin VFBGA Pin Package Diagram Added 56 p
78. clock The default 8051 clock Note CY7C68013A CY7C68014A CY7C68015A CY7C68016A frequency is 12 MHz The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register dynamically Figure 1 Crystal Configuration C1 24MHz C2 II 712 pf 12 20 x PLL 12 pF capacitor values assumes a trace capacitance of 3 pF per side on a four layer FR4 PCA The CLKOUT pin which can be three stated and inverted using internal control bits outputs the 50 duty cycle 8051 clock at the selected 8051 clock frequency 48 MHz 24 MHz or 12 MHz 3 2 2 USARTS FX2LP contains two standard 8051 USARTs addressed via Special Function Register SFR bits The USART interface pins are available on separate IO pins and are not multiplexed with port pins UARTO and UART1 can operate using an internal clock at 230 KBaud with no more than 1 baud rate error 230 KBaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time The internal clock adjusts for the 8051 clock rate 48 MHz 24 MHz and 12 MHz such that it always presents the correct frequency for 230 KBaud operation 3 2 3 Special Function Registers Certain 8051 SFR addresses are populated to provide fast access to critical FX2LP functions These SFR additions are shown in Table 1 on page 4 Bold type indicates non standard enhanced 8051 registers T
79. d 3 14 GPIF The GPIF is a flexible 8 bit or 16 bit parallel interface driven by a user programmable finite state machine It enables the CY7C68013A 15A to perform local bus mastering and can implement a wide variety of protocols such as ATA interface printer parallel port and Utopia The GPIF has six programmable control outputs CTL nine address outputs GPIFADRx and six general purpose ready inputs RDY The data bus width can be 8 or 16 bits Each GPIF vector defines the state of the control outputs and determines what state a ready input or multiple inputs must be before proceeding The GPIF vector can be programmed to advance a FIFO to the next data value advance an address etc A sequence of the GPIF vectors make up a single waveform that is executed to perform the desired data move between the FX2LP and the external device 3 14 1 Six Control OUT Signals The 100 pin and 128 pin packages bring out all six Control Output pins CTLO CTL5 The 8051 programs the GPIF unit to define the CTL waveforms The 56 pin package brings out three of these signals CTLO CTL2 CTLx waveform edges can be programmed to make transitions as fast as once per clock 20 8 ns using a 48 MHz clock 3 14 2 Six Ready IN Signals The 100 pin and 128 pin packages bring out all six Ready inputs RDYO RDY5 The 8051 programs the GPIF unit to test the RDY pins for GPIF branching The 56 pin package brings out two of these signals RDYO 1 3 14
80. e rising edge that CY7C68013A CY7C68014A CY7C68015A CY7C68016A caused the last byte or word to be clocked into the previous auto committed packet Figure 23 shows this scenario X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode Figure 23 shows a scenario where two packets are committed The first packet gets committed automatically when the number of bytes in the FIFO reaches X value set in AUTOINLEN register and the second one byte word short packet being committed manually using PKTEND Note that there is at least one IFCLK cycle timing between the assertion of PKTEND and clocking of the last byte of the previous packet causing the packet to be committed automatically Failing to adhere to this timing results the FX2 failing to send the one byte or word short packet Figure 23 Slave FIFO Synchronous Write Sequence and Timing 0 tsFA tFAH FIFOADR gt tswR gt lwnH SLWR 1 1 1 tsFp sro le tsrp k srp k tsep DATA 4 3 2 x 1 At least one IFCLK cycle PKTEND 10 12 Slave FIFO Asynchronous Packet End Strobe Figure 24 Slave FIFO Asynchronous Packet End Strobe Timing tpEpwh
81. erted inhibits the EZ USB chip from suspending This pin has programmable polarity WAKEUP 4 36 29 22 15 SCL OD 2 Clock for the 2 interface Connect to VCC with a 2 2K resistor even if peripheral is attached 37 30 23 16 3G ISDA OD Z Data for I C compatible interface Connect to VCC with a 2 2K resistor even if no I C compatible peripheral is attached 2 1 6 55 VCC Power N A VCC Connect to 3 3V power source 26 20 18 11 18 VCC Power N A VCC Connect to 3 3V power source 43 33 24 17 7E Power N A VCC Connect to 3 3V power source 48 38 VCC Power N A Connect to 3 3V power source 64 49 34 27 8E VCC Power N A VCC Connect to 3 3V power source 68 53 VCC Power N A Connect to 3 3V power source 81 66 39 32 5C Power N A Connect to 3 3V power source 100 78 50 43 5B VCC Power N A VCC Connect to 3 3V power source 107 85 VCC Power N A Connect to 3 3V power source 3 2 7 56 4B Ground N A Ground 27 21 19 12 1H GND Ground N A Ground 49 39 GND Ground N A Ground 58 48 33 26 7D GND Ground N A Ground 65 50 35 28 8D GND Ground N A Ground 80 65 GND Ground N A Ground 93 75 48 41 Ground N A Ground 116 94 GND Ground Ground 125 99 4 53 4A Ground N A Ground 14 13 NC N A N A Connect This pin must be left open 15 14 NC N A N A Connect This pin must be left open 16 15
82. es may indicate activity to the FX2LP and initiate a wakeup m External logic asserts the WAKEUP pin m External logic asserts the PA3 WU2 pin The second wakeup pin WU2 can also be configured as a general purpose IO pin This enables a simple external R C network to be used as a periodic wakeup source WAKEUP is by default active LOW Document 38 08032 Rev L RESET 3 3V VCC OV Powered Reset 3 10 Program Data RAM 3 10 1 Size The FX2LP has 16 KBytes of internal program data RAM where PSEN RD signals are internally ORed to enable the 8051 to access it as both program and data memory No USB control registers appear in this space Two memory maps are shown in the following diagrams Figure 3 on page 8 shows the Internal Code Memory EA 0 Figure 4 on page 9 shows the External Code Memory EA 1 3 10 2 Internal Code Memory EA 0 This mode implements the internal 16 KByte block of RAM starting at 0 as combined code and data memory When external RAM or ROM is added the external read and write strobes are suppressed for memory spaces that exist inside the chip This enables the user to connect a 64 KByte memory without requiring address decodes to keep clear of internal memory spaces Only the internal 16 KBytes and scratch pad 0 5 KBytes RAM spaces have the following access m USB download m USB upload m Setup data pointer m 2 interface boot load
83. f the IFCLK the FIFO pointer is incremented The FIFO flag is also updated after a delay of tx L from the rising edge of the clock The same sequence of events are also shown for a burst write and are marked with the time indicators of T 0 through 5 Note For the burst mode SLWR and SLCS are left asserted for the entire duration of writing all the required data values In this burst write mode after the SLWR is asserted the data on the Document 38 08032 Rev L FIFO data bus is written to the FIFO on every rising edge of IFCLK The FIFO pointer is updated on each rising edge of IFCLK In Figure 31 after the four bytes are written to the FIFO SLWR is deasserted The short 4 byte packet can be committed to the host by asserting the PKTEND signal There is no specific timing requirement that should be met for asserting PKTEND signal with regards to asserting the SLWR signal PKTEND can be asserted with the last data value or thereafter The only requirement is that the setup time tspg and the hold time must be met In the scenario of Figure 31 the number of data values committed includes the last value written to the FIFO In this example both the data value and the PKTEND signal are clocked on the same rising edge of IFCLK PKTEND can also be asserted in subsequent clock cycles The FIFOADDR lines should be held constant during the PKTEND assertion Although there are no specific timing requirement for the PKTEND
84. g equation 0j P 0Ja where P Power 0Ja Junction to Ambient Temperature 0Jc 0a Ambient Temperature 70 C The Case Temperature can be calculated using the following equation where P Power Case to Ambient Temperature 0a Ambient Temperature 70 C Note 15 Do not power IO with chip power off Document 38 08032 Rev L Page 36 of 62 Feedback gt ED CYPRESS PERFOR M 9 DC Characteristics Table 14 DC Characteristics CY7C68013A CY7C68014A CY7C68015A CY7C68016A 9 1 USB Transceiver USB 2 0 compliant in full speed and high speed modes 10 AC Electrical Characteristics 10 1 USB Transceiver USB 2 0 compliant in full speed and high speed modes Note 16 Measured at 25 Document 38 08032 Rev L Parameter Description Conditions Min Typ Max Unit VCC Supply Voltage 3 00 3 3 3 60 V VCC Ramp Up 0 3 3V 200 us ViH Input HIGH Voltage 2 5 25 V Input LOW Voltage 0 5 0 8 V ViH x Crystal Input HIGH Voltage 2 5 25 V Crystal Input LOW Voltage 0 5 0 8 V l Input Leakage Current 0 lt Vin lt 10 Output Voltage HIGH lout 4 2 4 V VoL Output LOW Voltage lour 4 mA 0 4 V Output Current HIGH 4 mA loL Output Current LOW 4 mA Cin Input Pin Capacitance Except D D
85. gic When using an external IFCLK the external clock must be present before switching to the external clock with the IFCLKSRC bit Each endpoint can individually be selected for byte or word operation by an internal configuration bit and a Slave FIFO Output Enable signal SLOE enables data of the selected width External logic must ensure that the output enable signal is inactive when writing data to a slave FIFO The slave interface can also operate asynchronously where the SLRD and SLWR signals act directly as strobes rather than a clock qualifier as in synchronous mode The signals SLRD SLWR SLOE and PKTEND are gated by the signal SLCS 6 Even though these buffers are 64 bytes they are reported as 512 for USB 2 0 compliance The user must never transfer packets larger than 64 bytes to EP1 Document 38 08032 Rev L Page 11 of 62 Feedback CYPRESS PERFORM 3 13 3 GPIF and FIFO Clock Rates An 8051 register bit selects one of two frequencies for the inter nally supplied interface clock 30 MHz and 48 MHz Alternatively an externally supplied clock of 5 MHz 48 MHz feeding the IFCLK pin can be used as the interface clock IFCLK can be configured to function as an output clock when the GPIF and FIFOs are internally clocked An output enable bit in the IFCONFIG register turns this clock output off if desired Another bit within the IFCONFIG register inverts the IFCLK signal whether internally or externally source
86. he two SFR rows that end with 0 and 8 contain bit addressable registers The four IO ports A to D use the SFR addresses used in the standard 8051 for ports 0 to 3 which are not implemented in FX2LP Because of the faster and more efficient SFR addressing the FX2LP IO ports are not addressable in external RAM space using the MOVX instruction 3 3 Bus FX2LP supports the 2 bus as a master only at 100 400 KHz SCL and SDA pins have open drain outputs and hysteresis inputs These signals must be pulled up to 3 3V even if no device is connected 3 4 Buses All packages 8 bit or 16 bit FIFO bidirectional data bus multi plexed on IO ports B and D 128 pin package adds 16 bit output only 8051 address bus 8 bit bidirectional data bus 1 115 KBaud operation is also possible by programming the 8051 SMODO or SMOD bits to a 1 for UARTO UART1 or both respectively Document 38 08032 Rev L Page 3 of 62 Feedback Cypress PERFORM Table 1 Special Function Registers CY7C68013A CY7C68014A CY7C68015A CY7C68016A 3 5 USB Boot Methods During the power up sequence internal logic checks the 2 for the connection of an EEPROM whose first byte is either 0xC0 or OxC2 If found it uses the VID PID DID values in the EEPROM in place of the internally stored values 0xCO or it boot loads the
87. in Mode 0 this pin provides the output data for UART1 only when itis in sync mode In Modes 1 2 this pin is HIGH 113 91 PE5 or IO Z Multiplexed whose function is selected by the INT6 PORTECFG5 bit is a bidirectional IO port pin INT6 is the 8051 INT6 interrupt request input signal The INT6 pin is edge sensitive active HIGH 114 92 PE6 or 10 2 Multiplexed whose function is selected the T2EX PORTECFG 6 bit PEG is a bidirectional IO port pin 2 is an active HIGH input signal to the 8051 Timer2 T2EX reloads timer 2 on its falling edge T2EX is active only if the EXEN bit is set in T2CON 115 93 PE7 or IO Z Multiplexed whose function is selected by the GPIFADR8 PE7 IPORTECFG 7 bit PE7 is a bidirectional IO port pin GPIFADR8 is a GPIF address output pin 4 3 8 1 RDYO or Input N A Multiplexed pin whose function is selected by the SLRD following bits IFCONFIG 1 0 RDYO is a GPIF input signal SLRD is the input only read strobe with programmable polarity FIFOPINPOLAR 3 for the slave FIFOs connected to FD 7 0 or FD 15 0 5 4 9 2 1B RDY1 or Input N A Multiplexed pin whose function is selected by the SLWR following bits IFCONFIG 1 0 RDY1 is a GPIF input signal SLWR is the input only write strobe with programmable polarity FIFOPINPOLAR 2 for the slave FIFOs connected to FD 7 0 or FD 15 0 6 5 RDY2 Input N A RDY2 is a GPIF input signal 7
88. in VFBGA definition in pin listing Added RDK part number to the Ordering Information table Page 61 of 62 Feedback Document 38 08032 Rev L _ CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A PERFORM Document Title CY7C68013A CY7C68014A CY7C68015A CY7C68016A EZ USB FX2LP USB Microcontroller High Speed USB Peripheral Controller Document Number 38 08032 Issue Orig of REV NO Date Change Description of Change 420505 See ECN MON SLCS from figure in Section 10 10 Removed indications that SLRD can be asserted simultaneously with SLCS in Section 10 17 2 and Section 10 17 3 Added Absolute Maximum Temperature Rating for industrial packages in Section 6 Changed number of packages stated in the description in Section 4 to five Added Table 13 on Thermal Coefficients for various packages L 2064406 See ECN Changed TID number PYRS Removed TOOUT and T1OUT from CY7C68015A 16A Updated tswn Min value in Figure 20 Updated 56 lead QFN package diagram Cypress Semiconductor Corporation 2003 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are
89. iod 20 83 ns tspe PKTEND to Clock Setup Time 14 6 ns Clock to PKTEND Hold Time 0 ns txFLG Clock to FLAGS Output Propagation Delay 9 5 ns Table 27 Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLKP Parameter Description Min Max Unit tlECLK IFCLK Period 20 83 200 ns to Clock Setup Time 8 6 ns Clock to PKTEND Hold Time 2 5 ns Clock to FLAGS Output Propagation Delay 13 5 ns Document 38 08032 Rev L Page 46 of 62 Feedback There is no specific timing requirement that should met for asserting PKTEND pin to asserting SLWR PKTEND can be asserted with the last data value clocked into the FIFOs or there after The setup time tgpe and the hold time must be met Although there are no specific timing requirements for the PKTEND assertion there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte or word packet There is an additional timing requirement that needs to be met when the FIFO is configured to operate in auto mode and it is required to send two packets back to back a full packet full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register committed automatically followed by a short one byte or word packet committed manually using the PKTEND pin In this scenario the user must ensure to assert PKTEND at least one clock cycle after th
90. ive HIGH input signal for 8051 UART1 which provides data to the UART in all modes 52 42 TXD1 Output H TXDhlis an active HIGH output from 8051 UART1 which provides the output clock in sync mode and the output data in async mode 51 41 RXDO Input N A RXDOis the active HIGH RXDO input to 8051 UARTO which provides data to the UART in all modes Page 27 of 62 Feedback CYPRESS PERFORM CY7C68013A CY7C68014A CY7C68015A CY7C68016A Table 11 FX2LP Pin Descriptions continued 128 100 56 56 56 VF M TQFP TQFP SSOP BGA Name Type Default Description 50 40 TXDO Output H TXDO is the active HIGH TXDO output from 8051 UARTO which provides the output clock in sync mode and the output data in async mode 42 CS Output H CS is the active LOW chip select for external memory 41 32 WR Output H WRi is the active LOW write strobe output for external memory 40 31 RD Output H RD is the active LOW read strobe output for external memory 38 OE Output H is the active LOW output enable for external memory 33 27 21 14 2H Reserved Input N A Reserved Connect to ground 101 79 51 44 7B WAKEUP Input N A USB Wakeup If the 8051 is in suspend asserting this pin starts up the oscillator and interrupts the 8051 to enable it to exit the suspend mode Holding WAKEUP ass
91. level for one CLKOUT clock cycle when Timer1 overflows If Timer1 is operated in Mode 3 two separate timer counters T1OUT is active when the low byte timer counter overflows 110 88 or T20UT 10 2 2 Multiplexed pin whose function is selected by the 2 bit PE2 is a bidirectional IO port pin T2OUT is the active HIGH output signal from 8051 Timer2 T2OUT is active HIGH for one clock cycle when Timer Counter 2 overflows 111 89 or RXDOOUT IO Z Multiplexed whose function is selected the bit is a bidirectional IO port pin RXD0OUT is an active HIGH signal from 8051 UARTO If RXDOOUT is selected and UARTO is in Mode 0 this pin provides the output data for UARTO only when it is in sync mode Otherwise it is a 1 Document 38 08032 Rev L Page 25 of 62 Feedback CYPRESS PERFORM CY7C68013A CY7C68014A CY7C68015A CY7C68016A Table 11 FX2LP Pin Descriptions continued 100 56 56 VF TOFP TQFP Default Description 112 90 PE4 or 10 2 Multiplexed pin whose function is selected by the RXD1OUT 4 PORTECFGA bit 4 is a bidirectional IO port pin RXD10OUT is an active HIGH output from 8051 UART1 When RXD10UT is selected and UART1 is
92. nd must be near the USB connector m To control impedance maintain trace widths and trace spacing m Minimize stubs to minimize reflected signals Note 24 Source for recommendations EZ USB FX2 PCB Design Recommendations http www cypress com cfuploads support app notes FX2 PCB pdf and High Speed USB Platform Design Guidelines http www usb org developers docs hs usb pdg r1 O pdf Document 38 08032 Rev L Page 59 of 62 Feedback _ 59 CYPRESS CY7C68013A CY7C68014A CY7C68015A CY7C68016A 14 Quad Flat Package No Leads QFN Package Design Notes Electrical contact of the part to the Printed Circuit Board PCB is made by soldering the leads on the bottom surface of the package to the PCB Hence special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board Design a Copper Cu fill in the PCB as a thermal pad under the package Heat is transferred from the FX2LP through the device s metal paddle on the bottom side of the package Heat from here is conducted to the PCB at the thermal pad It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of via A via is a plated through hole in the PCB with a finished diameter of 13 mil The QFN s metal die paddle must be soldered to the PCB s thermal pad Solder mask is placed on the board top side over each via to resist solder flow into
93. not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED
94. nts is also shown for a burst read marked with T 0 through 5 Note In burst read mode during SLOE is assertion the data bus is in a driven state and outputs the previous data After SLRD is asserted the data from the FIFO is driven on the data bus SLOE must also be asserted and then the FIFO pointer is incre mented Page 52 of 62 Feedback L Ed CY7C68013A CY7C68014A CY7C68015A CY7C68016A 10 17 4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 34 Slave FIFO Asynchronous Write Sequence and Timing 2 tsFA gt tsFA FIFOADR 1 cm twrpwh twRpwh US RETE SLWR i G SLCS DOM FLAGS tsep tFDH tsFD tro 1520 N 1 E N 2 e gt G E gt PKTEND Figure 34 shows the timing relationship of the SLAVE FIFO write in an asynchronous mode The diagram shows a single write followed by a burst write of 3 bytes and committing the 4 byte short packet using PKTEND m Att 0 the FIFO address is applied insuring that it meets the setup time of tga SLCS is used it must also be asserted SLCS may be tied low in some applications m Att 1 SLWR is asserted SLWR must meet the minimum active pulse of twroyw and minimum de active pulse width of twrown If
95. one reading PORTC and the data was latched into PORTC three CLKOUT cycles before asserting the RD signal After the RD is pulsed the external logic can update the data on PORTC Following is the timing diagram of the read and write strobing function on accessing PORTC Refer to Section 10 3 and Section 10 4 for details on propagation delay of RD and WR signals Figure 15 WR Strobe Function when PORTC is Accessed by 8051 tei kour 4 IS 1 tsrBL terBH WR Figure 16 RD Strobe Function when PORTC is Accessed by 8051 P och 8051 5 DATA MUST BE HELD FOR 3 CLK CYLCES DATA CAN BE UPDATED BY EXTERNAL LOGIC tsTBH lt i gt RD 1 Document 38 08032 Rev L Page 41 of 62 Feedback Cypress PERFORM 10 6 GPIF Synchronous Signals CY7C68013A CY7C68014A CY7C68015A CY7C68016A Figure 17 GPIF Synchronous Signals Timing 201 tiFcLK gt IFCLK e tsGA GPIFADR 8 0 RDY Y tsr DATA input valid tsep gt txet DATA output N Net
96. plication without pushing them to a high pincount version of FX2LP The CY7C68015A is only available in the 56 pin QFN package Table 10 CY7C68013A 14A and CY7C68015A 16A Pin Dif ferences CY7C68013A CY7C68014A CY7C68015A CY7C68016A IFCLK PEO CLKOUT PE1 Document 38 08032 Rev L CY7C68013A CY7C68014A CY7C68015A CY7C68016A 4 Pin Assignments Figure 6 on page 15 identifies all signals for the five package types The following pages illustrate the individual pin diagrams plus a combination diagram showing which of the full set of signals are available in the 128 pin 100 pin and 56 pin packages The signals on the left edge of the 56 pin package in Figure 6 on page 15 are common to all versions in the FX2LP family with the noted differences between the CY7C68013A 14A and the CY7C68015A 16A Three modes are available in all package versions Port GPIF master and Slave FIFO These modes define the signals on the right edge of the diagram The 8051 selects the interface mode using the IFCONFIG 1 0 register bits Port mode is the power on default configuration The 100 pin package adds functionality to the 56 pin package by adding these pins m PORTO or alternate GPIFADR 7 0 address signals m PORTE or alternate GPIFADR 8 address signal and seven additional 8051 signals m Three GPIF Control signals m Four GPIF Ready signals m Nine 8051 signals two USARTs three timer inputs INT4 and
97. pplied to the circuit A powered reset is when the FX2LP powered on and operating and the RESET pin is asserted Cypress provides an application note which describes and recommends power on reset implementation For more infor mation about reset implementation for the FX2 family of products visit http www cypress com 3 If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period it must be added to the 200 us Document 38 08032 Rev L Page 6 of 62 Feedback CYPRESS PERFORM CY7C68013A CY7C68014A CY7C68015A CY7C68016A Figure 2 Reset Timing Plots RESET 3 3V 3 0 VCC u ov TRESET Power Reset Table 5 Reset Timing Values Condition Power Reset with Crystal 5 ms Power on Reset with External 200 us Clock stability time Clock Powered Reset 200 us 3 9 2 Wakeup Pins The 8051 puts itself and the rest of the chip into a power down mode by setting 0 1 This stops the oscillator and PLL When WAKEUP is asserted by external logic the oscillator restarts after the PLL stabilizes and the 8051 receives a wakeup interrupt This applies whether or not FX2LP is connected to the USB The FX2LP exits the power down USB suspend state using one of the following methods m USB bus activity if D D lines are left floating noise on these lin
98. rams Figure 35 56 lead Shrunk Small Outline Package 056 51 85062 080 S 0395 ia 0 720 0 730 SEATING PLANE Ir 0 005 9053 010 E Y 0 010 E _ I 110 m oo P BSC 0008 0 008 0 8 0008 0 016 51 85062 C Page 55 of 62 Document 38 08032 Rev L Feedback e CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A PERFORM Package Diagrams continued Figure 36 56 Lead QFN 8 x 8 mm LF56A 51 85144 TOP VIEW SIDE VIEW BOTTOM VIEW 0 0810 003 7 900 311 1 00 0 039 MAX 0 05 0 002 7 70 0 303 0 18 0 007 7 80 0 307 0 80 0 031 0 28 0 011 0 200 008 REF N PIN1 ID N 0 20 0 008 R T EP peu Mu M 0 80 0301 21 247 E 0 45 0 018 DIA SOLDERABLE cj aor L3 Y 88 5 64 EXPOSED zB ss PE 28 ge PAD c eg RO 4 2 es 01 2 m T t hn I 0240009
99. reserved AUTOPTRSET UP GPIFSGLDATLNOX Two control bits in the USBCS USB Control and Status register control the ReNumeration process DISCON and RENUM To simulate a USB disconnect the firmware sets DISCON to 1 To reconnect the firmware clears DISCON to 0 Before reconnecting the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device handles device requests over endpoint zero if RENUM 0 the Default USB Device handles device requests if RENUM 1 the firmware services the requests 3 7 Bus powered Applications The FX2LP fully supports bus powered designs by enumerating with less than 100 mA as required by the USB 2 0 specification 3 8 Interrupt System 3 8 1 INT2 Interrupt Request and Enable Registers FX2LP implements an autovector feature for INT2 and INT4 There are 27 INT2 USB vectors and 14 INT4 FIFO GPIF vectors See EZ USB Technical Reference Manual TRM for more details 3 8 2 USB Interrupt Autovectors The main USB interrupt is shared by 27 interrupt sources To save the code and processing time that is required to identify the individual USB interrupt source the FX2LP provides a second level of interrupt vectoring called Autovectoring When a USB interrupt is asserted the FX2LP pushes the program counter onto its stack then jumps to the address 0x0043 where it expects to find a jump instruction to the USB Interrupt service routine 2
100. rrrrrrb E629 1 ECCRESET ECC Reset x x x x x x x x 00000000 W E62A11 ECC1B0 ECC1 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R Note 11 Read and writes to these registers may require synchronization delay see Technical Reference Manual for Synchronization Delay Document 38 08032 Rev L Page 29 of 62 Feedback 1 253 p gt Y CYPRESS PERFORM Table 12 FX2LP Register Summary continued Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 50 Default E62B 1 Address LINE7 LINE6 LINES LINE4 LINE3 LINE2 LINE1 LINEO 00000000 R 2 1 ECC1B2 ECC1 Byte 2 Address 15 COL4 COL3 COL2 COL1 COLO LINE17 LINE16 00000000 R E62D 1 ECC2BO 2 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 E62E ECC2B1 2 Byte 1 Address LINE7 LINE6 LINES LINE4 LINE3 LINE2 LINE1 LINEO 00000000R E62F ECC2B2 2 Byte 2 Address 15 COL4 COL3 COL2 COL1 COLO 0 0 00000000 R E630 1 EP2FIFOPFHITI Endpoint 2 slave DECIS PKTSTAT IN PKTS 2 IN PKTS 1 IN PKTS 0 0 PFC9 PFC8 10001000 bbbbbrbb H S Programmable Flag H OUT PFC12 O
101. synchronous Read Parameters Parameter Description Min Max Unit RDpwi SLRD Pulse Width LOW 50 ns tRDpwh SLRD Pulse Width HIGH 50 ns SLRD to FLAGS Output Propagation Delay 70 ns SLRD to FIFO Data Output Propagation Delay 15 ns loEon SLOE Turn on to FIFO Data Valid 10 5 ns toEot SLOE Turn off to FIFO Data Hold 10 5 ns Note 23 Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz Document 38 08032 Rev L Page 44 of 62 Feedback I E lt P CYPRESS PERFORM 10 9 Slave FIFO Synchronous Write Figure 20 Slave FIFO Synchronous Write Timing 2 Table 23 Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK CY7C68013A CY7C68014A CY7C68015A CY7C68016A tiFcLK IFCLK t SLWR Towa WM DATA 7 N z 15 trpH gt FLAGS txFLG 21 Parameter Description Min Max Unit IFCLK Period 20 83 ns tswr SLWR to Clock Setup Time 10 4 ns twRH Clock to SLWR Hold Time 0 ns FIFO Data to Clock Setup Time 9 2 ns teDH Clock to FIFO Data Hold Time 0 ns Clock to FLAGS Output Propagation Time 9 5 ns Table 24 Slave FIFO Synchronous Write Parameters with Externally Sourced 22 Parameter Description Min Max Unit IF
102. the chip from suspending if WU2EN 1 89 71 44 37 6F PA4 or FIFOADRO 10 2 PAA Multiplexed pin whose function is selected by IFCONFIG 1 0 is a bidirectional IO port pin FIFOADRO is an input only address select for the slave FIFOs connected to FD 7 0 or FD 15 0 90 72 45 38 8C FIFOADR1 10 2 Multiplexed pin whose function is selected by IFCONFIG 1 0 PAS is a bidirectional IO port pin FIFOADRT is an input only address select for the slave FIFOs connected to FD 7 0 or FD 15 0 91 73 46 39 7C PA60r PKTEND 92 74 47 40 6 7 FLAGD or SLCS 10 2 10 2 7 Multiplexed whose function is selected by the IFCONFIG 1 0 bits is a bidirectional IO port pin PKTEND is an input used to commit the FIFO packet data to the endpoint and whose polarity is program mable FIFOPINPOLAR 5 Multiplexed pin whose function is selected by the IFCONFIG 1 0 and PORTACFG 7 bits 7 is a bidirectional IO port pin FLAGD is a programmable slave FIFO output status flag signal SLCS gates all other slave FIFO enable strobes Port B 44 34 25 18 3H PBOor FD 0 10 2 Multiplexed whose function is selected the following bits IFCONFIG 1 0 PBO is a bidirectional IO port pin FD 0 is the bidirectional FIFO GPIF data bus 45 35 26 19 4F PB1or FD 1 IO Z PB1
103. the via The mask on the top side also minimizes outgassing during the solder reflow process For further information on this package design refer to Appli cation Notes for Surface Mount Assembly of Amkor s MicroLead Frame MLF Packages You can find this on Amkor s website http www amkor com The application note provides detailed information about board mounting guidelines soldering flow rework process etc Figure 40 shows a cross sectional area underneath the package The cross section is of only one via The solder paste template should be designed to allow at least 50 solder coverage The thickness of the solder paste template should be 5 mil Use the No Clean type 3 solder paste for mounting the part Nitrogen purge is recommended during reflow Figure 41 is a plot of the solder mask pattern and Figure 42 displays an X Ray image of the assembly darker areas indicate solder Figure 40 Cross section of the Area Underneath the QFN Package 0 017 dia Solder Mask Cu Fill PCB Material Via hole for thermally connecting the to the circuit board ground plane 0 013 dia Cu Fill PCB Material This figure only shows the top three layers of the circuit board Top Solder PCB Dielectric and the Ground Plane Figure 41 Plot of the Solder Mask White Area HH EE E E E GN N G Figure 42 X ray Image of the Assembly Document 38 08032 Rev L Page
104. uration Endpoint 0 is the only CONTROL endpoint and endpoint 1 can be either BULK or INTERRUPT The endpoint buffers can be configured in any 1 of the 12 config urations shown in the vertical columns When operating in the full speed BULK mode only the first 64 bytes of each buffer are used For example in high speed the max packet size is 512 bytes but in full speed it is 64 bytes Even though a buffer is configured to a 512 byte buffer in full speed only the first 64 bytes are used The unused endpoint buffer space is not available for other operations An example endpoint configu ration is the EP2 1024 double buffered EP6 512 quad buffered column 8 Figure 5 Endpoint Configuration EPO IN amp OUT 64 64 64 64 64 64 64 64 64 64 64 64 IN 64 64 64 64 64 64 64 64 64 64 64 64 EP1 OUT 64 64 64 64 64 64 64 64 64 64 64 64 a fa Bul o o a fe po PS 1 d a fe s Ed Dis is 9 Document 38 08032 Rev L Page 10 of 62 Feedback 3 12 5 Default Full Speed Alternate Settings Table 6 Default Full Speed Alternate Settings 5 CY7C68013A CY7C68014A CY7C68015A CY7C68016A Alternate Setting 0 1 2 3 ep0 64 64 64 64 eplout 0 64 bulk 64 int 64 int eplin 0 64

Cypress CY7C68013A User's Manual

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