Cypress CY7C199 User's Manual
Contents
1. Storage Temperature 65 C to 150 C Output Current into Outputs 20 mA Ambient Temperature with Static Discharge Voltage gt 2001 Power 55 to 125 MIL STD 883 Method 3015 Supply Voltage to Ground Potential Latch Up Cumt 2200 mA Pin 28 to 14 200000000 0 5V to 7 0V Operating Range Range Ambient Temperature Commercial 0 to 70 5V 10 Industrial 40 C to 85 5V 10 Military 55 to 125 5V 10 Electrical Characteristics Over the Operating Range 7C199 8 7C199 10 7C199 12 7C199 15 Parameter Description Test Conditions Min Max Min Min Min Max Unit Output HIGH Vcc Min 4 0 mA 2 4 2 4 2 4 2 4 V Voltage VoL Output LOW Vec Min 28 0 mA 0 4 0 4 0 4 0 4 V Voltage Vin Input HIGH 2 2 Voc 2 2 Voc 2 2 Voc 2 2 Voc V Voltage 0 3V 0 3V 0 3V 0 3V Input LOW 05 08 0 5 08 05 08 0 5 0 8 V Voltage lix Input Load GND lt Vi lt Voc 5 5 5 5 5 5 5 5 loz Output Leakage GND lt Vo lt Vcc 5 5 5 5 5 5 5 5 LA Current Output Disabled loc Vcc Operating Voc Max 120 110 160 155 lour 0 n 85 85 100 mA MNT 1802. YPRESS CY7C199 Typical DC and AC Characteristics continued TYPICAL POWER ON CURRENT vs SUPPLY VOLTAGE TYPICAL ACCESS TIME CHANGE vs OUTPUT LOADING NORMALIZED Icc vs CYCLE TIME 8 T 8 Voc 5 0V d a 25 C N 2 N t 2 S 4 0 200 400 600 800 1000 SUPPLY VOLTAGE V CAPACITANCE pF CYCLE FREQUENCY MHz Truth Table CE WE OE Inputs Outputs Mode Power H X X High Z Deselect Power Down Standby Isp L H L Data Out Read Active lcc L L X In Write Active lec L H H High Z Deselect Output Disabled Active lec Ordering Information Speed Package Operating ns Ordering Code Name Package Type Range 8 CY7C199 8VC V21 28 Lead Molded SOJ Commercial 7 199 87 228 28 Lead Thin Small Outline Package CY7C199L 8VC V21 28 Lead Molded SOJ CY7C199L 8ZC 228 28 Lead Thin Small Outline Package 10 CY7C199 10VC V21 28 Lead Molded SOJ Commercial CY7C199 10ZC 228 28 Lead Thin Small Outline Package CY7C199L 10VC V21 28 Lead Molded SOJ CY7C199L 10ZC 728 28 Lead Thin Small Outline Package CY7C199 10VI V21 28 Lead Molded SOJ Industrial 7 199 107 228 28 Lead Thin Small Outline Package CY7C199L 10VI V21 28 Lead Molded SOJ CY7C199L 10ZI 728 28 Lead Thin Small Outline Package 12 CY7C199 12PC P21 28 Lead 300 Mil Molded DIP Commercial CY7C199 12VC V21 28 Lead Molded SOJ
3. Output Disabled loc Voc Operating Voc Max 150 150 140 140 mA Supply Current lout 0 mA 90 80 70 70 f 170 150 150 150 mA leg Automatic CE gt Com 30 30 25 25 mA Power Down ViN 2 Current or ViN lt Vi f L 5 5 5 5 mA TTL Inputs Ispo Automatic CE Max Vcc Com 10 10 10 10 mA Power Down CE gt Vcc 0 3V Currerit Vin gt 03V or L 0 05 0 05 0 05 0 05 pA CMOS Inputs Vin lt 03V f 0 Mil 15 15 15 15 mA Capacitance Parameter Description Test Conditions Max Unit Input Capacitance 25 C f 1 MHz 8 pF Output Capacitance Voc 50V 8 pF Note 4 Tested initially and after any design or process changes that may affect these parameters Document 38 05160 Rev Page 3 of 16 N CY7C199 _ a u CYPRESS C Test Loads and Waveforms A R1 4810 ALL INPUT PULSES OUTPUT OUTPUT 3 0V 90 10 30 pF H2 5pF R2 GND 2550 2550 INCLUDING INCLUDING zn AND 7 JIGAND SCOPE SCOPE C199 5 C199 6 a Equivalent to TH VENIN EQUIVALENT 1670 OUTPUTo w 1 73V Data Retention Characteristics Over the Operating Range L version only Parameter Description Conditions Min Max Unit VDR Voc for Data Retention 2 0 V Data Retention Current Vec
4. PIN 28 ain PIN 1 lt 027 018 PIN 7 4 PIN 84 Y AE 1 02 DIMENSION IN MM e c G2 MAX MIN 51 85071 F Document 38 05160 Rev Page 15 of 16 Cypress Semiconductor Corporation 2001 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress CY7C199 YPRESS lit Document Title CY7C199 32K x 8 Static RAM Document Number 38 05160 Issue Orig of REV ECN NO Date Change Description of Change is 109971 10 28 01 SZV Change from Spec number 38 00239 to 38 05160 Document 38 05160 Rev Page 16 of 16
5. Vor 2 0 n gt Voc 0 3V Com L VN gt Voc 0 3V or 10 uA teprl Chip Deselect to Data Retention Time Vin lt 0 3V 0 ns tr 5 Operation Recovery Time 200 us Data Retention Waveform 5 6 may exceed Voc 0 5V Document 38 05160 Rev DATA RETENTION MODE Vpn gt 2V Note lt 3 ns for the 12 and the 15 speeds lt 5 ns for the 20 and slower speeds C199 7 Page 4 of 16 J Switching Characteristics Over the Operating Range 71 7C199 8 7C199 10 7C199 12 7C199 15 Parameter Description Min Max Min Max Min Max Min Max Unit READ CYCLE tnc Read Cycle Time 8 10 12 15 ns tana Address to Data Valid 8 10 12 15 ns Data Hold from Address Change 3 3 3 3 ns CE LOW to Data Valid 8 10 12 15 ns ipoE OE LOW to Data Valid 4 5 5 5 7 ns tizoE OE LOW to Low 218 0 0 0 0 ns tuzoE OE HIGH to High 218 91 5 5 5 7 ns lizcE CE LOW to Low Zll 3 3 3 3 ns tuzcE CE HIGH to High 21891 4 5 5 7 ns tpu CE LOW to Power Up 0 0 0 0 ns CE HIGH to Power Down 8 10 12 15 ns WRITE 111 twc Write Cycle Time 8 10 12 15 ns tsce CE LOW to Write End 7 7 9 10 ns taw Address Set Up to Write End 7 7 9 10 ns tua Address Hold from Write End 0 0 0 0 ns tsa Address Set Up to Write Start 0 0 0 0 ns tpwe WE Pulse Width 7 7 8 9 ns tep Data Set Up to Wri
6. mA Ispi Automatic CE Vcc 5 5 30 30 mA Power Down CE gt Vin Current TTL Vin gt or Inputs lt gt Automatic Com 0 5 0 5 10 10 mA Power Down gt 0 3V Current CMOS Vin gt Veg 0 3V 0 05 0 05 0 05 0 05 Inputs or Vin lt 0 3V f 0 Mil 15 mA Shaded area contains advance information Notes 1 min 2 0V for pulse durations of less than 20 ns 2 Taxis the instant on case temperature 3 See the last page of this specification for Group A subgroup testing information Document 38 05160 Rev Page 2 of 16 CY7C199 Electrical Characteristics Over the Operating continued 7C199 20 7C199 25 7C199 35 7C199 45 Parameter Description Test Conditions Min Max Min Max Min Min Max Unit Vou Output HIGH Voc Min 4 0 mA 2 4 2 4 2 4 2 4 V Voltage VoL Output LOW Voc Min 28 0 mA 0 4 0 4 0 4 0 4 V Voltage Input HIGH 2 2 Voc 2 2 Voc 2 2 Voc 2 2 Voc V Voltage 40 3V 0 3V 0 3V 0 3V Vib Input LOW 0 5 08 0 5 0 8 0 5 0 8 0 5 0 8 V Voltage lix Input Load GND lt Vi lt Voc 5 5 5 5 5 5 5 5 uA Current loz Output Leakage GND lt Vj lt 5 5 5 5 5 5 5 5
7. 20 7 199 25 7 199 35 7 199 45 Parameter Description Min Max Min Max Min Max Min Max Unit READ CYCLE tnc Read Cycle Time 20 25 35 45 ns tan Address to Data Valid 20 25 35 45 ns Data Hold from Address 3 3 3 3 ns Change tACE CE LOW to Data Valid 20 25 35 45 ns tpoE OE LOW to Data Valid 9 10 16 16 ns tizoE OE LOW to Low 7181 0 0 0 0 ns tuzoE OE HIGH to High 2 8 91 9 11 15 15 ns lizcE CE LOW to Low Zll 3 3 3 3 ns tuzcE CE HIGH to High 219 9 9 11 15 15 ns tpu CE LOW to Power Up 0 0 0 0 ns tpp CE HIGH to Power Down 20 20 20 25 ns WRITE 10 11 twc Write Cycle Time 20 25 35 45 ns tsce CE LOW to Write End 15 18 22 22 ns taw Address Set Up to Write End 15 20 30 40 ns tua Address Hold from Write End 0 0 0 0 ns tsa Address Set Up to Write Start 0 0 0 0 ns tpwe WE Pulse Width 15 18 22 22 ns tsp Data Set Up to Write End 10 10 15 15 ns tup Data Hold from Write End 0 0 0 0 ns tuzwe WE LOW to High 2191 10 11 15 15 ns UE WE HIGH to Low 2 3 3 3 3 ns Switching Waveforms Read Cycle No 1112 13 ADDRESS DATA OUT Notes PREVIOUS DATA VALID 12 Device is continuously selected OE CE 13 WE is HIGH for read cycle Document 38 05160 Rev DATA VALID Page 6 of 16 C199 8 e CY7C199 59 E71 45 Switching Waveforms continued Read Cycle No 2 13 141 tHZOE tHZCE XR ome HIGH ll zoE IMPEDANCE HIGH
8. 7 199 127 228 28 Lead Thin Small Outline Package CY7C199L 12PC P21 28 Lead 300 Mil Molded DIP CY7C199L 12VC V21 28 Lead Molded SOJ 7 1991 127 228 28 Lead Thin Small Outline Package CY7C199 12VI V21 28 Lead Molded SOJ Industrial 7 199 122 228 28 Lead Thin Small Outline Package CY7C199L 12VI V21 28 Lead Molded SOJ CY7C199L 12ZI 728 28 Lead Thin Small Outline Package Shaded area contains advance information Contact your Cypress sales representative for availability Document 38 05160 Rev Page 9 of 16 ES CYPRESS erie 188 Ordering Information continued Speed Package Operating ns Ordering Code Name Package Type Range 15 CY7C199 15PC P21 28 Lead 300 Mil Molded DIP Commercial CY7C199 15VC V21 28 Lead Molded SOJ 7 199 157 728 28 Lead Thin Small Outline Package CY7C199L 15PC P21 28 Lead 300 Mil Molded DIP CY7C199L 15VC V21 28 Lead Molded SOJ CY7C199L 15ZC 728 28 Lead Thin Small Outline Package CY7C199 15VI V21 28 Lead Molded SOJ Industrial 7 199 157 228 28 Lead Thin Small Outline Package CY7C199 15DMB D22 28 Lead 300 Mil CerDIP Military CY7C199 15LMB L54 28 Pin Rectangular Leadless Chip Carrier CY7C199L 15DMB D22 28 Lead 300 Mil CerDIP CY7C199L 15LMB 54 28 Pin Rectangular Leadless Chip Carrier 20 CY7C199 20PC P21 28 Lead 300 Mil Molded DIP Commercial CY7C199 20VC V21 28 Lead Mold
9. IMPEDANCE DATA OUT Vcc ICC SUPPLY CURRENT ISB C199 9 tHD DATA I O DATA VALID 6199 10 Write Cycle 2 CE Controlled 15 16 twc ADDRESS CE tsa taw tHA tsp DATA I O DATA VALID C199 11 Notes 14 Address valid prior to or coincident with CE transition LOW 15 Data I O is high impedance if OE 16 If CE goes HIGH simultaneously with WE HIGH the output remains in a high impedance state Document 38 05160 Rev Page 7 of 16 lis BD CY7C199 Switching Waveforms continued Write Cycle No 3 WE Controlled OE 16 twc ADDRESS CX XX XX XS C199 12 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT vs SUPPLY VOLTAGE vs AMBIENT TEMPERATURE 5 OUTPUT VOLTAGE 1 4 m m 2 2 1 2 2 9 1 0 i lt lt 5 9 2 Zz 2 n 5 7420 4 5 5 0 5 5 6 0 0 0 1 0 2 0 3 0 4 0 SUPPLY VOLTAGE V AMBIENT TEMPERATURE C OUTPUT VOLTAGE V NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME OUTPUT SINK CURRENT vs AMBIENT TEMPERATURE vs OUTPUT VOLTAGE vs SUPPLY VOLTAGE NORMALIZED t 44 NORMALIZED t OUTPUT SINK CURRENT mA 0 8 40 45 50 55 60 SUPPLY VOLTAGE V AMBIENT TEMPERATURE C OUTPUT VOLTAGE V Document 38 05160 Rev Page 8 of 16
10. information on address pins are present on the eight data input output pins The input output pins remain in a high impedance state unless the chip is selected outputs are enabled and Write Enable WE is HIGH A die coat is used to improve alpha immunity Logic Block Diagram ROW DECODER ARRAY COLUMN DECODER Pin Configurations SOJ SOIC Top View Tap View Veo 522 WE 1 04 1 03 1 04 Os TSOP Top View not to scale 6 1 07 Selection Guide 7 199 8 7 199 10 7 199 12 7 199 15 7 199 20 7 199 25 7 199 35 7 199 45 Maximum Access Time ns 8 10 12 15 20 25 35 45 Maximum Operating 120 110 160 155 150 150 140 140 Current mA L 90 90 90 90 80 70 Maximum CMOS 0 5 0 5 10 10 10 10 10 10 Standby Current mA fT 0 05 0 05 0 05 0 05 0 05 0 05 Shaded area contains advance information Cypress Semiconductor Corporation 3901 North First Street SanJose 95134 408 943 2600 Document 38 05160 Rev Revised September 7 2001 YPRESS CY7C199 Q Maximum Ratings Above which the useful life may be impaired For user guide lines not tested DC Voltage Ap plied to Outputs in High 2 Statel l DC Input Voltagel 0 5V to Voc 4 0 5V 0 5V to Voc 0 5V
11. pu gm ng Ng hg ng ng le 28 26 0 280 i 0 030 0 080 SEATING PLANE 370 APS 0 160 0 51 85014 Page 13 of 16 Document 38 05160 Rev CY7C199 CYPRESS Package Diagrams continued T C 28 Lead 300 Mil Molded SOIC 521 PIN 1 ID DIMENSIONS IN INCHES MIN MAX SEATING PLANE 0 0091 x 0 0125 51 85026 A 28 Lead 300 Mil Molded SOJ V21 DIMENSIONS IN INCHES MIN MAX PIN 1 1D A EXTERNAL LEAD DESIGN 0020 OPTION 1 OPTION 2 7 SEATING PLANE VOODOO 0 007 0 013 0 262 0 272 51 85031 0 050 0 025 MIN Page 14 of 16 Document 38 05160 Rev h UR CYPRESS Package Diagrams continued 28 Lead Thin Small Outline Package Z28 CY7C199 RIENTATION LD MAY BE LOCATED EITHER AS SHOWN IN OPTION 1 OR OPTION 2 T m 55 13 6 d 132 EIIHN _ 00 T SEE NOTED 0 05 PIN 22 E gt PIN 21 bo Fh 1 BSC 2 SEE NOTE
12. RESS CY7C199 li ma MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups Vou 1 2 3 VoL 1 2 3 1 2 3 Vit Max 1 2 3 lx 1 2 3 loz 1 28 loc 1 2 3 lsB1 1 2 3 Ispe 1 2 3 Switching Characteristics Parameter Subgroups READ CYCLE 7 8 9 10 11 taa 7 8 9 10 11 7 8 9 10 11 7 8 9 10 11 7 8 9 10 11 WRITE CYCLE two 7 8 9 10 11 taa 7 8 9 10 11 taw 7 8 9 10 11 7 8 9 10 11 tsa 7 8 9 10 11 7 8 9 10 11 tsp 7 8 9 10 11 tup 7 8 9 10 11 Document 38 05160 Rev Page 11 of 16 CY7C199 Cypress Package Diagrams 28 Lead 300 Mil CerDIP D22 MIL STD 1835 D 15 Config A PIN 1 245 310 ERE i 005 MIN Ui AIA gi o olo glo 150 P 090 065 110 015 SEATING PLANE 0 Document 38 05160 Rev MIN DIMENSIONS IN INCHES MIN MAX BASE PLANE 290 il 390 51 80032 Page 12 of 16 CY7C199 TPHESS Package Diagrams continued 4 28 Rectangular Leadless Chip Carrier 154 MIL STD 1835 11A DIMENSIDNS IN INCHES 28 PLACES ojo O oa ojo 51 80067 or 398 28 Lead 300 Mil Molded DIP P21 DIMENSIONS IN INCHES MIN MAX 14 pu pu ph pug gs gs gs
13. SS 4 V 7 27 SS a A MT DENN A _ 7 199 CIPRESO Features High speed 10 ns Fast tpoE CMOS for optimum speed power Low active power 467 mW max 12 ns L version Low standby power 0 275 mW max L version 2V data retention L version only Easy memory expansion with CE and OE features TTL compatible inputs and outputs Automatic power down when deselected Functional Description The CY7C199 is a high performance CMOS static RAM orga nized as 32 768 words by 8 bits Easy memory expansion is 32K x 8 Static RAM provided by an active LOW Chip Enable CE and active LOW Output Enable OE and three state drivers This device has an automatic power down feature reducing the power con sumption by 8196 when deselected The CY7C199 is in the standard 300 mil wide DIP SOJ and LCC packages An active LOW Write Enable signal WE controls the writ ing reading operation of the memory When CE and WE inputs are both LOW data on the eight data input output pins l Og through 1 is written into the memory location addressed by the address present on the address pins Ag through A44 Reading the device is accomplished by selecting the device and enabling the outputs CE and OE active LOW while WE remains inactive or HIGH Under these conditions the con tents of the location addressed by the
14. ed SOJ 7 199 207 728 28 Lead Thin Small Outline Package CY7C199L 20PC P21 28 Lead 300 Mil Molded DIP CY7C199L 20VC V21 28 Lead Molded SOJ CY7C199L 20ZC 728 28 Lead Thin Small Outline Package CY7C199 20VI V21 28 Lead Molded SOJ Industrial CY7C199 20Zl Z28 28 Lead Thin Small Outline Package CY7C199 20DMB D22 28 Lead 300 Mil CerDIP Military CY7C199 20LMB L54 28 Pin Rectangular Leadless Chip Carrier CY7C199L 20DMB D22 28 Lead 300 Mil CerDIP CY7C199L 20LMB L54 28 Pin Rectangular Leadless Chip Carrier 25 CY7C199 25PC P21 28 Lead 300 Mil Molded DIP Commercial CY7C199 25SC 21 28 Lead Molded SOIC CY7C199 25VC V21 28 Lead Molded SOJ 7 199 257 728 28 Lead Thin Small Outline Package 7 1991 254 228 28 Lead Thin Small Outline Package Industrial CY7C199 25DMB D22 28 Lead 300 Mil CerDIP Military CY7C199 25LMB L54 28 Pin Rectangular Leadless Chip Carrier 35 CY7C199 35PC P21 28 Lead 300 Mil Molded DIP Commercial CY7C199 35SC 521 28 Lead Molded SOIC CY7C199 35VC V21 28 Lead Molded SOJ CY7C199 35ZC Z28 28 Lead Thin Small Outline Package CY7C199 35DMB D22 28 Lead 300 Mil CerDIP Military CY7C199 35LMB L54 28 Pin Rectangular Leadless Chip Carrier 45 CY7C199 45DMB D22 28 Lead 300 Mil CerDIP Military CY7C199 45LMB L54 28 Pin Rectangular Leadless Chip Carrier Shaded area contains advance information Contact your Cypress sales representative for availability Document 38 05160 Rev Page 10 of 16 YP
15. te End 5 5 8 9 ns tup Data Hold from Write End 0 0 0 0 ns tuzwe WE LOW to High 2191 5 6 7 7 ns 1 2 WE HIGH to Low 2181 3 3 3 3 ns Shaded area contains advance information Notes 7 Test conditions assume signal transition time of 3 ns or less for 12 and 15 speeds and 5 ns or less for 20 and slower speeds timing reference levels of 1 5V input pulse levels of 0 to 3 0V and output loading of the specified lo and 30 pF load capacitance 8 At any given temperature and voltage condition is less than tyzoe is less than tj zog and tyzwe is less than tj zwe for any given device 9 tuz0e tuzce and thzwe are specified with C 5 pF as in part b of AC Test Loads Transition is measured 500 mV from steady state voltage 10 The internal write time of the memory is defined by the overlap of CE LOW and WE LOW Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH The data input set up and hold timing should be referenced to the rising edge of the signal that terminates the write 11 The minimum write cycle time for write cycle 3 WE controlled OE LOW is the sum of tyzwe and tgp Document 38 05160 Rev Page 5 of 16 CY7C199 CYPRESS Switching Characteristics Over the Operating Rangel continued 7 199
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