Cypress CY7C185 User's Manual
Contents
1. uns aeneo E fax id 1013 CY7C185 gt CYPRESS Features High speed 15ns Fast tpoE Low active power 715 mW Low standby power 220 mW CMOS for optimum speed power Easy memory expansion with CE and OE features TTL compatible inputs and outputs Automatic power down when deselected Functional Description The CY7C185 is a high performance CMOS static RAM orga nized as 8192 words by 8 bits Easy memory expansion is 8K x 8 Static RAM provided by an active LOW chip enable CE an active HIGH chip enable 2 and active LOW output enable OE and three state drivers This device has an automatic power down feature CE or reducing the power consumption by 70 when deselected The CY7C185 is in a standard 300 mil wide DIP SOJ or SOIC package An active LOW write enable signal WE controls the writ ing reading operation of the memory When CE and WE in puts are both LOW and is HIGH data on the eight data input output pins l Og through is written into the memory location addressed by the address present on the address pins Ag through A45 Reading the device is accomplished by selecting the device and enabling the outputs CE and OE active LOW active HIGH while WE remains inactive or HIGH Under these conditions the contents of the location ad dressed by the information on address pins are present on the eight data input output pins T2. circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges
3. of 0 to 3 0V and output loading of the specified and 30 pF load capacitance and tyzwe are specified with C 5 pF as in part b of AC Test Loads Transition is measured 500 mV from steady state voltage A any given temperature and voltage condition t4zce is less than tj zog and t for any given device 8 Theinternal write time of the memory is defined by the overlap of CE LOW CEs hi and WE LOW All signals must be active to initiate a write and either signal can terminate a write by going HIGH The data input set up and hold timing should be referenced to the rising edge of the signal that terminates the write NO CY7C185 CYPRESS Switching Waveforms Read Cycle No 1 9 1 tRC ADDRESS DATA VALID PREVIOUS DATA VALID DATA OUT C185 6 Read Cycle 2111 121 IMPEDANCE DATA OUT Vcc ICC SUPPLY CURRENT ISB C185 7 Write Cycle No 1 WE Controlled 0 12 two ADDRESS SSS omaro IER 7 tHZOE m C185 8 9 Device is continuously selected OE Vi CE 10 WE is HIGH for read cycle 11 Data I O is High Z if OE Vi CE WE Vi or 12 The internal write time of the memory is defined by the he overlap of CE LOW CE HIGH and WE LOW CE and WE must be LOW and CE must be HIGH to initiate write A write can be terminated by CE or WE going HIGH or CE going LOW T
4. 7C185 25 7C185 35 Parameter Description Min Max Min Max Min Max Min Max Unit READ CYCLE tro Read Cycle Time 15 20 25 35 ns Address to Data Valid 15 20 25 35 ns Data Hold from 3 5 5 5 ns Address Change CE LOW to Data Valid 15 20 25 35 ns 1 2 HIGH to Data Valid 15 20 25 35 ns iDoE OE LOW to Data Valid 8 9 12 15 ns tLZ0E OE LOW to Low Z 3 3 3 3 ns tuzoE OE HIGH to High 2191 7 8 10 10 ns lizcE1 CE LOW to Low 217 3 5 5 5 ns ti zcE2 HIGH to Low Z 3 3 3 3 ns 2 CE HIGH to High 216 7 8 10 10 ns LOW to High Z tpu CE4 LOW to Power Up 0 0 0 0 ns CE to HIGH to Power Up CE HIGH to Power Down 15 20 20 20 ns LOW to Power Down WRITE CYCLES twc Write Cycle Time 15 20 25 35 ns CE LOW to Write End 12 15 20 20 ns lecE2 HIGH to Write End 12 15 20 20 ns tAW Address Set Up to 12 15 20 25 ns Write End tua Address Hold from 0 0 0 0 ns Write End tsa Address Set Up to 0 0 0 0 ns Write Start tpwe WE Pulse Width 12 15 15 20 ns tsp Data Set Up to Write End 8 10 10 12 ns tup Data Hold from Write End 0 0 0 0 ns tuzwE WE LOW to High 216 7 y 7 8 ns tizwE WE HIGH to Low Z 3 5 5 5 ns Notes 5 Test conditions assume signal transition time of 5 ns or less timing reference levels of 1 5V input pulse levels
5. d DIP Commercial 7 185 255 S21 28 Lead Molded SOIC CY7C185 25VC V21 28 Lead Molded SOJ CY7C185 25VI V21 28 Lead Molded SOJ Industrial 35 CY7C185 35PC P21 28 Lead 300 Mil Molded DIP Commercial CY7C185 35SC S21 28 Lead Molded SOIC CY7C185 35VC V21 28 Lead Molded SOJ CY7C185 35VI V21 28 Lead Molded SOJ Industrial Document 38 00037 K CYPRESS CY 7Ci85 Package Diagrams 28 Lead 300 Mil Molded DIP P21 14 1 da er or oT er ett rd c DIMENSIONS IN INCHES MIN MAX d 926 0 280 L 5L 0 030 0 080 SEATING PLANE 1 370 1 425 51 85014 28 Lead 300 Mil Molded SOIC S21 PIN 1 ID DIMENSIONS IN INCHES MIN MAX SEATING PLANE 51 85026 A CY7C185 gt z CYPRESS Package Diagrams continued 28 Lead 300 Mil Molded SOJ V21 DIMENSIONS IN INCHES MIN MAX PIN 1 ID DETAIL A XT 330 7 0 026 H MT 0 032 0 019 0 014 0 020 OPTION 2 OPTION 1 0 697 0 713 SEATING PLANE 0 272 51 85031 B SR e 0 025 MIN 0 050 TYP Cypress Semiconductor Corporation 1998 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than
6. he data input sel up and hold timing should be r ferenced to the rising edge of the signal that terminates the write 13 During this period the I Os are in the output state and input signals should not be applied CY7C185 4 7 CYPRESS Switching Waveforms continued Write Cycle No 2 CE Controlled 13 14l D S uem tsce2 WE tsp tup DATA I O DATA jn VALID 185 9 Write Cycle No 3 WE Controlled OE Low 2 13 14 15 two ADDRESS OK CE NNN SX ce LLM WE d AX lt lt TE OOOO He KKK 4 gt E tHZWE big The minimum write cycle time for write cycle 3 WE controlled OE LOW is the sum of tyzwe_ and tg 15 If CE goes HIGH or CE goes LOW simultaneously with WE HIGH the output remains in a high impedance state p CYPRESS CY C 85 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT vs OUTPUT VOLTAGE vs SUPPLY VOLTAGE vs AMBIENT TEMPERATURE NORMALIZED lsg NORMALIZED Igo lsg OUTPUT SOURCE CURRENT mA 0 0 1 0 2 0 3 0 4 0 SUPPLY VOLTAGE V AMBIENT TEMPERATURE C OUTPUT VOLTAGE V NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME OUTPUT SINK CURRENT vs SUPPLY VOLTAGE vs AMBIENT TEMPERATURE vs OUTPUT VOLTAGE T 140 L 120 3 3 5 a 100 N 2 a o 80 lt lt gt Z 60 4 Z z 2 40 D g
7. he input output pins remain in a high impedance state unless the chip is selected outputs are enabled and write enable WE is HIGH A die coat is used to insure alpha immunity Logic Block Diagram INPUT BUFFER V Pin Configurations DIP SOJ SOIC Top View Oo N oa 2 1 03 256 x 32 8 i C185 2 2 4 I Os l Og WE d F C185 1 Selection Guide 7C185 15 7C185 20 7 185 25 7 185 35 Maximum Access Time ns 15 20 25 35 Maximum Operating Current mA 130 110 100 100 Maximum Standby Current mA 40 15 20 15 20 15 20 15 Note 1 For military specifications see the CY7C185A datasheet Cypress Semiconductor Corporation 3901 North First Street 408 943 2600 August 12 1998 San Jose 95134 CYPRESS Maximum Ratings Output Current into Outputs 0 20 mA E Disch Voltage wire pate oti 2001V Above which the useful life may be impaired For user guide aes Kier 3015 lines not tested Boon 65 C to 150 C atch Up gt m Ambient Temperature with Operating Range Power Applied 55 C to 125 C Ambient Supply Voltage to Ground Potential 0 5V to 7 0V Range Temperature DC Voltage Applied to Outp
8. meter Description Test Conditions Min Max Min Max Unit Vou Output HIGH Voltage Voc Min 4 0 mA 2 4 2 4 V VoL Output LOW Voltage Voc Min lo 8 0 mA 0 4 0 4 V Input HIGH Voltage 2 2 Voc 2 2 Voc V 0 3V 0 3V Input LOW Voltagel 0 5 0 8 0 5 0 8 V lix Input Load Current GND lt Vi x Voc 5 5 5 5 loz Output Leakage GND lt Vi Vcc 5 5 5 5 uA Current Output Disabled los Output Short Vcc Max 300 300 Circuit Current Vout GND loc Voc Operating Voc Max 100 100 mA Supply Current lout 0 mA Automatic Voc CE gt CE2 lt Vi 20 20 mA Power Down Current Min Duty Cycle 10096 Isg2 Automatic Max Voc CE4 gt Vec 0 3V 15 15 mA Power Down Current or x 0 3V Vin 2 Vcc 0 3V or lt 0 3 Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 2 1 MHz 7 pF Cour Output Capacitance Voc 5 0V 7 pF Note 4 Tested initially and after any design or process changes that may affect these parameters AC Test Loads and Waveforms ALL INPUT PULSES R1 4810 R1 4810 5V TPUT TPUT i iin 3 0V 30 pF R2 5pF R2 INCLUDING 290 INCLUDING 22 GND JIG AND JIGAND lt 5ns gt SCOPE SCOPE b Equivalent to 1670 TH VENIN EQUIVALENT OUTPUT o wo 1 73V C185 5 CY7C185 Switching Characteristics Over the Operating Rangel 7C185 15 7C185 20
9. t 20 0 8 0 4 0 45 5 0 55 6 0 0 0 1 0 2 0 30 4 0 SUPPLY VOLTAGE V AMBIENT TEMPERATURE C QUTRUT VOLTAGE V TYPICAL POWER ON CURRENT TYPICAL ACCESS TIME CHANGE vs SUPPLY VOLTAGE vs OUTPUT LOADING NORMALIZED Icc vs CYCLE TIME ES a a LLI Lu N N lt lt gt gt jam 2 2 0 00 10 20 30 40 5 0 0 200 400 600 800 1000 SUPPLY VOLTAGE V CAPACITANCE pF CYCLE FREQUENCY MHz CY7C185 YPRESS Truth Table CE WE OE Input Output Mode H X X X HighZ Deselect Power Down X L X X HighZ Deselect Power Down L H H L Data Out Read L H L X Data In Write L H H H High 2 Deselect Address Designators Address Address Pin Name Function Number A4 x3 2 A5 X4 3 A6 X5 4 A7 X6 5 A8 X7 6 A9 Y1 7 A10 Y4 8 A11 Y3 9 A12 YO 10 AO Y2 21 Al X0 23 A2 X1 24 A3 2 25 Ordering Information Speed Package Operating ns Ordering Code Name Package Type Range 15 CY7C185 15PC P21 28 Lead 300 Mil Molded DIP Commercial CY7C185 15SC S21 28 Lead Molded SOIC CY7C185 15VC V21 28 Lead Molded SOJ CY7C185 15VI V21 28 Lead Molded SOJ Industrial 20 CY7C185 20PC P21 28 Lead 300 Mil Molded DIP Commercial 7 185 205 521 28 Lead Molded SOIC CY7C185 20VC V21 28 Lead Molded SOJ CY7C185 20VI V21 28 Lead Molded SOJ Industrial 25 CY7C185 25PC P21 28 Lead 300 Mil Molde
10. uts Commercial 0 C to 70 C 5V 10 in High Z State CREER 0 5V to 7 0 industrial 40 C to 285 C BV 10 DC Input Voltage Tis E A 0 5V to 7 0V Electrical Characteristics Over the Operating Range 7C185 15 7 185 20 Parameter Description Test Conditions Min Max Min Max Unit Vou Output HIGH Voltage Voc Min 4 0 mA 2 4 2 4 V VoL Output LOW Voltage Voc Min lo 8 0 mA 0 4 0 4 V Input HIGH Voltage 2 2 Voc 22 Voct V 0 3V 0 3V Input LOW Voltagel 0 5 08 05 08 V lix Input Load Current GND lt Vi lt Vcc 5 5 5 5 uA loz Output Leakage GND lt VI lt Vcc 5 5 5 5 uA Current Output Disabled los Output Short Vcc Max 300 300 mA Circuit Current Vour GND loc Voc Operating Voc Max 130 110 mA Supply Current lout 0 mA Voc CE 2 Vin or lt ViL 40 20 mA Power Down Current Min Duty Cycle 100 Isg2 Automatic Max Vcc CE4 gt Vcc 0 3V 15 15 mA Power Down Current or x 0 3V Vin 2 Vcc 0 3V or Vin 0 3V Notes 2 Minimum voltage is equal to 3 0V for pulse durations less than 30 ns 3 Not more than 1 output should be shorted at one time Duration of the short circuit should not exceed 30 seconds CYPRESS CITES Electrical Characteristics Over the Operating Range continued 7 185 25 7 185 35 Para
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